1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* Copyright (c) 2025 Intel Corporation. */ 3 #ifndef ADF_GEN6_TL_H 4 #define ADF_GEN6_TL_H 5 6 #include <linux/types.h> 7 8 struct adf_tl_hw_data; 9 10 /* Computation constants. */ 11 #define ADF_GEN6_CPP_NS_PER_CYCLE 2 12 #define ADF_GEN6_TL_BW_HW_UNITS_TO_BYTES 64 13 14 /* Maximum aggregation time. Value is in milliseconds. */ 15 #define ADF_GEN6_TL_MAX_AGGR_TIME_MS 4000 16 /* Number of buffers to store historic values. */ 17 #define ADF_GEN6_TL_NUM_HIST_BUFFS \ 18 (ADF_GEN6_TL_MAX_AGGR_TIME_MS / ADF_TL_DATA_WR_INTERVAL_MS) 19 20 /* Max number of HW resources of one type */ 21 #define ADF_GEN6_TL_MAX_SLICES_PER_TYPE 32 22 #define MAX_ATH_SL_COUNT 7 23 #define MAX_CNV_SL_COUNT 2 24 #define MAX_DCPRZ_SL_COUNT 2 25 #define MAX_PKE_SL_COUNT 32 26 #define MAX_UCS_SL_COUNT 4 27 #define MAX_WAT_SL_COUNT 5 28 #define MAX_WCP_SL_COUNT 5 29 30 #define MAX_ATH_CMDQ_COUNT 14 31 #define MAX_CNV_CMDQ_COUNT 6 32 #define MAX_DCPRZ_CMDQ_COUNT 6 33 #define MAX_PKE_CMDQ_COUNT 32 34 #define MAX_UCS_CMDQ_COUNT 12 35 #define MAX_WAT_CMDQ_COUNT 35 36 #define MAX_WCP_CMDQ_COUNT 35 37 38 /* Max number of simultaneously monitored ring pairs. */ 39 #define ADF_GEN6_TL_MAX_RP_NUM 4 40 41 /** 42 * struct adf_gen6_tl_slice_data_regs - HW slice data as populated by FW. 43 * @reg_tm_slice_exec_cnt: Slice execution count. 44 * @reg_tm_slice_util: Slice utilization. 45 */ 46 struct adf_gen6_tl_slice_data_regs { 47 __u32 reg_tm_slice_exec_cnt; 48 __u32 reg_tm_slice_util; 49 }; 50 51 #define ADF_GEN6_TL_SLICE_REG_SZ sizeof(struct adf_gen6_tl_slice_data_regs) 52 53 /** 54 * struct adf_gen6_tl_cmdq_data_regs - HW CMDQ data as populated by FW. 55 * @reg_tm_cmdq_wait_cnt: CMDQ wait count. 56 * @reg_tm_cmdq_exec_cnt: CMDQ execution count. 57 * @reg_tm_cmdq_drain_cnt: CMDQ drain count. 58 */ 59 struct adf_gen6_tl_cmdq_data_regs { 60 __u32 reg_tm_cmdq_wait_cnt; 61 __u32 reg_tm_cmdq_exec_cnt; 62 __u32 reg_tm_cmdq_drain_cnt; 63 __u32 reserved; 64 }; 65 66 #define ADF_GEN6_TL_CMDQ_REG_SZ sizeof(struct adf_gen6_tl_cmdq_data_regs) 67 68 /** 69 * struct adf_gen6_tl_device_data_regs - This structure stores device telemetry 70 * counter values as are being populated periodically by device. 71 * @reg_tl_rd_lat_acc: read latency accumulator 72 * @reg_tl_gp_lat_acc: "get to put" latency accumulator 73 * @reg_tl_at_page_req_lat_acc: AT/DevTLB page request latency accumulator 74 * @reg_tl_at_trans_lat_acc: DevTLB transaction latency accumulator 75 * @reg_tl_re_acc: accumulated ring empty time 76 * @reg_tl_prt_trans_cnt: PCIe partial transactions 77 * @reg_tl_rd_lat_max: maximum logged read latency 78 * @reg_tl_rd_cmpl_cnt: read requests completed count 79 * @reg_tl_gp_lat_max: maximum logged get to put latency 80 * @reg_tl_ae_put_cnt: Accelerator Engine put counts across all rings 81 * @reg_tl_bw_in: PCIe write bandwidth 82 * @reg_tl_bw_out: PCIe read bandwidth 83 * @reg_tl_at_page_req_cnt: DevTLB page requests count 84 * @reg_tl_at_trans_lat_cnt: DevTLB transaction latency samples count 85 * @reg_tl_at_max_utlb_used: maximum uTLB used 86 * @reg_tl_re_cnt: ring empty time samples count 87 * @reserved: reserved 88 * @ath_slices: array of Authentication slices utilization registers 89 * @cnv_slices: array of Compression slices utilization registers 90 * @dcprz_slices: array of Decompression slices utilization registers 91 * @pke_slices: array of PKE slices utilization registers 92 * @ucs_slices: array of UCS slices utilization registers 93 * @wat_slices: array of Wireless Authentication slices utilization registers 94 * @wcp_slices: array of Wireless Cipher slices utilization registers 95 * @ath_cmdq: array of Authentication cmdq telemetry registers 96 * @cnv_cmdq: array of Compression cmdq telemetry registers 97 * @dcprz_cmdq: array of Decomopression cmdq telemetry registers 98 * @pke_cmdq: array of PKE cmdq telemetry registers 99 * @ucs_cmdq: array of UCS cmdq telemetry registers 100 * @wat_cmdq: array of Wireless Authentication cmdq telemetry registers 101 * @wcp_cmdq: array of Wireless Cipher cmdq telemetry registers 102 */ 103 struct adf_gen6_tl_device_data_regs { 104 __u64 reg_tl_rd_lat_acc; 105 __u64 reg_tl_gp_lat_acc; 106 __u64 reg_tl_at_page_req_lat_acc; 107 __u64 reg_tl_at_trans_lat_acc; 108 __u64 reg_tl_re_acc; 109 __u32 reg_tl_prt_trans_cnt; 110 __u32 reg_tl_rd_lat_max; 111 __u32 reg_tl_rd_cmpl_cnt; 112 __u32 reg_tl_gp_lat_max; 113 __u32 reg_tl_ae_put_cnt; 114 __u32 reg_tl_bw_in; 115 __u32 reg_tl_bw_out; 116 __u32 reg_tl_at_page_req_cnt; 117 __u32 reg_tl_at_trans_lat_cnt; 118 __u32 reg_tl_at_max_utlb_used; 119 __u32 reg_tl_re_cnt; 120 __u32 reserved; 121 struct adf_gen6_tl_slice_data_regs ath_slices[MAX_ATH_SL_COUNT]; 122 struct adf_gen6_tl_slice_data_regs cnv_slices[MAX_CNV_SL_COUNT]; 123 struct adf_gen6_tl_slice_data_regs dcprz_slices[MAX_DCPRZ_SL_COUNT]; 124 struct adf_gen6_tl_slice_data_regs pke_slices[MAX_PKE_SL_COUNT]; 125 struct adf_gen6_tl_slice_data_regs ucs_slices[MAX_UCS_SL_COUNT]; 126 struct adf_gen6_tl_slice_data_regs wat_slices[MAX_WAT_SL_COUNT]; 127 struct adf_gen6_tl_slice_data_regs wcp_slices[MAX_WCP_SL_COUNT]; 128 struct adf_gen6_tl_cmdq_data_regs ath_cmdq[MAX_ATH_CMDQ_COUNT]; 129 struct adf_gen6_tl_cmdq_data_regs cnv_cmdq[MAX_CNV_CMDQ_COUNT]; 130 struct adf_gen6_tl_cmdq_data_regs dcprz_cmdq[MAX_DCPRZ_CMDQ_COUNT]; 131 struct adf_gen6_tl_cmdq_data_regs pke_cmdq[MAX_PKE_CMDQ_COUNT]; 132 struct adf_gen6_tl_cmdq_data_regs ucs_cmdq[MAX_UCS_CMDQ_COUNT]; 133 struct adf_gen6_tl_cmdq_data_regs wat_cmdq[MAX_WAT_CMDQ_COUNT]; 134 struct adf_gen6_tl_cmdq_data_regs wcp_cmdq[MAX_WCP_CMDQ_COUNT]; 135 }; 136 137 /** 138 * struct adf_gen6_tl_ring_pair_data_regs - This structure stores ring pair 139 * telemetry counter values as they are being populated periodically by device. 140 * @reg_tl_gp_lat_acc: get-put latency accumulator 141 * @reg_tl_re_acc: accumulated ring empty time 142 * @reg_tl_pci_trans_cnt: PCIe partial transactions 143 * @reg_tl_ae_put_cnt: Accelerator Engine put counts across all rings 144 * @reg_tl_bw_in: PCIe write bandwidth 145 * @reg_tl_bw_out: PCIe read bandwidth 146 * @reg_tl_at_glob_devtlb_hit: Message descriptor DevTLB hit rate 147 * @reg_tl_at_glob_devtlb_miss: Message descriptor DevTLB miss rate 148 * @reg_tl_at_payld_devtlb_hit: Payload DevTLB hit rate 149 * @reg_tl_at_payld_devtlb_miss: Payload DevTLB miss rate 150 * @reg_tl_re_cnt: ring empty time samples count 151 * @reserved1: reserved 152 */ 153 struct adf_gen6_tl_ring_pair_data_regs { 154 __u64 reg_tl_gp_lat_acc; 155 __u64 reg_tl_re_acc; 156 __u32 reg_tl_prt_trans_cnt; 157 __u32 reg_tl_ae_put_cnt; 158 __u32 reg_tl_bw_in; 159 __u32 reg_tl_bw_out; 160 __u32 reg_tl_at_glob_devtlb_hit; 161 __u32 reg_tl_at_glob_devtlb_miss; 162 __u32 reg_tl_at_payld_devtlb_hit; 163 __u32 reg_tl_at_payld_devtlb_miss; 164 __u32 reg_tl_re_cnt; 165 __u32 reserved1; 166 }; 167 168 #define ADF_GEN6_TL_RP_REG_SZ sizeof(struct adf_gen6_tl_ring_pair_data_regs) 169 170 /** 171 * struct adf_gen6_tl_layout - This structure represents the entire telemetry 172 * counters data: Device + 4 Ring Pairs as they are being populated periodically 173 * by device. 174 * @tl_device_data_regs: structure of device telemetry registers 175 * @tl_ring_pairs_data_regs: array of ring pairs telemetry registers 176 * @reg_tl_msg_cnt: telemetry message counter 177 * @reserved: reserved 178 */ 179 struct adf_gen6_tl_layout { 180 struct adf_gen6_tl_device_data_regs tl_device_data_regs; 181 struct adf_gen6_tl_ring_pair_data_regs 182 tl_ring_pairs_data_regs[ADF_GEN6_TL_MAX_RP_NUM]; 183 __u32 reg_tl_msg_cnt; 184 __u32 reserved; 185 }; 186 187 #define ADF_GEN6_TL_LAYOUT_SZ sizeof(struct adf_gen6_tl_layout) 188 #define ADF_GEN6_TL_MSG_CNT_OFF \ 189 offsetof(struct adf_gen6_tl_layout, reg_tl_msg_cnt) 190 191 #ifdef CONFIG_DEBUG_FS 192 void adf_gen6_init_tl_data(struct adf_tl_hw_data *tl_data); 193 #else 194 static inline void adf_gen6_init_tl_data(struct adf_tl_hw_data *tl_data) 195 { 196 } 197 #endif /* CONFIG_DEBUG_FS */ 198 #endif /* ADF_GEN6_TL_H */ 199