1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* Copyright(c) 2023 Intel Corporation */ 3 #ifndef ADF_420XX_HW_DATA_H_ 4 #define ADF_420XX_HW_DATA_H_ 5 6 #include <adf_accel_devices.h> 7 8 #define ADF_420XX_MAX_ACCELENGINES 17 9 10 #define ADF_420XX_ACCELENGINES_MASK 0x1FFFF 11 #define ADF_420XX_ADMIN_AE_MASK 0x10000 12 13 #define ADF_420XX_HICPPAGENTCMDPARERRLOG_MASK (0xFF) 14 #define ADF_420XX_PARITYERRORMASK_ATH_CPH_MASK (0xFF00FF) 15 #define ADF_420XX_PARITYERRORMASK_CPR_XLT_MASK (0x10001) 16 #define ADF_420XX_PARITYERRORMASK_DCPR_UCS_MASK (0xF0007) 17 #define ADF_420XX_PARITYERRORMASK_PKE_MASK (0xFFF) 18 #define ADF_420XX_PARITYERRORMASK_WAT_WCP_MASK (0x3FF03FF) 19 20 /* 21 * SSMFEATREN bit mask 22 * BIT(4) - enables parity detection on CPP 23 * BIT(12) - enables the logging of push/pull data errors 24 * in pperr register 25 * BIT(16) - BIT(27) - enable parity detection on SPPs 26 */ 27 #define ADF_420XX_SSMFEATREN_MASK \ 28 (BIT(4) | BIT(12) | BIT(16) | BIT(17) | BIT(18) | BIT(19) | BIT(20) | \ 29 BIT(21) | BIT(22) | BIT(23) | BIT(24) | BIT(25) | BIT(26) | BIT(27)) 30 31 /* Firmware Binaries */ 32 #define ADF_420XX_FW "qat_420xx.bin" 33 #define ADF_420XX_MMP "qat_420xx_mmp.bin" 34 #define ADF_420XX_SYM_OBJ "qat_420xx_sym.bin" 35 #define ADF_420XX_DC_OBJ "qat_420xx_dc.bin" 36 #define ADF_420XX_ASYM_OBJ "qat_420xx_asym.bin" 37 #define ADF_420XX_ADMIN_OBJ "qat_420xx_admin.bin" 38 39 /* RL constants */ 40 #define ADF_420XX_RL_PCIE_SCALE_FACTOR_DIV 100 41 #define ADF_420XX_RL_PCIE_SCALE_FACTOR_MUL 102 42 #define ADF_420XX_RL_DCPR_CORRECTION 1 43 #define ADF_420XX_RL_SCANS_PER_SEC 954 44 #define ADF_420XX_RL_MAX_TP_ASYM 173750UL 45 #define ADF_420XX_RL_MAX_TP_SYM 95000UL 46 #define ADF_420XX_RL_MAX_TP_DC 40000UL 47 #define ADF_420XX_RL_SLICE_REF 1000UL 48 49 /* Clocks frequency */ 50 #define ADF_420XX_AE_FREQ (1000 * HZ_PER_MHZ) 51 52 void adf_init_hw_data_420xx(struct adf_hw_device_data *hw_data, u32 dev_id); 53 void adf_clean_hw_data_420xx(struct adf_hw_device_data *hw_data); 54 55 #endif 56