1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * comedi/drivers/cb_pcidas64.c 4 * This is a driver for the ComputerBoards/MeasurementComputing PCI-DAS 5 * 64xx, 60xx, and 4020 cards. 6 * 7 * Author: Frank Mori Hess <fmhess@users.sourceforge.net> 8 * Copyright (C) 2001, 2002 Frank Mori Hess 9 * 10 * Thanks also go to the following people: 11 * 12 * Steve Rosenbluth, for providing the source code for 13 * his pci-das6402 driver, and source code for working QNX pci-6402 14 * drivers by Greg Laird and Mariusz Bogacz. None of the code was 15 * used directly here, but it was useful as an additional source of 16 * documentation on how to program the boards. 17 * 18 * John Sims, for much testing and feedback on pcidas-4020 support. 19 * 20 * COMEDI - Linux Control and Measurement Device Interface 21 * Copyright (C) 1997-8 David A. Schleef <ds@schleef.org> 22 */ 23 24 /* 25 * Driver: cb_pcidas64 26 * Description: MeasurementComputing PCI-DAS64xx, 60XX, and 4020 series 27 * with the PLX 9080 PCI controller 28 * Author: Frank Mori Hess <fmhess@users.sourceforge.net> 29 * Status: works 30 * Updated: Fri, 02 Nov 2012 18:58:55 +0000 31 * Devices: [Measurement Computing] PCI-DAS6402/16 (cb_pcidas64), 32 * PCI-DAS6402/12, PCI-DAS64/M1/16, PCI-DAS64/M2/16, 33 * PCI-DAS64/M3/16, PCI-DAS6402/16/JR, PCI-DAS64/M1/16/JR, 34 * PCI-DAS64/M2/16/JR, PCI-DAS64/M3/16/JR, PCI-DAS64/M1/14, 35 * PCI-DAS64/M2/14, PCI-DAS64/M3/14, PCI-DAS6013, PCI-DAS6014, 36 * PCI-DAS6023, PCI-DAS6025, PCI-DAS6030, 37 * PCI-DAS6031, PCI-DAS6032, PCI-DAS6033, PCI-DAS6034, 38 * PCI-DAS6035, PCI-DAS6036, PCI-DAS6040, PCI-DAS6052, 39 * PCI-DAS6070, PCI-DAS6071, PCI-DAS4020/12 40 * 41 * Configuration options: 42 * None. 43 * 44 * Manual attachment of PCI cards with the comedi_config utility is not 45 * supported by this driver; they are attached automatically. 46 * 47 * These boards may be autocalibrated with the comedi_calibrate utility. 48 * 49 * To select the bnc trigger input on the 4020 (instead of the dio input), 50 * specify a nonzero channel in the chanspec. If you wish to use an external 51 * master clock on the 4020, you may do so by setting the scan_begin_src 52 * to TRIG_OTHER, and using an INSN_CONFIG_TIMER_1 configuration insn 53 * to configure the divisor to use for the external clock. 54 * 55 * Some devices are not identified because the PCI device IDs are not yet 56 * known. If you have such a board, please let the maintainers know. 57 */ 58 59 /* 60 * TODO: 61 * make it return error if user attempts an ai command that uses the 62 * external queue, and an ao command simultaneously user counter subdevice 63 * there are a number of boards this driver will support when they are 64 * fully released, but does not yet since the pci device id numbers 65 * are not yet available. 66 * 67 * support prescaled 100khz clock for slow pacing (not available on 6000 68 * series?) 69 * 70 * make ao fifo size adjustable like ai fifo 71 */ 72 73 #include <linux/module.h> 74 #include <linux/delay.h> 75 #include <linux/interrupt.h> 76 #include <linux/comedi/comedi_pci.h> 77 #include <linux/comedi/comedi_8255.h> 78 79 #include "plx9080.h" 80 81 #define TIMER_BASE 25 /* 40MHz master clock */ 82 /* 83 * 100kHz 'prescaled' clock for slow acquisition, 84 * maybe I'll support this someday 85 */ 86 #define PRESCALED_TIMER_BASE 10000 87 #define DMA_BUFFER_SIZE 0x1000 88 #define DAC_FIFO_SIZE 0x2000 89 90 /* maximum value that can be loaded into board's 24-bit counters */ 91 static const int max_counter_value = 0xffffff; 92 93 /* PCI-DAS64xxx base addresses */ 94 95 /* devpriv->main_iobase registers */ 96 enum write_only_registers { 97 INTR_ENABLE_REG = 0x0, /* interrupt enable register */ 98 HW_CONFIG_REG = 0x2, /* hardware config register */ 99 DAQ_SYNC_REG = 0xc, 100 DAQ_ATRIG_LOW_4020_REG = 0xc, 101 ADC_CONTROL0_REG = 0x10, /* adc control register 0 */ 102 ADC_CONTROL1_REG = 0x12, /* adc control register 1 */ 103 CALIBRATION_REG = 0x14, 104 /* lower 16 bits of adc sample interval counter */ 105 ADC_SAMPLE_INTERVAL_LOWER_REG = 0x16, 106 /* upper 8 bits of adc sample interval counter */ 107 ADC_SAMPLE_INTERVAL_UPPER_REG = 0x18, 108 /* lower 16 bits of delay interval counter */ 109 ADC_DELAY_INTERVAL_LOWER_REG = 0x1a, 110 /* upper 8 bits of delay interval counter */ 111 ADC_DELAY_INTERVAL_UPPER_REG = 0x1c, 112 /* lower 16 bits of hardware conversion/scan counter */ 113 ADC_COUNT_LOWER_REG = 0x1e, 114 /* upper 8 bits of hardware conversion/scan counter */ 115 ADC_COUNT_UPPER_REG = 0x20, 116 ADC_START_REG = 0x22, /* software trigger to start acquisition */ 117 ADC_CONVERT_REG = 0x24, /* initiates single conversion */ 118 ADC_QUEUE_CLEAR_REG = 0x26, /* clears adc queue */ 119 ADC_QUEUE_LOAD_REG = 0x28, /* loads adc queue */ 120 ADC_BUFFER_CLEAR_REG = 0x2a, 121 /* high channel for internal queue, use adc_chan_bits() inline above */ 122 ADC_QUEUE_HIGH_REG = 0x2c, 123 DAC_CONTROL0_REG = 0x50, /* dac control register 0 */ 124 DAC_CONTROL1_REG = 0x52, /* dac control register 0 */ 125 /* lower 16 bits of dac sample interval counter */ 126 DAC_SAMPLE_INTERVAL_LOWER_REG = 0x54, 127 /* upper 8 bits of dac sample interval counter */ 128 DAC_SAMPLE_INTERVAL_UPPER_REG = 0x56, 129 DAC_SELECT_REG = 0x60, 130 DAC_START_REG = 0x64, 131 DAC_BUFFER_CLEAR_REG = 0x66, /* clear dac buffer */ 132 }; 133 134 static inline unsigned int dac_convert_reg(unsigned int channel) 135 { 136 return 0x70 + (2 * (channel & 0x1)); 137 } 138 139 static inline unsigned int dac_lsb_4020_reg(unsigned int channel) 140 { 141 return 0x70 + (4 * (channel & 0x1)); 142 } 143 144 static inline unsigned int dac_msb_4020_reg(unsigned int channel) 145 { 146 return 0x72 + (4 * (channel & 0x1)); 147 } 148 149 enum read_only_registers { 150 /* 151 * hardware status register, 152 * reading this apparently clears pending interrupts as well 153 */ 154 HW_STATUS_REG = 0x0, 155 PIPE1_READ_REG = 0x4, 156 ADC_READ_PNTR_REG = 0x8, 157 LOWER_XFER_REG = 0x10, 158 ADC_WRITE_PNTR_REG = 0xc, 159 PREPOST_REG = 0x14, 160 }; 161 162 enum read_write_registers { 163 I8255_4020_REG = 0x48, /* 8255 offset, for 4020 only */ 164 /* external channel/gain queue, uses same bits as ADC_QUEUE_LOAD_REG */ 165 ADC_QUEUE_FIFO_REG = 0x100, 166 ADC_FIFO_REG = 0x200, /* adc data fifo */ 167 /* dac data fifo, has weird interactions with external channel queue */ 168 DAC_FIFO_REG = 0x300, 169 }; 170 171 /* dev->mmio registers */ 172 enum dio_counter_registers { 173 DIO_8255_OFFSET = 0x0, 174 DO_REG = 0x20, 175 DI_REG = 0x28, 176 DIO_DIRECTION_60XX_REG = 0x40, 177 DIO_DATA_60XX_REG = 0x48, 178 }; 179 180 /* bit definitions for write-only registers */ 181 182 enum intr_enable_contents { 183 ADC_INTR_SRC_MASK = 0x3, /* adc interrupt source mask */ 184 ADC_INTR_QFULL_BITS = 0x0, /* interrupt fifo quarter full */ 185 ADC_INTR_EOC_BITS = 0x1, /* interrupt end of conversion */ 186 ADC_INTR_EOSCAN_BITS = 0x2, /* interrupt end of scan */ 187 ADC_INTR_EOSEQ_BITS = 0x3, /* interrupt end of sequence mask */ 188 EN_ADC_INTR_SRC_BIT = 0x4, /* enable adc interrupt source */ 189 EN_ADC_DONE_INTR_BIT = 0x8, /* enable adc acquisition done intr */ 190 DAC_INTR_SRC_MASK = 0x30, 191 DAC_INTR_QEMPTY_BITS = 0x0, 192 DAC_INTR_HIGH_CHAN_BITS = 0x10, 193 EN_DAC_INTR_SRC_BIT = 0x40, /* enable dac interrupt source */ 194 EN_DAC_DONE_INTR_BIT = 0x80, 195 EN_ADC_ACTIVE_INTR_BIT = 0x200, /* enable adc active interrupt */ 196 EN_ADC_STOP_INTR_BIT = 0x400, /* enable adc stop trigger interrupt */ 197 EN_DAC_ACTIVE_INTR_BIT = 0x800, /* enable dac active interrupt */ 198 EN_DAC_UNDERRUN_BIT = 0x4000, /* enable dac underrun status bit */ 199 EN_ADC_OVERRUN_BIT = 0x8000, /* enable adc overrun status bit */ 200 }; 201 202 enum hw_config_contents { 203 MASTER_CLOCK_4020_MASK = 0x3, /* master clock source mask for 4020 */ 204 INTERNAL_CLOCK_4020_BITS = 0x1, /* use 40 MHz internal master clock */ 205 BNC_CLOCK_4020_BITS = 0x2, /* use BNC input for master clock */ 206 EXT_CLOCK_4020_BITS = 0x3, /* use dio input for master clock */ 207 EXT_QUEUE_BIT = 0x200, /* use external channel/gain queue */ 208 /* use 225 nanosec strobe when loading dac instead of 50 nanosec */ 209 SLOW_DAC_BIT = 0x400, 210 /* 211 * bit with unknown function yet given as default value in pci-das64 212 * manual 213 */ 214 HW_CONFIG_DUMMY_BITS = 0x2000, 215 /* bit selects channels 1/0 for analog input/output, otherwise 0/1 */ 216 DMA_CH_SELECT_BIT = 0x8000, 217 FIFO_SIZE_REG = 0x4, /* allows adjustment of fifo sizes */ 218 DAC_FIFO_SIZE_MASK = 0xff00, /* bits that set dac fifo size */ 219 DAC_FIFO_BITS = 0xf800, /* 8k sample ao fifo */ 220 }; 221 222 enum daq_atrig_low_4020_contents { 223 /* use trig/ext clk bnc input for analog gate signal */ 224 EXT_AGATE_BNC_BIT = 0x8000, 225 /* use trig/ext clk bnc input for external stop trigger signal */ 226 EXT_STOP_TRIG_BNC_BIT = 0x4000, 227 /* use trig/ext clk bnc input for external start trigger signal */ 228 EXT_START_TRIG_BNC_BIT = 0x2000, 229 }; 230 231 enum adc_control0_contents { 232 ADC_GATE_SRC_MASK = 0x3, /* bits that select gate */ 233 ADC_SOFT_GATE_BITS = 0x1, /* software gate */ 234 ADC_EXT_GATE_BITS = 0x2, /* external digital gate */ 235 ADC_ANALOG_GATE_BITS = 0x3, /* analog level gate */ 236 /* level-sensitive gate (for digital) */ 237 ADC_GATE_LEVEL_BIT = 0x4, 238 ADC_GATE_POLARITY_BIT = 0x8, /* gate active low */ 239 ADC_START_TRIG_SOFT_BITS = 0x10, 240 ADC_START_TRIG_EXT_BITS = 0x20, 241 ADC_START_TRIG_ANALOG_BITS = 0x30, 242 ADC_START_TRIG_MASK = 0x30, 243 ADC_START_TRIG_FALLING_BIT = 0x40, /* trig 1 uses falling edge */ 244 /* external pacing uses falling edge */ 245 ADC_EXT_CONV_FALLING_BIT = 0x800, 246 /* enable hardware scan counter */ 247 ADC_SAMPLE_COUNTER_EN_BIT = 0x1000, 248 ADC_DMA_DISABLE_BIT = 0x4000, /* disables dma */ 249 ADC_ENABLE_BIT = 0x8000, /* master adc enable */ 250 }; 251 252 enum adc_control1_contents { 253 /* should be set for boards with > 16 channels */ 254 ADC_QUEUE_CONFIG_BIT = 0x1, 255 CONVERT_POLARITY_BIT = 0x10, 256 EOC_POLARITY_BIT = 0x20, 257 ADC_SW_GATE_BIT = 0x40, /* software gate of adc */ 258 ADC_DITHER_BIT = 0x200, /* turn on extra noise for dithering */ 259 RETRIGGER_BIT = 0x800, 260 ADC_LO_CHANNEL_4020_MASK = 0x300, 261 ADC_HI_CHANNEL_4020_MASK = 0xc00, 262 TWO_CHANNEL_4020_BITS = 0x1000, /* two channel mode for 4020 */ 263 FOUR_CHANNEL_4020_BITS = 0x2000, /* four channel mode for 4020 */ 264 CHANNEL_MODE_4020_MASK = 0x3000, 265 ADC_MODE_MASK = 0xf000, 266 }; 267 268 static inline u16 adc_lo_chan_4020_bits(unsigned int channel) 269 { 270 return (channel & 0x3) << 8; 271 }; 272 273 static inline u16 adc_hi_chan_4020_bits(unsigned int channel) 274 { 275 return (channel & 0x3) << 10; 276 }; 277 278 static inline u16 adc_mode_bits(unsigned int mode) 279 { 280 return (mode & 0xf) << 12; 281 }; 282 283 enum calibration_contents { 284 SELECT_8800_BIT = 0x1, 285 SELECT_8402_64XX_BIT = 0x2, 286 SELECT_1590_60XX_BIT = 0x2, 287 CAL_EN_64XX_BIT = 0x40, /* calibration enable for 64xx series */ 288 SERIAL_DATA_IN_BIT = 0x80, 289 SERIAL_CLOCK_BIT = 0x100, 290 CAL_EN_60XX_BIT = 0x200, /* calibration enable for 60xx series */ 291 CAL_GAIN_BIT = 0x800, 292 }; 293 294 /* 295 * calibration sources for 6025 are: 296 * 0 : ground 297 * 1 : 10V 298 * 2 : 5V 299 * 3 : 0.5V 300 * 4 : 0.05V 301 * 5 : ground 302 * 6 : dac channel 0 303 * 7 : dac channel 1 304 */ 305 306 static inline u16 adc_src_bits(unsigned int source) 307 { 308 return (source & 0xf) << 3; 309 }; 310 311 static inline u16 adc_convert_chan_4020_bits(unsigned int channel) 312 { 313 return (channel & 0x3) << 8; 314 }; 315 316 enum adc_queue_load_contents { 317 UNIP_BIT = 0x800, /* unipolar/bipolar bit */ 318 ADC_SE_DIFF_BIT = 0x1000, /* single-ended/ differential bit */ 319 /* non-referenced single-ended (common-mode input) */ 320 ADC_COMMON_BIT = 0x2000, 321 QUEUE_EOSEQ_BIT = 0x4000, /* queue end of sequence */ 322 QUEUE_EOSCAN_BIT = 0x8000, /* queue end of scan */ 323 }; 324 325 static inline u16 adc_chan_bits(unsigned int channel) 326 { 327 return channel & 0x3f; 328 }; 329 330 enum dac_control0_contents { 331 DAC_ENABLE_BIT = 0x8000, /* dac controller enable bit */ 332 DAC_CYCLIC_STOP_BIT = 0x4000, 333 DAC_WAVEFORM_MODE_BIT = 0x100, 334 DAC_EXT_UPDATE_FALLING_BIT = 0x80, 335 DAC_EXT_UPDATE_ENABLE_BIT = 0x40, 336 WAVEFORM_TRIG_MASK = 0x30, 337 WAVEFORM_TRIG_DISABLED_BITS = 0x0, 338 WAVEFORM_TRIG_SOFT_BITS = 0x10, 339 WAVEFORM_TRIG_EXT_BITS = 0x20, 340 WAVEFORM_TRIG_ADC1_BITS = 0x30, 341 WAVEFORM_TRIG_FALLING_BIT = 0x8, 342 WAVEFORM_GATE_LEVEL_BIT = 0x4, 343 WAVEFORM_GATE_ENABLE_BIT = 0x2, 344 WAVEFORM_GATE_SELECT_BIT = 0x1, 345 }; 346 347 enum dac_control1_contents { 348 DAC_WRITE_POLARITY_BIT = 0x800, /* board-dependent setting */ 349 DAC1_EXT_REF_BIT = 0x200, 350 DAC0_EXT_REF_BIT = 0x100, 351 DAC_OUTPUT_ENABLE_BIT = 0x80, /* dac output enable bit */ 352 DAC_UPDATE_POLARITY_BIT = 0x40, /* board-dependent setting */ 353 DAC_SW_GATE_BIT = 0x20, 354 DAC1_UNIPOLAR_BIT = 0x8, 355 DAC0_UNIPOLAR_BIT = 0x2, 356 }; 357 358 /* bit definitions for read-only registers */ 359 enum hw_status_contents { 360 DAC_UNDERRUN_BIT = 0x1, 361 ADC_OVERRUN_BIT = 0x2, 362 DAC_ACTIVE_BIT = 0x4, 363 ADC_ACTIVE_BIT = 0x8, 364 DAC_INTR_PENDING_BIT = 0x10, 365 ADC_INTR_PENDING_BIT = 0x20, 366 DAC_DONE_BIT = 0x40, 367 ADC_DONE_BIT = 0x80, 368 EXT_INTR_PENDING_BIT = 0x100, 369 ADC_STOP_BIT = 0x200, 370 }; 371 372 static inline u16 pipe_full_bits(u16 hw_status_bits) 373 { 374 return (hw_status_bits >> 10) & 0x3; 375 }; 376 377 static inline unsigned int adc_upper_read_ptr_code(u16 prepost_bits) 378 { 379 return (prepost_bits >> 12) & 0x3; 380 } 381 382 static inline unsigned int adc_upper_write_ptr_code(u16 prepost_bits) 383 { 384 return (prepost_bits >> 14) & 0x3; 385 } 386 387 /* I2C addresses for 4020 */ 388 enum i2c_addresses { 389 RANGE_CAL_I2C_ADDR = 0x20, 390 CALDAC0_I2C_ADDR = 0xc, 391 CALDAC1_I2C_ADDR = 0xd, 392 }; 393 394 enum range_cal_i2c_contents { 395 /* bits that set what source the adc converter measures */ 396 ADC_SRC_4020_MASK = 0x70, 397 /* make bnc trig/ext clock threshold 0V instead of 2.5V */ 398 BNC_TRIG_THRESHOLD_0V_BIT = 0x80, 399 }; 400 401 static inline u8 adc_src_4020_bits(unsigned int source) 402 { 403 return (source << 4) & ADC_SRC_4020_MASK; 404 }; 405 406 static inline u8 attenuate_bit(unsigned int channel) 407 { 408 /* attenuate channel (+-5V input range) */ 409 return 1 << (channel & 0x3); 410 }; 411 412 /* analog input ranges for 64xx boards */ 413 static const struct comedi_lrange ai_ranges_64xx = { 414 8, { 415 BIP_RANGE(10), 416 BIP_RANGE(5), 417 BIP_RANGE(2.5), 418 BIP_RANGE(1.25), 419 UNI_RANGE(10), 420 UNI_RANGE(5), 421 UNI_RANGE(2.5), 422 UNI_RANGE(1.25) 423 } 424 }; 425 426 static const u8 ai_range_code_64xx[8] = { 427 0x0, 0x1, 0x2, 0x3, /* bipolar 10, 5, 2,5, 1.25 */ 428 0x8, 0x9, 0xa, 0xb /* unipolar 10, 5, 2.5, 1.25 */ 429 }; 430 431 /* analog input ranges for 64-Mx boards */ 432 static const struct comedi_lrange ai_ranges_64_mx = { 433 7, { 434 BIP_RANGE(5), 435 BIP_RANGE(2.5), 436 BIP_RANGE(1.25), 437 BIP_RANGE(0.625), 438 UNI_RANGE(5), 439 UNI_RANGE(2.5), 440 UNI_RANGE(1.25) 441 } 442 }; 443 444 static const u8 ai_range_code_64_mx[7] = { 445 0x0, 0x1, 0x2, 0x3, /* bipolar 5, 2.5, 1.25, 0.625 */ 446 0x9, 0xa, 0xb /* unipolar 5, 2.5, 1.25 */ 447 }; 448 449 /* analog input ranges for 60xx boards */ 450 static const struct comedi_lrange ai_ranges_60xx = { 451 4, { 452 BIP_RANGE(10), 453 BIP_RANGE(5), 454 BIP_RANGE(0.5), 455 BIP_RANGE(0.05) 456 } 457 }; 458 459 static const u8 ai_range_code_60xx[4] = { 460 0x0, 0x1, 0x4, 0x7 /* bipolar 10, 5, 0.5, 0.05 */ 461 }; 462 463 /* analog input ranges for 6030, etc boards */ 464 static const struct comedi_lrange ai_ranges_6030 = { 465 14, { 466 BIP_RANGE(10), 467 BIP_RANGE(5), 468 BIP_RANGE(2), 469 BIP_RANGE(1), 470 BIP_RANGE(0.5), 471 BIP_RANGE(0.2), 472 BIP_RANGE(0.1), 473 UNI_RANGE(10), 474 UNI_RANGE(5), 475 UNI_RANGE(2), 476 UNI_RANGE(1), 477 UNI_RANGE(0.5), 478 UNI_RANGE(0.2), 479 UNI_RANGE(0.1) 480 } 481 }; 482 483 static const u8 ai_range_code_6030[14] = { 484 0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, /* bip 10, 5, 2, 1, 0.5, 0.2, 0.1 */ 485 0x9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf /* uni 10, 5, 2, 1, 0.5, 0.2, 0.1 */ 486 }; 487 488 /* analog input ranges for 6052, etc boards */ 489 static const struct comedi_lrange ai_ranges_6052 = { 490 15, { 491 BIP_RANGE(10), 492 BIP_RANGE(5), 493 BIP_RANGE(2.5), 494 BIP_RANGE(1), 495 BIP_RANGE(0.5), 496 BIP_RANGE(0.25), 497 BIP_RANGE(0.1), 498 BIP_RANGE(0.05), 499 UNI_RANGE(10), 500 UNI_RANGE(5), 501 UNI_RANGE(2), 502 UNI_RANGE(1), 503 UNI_RANGE(0.5), 504 UNI_RANGE(0.2), 505 UNI_RANGE(0.1) 506 } 507 }; 508 509 static const u8 ai_range_code_6052[15] = { 510 0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, /* bipolar 10 ... 0.05 */ 511 0x9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf /* unipolar 10 ... 0.1 */ 512 }; 513 514 /* analog input ranges for 4020 board */ 515 static const struct comedi_lrange ai_ranges_4020 = { 516 2, { 517 BIP_RANGE(5), 518 BIP_RANGE(1) 519 } 520 }; 521 522 /* analog output ranges */ 523 static const struct comedi_lrange ao_ranges_64xx = { 524 4, { 525 BIP_RANGE(5), 526 BIP_RANGE(10), 527 UNI_RANGE(5), 528 UNI_RANGE(10) 529 } 530 }; 531 532 static const int ao_range_code_64xx[] = { 533 0x0, 534 0x1, 535 0x2, 536 0x3, 537 }; 538 539 static const int ao_range_code_60xx[] = { 540 0x0, 541 }; 542 543 static const struct comedi_lrange ao_ranges_6030 = { 544 2, { 545 BIP_RANGE(10), 546 UNI_RANGE(10) 547 } 548 }; 549 550 static const int ao_range_code_6030[] = { 551 0x0, 552 0x2, 553 }; 554 555 static const struct comedi_lrange ao_ranges_4020 = { 556 2, { 557 BIP_RANGE(5), 558 BIP_RANGE(10) 559 } 560 }; 561 562 static const int ao_range_code_4020[] = { 563 0x1, 564 0x0, 565 }; 566 567 enum register_layout { 568 LAYOUT_60XX, 569 LAYOUT_64XX, 570 LAYOUT_4020, 571 }; 572 573 struct hw_fifo_info { 574 unsigned int num_segments; 575 unsigned int max_segment_length; 576 unsigned int sample_packing_ratio; 577 u16 fifo_size_reg_mask; 578 }; 579 580 enum pcidas64_boardid { 581 BOARD_PCIDAS6402_16, 582 BOARD_PCIDAS6402_12, 583 BOARD_PCIDAS64_M1_16, 584 BOARD_PCIDAS64_M2_16, 585 BOARD_PCIDAS64_M3_16, 586 BOARD_PCIDAS6013, 587 BOARD_PCIDAS6014, 588 BOARD_PCIDAS6023, 589 BOARD_PCIDAS6025, 590 BOARD_PCIDAS6030, 591 BOARD_PCIDAS6031, 592 BOARD_PCIDAS6032, 593 BOARD_PCIDAS6033, 594 BOARD_PCIDAS6034, 595 BOARD_PCIDAS6035, 596 BOARD_PCIDAS6036, 597 BOARD_PCIDAS6040, 598 BOARD_PCIDAS6052, 599 BOARD_PCIDAS6070, 600 BOARD_PCIDAS6071, 601 BOARD_PCIDAS4020_12, 602 BOARD_PCIDAS6402_16_JR, 603 BOARD_PCIDAS64_M1_16_JR, 604 BOARD_PCIDAS64_M2_16_JR, 605 BOARD_PCIDAS64_M3_16_JR, 606 BOARD_PCIDAS64_M1_14, 607 BOARD_PCIDAS64_M2_14, 608 BOARD_PCIDAS64_M3_14, 609 }; 610 611 struct pcidas64_board { 612 const char *name; 613 int ai_se_chans; /* number of ai inputs in single-ended mode */ 614 int ai_bits; /* analog input resolution */ 615 int ai_speed; /* fastest conversion period in ns */ 616 const struct comedi_lrange *ai_range_table; 617 const u8 *ai_range_code; 618 int ao_nchan; /* number of analog out channels */ 619 int ao_bits; /* analog output resolution */ 620 int ao_scan_speed; /* analog output scan speed */ 621 const struct comedi_lrange *ao_range_table; 622 const int *ao_range_code; 623 const struct hw_fifo_info *const ai_fifo; 624 /* different board families have slightly different registers */ 625 enum register_layout layout; 626 unsigned has_8255:1; 627 }; 628 629 static const struct hw_fifo_info ai_fifo_4020 = { 630 .num_segments = 2, 631 .max_segment_length = 0x8000, 632 .sample_packing_ratio = 2, 633 .fifo_size_reg_mask = 0x7f, 634 }; 635 636 static const struct hw_fifo_info ai_fifo_64xx = { 637 .num_segments = 4, 638 .max_segment_length = 0x800, 639 .sample_packing_ratio = 1, 640 .fifo_size_reg_mask = 0x3f, 641 }; 642 643 static const struct hw_fifo_info ai_fifo_60xx = { 644 .num_segments = 4, 645 .max_segment_length = 0x800, 646 .sample_packing_ratio = 1, 647 .fifo_size_reg_mask = 0x7f, 648 }; 649 650 /* 651 * maximum number of dma transfers we will chain together into a ring 652 * (and the maximum number of dma buffers we maintain) 653 */ 654 #define MAX_AI_DMA_RING_COUNT (0x80000 / DMA_BUFFER_SIZE) 655 #define MIN_AI_DMA_RING_COUNT (0x10000 / DMA_BUFFER_SIZE) 656 #define AO_DMA_RING_COUNT (0x10000 / DMA_BUFFER_SIZE) 657 static inline unsigned int ai_dma_ring_count(const struct pcidas64_board *board) 658 { 659 if (board->layout == LAYOUT_4020) 660 return MAX_AI_DMA_RING_COUNT; 661 662 return MIN_AI_DMA_RING_COUNT; 663 } 664 665 static const int bytes_in_sample = 2; 666 667 static const struct pcidas64_board pcidas64_boards[] = { 668 [BOARD_PCIDAS6402_16] = { 669 .name = "pci-das6402/16", 670 .ai_se_chans = 64, 671 .ai_bits = 16, 672 .ai_speed = 5000, 673 .ao_nchan = 2, 674 .ao_bits = 16, 675 .ao_scan_speed = 10000, 676 .layout = LAYOUT_64XX, 677 .ai_range_table = &ai_ranges_64xx, 678 .ai_range_code = ai_range_code_64xx, 679 .ao_range_table = &ao_ranges_64xx, 680 .ao_range_code = ao_range_code_64xx, 681 .ai_fifo = &ai_fifo_64xx, 682 .has_8255 = 1, 683 }, 684 [BOARD_PCIDAS6402_12] = { 685 .name = "pci-das6402/12", /* XXX check */ 686 .ai_se_chans = 64, 687 .ai_bits = 12, 688 .ai_speed = 5000, 689 .ao_nchan = 2, 690 .ao_bits = 12, 691 .ao_scan_speed = 10000, 692 .layout = LAYOUT_64XX, 693 .ai_range_table = &ai_ranges_64xx, 694 .ai_range_code = ai_range_code_64xx, 695 .ao_range_table = &ao_ranges_64xx, 696 .ao_range_code = ao_range_code_64xx, 697 .ai_fifo = &ai_fifo_64xx, 698 .has_8255 = 1, 699 }, 700 [BOARD_PCIDAS64_M1_16] = { 701 .name = "pci-das64/m1/16", 702 .ai_se_chans = 64, 703 .ai_bits = 16, 704 .ai_speed = 1000, 705 .ao_nchan = 2, 706 .ao_bits = 16, 707 .ao_scan_speed = 10000, 708 .layout = LAYOUT_64XX, 709 .ai_range_table = &ai_ranges_64_mx, 710 .ai_range_code = ai_range_code_64_mx, 711 .ao_range_table = &ao_ranges_64xx, 712 .ao_range_code = ao_range_code_64xx, 713 .ai_fifo = &ai_fifo_64xx, 714 .has_8255 = 1, 715 }, 716 [BOARD_PCIDAS64_M2_16] = { 717 .name = "pci-das64/m2/16", 718 .ai_se_chans = 64, 719 .ai_bits = 16, 720 .ai_speed = 500, 721 .ao_nchan = 2, 722 .ao_bits = 16, 723 .ao_scan_speed = 10000, 724 .layout = LAYOUT_64XX, 725 .ai_range_table = &ai_ranges_64_mx, 726 .ai_range_code = ai_range_code_64_mx, 727 .ao_range_table = &ao_ranges_64xx, 728 .ao_range_code = ao_range_code_64xx, 729 .ai_fifo = &ai_fifo_64xx, 730 .has_8255 = 1, 731 }, 732 [BOARD_PCIDAS64_M3_16] = { 733 .name = "pci-das64/m3/16", 734 .ai_se_chans = 64, 735 .ai_bits = 16, 736 .ai_speed = 333, 737 .ao_nchan = 2, 738 .ao_bits = 16, 739 .ao_scan_speed = 10000, 740 .layout = LAYOUT_64XX, 741 .ai_range_table = &ai_ranges_64_mx, 742 .ai_range_code = ai_range_code_64_mx, 743 .ao_range_table = &ao_ranges_64xx, 744 .ao_range_code = ao_range_code_64xx, 745 .ai_fifo = &ai_fifo_64xx, 746 .has_8255 = 1, 747 }, 748 [BOARD_PCIDAS6013] = { 749 .name = "pci-das6013", 750 .ai_se_chans = 16, 751 .ai_bits = 16, 752 .ai_speed = 5000, 753 .ao_nchan = 0, 754 .ao_bits = 16, 755 .layout = LAYOUT_60XX, 756 .ai_range_table = &ai_ranges_60xx, 757 .ai_range_code = ai_range_code_60xx, 758 .ao_range_table = &range_bipolar10, 759 .ao_range_code = ao_range_code_60xx, 760 .ai_fifo = &ai_fifo_60xx, 761 .has_8255 = 0, 762 }, 763 [BOARD_PCIDAS6014] = { 764 .name = "pci-das6014", 765 .ai_se_chans = 16, 766 .ai_bits = 16, 767 .ai_speed = 5000, 768 .ao_nchan = 2, 769 .ao_bits = 16, 770 .ao_scan_speed = 100000, 771 .layout = LAYOUT_60XX, 772 .ai_range_table = &ai_ranges_60xx, 773 .ai_range_code = ai_range_code_60xx, 774 .ao_range_table = &range_bipolar10, 775 .ao_range_code = ao_range_code_60xx, 776 .ai_fifo = &ai_fifo_60xx, 777 .has_8255 = 0, 778 }, 779 [BOARD_PCIDAS6023] = { 780 .name = "pci-das6023", 781 .ai_se_chans = 16, 782 .ai_bits = 12, 783 .ai_speed = 5000, 784 .ao_nchan = 0, 785 .ao_scan_speed = 100000, 786 .layout = LAYOUT_60XX, 787 .ai_range_table = &ai_ranges_60xx, 788 .ai_range_code = ai_range_code_60xx, 789 .ao_range_table = &range_bipolar10, 790 .ao_range_code = ao_range_code_60xx, 791 .ai_fifo = &ai_fifo_60xx, 792 .has_8255 = 1, 793 }, 794 [BOARD_PCIDAS6025] = { 795 .name = "pci-das6025", 796 .ai_se_chans = 16, 797 .ai_bits = 12, 798 .ai_speed = 5000, 799 .ao_nchan = 2, 800 .ao_bits = 12, 801 .ao_scan_speed = 100000, 802 .layout = LAYOUT_60XX, 803 .ai_range_table = &ai_ranges_60xx, 804 .ai_range_code = ai_range_code_60xx, 805 .ao_range_table = &range_bipolar10, 806 .ao_range_code = ao_range_code_60xx, 807 .ai_fifo = &ai_fifo_60xx, 808 .has_8255 = 1, 809 }, 810 [BOARD_PCIDAS6030] = { 811 .name = "pci-das6030", 812 .ai_se_chans = 16, 813 .ai_bits = 16, 814 .ai_speed = 10000, 815 .ao_nchan = 2, 816 .ao_bits = 16, 817 .ao_scan_speed = 10000, 818 .layout = LAYOUT_60XX, 819 .ai_range_table = &ai_ranges_6030, 820 .ai_range_code = ai_range_code_6030, 821 .ao_range_table = &ao_ranges_6030, 822 .ao_range_code = ao_range_code_6030, 823 .ai_fifo = &ai_fifo_60xx, 824 .has_8255 = 0, 825 }, 826 [BOARD_PCIDAS6031] = { 827 .name = "pci-das6031", 828 .ai_se_chans = 64, 829 .ai_bits = 16, 830 .ai_speed = 10000, 831 .ao_nchan = 2, 832 .ao_bits = 16, 833 .ao_scan_speed = 10000, 834 .layout = LAYOUT_60XX, 835 .ai_range_table = &ai_ranges_6030, 836 .ai_range_code = ai_range_code_6030, 837 .ao_range_table = &ao_ranges_6030, 838 .ao_range_code = ao_range_code_6030, 839 .ai_fifo = &ai_fifo_60xx, 840 .has_8255 = 0, 841 }, 842 [BOARD_PCIDAS6032] = { 843 .name = "pci-das6032", 844 .ai_se_chans = 16, 845 .ai_bits = 16, 846 .ai_speed = 10000, 847 .ao_nchan = 0, 848 .layout = LAYOUT_60XX, 849 .ai_range_table = &ai_ranges_6030, 850 .ai_range_code = ai_range_code_6030, 851 .ai_fifo = &ai_fifo_60xx, 852 .has_8255 = 0, 853 }, 854 [BOARD_PCIDAS6033] = { 855 .name = "pci-das6033", 856 .ai_se_chans = 64, 857 .ai_bits = 16, 858 .ai_speed = 10000, 859 .ao_nchan = 0, 860 .layout = LAYOUT_60XX, 861 .ai_range_table = &ai_ranges_6030, 862 .ai_range_code = ai_range_code_6030, 863 .ai_fifo = &ai_fifo_60xx, 864 .has_8255 = 0, 865 }, 866 [BOARD_PCIDAS6034] = { 867 .name = "pci-das6034", 868 .ai_se_chans = 16, 869 .ai_bits = 16, 870 .ai_speed = 5000, 871 .ao_nchan = 0, 872 .ao_scan_speed = 0, 873 .layout = LAYOUT_60XX, 874 .ai_range_table = &ai_ranges_60xx, 875 .ai_range_code = ai_range_code_60xx, 876 .ai_fifo = &ai_fifo_60xx, 877 .has_8255 = 0, 878 }, 879 [BOARD_PCIDAS6035] = { 880 .name = "pci-das6035", 881 .ai_se_chans = 16, 882 .ai_bits = 16, 883 .ai_speed = 5000, 884 .ao_nchan = 2, 885 .ao_bits = 12, 886 .ao_scan_speed = 100000, 887 .layout = LAYOUT_60XX, 888 .ai_range_table = &ai_ranges_60xx, 889 .ai_range_code = ai_range_code_60xx, 890 .ao_range_table = &range_bipolar10, 891 .ao_range_code = ao_range_code_60xx, 892 .ai_fifo = &ai_fifo_60xx, 893 .has_8255 = 0, 894 }, 895 [BOARD_PCIDAS6036] = { 896 .name = "pci-das6036", 897 .ai_se_chans = 16, 898 .ai_bits = 16, 899 .ai_speed = 5000, 900 .ao_nchan = 2, 901 .ao_bits = 16, 902 .ao_scan_speed = 100000, 903 .layout = LAYOUT_60XX, 904 .ai_range_table = &ai_ranges_60xx, 905 .ai_range_code = ai_range_code_60xx, 906 .ao_range_table = &range_bipolar10, 907 .ao_range_code = ao_range_code_60xx, 908 .ai_fifo = &ai_fifo_60xx, 909 .has_8255 = 0, 910 }, 911 [BOARD_PCIDAS6040] = { 912 .name = "pci-das6040", 913 .ai_se_chans = 16, 914 .ai_bits = 12, 915 .ai_speed = 2000, 916 .ao_nchan = 2, 917 .ao_bits = 12, 918 .ao_scan_speed = 1000, 919 .layout = LAYOUT_60XX, 920 .ai_range_table = &ai_ranges_6052, 921 .ai_range_code = ai_range_code_6052, 922 .ao_range_table = &ao_ranges_6030, 923 .ao_range_code = ao_range_code_6030, 924 .ai_fifo = &ai_fifo_60xx, 925 .has_8255 = 0, 926 }, 927 [BOARD_PCIDAS6052] = { 928 .name = "pci-das6052", 929 .ai_se_chans = 16, 930 .ai_bits = 16, 931 .ai_speed = 3333, 932 .ao_nchan = 2, 933 .ao_bits = 16, 934 .ao_scan_speed = 3333, 935 .layout = LAYOUT_60XX, 936 .ai_range_table = &ai_ranges_6052, 937 .ai_range_code = ai_range_code_6052, 938 .ao_range_table = &ao_ranges_6030, 939 .ao_range_code = ao_range_code_6030, 940 .ai_fifo = &ai_fifo_60xx, 941 .has_8255 = 0, 942 }, 943 [BOARD_PCIDAS6070] = { 944 .name = "pci-das6070", 945 .ai_se_chans = 16, 946 .ai_bits = 12, 947 .ai_speed = 800, 948 .ao_nchan = 2, 949 .ao_bits = 12, 950 .ao_scan_speed = 1000, 951 .layout = LAYOUT_60XX, 952 .ai_range_table = &ai_ranges_6052, 953 .ai_range_code = ai_range_code_6052, 954 .ao_range_table = &ao_ranges_6030, 955 .ao_range_code = ao_range_code_6030, 956 .ai_fifo = &ai_fifo_60xx, 957 .has_8255 = 0, 958 }, 959 [BOARD_PCIDAS6071] = { 960 .name = "pci-das6071", 961 .ai_se_chans = 64, 962 .ai_bits = 12, 963 .ai_speed = 800, 964 .ao_nchan = 2, 965 .ao_bits = 12, 966 .ao_scan_speed = 1000, 967 .layout = LAYOUT_60XX, 968 .ai_range_table = &ai_ranges_6052, 969 .ai_range_code = ai_range_code_6052, 970 .ao_range_table = &ao_ranges_6030, 971 .ao_range_code = ao_range_code_6030, 972 .ai_fifo = &ai_fifo_60xx, 973 .has_8255 = 0, 974 }, 975 [BOARD_PCIDAS4020_12] = { 976 .name = "pci-das4020/12", 977 .ai_se_chans = 4, 978 .ai_bits = 12, 979 .ai_speed = 50, 980 .ao_bits = 12, 981 .ao_nchan = 2, 982 .ao_scan_speed = 0, /* no hardware pacing on ao */ 983 .layout = LAYOUT_4020, 984 .ai_range_table = &ai_ranges_4020, 985 .ao_range_table = &ao_ranges_4020, 986 .ao_range_code = ao_range_code_4020, 987 .ai_fifo = &ai_fifo_4020, 988 .has_8255 = 1, 989 }, 990 #if 0 991 /* The device id for these boards is unknown */ 992 993 [BOARD_PCIDAS6402_16_JR] = { 994 .name = "pci-das6402/16/jr", 995 .ai_se_chans = 64, 996 .ai_bits = 16, 997 .ai_speed = 5000, 998 .ao_nchan = 0, 999 .ao_scan_speed = 10000, 1000 .layout = LAYOUT_64XX, 1001 .ai_range_table = &ai_ranges_64xx, 1002 .ai_range_code = ai_range_code_64xx, 1003 .ai_fifo = ai_fifo_64xx, 1004 .has_8255 = 1, 1005 }, 1006 [BOARD_PCIDAS64_M1_16_JR] = { 1007 .name = "pci-das64/m1/16/jr", 1008 .ai_se_chans = 64, 1009 .ai_bits = 16, 1010 .ai_speed = 1000, 1011 .ao_nchan = 0, 1012 .ao_scan_speed = 10000, 1013 .layout = LAYOUT_64XX, 1014 .ai_range_table = &ai_ranges_64_mx, 1015 .ai_range_code = ai_range_code_64_mx, 1016 .ai_fifo = ai_fifo_64xx, 1017 .has_8255 = 1, 1018 }, 1019 [BOARD_PCIDAS64_M2_16_JR] = { 1020 .name = "pci-das64/m2/16/jr", 1021 .ai_se_chans = 64, 1022 .ai_bits = 16, 1023 .ai_speed = 500, 1024 .ao_nchan = 0, 1025 .ao_scan_speed = 10000, 1026 .layout = LAYOUT_64XX, 1027 .ai_range_table = &ai_ranges_64_mx, 1028 .ai_range_code = ai_range_code_64_mx, 1029 .ai_fifo = ai_fifo_64xx, 1030 .has_8255 = 1, 1031 }, 1032 [BOARD_PCIDAS64_M3_16_JR] = { 1033 .name = "pci-das64/m3/16/jr", 1034 .ai_se_chans = 64, 1035 .ai_bits = 16, 1036 .ai_speed = 333, 1037 .ao_nchan = 0, 1038 .ao_scan_speed = 10000, 1039 .layout = LAYOUT_64XX, 1040 .ai_range_table = &ai_ranges_64_mx, 1041 .ai_range_code = ai_range_code_64_mx, 1042 .ai_fifo = ai_fifo_64xx, 1043 .has_8255 = 1, 1044 }, 1045 [BOARD_PCIDAS64_M1_14] = { 1046 .name = "pci-das64/m1/14", 1047 .ai_se_chans = 64, 1048 .ai_bits = 14, 1049 .ai_speed = 1000, 1050 .ao_nchan = 2, 1051 .ao_scan_speed = 10000, 1052 .layout = LAYOUT_64XX, 1053 .ai_range_table = &ai_ranges_64_mx, 1054 .ai_range_code = ai_range_code_64_mx, 1055 .ai_fifo = ai_fifo_64xx, 1056 .has_8255 = 1, 1057 }, 1058 [BOARD_PCIDAS64_M2_14] = { 1059 .name = "pci-das64/m2/14", 1060 .ai_se_chans = 64, 1061 .ai_bits = 14, 1062 .ai_speed = 500, 1063 .ao_nchan = 2, 1064 .ao_scan_speed = 10000, 1065 .layout = LAYOUT_64XX, 1066 .ai_range_table = &ai_ranges_64_mx, 1067 .ai_range_code = ai_range_code_64_mx, 1068 .ai_fifo = ai_fifo_64xx, 1069 .has_8255 = 1, 1070 }, 1071 [BOARD_PCIDAS64_M3_14] = { 1072 .name = "pci-das64/m3/14", 1073 .ai_se_chans = 64, 1074 .ai_bits = 14, 1075 .ai_speed = 333, 1076 .ao_nchan = 2, 1077 .ao_scan_speed = 10000, 1078 .layout = LAYOUT_64XX, 1079 .ai_range_table = &ai_ranges_64_mx, 1080 .ai_range_code = ai_range_code_64_mx, 1081 .ai_fifo = ai_fifo_64xx, 1082 .has_8255 = 1, 1083 }, 1084 #endif 1085 }; 1086 1087 static inline unsigned short se_diff_bit_6xxx(struct comedi_device *dev, 1088 int use_differential) 1089 { 1090 const struct pcidas64_board *board = dev->board_ptr; 1091 1092 if ((board->layout == LAYOUT_64XX && !use_differential) || 1093 (board->layout == LAYOUT_60XX && use_differential)) 1094 return ADC_SE_DIFF_BIT; 1095 1096 return 0; 1097 } 1098 1099 struct ext_clock_info { 1100 /* master clock divisor to use for scans with external master clock */ 1101 unsigned int divisor; 1102 /* chanspec for master clock input when used as scan begin src */ 1103 unsigned int chanspec; 1104 }; 1105 1106 /* this structure is for data unique to this hardware driver. */ 1107 struct pcidas64_private { 1108 /* base addresses (physical) */ 1109 resource_size_t main_phys_iobase; 1110 resource_size_t dio_counter_phys_iobase; 1111 /* base addresses (ioremapped) */ 1112 void __iomem *plx9080_iobase; 1113 void __iomem *main_iobase; 1114 /* local address (used by dma controller) */ 1115 u32 local0_iobase; 1116 u32 local1_iobase; 1117 /* dma buffers for analog input */ 1118 u16 *ai_buffer[MAX_AI_DMA_RING_COUNT]; 1119 /* physical addresses of ai dma buffers */ 1120 dma_addr_t ai_buffer_bus_addr[MAX_AI_DMA_RING_COUNT]; 1121 /* 1122 * array of ai dma descriptors read by plx9080, 1123 * allocated to get proper alignment 1124 */ 1125 struct plx_dma_desc *ai_dma_desc; 1126 /* physical address of ai dma descriptor array */ 1127 dma_addr_t ai_dma_desc_bus_addr; 1128 /* 1129 * index of the ai dma descriptor/buffer 1130 * that is currently being used 1131 */ 1132 unsigned int ai_dma_index; 1133 /* dma buffers for analog output */ 1134 u16 *ao_buffer[AO_DMA_RING_COUNT]; 1135 /* physical addresses of ao dma buffers */ 1136 dma_addr_t ao_buffer_bus_addr[AO_DMA_RING_COUNT]; 1137 struct plx_dma_desc *ao_dma_desc; 1138 dma_addr_t ao_dma_desc_bus_addr; 1139 /* keeps track of buffer where the next ao sample should go */ 1140 unsigned int ao_dma_index; 1141 unsigned int hw_revision; /* stc chip hardware revision number */ 1142 /* last bits sent to INTR_ENABLE_REG register */ 1143 unsigned int intr_enable_bits; 1144 /* last bits sent to ADC_CONTROL1_REG register */ 1145 u16 adc_control1_bits; 1146 /* last bits sent to FIFO_SIZE_REG register */ 1147 u16 fifo_size_bits; 1148 /* last bits sent to HW_CONFIG_REG register */ 1149 u16 hw_config_bits; 1150 u16 dac_control1_bits; 1151 /* last bits written to plx9080 control register */ 1152 u32 plx_control_bits; 1153 /* last bits written to plx interrupt control and status register */ 1154 u32 plx_intcsr_bits; 1155 /* index of calibration source readable through ai ch0 */ 1156 int calibration_source; 1157 /* bits written to i2c calibration/range register */ 1158 u8 i2c_cal_range_bits; 1159 /* configure digital triggers to trigger on falling edge */ 1160 unsigned int ext_trig_falling; 1161 short ai_cmd_running; 1162 unsigned int ai_fifo_segment_length; 1163 struct ext_clock_info ext_clock; 1164 unsigned short ao_bounce_buffer[DAC_FIFO_SIZE]; 1165 }; 1166 1167 static unsigned int ai_range_bits_6xxx(const struct comedi_device *dev, 1168 unsigned int range_index) 1169 { 1170 const struct pcidas64_board *board = dev->board_ptr; 1171 1172 return board->ai_range_code[range_index] << 8; 1173 } 1174 1175 static unsigned int hw_revision(const struct comedi_device *dev, 1176 u16 hw_status_bits) 1177 { 1178 const struct pcidas64_board *board = dev->board_ptr; 1179 1180 if (board->layout == LAYOUT_4020) 1181 return (hw_status_bits >> 13) & 0x7; 1182 1183 return (hw_status_bits >> 12) & 0xf; 1184 } 1185 1186 static void set_dac_range_bits(struct comedi_device *dev, 1187 u16 *bits, unsigned int channel, 1188 unsigned int range) 1189 { 1190 const struct pcidas64_board *board = dev->board_ptr; 1191 unsigned int code = board->ao_range_code[range]; 1192 1193 if (channel > 1) 1194 dev_err(dev->class_dev, "bug! bad channel?\n"); 1195 if (code & ~0x3) 1196 dev_err(dev->class_dev, "bug! bad range code?\n"); 1197 1198 *bits &= ~(0x3 << (2 * channel)); 1199 *bits |= code << (2 * channel); 1200 }; 1201 1202 static inline int ao_cmd_is_supported(const struct pcidas64_board *board) 1203 { 1204 return board->ao_nchan && board->layout != LAYOUT_4020; 1205 } 1206 1207 static void abort_dma(struct comedi_device *dev, unsigned int channel) 1208 { 1209 struct pcidas64_private *devpriv = dev->private; 1210 unsigned long flags; 1211 1212 /* spinlock for plx dma control/status reg */ 1213 spin_lock_irqsave(&dev->spinlock, flags); 1214 1215 plx9080_abort_dma(devpriv->plx9080_iobase, channel); 1216 1217 spin_unlock_irqrestore(&dev->spinlock, flags); 1218 } 1219 1220 static void disable_plx_interrupts(struct comedi_device *dev) 1221 { 1222 struct pcidas64_private *devpriv = dev->private; 1223 1224 devpriv->plx_intcsr_bits = 0; 1225 writel(devpriv->plx_intcsr_bits, 1226 devpriv->plx9080_iobase + PLX_REG_INTCSR); 1227 } 1228 1229 static void disable_ai_interrupts(struct comedi_device *dev) 1230 { 1231 struct pcidas64_private *devpriv = dev->private; 1232 unsigned long flags; 1233 1234 spin_lock_irqsave(&dev->spinlock, flags); 1235 devpriv->intr_enable_bits &= 1236 ~EN_ADC_INTR_SRC_BIT & ~EN_ADC_DONE_INTR_BIT & 1237 ~EN_ADC_ACTIVE_INTR_BIT & ~EN_ADC_STOP_INTR_BIT & 1238 ~EN_ADC_OVERRUN_BIT & ~ADC_INTR_SRC_MASK; 1239 writew(devpriv->intr_enable_bits, 1240 devpriv->main_iobase + INTR_ENABLE_REG); 1241 spin_unlock_irqrestore(&dev->spinlock, flags); 1242 } 1243 1244 static void enable_ai_interrupts(struct comedi_device *dev, 1245 const struct comedi_cmd *cmd) 1246 { 1247 const struct pcidas64_board *board = dev->board_ptr; 1248 struct pcidas64_private *devpriv = dev->private; 1249 u32 bits; 1250 unsigned long flags; 1251 1252 bits = EN_ADC_OVERRUN_BIT | EN_ADC_DONE_INTR_BIT | 1253 EN_ADC_ACTIVE_INTR_BIT | EN_ADC_STOP_INTR_BIT; 1254 /* 1255 * Use pio transfer and interrupt on end of conversion 1256 * if CMDF_WAKE_EOS flag is set. 1257 */ 1258 if (cmd->flags & CMDF_WAKE_EOS) { 1259 /* 4020 doesn't support pio transfers except for fifo dregs */ 1260 if (board->layout != LAYOUT_4020) 1261 bits |= ADC_INTR_EOSCAN_BITS | EN_ADC_INTR_SRC_BIT; 1262 } 1263 spin_lock_irqsave(&dev->spinlock, flags); 1264 devpriv->intr_enable_bits |= bits; 1265 writew(devpriv->intr_enable_bits, 1266 devpriv->main_iobase + INTR_ENABLE_REG); 1267 spin_unlock_irqrestore(&dev->spinlock, flags); 1268 } 1269 1270 /* initialize plx9080 chip */ 1271 static void init_plx9080(struct comedi_device *dev) 1272 { 1273 const struct pcidas64_board *board = dev->board_ptr; 1274 struct pcidas64_private *devpriv = dev->private; 1275 u32 bits; 1276 void __iomem *plx_iobase = devpriv->plx9080_iobase; 1277 1278 devpriv->plx_control_bits = 1279 readl(devpriv->plx9080_iobase + PLX_REG_CNTRL); 1280 1281 #ifdef __BIG_ENDIAN 1282 bits = PLX_BIGEND_DMA0 | PLX_BIGEND_DMA1; 1283 #else 1284 bits = 0; 1285 #endif 1286 writel(bits, devpriv->plx9080_iobase + PLX_REG_BIGEND); 1287 1288 disable_plx_interrupts(dev); 1289 1290 abort_dma(dev, 0); 1291 abort_dma(dev, 1); 1292 1293 /* configure dma0 mode */ 1294 bits = 0; 1295 /* enable ready input, not sure if this is necessary */ 1296 bits |= PLX_DMAMODE_READYIEN; 1297 /* enable bterm, not sure if this is necessary */ 1298 bits |= PLX_DMAMODE_BTERMIEN; 1299 /* enable dma chaining */ 1300 bits |= PLX_DMAMODE_CHAINEN; 1301 /* 1302 * enable interrupt on dma done 1303 * (probably don't need this, since chain never finishes) 1304 */ 1305 bits |= PLX_DMAMODE_DONEIEN; 1306 /* 1307 * don't increment local address during transfers 1308 * (we are transferring from a fixed fifo register) 1309 */ 1310 bits |= PLX_DMAMODE_LACONST; 1311 /* route dma interrupt to pci bus */ 1312 bits |= PLX_DMAMODE_INTRPCI; 1313 /* enable demand mode */ 1314 bits |= PLX_DMAMODE_DEMAND; 1315 /* enable local burst mode */ 1316 bits |= PLX_DMAMODE_BURSTEN; 1317 /* 4020 uses 32 bit dma */ 1318 if (board->layout == LAYOUT_4020) 1319 bits |= PLX_DMAMODE_WIDTH_32; 1320 else /* localspace0 bus is 16 bits wide */ 1321 bits |= PLX_DMAMODE_WIDTH_16; 1322 writel(bits, plx_iobase + PLX_REG_DMAMODE1); 1323 if (ao_cmd_is_supported(board)) 1324 writel(bits, plx_iobase + PLX_REG_DMAMODE0); 1325 1326 /* enable interrupts on plx 9080 */ 1327 devpriv->plx_intcsr_bits |= 1328 PLX_INTCSR_LSEABORTEN | PLX_INTCSR_LSEPARITYEN | PLX_INTCSR_PIEN | 1329 PLX_INTCSR_PLIEN | PLX_INTCSR_PABORTIEN | PLX_INTCSR_LIOEN | 1330 PLX_INTCSR_DMA0IEN | PLX_INTCSR_DMA1IEN; 1331 writel(devpriv->plx_intcsr_bits, 1332 devpriv->plx9080_iobase + PLX_REG_INTCSR); 1333 } 1334 1335 static void disable_ai_pacing(struct comedi_device *dev) 1336 { 1337 struct pcidas64_private *devpriv = dev->private; 1338 unsigned long flags; 1339 1340 disable_ai_interrupts(dev); 1341 1342 spin_lock_irqsave(&dev->spinlock, flags); 1343 devpriv->adc_control1_bits &= ~ADC_SW_GATE_BIT; 1344 writew(devpriv->adc_control1_bits, 1345 devpriv->main_iobase + ADC_CONTROL1_REG); 1346 spin_unlock_irqrestore(&dev->spinlock, flags); 1347 1348 /* disable pacing, triggering, etc */ 1349 writew(ADC_DMA_DISABLE_BIT | ADC_SOFT_GATE_BITS | ADC_GATE_LEVEL_BIT, 1350 devpriv->main_iobase + ADC_CONTROL0_REG); 1351 } 1352 1353 static int set_ai_fifo_segment_length(struct comedi_device *dev, 1354 unsigned int num_entries) 1355 { 1356 const struct pcidas64_board *board = dev->board_ptr; 1357 struct pcidas64_private *devpriv = dev->private; 1358 static const int increment_size = 0x100; 1359 const struct hw_fifo_info *const fifo = board->ai_fifo; 1360 unsigned int num_increments; 1361 u16 bits; 1362 1363 if (num_entries < increment_size) 1364 num_entries = increment_size; 1365 if (num_entries > fifo->max_segment_length) 1366 num_entries = fifo->max_segment_length; 1367 1368 /* 1 == 256 entries, 2 == 512 entries, etc */ 1369 num_increments = DIV_ROUND_CLOSEST(num_entries, increment_size); 1370 1371 bits = (~(num_increments - 1)) & fifo->fifo_size_reg_mask; 1372 devpriv->fifo_size_bits &= ~fifo->fifo_size_reg_mask; 1373 devpriv->fifo_size_bits |= bits; 1374 writew(devpriv->fifo_size_bits, 1375 devpriv->main_iobase + FIFO_SIZE_REG); 1376 1377 devpriv->ai_fifo_segment_length = num_increments * increment_size; 1378 1379 return devpriv->ai_fifo_segment_length; 1380 } 1381 1382 /* 1383 * adjusts the size of hardware fifo (which determines block size for dma xfers) 1384 */ 1385 static int set_ai_fifo_size(struct comedi_device *dev, unsigned int num_samples) 1386 { 1387 const struct pcidas64_board *board = dev->board_ptr; 1388 unsigned int num_fifo_entries; 1389 int retval; 1390 const struct hw_fifo_info *const fifo = board->ai_fifo; 1391 1392 num_fifo_entries = num_samples / fifo->sample_packing_ratio; 1393 1394 retval = set_ai_fifo_segment_length(dev, 1395 num_fifo_entries / 1396 fifo->num_segments); 1397 if (retval < 0) 1398 return retval; 1399 1400 return retval * fifo->num_segments * fifo->sample_packing_ratio; 1401 } 1402 1403 /* query length of fifo */ 1404 static unsigned int ai_fifo_size(struct comedi_device *dev) 1405 { 1406 const struct pcidas64_board *board = dev->board_ptr; 1407 struct pcidas64_private *devpriv = dev->private; 1408 1409 return devpriv->ai_fifo_segment_length * 1410 board->ai_fifo->num_segments * 1411 board->ai_fifo->sample_packing_ratio; 1412 } 1413 1414 static void init_stc_registers(struct comedi_device *dev) 1415 { 1416 const struct pcidas64_board *board = dev->board_ptr; 1417 struct pcidas64_private *devpriv = dev->private; 1418 u16 bits; 1419 unsigned long flags; 1420 1421 spin_lock_irqsave(&dev->spinlock, flags); 1422 1423 /* 1424 * bit should be set for 6025, 1425 * although docs say boards with <= 16 chans should be cleared XXX 1426 */ 1427 if (1) 1428 devpriv->adc_control1_bits |= ADC_QUEUE_CONFIG_BIT; 1429 writew(devpriv->adc_control1_bits, 1430 devpriv->main_iobase + ADC_CONTROL1_REG); 1431 1432 /* 6402/16 manual says this register must be initialized to 0xff? */ 1433 writew(0xff, devpriv->main_iobase + ADC_SAMPLE_INTERVAL_UPPER_REG); 1434 1435 bits = SLOW_DAC_BIT | DMA_CH_SELECT_BIT; 1436 if (board->layout == LAYOUT_4020) 1437 bits |= INTERNAL_CLOCK_4020_BITS; 1438 devpriv->hw_config_bits |= bits; 1439 writew(devpriv->hw_config_bits, 1440 devpriv->main_iobase + HW_CONFIG_REG); 1441 1442 writew(0, devpriv->main_iobase + DAQ_SYNC_REG); 1443 writew(0, devpriv->main_iobase + CALIBRATION_REG); 1444 1445 spin_unlock_irqrestore(&dev->spinlock, flags); 1446 1447 /* set fifos to maximum size */ 1448 devpriv->fifo_size_bits |= DAC_FIFO_BITS; 1449 set_ai_fifo_segment_length(dev, board->ai_fifo->max_segment_length); 1450 1451 devpriv->dac_control1_bits = DAC_OUTPUT_ENABLE_BIT; 1452 devpriv->intr_enable_bits = 1453 /* EN_DAC_INTR_SRC_BIT | DAC_INTR_QEMPTY_BITS | */ 1454 EN_DAC_DONE_INTR_BIT | EN_DAC_UNDERRUN_BIT; 1455 writew(devpriv->intr_enable_bits, 1456 devpriv->main_iobase + INTR_ENABLE_REG); 1457 1458 disable_ai_pacing(dev); 1459 }; 1460 1461 static int alloc_and_init_dma_members(struct comedi_device *dev) 1462 { 1463 const struct pcidas64_board *board = dev->board_ptr; 1464 struct pci_dev *pcidev = comedi_to_pci_dev(dev); 1465 struct pcidas64_private *devpriv = dev->private; 1466 int i; 1467 1468 /* allocate pci dma buffers */ 1469 for (i = 0; i < ai_dma_ring_count(board); i++) { 1470 devpriv->ai_buffer[i] = 1471 dma_alloc_coherent(&pcidev->dev, DMA_BUFFER_SIZE, 1472 &devpriv->ai_buffer_bus_addr[i], 1473 GFP_KERNEL); 1474 if (!devpriv->ai_buffer[i]) 1475 return -ENOMEM; 1476 } 1477 for (i = 0; i < AO_DMA_RING_COUNT; i++) { 1478 if (ao_cmd_is_supported(board)) { 1479 devpriv->ao_buffer[i] = 1480 dma_alloc_coherent(&pcidev->dev, 1481 DMA_BUFFER_SIZE, 1482 &devpriv->ao_buffer_bus_addr[i], 1483 GFP_KERNEL); 1484 if (!devpriv->ao_buffer[i]) 1485 return -ENOMEM; 1486 } 1487 } 1488 /* allocate dma descriptors */ 1489 devpriv->ai_dma_desc = 1490 dma_alloc_coherent(&pcidev->dev, sizeof(struct plx_dma_desc) * 1491 ai_dma_ring_count(board), 1492 &devpriv->ai_dma_desc_bus_addr, GFP_KERNEL); 1493 if (!devpriv->ai_dma_desc) 1494 return -ENOMEM; 1495 1496 if (ao_cmd_is_supported(board)) { 1497 devpriv->ao_dma_desc = 1498 dma_alloc_coherent(&pcidev->dev, 1499 sizeof(struct plx_dma_desc) * 1500 AO_DMA_RING_COUNT, 1501 &devpriv->ao_dma_desc_bus_addr, 1502 GFP_KERNEL); 1503 if (!devpriv->ao_dma_desc) 1504 return -ENOMEM; 1505 } 1506 /* initialize dma descriptors */ 1507 for (i = 0; i < ai_dma_ring_count(board); i++) { 1508 devpriv->ai_dma_desc[i].pci_start_addr = 1509 cpu_to_le32(devpriv->ai_buffer_bus_addr[i]); 1510 if (board->layout == LAYOUT_4020) 1511 devpriv->ai_dma_desc[i].local_start_addr = 1512 cpu_to_le32(devpriv->local1_iobase + 1513 ADC_FIFO_REG); 1514 else 1515 devpriv->ai_dma_desc[i].local_start_addr = 1516 cpu_to_le32(devpriv->local0_iobase + 1517 ADC_FIFO_REG); 1518 devpriv->ai_dma_desc[i].transfer_size = cpu_to_le32(0); 1519 devpriv->ai_dma_desc[i].next = 1520 cpu_to_le32((devpriv->ai_dma_desc_bus_addr + 1521 ((i + 1) % ai_dma_ring_count(board)) * 1522 sizeof(devpriv->ai_dma_desc[0])) | 1523 PLX_DMADPR_DESCPCI | PLX_DMADPR_TCINTR | 1524 PLX_DMADPR_XFERL2P); 1525 } 1526 if (ao_cmd_is_supported(board)) { 1527 for (i = 0; i < AO_DMA_RING_COUNT; i++) { 1528 devpriv->ao_dma_desc[i].pci_start_addr = 1529 cpu_to_le32(devpriv->ao_buffer_bus_addr[i]); 1530 devpriv->ao_dma_desc[i].local_start_addr = 1531 cpu_to_le32(devpriv->local0_iobase + 1532 DAC_FIFO_REG); 1533 devpriv->ao_dma_desc[i].transfer_size = cpu_to_le32(0); 1534 devpriv->ao_dma_desc[i].next = 1535 cpu_to_le32((devpriv->ao_dma_desc_bus_addr + 1536 ((i + 1) % (AO_DMA_RING_COUNT)) * 1537 sizeof(devpriv->ao_dma_desc[0])) | 1538 PLX_DMADPR_DESCPCI | 1539 PLX_DMADPR_TCINTR); 1540 } 1541 } 1542 return 0; 1543 } 1544 1545 static void cb_pcidas64_free_dma(struct comedi_device *dev) 1546 { 1547 const struct pcidas64_board *board = dev->board_ptr; 1548 struct pci_dev *pcidev = comedi_to_pci_dev(dev); 1549 struct pcidas64_private *devpriv = dev->private; 1550 int i; 1551 1552 if (!devpriv) 1553 return; 1554 1555 /* free pci dma buffers */ 1556 for (i = 0; i < ai_dma_ring_count(board); i++) { 1557 if (devpriv->ai_buffer[i]) 1558 dma_free_coherent(&pcidev->dev, 1559 DMA_BUFFER_SIZE, 1560 devpriv->ai_buffer[i], 1561 devpriv->ai_buffer_bus_addr[i]); 1562 } 1563 for (i = 0; i < AO_DMA_RING_COUNT; i++) { 1564 if (devpriv->ao_buffer[i]) 1565 dma_free_coherent(&pcidev->dev, 1566 DMA_BUFFER_SIZE, 1567 devpriv->ao_buffer[i], 1568 devpriv->ao_buffer_bus_addr[i]); 1569 } 1570 /* free dma descriptors */ 1571 if (devpriv->ai_dma_desc) 1572 dma_free_coherent(&pcidev->dev, 1573 sizeof(struct plx_dma_desc) * 1574 ai_dma_ring_count(board), 1575 devpriv->ai_dma_desc, 1576 devpriv->ai_dma_desc_bus_addr); 1577 if (devpriv->ao_dma_desc) 1578 dma_free_coherent(&pcidev->dev, 1579 sizeof(struct plx_dma_desc) * 1580 AO_DMA_RING_COUNT, 1581 devpriv->ao_dma_desc, 1582 devpriv->ao_dma_desc_bus_addr); 1583 } 1584 1585 static inline void warn_external_queue(struct comedi_device *dev) 1586 { 1587 dev_err(dev->class_dev, 1588 "AO command and AI external channel queue cannot be used simultaneously\n"); 1589 dev_err(dev->class_dev, 1590 "Use internal AI channel queue (channels must be consecutive and use same range/aref)\n"); 1591 } 1592 1593 /* 1594 * their i2c requires a huge delay on setting clock or data high for some reason 1595 */ 1596 static const int i2c_high_udelay = 1000; 1597 static const int i2c_low_udelay = 10; 1598 1599 /* set i2c data line high or low */ 1600 static void i2c_set_sda(struct comedi_device *dev, int state) 1601 { 1602 struct pcidas64_private *devpriv = dev->private; 1603 static const int data_bit = PLX_CNTRL_EEWB; 1604 void __iomem *plx_control_addr = devpriv->plx9080_iobase + 1605 PLX_REG_CNTRL; 1606 1607 if (state) { /* set data line high */ 1608 devpriv->plx_control_bits &= ~data_bit; 1609 writel(devpriv->plx_control_bits, plx_control_addr); 1610 udelay(i2c_high_udelay); 1611 } else { /* set data line low */ 1612 devpriv->plx_control_bits |= data_bit; 1613 writel(devpriv->plx_control_bits, plx_control_addr); 1614 udelay(i2c_low_udelay); 1615 } 1616 } 1617 1618 /* set i2c clock line high or low */ 1619 static void i2c_set_scl(struct comedi_device *dev, int state) 1620 { 1621 struct pcidas64_private *devpriv = dev->private; 1622 static const int clock_bit = PLX_CNTRL_USERO; 1623 void __iomem *plx_control_addr = devpriv->plx9080_iobase + 1624 PLX_REG_CNTRL; 1625 1626 if (state) { /* set clock line high */ 1627 devpriv->plx_control_bits &= ~clock_bit; 1628 writel(devpriv->plx_control_bits, plx_control_addr); 1629 udelay(i2c_high_udelay); 1630 } else { /* set clock line low */ 1631 devpriv->plx_control_bits |= clock_bit; 1632 writel(devpriv->plx_control_bits, plx_control_addr); 1633 udelay(i2c_low_udelay); 1634 } 1635 } 1636 1637 static void i2c_write_byte(struct comedi_device *dev, u8 byte) 1638 { 1639 u8 bit; 1640 unsigned int num_bits = 8; 1641 1642 for (bit = 1 << (num_bits - 1); bit; bit >>= 1) { 1643 i2c_set_scl(dev, 0); 1644 if ((byte & bit)) 1645 i2c_set_sda(dev, 1); 1646 else 1647 i2c_set_sda(dev, 0); 1648 i2c_set_scl(dev, 1); 1649 } 1650 } 1651 1652 /* we can't really read the lines, so fake it */ 1653 static int i2c_read_ack(struct comedi_device *dev) 1654 { 1655 i2c_set_scl(dev, 0); 1656 i2c_set_sda(dev, 1); 1657 i2c_set_scl(dev, 1); 1658 1659 return 0; /* return fake acknowledge bit */ 1660 } 1661 1662 /* send start bit */ 1663 static void i2c_start(struct comedi_device *dev) 1664 { 1665 i2c_set_scl(dev, 1); 1666 i2c_set_sda(dev, 1); 1667 i2c_set_sda(dev, 0); 1668 } 1669 1670 /* send stop bit */ 1671 static void i2c_stop(struct comedi_device *dev) 1672 { 1673 i2c_set_scl(dev, 0); 1674 i2c_set_sda(dev, 0); 1675 i2c_set_scl(dev, 1); 1676 i2c_set_sda(dev, 1); 1677 } 1678 1679 static void i2c_write(struct comedi_device *dev, unsigned int address, 1680 const u8 *data, unsigned int length) 1681 { 1682 struct pcidas64_private *devpriv = dev->private; 1683 unsigned int i; 1684 u8 bitstream; 1685 static const int read_bit = 0x1; 1686 1687 /* 1688 * XXX need mutex to prevent simultaneous attempts to access 1689 * eeprom and i2c bus 1690 */ 1691 1692 /* make sure we don't send anything to eeprom */ 1693 devpriv->plx_control_bits &= ~PLX_CNTRL_EECS; 1694 1695 i2c_stop(dev); 1696 i2c_start(dev); 1697 1698 /* send address and write bit */ 1699 bitstream = (address << 1) & ~read_bit; 1700 i2c_write_byte(dev, bitstream); 1701 1702 /* get acknowledge */ 1703 if (i2c_read_ack(dev) != 0) { 1704 dev_err(dev->class_dev, "failed: no acknowledge\n"); 1705 i2c_stop(dev); 1706 return; 1707 } 1708 /* write data bytes */ 1709 for (i = 0; i < length; i++) { 1710 i2c_write_byte(dev, data[i]); 1711 if (i2c_read_ack(dev) != 0) { 1712 dev_err(dev->class_dev, "failed: no acknowledge\n"); 1713 i2c_stop(dev); 1714 return; 1715 } 1716 } 1717 i2c_stop(dev); 1718 } 1719 1720 static int cb_pcidas64_ai_eoc(struct comedi_device *dev, 1721 struct comedi_subdevice *s, 1722 struct comedi_insn *insn, 1723 unsigned long context) 1724 { 1725 const struct pcidas64_board *board = dev->board_ptr; 1726 struct pcidas64_private *devpriv = dev->private; 1727 unsigned int status; 1728 1729 status = readw(devpriv->main_iobase + HW_STATUS_REG); 1730 if (board->layout == LAYOUT_4020) { 1731 status = readw(devpriv->main_iobase + ADC_WRITE_PNTR_REG); 1732 if (status) 1733 return 0; 1734 } else { 1735 if (pipe_full_bits(status)) 1736 return 0; 1737 } 1738 return -EBUSY; 1739 } 1740 1741 static int ai_rinsn(struct comedi_device *dev, struct comedi_subdevice *s, 1742 struct comedi_insn *insn, unsigned int *data) 1743 { 1744 const struct pcidas64_board *board = dev->board_ptr; 1745 struct pcidas64_private *devpriv = dev->private; 1746 unsigned int bits = 0, n; 1747 unsigned int channel, range, aref; 1748 unsigned long flags; 1749 int ret; 1750 1751 channel = CR_CHAN(insn->chanspec); 1752 range = CR_RANGE(insn->chanspec); 1753 aref = CR_AREF(insn->chanspec); 1754 1755 /* disable card's analog input interrupt sources and pacing */ 1756 /* 4020 generates dac done interrupts even though they are disabled */ 1757 disable_ai_pacing(dev); 1758 1759 spin_lock_irqsave(&dev->spinlock, flags); 1760 if (insn->chanspec & CR_ALT_FILTER) 1761 devpriv->adc_control1_bits |= ADC_DITHER_BIT; 1762 else 1763 devpriv->adc_control1_bits &= ~ADC_DITHER_BIT; 1764 writew(devpriv->adc_control1_bits, 1765 devpriv->main_iobase + ADC_CONTROL1_REG); 1766 spin_unlock_irqrestore(&dev->spinlock, flags); 1767 1768 if (board->layout != LAYOUT_4020) { 1769 /* use internal queue */ 1770 devpriv->hw_config_bits &= ~EXT_QUEUE_BIT; 1771 writew(devpriv->hw_config_bits, 1772 devpriv->main_iobase + HW_CONFIG_REG); 1773 1774 /* ALT_SOURCE is internal calibration reference */ 1775 if (insn->chanspec & CR_ALT_SOURCE) { 1776 unsigned int cal_en_bit; 1777 1778 if (board->layout == LAYOUT_60XX) 1779 cal_en_bit = CAL_EN_60XX_BIT; 1780 else 1781 cal_en_bit = CAL_EN_64XX_BIT; 1782 /* 1783 * select internal reference source to connect 1784 * to channel 0 1785 */ 1786 writew(cal_en_bit | 1787 adc_src_bits(devpriv->calibration_source), 1788 devpriv->main_iobase + CALIBRATION_REG); 1789 } else { 1790 /* 1791 * make sure internal calibration source 1792 * is turned off 1793 */ 1794 writew(0, devpriv->main_iobase + CALIBRATION_REG); 1795 } 1796 /* load internal queue */ 1797 bits = 0; 1798 /* set gain */ 1799 bits |= ai_range_bits_6xxx(dev, CR_RANGE(insn->chanspec)); 1800 /* set single-ended / differential */ 1801 bits |= se_diff_bit_6xxx(dev, aref == AREF_DIFF); 1802 if (aref == AREF_COMMON) 1803 bits |= ADC_COMMON_BIT; 1804 bits |= adc_chan_bits(channel); 1805 /* set stop channel */ 1806 writew(adc_chan_bits(channel), 1807 devpriv->main_iobase + ADC_QUEUE_HIGH_REG); 1808 /* set start channel, and rest of settings */ 1809 writew(bits, devpriv->main_iobase + ADC_QUEUE_LOAD_REG); 1810 } else { 1811 u8 old_cal_range_bits = devpriv->i2c_cal_range_bits; 1812 1813 devpriv->i2c_cal_range_bits &= ~ADC_SRC_4020_MASK; 1814 if (insn->chanspec & CR_ALT_SOURCE) { 1815 devpriv->i2c_cal_range_bits |= 1816 adc_src_4020_bits(devpriv->calibration_source); 1817 } else { /* select BNC inputs */ 1818 devpriv->i2c_cal_range_bits |= adc_src_4020_bits(4); 1819 } 1820 /* select range */ 1821 if (range == 0) 1822 devpriv->i2c_cal_range_bits |= attenuate_bit(channel); 1823 else 1824 devpriv->i2c_cal_range_bits &= ~attenuate_bit(channel); 1825 /* 1826 * update calibration/range i2c register only if necessary, 1827 * as it is very slow 1828 */ 1829 if (old_cal_range_bits != devpriv->i2c_cal_range_bits) { 1830 u8 i2c_data = devpriv->i2c_cal_range_bits; 1831 1832 i2c_write(dev, RANGE_CAL_I2C_ADDR, &i2c_data, 1833 sizeof(i2c_data)); 1834 } 1835 1836 /* 1837 * 4020 manual asks that sample interval register to be set 1838 * before writing to convert register. 1839 * Using somewhat arbitrary setting of 4 master clock ticks 1840 * = 0.1 usec 1841 */ 1842 writew(0, devpriv->main_iobase + ADC_SAMPLE_INTERVAL_UPPER_REG); 1843 writew(2, devpriv->main_iobase + ADC_SAMPLE_INTERVAL_LOWER_REG); 1844 } 1845 1846 for (n = 0; n < insn->n; n++) { 1847 /* clear adc buffer (inside loop for 4020 sake) */ 1848 writew(0, devpriv->main_iobase + ADC_BUFFER_CLEAR_REG); 1849 1850 /* trigger conversion, bits sent only matter for 4020 */ 1851 writew(adc_convert_chan_4020_bits(CR_CHAN(insn->chanspec)), 1852 devpriv->main_iobase + ADC_CONVERT_REG); 1853 1854 /* wait for data */ 1855 ret = comedi_timeout(dev, s, insn, cb_pcidas64_ai_eoc, 0); 1856 if (ret) 1857 return ret; 1858 1859 if (board->layout == LAYOUT_4020) 1860 data[n] = readl(dev->mmio + ADC_FIFO_REG) & 0xffff; 1861 else 1862 data[n] = readw(devpriv->main_iobase + PIPE1_READ_REG); 1863 } 1864 1865 return n; 1866 } 1867 1868 static int ai_config_calibration_source(struct comedi_device *dev, 1869 unsigned int *data) 1870 { 1871 const struct pcidas64_board *board = dev->board_ptr; 1872 struct pcidas64_private *devpriv = dev->private; 1873 unsigned int source = data[1]; 1874 int num_calibration_sources; 1875 1876 if (board->layout == LAYOUT_60XX) 1877 num_calibration_sources = 16; 1878 else 1879 num_calibration_sources = 8; 1880 if (source >= num_calibration_sources) { 1881 dev_dbg(dev->class_dev, "invalid calibration source: %i\n", 1882 source); 1883 return -EINVAL; 1884 } 1885 1886 devpriv->calibration_source = source; 1887 1888 return 2; 1889 } 1890 1891 static int ai_config_block_size(struct comedi_device *dev, unsigned int *data) 1892 { 1893 const struct pcidas64_board *board = dev->board_ptr; 1894 int fifo_size; 1895 const struct hw_fifo_info *const fifo = board->ai_fifo; 1896 unsigned int block_size, requested_block_size; 1897 int retval; 1898 1899 requested_block_size = data[1]; 1900 1901 if (requested_block_size) { 1902 fifo_size = requested_block_size * fifo->num_segments / 1903 bytes_in_sample; 1904 1905 retval = set_ai_fifo_size(dev, fifo_size); 1906 if (retval < 0) 1907 return retval; 1908 } 1909 1910 block_size = ai_fifo_size(dev) / fifo->num_segments * bytes_in_sample; 1911 1912 data[1] = block_size; 1913 1914 return 2; 1915 } 1916 1917 static int ai_config_master_clock_4020(struct comedi_device *dev, 1918 unsigned int *data) 1919 { 1920 struct pcidas64_private *devpriv = dev->private; 1921 unsigned int divisor = data[4]; 1922 int retval = 0; 1923 1924 if (divisor < 2) { 1925 divisor = 2; 1926 retval = -EAGAIN; 1927 } 1928 1929 switch (data[1]) { 1930 case COMEDI_EV_SCAN_BEGIN: 1931 devpriv->ext_clock.divisor = divisor; 1932 devpriv->ext_clock.chanspec = data[2]; 1933 break; 1934 default: 1935 return -EINVAL; 1936 } 1937 1938 data[4] = divisor; 1939 1940 return retval ? retval : 5; 1941 } 1942 1943 /* XXX could add support for 60xx series */ 1944 static int ai_config_master_clock(struct comedi_device *dev, unsigned int *data) 1945 { 1946 const struct pcidas64_board *board = dev->board_ptr; 1947 1948 switch (board->layout) { 1949 case LAYOUT_4020: 1950 return ai_config_master_clock_4020(dev, data); 1951 default: 1952 return -EINVAL; 1953 } 1954 1955 return -EINVAL; 1956 } 1957 1958 static int ai_config_insn(struct comedi_device *dev, struct comedi_subdevice *s, 1959 struct comedi_insn *insn, unsigned int *data) 1960 { 1961 int id = data[0]; 1962 1963 switch (id) { 1964 case INSN_CONFIG_ALT_SOURCE: 1965 return ai_config_calibration_source(dev, data); 1966 case INSN_CONFIG_BLOCK_SIZE: 1967 return ai_config_block_size(dev, data); 1968 case INSN_CONFIG_TIMER_1: 1969 return ai_config_master_clock(dev, data); 1970 default: 1971 return -EINVAL; 1972 } 1973 return -EINVAL; 1974 } 1975 1976 /* 1977 * Gets nearest achievable timing given master clock speed, does not 1978 * take into account possible minimum/maximum divisor values. Used 1979 * by other timing checking functions. 1980 */ 1981 static unsigned int get_divisor(unsigned int ns, unsigned int flags) 1982 { 1983 unsigned int divisor; 1984 1985 switch (flags & CMDF_ROUND_MASK) { 1986 case CMDF_ROUND_UP: 1987 divisor = DIV_ROUND_UP(ns, TIMER_BASE); 1988 break; 1989 case CMDF_ROUND_DOWN: 1990 divisor = ns / TIMER_BASE; 1991 break; 1992 case CMDF_ROUND_NEAREST: 1993 default: 1994 divisor = DIV_ROUND_CLOSEST(ns, TIMER_BASE); 1995 break; 1996 } 1997 return divisor; 1998 } 1999 2000 /* 2001 * utility function that rounds desired timing to an achievable time, and 2002 * sets cmd members appropriately. 2003 * adc paces conversions from master clock by dividing by (x + 3) where x is 2004 * 24 bit number 2005 */ 2006 static void check_adc_timing(struct comedi_device *dev, struct comedi_cmd *cmd) 2007 { 2008 const struct pcidas64_board *board = dev->board_ptr; 2009 unsigned long long convert_divisor = 0; 2010 unsigned int scan_divisor; 2011 static const int min_convert_divisor = 3; 2012 static const int max_convert_divisor = 2013 max_counter_value + min_convert_divisor; 2014 static const int min_scan_divisor_4020 = 2; 2015 unsigned long long max_scan_divisor, min_scan_divisor; 2016 2017 if (cmd->convert_src == TRIG_TIMER) { 2018 if (board->layout == LAYOUT_4020) { 2019 cmd->convert_arg = 0; 2020 } else { 2021 convert_divisor = get_divisor(cmd->convert_arg, 2022 cmd->flags); 2023 if (convert_divisor > max_convert_divisor) 2024 convert_divisor = max_convert_divisor; 2025 if (convert_divisor < min_convert_divisor) 2026 convert_divisor = min_convert_divisor; 2027 cmd->convert_arg = convert_divisor * TIMER_BASE; 2028 } 2029 } else if (cmd->convert_src == TRIG_NOW) { 2030 cmd->convert_arg = 0; 2031 } 2032 2033 if (cmd->scan_begin_src == TRIG_TIMER) { 2034 scan_divisor = get_divisor(cmd->scan_begin_arg, cmd->flags); 2035 if (cmd->convert_src == TRIG_TIMER) { 2036 min_scan_divisor = convert_divisor * cmd->chanlist_len; 2037 max_scan_divisor = 2038 (convert_divisor * cmd->chanlist_len - 1) + 2039 max_counter_value; 2040 } else { 2041 min_scan_divisor = min_scan_divisor_4020; 2042 max_scan_divisor = max_counter_value + min_scan_divisor; 2043 } 2044 if (scan_divisor > max_scan_divisor) 2045 scan_divisor = max_scan_divisor; 2046 if (scan_divisor < min_scan_divisor) 2047 scan_divisor = min_scan_divisor; 2048 cmd->scan_begin_arg = scan_divisor * TIMER_BASE; 2049 } 2050 } 2051 2052 static int cb_pcidas64_ai_check_chanlist(struct comedi_device *dev, 2053 struct comedi_subdevice *s, 2054 struct comedi_cmd *cmd) 2055 { 2056 const struct pcidas64_board *board = dev->board_ptr; 2057 unsigned int aref0 = CR_AREF(cmd->chanlist[0]); 2058 int i; 2059 2060 for (i = 1; i < cmd->chanlist_len; i++) { 2061 unsigned int aref = CR_AREF(cmd->chanlist[i]); 2062 2063 if (aref != aref0) { 2064 dev_dbg(dev->class_dev, 2065 "all elements in chanlist must use the same analog reference\n"); 2066 return -EINVAL; 2067 } 2068 } 2069 2070 if (board->layout == LAYOUT_4020) { 2071 unsigned int chan0 = CR_CHAN(cmd->chanlist[0]); 2072 2073 for (i = 1; i < cmd->chanlist_len; i++) { 2074 unsigned int chan = CR_CHAN(cmd->chanlist[i]); 2075 2076 if (chan != (chan0 + i)) { 2077 dev_dbg(dev->class_dev, 2078 "chanlist must use consecutive channels\n"); 2079 return -EINVAL; 2080 } 2081 } 2082 if (cmd->chanlist_len == 3) { 2083 dev_dbg(dev->class_dev, 2084 "chanlist cannot be 3 channels long, use 1, 2, or 4 channels\n"); 2085 return -EINVAL; 2086 } 2087 } 2088 2089 return 0; 2090 } 2091 2092 static int ai_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s, 2093 struct comedi_cmd *cmd) 2094 { 2095 const struct pcidas64_board *board = dev->board_ptr; 2096 int err = 0; 2097 unsigned int tmp_arg, tmp_arg2; 2098 unsigned int triggers; 2099 2100 /* Step 1 : check if triggers are trivially valid */ 2101 2102 err |= comedi_check_trigger_src(&cmd->start_src, TRIG_NOW | TRIG_EXT); 2103 2104 triggers = TRIG_TIMER; 2105 if (board->layout == LAYOUT_4020) 2106 triggers |= TRIG_OTHER; 2107 else 2108 triggers |= TRIG_FOLLOW; 2109 err |= comedi_check_trigger_src(&cmd->scan_begin_src, triggers); 2110 2111 triggers = TRIG_TIMER; 2112 if (board->layout == LAYOUT_4020) 2113 triggers |= TRIG_NOW; 2114 else 2115 triggers |= TRIG_EXT; 2116 err |= comedi_check_trigger_src(&cmd->convert_src, triggers); 2117 err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT); 2118 err |= comedi_check_trigger_src(&cmd->stop_src, 2119 TRIG_COUNT | TRIG_EXT | TRIG_NONE); 2120 2121 if (err) 2122 return 1; 2123 2124 /* Step 2a : make sure trigger sources are unique */ 2125 2126 err |= comedi_check_trigger_is_unique(cmd->start_src); 2127 err |= comedi_check_trigger_is_unique(cmd->scan_begin_src); 2128 err |= comedi_check_trigger_is_unique(cmd->convert_src); 2129 err |= comedi_check_trigger_is_unique(cmd->stop_src); 2130 2131 /* Step 2b : and mutually compatible */ 2132 2133 if (cmd->convert_src == TRIG_EXT && cmd->scan_begin_src == TRIG_TIMER) 2134 err |= -EINVAL; 2135 2136 if (err) 2137 return 2; 2138 2139 /* Step 3: check if arguments are trivially valid */ 2140 2141 switch (cmd->start_src) { 2142 case TRIG_NOW: 2143 err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0); 2144 break; 2145 case TRIG_EXT: 2146 /* 2147 * start_arg is the CR_CHAN | CR_INVERT of the 2148 * external trigger. 2149 */ 2150 break; 2151 } 2152 2153 if (cmd->convert_src == TRIG_TIMER) { 2154 if (board->layout == LAYOUT_4020) { 2155 err |= comedi_check_trigger_arg_is(&cmd->convert_arg, 2156 0); 2157 } else { 2158 err |= comedi_check_trigger_arg_min(&cmd->convert_arg, 2159 board->ai_speed); 2160 /* 2161 * if scans are timed faster than conversion rate 2162 * allows 2163 */ 2164 if (cmd->scan_begin_src == TRIG_TIMER) { 2165 err |= comedi_check_trigger_arg_min( 2166 &cmd->scan_begin_arg, 2167 cmd->convert_arg * 2168 cmd->chanlist_len); 2169 } 2170 } 2171 } 2172 2173 err |= comedi_check_trigger_arg_min(&cmd->chanlist_len, 1); 2174 err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg, 2175 cmd->chanlist_len); 2176 2177 switch (cmd->stop_src) { 2178 case TRIG_EXT: 2179 break; 2180 case TRIG_COUNT: 2181 err |= comedi_check_trigger_arg_min(&cmd->stop_arg, 1); 2182 break; 2183 case TRIG_NONE: 2184 err |= comedi_check_trigger_arg_is(&cmd->stop_arg, 0); 2185 break; 2186 default: 2187 break; 2188 } 2189 2190 if (err) 2191 return 3; 2192 2193 /* step 4: fix up any arguments */ 2194 2195 if (cmd->convert_src == TRIG_TIMER) { 2196 tmp_arg = cmd->convert_arg; 2197 tmp_arg2 = cmd->scan_begin_arg; 2198 check_adc_timing(dev, cmd); 2199 if (tmp_arg != cmd->convert_arg) 2200 err++; 2201 if (tmp_arg2 != cmd->scan_begin_arg) 2202 err++; 2203 } 2204 2205 if (err) 2206 return 4; 2207 2208 /* Step 5: check channel list if it exists */ 2209 if (cmd->chanlist && cmd->chanlist_len > 0) 2210 err |= cb_pcidas64_ai_check_chanlist(dev, s, cmd); 2211 2212 if (err) 2213 return 5; 2214 2215 return 0; 2216 } 2217 2218 static int use_hw_sample_counter(struct comedi_cmd *cmd) 2219 { 2220 /* disable for now until I work out a race */ 2221 return 0; 2222 2223 if (cmd->stop_src == TRIG_COUNT && cmd->stop_arg <= max_counter_value) 2224 return 1; 2225 2226 return 0; 2227 } 2228 2229 static void setup_sample_counters(struct comedi_device *dev, 2230 struct comedi_cmd *cmd) 2231 { 2232 struct pcidas64_private *devpriv = dev->private; 2233 2234 /* load hardware conversion counter */ 2235 if (use_hw_sample_counter(cmd)) { 2236 writew(cmd->stop_arg & 0xffff, 2237 devpriv->main_iobase + ADC_COUNT_LOWER_REG); 2238 writew((cmd->stop_arg >> 16) & 0xff, 2239 devpriv->main_iobase + ADC_COUNT_UPPER_REG); 2240 } else { 2241 writew(1, devpriv->main_iobase + ADC_COUNT_LOWER_REG); 2242 } 2243 } 2244 2245 static inline unsigned int dma_transfer_size(struct comedi_device *dev) 2246 { 2247 const struct pcidas64_board *board = dev->board_ptr; 2248 struct pcidas64_private *devpriv = dev->private; 2249 unsigned int num_samples; 2250 2251 num_samples = devpriv->ai_fifo_segment_length * 2252 board->ai_fifo->sample_packing_ratio; 2253 if (num_samples > DMA_BUFFER_SIZE / sizeof(u16)) 2254 num_samples = DMA_BUFFER_SIZE / sizeof(u16); 2255 2256 return num_samples; 2257 } 2258 2259 static u32 ai_convert_counter_6xxx(const struct comedi_device *dev, 2260 const struct comedi_cmd *cmd) 2261 { 2262 /* supposed to load counter with desired divisor minus 3 */ 2263 return cmd->convert_arg / TIMER_BASE - 3; 2264 } 2265 2266 static u32 ai_scan_counter_6xxx(struct comedi_device *dev, 2267 struct comedi_cmd *cmd) 2268 { 2269 u32 count; 2270 2271 /* figure out how long we need to delay at end of scan */ 2272 switch (cmd->scan_begin_src) { 2273 case TRIG_TIMER: 2274 count = (cmd->scan_begin_arg - 2275 (cmd->convert_arg * (cmd->chanlist_len - 1))) / 2276 TIMER_BASE; 2277 break; 2278 case TRIG_FOLLOW: 2279 count = cmd->convert_arg / TIMER_BASE; 2280 break; 2281 default: 2282 return 0; 2283 } 2284 return count - 3; 2285 } 2286 2287 static u32 ai_convert_counter_4020(struct comedi_device *dev, 2288 struct comedi_cmd *cmd) 2289 { 2290 struct pcidas64_private *devpriv = dev->private; 2291 unsigned int divisor; 2292 2293 switch (cmd->scan_begin_src) { 2294 case TRIG_TIMER: 2295 divisor = cmd->scan_begin_arg / TIMER_BASE; 2296 break; 2297 case TRIG_OTHER: 2298 divisor = devpriv->ext_clock.divisor; 2299 break; 2300 default: /* should never happen */ 2301 dev_err(dev->class_dev, "bug! failed to set ai pacing!\n"); 2302 divisor = 1000; 2303 break; 2304 } 2305 2306 /* supposed to load counter with desired divisor minus 2 for 4020 */ 2307 return divisor - 2; 2308 } 2309 2310 static void select_master_clock_4020(struct comedi_device *dev, 2311 const struct comedi_cmd *cmd) 2312 { 2313 struct pcidas64_private *devpriv = dev->private; 2314 2315 /* select internal/external master clock */ 2316 devpriv->hw_config_bits &= ~MASTER_CLOCK_4020_MASK; 2317 if (cmd->scan_begin_src == TRIG_OTHER) { 2318 int chanspec = devpriv->ext_clock.chanspec; 2319 2320 if (CR_CHAN(chanspec)) 2321 devpriv->hw_config_bits |= BNC_CLOCK_4020_BITS; 2322 else 2323 devpriv->hw_config_bits |= EXT_CLOCK_4020_BITS; 2324 } else { 2325 devpriv->hw_config_bits |= INTERNAL_CLOCK_4020_BITS; 2326 } 2327 writew(devpriv->hw_config_bits, 2328 devpriv->main_iobase + HW_CONFIG_REG); 2329 } 2330 2331 static void select_master_clock(struct comedi_device *dev, 2332 const struct comedi_cmd *cmd) 2333 { 2334 const struct pcidas64_board *board = dev->board_ptr; 2335 2336 switch (board->layout) { 2337 case LAYOUT_4020: 2338 select_master_clock_4020(dev, cmd); 2339 break; 2340 default: 2341 break; 2342 } 2343 } 2344 2345 static inline void dma_start_sync(struct comedi_device *dev, 2346 unsigned int channel) 2347 { 2348 struct pcidas64_private *devpriv = dev->private; 2349 unsigned long flags; 2350 2351 /* spinlock for plx dma control/status reg */ 2352 spin_lock_irqsave(&dev->spinlock, flags); 2353 writeb(PLX_DMACSR_ENABLE | PLX_DMACSR_START | PLX_DMACSR_CLEARINTR, 2354 devpriv->plx9080_iobase + PLX_REG_DMACSR(channel)); 2355 spin_unlock_irqrestore(&dev->spinlock, flags); 2356 } 2357 2358 static void set_ai_pacing(struct comedi_device *dev, struct comedi_cmd *cmd) 2359 { 2360 const struct pcidas64_board *board = dev->board_ptr; 2361 struct pcidas64_private *devpriv = dev->private; 2362 u32 convert_counter = 0, scan_counter = 0; 2363 2364 check_adc_timing(dev, cmd); 2365 2366 select_master_clock(dev, cmd); 2367 2368 if (board->layout == LAYOUT_4020) { 2369 convert_counter = ai_convert_counter_4020(dev, cmd); 2370 } else { 2371 convert_counter = ai_convert_counter_6xxx(dev, cmd); 2372 scan_counter = ai_scan_counter_6xxx(dev, cmd); 2373 } 2374 2375 /* load lower 16 bits of convert interval */ 2376 writew(convert_counter & 0xffff, 2377 devpriv->main_iobase + ADC_SAMPLE_INTERVAL_LOWER_REG); 2378 /* load upper 8 bits of convert interval */ 2379 writew((convert_counter >> 16) & 0xff, 2380 devpriv->main_iobase + ADC_SAMPLE_INTERVAL_UPPER_REG); 2381 /* load lower 16 bits of scan delay */ 2382 writew(scan_counter & 0xffff, 2383 devpriv->main_iobase + ADC_DELAY_INTERVAL_LOWER_REG); 2384 /* load upper 8 bits of scan delay */ 2385 writew((scan_counter >> 16) & 0xff, 2386 devpriv->main_iobase + ADC_DELAY_INTERVAL_UPPER_REG); 2387 } 2388 2389 static int use_internal_queue_6xxx(const struct comedi_cmd *cmd) 2390 { 2391 int i; 2392 2393 for (i = 0; i + 1 < cmd->chanlist_len; i++) { 2394 if (CR_CHAN(cmd->chanlist[i + 1]) != 2395 CR_CHAN(cmd->chanlist[i]) + 1) 2396 return 0; 2397 if (CR_RANGE(cmd->chanlist[i + 1]) != 2398 CR_RANGE(cmd->chanlist[i])) 2399 return 0; 2400 if (CR_AREF(cmd->chanlist[i + 1]) != CR_AREF(cmd->chanlist[i])) 2401 return 0; 2402 } 2403 return 1; 2404 } 2405 2406 static int setup_channel_queue(struct comedi_device *dev, 2407 const struct comedi_cmd *cmd) 2408 { 2409 const struct pcidas64_board *board = dev->board_ptr; 2410 struct pcidas64_private *devpriv = dev->private; 2411 unsigned short bits; 2412 int i; 2413 2414 if (board->layout != LAYOUT_4020) { 2415 if (use_internal_queue_6xxx(cmd)) { 2416 devpriv->hw_config_bits &= ~EXT_QUEUE_BIT; 2417 writew(devpriv->hw_config_bits, 2418 devpriv->main_iobase + HW_CONFIG_REG); 2419 bits = 0; 2420 /* set channel */ 2421 bits |= adc_chan_bits(CR_CHAN(cmd->chanlist[0])); 2422 /* set gain */ 2423 bits |= ai_range_bits_6xxx(dev, 2424 CR_RANGE(cmd->chanlist[0])); 2425 /* set single-ended / differential */ 2426 bits |= se_diff_bit_6xxx(dev, 2427 CR_AREF(cmd->chanlist[0]) == 2428 AREF_DIFF); 2429 if (CR_AREF(cmd->chanlist[0]) == AREF_COMMON) 2430 bits |= ADC_COMMON_BIT; 2431 /* set stop channel */ 2432 writew(adc_chan_bits 2433 (CR_CHAN(cmd->chanlist[cmd->chanlist_len - 1])), 2434 devpriv->main_iobase + ADC_QUEUE_HIGH_REG); 2435 /* set start channel, and rest of settings */ 2436 writew(bits, 2437 devpriv->main_iobase + ADC_QUEUE_LOAD_REG); 2438 } else { 2439 /* use external queue */ 2440 if (dev->write_subdev && dev->write_subdev->busy) { 2441 warn_external_queue(dev); 2442 return -EBUSY; 2443 } 2444 devpriv->hw_config_bits |= EXT_QUEUE_BIT; 2445 writew(devpriv->hw_config_bits, 2446 devpriv->main_iobase + HW_CONFIG_REG); 2447 /* clear DAC buffer to prevent weird interactions */ 2448 writew(0, 2449 devpriv->main_iobase + DAC_BUFFER_CLEAR_REG); 2450 /* clear queue pointer */ 2451 writew(0, devpriv->main_iobase + ADC_QUEUE_CLEAR_REG); 2452 /* load external queue */ 2453 for (i = 0; i < cmd->chanlist_len; i++) { 2454 unsigned int chanspec = cmd->chanlist[i]; 2455 int use_differential; 2456 2457 bits = 0; 2458 /* set channel */ 2459 bits |= adc_chan_bits(CR_CHAN(chanspec)); 2460 /* set gain */ 2461 bits |= ai_range_bits_6xxx(dev, 2462 CR_RANGE(chanspec)); 2463 /* set single-ended / differential */ 2464 use_differential = 0; 2465 if (CR_AREF(chanspec) == AREF_DIFF) 2466 use_differential = 1; 2467 bits |= se_diff_bit_6xxx(dev, use_differential); 2468 2469 if (CR_AREF(cmd->chanlist[i]) == AREF_COMMON) 2470 bits |= ADC_COMMON_BIT; 2471 /* mark end of queue */ 2472 if (i == cmd->chanlist_len - 1) 2473 bits |= QUEUE_EOSCAN_BIT | 2474 QUEUE_EOSEQ_BIT; 2475 writew(bits, 2476 devpriv->main_iobase + 2477 ADC_QUEUE_FIFO_REG); 2478 } 2479 /* 2480 * doing a queue clear is not specified in board docs, 2481 * but required for reliable operation 2482 */ 2483 writew(0, devpriv->main_iobase + ADC_QUEUE_CLEAR_REG); 2484 /* prime queue holding register */ 2485 writew(0, devpriv->main_iobase + ADC_QUEUE_LOAD_REG); 2486 } 2487 } else { 2488 unsigned short old_cal_range_bits = devpriv->i2c_cal_range_bits; 2489 2490 devpriv->i2c_cal_range_bits &= ~ADC_SRC_4020_MASK; 2491 /* select BNC inputs */ 2492 devpriv->i2c_cal_range_bits |= adc_src_4020_bits(4); 2493 /* select ranges */ 2494 for (i = 0; i < cmd->chanlist_len; i++) { 2495 unsigned int channel = CR_CHAN(cmd->chanlist[i]); 2496 unsigned int range = CR_RANGE(cmd->chanlist[i]); 2497 2498 if (range == 0) 2499 devpriv->i2c_cal_range_bits |= 2500 attenuate_bit(channel); 2501 else 2502 devpriv->i2c_cal_range_bits &= 2503 ~attenuate_bit(channel); 2504 } 2505 /* 2506 * update calibration/range i2c register only if necessary, 2507 * as it is very slow 2508 */ 2509 if (old_cal_range_bits != devpriv->i2c_cal_range_bits) { 2510 u8 i2c_data = devpriv->i2c_cal_range_bits; 2511 2512 i2c_write(dev, RANGE_CAL_I2C_ADDR, &i2c_data, 2513 sizeof(i2c_data)); 2514 } 2515 } 2516 return 0; 2517 } 2518 2519 static inline void load_first_dma_descriptor(struct comedi_device *dev, 2520 unsigned int dma_channel, 2521 unsigned int descriptor_bits) 2522 { 2523 struct pcidas64_private *devpriv = dev->private; 2524 2525 /* 2526 * The transfer size, pci address, and local address registers 2527 * are supposedly unused during chained dma, 2528 * but I have found that left over values from last operation 2529 * occasionally cause problems with transfer of first dma 2530 * block. Initializing them to zero seems to fix the problem. 2531 */ 2532 if (dma_channel) { 2533 writel(0, devpriv->plx9080_iobase + PLX_REG_DMASIZ1); 2534 writel(0, devpriv->plx9080_iobase + PLX_REG_DMAPADR1); 2535 writel(0, devpriv->plx9080_iobase + PLX_REG_DMALADR1); 2536 writel(descriptor_bits, 2537 devpriv->plx9080_iobase + PLX_REG_DMADPR1); 2538 } else { 2539 writel(0, devpriv->plx9080_iobase + PLX_REG_DMASIZ0); 2540 writel(0, devpriv->plx9080_iobase + PLX_REG_DMAPADR0); 2541 writel(0, devpriv->plx9080_iobase + PLX_REG_DMALADR0); 2542 writel(descriptor_bits, 2543 devpriv->plx9080_iobase + PLX_REG_DMADPR0); 2544 } 2545 } 2546 2547 static int ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s) 2548 { 2549 const struct pcidas64_board *board = dev->board_ptr; 2550 struct pcidas64_private *devpriv = dev->private; 2551 struct comedi_async *async = s->async; 2552 struct comedi_cmd *cmd = &async->cmd; 2553 u32 bits; 2554 unsigned int i; 2555 unsigned long flags; 2556 int retval; 2557 2558 disable_ai_pacing(dev); 2559 abort_dma(dev, 1); 2560 2561 retval = setup_channel_queue(dev, cmd); 2562 if (retval < 0) 2563 return retval; 2564 2565 /* make sure internal calibration source is turned off */ 2566 writew(0, devpriv->main_iobase + CALIBRATION_REG); 2567 2568 set_ai_pacing(dev, cmd); 2569 2570 setup_sample_counters(dev, cmd); 2571 2572 enable_ai_interrupts(dev, cmd); 2573 2574 spin_lock_irqsave(&dev->spinlock, flags); 2575 /* set mode, allow conversions through software gate */ 2576 devpriv->adc_control1_bits |= ADC_SW_GATE_BIT; 2577 devpriv->adc_control1_bits &= ~ADC_DITHER_BIT; 2578 if (board->layout != LAYOUT_4020) { 2579 devpriv->adc_control1_bits &= ~ADC_MODE_MASK; 2580 if (cmd->convert_src == TRIG_EXT) 2581 /* good old mode 13 */ 2582 devpriv->adc_control1_bits |= adc_mode_bits(13); 2583 else 2584 /* mode 8. What else could you need? */ 2585 devpriv->adc_control1_bits |= adc_mode_bits(8); 2586 } else { 2587 devpriv->adc_control1_bits &= ~CHANNEL_MODE_4020_MASK; 2588 if (cmd->chanlist_len == 4) 2589 devpriv->adc_control1_bits |= FOUR_CHANNEL_4020_BITS; 2590 else if (cmd->chanlist_len == 2) 2591 devpriv->adc_control1_bits |= TWO_CHANNEL_4020_BITS; 2592 devpriv->adc_control1_bits &= ~ADC_LO_CHANNEL_4020_MASK; 2593 devpriv->adc_control1_bits |= 2594 adc_lo_chan_4020_bits(CR_CHAN(cmd->chanlist[0])); 2595 devpriv->adc_control1_bits &= ~ADC_HI_CHANNEL_4020_MASK; 2596 devpriv->adc_control1_bits |= 2597 adc_hi_chan_4020_bits(CR_CHAN(cmd->chanlist 2598 [cmd->chanlist_len - 1])); 2599 } 2600 writew(devpriv->adc_control1_bits, 2601 devpriv->main_iobase + ADC_CONTROL1_REG); 2602 spin_unlock_irqrestore(&dev->spinlock, flags); 2603 2604 /* clear adc buffer */ 2605 writew(0, devpriv->main_iobase + ADC_BUFFER_CLEAR_REG); 2606 2607 if ((cmd->flags & CMDF_WAKE_EOS) == 0 || 2608 board->layout == LAYOUT_4020) { 2609 devpriv->ai_dma_index = 0; 2610 2611 /* set dma transfer size */ 2612 for (i = 0; i < ai_dma_ring_count(board); i++) 2613 devpriv->ai_dma_desc[i].transfer_size = 2614 cpu_to_le32(dma_transfer_size(dev) * 2615 sizeof(u16)); 2616 2617 /* give location of first dma descriptor */ 2618 load_first_dma_descriptor(dev, 1, 2619 devpriv->ai_dma_desc_bus_addr | 2620 PLX_DMADPR_DESCPCI | 2621 PLX_DMADPR_TCINTR | 2622 PLX_DMADPR_XFERL2P); 2623 2624 dma_start_sync(dev, 1); 2625 } 2626 2627 if (board->layout == LAYOUT_4020) { 2628 /* set source for external triggers */ 2629 bits = 0; 2630 if (cmd->start_src == TRIG_EXT && CR_CHAN(cmd->start_arg)) 2631 bits |= EXT_START_TRIG_BNC_BIT; 2632 if (cmd->stop_src == TRIG_EXT && CR_CHAN(cmd->stop_arg)) 2633 bits |= EXT_STOP_TRIG_BNC_BIT; 2634 writew(bits, devpriv->main_iobase + DAQ_ATRIG_LOW_4020_REG); 2635 } 2636 2637 spin_lock_irqsave(&dev->spinlock, flags); 2638 2639 /* enable pacing, triggering, etc */ 2640 bits = ADC_ENABLE_BIT | ADC_SOFT_GATE_BITS | ADC_GATE_LEVEL_BIT; 2641 if (cmd->flags & CMDF_WAKE_EOS) 2642 bits |= ADC_DMA_DISABLE_BIT; 2643 /* set start trigger */ 2644 if (cmd->start_src == TRIG_EXT) { 2645 bits |= ADC_START_TRIG_EXT_BITS; 2646 if (cmd->start_arg & CR_INVERT) 2647 bits |= ADC_START_TRIG_FALLING_BIT; 2648 } else if (cmd->start_src == TRIG_NOW) { 2649 bits |= ADC_START_TRIG_SOFT_BITS; 2650 } 2651 if (use_hw_sample_counter(cmd)) 2652 bits |= ADC_SAMPLE_COUNTER_EN_BIT; 2653 writew(bits, devpriv->main_iobase + ADC_CONTROL0_REG); 2654 2655 devpriv->ai_cmd_running = 1; 2656 2657 spin_unlock_irqrestore(&dev->spinlock, flags); 2658 2659 /* start acquisition */ 2660 if (cmd->start_src == TRIG_NOW) 2661 writew(0, devpriv->main_iobase + ADC_START_REG); 2662 2663 return 0; 2664 } 2665 2666 /* read num_samples from 16 bit wide ai fifo */ 2667 static void pio_drain_ai_fifo_16(struct comedi_device *dev) 2668 { 2669 struct pcidas64_private *devpriv = dev->private; 2670 struct comedi_subdevice *s = dev->read_subdev; 2671 unsigned int i; 2672 u16 prepost_bits; 2673 int read_segment, read_index, write_segment, write_index; 2674 int num_samples; 2675 2676 do { 2677 /* get least significant 15 bits */ 2678 read_index = readw(devpriv->main_iobase + ADC_READ_PNTR_REG) & 2679 0x7fff; 2680 write_index = readw(devpriv->main_iobase + ADC_WRITE_PNTR_REG) & 2681 0x7fff; 2682 /* 2683 * Get most significant bits (grey code). 2684 * Different boards use different code so use a scheme 2685 * that doesn't depend on encoding. This read must 2686 * occur after reading least significant 15 bits to avoid race 2687 * with fifo switching to next segment. 2688 */ 2689 prepost_bits = readw(devpriv->main_iobase + PREPOST_REG); 2690 2691 /* 2692 * if read and write pointers are not on the same fifo segment, 2693 * read to the end of the read segment 2694 */ 2695 read_segment = adc_upper_read_ptr_code(prepost_bits); 2696 write_segment = adc_upper_write_ptr_code(prepost_bits); 2697 2698 if (read_segment != write_segment) 2699 num_samples = 2700 devpriv->ai_fifo_segment_length - read_index; 2701 else 2702 num_samples = write_index - read_index; 2703 if (num_samples < 0) { 2704 dev_err(dev->class_dev, 2705 "cb_pcidas64: bug! num_samples < 0\n"); 2706 break; 2707 } 2708 2709 num_samples = comedi_nsamples_left(s, num_samples); 2710 if (num_samples == 0) 2711 break; 2712 2713 for (i = 0; i < num_samples; i++) { 2714 unsigned short val; 2715 2716 val = readw(devpriv->main_iobase + ADC_FIFO_REG); 2717 comedi_buf_write_samples(s, &val, 1); 2718 } 2719 2720 } while (read_segment != write_segment); 2721 } 2722 2723 /* 2724 * Read from 32 bit wide ai fifo of 4020 - deal with insane grey coding of 2725 * pointers. The pci-4020 hardware only supports dma transfers (it only 2726 * supports the use of pio for draining the last remaining points from the 2727 * fifo when a data acquisition operation has completed). 2728 */ 2729 static void pio_drain_ai_fifo_32(struct comedi_device *dev) 2730 { 2731 struct pcidas64_private *devpriv = dev->private; 2732 struct comedi_subdevice *s = dev->read_subdev; 2733 unsigned int nsamples; 2734 unsigned int i; 2735 u32 fifo_data; 2736 int write_code = 2737 readw(devpriv->main_iobase + ADC_WRITE_PNTR_REG) & 0x7fff; 2738 int read_code = 2739 readw(devpriv->main_iobase + ADC_READ_PNTR_REG) & 0x7fff; 2740 2741 nsamples = comedi_nsamples_left(s, 100000); 2742 for (i = 0; read_code != write_code && i < nsamples;) { 2743 unsigned short val; 2744 2745 fifo_data = readl(dev->mmio + ADC_FIFO_REG); 2746 val = fifo_data & 0xffff; 2747 comedi_buf_write_samples(s, &val, 1); 2748 i++; 2749 if (i < nsamples) { 2750 val = (fifo_data >> 16) & 0xffff; 2751 comedi_buf_write_samples(s, &val, 1); 2752 i++; 2753 } 2754 read_code = readw(devpriv->main_iobase + ADC_READ_PNTR_REG) & 2755 0x7fff; 2756 } 2757 } 2758 2759 /* empty fifo */ 2760 static void pio_drain_ai_fifo(struct comedi_device *dev) 2761 { 2762 const struct pcidas64_board *board = dev->board_ptr; 2763 2764 if (board->layout == LAYOUT_4020) 2765 pio_drain_ai_fifo_32(dev); 2766 else 2767 pio_drain_ai_fifo_16(dev); 2768 } 2769 2770 static void drain_dma_buffers(struct comedi_device *dev, unsigned int channel) 2771 { 2772 const struct pcidas64_board *board = dev->board_ptr; 2773 struct pcidas64_private *devpriv = dev->private; 2774 struct comedi_subdevice *s = dev->read_subdev; 2775 u32 next_transfer_addr; 2776 int j; 2777 int num_samples = 0; 2778 void __iomem *pci_addr_reg; 2779 2780 pci_addr_reg = devpriv->plx9080_iobase + PLX_REG_DMAPADR(channel); 2781 2782 /* loop until we have read all the full buffers */ 2783 for (j = 0, next_transfer_addr = readl(pci_addr_reg); 2784 (next_transfer_addr < 2785 devpriv->ai_buffer_bus_addr[devpriv->ai_dma_index] || 2786 next_transfer_addr >= 2787 devpriv->ai_buffer_bus_addr[devpriv->ai_dma_index] + 2788 DMA_BUFFER_SIZE) && j < ai_dma_ring_count(board); j++) { 2789 /* transfer data from dma buffer to comedi buffer */ 2790 num_samples = comedi_nsamples_left(s, dma_transfer_size(dev)); 2791 comedi_buf_write_samples(s, 2792 devpriv->ai_buffer[devpriv->ai_dma_index], 2793 num_samples); 2794 devpriv->ai_dma_index = (devpriv->ai_dma_index + 1) % 2795 ai_dma_ring_count(board); 2796 } 2797 /* 2798 * XXX check for dma ring buffer overrun 2799 * (use end-of-chain bit to mark last unused buffer) 2800 */ 2801 } 2802 2803 static void handle_ai_interrupt(struct comedi_device *dev, 2804 unsigned short status, 2805 unsigned int plx_status) 2806 { 2807 const struct pcidas64_board *board = dev->board_ptr; 2808 struct pcidas64_private *devpriv = dev->private; 2809 struct comedi_subdevice *s = dev->read_subdev; 2810 struct comedi_async *async = s->async; 2811 struct comedi_cmd *cmd = &async->cmd; 2812 u8 dma1_status; 2813 unsigned long flags; 2814 2815 /* check for fifo overrun */ 2816 if (status & ADC_OVERRUN_BIT) { 2817 dev_err(dev->class_dev, "fifo overrun\n"); 2818 async->events |= COMEDI_CB_ERROR; 2819 } 2820 /* spin lock makes sure no one else changes plx dma control reg */ 2821 spin_lock_irqsave(&dev->spinlock, flags); 2822 dma1_status = readb(devpriv->plx9080_iobase + PLX_REG_DMACSR1); 2823 if (plx_status & PLX_INTCSR_DMA1IA) { /* dma chan 1 interrupt */ 2824 writeb((dma1_status & PLX_DMACSR_ENABLE) | PLX_DMACSR_CLEARINTR, 2825 devpriv->plx9080_iobase + PLX_REG_DMACSR1); 2826 2827 if (dma1_status & PLX_DMACSR_ENABLE) 2828 drain_dma_buffers(dev, 1); 2829 } 2830 spin_unlock_irqrestore(&dev->spinlock, flags); 2831 2832 /* drain fifo with pio */ 2833 if ((status & ADC_DONE_BIT) || 2834 ((cmd->flags & CMDF_WAKE_EOS) && 2835 (status & ADC_INTR_PENDING_BIT) && 2836 (board->layout != LAYOUT_4020))) { 2837 spin_lock_irqsave(&dev->spinlock, flags); 2838 if (devpriv->ai_cmd_running) { 2839 spin_unlock_irqrestore(&dev->spinlock, flags); 2840 pio_drain_ai_fifo(dev); 2841 } else { 2842 spin_unlock_irqrestore(&dev->spinlock, flags); 2843 } 2844 } 2845 /* if we are have all the data, then quit */ 2846 if ((cmd->stop_src == TRIG_COUNT && 2847 async->scans_done >= cmd->stop_arg) || 2848 (cmd->stop_src == TRIG_EXT && (status & ADC_STOP_BIT))) 2849 async->events |= COMEDI_CB_EOA; 2850 2851 comedi_handle_events(dev, s); 2852 } 2853 2854 static inline unsigned int prev_ao_dma_index(struct comedi_device *dev) 2855 { 2856 struct pcidas64_private *devpriv = dev->private; 2857 unsigned int buffer_index; 2858 2859 if (devpriv->ao_dma_index == 0) 2860 buffer_index = AO_DMA_RING_COUNT - 1; 2861 else 2862 buffer_index = devpriv->ao_dma_index - 1; 2863 return buffer_index; 2864 } 2865 2866 static int last_ao_dma_load_completed(struct comedi_device *dev) 2867 { 2868 struct pcidas64_private *devpriv = dev->private; 2869 unsigned int buffer_index; 2870 unsigned int transfer_address; 2871 unsigned short dma_status; 2872 2873 buffer_index = prev_ao_dma_index(dev); 2874 dma_status = readb(devpriv->plx9080_iobase + PLX_REG_DMACSR0); 2875 if ((dma_status & PLX_DMACSR_DONE) == 0) 2876 return 0; 2877 2878 transfer_address = 2879 readl(devpriv->plx9080_iobase + PLX_REG_DMAPADR0); 2880 if (transfer_address != devpriv->ao_buffer_bus_addr[buffer_index]) 2881 return 0; 2882 2883 return 1; 2884 } 2885 2886 static inline int ao_dma_needs_restart(struct comedi_device *dev, 2887 unsigned short dma_status) 2888 { 2889 if ((dma_status & PLX_DMACSR_DONE) == 0 || 2890 (dma_status & PLX_DMACSR_ENABLE) == 0) 2891 return 0; 2892 if (last_ao_dma_load_completed(dev)) 2893 return 0; 2894 2895 return 1; 2896 } 2897 2898 static void restart_ao_dma(struct comedi_device *dev) 2899 { 2900 struct pcidas64_private *devpriv = dev->private; 2901 unsigned int dma_desc_bits; 2902 2903 dma_desc_bits = readl(devpriv->plx9080_iobase + PLX_REG_DMADPR0); 2904 dma_desc_bits &= ~PLX_DMADPR_CHAINEND; 2905 load_first_dma_descriptor(dev, 0, dma_desc_bits); 2906 2907 dma_start_sync(dev, 0); 2908 } 2909 2910 static unsigned int cb_pcidas64_ao_fill_buffer(struct comedi_device *dev, 2911 struct comedi_subdevice *s, 2912 unsigned short *dest, 2913 unsigned int max_bytes) 2914 { 2915 unsigned int nsamples = comedi_bytes_to_samples(s, max_bytes); 2916 unsigned int actual_bytes; 2917 2918 nsamples = comedi_nsamples_left(s, nsamples); 2919 actual_bytes = comedi_buf_read_samples(s, dest, nsamples); 2920 2921 return comedi_bytes_to_samples(s, actual_bytes); 2922 } 2923 2924 static unsigned int load_ao_dma_buffer(struct comedi_device *dev, 2925 const struct comedi_cmd *cmd) 2926 { 2927 struct pcidas64_private *devpriv = dev->private; 2928 struct comedi_subdevice *s = dev->write_subdev; 2929 unsigned int buffer_index = devpriv->ao_dma_index; 2930 unsigned int prev_buffer_index = prev_ao_dma_index(dev); 2931 unsigned int nsamples; 2932 unsigned int nbytes; 2933 unsigned int next_bits; 2934 2935 nsamples = cb_pcidas64_ao_fill_buffer(dev, s, 2936 devpriv->ao_buffer[buffer_index], 2937 DMA_BUFFER_SIZE); 2938 if (nsamples == 0) 2939 return 0; 2940 2941 nbytes = comedi_samples_to_bytes(s, nsamples); 2942 devpriv->ao_dma_desc[buffer_index].transfer_size = cpu_to_le32(nbytes); 2943 /* set end of chain bit so we catch underruns */ 2944 next_bits = le32_to_cpu(devpriv->ao_dma_desc[buffer_index].next); 2945 next_bits |= PLX_DMADPR_CHAINEND; 2946 devpriv->ao_dma_desc[buffer_index].next = cpu_to_le32(next_bits); 2947 /* 2948 * clear end of chain bit on previous buffer now that we have set it 2949 * for the last buffer 2950 */ 2951 next_bits = le32_to_cpu(devpriv->ao_dma_desc[prev_buffer_index].next); 2952 next_bits &= ~PLX_DMADPR_CHAINEND; 2953 devpriv->ao_dma_desc[prev_buffer_index].next = cpu_to_le32(next_bits); 2954 2955 devpriv->ao_dma_index = (buffer_index + 1) % AO_DMA_RING_COUNT; 2956 2957 return nbytes; 2958 } 2959 2960 static void load_ao_dma(struct comedi_device *dev, const struct comedi_cmd *cmd) 2961 { 2962 struct pcidas64_private *devpriv = dev->private; 2963 unsigned int num_bytes; 2964 unsigned int next_transfer_addr; 2965 void __iomem *pci_addr_reg = devpriv->plx9080_iobase + PLX_REG_DMAPADR0; 2966 unsigned int buffer_index; 2967 2968 do { 2969 buffer_index = devpriv->ao_dma_index; 2970 /* don't overwrite data that hasn't been transferred yet */ 2971 next_transfer_addr = readl(pci_addr_reg); 2972 if (next_transfer_addr >= 2973 devpriv->ao_buffer_bus_addr[buffer_index] && 2974 next_transfer_addr < 2975 devpriv->ao_buffer_bus_addr[buffer_index] + 2976 DMA_BUFFER_SIZE) 2977 return; 2978 num_bytes = load_ao_dma_buffer(dev, cmd); 2979 } while (num_bytes >= DMA_BUFFER_SIZE); 2980 } 2981 2982 static void handle_ao_interrupt(struct comedi_device *dev, 2983 unsigned short status, unsigned int plx_status) 2984 { 2985 struct pcidas64_private *devpriv = dev->private; 2986 struct comedi_subdevice *s = dev->write_subdev; 2987 struct comedi_async *async; 2988 struct comedi_cmd *cmd; 2989 u8 dma0_status; 2990 unsigned long flags; 2991 2992 /* board might not support ao, in which case write_subdev is NULL */ 2993 if (!s) 2994 return; 2995 async = s->async; 2996 cmd = &async->cmd; 2997 2998 /* spin lock makes sure no one else changes plx dma control reg */ 2999 spin_lock_irqsave(&dev->spinlock, flags); 3000 dma0_status = readb(devpriv->plx9080_iobase + PLX_REG_DMACSR0); 3001 if (plx_status & PLX_INTCSR_DMA0IA) { /* dma chan 0 interrupt */ 3002 if ((dma0_status & PLX_DMACSR_ENABLE) && 3003 !(dma0_status & PLX_DMACSR_DONE)) { 3004 writeb(PLX_DMACSR_ENABLE | PLX_DMACSR_CLEARINTR, 3005 devpriv->plx9080_iobase + PLX_REG_DMACSR0); 3006 } else { 3007 writeb(PLX_DMACSR_CLEARINTR, 3008 devpriv->plx9080_iobase + PLX_REG_DMACSR0); 3009 } 3010 spin_unlock_irqrestore(&dev->spinlock, flags); 3011 if (dma0_status & PLX_DMACSR_ENABLE) { 3012 load_ao_dma(dev, cmd); 3013 /* try to recover from dma end-of-chain event */ 3014 if (ao_dma_needs_restart(dev, dma0_status)) 3015 restart_ao_dma(dev); 3016 } 3017 } else { 3018 spin_unlock_irqrestore(&dev->spinlock, flags); 3019 } 3020 3021 if ((status & DAC_DONE_BIT)) { 3022 if ((cmd->stop_src == TRIG_COUNT && 3023 async->scans_done >= cmd->stop_arg) || 3024 last_ao_dma_load_completed(dev)) 3025 async->events |= COMEDI_CB_EOA; 3026 else 3027 async->events |= COMEDI_CB_ERROR; 3028 } 3029 comedi_handle_events(dev, s); 3030 } 3031 3032 static irqreturn_t handle_interrupt(int irq, void *d) 3033 { 3034 struct comedi_device *dev = d; 3035 struct pcidas64_private *devpriv = dev->private; 3036 unsigned short status; 3037 u32 plx_status; 3038 u32 plx_bits; 3039 3040 plx_status = readl(devpriv->plx9080_iobase + PLX_REG_INTCSR); 3041 status = readw(devpriv->main_iobase + HW_STATUS_REG); 3042 3043 /* 3044 * an interrupt before all the postconfig stuff gets done could 3045 * cause a NULL dereference if we continue through the 3046 * interrupt handler 3047 */ 3048 if (!dev->attached) 3049 return IRQ_HANDLED; 3050 3051 handle_ai_interrupt(dev, status, plx_status); 3052 handle_ao_interrupt(dev, status, plx_status); 3053 3054 /* clear possible plx9080 interrupt sources */ 3055 if (plx_status & PLX_INTCSR_LDBIA) { 3056 /* clear local doorbell interrupt */ 3057 plx_bits = readl(devpriv->plx9080_iobase + PLX_REG_L2PDBELL); 3058 writel(plx_bits, devpriv->plx9080_iobase + PLX_REG_L2PDBELL); 3059 } 3060 3061 return IRQ_HANDLED; 3062 } 3063 3064 static int ai_cancel(struct comedi_device *dev, struct comedi_subdevice *s) 3065 { 3066 struct pcidas64_private *devpriv = dev->private; 3067 unsigned long flags; 3068 3069 spin_lock_irqsave(&dev->spinlock, flags); 3070 if (devpriv->ai_cmd_running == 0) { 3071 spin_unlock_irqrestore(&dev->spinlock, flags); 3072 return 0; 3073 } 3074 devpriv->ai_cmd_running = 0; 3075 spin_unlock_irqrestore(&dev->spinlock, flags); 3076 3077 disable_ai_pacing(dev); 3078 3079 abort_dma(dev, 1); 3080 3081 return 0; 3082 } 3083 3084 static int ao_winsn(struct comedi_device *dev, struct comedi_subdevice *s, 3085 struct comedi_insn *insn, unsigned int *data) 3086 { 3087 const struct pcidas64_board *board = dev->board_ptr; 3088 struct pcidas64_private *devpriv = dev->private; 3089 unsigned int chan = CR_CHAN(insn->chanspec); 3090 unsigned int range = CR_RANGE(insn->chanspec); 3091 unsigned int val = s->readback[chan]; 3092 unsigned int i; 3093 3094 /* do some initializing */ 3095 writew(0, devpriv->main_iobase + DAC_CONTROL0_REG); 3096 3097 /* set range */ 3098 set_dac_range_bits(dev, &devpriv->dac_control1_bits, chan, range); 3099 writew(devpriv->dac_control1_bits, 3100 devpriv->main_iobase + DAC_CONTROL1_REG); 3101 3102 for (i = 0; i < insn->n; i++) { 3103 /* write to channel */ 3104 val = data[i]; 3105 if (board->layout == LAYOUT_4020) { 3106 writew(val & 0xff, 3107 devpriv->main_iobase + dac_lsb_4020_reg(chan)); 3108 writew((val >> 8) & 0xf, 3109 devpriv->main_iobase + dac_msb_4020_reg(chan)); 3110 } else { 3111 writew(val, 3112 devpriv->main_iobase + dac_convert_reg(chan)); 3113 } 3114 } 3115 3116 /* remember last output value */ 3117 s->readback[chan] = val; 3118 3119 return insn->n; 3120 } 3121 3122 static void set_dac_control0_reg(struct comedi_device *dev, 3123 const struct comedi_cmd *cmd) 3124 { 3125 struct pcidas64_private *devpriv = dev->private; 3126 unsigned int bits = DAC_ENABLE_BIT | WAVEFORM_GATE_LEVEL_BIT | 3127 WAVEFORM_GATE_ENABLE_BIT | WAVEFORM_GATE_SELECT_BIT; 3128 3129 if (cmd->start_src == TRIG_EXT) { 3130 bits |= WAVEFORM_TRIG_EXT_BITS; 3131 if (cmd->start_arg & CR_INVERT) 3132 bits |= WAVEFORM_TRIG_FALLING_BIT; 3133 } else { 3134 bits |= WAVEFORM_TRIG_SOFT_BITS; 3135 } 3136 if (cmd->scan_begin_src == TRIG_EXT) { 3137 bits |= DAC_EXT_UPDATE_ENABLE_BIT; 3138 if (cmd->scan_begin_arg & CR_INVERT) 3139 bits |= DAC_EXT_UPDATE_FALLING_BIT; 3140 } 3141 writew(bits, devpriv->main_iobase + DAC_CONTROL0_REG); 3142 } 3143 3144 static void set_dac_control1_reg(struct comedi_device *dev, 3145 const struct comedi_cmd *cmd) 3146 { 3147 struct pcidas64_private *devpriv = dev->private; 3148 int i; 3149 3150 for (i = 0; i < cmd->chanlist_len; i++) { 3151 int channel, range; 3152 3153 channel = CR_CHAN(cmd->chanlist[i]); 3154 range = CR_RANGE(cmd->chanlist[i]); 3155 set_dac_range_bits(dev, &devpriv->dac_control1_bits, channel, 3156 range); 3157 } 3158 devpriv->dac_control1_bits |= DAC_SW_GATE_BIT; 3159 writew(devpriv->dac_control1_bits, 3160 devpriv->main_iobase + DAC_CONTROL1_REG); 3161 } 3162 3163 static void set_dac_select_reg(struct comedi_device *dev, 3164 const struct comedi_cmd *cmd) 3165 { 3166 struct pcidas64_private *devpriv = dev->private; 3167 u16 bits; 3168 unsigned int first_channel, last_channel; 3169 3170 first_channel = CR_CHAN(cmd->chanlist[0]); 3171 last_channel = CR_CHAN(cmd->chanlist[cmd->chanlist_len - 1]); 3172 if (last_channel < first_channel) 3173 dev_err(dev->class_dev, 3174 "bug! last ao channel < first ao channel\n"); 3175 3176 bits = (first_channel & 0x7) | (last_channel & 0x7) << 3; 3177 3178 writew(bits, devpriv->main_iobase + DAC_SELECT_REG); 3179 } 3180 3181 static unsigned int get_ao_divisor(unsigned int ns, unsigned int flags) 3182 { 3183 return get_divisor(ns, flags) - 2; 3184 } 3185 3186 static void set_dac_interval_regs(struct comedi_device *dev, 3187 const struct comedi_cmd *cmd) 3188 { 3189 struct pcidas64_private *devpriv = dev->private; 3190 unsigned int divisor; 3191 3192 if (cmd->scan_begin_src != TRIG_TIMER) 3193 return; 3194 3195 divisor = get_ao_divisor(cmd->scan_begin_arg, cmd->flags); 3196 if (divisor > max_counter_value) { 3197 dev_err(dev->class_dev, "bug! ao divisor too big\n"); 3198 divisor = max_counter_value; 3199 } 3200 writew(divisor & 0xffff, 3201 devpriv->main_iobase + DAC_SAMPLE_INTERVAL_LOWER_REG); 3202 writew((divisor >> 16) & 0xff, 3203 devpriv->main_iobase + DAC_SAMPLE_INTERVAL_UPPER_REG); 3204 } 3205 3206 static int prep_ao_dma(struct comedi_device *dev, const struct comedi_cmd *cmd) 3207 { 3208 struct pcidas64_private *devpriv = dev->private; 3209 struct comedi_subdevice *s = dev->write_subdev; 3210 unsigned int nsamples; 3211 unsigned int nbytes; 3212 int i; 3213 3214 /* 3215 * clear queue pointer too, since external queue has 3216 * weird interactions with ao fifo 3217 */ 3218 writew(0, devpriv->main_iobase + ADC_QUEUE_CLEAR_REG); 3219 writew(0, devpriv->main_iobase + DAC_BUFFER_CLEAR_REG); 3220 3221 nsamples = cb_pcidas64_ao_fill_buffer(dev, s, 3222 devpriv->ao_bounce_buffer, 3223 DAC_FIFO_SIZE); 3224 if (nsamples == 0) 3225 return -1; 3226 3227 for (i = 0; i < nsamples; i++) { 3228 writew(devpriv->ao_bounce_buffer[i], 3229 devpriv->main_iobase + DAC_FIFO_REG); 3230 } 3231 3232 if (cmd->stop_src == TRIG_COUNT && 3233 s->async->scans_done >= cmd->stop_arg) 3234 return 0; 3235 3236 nbytes = load_ao_dma_buffer(dev, cmd); 3237 if (nbytes == 0) 3238 return -1; 3239 load_ao_dma(dev, cmd); 3240 3241 dma_start_sync(dev, 0); 3242 3243 return 0; 3244 } 3245 3246 static inline int external_ai_queue_in_use(struct comedi_device *dev) 3247 { 3248 const struct pcidas64_board *board = dev->board_ptr; 3249 3250 if (!dev->read_subdev->busy) 3251 return 0; 3252 if (board->layout == LAYOUT_4020) 3253 return 0; 3254 else if (use_internal_queue_6xxx(&dev->read_subdev->async->cmd)) 3255 return 0; 3256 return 1; 3257 } 3258 3259 static int ao_inttrig(struct comedi_device *dev, struct comedi_subdevice *s, 3260 unsigned int trig_num) 3261 { 3262 struct pcidas64_private *devpriv = dev->private; 3263 struct comedi_cmd *cmd = &s->async->cmd; 3264 int retval; 3265 3266 if (trig_num != cmd->start_arg) 3267 return -EINVAL; 3268 3269 retval = prep_ao_dma(dev, cmd); 3270 if (retval < 0) 3271 return -EPIPE; 3272 3273 set_dac_control0_reg(dev, cmd); 3274 3275 if (cmd->start_src == TRIG_INT) 3276 writew(0, devpriv->main_iobase + DAC_START_REG); 3277 3278 s->async->inttrig = NULL; 3279 3280 return 0; 3281 } 3282 3283 static int ao_cmd(struct comedi_device *dev, struct comedi_subdevice *s) 3284 { 3285 struct pcidas64_private *devpriv = dev->private; 3286 struct comedi_cmd *cmd = &s->async->cmd; 3287 3288 if (external_ai_queue_in_use(dev)) { 3289 warn_external_queue(dev); 3290 return -EBUSY; 3291 } 3292 /* disable analog output system during setup */ 3293 writew(0x0, devpriv->main_iobase + DAC_CONTROL0_REG); 3294 3295 devpriv->ao_dma_index = 0; 3296 3297 set_dac_select_reg(dev, cmd); 3298 set_dac_interval_regs(dev, cmd); 3299 load_first_dma_descriptor(dev, 0, devpriv->ao_dma_desc_bus_addr | 3300 PLX_DMADPR_DESCPCI | PLX_DMADPR_TCINTR); 3301 3302 set_dac_control1_reg(dev, cmd); 3303 s->async->inttrig = ao_inttrig; 3304 3305 return 0; 3306 } 3307 3308 static int cb_pcidas64_ao_check_chanlist(struct comedi_device *dev, 3309 struct comedi_subdevice *s, 3310 struct comedi_cmd *cmd) 3311 { 3312 unsigned int chan0 = CR_CHAN(cmd->chanlist[0]); 3313 int i; 3314 3315 for (i = 1; i < cmd->chanlist_len; i++) { 3316 unsigned int chan = CR_CHAN(cmd->chanlist[i]); 3317 3318 if (chan != (chan0 + i)) { 3319 dev_dbg(dev->class_dev, 3320 "chanlist must use consecutive channels\n"); 3321 return -EINVAL; 3322 } 3323 } 3324 3325 return 0; 3326 } 3327 3328 static int ao_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s, 3329 struct comedi_cmd *cmd) 3330 { 3331 const struct pcidas64_board *board = dev->board_ptr; 3332 int err = 0; 3333 unsigned int tmp_arg; 3334 3335 /* Step 1 : check if triggers are trivially valid */ 3336 3337 err |= comedi_check_trigger_src(&cmd->start_src, TRIG_INT | TRIG_EXT); 3338 err |= comedi_check_trigger_src(&cmd->scan_begin_src, 3339 TRIG_TIMER | TRIG_EXT); 3340 err |= comedi_check_trigger_src(&cmd->convert_src, TRIG_NOW); 3341 err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT); 3342 err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_NONE); 3343 3344 if (err) 3345 return 1; 3346 3347 /* Step 2a : make sure trigger sources are unique */ 3348 3349 err |= comedi_check_trigger_is_unique(cmd->start_src); 3350 err |= comedi_check_trigger_is_unique(cmd->scan_begin_src); 3351 3352 /* Step 2b : and mutually compatible */ 3353 3354 if (cmd->convert_src == TRIG_EXT && cmd->scan_begin_src == TRIG_TIMER) 3355 err |= -EINVAL; 3356 if (cmd->stop_src != TRIG_COUNT && 3357 cmd->stop_src != TRIG_NONE && cmd->stop_src != TRIG_EXT) 3358 err |= -EINVAL; 3359 3360 if (err) 3361 return 2; 3362 3363 /* Step 3: check if arguments are trivially valid */ 3364 3365 err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0); 3366 3367 if (cmd->scan_begin_src == TRIG_TIMER) { 3368 err |= comedi_check_trigger_arg_min(&cmd->scan_begin_arg, 3369 board->ao_scan_speed); 3370 if (get_ao_divisor(cmd->scan_begin_arg, cmd->flags) > 3371 max_counter_value) { 3372 cmd->scan_begin_arg = (max_counter_value + 2) * 3373 TIMER_BASE; 3374 err |= -EINVAL; 3375 } 3376 } 3377 3378 err |= comedi_check_trigger_arg_min(&cmd->chanlist_len, 1); 3379 err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg, 3380 cmd->chanlist_len); 3381 3382 if (err) 3383 return 3; 3384 3385 /* step 4: fix up any arguments */ 3386 3387 if (cmd->scan_begin_src == TRIG_TIMER) { 3388 tmp_arg = cmd->scan_begin_arg; 3389 cmd->scan_begin_arg = get_divisor(cmd->scan_begin_arg, 3390 cmd->flags) * TIMER_BASE; 3391 if (tmp_arg != cmd->scan_begin_arg) 3392 err++; 3393 } 3394 3395 if (err) 3396 return 4; 3397 3398 /* Step 5: check channel list if it exists */ 3399 if (cmd->chanlist && cmd->chanlist_len > 0) 3400 err |= cb_pcidas64_ao_check_chanlist(dev, s, cmd); 3401 3402 if (err) 3403 return 5; 3404 3405 return 0; 3406 } 3407 3408 static int ao_cancel(struct comedi_device *dev, struct comedi_subdevice *s) 3409 { 3410 struct pcidas64_private *devpriv = dev->private; 3411 3412 writew(0x0, devpriv->main_iobase + DAC_CONTROL0_REG); 3413 abort_dma(dev, 0); 3414 return 0; 3415 } 3416 3417 static int dio_callback_4020(struct comedi_device *dev, 3418 int dir, int port, int data, unsigned long iobase) 3419 { 3420 struct pcidas64_private *devpriv = dev->private; 3421 3422 if (dir) { 3423 writew(data, devpriv->main_iobase + iobase + 2 * port); 3424 return 0; 3425 } 3426 return readw(devpriv->main_iobase + iobase + 2 * port); 3427 } 3428 3429 static int di_rbits(struct comedi_device *dev, struct comedi_subdevice *s, 3430 struct comedi_insn *insn, unsigned int *data) 3431 { 3432 unsigned int bits; 3433 3434 bits = readb(dev->mmio + DI_REG); 3435 bits &= 0xf; 3436 data[1] = bits; 3437 data[0] = 0; 3438 3439 return insn->n; 3440 } 3441 3442 static int do_wbits(struct comedi_device *dev, 3443 struct comedi_subdevice *s, 3444 struct comedi_insn *insn, 3445 unsigned int *data) 3446 { 3447 if (comedi_dio_update_state(s, data)) 3448 writeb(s->state, dev->mmio + DO_REG); 3449 3450 data[1] = s->state; 3451 3452 return insn->n; 3453 } 3454 3455 static int dio_60xx_config_insn(struct comedi_device *dev, 3456 struct comedi_subdevice *s, 3457 struct comedi_insn *insn, 3458 unsigned int *data) 3459 { 3460 int ret; 3461 3462 ret = comedi_dio_insn_config(dev, s, insn, data, 0); 3463 if (ret) 3464 return ret; 3465 3466 writeb(s->io_bits, dev->mmio + DIO_DIRECTION_60XX_REG); 3467 3468 return insn->n; 3469 } 3470 3471 static int dio_60xx_wbits(struct comedi_device *dev, 3472 struct comedi_subdevice *s, 3473 struct comedi_insn *insn, 3474 unsigned int *data) 3475 { 3476 if (comedi_dio_update_state(s, data)) 3477 writeb(s->state, dev->mmio + DIO_DATA_60XX_REG); 3478 3479 data[1] = readb(dev->mmio + DIO_DATA_60XX_REG); 3480 3481 return insn->n; 3482 } 3483 3484 /* 3485 * pci-6025 8800 caldac: 3486 * address 0 == dac channel 0 offset 3487 * address 1 == dac channel 0 gain 3488 * address 2 == dac channel 1 offset 3489 * address 3 == dac channel 1 gain 3490 * address 4 == fine adc offset 3491 * address 5 == coarse adc offset 3492 * address 6 == coarse adc gain 3493 * address 7 == fine adc gain 3494 */ 3495 /* 3496 * pci-6402/16 uses all 8 channels for dac: 3497 * address 0 == dac channel 0 fine gain 3498 * address 1 == dac channel 0 coarse gain 3499 * address 2 == dac channel 0 coarse offset 3500 * address 3 == dac channel 1 coarse offset 3501 * address 4 == dac channel 1 fine gain 3502 * address 5 == dac channel 1 coarse gain 3503 * address 6 == dac channel 0 fine offset 3504 * address 7 == dac channel 1 fine offset 3505 */ 3506 3507 static int caldac_8800_write(struct comedi_device *dev, unsigned int address, 3508 u8 value) 3509 { 3510 struct pcidas64_private *devpriv = dev->private; 3511 static const int num_caldac_channels = 8; 3512 static const int bitstream_length = 11; 3513 unsigned int bitstream = ((address & 0x7) << 8) | value; 3514 unsigned int bit, register_bits; 3515 static const int caldac_8800_udelay = 1; 3516 3517 if (address >= num_caldac_channels) { 3518 dev_err(dev->class_dev, "illegal caldac channel\n"); 3519 return -1; 3520 } 3521 for (bit = 1 << (bitstream_length - 1); bit; bit >>= 1) { 3522 register_bits = 0; 3523 if (bitstream & bit) 3524 register_bits |= SERIAL_DATA_IN_BIT; 3525 udelay(caldac_8800_udelay); 3526 writew(register_bits, devpriv->main_iobase + CALIBRATION_REG); 3527 register_bits |= SERIAL_CLOCK_BIT; 3528 udelay(caldac_8800_udelay); 3529 writew(register_bits, devpriv->main_iobase + CALIBRATION_REG); 3530 } 3531 udelay(caldac_8800_udelay); 3532 writew(SELECT_8800_BIT, devpriv->main_iobase + CALIBRATION_REG); 3533 udelay(caldac_8800_udelay); 3534 writew(0, devpriv->main_iobase + CALIBRATION_REG); 3535 udelay(caldac_8800_udelay); 3536 return 0; 3537 } 3538 3539 /* 4020 caldacs */ 3540 static int caldac_i2c_write(struct comedi_device *dev, 3541 unsigned int caldac_channel, unsigned int value) 3542 { 3543 u8 serial_bytes[3]; 3544 u8 i2c_addr; 3545 enum pointer_bits { 3546 /* manual has gain and offset bits switched */ 3547 OFFSET_0_2 = 0x1, 3548 GAIN_0_2 = 0x2, 3549 OFFSET_1_3 = 0x4, 3550 GAIN_1_3 = 0x8, 3551 }; 3552 enum data_bits { 3553 NOT_CLEAR_REGISTERS = 0x20, 3554 }; 3555 3556 switch (caldac_channel) { 3557 case 0: /* chan 0 offset */ 3558 i2c_addr = CALDAC0_I2C_ADDR; 3559 serial_bytes[0] = OFFSET_0_2; 3560 break; 3561 case 1: /* chan 1 offset */ 3562 i2c_addr = CALDAC0_I2C_ADDR; 3563 serial_bytes[0] = OFFSET_1_3; 3564 break; 3565 case 2: /* chan 2 offset */ 3566 i2c_addr = CALDAC1_I2C_ADDR; 3567 serial_bytes[0] = OFFSET_0_2; 3568 break; 3569 case 3: /* chan 3 offset */ 3570 i2c_addr = CALDAC1_I2C_ADDR; 3571 serial_bytes[0] = OFFSET_1_3; 3572 break; 3573 case 4: /* chan 0 gain */ 3574 i2c_addr = CALDAC0_I2C_ADDR; 3575 serial_bytes[0] = GAIN_0_2; 3576 break; 3577 case 5: /* chan 1 gain */ 3578 i2c_addr = CALDAC0_I2C_ADDR; 3579 serial_bytes[0] = GAIN_1_3; 3580 break; 3581 case 6: /* chan 2 gain */ 3582 i2c_addr = CALDAC1_I2C_ADDR; 3583 serial_bytes[0] = GAIN_0_2; 3584 break; 3585 case 7: /* chan 3 gain */ 3586 i2c_addr = CALDAC1_I2C_ADDR; 3587 serial_bytes[0] = GAIN_1_3; 3588 break; 3589 default: 3590 dev_err(dev->class_dev, "invalid caldac channel\n"); 3591 return -1; 3592 } 3593 serial_bytes[1] = NOT_CLEAR_REGISTERS | ((value >> 8) & 0xf); 3594 serial_bytes[2] = value & 0xff; 3595 i2c_write(dev, i2c_addr, serial_bytes, 3); 3596 return 0; 3597 } 3598 3599 static void caldac_write(struct comedi_device *dev, unsigned int channel, 3600 unsigned int value) 3601 { 3602 const struct pcidas64_board *board = dev->board_ptr; 3603 3604 switch (board->layout) { 3605 case LAYOUT_60XX: 3606 case LAYOUT_64XX: 3607 caldac_8800_write(dev, channel, value); 3608 break; 3609 case LAYOUT_4020: 3610 caldac_i2c_write(dev, channel, value); 3611 break; 3612 default: 3613 break; 3614 } 3615 } 3616 3617 static int cb_pcidas64_calib_insn_write(struct comedi_device *dev, 3618 struct comedi_subdevice *s, 3619 struct comedi_insn *insn, 3620 unsigned int *data) 3621 { 3622 unsigned int chan = CR_CHAN(insn->chanspec); 3623 3624 /* 3625 * Programming the calib device is slow. Only write the 3626 * last data value if the value has changed. 3627 */ 3628 if (insn->n) { 3629 unsigned int val = data[insn->n - 1]; 3630 3631 if (s->readback[chan] != val) { 3632 caldac_write(dev, chan, val); 3633 s->readback[chan] = val; 3634 } 3635 } 3636 3637 return insn->n; 3638 } 3639 3640 static void ad8402_write(struct comedi_device *dev, unsigned int channel, 3641 unsigned int value) 3642 { 3643 struct pcidas64_private *devpriv = dev->private; 3644 static const int bitstream_length = 10; 3645 unsigned int bit, register_bits; 3646 unsigned int bitstream = ((channel & 0x3) << 8) | (value & 0xff); 3647 static const int ad8402_udelay = 1; 3648 3649 register_bits = SELECT_8402_64XX_BIT; 3650 udelay(ad8402_udelay); 3651 writew(register_bits, devpriv->main_iobase + CALIBRATION_REG); 3652 3653 for (bit = 1 << (bitstream_length - 1); bit; bit >>= 1) { 3654 if (bitstream & bit) 3655 register_bits |= SERIAL_DATA_IN_BIT; 3656 else 3657 register_bits &= ~SERIAL_DATA_IN_BIT; 3658 udelay(ad8402_udelay); 3659 writew(register_bits, devpriv->main_iobase + CALIBRATION_REG); 3660 udelay(ad8402_udelay); 3661 writew(register_bits | SERIAL_CLOCK_BIT, 3662 devpriv->main_iobase + CALIBRATION_REG); 3663 } 3664 3665 udelay(ad8402_udelay); 3666 writew(0, devpriv->main_iobase + CALIBRATION_REG); 3667 } 3668 3669 /* for pci-das6402/16, channel 0 is analog input gain and channel 1 is offset */ 3670 static int cb_pcidas64_ad8402_insn_write(struct comedi_device *dev, 3671 struct comedi_subdevice *s, 3672 struct comedi_insn *insn, 3673 unsigned int *data) 3674 { 3675 unsigned int chan = CR_CHAN(insn->chanspec); 3676 3677 /* 3678 * Programming the calib device is slow. Only write the 3679 * last data value if the value has changed. 3680 */ 3681 if (insn->n) { 3682 unsigned int val = data[insn->n - 1]; 3683 3684 if (s->readback[chan] != val) { 3685 ad8402_write(dev, chan, val); 3686 s->readback[chan] = val; 3687 } 3688 } 3689 3690 return insn->n; 3691 } 3692 3693 static u16 read_eeprom(struct comedi_device *dev, u8 address) 3694 { 3695 struct pcidas64_private *devpriv = dev->private; 3696 static const int bitstream_length = 11; 3697 static const int read_command = 0x6; 3698 unsigned int bitstream = (read_command << 8) | address; 3699 unsigned int bit; 3700 void __iomem * const plx_control_addr = 3701 devpriv->plx9080_iobase + PLX_REG_CNTRL; 3702 u16 value; 3703 static const int value_length = 16; 3704 static const int eeprom_udelay = 1; 3705 3706 udelay(eeprom_udelay); 3707 devpriv->plx_control_bits &= ~PLX_CNTRL_EESK & ~PLX_CNTRL_EECS; 3708 /* make sure we don't send anything to the i2c bus on 4020 */ 3709 devpriv->plx_control_bits |= PLX_CNTRL_USERO; 3710 writel(devpriv->plx_control_bits, plx_control_addr); 3711 /* activate serial eeprom */ 3712 udelay(eeprom_udelay); 3713 devpriv->plx_control_bits |= PLX_CNTRL_EECS; 3714 writel(devpriv->plx_control_bits, plx_control_addr); 3715 3716 /* write read command and desired memory address */ 3717 for (bit = 1 << (bitstream_length - 1); bit; bit >>= 1) { 3718 /* set bit to be written */ 3719 udelay(eeprom_udelay); 3720 if (bitstream & bit) 3721 devpriv->plx_control_bits |= PLX_CNTRL_EEWB; 3722 else 3723 devpriv->plx_control_bits &= ~PLX_CNTRL_EEWB; 3724 writel(devpriv->plx_control_bits, plx_control_addr); 3725 /* clock in bit */ 3726 udelay(eeprom_udelay); 3727 devpriv->plx_control_bits |= PLX_CNTRL_EESK; 3728 writel(devpriv->plx_control_bits, plx_control_addr); 3729 udelay(eeprom_udelay); 3730 devpriv->plx_control_bits &= ~PLX_CNTRL_EESK; 3731 writel(devpriv->plx_control_bits, plx_control_addr); 3732 } 3733 /* read back value from eeprom memory location */ 3734 value = 0; 3735 for (bit = 1 << (value_length - 1); bit; bit >>= 1) { 3736 /* clock out bit */ 3737 udelay(eeprom_udelay); 3738 devpriv->plx_control_bits |= PLX_CNTRL_EESK; 3739 writel(devpriv->plx_control_bits, plx_control_addr); 3740 udelay(eeprom_udelay); 3741 devpriv->plx_control_bits &= ~PLX_CNTRL_EESK; 3742 writel(devpriv->plx_control_bits, plx_control_addr); 3743 udelay(eeprom_udelay); 3744 if (readl(plx_control_addr) & PLX_CNTRL_EERB) 3745 value |= bit; 3746 } 3747 3748 /* deactivate eeprom serial input */ 3749 udelay(eeprom_udelay); 3750 devpriv->plx_control_bits &= ~PLX_CNTRL_EECS; 3751 writel(devpriv->plx_control_bits, plx_control_addr); 3752 3753 return value; 3754 } 3755 3756 static int eeprom_read_insn(struct comedi_device *dev, 3757 struct comedi_subdevice *s, 3758 struct comedi_insn *insn, unsigned int *data) 3759 { 3760 unsigned int val; 3761 unsigned int i; 3762 3763 if (insn->n) { 3764 /* No point reading the same EEPROM location more than once. */ 3765 val = read_eeprom(dev, CR_CHAN(insn->chanspec)); 3766 for (i = 0; i < insn->n; i++) 3767 data[i] = val; 3768 } 3769 3770 return insn->n; 3771 } 3772 3773 /* Allocate and initialize the subdevice structures. */ 3774 static int setup_subdevices(struct comedi_device *dev) 3775 { 3776 const struct pcidas64_board *board = dev->board_ptr; 3777 struct pcidas64_private *devpriv = dev->private; 3778 struct comedi_subdevice *s; 3779 int i; 3780 int ret; 3781 3782 ret = comedi_alloc_subdevices(dev, 10); 3783 if (ret) 3784 return ret; 3785 3786 s = &dev->subdevices[0]; 3787 /* analog input subdevice */ 3788 dev->read_subdev = s; 3789 s->type = COMEDI_SUBD_AI; 3790 s->subdev_flags = SDF_READABLE | SDF_GROUND | SDF_DITHER | SDF_CMD_READ; 3791 if (board->layout == LAYOUT_60XX) 3792 s->subdev_flags |= SDF_COMMON | SDF_DIFF; 3793 else if (board->layout == LAYOUT_64XX) 3794 s->subdev_flags |= SDF_DIFF; 3795 /* XXX Number of inputs in differential mode is ignored */ 3796 s->n_chan = board->ai_se_chans; 3797 s->len_chanlist = 0x2000; 3798 s->maxdata = (1 << board->ai_bits) - 1; 3799 s->range_table = board->ai_range_table; 3800 s->insn_read = ai_rinsn; 3801 s->insn_config = ai_config_insn; 3802 s->do_cmd = ai_cmd; 3803 s->do_cmdtest = ai_cmdtest; 3804 s->cancel = ai_cancel; 3805 if (board->layout == LAYOUT_4020) { 3806 u8 data; 3807 /* 3808 * set adc to read from inputs 3809 * (not internal calibration sources) 3810 */ 3811 devpriv->i2c_cal_range_bits = adc_src_4020_bits(4); 3812 /* set channels to +-5 volt input ranges */ 3813 for (i = 0; i < s->n_chan; i++) 3814 devpriv->i2c_cal_range_bits |= attenuate_bit(i); 3815 data = devpriv->i2c_cal_range_bits; 3816 i2c_write(dev, RANGE_CAL_I2C_ADDR, &data, sizeof(data)); 3817 } 3818 3819 /* analog output subdevice */ 3820 s = &dev->subdevices[1]; 3821 if (board->ao_nchan) { 3822 s->type = COMEDI_SUBD_AO; 3823 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | 3824 SDF_GROUND | SDF_CMD_WRITE; 3825 s->n_chan = board->ao_nchan; 3826 s->maxdata = (1 << board->ao_bits) - 1; 3827 s->range_table = board->ao_range_table; 3828 s->insn_write = ao_winsn; 3829 3830 ret = comedi_alloc_subdev_readback(s); 3831 if (ret) 3832 return ret; 3833 3834 if (ao_cmd_is_supported(board)) { 3835 dev->write_subdev = s; 3836 s->do_cmdtest = ao_cmdtest; 3837 s->do_cmd = ao_cmd; 3838 s->len_chanlist = board->ao_nchan; 3839 s->cancel = ao_cancel; 3840 } 3841 } else { 3842 s->type = COMEDI_SUBD_UNUSED; 3843 } 3844 3845 /* digital input */ 3846 s = &dev->subdevices[2]; 3847 if (board->layout == LAYOUT_64XX) { 3848 s->type = COMEDI_SUBD_DI; 3849 s->subdev_flags = SDF_READABLE; 3850 s->n_chan = 4; 3851 s->maxdata = 1; 3852 s->range_table = &range_digital; 3853 s->insn_bits = di_rbits; 3854 } else { 3855 s->type = COMEDI_SUBD_UNUSED; 3856 } 3857 3858 /* digital output */ 3859 if (board->layout == LAYOUT_64XX) { 3860 s = &dev->subdevices[3]; 3861 s->type = COMEDI_SUBD_DO; 3862 s->subdev_flags = SDF_WRITABLE; 3863 s->n_chan = 4; 3864 s->maxdata = 1; 3865 s->range_table = &range_digital; 3866 s->insn_bits = do_wbits; 3867 } else { 3868 s->type = COMEDI_SUBD_UNUSED; 3869 } 3870 3871 /* 8255 */ 3872 s = &dev->subdevices[4]; 3873 if (board->has_8255) { 3874 if (board->layout == LAYOUT_4020) { 3875 ret = subdev_8255_cb_init(dev, s, dio_callback_4020, 3876 I8255_4020_REG); 3877 } else { 3878 ret = subdev_8255_mm_init(dev, s, DIO_8255_OFFSET); 3879 } 3880 if (ret) 3881 return ret; 3882 } else { 3883 s->type = COMEDI_SUBD_UNUSED; 3884 } 3885 3886 /* 8 channel dio for 60xx */ 3887 s = &dev->subdevices[5]; 3888 if (board->layout == LAYOUT_60XX) { 3889 s->type = COMEDI_SUBD_DIO; 3890 s->subdev_flags = SDF_WRITABLE | SDF_READABLE; 3891 s->n_chan = 8; 3892 s->maxdata = 1; 3893 s->range_table = &range_digital; 3894 s->insn_config = dio_60xx_config_insn; 3895 s->insn_bits = dio_60xx_wbits; 3896 } else { 3897 s->type = COMEDI_SUBD_UNUSED; 3898 } 3899 3900 /* caldac */ 3901 s = &dev->subdevices[6]; 3902 s->type = COMEDI_SUBD_CALIB; 3903 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL; 3904 s->n_chan = 8; 3905 if (board->layout == LAYOUT_4020) 3906 s->maxdata = 0xfff; 3907 else 3908 s->maxdata = 0xff; 3909 s->insn_write = cb_pcidas64_calib_insn_write; 3910 3911 ret = comedi_alloc_subdev_readback(s); 3912 if (ret) 3913 return ret; 3914 3915 for (i = 0; i < s->n_chan; i++) { 3916 caldac_write(dev, i, s->maxdata / 2); 3917 s->readback[i] = s->maxdata / 2; 3918 } 3919 3920 /* 2 channel ad8402 potentiometer */ 3921 s = &dev->subdevices[7]; 3922 if (board->layout == LAYOUT_64XX) { 3923 s->type = COMEDI_SUBD_CALIB; 3924 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL; 3925 s->n_chan = 2; 3926 s->maxdata = 0xff; 3927 s->insn_write = cb_pcidas64_ad8402_insn_write; 3928 3929 ret = comedi_alloc_subdev_readback(s); 3930 if (ret) 3931 return ret; 3932 3933 for (i = 0; i < s->n_chan; i++) { 3934 ad8402_write(dev, i, s->maxdata / 2); 3935 s->readback[i] = s->maxdata / 2; 3936 } 3937 } else { 3938 s->type = COMEDI_SUBD_UNUSED; 3939 } 3940 3941 /* serial EEPROM, if present */ 3942 s = &dev->subdevices[8]; 3943 if (readl(devpriv->plx9080_iobase + PLX_REG_CNTRL) & 3944 PLX_CNTRL_EEPRESENT) { 3945 s->type = COMEDI_SUBD_MEMORY; 3946 s->subdev_flags = SDF_READABLE | SDF_INTERNAL; 3947 s->n_chan = 128; 3948 s->maxdata = 0xffff; 3949 s->insn_read = eeprom_read_insn; 3950 } else { 3951 s->type = COMEDI_SUBD_UNUSED; 3952 } 3953 3954 /* user counter subd XXX */ 3955 s = &dev->subdevices[9]; 3956 s->type = COMEDI_SUBD_UNUSED; 3957 3958 return 0; 3959 } 3960 3961 static int auto_attach(struct comedi_device *dev, 3962 unsigned long context) 3963 { 3964 struct pci_dev *pcidev = comedi_to_pci_dev(dev); 3965 const struct pcidas64_board *board = NULL; 3966 struct pcidas64_private *devpriv; 3967 u32 local_range, local_decode; 3968 int retval; 3969 3970 if (context < ARRAY_SIZE(pcidas64_boards)) 3971 board = &pcidas64_boards[context]; 3972 if (!board) 3973 return -ENODEV; 3974 dev->board_ptr = board; 3975 3976 devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv)); 3977 if (!devpriv) 3978 return -ENOMEM; 3979 3980 retval = comedi_pci_enable(dev); 3981 if (retval) 3982 return retval; 3983 pci_set_master(pcidev); 3984 3985 /* Initialize dev->board_name */ 3986 dev->board_name = board->name; 3987 3988 devpriv->main_phys_iobase = pci_resource_start(pcidev, 2); 3989 devpriv->dio_counter_phys_iobase = pci_resource_start(pcidev, 3); 3990 3991 devpriv->plx9080_iobase = pci_ioremap_bar(pcidev, 0); 3992 devpriv->main_iobase = pci_ioremap_bar(pcidev, 2); 3993 dev->mmio = pci_ioremap_bar(pcidev, 3); 3994 3995 if (!devpriv->plx9080_iobase || !devpriv->main_iobase || !dev->mmio) { 3996 dev_warn(dev->class_dev, "failed to remap io memory\n"); 3997 return -ENOMEM; 3998 } 3999 4000 /* figure out what local addresses are */ 4001 local_range = readl(devpriv->plx9080_iobase + PLX_REG_LAS0RR) & 4002 PLX_LASRR_MEM_MASK; 4003 local_decode = readl(devpriv->plx9080_iobase + PLX_REG_LAS0BA) & 4004 local_range & PLX_LASBA_MEM_MASK; 4005 devpriv->local0_iobase = ((u32)devpriv->main_phys_iobase & 4006 ~local_range) | local_decode; 4007 local_range = readl(devpriv->plx9080_iobase + PLX_REG_LAS1RR) & 4008 PLX_LASRR_MEM_MASK; 4009 local_decode = readl(devpriv->plx9080_iobase + PLX_REG_LAS1BA) & 4010 local_range & PLX_LASBA_MEM_MASK; 4011 devpriv->local1_iobase = ((u32)devpriv->dio_counter_phys_iobase & 4012 ~local_range) | local_decode; 4013 4014 retval = alloc_and_init_dma_members(dev); 4015 if (retval < 0) 4016 return retval; 4017 4018 devpriv->hw_revision = 4019 hw_revision(dev, readw(devpriv->main_iobase + HW_STATUS_REG)); 4020 dev_dbg(dev->class_dev, "stc hardware revision %i\n", 4021 devpriv->hw_revision); 4022 init_plx9080(dev); 4023 init_stc_registers(dev); 4024 4025 retval = request_irq(pcidev->irq, handle_interrupt, IRQF_SHARED, 4026 "cb_pcidas64", dev); 4027 if (retval) { 4028 dev_dbg(dev->class_dev, "unable to allocate irq %u\n", 4029 pcidev->irq); 4030 return retval; 4031 } 4032 dev->irq = pcidev->irq; 4033 dev_dbg(dev->class_dev, "irq %u\n", dev->irq); 4034 4035 retval = setup_subdevices(dev); 4036 if (retval < 0) 4037 return retval; 4038 4039 return 0; 4040 } 4041 4042 static void detach(struct comedi_device *dev) 4043 { 4044 struct pcidas64_private *devpriv = dev->private; 4045 4046 if (dev->irq) 4047 free_irq(dev->irq, dev); 4048 if (devpriv) { 4049 if (devpriv->plx9080_iobase) { 4050 disable_plx_interrupts(dev); 4051 iounmap(devpriv->plx9080_iobase); 4052 } 4053 if (devpriv->main_iobase) 4054 iounmap(devpriv->main_iobase); 4055 if (dev->mmio) 4056 iounmap(dev->mmio); 4057 } 4058 comedi_pci_disable(dev); 4059 cb_pcidas64_free_dma(dev); 4060 } 4061 4062 static struct comedi_driver cb_pcidas64_driver = { 4063 .driver_name = "cb_pcidas64", 4064 .module = THIS_MODULE, 4065 .auto_attach = auto_attach, 4066 .detach = detach, 4067 }; 4068 4069 static int cb_pcidas64_pci_probe(struct pci_dev *dev, 4070 const struct pci_device_id *id) 4071 { 4072 return comedi_pci_auto_config(dev, &cb_pcidas64_driver, 4073 id->driver_data); 4074 } 4075 4076 static const struct pci_device_id cb_pcidas64_pci_table[] = { 4077 { PCI_VDEVICE(CB, 0x001d), BOARD_PCIDAS6402_16 }, 4078 { PCI_VDEVICE(CB, 0x001e), BOARD_PCIDAS6402_12 }, 4079 { PCI_VDEVICE(CB, 0x0035), BOARD_PCIDAS64_M1_16 }, 4080 { PCI_VDEVICE(CB, 0x0036), BOARD_PCIDAS64_M2_16 }, 4081 { PCI_VDEVICE(CB, 0x0037), BOARD_PCIDAS64_M3_16 }, 4082 { PCI_VDEVICE(CB, 0x0052), BOARD_PCIDAS4020_12 }, 4083 { PCI_VDEVICE(CB, 0x005d), BOARD_PCIDAS6023 }, 4084 { PCI_VDEVICE(CB, 0x005e), BOARD_PCIDAS6025 }, 4085 { PCI_VDEVICE(CB, 0x005f), BOARD_PCIDAS6030 }, 4086 { PCI_VDEVICE(CB, 0x0060), BOARD_PCIDAS6031 }, 4087 { PCI_VDEVICE(CB, 0x0061), BOARD_PCIDAS6032 }, 4088 { PCI_VDEVICE(CB, 0x0062), BOARD_PCIDAS6033 }, 4089 { PCI_VDEVICE(CB, 0x0063), BOARD_PCIDAS6034 }, 4090 { PCI_VDEVICE(CB, 0x0064), BOARD_PCIDAS6035 }, 4091 { PCI_VDEVICE(CB, 0x0065), BOARD_PCIDAS6040 }, 4092 { PCI_VDEVICE(CB, 0x0066), BOARD_PCIDAS6052 }, 4093 { PCI_VDEVICE(CB, 0x0067), BOARD_PCIDAS6070 }, 4094 { PCI_VDEVICE(CB, 0x0068), BOARD_PCIDAS6071 }, 4095 { PCI_VDEVICE(CB, 0x006f), BOARD_PCIDAS6036 }, 4096 { PCI_VDEVICE(CB, 0x0078), BOARD_PCIDAS6013 }, 4097 { PCI_VDEVICE(CB, 0x0079), BOARD_PCIDAS6014 }, 4098 { 0 } 4099 }; 4100 MODULE_DEVICE_TABLE(pci, cb_pcidas64_pci_table); 4101 4102 static struct pci_driver cb_pcidas64_pci_driver = { 4103 .name = "cb_pcidas64", 4104 .id_table = cb_pcidas64_pci_table, 4105 .probe = cb_pcidas64_pci_probe, 4106 .remove = comedi_pci_auto_unconfig, 4107 }; 4108 module_comedi_pci_driver(cb_pcidas64_driver, cb_pcidas64_pci_driver); 4109 4110 MODULE_AUTHOR("Comedi https://www.comedi.org"); 4111 MODULE_DESCRIPTION("Comedi low-level driver"); 4112 MODULE_LICENSE("GPL"); 4113