1*c28ca80bSNikita Shubin // SPDX-License-Identifier: GPL-2.0 2*c28ca80bSNikita Shubin /* 3*c28ca80bSNikita Shubin * Cirrus Logic EP93xx timer driver. 4*c28ca80bSNikita Shubin * Copyright (C) 2021 Nikita Shubin <nikita.shubin@maquefel.me> 5*c28ca80bSNikita Shubin * 6*c28ca80bSNikita Shubin * Based on a rewrite of arch/arm/mach-ep93xx/timer.c: 7*c28ca80bSNikita Shubin */ 8*c28ca80bSNikita Shubin 9*c28ca80bSNikita Shubin #include <linux/clockchips.h> 10*c28ca80bSNikita Shubin #include <linux/clocksource.h> 11*c28ca80bSNikita Shubin #include <linux/init.h> 12*c28ca80bSNikita Shubin #include <linux/interrupt.h> 13*c28ca80bSNikita Shubin #include <linux/io.h> 14*c28ca80bSNikita Shubin #include <linux/io-64-nonatomic-lo-hi.h> 15*c28ca80bSNikita Shubin #include <linux/irq.h> 16*c28ca80bSNikita Shubin #include <linux/kernel.h> 17*c28ca80bSNikita Shubin #include <linux/of_address.h> 18*c28ca80bSNikita Shubin #include <linux/of_irq.h> 19*c28ca80bSNikita Shubin #include <linux/sched_clock.h> 20*c28ca80bSNikita Shubin 21*c28ca80bSNikita Shubin #include <asm/mach/time.h> 22*c28ca80bSNikita Shubin 23*c28ca80bSNikita Shubin /************************************************************************* 24*c28ca80bSNikita Shubin * Timer handling for EP93xx 25*c28ca80bSNikita Shubin ************************************************************************* 26*c28ca80bSNikita Shubin * The ep93xx has four internal timers. Timers 1, 2 (both 16 bit) and 27*c28ca80bSNikita Shubin * 3 (32 bit) count down at 508 kHz, are self-reloading, and can generate 28*c28ca80bSNikita Shubin * an interrupt on underflow. Timer 4 (40 bit) counts down at 983.04 kHz, 29*c28ca80bSNikita Shubin * is free-running, and can't generate interrupts. 30*c28ca80bSNikita Shubin * 31*c28ca80bSNikita Shubin * The 508 kHz timers are ideal for use for the timer interrupt, as the 32*c28ca80bSNikita Shubin * most common values of HZ divide 508 kHz nicely. We pick the 32 bit 33*c28ca80bSNikita Shubin * timer (timer 3) to get as long sleep intervals as possible when using 34*c28ca80bSNikita Shubin * CONFIG_NO_HZ. 35*c28ca80bSNikita Shubin * 36*c28ca80bSNikita Shubin * The higher clock rate of timer 4 makes it a better choice than the 37*c28ca80bSNikita Shubin * other timers for use as clock source and for sched_clock(), providing 38*c28ca80bSNikita Shubin * a stable 40 bit time base. 39*c28ca80bSNikita Shubin ************************************************************************* 40*c28ca80bSNikita Shubin */ 41*c28ca80bSNikita Shubin 42*c28ca80bSNikita Shubin #define EP93XX_TIMER1_LOAD 0x00 43*c28ca80bSNikita Shubin #define EP93XX_TIMER1_VALUE 0x04 44*c28ca80bSNikita Shubin #define EP93XX_TIMER1_CONTROL 0x08 45*c28ca80bSNikita Shubin #define EP93XX_TIMER123_CONTROL_ENABLE BIT(7) 46*c28ca80bSNikita Shubin #define EP93XX_TIMER123_CONTROL_MODE BIT(6) 47*c28ca80bSNikita Shubin #define EP93XX_TIMER123_CONTROL_CLKSEL BIT(3) 48*c28ca80bSNikita Shubin #define EP93XX_TIMER1_CLEAR 0x0c 49*c28ca80bSNikita Shubin #define EP93XX_TIMER2_LOAD 0x20 50*c28ca80bSNikita Shubin #define EP93XX_TIMER2_VALUE 0x24 51*c28ca80bSNikita Shubin #define EP93XX_TIMER2_CONTROL 0x28 52*c28ca80bSNikita Shubin #define EP93XX_TIMER2_CLEAR 0x2c 53*c28ca80bSNikita Shubin /* 54*c28ca80bSNikita Shubin * This read-only register contains the low word of the time stamp debug timer 55*c28ca80bSNikita Shubin * ( Timer4). When this register is read, the high byte of the Timer4 counter is 56*c28ca80bSNikita Shubin * saved in the Timer4ValueHigh register. 57*c28ca80bSNikita Shubin */ 58*c28ca80bSNikita Shubin #define EP93XX_TIMER4_VALUE_LOW 0x60 59*c28ca80bSNikita Shubin #define EP93XX_TIMER4_VALUE_HIGH 0x64 60*c28ca80bSNikita Shubin #define EP93XX_TIMER4_VALUE_HIGH_ENABLE BIT(8) 61*c28ca80bSNikita Shubin #define EP93XX_TIMER3_LOAD 0x80 62*c28ca80bSNikita Shubin #define EP93XX_TIMER3_VALUE 0x84 63*c28ca80bSNikita Shubin #define EP93XX_TIMER3_CONTROL 0x88 64*c28ca80bSNikita Shubin #define EP93XX_TIMER3_CLEAR 0x8c 65*c28ca80bSNikita Shubin 66*c28ca80bSNikita Shubin #define EP93XX_TIMER123_RATE 508469 67*c28ca80bSNikita Shubin #define EP93XX_TIMER4_RATE 983040 68*c28ca80bSNikita Shubin 69*c28ca80bSNikita Shubin struct ep93xx_tcu { 70*c28ca80bSNikita Shubin void __iomem *base; 71*c28ca80bSNikita Shubin }; 72*c28ca80bSNikita Shubin 73*c28ca80bSNikita Shubin static struct ep93xx_tcu *ep93xx_tcu; 74*c28ca80bSNikita Shubin 75*c28ca80bSNikita Shubin static u64 ep93xx_clocksource_read(struct clocksource *c) 76*c28ca80bSNikita Shubin { 77*c28ca80bSNikita Shubin struct ep93xx_tcu *tcu = ep93xx_tcu; 78*c28ca80bSNikita Shubin 79*c28ca80bSNikita Shubin return lo_hi_readq(tcu->base + EP93XX_TIMER4_VALUE_LOW) & GENMASK_ULL(39, 0); 80*c28ca80bSNikita Shubin } 81*c28ca80bSNikita Shubin 82*c28ca80bSNikita Shubin static u64 notrace ep93xx_read_sched_clock(void) 83*c28ca80bSNikita Shubin { 84*c28ca80bSNikita Shubin return ep93xx_clocksource_read(NULL); 85*c28ca80bSNikita Shubin } 86*c28ca80bSNikita Shubin 87*c28ca80bSNikita Shubin static int ep93xx_clkevt_set_next_event(unsigned long next, 88*c28ca80bSNikita Shubin struct clock_event_device *evt) 89*c28ca80bSNikita Shubin { 90*c28ca80bSNikita Shubin struct ep93xx_tcu *tcu = ep93xx_tcu; 91*c28ca80bSNikita Shubin /* Default mode: periodic, off, 508 kHz */ 92*c28ca80bSNikita Shubin u32 tmode = EP93XX_TIMER123_CONTROL_MODE | 93*c28ca80bSNikita Shubin EP93XX_TIMER123_CONTROL_CLKSEL; 94*c28ca80bSNikita Shubin 95*c28ca80bSNikita Shubin /* Clear timer */ 96*c28ca80bSNikita Shubin writel(tmode, tcu->base + EP93XX_TIMER3_CONTROL); 97*c28ca80bSNikita Shubin 98*c28ca80bSNikita Shubin /* Set next event */ 99*c28ca80bSNikita Shubin writel(next, tcu->base + EP93XX_TIMER3_LOAD); 100*c28ca80bSNikita Shubin writel(tmode | EP93XX_TIMER123_CONTROL_ENABLE, 101*c28ca80bSNikita Shubin tcu->base + EP93XX_TIMER3_CONTROL); 102*c28ca80bSNikita Shubin return 0; 103*c28ca80bSNikita Shubin } 104*c28ca80bSNikita Shubin 105*c28ca80bSNikita Shubin static int ep93xx_clkevt_shutdown(struct clock_event_device *evt) 106*c28ca80bSNikita Shubin { 107*c28ca80bSNikita Shubin struct ep93xx_tcu *tcu = ep93xx_tcu; 108*c28ca80bSNikita Shubin /* Disable timer */ 109*c28ca80bSNikita Shubin writel(0, tcu->base + EP93XX_TIMER3_CONTROL); 110*c28ca80bSNikita Shubin 111*c28ca80bSNikita Shubin return 0; 112*c28ca80bSNikita Shubin } 113*c28ca80bSNikita Shubin 114*c28ca80bSNikita Shubin static struct clock_event_device ep93xx_clockevent = { 115*c28ca80bSNikita Shubin .name = "timer1", 116*c28ca80bSNikita Shubin .features = CLOCK_EVT_FEAT_ONESHOT, 117*c28ca80bSNikita Shubin .set_state_shutdown = ep93xx_clkevt_shutdown, 118*c28ca80bSNikita Shubin .set_state_oneshot = ep93xx_clkevt_shutdown, 119*c28ca80bSNikita Shubin .tick_resume = ep93xx_clkevt_shutdown, 120*c28ca80bSNikita Shubin .set_next_event = ep93xx_clkevt_set_next_event, 121*c28ca80bSNikita Shubin .rating = 300, 122*c28ca80bSNikita Shubin }; 123*c28ca80bSNikita Shubin 124*c28ca80bSNikita Shubin static irqreturn_t ep93xx_timer_interrupt(int irq, void *dev_id) 125*c28ca80bSNikita Shubin { 126*c28ca80bSNikita Shubin struct ep93xx_tcu *tcu = ep93xx_tcu; 127*c28ca80bSNikita Shubin struct clock_event_device *evt = dev_id; 128*c28ca80bSNikita Shubin 129*c28ca80bSNikita Shubin /* Writing any value clears the timer interrupt */ 130*c28ca80bSNikita Shubin writel(1, tcu->base + EP93XX_TIMER3_CLEAR); 131*c28ca80bSNikita Shubin 132*c28ca80bSNikita Shubin evt->event_handler(evt); 133*c28ca80bSNikita Shubin 134*c28ca80bSNikita Shubin return IRQ_HANDLED; 135*c28ca80bSNikita Shubin } 136*c28ca80bSNikita Shubin 137*c28ca80bSNikita Shubin static int __init ep93xx_timer_of_init(struct device_node *np) 138*c28ca80bSNikita Shubin { 139*c28ca80bSNikita Shubin int irq; 140*c28ca80bSNikita Shubin unsigned long flags = IRQF_TIMER | IRQF_IRQPOLL; 141*c28ca80bSNikita Shubin struct ep93xx_tcu *tcu; 142*c28ca80bSNikita Shubin int ret; 143*c28ca80bSNikita Shubin 144*c28ca80bSNikita Shubin tcu = kzalloc(sizeof(*tcu), GFP_KERNEL); 145*c28ca80bSNikita Shubin if (!tcu) 146*c28ca80bSNikita Shubin return -ENOMEM; 147*c28ca80bSNikita Shubin 148*c28ca80bSNikita Shubin tcu->base = of_iomap(np, 0); 149*c28ca80bSNikita Shubin if (!tcu->base) { 150*c28ca80bSNikita Shubin pr_err("Can't remap registers\n"); 151*c28ca80bSNikita Shubin ret = -ENXIO; 152*c28ca80bSNikita Shubin goto out_free; 153*c28ca80bSNikita Shubin } 154*c28ca80bSNikita Shubin 155*c28ca80bSNikita Shubin ep93xx_tcu = tcu; 156*c28ca80bSNikita Shubin 157*c28ca80bSNikita Shubin irq = irq_of_parse_and_map(np, 0); 158*c28ca80bSNikita Shubin if (irq == 0) 159*c28ca80bSNikita Shubin irq = -EINVAL; 160*c28ca80bSNikita Shubin if (irq < 0) { 161*c28ca80bSNikita Shubin pr_err("EP93XX Timer Can't parse IRQ %d", irq); 162*c28ca80bSNikita Shubin goto out_free; 163*c28ca80bSNikita Shubin } 164*c28ca80bSNikita Shubin 165*c28ca80bSNikita Shubin /* Enable and register clocksource and sched_clock on timer 4 */ 166*c28ca80bSNikita Shubin writel(EP93XX_TIMER4_VALUE_HIGH_ENABLE, 167*c28ca80bSNikita Shubin tcu->base + EP93XX_TIMER4_VALUE_HIGH); 168*c28ca80bSNikita Shubin clocksource_mmio_init(NULL, "timer4", 169*c28ca80bSNikita Shubin EP93XX_TIMER4_RATE, 200, 40, 170*c28ca80bSNikita Shubin ep93xx_clocksource_read); 171*c28ca80bSNikita Shubin sched_clock_register(ep93xx_read_sched_clock, 40, 172*c28ca80bSNikita Shubin EP93XX_TIMER4_RATE); 173*c28ca80bSNikita Shubin 174*c28ca80bSNikita Shubin /* Set up clockevent on timer 3 */ 175*c28ca80bSNikita Shubin if (request_irq(irq, ep93xx_timer_interrupt, flags, "ep93xx timer", 176*c28ca80bSNikita Shubin &ep93xx_clockevent)) 177*c28ca80bSNikita Shubin pr_err("Failed to request irq %d (ep93xx timer)\n", irq); 178*c28ca80bSNikita Shubin 179*c28ca80bSNikita Shubin clockevents_config_and_register(&ep93xx_clockevent, 180*c28ca80bSNikita Shubin EP93XX_TIMER123_RATE, 181*c28ca80bSNikita Shubin 1, 182*c28ca80bSNikita Shubin UINT_MAX); 183*c28ca80bSNikita Shubin 184*c28ca80bSNikita Shubin return 0; 185*c28ca80bSNikita Shubin 186*c28ca80bSNikita Shubin out_free: 187*c28ca80bSNikita Shubin kfree(tcu); 188*c28ca80bSNikita Shubin return ret; 189*c28ca80bSNikita Shubin } 190*c28ca80bSNikita Shubin TIMER_OF_DECLARE(ep93xx_timer, "cirrus,ep9301-timer", ep93xx_timer_of_init); 191