1c28ca80bSNikita Shubin // SPDX-License-Identifier: GPL-2.0 2c28ca80bSNikita Shubin /* 3c28ca80bSNikita Shubin * Cirrus Logic EP93xx timer driver. 4c28ca80bSNikita Shubin * Copyright (C) 2021 Nikita Shubin <nikita.shubin@maquefel.me> 5c28ca80bSNikita Shubin * 6c28ca80bSNikita Shubin * Based on a rewrite of arch/arm/mach-ep93xx/timer.c: 7c28ca80bSNikita Shubin */ 8c28ca80bSNikita Shubin 9c28ca80bSNikita Shubin #include <linux/clockchips.h> 10c28ca80bSNikita Shubin #include <linux/clocksource.h> 11c28ca80bSNikita Shubin #include <linux/init.h> 12c28ca80bSNikita Shubin #include <linux/interrupt.h> 13c28ca80bSNikita Shubin #include <linux/io.h> 14c28ca80bSNikita Shubin #include <linux/io-64-nonatomic-lo-hi.h> 15c28ca80bSNikita Shubin #include <linux/irq.h> 16c28ca80bSNikita Shubin #include <linux/kernel.h> 17c28ca80bSNikita Shubin #include <linux/of_address.h> 18c28ca80bSNikita Shubin #include <linux/of_irq.h> 19c28ca80bSNikita Shubin #include <linux/sched_clock.h> 20c28ca80bSNikita Shubin 21c28ca80bSNikita Shubin #include <asm/mach/time.h> 22c28ca80bSNikita Shubin 23c28ca80bSNikita Shubin /************************************************************************* 24c28ca80bSNikita Shubin * Timer handling for EP93xx 25c28ca80bSNikita Shubin ************************************************************************* 26c28ca80bSNikita Shubin * The ep93xx has four internal timers. Timers 1, 2 (both 16 bit) and 27c28ca80bSNikita Shubin * 3 (32 bit) count down at 508 kHz, are self-reloading, and can generate 28c28ca80bSNikita Shubin * an interrupt on underflow. Timer 4 (40 bit) counts down at 983.04 kHz, 29c28ca80bSNikita Shubin * is free-running, and can't generate interrupts. 30c28ca80bSNikita Shubin * 31c28ca80bSNikita Shubin * The 508 kHz timers are ideal for use for the timer interrupt, as the 32c28ca80bSNikita Shubin * most common values of HZ divide 508 kHz nicely. We pick the 32 bit 33c28ca80bSNikita Shubin * timer (timer 3) to get as long sleep intervals as possible when using 34c28ca80bSNikita Shubin * CONFIG_NO_HZ. 35c28ca80bSNikita Shubin * 36c28ca80bSNikita Shubin * The higher clock rate of timer 4 makes it a better choice than the 37c28ca80bSNikita Shubin * other timers for use as clock source and for sched_clock(), providing 38c28ca80bSNikita Shubin * a stable 40 bit time base. 39c28ca80bSNikita Shubin ************************************************************************* 40c28ca80bSNikita Shubin */ 41c28ca80bSNikita Shubin 42c28ca80bSNikita Shubin #define EP93XX_TIMER1_LOAD 0x00 43c28ca80bSNikita Shubin #define EP93XX_TIMER1_VALUE 0x04 44c28ca80bSNikita Shubin #define EP93XX_TIMER1_CONTROL 0x08 45c28ca80bSNikita Shubin #define EP93XX_TIMER123_CONTROL_ENABLE BIT(7) 46c28ca80bSNikita Shubin #define EP93XX_TIMER123_CONTROL_MODE BIT(6) 47c28ca80bSNikita Shubin #define EP93XX_TIMER123_CONTROL_CLKSEL BIT(3) 48c28ca80bSNikita Shubin #define EP93XX_TIMER1_CLEAR 0x0c 49c28ca80bSNikita Shubin #define EP93XX_TIMER2_LOAD 0x20 50c28ca80bSNikita Shubin #define EP93XX_TIMER2_VALUE 0x24 51c28ca80bSNikita Shubin #define EP93XX_TIMER2_CONTROL 0x28 52c28ca80bSNikita Shubin #define EP93XX_TIMER2_CLEAR 0x2c 53c28ca80bSNikita Shubin /* 54c28ca80bSNikita Shubin * This read-only register contains the low word of the time stamp debug timer 55c28ca80bSNikita Shubin * ( Timer4). When this register is read, the high byte of the Timer4 counter is 56c28ca80bSNikita Shubin * saved in the Timer4ValueHigh register. 57c28ca80bSNikita Shubin */ 58c28ca80bSNikita Shubin #define EP93XX_TIMER4_VALUE_LOW 0x60 59c28ca80bSNikita Shubin #define EP93XX_TIMER4_VALUE_HIGH 0x64 60c28ca80bSNikita Shubin #define EP93XX_TIMER4_VALUE_HIGH_ENABLE BIT(8) 61c28ca80bSNikita Shubin #define EP93XX_TIMER3_LOAD 0x80 62c28ca80bSNikita Shubin #define EP93XX_TIMER3_VALUE 0x84 63c28ca80bSNikita Shubin #define EP93XX_TIMER3_CONTROL 0x88 64c28ca80bSNikita Shubin #define EP93XX_TIMER3_CLEAR 0x8c 65c28ca80bSNikita Shubin 66c28ca80bSNikita Shubin #define EP93XX_TIMER123_RATE 508469 67c28ca80bSNikita Shubin #define EP93XX_TIMER4_RATE 983040 68c28ca80bSNikita Shubin 69c28ca80bSNikita Shubin struct ep93xx_tcu { 70c28ca80bSNikita Shubin void __iomem *base; 71c28ca80bSNikita Shubin }; 72c28ca80bSNikita Shubin 73c28ca80bSNikita Shubin static struct ep93xx_tcu *ep93xx_tcu; 74c28ca80bSNikita Shubin 75c28ca80bSNikita Shubin static u64 ep93xx_clocksource_read(struct clocksource *c) 76c28ca80bSNikita Shubin { 77c28ca80bSNikita Shubin struct ep93xx_tcu *tcu = ep93xx_tcu; 78c28ca80bSNikita Shubin 79c28ca80bSNikita Shubin return lo_hi_readq(tcu->base + EP93XX_TIMER4_VALUE_LOW) & GENMASK_ULL(39, 0); 80c28ca80bSNikita Shubin } 81c28ca80bSNikita Shubin 82c28ca80bSNikita Shubin static u64 notrace ep93xx_read_sched_clock(void) 83c28ca80bSNikita Shubin { 84c28ca80bSNikita Shubin return ep93xx_clocksource_read(NULL); 85c28ca80bSNikita Shubin } 86c28ca80bSNikita Shubin 87c28ca80bSNikita Shubin static int ep93xx_clkevt_set_next_event(unsigned long next, 88c28ca80bSNikita Shubin struct clock_event_device *evt) 89c28ca80bSNikita Shubin { 90c28ca80bSNikita Shubin struct ep93xx_tcu *tcu = ep93xx_tcu; 91c28ca80bSNikita Shubin /* Default mode: periodic, off, 508 kHz */ 92c28ca80bSNikita Shubin u32 tmode = EP93XX_TIMER123_CONTROL_MODE | 93c28ca80bSNikita Shubin EP93XX_TIMER123_CONTROL_CLKSEL; 94c28ca80bSNikita Shubin 95c28ca80bSNikita Shubin /* Clear timer */ 96c28ca80bSNikita Shubin writel(tmode, tcu->base + EP93XX_TIMER3_CONTROL); 97c28ca80bSNikita Shubin 98c28ca80bSNikita Shubin /* Set next event */ 99c28ca80bSNikita Shubin writel(next, tcu->base + EP93XX_TIMER3_LOAD); 100c28ca80bSNikita Shubin writel(tmode | EP93XX_TIMER123_CONTROL_ENABLE, 101c28ca80bSNikita Shubin tcu->base + EP93XX_TIMER3_CONTROL); 102c28ca80bSNikita Shubin return 0; 103c28ca80bSNikita Shubin } 104c28ca80bSNikita Shubin 105c28ca80bSNikita Shubin static int ep93xx_clkevt_shutdown(struct clock_event_device *evt) 106c28ca80bSNikita Shubin { 107c28ca80bSNikita Shubin struct ep93xx_tcu *tcu = ep93xx_tcu; 108c28ca80bSNikita Shubin /* Disable timer */ 109c28ca80bSNikita Shubin writel(0, tcu->base + EP93XX_TIMER3_CONTROL); 110c28ca80bSNikita Shubin 111c28ca80bSNikita Shubin return 0; 112c28ca80bSNikita Shubin } 113c28ca80bSNikita Shubin 114c28ca80bSNikita Shubin static struct clock_event_device ep93xx_clockevent = { 115c28ca80bSNikita Shubin .name = "timer1", 116c28ca80bSNikita Shubin .features = CLOCK_EVT_FEAT_ONESHOT, 117c28ca80bSNikita Shubin .set_state_shutdown = ep93xx_clkevt_shutdown, 118c28ca80bSNikita Shubin .set_state_oneshot = ep93xx_clkevt_shutdown, 119c28ca80bSNikita Shubin .tick_resume = ep93xx_clkevt_shutdown, 120c28ca80bSNikita Shubin .set_next_event = ep93xx_clkevt_set_next_event, 121c28ca80bSNikita Shubin .rating = 300, 122c28ca80bSNikita Shubin }; 123c28ca80bSNikita Shubin 124c28ca80bSNikita Shubin static irqreturn_t ep93xx_timer_interrupt(int irq, void *dev_id) 125c28ca80bSNikita Shubin { 126c28ca80bSNikita Shubin struct ep93xx_tcu *tcu = ep93xx_tcu; 127c28ca80bSNikita Shubin struct clock_event_device *evt = dev_id; 128c28ca80bSNikita Shubin 129c28ca80bSNikita Shubin /* Writing any value clears the timer interrupt */ 130c28ca80bSNikita Shubin writel(1, tcu->base + EP93XX_TIMER3_CLEAR); 131c28ca80bSNikita Shubin 132c28ca80bSNikita Shubin evt->event_handler(evt); 133c28ca80bSNikita Shubin 134c28ca80bSNikita Shubin return IRQ_HANDLED; 135c28ca80bSNikita Shubin } 136c28ca80bSNikita Shubin 137c28ca80bSNikita Shubin static int __init ep93xx_timer_of_init(struct device_node *np) 138c28ca80bSNikita Shubin { 139c28ca80bSNikita Shubin int irq; 140c28ca80bSNikita Shubin unsigned long flags = IRQF_TIMER | IRQF_IRQPOLL; 141c28ca80bSNikita Shubin struct ep93xx_tcu *tcu; 142c28ca80bSNikita Shubin int ret; 143c28ca80bSNikita Shubin 144c28ca80bSNikita Shubin tcu = kzalloc(sizeof(*tcu), GFP_KERNEL); 145c28ca80bSNikita Shubin if (!tcu) 146c28ca80bSNikita Shubin return -ENOMEM; 147c28ca80bSNikita Shubin 148c28ca80bSNikita Shubin tcu->base = of_iomap(np, 0); 149c28ca80bSNikita Shubin if (!tcu->base) { 150c28ca80bSNikita Shubin pr_err("Can't remap registers\n"); 151c28ca80bSNikita Shubin ret = -ENXIO; 152c28ca80bSNikita Shubin goto out_free; 153c28ca80bSNikita Shubin } 154c28ca80bSNikita Shubin 155c28ca80bSNikita Shubin ep93xx_tcu = tcu; 156c28ca80bSNikita Shubin 157c28ca80bSNikita Shubin irq = irq_of_parse_and_map(np, 0); 158*c0c4579dSArnd Bergmann if (!irq) { 159*c0c4579dSArnd Bergmann ret = -EINVAL; 160c28ca80bSNikita Shubin pr_err("EP93XX Timer Can't parse IRQ %d", irq); 161c28ca80bSNikita Shubin goto out_free; 162c28ca80bSNikita Shubin } 163c28ca80bSNikita Shubin 164c28ca80bSNikita Shubin /* Enable and register clocksource and sched_clock on timer 4 */ 165c28ca80bSNikita Shubin writel(EP93XX_TIMER4_VALUE_HIGH_ENABLE, 166c28ca80bSNikita Shubin tcu->base + EP93XX_TIMER4_VALUE_HIGH); 167c28ca80bSNikita Shubin clocksource_mmio_init(NULL, "timer4", 168c28ca80bSNikita Shubin EP93XX_TIMER4_RATE, 200, 40, 169c28ca80bSNikita Shubin ep93xx_clocksource_read); 170c28ca80bSNikita Shubin sched_clock_register(ep93xx_read_sched_clock, 40, 171c28ca80bSNikita Shubin EP93XX_TIMER4_RATE); 172c28ca80bSNikita Shubin 173c28ca80bSNikita Shubin /* Set up clockevent on timer 3 */ 174c28ca80bSNikita Shubin if (request_irq(irq, ep93xx_timer_interrupt, flags, "ep93xx timer", 175c28ca80bSNikita Shubin &ep93xx_clockevent)) 176c28ca80bSNikita Shubin pr_err("Failed to request irq %d (ep93xx timer)\n", irq); 177c28ca80bSNikita Shubin 178c28ca80bSNikita Shubin clockevents_config_and_register(&ep93xx_clockevent, 179c28ca80bSNikita Shubin EP93XX_TIMER123_RATE, 180c28ca80bSNikita Shubin 1, 181c28ca80bSNikita Shubin UINT_MAX); 182c28ca80bSNikita Shubin 183c28ca80bSNikita Shubin return 0; 184c28ca80bSNikita Shubin 185c28ca80bSNikita Shubin out_free: 186c28ca80bSNikita Shubin kfree(tcu); 187c28ca80bSNikita Shubin return ret; 188c28ca80bSNikita Shubin } 189c28ca80bSNikita Shubin TIMER_OF_DECLARE(ep93xx_timer, "cirrus,ep9301-timer", ep93xx_timer_of_init); 190