1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2022 Rockchip Electronics Co. Ltd.
4 * Author: Elaine Zhang <zhangqing@rock-chips.com>
5 */
6
7 #include <linux/clk-provider.h>
8 #include <linux/of.h>
9 #include <linux/platform_device.h>
10 #include <linux/regmap.h>
11 #include <dt-bindings/clock/rockchip,rv1106-cru.h>
12 #include "clk.h"
13
14 /*
15 * Register offsets inside the CRU region. The RV1106 CRU is split into
16 * several sub-blocks, one per power domain, all accessed through a
17 * single register window.
18 */
19 #define RV1106_TOPCRU_BASE 0x10000
20 #define RV1106_PERICRU_BASE 0x12000
21 #define RV1106_VICRU_BASE 0x14000
22 #define RV1106_NPUCRU_BASE 0x16000
23 #define RV1106_CORECRU_BASE 0x18000
24 #define RV1106_VEPUCRU_BASE 0x1a000
25 #define RV1106_VOCRU_BASE 0x1c000
26 #define RV1106_DDRCRU_BASE 0x1e000
27 #define RV1106_SUBDDRCRU_BASE 0x1f000
28
29 #define RV1106_PMUCLKSEL_CON(x) ((x) * 0x4 + 0x300)
30 #define RV1106_PMUCLKGATE_CON(x) ((x) * 0x4 + 0x800)
31 #define RV1106_PLL_CON(x) ((x) * 0x4 + RV1106_TOPCRU_BASE)
32 #define RV1106_MODE_CON (0x280 + RV1106_TOPCRU_BASE)
33 #define RV1106_CLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1106_TOPCRU_BASE)
34 #define RV1106_CLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1106_TOPCRU_BASE)
35 #define RV1106_GLB_SRST_FST (0xc08 + RV1106_TOPCRU_BASE)
36 #define RV1106_PERICLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1106_PERICRU_BASE)
37 #define RV1106_PERICLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1106_PERICRU_BASE)
38 #define RV1106_VICLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1106_VICRU_BASE)
39 #define RV1106_VICLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1106_VICRU_BASE)
40 #define RV1106_NPUCLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1106_NPUCRU_BASE)
41 #define RV1106_NPUCLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1106_NPUCRU_BASE)
42 #define RV1106_CORECLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1106_CORECRU_BASE)
43 #define RV1106_CORECLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1106_CORECRU_BASE)
44 #define RV1106_VEPUCLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1106_VEPUCRU_BASE)
45 #define RV1106_VEPUCLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1106_VEPUCRU_BASE)
46 #define RV1106_VOCLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1106_VOCRU_BASE)
47 #define RV1106_VOCLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1106_VOCRU_BASE)
48 #define RV1106_DDRCLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1106_DDRCRU_BASE)
49 #define RV1106_DDRCLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1106_DDRCRU_BASE)
50 #define RV1106_SUBDDRCLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1106_SUBDDRCRU_BASE)
51 #define RV1106_SUBDDRCLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1106_SUBDDRCRU_BASE)
52 #define RV1106_SUBDDRMODE_CON (0x280 + RV1106_SUBDDRCRU_BASE)
53
54 /* Register offsets inside the GRF region for the MMC phase clocks */
55 #define RV1106_VI_GRF_BASE 0x50000
56 #define RV1106_VO_GRF_BASE 0x60000
57
58 #define RV1106_EMMC_CON0 0x20
59 #define RV1106_EMMC_CON1 0x24
60 #define RV1106_SDMMC_CON0 (0x4 + RV1106_VI_GRF_BASE)
61 #define RV1106_SDMMC_CON1 (0x8 + RV1106_VI_GRF_BASE)
62 #define RV1106_SDIO_CON0 (0x1c + RV1106_VO_GRF_BASE)
63 #define RV1106_SDIO_CON1 (0x20 + RV1106_VO_GRF_BASE)
64
65 #define CRU_PVTPLL0_CON0_L 0x11000
66 #define CRU_PVTPLL0_CON0_H 0x11004
67 #define CRU_PVTPLL0_CON1_L 0x11008
68 #define CRU_PVTPLL0_CON2_H 0x11014
69
70 #define CRU_PVTPLL1_CON0_L 0x11030
71 #define CRU_PVTPLL1_CON0_H 0x11034
72 #define CRU_PVTPLL1_CON1_L 0x11038
73 #define CRU_PVTPLL1_CON2_H 0x11044
74
75 #define RV1106_GRF_SOC_STATUS0 0x10
76 #define CPU_PVTPLL_CON0_L 0x40000
77 #define CPU_PVTPLL_CON0_H 0x40004
78
79 #define PVTPLL_RING_SEL_MASK 0x7
80 #define PVTPLL_RING_SEL_SHIFT 8
81 #define PVTPLL_EN_MASK 0x3
82 #define PVTPLL_EN_SHIFT 0
83 #define PVTPLL_LENGTH_SEL_MASK 0x7f
84 #define PVTPLL_LENGTH_SEL_SHIFT 0
85
86 #define CPU_CLK_PATH_BASE RV1106_CORECLKSEL_CON(0)
87 #define CPU_PVTPLL_PATH_CORE (BIT(12) | BIT(28))
88
89 #define RV1106_FRAC_MAX_PRATE 1200000000
90
91 enum rv1106_plls {
92 apll, dpll, cpll, gpll,
93 };
94
95 static struct rockchip_pll_rate_table rv1106_pll_rates[] = {
96 /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
97 RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0),
98 RK3036_PLL_RATE(1600000000, 3, 200, 1, 1, 1, 0),
99 RK3036_PLL_RATE(1584000000, 1, 132, 2, 1, 1, 0),
100 RK3036_PLL_RATE(1560000000, 1, 130, 2, 1, 1, 0),
101 RK3036_PLL_RATE(1536000000, 1, 128, 2, 1, 1, 0),
102 RK3036_PLL_RATE(1512000000, 1, 126, 2, 1, 1, 0),
103 RK3036_PLL_RATE(1488000000, 1, 124, 2, 1, 1, 0),
104 RK3036_PLL_RATE(1464000000, 1, 122, 2, 1, 1, 0),
105 RK3036_PLL_RATE(1440000000, 1, 120, 2, 1, 1, 0),
106 RK3036_PLL_RATE(1416000000, 1, 118, 2, 1, 1, 0),
107 RK3036_PLL_RATE(1400000000, 3, 350, 2, 1, 1, 0),
108 RK3036_PLL_RATE(1392000000, 1, 116, 2, 1, 1, 0),
109 RK3036_PLL_RATE(1368000000, 1, 114, 2, 1, 1, 0),
110 RK3036_PLL_RATE(1344000000, 1, 112, 2, 1, 1, 0),
111 RK3036_PLL_RATE(1320000000, 1, 110, 2, 1, 1, 0),
112 RK3036_PLL_RATE(1296000000, 1, 108, 2, 1, 1, 0),
113 RK3036_PLL_RATE(1272000000, 1, 106, 2, 1, 1, 0),
114 RK3036_PLL_RATE(1248000000, 1, 104, 2, 1, 1, 0),
115 RK3036_PLL_RATE(1200000000, 1, 100, 2, 1, 1, 0),
116 RK3036_PLL_RATE(1188000000, 1, 99, 2, 1, 1, 0),
117 RK3036_PLL_RATE(1104000000, 1, 92, 2, 1, 1, 0),
118 RK3036_PLL_RATE(1100000000, 3, 275, 2, 1, 1, 0),
119 RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0),
120 RK3036_PLL_RATE(1000000000, 3, 250, 2, 1, 1, 0),
121 RK3036_PLL_RATE(993484800, 1, 124, 3, 1, 0, 3113851),
122 RK3036_PLL_RATE(984000000, 1, 82, 2, 1, 1, 0),
123 RK3036_PLL_RATE(983040000, 1, 81, 2, 1, 0, 15435038),
124 RK3036_PLL_RATE(960000000, 1, 80, 2, 1, 1, 0),
125 RK3036_PLL_RATE(936000000, 1, 78, 2, 1, 1, 0),
126 RK3036_PLL_RATE(912000000, 1, 76, 2, 1, 1, 0),
127 RK3036_PLL_RATE(900000000, 1, 75, 2, 1, 1, 0),
128 RK3036_PLL_RATE(888000000, 1, 74, 2, 1, 1, 0),
129 RK3036_PLL_RATE(864000000, 1, 72, 2, 1, 1, 0),
130 RK3036_PLL_RATE(840000000, 1, 70, 2, 1, 1, 0),
131 RK3036_PLL_RATE(816000000, 1, 68, 2, 1, 1, 0),
132 RK3036_PLL_RATE(800000000, 3, 200, 2, 1, 1, 0),
133 RK3036_PLL_RATE(700000000, 3, 350, 4, 1, 1, 0),
134 RK3036_PLL_RATE(696000000, 1, 116, 4, 1, 1, 0),
135 RK3036_PLL_RATE(624000000, 1, 104, 4, 1, 1, 0),
136 RK3036_PLL_RATE(600000000, 1, 100, 4, 1, 1, 0),
137 RK3036_PLL_RATE(594000000, 1, 99, 4, 1, 1, 0),
138 RK3036_PLL_RATE(504000000, 1, 84, 4, 1, 1, 0),
139 RK3036_PLL_RATE(500000000, 1, 125, 6, 1, 1, 0),
140 RK3036_PLL_RATE(496742400, 1, 124, 6, 1, 0, 3113851),
141 RK3036_PLL_RATE(491520000, 1, 40, 2, 1, 0, 16106127),
142 RK3036_PLL_RATE(408000000, 1, 68, 2, 2, 1, 0),
143 RK3036_PLL_RATE(312000000, 1, 78, 6, 1, 1, 0),
144 RK3036_PLL_RATE(216000000, 1, 72, 4, 2, 1, 0),
145 RK3036_PLL_RATE(96000000, 1, 96, 6, 4, 1, 0),
146 { /* sentinel */ },
147 };
148
149 #define RV1106_DIV_ACLK_CORE_MASK 0x1f
150 #define RV1106_DIV_ACLK_CORE_SHIFT 7
151 #define RV1106_DIV_PCLK_DBG_MASK 0x1f
152 #define RV1106_DIV_PCLK_DBG_SHIFT 0
153 #define RV1106_CORE_SEL_MASK 0x3
154 #define RV1106_CORE_SEL_SHIFT 5
155
156 #define RV1106_CLKSEL0(_aclk_core) \
157 { \
158 .reg = RV1106_CORECLKSEL_CON(0), \
159 .val = HIWORD_UPDATE(_aclk_core, RV1106_DIV_ACLK_CORE_MASK, \
160 RV1106_DIV_ACLK_CORE_SHIFT), \
161 }
162
163 #define RV1106_CLKSEL1(_pclk_dbg) \
164 { \
165 .reg = RV1106_CORECLKSEL_CON(1), \
166 .val = HIWORD_UPDATE(_pclk_dbg, RV1106_DIV_PCLK_DBG_MASK, \
167 RV1106_DIV_PCLK_DBG_SHIFT), \
168 }
169
170 #define RV1106_CLKSEL2(_is_pvtpll) \
171 { \
172 .reg = RV1106_CORECLKSEL_CON(0), \
173 .val = HIWORD_UPDATE(_is_pvtpll, RV1106_CORE_SEL_MASK, \
174 RV1106_CORE_SEL_SHIFT), \
175 }
176
177 #define RV1106_CPUCLK_RATE(_prate, _aclk_core, _pclk_dbg, _is_pvtpll) \
178 { \
179 .prate = _prate, \
180 .divs = { \
181 RV1106_CLKSEL0(_aclk_core), \
182 RV1106_CLKSEL1(_pclk_dbg), \
183 }, \
184 .post_muxs = { \
185 RV1106_CLKSEL2(_is_pvtpll), \
186 }, \
187 }
188
189 static struct rockchip_cpuclk_rate_table rv1106_cpuclk_rates[] __initdata = {
190 RV1106_CPUCLK_RATE(1608000000, 3, 7, 1),
191 RV1106_CPUCLK_RATE(1584000000, 3, 7, 1),
192 RV1106_CPUCLK_RATE(1560000000, 3, 7, 1),
193 RV1106_CPUCLK_RATE(1536000000, 3, 7, 1),
194 RV1106_CPUCLK_RATE(1512000000, 3, 7, 1),
195 RV1106_CPUCLK_RATE(1488000000, 2, 5, 1),
196 RV1106_CPUCLK_RATE(1464000000, 2, 5, 1),
197 RV1106_CPUCLK_RATE(1440000000, 2, 5, 1),
198 RV1106_CPUCLK_RATE(1416000000, 2, 5, 1),
199 RV1106_CPUCLK_RATE(1392000000, 2, 5, 1),
200 RV1106_CPUCLK_RATE(1368000000, 2, 5, 1),
201 RV1106_CPUCLK_RATE(1344000000, 2, 5, 1),
202 RV1106_CPUCLK_RATE(1320000000, 2, 5, 1),
203 RV1106_CPUCLK_RATE(1296000000, 2, 5, 1),
204 RV1106_CPUCLK_RATE(1272000000, 2, 5, 1),
205 RV1106_CPUCLK_RATE(1248000000, 2, 5, 1),
206 RV1106_CPUCLK_RATE(1224000000, 2, 5, 1),
207 RV1106_CPUCLK_RATE(1200000000, 2, 5, 1),
208 RV1106_CPUCLK_RATE(1104000000, 2, 5, 1),
209 RV1106_CPUCLK_RATE(1096000000, 2, 5, 1),
210 RV1106_CPUCLK_RATE(1008000000, 1, 5, 1),
211 RV1106_CPUCLK_RATE(912000000, 1, 5, 1),
212 RV1106_CPUCLK_RATE(816000000, 1, 3, 1),
213 RV1106_CPUCLK_RATE(696000000, 1, 3, 0),
214 RV1106_CPUCLK_RATE(600000000, 1, 3, 0),
215 RV1106_CPUCLK_RATE(408000000, 1, 1, 0),
216 RV1106_CPUCLK_RATE(312000000, 1, 1, 0),
217 RV1106_CPUCLK_RATE(216000000, 1, 1, 0),
218 RV1106_CPUCLK_RATE(96000000, 1, 1, 0),
219 };
220
221 static const struct rockchip_cpuclk_reg_data rv1106_cpuclk_data = {
222 .core_reg[0] = RV1106_CORECLKSEL_CON(0),
223 .div_core_shift[0] = 0,
224 .div_core_mask[0] = 0x1f,
225 .num_cores = 1,
226 .mux_core_alt = 2,
227 .mux_core_main = 0,
228 .mux_core_shift = 5,
229 .mux_core_mask = 0x3,
230 };
231
232 PNAME(mux_pll_p) = { "xin24m" };
233 PNAME(mux_armclk_p) = { "apll", "cpu_pvtpll", "gpll" };
234 PNAME(mux_24m_32k_p) = { "xin24m", "clk_rtc_32k" };
235 PNAME(mux_gpll_cpll_p) = { "gpll", "cpll" };
236 PNAME(mux_gpll_24m_p) = { "gpll", "xin24m" };
237 PNAME(mux_100m_50m_24m_p) = { "clk_100m_src", "clk_50m_src", "xin24m" };
238 PNAME(mux_150m_100m_50m_24m_p) = { "clk_150m_src", "clk_100m_src", "clk_50m_src", "xin24m" };
239 PNAME(mux_500m_300m_100m_24m_p) = { "clk_500m_src", "clk_300m_src", "clk_100m_src", "xin24m" };
240 PNAME(mux_400m_300m_pvtpll0_pvtpll1_p) = { "clk_400m_src", "clk_300m_src", "clk_pvtpll_0", "clk_pvtpll_1" };
241 PNAME(mux_500m_300m_pvtpll0_pvtpll1_p) = { "clk_500m_src", "clk_300m_src", "clk_pvtpll_0", "clk_pvtpll_1" };
242 PNAME(mux_339m_200m_pvtpll0_pvtpll1_p) = { "clk_339m_src", "clk_200m_src", "clk_pvtpll_0", "clk_pvtpll_1" };
243 PNAME(mux_400m_200m_100m_24m_p) = { "clk_400m_src", "clk_200m_src", "clk_100m_src", "xin24m" };
244 PNAME(mux_200m_100m_50m_24m_p) = { "clk_200m_src", "clk_100m_src", "clk_50m_src", "xin24m" };
245 PNAME(mux_300m_200m_100m_24m_p) = { "clk_300m_src", "clk_200m_src", "clk_100m_src", "xin24m" };
246 PNAME(mux_500m_300m_200m_24m_p) = { "clk_500m_src", "clk_300m_src", "clk_200m_src", "xin24m" };
247 PNAME(mux_50m_24m_p) = { "clk_50m_src", "xin24m" };
248 PNAME(mux_400m_24m_p) = { "clk_400m_src", "xin24m" };
249 PNAME(clk_rtc32k_pmu_p) = { "clk_rtc32k_frac", "xin32k", "clk_pvtm_32k" };
250 PNAME(mux_200m_100m_24m_32k_p) = { "clk_200m_src", "clk_100m_src", "xin24m", "clk_rtc_32k" };
251 PNAME(mux_100m_pmu_24m_p) = { "clk_100m_pmu", "xin24m" };
252 PNAME(mux_200m_100m_24m_p) = { "clk_200m_src", "clk_100m_pmu", "xin24m" };
253 PNAME(mux_339m_200m_100m_24m_p) = { "clk_339m_src", "clk_200m_src", "clk_100m_pmu", "xin24m" };
254 PNAME(mux_dpll_300m_p) = { "dpll", "clk_300m_src" };
255 PNAME(clk_i2s0_8ch_tx_p) = { "clk_i2s0_8ch_tx_src", "clk_i2s0_8ch_tx_frac", "i2s0_mclkin", "xin_osc0_half" };
256 PNAME(clk_i2s0_8ch_rx_p) = { "clk_i2s0_8ch_rx_src", "clk_i2s0_8ch_rx_frac", "i2s0_mclkin", "xin_osc0_half" };
257 PNAME(i2s0_8ch_mclkout_p) = { "mclk_i2s0_8ch_tx", "mclk_i2s0_8ch_rx", "xin_osc0_half" };
258 PNAME(clk_ref_mipi0_p) = { "clk_ref_mipi0_src", "clk_ref_mipi0_frac", "xin24m" };
259 PNAME(clk_ref_mipi1_p) = { "clk_ref_mipi1_src", "clk_ref_mipi1_frac", "xin24m" };
260 PNAME(clk_uart0_p) = { "clk_uart0_src", "clk_uart0_frac", "xin24m" };
261 PNAME(clk_uart1_p) = { "clk_uart1_src", "clk_uart1_frac", "xin24m" };
262 PNAME(clk_uart2_p) = { "clk_uart2_src", "clk_uart2_frac", "xin24m" };
263 PNAME(clk_uart3_p) = { "clk_uart3_src", "clk_uart3_frac", "xin24m" };
264 PNAME(clk_uart4_p) = { "clk_uart4_src", "clk_uart4_frac", "xin24m" };
265 PNAME(clk_uart5_p) = { "clk_uart5_src", "clk_uart5_frac", "xin24m" };
266 PNAME(clk_vicap_m0_p) = { "clk_vicap_m0_src", "clk_vicap_m0_frac", "xin24m" };
267 PNAME(clk_vicap_m1_p) = { "clk_vicap_m1_src", "clk_vicap_m1_frac", "xin24m" };
268
269 static struct rockchip_pll_clock rv1106_pll_clks[] __initdata = {
270 [apll] = PLL(pll_rk3328, PLL_APLL, "apll", mux_pll_p,
271 CLK_IGNORE_UNUSED, RV1106_PLL_CON(0),
272 RV1106_MODE_CON, 0, 10, 0, rv1106_pll_rates),
273 [cpll] = PLL(pll_rk3328, PLL_CPLL, "cpll", mux_pll_p,
274 0, RV1106_PLL_CON(8),
275 RV1106_MODE_CON, 2, 10, 0, rv1106_pll_rates),
276 [dpll] = PLL(pll_rk3328, PLL_DPLL, "dpll", mux_pll_p,
277 CLK_IGNORE_UNUSED, RV1106_PLL_CON(16),
278 RV1106_SUBDDRMODE_CON, 0, 10, 0, NULL),
279 [gpll] = PLL(pll_rk3328, PLL_GPLL, "gpll", mux_pll_p,
280 0, RV1106_PLL_CON(24),
281 RV1106_MODE_CON, 4, 10, 0, rv1106_pll_rates),
282 };
283
284 #define MFLAGS CLK_MUX_HIWORD_MASK
285 #define DFLAGS CLK_DIVIDER_HIWORD_MASK
286 #define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
287
288 static struct rockchip_clk_branch rv1106_rtc32k_pmu_fracmux __initdata =
289 MUX(CLK_RTC_32K, "clk_rtc_32k", clk_rtc32k_pmu_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
290 RV1106_PMUCLKSEL_CON(0), 6, 2, MFLAGS);
291
292 static struct rockchip_clk_branch rv1106_i2s0_8ch_tx_fracmux __initdata =
293 MUX(CLK_I2S0_8CH_TX, "clk_i2s0_8ch_tx", clk_i2s0_8ch_tx_p, CLK_SET_RATE_PARENT,
294 RV1106_CLKSEL_CON(19), 0, 2, MFLAGS);
295
296 static struct rockchip_clk_branch rv1106_i2s0_8ch_rx_fracmux __initdata =
297 MUX(CLK_I2S0_8CH_RX, "clk_i2s0_8ch_rx", clk_i2s0_8ch_rx_p, CLK_SET_RATE_PARENT,
298 RV1106_CLKSEL_CON(21), 0, 2, MFLAGS);
299
300 static struct rockchip_clk_branch rv1106_clk_ref_mipi0_fracmux __initdata =
301 MUX(CLK_REF_MIPI0, "clk_ref_mipi0", clk_ref_mipi0_p, CLK_SET_RATE_PARENT,
302 RV1106_CLKSEL_CON(27), 0, 2, MFLAGS);
303
304 static struct rockchip_clk_branch rv1106_clk_ref_mipi1_fracmux __initdata =
305 MUX(CLK_REF_MIPI1, "clk_ref_mipi1", clk_ref_mipi1_p, CLK_SET_RATE_PARENT,
306 RV1106_CLKSEL_CON(29), 0, 2, MFLAGS);
307
308 static struct rockchip_clk_branch rv1106_clk_uart0_fracmux __initdata =
309 MUX(CLK_UART0, "clk_uart0", clk_uart0_p, CLK_SET_RATE_PARENT,
310 RV1106_CLKSEL_CON(7), 0, 2, MFLAGS);
311
312 static struct rockchip_clk_branch rv1106_clk_uart1_fracmux __initdata =
313 MUX(CLK_UART1, "clk_uart1", clk_uart1_p, CLK_SET_RATE_PARENT,
314 RV1106_CLKSEL_CON(9), 0, 2, MFLAGS);
315
316 static struct rockchip_clk_branch rv1106_clk_uart2_fracmux __initdata =
317 MUX(CLK_UART2, "clk_uart2", clk_uart2_p, CLK_SET_RATE_PARENT,
318 RV1106_CLKSEL_CON(11), 0, 2, MFLAGS);
319
320 static struct rockchip_clk_branch rv1106_clk_uart3_fracmux __initdata =
321 MUX(CLK_UART3, "clk_uart3", clk_uart3_p, CLK_SET_RATE_PARENT,
322 RV1106_CLKSEL_CON(13), 0, 2, MFLAGS);
323
324 static struct rockchip_clk_branch rv1106_clk_uart4_fracmux __initdata =
325 MUX(CLK_UART4, "clk_uart4", clk_uart4_p, CLK_SET_RATE_PARENT,
326 RV1106_CLKSEL_CON(15), 0, 2, MFLAGS);
327
328 static struct rockchip_clk_branch rv1106_clk_uart5_fracmux __initdata =
329 MUX(CLK_UART5, "clk_uart5", clk_uart5_p, CLK_SET_RATE_PARENT,
330 RV1106_CLKSEL_CON(17), 0, 2, MFLAGS);
331
332 static struct rockchip_clk_branch rv1106_clk_vicap_m0_fracmux __initdata =
333 MUX(CLK_VICAP_M0, "clk_vicap_m0", clk_vicap_m0_p, CLK_SET_RATE_PARENT,
334 RV1106_CLKSEL_CON(31), 0, 2, MFLAGS);
335
336 static struct rockchip_clk_branch rv1106_clk_vicap_m1_fracmux __initdata =
337 MUX(CLK_VICAP_M1, "clk_vicap_m1", clk_vicap_m1_p, CLK_SET_RATE_PARENT,
338 RV1106_CLKSEL_CON(33), 0, 2, MFLAGS);
339
340 static struct rockchip_clk_branch rv1106_clk_branches[] __initdata = {
341
342 FACTOR(XIN_OSC0_HALF, "xin_osc0_half", "xin24m", 0, 1, 2),
343
344 /* PD_CORE */
345 GATE(CLK_PVTM_CORE, "clk_pvtm_core", "xin24m", 0,
346 RV1106_CORECLKGATE_CON(0), 14, GFLAGS),
347 GATE(CLK_CORE_MCU_RTC, "clk_core_mcu_rtc", "xin24m", 0,
348 RV1106_CORECLKGATE_CON(1), 6, GFLAGS),
349 COMPOSITE(HCLK_CPU, "hclk_cpu", mux_gpll_24m_p, CLK_IS_CRITICAL,
350 RV1106_CORECLKSEL_CON(2), 5, 1, MFLAGS, 0, 5, DFLAGS,
351 RV1106_CORECLKGATE_CON(0), 12, GFLAGS),
352 COMPOSITE(CLK_CORE_MCU, "clk_core_mcu", mux_gpll_24m_p, 0,
353 RV1106_CORECLKSEL_CON(3), 11, 1, MFLAGS, 6, 5, DFLAGS,
354 RV1106_CORECLKGATE_CON(1), 1, GFLAGS),
355 COMPOSITE_NOMUX(PCLK_DBG, "pclk_dbg", "armclk", CLK_IS_CRITICAL,
356 RV1106_CORECLKSEL_CON(1), 0, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
357 RV1106_CORECLKGATE_CON(0), 6, GFLAGS),
358 GATE(PCLK_CPU_ROOT, "pclk_cpu_root", "pclk_dbg", CLK_IS_CRITICAL,
359 RV1106_CORECLKGATE_CON(0), 10, GFLAGS),
360 GATE(PCLK_MAILBOX, "pclk_mailbox", "pclk_cpu_root", 0,
361 RV1106_CORECLKGATE_CON(1), 8, GFLAGS),
362
363 /* PD _TOP */
364 COMPOSITE(CLK_50M_SRC, "clk_50m_src", mux_gpll_cpll_p, CLK_IS_CRITICAL,
365 RV1106_CLKSEL_CON(0), 5, 1, MFLAGS, 0, 5, DFLAGS,
366 RV1106_CLKGATE_CON(0), 1, GFLAGS),
367 COMPOSITE(CLK_100M_SRC, "clk_100m_src", mux_gpll_cpll_p, CLK_IS_CRITICAL,
368 RV1106_CLKSEL_CON(0), 11, 1, MFLAGS, 6, 5, DFLAGS,
369 RV1106_CLKGATE_CON(0), 2, GFLAGS),
370 COMPOSITE(CLK_150M_SRC, "clk_150m_src", mux_gpll_cpll_p, CLK_IS_CRITICAL,
371 RV1106_CLKSEL_CON(1), 5, 1, MFLAGS, 0, 5, DFLAGS,
372 RV1106_CLKGATE_CON(0), 3, GFLAGS),
373 COMPOSITE(CLK_200M_SRC, "clk_200m_src", mux_gpll_cpll_p, CLK_IS_CRITICAL,
374 RV1106_CLKSEL_CON(1), 11, 1, MFLAGS, 6, 5, DFLAGS,
375 RV1106_CLKGATE_CON(0), 4, GFLAGS),
376 COMPOSITE(CLK_250M_SRC, "clk_250m_src", mux_gpll_cpll_p, CLK_IS_CRITICAL,
377 RV1106_CLKSEL_CON(2), 5, 1, MFLAGS, 0, 5, DFLAGS,
378 RV1106_CLKGATE_CON(0), 5, GFLAGS),
379 COMPOSITE(CLK_300M_SRC, "clk_300m_src", mux_gpll_cpll_p, CLK_IS_CRITICAL,
380 RV1106_CLKSEL_CON(2), 11, 1, MFLAGS, 6, 5, DFLAGS,
381 RV1106_CLKGATE_CON(0), 6, GFLAGS),
382 COMPOSITE_HALFDIV(CLK_339M_SRC, "clk_339m_src", mux_gpll_cpll_p, CLK_IS_CRITICAL,
383 RV1106_CLKSEL_CON(3), 5, 1, MFLAGS, 0, 5, DFLAGS,
384 RV1106_CLKGATE_CON(0), 7, GFLAGS),
385 COMPOSITE(CLK_400M_SRC, "clk_400m_src", mux_gpll_cpll_p, CLK_IS_CRITICAL,
386 RV1106_CLKSEL_CON(3), 11, 1, MFLAGS, 6, 5, DFLAGS,
387 RV1106_CLKGATE_CON(0), 8, GFLAGS),
388 COMPOSITE_HALFDIV(CLK_450M_SRC, "clk_450m_src", mux_gpll_cpll_p, CLK_IS_CRITICAL,
389 RV1106_CLKSEL_CON(4), 5, 1, MFLAGS, 0, 5, DFLAGS,
390 RV1106_CLKGATE_CON(0), 9, GFLAGS),
391 COMPOSITE(CLK_500M_SRC, "clk_500m_src", mux_gpll_cpll_p, CLK_IS_CRITICAL,
392 RV1106_CLKSEL_CON(4), 11, 1, MFLAGS, 6, 5, DFLAGS,
393 RV1106_CLKGATE_CON(0), 10, GFLAGS),
394
395 COMPOSITE_NODIV(PCLK_TOP_ROOT, "pclk_top_root", mux_100m_50m_24m_p, CLK_IS_CRITICAL,
396 RV1106_CLKSEL_CON(24), 5, 2, MFLAGS,
397 RV1106_CLKGATE_CON(2), 9, GFLAGS),
398
399 COMPOSITE(CLK_I2S0_8CH_TX_SRC, "clk_i2s0_8ch_tx_src", mux_gpll_cpll_p, 0,
400 RV1106_CLKSEL_CON(17), 7, 1, MFLAGS, 2, 5, DFLAGS,
401 RV1106_CLKGATE_CON(1), 13, GFLAGS),
402 COMPOSITE_FRACMUX(CLK_I2S0_8CH_TX_FRAC, "clk_i2s0_8ch_tx_frac", "clk_i2s0_8ch_tx_src", CLK_SET_RATE_PARENT,
403 RV1106_CLKSEL_CON(18), 0,
404 RV1106_CLKGATE_CON(1), 14, GFLAGS,
405 &rv1106_i2s0_8ch_tx_fracmux),
406 GATE(MCLK_I2S0_8CH_TX, "mclk_i2s0_8ch_tx", "clk_i2s0_8ch_tx", 0,
407 RV1106_CLKGATE_CON(1), 15, GFLAGS),
408 COMPOSITE(CLK_I2S0_8CH_RX_SRC, "clk_i2s0_8ch_rx_src", mux_gpll_cpll_p, 0,
409 RV1106_CLKSEL_CON(19), 7, 1, MFLAGS, 2, 5, DFLAGS,
410 RV1106_CLKGATE_CON(2), 0, GFLAGS),
411 COMPOSITE_FRACMUX(CLK_I2S0_8CH_RX_FRAC, "clk_i2s0_8ch_rx_frac", "clk_i2s0_8ch_rx_src", CLK_SET_RATE_PARENT,
412 RV1106_CLKSEL_CON(20), 0,
413 RV1106_CLKGATE_CON(2), 1, GFLAGS,
414 &rv1106_i2s0_8ch_rx_fracmux),
415 GATE(MCLK_I2S0_8CH_RX, "mclk_i2s0_8ch_rx", "clk_i2s0_8ch_rx", 0,
416 RV1106_CLKGATE_CON(2), 2, GFLAGS),
417 MUX(I2S0_8CH_MCLKOUT, "i2s0_8ch_mclkout", i2s0_8ch_mclkout_p, CLK_SET_RATE_PARENT,
418 RV1106_CLKSEL_CON(21), 2, 2, MFLAGS),
419 COMPOSITE(CLK_REF_MIPI0_SRC, "clk_ref_mipi0_src", mux_gpll_cpll_p, 0,
420 RV1106_CLKSEL_CON(25), 7, 1, MFLAGS, 2, 5, DFLAGS,
421 RV1106_CLKGATE_CON(3), 4, GFLAGS),
422 COMPOSITE_FRACMUX(CLK_REF_MIPI0_FRAC, "clk_ref_mipi0_frac", "clk_ref_mipi0_src", CLK_SET_RATE_PARENT,
423 RV1106_CLKSEL_CON(26), 0,
424 RV1106_CLKGATE_CON(3), 5, GFLAGS,
425 &rv1106_clk_ref_mipi0_fracmux),
426 GATE(MCLK_REF_MIPI0, "mclk_ref_mipi0", "clk_ref_mipi0", 0,
427 RV1106_CLKGATE_CON(3), 6, GFLAGS),
428 COMPOSITE(CLK_REF_MIPI1_SRC, "clk_ref_mipi1_src", mux_gpll_cpll_p, 0,
429 RV1106_CLKSEL_CON(27), 7, 1, MFLAGS, 2, 5, DFLAGS,
430 RV1106_CLKGATE_CON(3), 7, GFLAGS),
431 COMPOSITE_FRACMUX(CLK_REF_MIPI1_FRAC, "clk_ref_mipi1_frac", "clk_ref_mipi1_src", CLK_SET_RATE_PARENT,
432 RV1106_CLKSEL_CON(28), 0,
433 RV1106_CLKGATE_CON(3), 8, GFLAGS,
434 &rv1106_clk_ref_mipi1_fracmux),
435 GATE(MCLK_REF_MIPI1, "mclk_ref_mipi1", "clk_ref_mipi1", 0,
436 RV1106_CLKGATE_CON(3), 9, GFLAGS),
437 COMPOSITE(CLK_UART0_SRC, "clk_uart0_src", mux_gpll_cpll_p, 0,
438 RV1106_CLKSEL_CON(5), 5, 1, MFLAGS, 0, 5, DFLAGS,
439 RV1106_CLKGATE_CON(0), 11, GFLAGS),
440 COMPOSITE_FRACMUX(CLK_UART0_FRAC, "clk_uart0_frac", "clk_uart0_src", CLK_SET_RATE_PARENT,
441 RV1106_CLKSEL_CON(6), 0,
442 RV1106_CLKGATE_CON(0), 12, GFLAGS,
443 &rv1106_clk_uart0_fracmux),
444 GATE(SCLK_UART0, "sclk_uart0", "clk_uart0", 0,
445 RV1106_CLKGATE_CON(0), 13, GFLAGS),
446 COMPOSITE(CLK_UART1_SRC, "clk_uart1_src", mux_gpll_cpll_p, 0,
447 RV1106_CLKSEL_CON(7), 7, 1, MFLAGS, 2, 5, DFLAGS,
448 RV1106_CLKGATE_CON(0), 14, GFLAGS),
449 COMPOSITE_FRACMUX(CLK_UART1_FRAC, "clk_uart1_frac", "clk_uart1_src", CLK_SET_RATE_PARENT,
450 RV1106_CLKSEL_CON(8), 0,
451 RV1106_CLKGATE_CON(0), 15, GFLAGS,
452 &rv1106_clk_uart1_fracmux),
453 GATE(SCLK_UART1, "sclk_uart1", "clk_uart1", 0,
454 RV1106_CLKGATE_CON(1), 0, GFLAGS),
455 COMPOSITE(CLK_UART2_SRC, "clk_uart2_src", mux_gpll_cpll_p, 0,
456 RV1106_CLKSEL_CON(9), 7, 1, MFLAGS, 2, 5, DFLAGS,
457 RV1106_CLKGATE_CON(1), 1, GFLAGS),
458 COMPOSITE_FRACMUX(CLK_UART2_FRAC, "clk_uart2_frac", "clk_uart2_src", CLK_SET_RATE_PARENT,
459 RV1106_CLKSEL_CON(10), 0,
460 RV1106_CLKGATE_CON(1), 2, GFLAGS,
461 &rv1106_clk_uart2_fracmux),
462 GATE(SCLK_UART2, "sclk_uart2", "clk_uart2", 0,
463 RV1106_CLKGATE_CON(1), 3, GFLAGS),
464 COMPOSITE(CLK_UART3_SRC, "clk_uart3_src", mux_gpll_cpll_p, 0,
465 RV1106_CLKSEL_CON(11), 7, 1, MFLAGS, 2, 5, DFLAGS,
466 RV1106_CLKGATE_CON(1), 4, GFLAGS),
467 COMPOSITE_FRACMUX(CLK_UART3_FRAC, "clk_uart3_frac", "clk_uart3_src", CLK_SET_RATE_PARENT,
468 RV1106_CLKSEL_CON(12), 0,
469 RV1106_CLKGATE_CON(1), 5, GFLAGS,
470 &rv1106_clk_uart3_fracmux),
471 GATE(SCLK_UART3, "sclk_uart3", "clk_uart3", 0,
472 RV1106_CLKGATE_CON(1), 6, GFLAGS),
473 COMPOSITE(CLK_UART4_SRC, "clk_uart4_src", mux_gpll_cpll_p, 0,
474 RV1106_CLKSEL_CON(13), 7, 1, MFLAGS, 2, 5, DFLAGS,
475 RV1106_CLKGATE_CON(1), 7, GFLAGS),
476 COMPOSITE_FRACMUX(CLK_UART4_FRAC, "clk_uart4_frac", "clk_uart4_src", CLK_SET_RATE_PARENT,
477 RV1106_CLKSEL_CON(14), 0,
478 RV1106_CLKGATE_CON(1), 8, GFLAGS,
479 &rv1106_clk_uart4_fracmux),
480 GATE(SCLK_UART4, "sclk_uart4", "clk_uart4", 0,
481 RV1106_CLKGATE_CON(1), 9, GFLAGS),
482 COMPOSITE(CLK_UART5_SRC, "clk_uart5_src", mux_gpll_cpll_p, 0,
483 RV1106_CLKSEL_CON(15), 7, 1, MFLAGS, 2, 5, DFLAGS,
484 RV1106_CLKGATE_CON(1), 10, GFLAGS),
485 COMPOSITE_FRACMUX(CLK_UART5_FRAC, "clk_uart5_frac", "clk_uart5_src", CLK_SET_RATE_PARENT,
486 RV1106_CLKSEL_CON(16), 0,
487 RV1106_CLKGATE_CON(1), 11, GFLAGS,
488 &rv1106_clk_uart5_fracmux),
489 GATE(SCLK_UART5, "sclk_uart5", "clk_uart5", 0,
490 RV1106_CLKGATE_CON(1), 12, GFLAGS),
491 COMPOSITE(CLK_VICAP_M0_SRC, "clk_vicap_m0_src", mux_gpll_cpll_p, 0,
492 RV1106_CLKSEL_CON(29), 7, 1, MFLAGS, 2, 5, DFLAGS,
493 RV1106_CLKGATE_CON(3), 10, GFLAGS),
494 COMPOSITE_FRACMUX(CLK_VICAP_M0_FRAC, "clk_vicap_m0_frac", "clk_vicap_m0_src", CLK_SET_RATE_PARENT,
495 RV1106_CLKSEL_CON(30), 0,
496 RV1106_CLKGATE_CON(3), 11, GFLAGS,
497 &rv1106_clk_vicap_m0_fracmux),
498 GATE(SCLK_VICAP_M0, "sclk_vicap_m0", "clk_vicap_m0", 0,
499 RV1106_CLKGATE_CON(3), 12, GFLAGS),
500 COMPOSITE(CLK_VICAP_M1_SRC, "clk_vicap_m1_src", mux_gpll_cpll_p, 0,
501 RV1106_CLKSEL_CON(31), 7, 1, MFLAGS, 2, 5, DFLAGS,
502 RV1106_CLKGATE_CON(3), 13, GFLAGS),
503 COMPOSITE_FRACMUX(CLK_VICAP_M1_FRAC, "clk_vicap_m1_frac", "clk_vicap_m1_src", CLK_SET_RATE_PARENT,
504 RV1106_CLKSEL_CON(32), 0,
505 RV1106_CLKGATE_CON(3), 14, GFLAGS,
506 &rv1106_clk_vicap_m1_fracmux),
507 GATE(SCLK_VICAP_M1, "sclk_vicap_m1", "clk_vicap_m1", 0,
508 RV1106_CLKGATE_CON(3), 15, GFLAGS),
509 COMPOSITE(DCLK_VOP_SRC, "dclk_vop_src", mux_gpll_cpll_p, 0,
510 RV1106_CLKSEL_CON(23), 8, 1, MFLAGS, 3, 5, DFLAGS,
511 RV1106_CLKGATE_CON(2), 6, GFLAGS),
512
513 /* PD_DDR */
514 COMPOSITE_NODIV(PCLK_DDR_ROOT, "pclk_ddr_root", mux_100m_50m_24m_p, CLK_IS_CRITICAL,
515 RV1106_DDRCLKSEL_CON(0), 0, 2, MFLAGS,
516 RV1106_DDRCLKGATE_CON(0), 0, GFLAGS),
517 COMPOSITE_NODIV(ACLK_DDR_ROOT, "aclk_ddr_root", mux_500m_300m_100m_24m_p, CLK_IS_CRITICAL,
518 RV1106_DDRCLKSEL_CON(0), 8, 2, MFLAGS,
519 RV1106_DDRCLKGATE_CON(0), 12, GFLAGS),
520 GATE(PCLK_DDRPHY, "pclk_ddrphy", "pclk_ddr_root", CLK_IGNORE_UNUSED,
521 RV1106_DDRCLKGATE_CON(1), 3, GFLAGS),
522 GATE(PCLK_DDR_HWLP, "pclk_ddr_hwlp", "pclk_ddr_root", CLK_IGNORE_UNUSED,
523 RV1106_DDRCLKGATE_CON(1), 2, GFLAGS),
524 GATE(PCLK_DDRMON, "pclk_ddrmon", "pclk_ddr_root", 0,
525 RV1106_DDRCLKGATE_CON(0), 7, GFLAGS),
526 GATE(CLK_TIMER_DDRMON, "clk_timer_ddrmon", "xin24m", 0,
527 RV1106_DDRCLKGATE_CON(0), 8, GFLAGS),
528 GATE(PCLK_DDRC, "pclk_ddrc", "pclk_ddr_root", CLK_IGNORE_UNUSED,
529 RV1106_DDRCLKGATE_CON(0), 5, GFLAGS),
530 GATE(PCLK_DFICTRL, "pclk_dfictrl", "pclk_ddr_root", CLK_IS_CRITICAL,
531 RV1106_DDRCLKGATE_CON(0), 11, GFLAGS),
532 GATE(ACLK_SYS_SHRM, "aclk_sys_shrm", "aclk_ddr_root", CLK_IS_CRITICAL,
533 RV1106_DDRCLKGATE_CON(0), 13, GFLAGS),
534
535 /* PD_NPU */
536 COMPOSITE_NODIV(HCLK_NPU_ROOT, "hclk_npu_root", mux_150m_100m_50m_24m_p, CLK_IS_CRITICAL,
537 RV1106_NPUCLKSEL_CON(0), 0, 2, MFLAGS,
538 RV1106_NPUCLKGATE_CON(0), 0, GFLAGS),
539 COMPOSITE_NODIV(ACLK_NPU_ROOT, "aclk_npu_root", mux_500m_300m_pvtpll0_pvtpll1_p, CLK_IS_CRITICAL,
540 RV1106_NPUCLKSEL_CON(0), 2, 2, MFLAGS,
541 RV1106_NPUCLKGATE_CON(0), 1, GFLAGS),
542 COMPOSITE_NODIV(PCLK_NPU_ROOT, "pclk_npu_root", mux_100m_50m_24m_p, CLK_IS_CRITICAL,
543 RV1106_NPUCLKSEL_CON(0), 4, 2, MFLAGS,
544 RV1106_NPUCLKGATE_CON(0), 2, GFLAGS),
545 GATE(HCLK_RKNN, "hclk_rknn", "hclk_npu_root", 0,
546 RV1106_NPUCLKGATE_CON(0), 9, GFLAGS),
547 GATE(ACLK_RKNN, "aclk_rknn", "aclk_npu_root", 0,
548 RV1106_NPUCLKGATE_CON(0), 10, GFLAGS),
549
550 /* PD_PERI */
551 COMPOSITE_NODIV(PCLK_PERI_ROOT, "pclk_peri_root", mux_100m_50m_24m_p, CLK_IS_CRITICAL,
552 RV1106_PERICLKSEL_CON(1), 0, 2, MFLAGS,
553 RV1106_PERICLKGATE_CON(0), 0, GFLAGS),
554 COMPOSITE_NODIV(ACLK_PERI_ROOT, "aclk_peri_root", mux_400m_200m_100m_24m_p, CLK_IS_CRITICAL,
555 RV1106_PERICLKSEL_CON(1), 2, 2, MFLAGS,
556 RV1106_PERICLKGATE_CON(0), 1, GFLAGS),
557 COMPOSITE_NODIV(HCLK_PERI_ROOT, "hclk_peri_root", mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL,
558 RV1106_PERICLKSEL_CON(1), 4, 2, MFLAGS,
559 RV1106_PERICLKGATE_CON(0), 2, GFLAGS),
560 COMPOSITE_NODIV(ACLK_BUS_ROOT, "aclk_bus_root", mux_300m_200m_100m_24m_p, CLK_IS_CRITICAL,
561 RV1106_PERICLKSEL_CON(9), 0, 2, MFLAGS,
562 RV1106_PERICLKGATE_CON(6), 8, GFLAGS),
563 GATE(PCLK_ACODEC, "pclk_acodec", "pclk_peri_root", 0,
564 RV1106_PERICLKGATE_CON(6), 3, GFLAGS),
565 COMPOSITE_NOMUX(MCLK_ACODEC_TX, "mclk_acodec_tx", "mclk_i2s0_8ch_tx", 0,
566 RV1106_PERICLKSEL_CON(8), 0, 8, DFLAGS,
567 RV1106_PERICLKGATE_CON(6), 4, GFLAGS),
568 COMPOSITE_NODIV(CLK_CORE_CRYPTO, "clk_core_crypto", mux_300m_200m_100m_24m_p, 0,
569 RV1106_PERICLKSEL_CON(6), 5, 2, MFLAGS,
570 RV1106_PERICLKGATE_CON(3), 11, GFLAGS),
571 COMPOSITE_NODIV(CLK_PKA_CRYPTO, "clk_pka_crypto", mux_300m_200m_100m_24m_p, 0,
572 RV1106_PERICLKSEL_CON(6), 7, 2, MFLAGS,
573 RV1106_PERICLKGATE_CON(3), 12, GFLAGS),
574 GATE(ACLK_CRYPTO, "aclk_crypto", "aclk_bus_root", 0,
575 RV1106_PERICLKGATE_CON(3), 13, GFLAGS),
576 GATE(HCLK_CRYPTO, "hclk_crypto", "hclk_peri_root", 0,
577 RV1106_PERICLKGATE_CON(3), 14, GFLAGS),
578 GATE(ACLK_DECOM, "aclk_decom", "aclk_peri_root", 0,
579 RV1106_PERICLKGATE_CON(5), 9, GFLAGS),
580 GATE(PCLK_DECOM, "pclk_decom", "pclk_peri_root", 0,
581 RV1106_PERICLKGATE_CON(5), 10, GFLAGS),
582 COMPOSITE_NODIV(DCLK_DECOM, "dclk_decom", mux_400m_200m_100m_24m_p, 0,
583 RV1106_PERICLKSEL_CON(7), 14, 2, MFLAGS,
584 RV1106_PERICLKGATE_CON(5), 11, GFLAGS),
585 GATE(ACLK_DMAC, "aclk_dmac", "aclk_bus_root", 0,
586 RV1106_PERICLKGATE_CON(5), 8, GFLAGS),
587 GATE(PCLK_DSM, "pclk_dsm", "pclk_peri_root", 0,
588 RV1106_PERICLKGATE_CON(6), 2, GFLAGS),
589 GATE(MCLK_DSM, "mclk_dsm", "mclk_i2s0_8ch_tx", 0,
590 RV1106_PERICLKGATE_CON(6), 1, GFLAGS),
591 COMPOSITE(CCLK_SRC_EMMC, "cclk_src_emmc", mux_400m_24m_p, 0,
592 RV1106_PERICLKSEL_CON(7), 6, 1, MFLAGS, 0, 6, DFLAGS,
593 RV1106_PERICLKGATE_CON(4), 12, GFLAGS),
594 GATE(HCLK_EMMC, "hclk_emmc", "hclk_peri_root", 0,
595 RV1106_PERICLKGATE_CON(4), 13, GFLAGS),
596 GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_peri_root", 0,
597 RV1106_PERICLKGATE_CON(2), 0, GFLAGS),
598 GATE(DBCLK_GPIO4, "dbclk_gpio4", "xin24m", 0,
599 RV1106_PERICLKGATE_CON(2), 1, GFLAGS),
600 GATE(PCLK_I2C0, "pclk_i2c0", "pclk_peri_root", 0,
601 RV1106_PERICLKGATE_CON(1), 6, GFLAGS),
602 COMPOSITE_NODIV(CLK_I2C0, "clk_i2c0", mux_200m_100m_50m_24m_p, 0,
603 RV1106_PERICLKSEL_CON(1), 8, 2, MFLAGS,
604 RV1106_PERICLKGATE_CON(1), 7, GFLAGS),
605 GATE(PCLK_I2C2, "pclk_i2c2", "pclk_peri_root", 0,
606 RV1106_PERICLKGATE_CON(1), 10, GFLAGS),
607 COMPOSITE_NODIV(CLK_I2C2, "clk_i2c2", mux_200m_100m_50m_24m_p, 0,
608 RV1106_PERICLKSEL_CON(1), 12, 2, MFLAGS,
609 RV1106_PERICLKGATE_CON(1), 11, GFLAGS),
610 GATE(PCLK_I2C3, "pclk_i2c3", "pclk_peri_root", 0,
611 RV1106_PERICLKGATE_CON(1), 12, GFLAGS),
612 COMPOSITE_NODIV(CLK_I2C3, "clk_i2c3", mux_200m_100m_50m_24m_p, 0,
613 RV1106_PERICLKSEL_CON(1), 14, 2, MFLAGS,
614 RV1106_PERICLKGATE_CON(1), 13, GFLAGS),
615 GATE(PCLK_I2C4, "pclk_i2c4", "pclk_peri_root", 0,
616 RV1106_PERICLKGATE_CON(1), 14, GFLAGS),
617 COMPOSITE_NODIV(CLK_I2C4, "clk_i2c4", mux_200m_100m_50m_24m_p, 0,
618 RV1106_PERICLKSEL_CON(2), 0, 2, MFLAGS,
619 RV1106_PERICLKGATE_CON(1), 15, GFLAGS),
620 GATE(HCLK_I2S0, "hclk_i2s0", "hclk_peri_root", 0,
621 RV1106_PERICLKGATE_CON(6), 0, GFLAGS),
622 GATE(PCLK_DFT2APB, "pclk_dft2apb", "pclk_peri_root", CLK_IGNORE_UNUSED,
623 RV1106_PERICLKGATE_CON(6), 7, GFLAGS),
624 GATE(HCLK_IVE, "hclk_ive", "hclk_peri_root", 0,
625 RV1106_PERICLKGATE_CON(6), 9, GFLAGS),
626 GATE(ACLK_IVE, "aclk_ive", "aclk_peri_root", 0,
627 RV1106_PERICLKGATE_CON(6), 10, GFLAGS),
628 GATE(PCLK_PWM0_PERI, "pclk_pwm0_peri", "pclk_peri_root", 0,
629 RV1106_PERICLKGATE_CON(7), 3, GFLAGS),
630 COMPOSITE_NODIV(CLK_PWM0_PERI, "clk_pwm0_peri", mux_100m_50m_24m_p, 0,
631 RV1106_PERICLKSEL_CON(11), 0, 2, MFLAGS,
632 RV1106_PERICLKGATE_CON(7), 4, GFLAGS),
633 GATE(CLK_CAPTURE_PWM0_PERI, "clk_capture_pwm0_peri", "xin24m", 0,
634 RV1106_PERICLKGATE_CON(7), 5, GFLAGS),
635 GATE(CLK_TIMER_ROOT, "clk_timer_root", "xin24m", 0,
636 RV1106_PERICLKGATE_CON(0), 3, GFLAGS),
637 GATE(HCLK_SFC, "hclk_sfc", "hclk_peri_root", 0,
638 RV1106_PERICLKGATE_CON(4), 14, GFLAGS),
639 COMPOSITE(SCLK_SFC, "sclk_sfc", mux_500m_300m_200m_24m_p, 0,
640 RV1106_PERICLKSEL_CON(7), 12, 2, MFLAGS, 7, 5, DFLAGS,
641 RV1106_PERICLKGATE_CON(5), 0, GFLAGS),
642 GATE(PCLK_UART0, "pclk_uart0", "pclk_peri_root", 0,
643 RV1106_PERICLKGATE_CON(6), 11, GFLAGS),
644 GATE(PCLK_UART1, "pclk_uart1", "pclk_peri_root", 0,
645 RV1106_PERICLKGATE_CON(6), 15, GFLAGS),
646 GATE(PCLK_PWM1_PERI, "pclk_pwm1_peri", "pclk_peri_root", 0,
647 RV1106_PERICLKGATE_CON(3), 15, GFLAGS),
648 COMPOSITE_NODIV(CLK_PWM1_PERI, "clk_pwm1_peri", mux_100m_50m_24m_p, 0,
649 RV1106_PERICLKSEL_CON(6), 9, 2, MFLAGS,
650 RV1106_PERICLKGATE_CON(4), 0, GFLAGS),
651 GATE(CLK_CAPTURE_PWM1_PERI, "clk_capture_pwm1_peri", "xin24m", 0,
652 RV1106_PERICLKGATE_CON(4), 1, GFLAGS),
653 GATE(PCLK_PWM2_PERI, "pclk_pwm2_peri", "pclk_peri_root", 0,
654 RV1106_PERICLKGATE_CON(4), 2, GFLAGS),
655 COMPOSITE_NODIV(CLK_PWM2_PERI, "clk_pwm2_peri", mux_100m_50m_24m_p, 0,
656 RV1106_PERICLKSEL_CON(6), 11, 2, MFLAGS,
657 RV1106_PERICLKGATE_CON(4), 3, GFLAGS),
658 GATE(CLK_CAPTURE_PWM2_PERI, "clk_capture_pwm2_peri", "xin24m", 0,
659 RV1106_PERICLKGATE_CON(4), 4, GFLAGS),
660 GATE(HCLK_BOOTROM, "hclk_bootrom", "hclk_peri_root", 0,
661 RV1106_PERICLKGATE_CON(0), 7, GFLAGS),
662 GATE(HCLK_SAI, "hclk_sai", "hclk_peri_root", 0,
663 RV1106_PERICLKGATE_CON(5), 13, GFLAGS),
664 GATE(MCLK_SAI, "mclk_sai", "mclk_i2s0_8ch_tx", 0,
665 RV1106_PERICLKGATE_CON(5), 14, GFLAGS),
666 GATE(PCLK_SARADC, "pclk_saradc", "pclk_peri_root", 0,
667 RV1106_PERICLKGATE_CON(3), 3, GFLAGS),
668 COMPOSITE_NOMUX(CLK_SARADC, "clk_saradc", "xin24m", 0,
669 RV1106_PERICLKSEL_CON(6), 0, 3, DFLAGS,
670 RV1106_PERICLKGATE_CON(3), 4, GFLAGS),
671 GATE(PCLK_SPI1, "pclk_spi1", "pclk_peri_root", 0,
672 RV1106_PERICLKGATE_CON(3), 6, GFLAGS),
673 COMPOSITE_NODIV(CLK_SPI1, "clk_spi1", mux_200m_100m_50m_24m_p, 0,
674 RV1106_PERICLKSEL_CON(6), 3, 2, MFLAGS,
675 RV1106_PERICLKGATE_CON(3), 7, GFLAGS),
676 GATE(PCLK_STIMER, "pclk_stimer", "pclk_peri_root", 0,
677 RV1106_PERICLKGATE_CON(0), 15, GFLAGS),
678 GATE(CLK_STIMER0, "clk_stimer0", "clk_timer_root", 0,
679 RV1106_PERICLKGATE_CON(1), 0, GFLAGS),
680 GATE(CLK_STIMER1, "clk_stimer1", "clk_timer_root", 0,
681 RV1106_PERICLKGATE_CON(1), 1, GFLAGS),
682 GATE(PCLK_TIMER, "pclk_timer", "pclk_peri_root", 0,
683 RV1106_PERICLKGATE_CON(0), 8, GFLAGS),
684 GATE(CLK_TIMER0, "clk_timer0", "clk_timer_root", 0,
685 RV1106_PERICLKGATE_CON(0), 9, GFLAGS),
686 GATE(CLK_TIMER1, "clk_timer1", "clk_timer_root", 0,
687 RV1106_PERICLKGATE_CON(0), 10, GFLAGS),
688 GATE(CLK_TIMER2, "clk_timer2", "clk_timer_root", 0,
689 RV1106_PERICLKGATE_CON(0), 11, GFLAGS),
690 GATE(CLK_TIMER3, "clk_timer3", "clk_timer_root", 0,
691 RV1106_PERICLKGATE_CON(0), 12, GFLAGS),
692 GATE(CLK_TIMER4, "clk_timer4", "clk_timer_root", 0,
693 RV1106_PERICLKGATE_CON(0), 13, GFLAGS),
694 GATE(CLK_TIMER5, "clk_timer5", "clk_timer_root", 0,
695 RV1106_PERICLKGATE_CON(0), 14, GFLAGS),
696 GATE(HCLK_TRNG_NS, "hclk_trng_ns", "hclk_peri_root", 0,
697 RV1106_PERICLKGATE_CON(3), 9, GFLAGS),
698 GATE(HCLK_TRNG_S, "hclk_trng_s", "hclk_peri_root", 0,
699 RV1106_PERICLKGATE_CON(3), 10, GFLAGS),
700 GATE(PCLK_UART2, "pclk_uart2", "pclk_peri_root", 0,
701 RV1106_PERICLKGATE_CON(2), 3, GFLAGS),
702 GATE(PCLK_UART3, "pclk_uart3", "pclk_peri_root", 0,
703 RV1106_PERICLKGATE_CON(2), 7, GFLAGS),
704 GATE(PCLK_UART4, "pclk_uart4", "pclk_peri_root", 0,
705 RV1106_PERICLKGATE_CON(2), 11, GFLAGS),
706 GATE(PCLK_UART5, "pclk_uart5", "pclk_peri_root", 0,
707 RV1106_PERICLKGATE_CON(2), 15, GFLAGS),
708 GATE(ACLK_USBOTG, "aclk_usbotg", "aclk_bus_root", 0,
709 RV1106_PERICLKGATE_CON(4), 7, GFLAGS),
710 GATE(CLK_REF_USBOTG, "clk_ref_usbotg", "xin24m", 0,
711 RV1106_PERICLKGATE_CON(4), 8, GFLAGS),
712 GATE(PCLK_USBPHY, "pclk_usbphy", "pclk_peri_root", 0,
713 RV1106_PERICLKGATE_CON(5), 1, GFLAGS),
714 GATE(CLK_REF_USBPHY, "clk_ref_usbphy", "xin24m", 0,
715 RV1106_PERICLKGATE_CON(5), 2, GFLAGS),
716 GATE(PCLK_WDT_NS, "pclk_wdt_ns", "pclk_peri_root", 0,
717 RV1106_PERICLKGATE_CON(1), 2, GFLAGS),
718 GATE(TCLK_WDT_NS, "tclk_wdt_ns", "xin24m", 0,
719 RV1106_PERICLKGATE_CON(1), 3, GFLAGS),
720 GATE(PCLK_WDT_S, "pclk_wdt_s", "pclk_peri_root", 0,
721 RV1106_PERICLKGATE_CON(1), 4, GFLAGS),
722 GATE(TCLK_WDT_S, "tclk_wdt_s", "xin24m", 0,
723 RV1106_PERICLKGATE_CON(1), 5, GFLAGS),
724
725 /* PD_PMU */
726 COMPOSITE_FRACMUX(CLK_RTC32K_FRAC, "clk_rtc32k_frac", "xin24m", CLK_IGNORE_UNUSED,
727 RV1106_PMUCLKSEL_CON(6), 0,
728 RV1106_PMUCLKGATE_CON(1), 14, GFLAGS,
729 &rv1106_rtc32k_pmu_fracmux),
730 DIV(CLK_100M_PMU, "clk_100m_pmu", "clk_200m_src", 0,
731 RV1106_PMUCLKSEL_CON(0), 0, 3, DFLAGS),
732 COMPOSITE_NODIV(PCLK_PMU_ROOT, "pclk_pmu_root", mux_100m_pmu_24m_p, CLK_IS_CRITICAL,
733 RV1106_PMUCLKSEL_CON(0), 3, 1, MFLAGS,
734 RV1106_PMUCLKGATE_CON(0), 1, GFLAGS),
735 COMPOSITE_NODIV(HCLK_PMU_ROOT, "hclk_pmu_root", mux_200m_100m_24m_p, CLK_IS_CRITICAL,
736 RV1106_PMUCLKSEL_CON(0), 4, 2, MFLAGS,
737 RV1106_PMUCLKGATE_CON(0), 2, GFLAGS),
738 GATE(CLK_PMU, "clk_pmu", "xin24m", CLK_IS_CRITICAL,
739 RV1106_PMUCLKGATE_CON(1), 0, GFLAGS),
740 GATE(PCLK_PMU, "pclk_pmu", "pclk_pmu_root", CLK_IS_CRITICAL,
741 RV1106_PMUCLKGATE_CON(1), 1, GFLAGS),
742 GATE(CLK_DDR_FAIL_SAFE, "clk_ddr_fail_safe", "clk_pmu", 0,
743 RV1106_PMUCLKGATE_CON(1), 15, GFLAGS),
744 GATE(PCLK_PMU_GPIO0, "pclk_pmu_gpio0", "pclk_pmu_root", 0,
745 RV1106_PMUCLKGATE_CON(1), 2, GFLAGS),
746 COMPOSITE_NODIV(DBCLK_PMU_GPIO0, "dbclk_pmu_gpio0", mux_24m_32k_p, 0,
747 RV1106_PMUCLKSEL_CON(0), 15, 1, MFLAGS,
748 RV1106_PMUCLKGATE_CON(1), 3, GFLAGS),
749 GATE(PCLK_I2C1, "pclk_i2c1", "pclk_pmu_root", 0,
750 RV1106_PMUCLKGATE_CON(0), 3, GFLAGS),
751 COMPOSITE_NODIV(CLK_I2C1, "clk_i2c1", mux_200m_100m_24m_32k_p, 0,
752 RV1106_PMUCLKSEL_CON(0), 6, 2, MFLAGS,
753 RV1106_PMUCLKGATE_CON(0), 4, GFLAGS),
754 GATE(PCLK_PMU_MAILBOX, "pclk_pmu_mailbox", "pclk_pmu_root", 0,
755 RV1106_PMUCLKGATE_CON(2), 10, GFLAGS),
756 GATE(CLK_PMU_MCU, "clk_pmu_mcu", "hclk_pmu_root", 0,
757 RV1106_PMUCLKGATE_CON(0), 9, GFLAGS),
758 GATE(CLK_PMU_MCU_RTC, "clk_pmu_mcu_rtc", "xin24m", 0,
759 RV1106_PMUCLKGATE_CON(0), 13, GFLAGS),
760 COMPOSITE_NOMUX(CLK_PVTM_PMU, "clk_pvtm_pmu", "xin24m", 0,
761 RV1106_PMUCLKSEL_CON(1), 0, 5, DFLAGS,
762 RV1106_PMUCLKGATE_CON(1), 4, GFLAGS),
763 GATE(PCLK_PVTM_PMU, "pclk_pvtm_pmu", "pclk_pmu_root", 0,
764 RV1106_PMUCLKGATE_CON(1), 5, GFLAGS),
765 GATE(CLK_REFOUT, "clk_refout", "xin24m", 0,
766 RV1106_PMUCLKGATE_CON(2), 13, GFLAGS),
767 GATE(HCLK_PMU_SRAM, "hclk_pmu_sram", "hclk_pmu_root", CLK_IGNORE_UNUSED,
768 RV1106_PMUCLKGATE_CON(0), 8, GFLAGS),
769 GATE(PCLK_PMU_WDT, "pclk_pmu_wdt", "pclk_pmu_root", 0,
770 RV1106_PMUCLKGATE_CON(2), 8, GFLAGS),
771 COMPOSITE_NODIV(TCLK_PMU_WDT, "tclk_pmu_wdt", mux_24m_32k_p, 0,
772 RV1106_PMUCLKSEL_CON(7), 2, 1, MFLAGS,
773 RV1106_PMUCLKGATE_CON(2), 9, GFLAGS),
774
775 /* PD_SUBDDR */
776 COMPOSITE(CLK_CORE_DDRC_SRC, "clk_core_ddrc_src", mux_dpll_300m_p, CLK_IGNORE_UNUSED,
777 RV1106_SUBDDRCLKSEL_CON(0), 5, 1, MFLAGS, 0, 5, DFLAGS,
778 RV1106_SUBDDRCLKGATE_CON(0), 2, GFLAGS),
779 GATE(CLK_DFICTRL, "clk_dfictrl", "clk_core_ddrc_src", CLK_IGNORE_UNUSED,
780 RV1106_SUBDDRCLKGATE_CON(0), 5, GFLAGS),
781 GATE(CLK_DDRMON, "clk_ddrmon", "clk_core_ddrc_src", CLK_IGNORE_UNUSED,
782 RV1106_SUBDDRCLKGATE_CON(0), 4, GFLAGS),
783 GATE(CLK_DDR_PHY, "clk_ddr_phy", "clk_core_ddrc_src", CLK_IGNORE_UNUSED,
784 RV1106_SUBDDRCLKGATE_CON(0), 6, GFLAGS),
785 GATE(ACLK_DDRC, "aclk_ddrc", "clk_core_ddrc_src", CLK_IS_CRITICAL,
786 RV1106_SUBDDRCLKGATE_CON(0), 1, GFLAGS),
787 GATE(CLK_CORE_DDRC, "clk_core_ddrc", "clk_core_ddrc_src", CLK_IS_CRITICAL,
788 RV1106_SUBDDRCLKGATE_CON(0), 3, GFLAGS),
789
790 /* PD_VEPU */
791 COMPOSITE_NODIV(HCLK_VEPU_ROOT, "hclk_vepu_root", mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL,
792 RV1106_VEPUCLKSEL_CON(0), 0, 2, MFLAGS,
793 RV1106_VEPUCLKGATE_CON(0), 0, GFLAGS),
794 COMPOSITE_NODIV(ACLK_VEPU_COM_ROOT, "aclk_vepu_com_root", mux_400m_200m_100m_24m_p, CLK_IS_CRITICAL,
795 RV1106_VEPUCLKSEL_CON(0), 2, 2, MFLAGS,
796 RV1106_VEPUCLKGATE_CON(0), 1, GFLAGS),
797 COMPOSITE_NODIV(ACLK_VEPU_ROOT, "aclk_vepu_root", mux_300m_200m_100m_24m_p, CLK_IS_CRITICAL,
798 RV1106_VEPUCLKSEL_CON(0), 4, 2, MFLAGS,
799 RV1106_VEPUCLKGATE_CON(0), 2, GFLAGS),
800 COMPOSITE_NODIV(PCLK_VEPU_ROOT, "pclk_vepu_root", mux_100m_50m_24m_p, CLK_IS_CRITICAL,
801 RV1106_VEPUCLKSEL_CON(0), 6, 2, MFLAGS,
802 RV1106_VEPUCLKGATE_CON(0), 3, GFLAGS),
803 GATE(PCLK_SPI0, "pclk_spi0", "pclk_vepu_root", 0,
804 RV1106_VEPUCLKGATE_CON(1), 2, GFLAGS),
805 COMPOSITE_NODIV(CLK_SPI0, "clk_spi0", mux_200m_100m_50m_24m_p, 0,
806 RV1106_VEPUCLKSEL_CON(0), 12, 2, MFLAGS,
807 RV1106_VEPUCLKGATE_CON(1), 3, GFLAGS),
808 GATE(CLK_UART_DETN_FLT, "clk_uart_detn_flt", "xin24m", 0,
809 RV1106_VEPUCLKGATE_CON(1), 8, GFLAGS),
810 GATE(HCLK_VEPU, "hclk_vepu", "hclk_vepu_root", 0,
811 RV1106_VEPUCLKGATE_CON(0), 8, GFLAGS),
812 GATE(ACLK_VEPU, "aclk_vepu", "aclk_vepu_root", 0,
813 RV1106_VEPUCLKGATE_CON(0), 9, GFLAGS),
814 COMPOSITE_NODIV(CLK_CORE_VEPU, "clk_core_vepu", mux_400m_300m_pvtpll0_pvtpll1_p, 0,
815 RV1106_VEPUCLKSEL_CON(0), 8, 2, MFLAGS,
816 RV1106_VEPUCLKGATE_CON(0), 10, GFLAGS),
817 COMPOSITE_NODIV(CLK_CORE_VEPU_DVBM, "clk_core_vepu_dvbm", mux_200m_100m_50m_24m_p, 0,
818 RV1106_VEPUCLKSEL_CON(0), 10, 2, MFLAGS,
819 RV1106_VEPUCLKGATE_CON(0), 13, GFLAGS),
820 GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_vepu_root", 0,
821 RV1106_VEPUCLKGATE_CON(0), 15, GFLAGS),
822 GATE(DBCLK_GPIO1, "dbclk_gpio1", "xin24m", 0,
823 RV1106_VEPUCLKGATE_CON(1), 0, GFLAGS),
824 GATE(HCLK_VEPU_PP, "hclk_vepu_pp", "hclk_vepu_root", 0,
825 RV1106_VEPUCLKGATE_CON(0), 11, GFLAGS),
826 GATE(ACLK_VEPU_PP, "aclk_vepu_pp", "aclk_vepu_root", 0,
827 RV1106_VEPUCLKGATE_CON(0), 12, GFLAGS),
828
829 /* PD_VI */
830 COMPOSITE_NODIV(HCLK_VI_ROOT, "hclk_vi_root", mux_150m_100m_50m_24m_p, CLK_IS_CRITICAL,
831 RV1106_VICLKSEL_CON(0), 0, 2, MFLAGS,
832 RV1106_VICLKGATE_CON(0), 0, GFLAGS),
833 COMPOSITE_NODIV(ACLK_VI_ROOT, "aclk_vi_root", mux_339m_200m_100m_24m_p, CLK_IS_CRITICAL,
834 RV1106_VICLKSEL_CON(0), 2, 2, MFLAGS,
835 RV1106_VICLKGATE_CON(0), 1, GFLAGS),
836 COMPOSITE_NODIV(PCLK_VI_ROOT, "pclk_vi_root", mux_150m_100m_50m_24m_p, CLK_IS_CRITICAL,
837 RV1106_VICLKSEL_CON(0), 4, 2, MFLAGS,
838 RV1106_VICLKGATE_CON(0), 2, GFLAGS),
839 COMPOSITE_NODIV(PCLK_VI_RTC_ROOT, "pclk_vi_rtc_root", mux_50m_24m_p, 0,
840 RV1106_VICLKSEL_CON(0), 6, 1, MFLAGS,
841 RV1106_VICLKGATE_CON(0), 3, GFLAGS),
842
843 GATE(PCLK_CSIHOST0, "pclk_csihost0", "pclk_vi_root", 0,
844 RV1106_VICLKGATE_CON(1), 3, GFLAGS),
845 GATE(PCLK_CSIHOST1, "pclk_csihost1", "pclk_vi_root", 0,
846 RV1106_VICLKGATE_CON(1), 5, GFLAGS),
847 GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_vi_root", 0,
848 RV1106_VICLKGATE_CON(1), 15, GFLAGS),
849 GATE(DBCLK_GPIO3, "dbclk_gpio3", "xin24m", 0,
850 RV1106_VICLKGATE_CON(2), 0, GFLAGS),
851 GATE(HCLK_ISP3P2, "hclk_isp3p2", "hclk_vi_root", 0,
852 RV1106_VICLKGATE_CON(0), 7, GFLAGS),
853 GATE(ACLK_ISP3P2, "aclk_isp3p2", "aclk_vi_root", 0,
854 RV1106_VICLKGATE_CON(0), 8, GFLAGS),
855 COMPOSITE_NODIV(CLK_CORE_ISP3P2, "clk_core_isp3p2", mux_339m_200m_pvtpll0_pvtpll1_p, 0,
856 RV1106_VICLKSEL_CON(0), 7, 2, MFLAGS,
857 RV1106_VICLKGATE_CON(0), 9, GFLAGS),
858 GATE(PCLK_MIPICSIPHY, "pclk_mipicsiphy", "pclk_vi_root", 0,
859 RV1106_VICLKGATE_CON(1), 14, GFLAGS),
860 COMPOSITE(CCLK_SRC_SDMMC, "cclk_src_sdmmc", mux_400m_24m_p, 0,
861 RV1106_VICLKSEL_CON(1), 14, 1, MFLAGS, 8, 6, DFLAGS,
862 RV1106_VICLKGATE_CON(1), 11, GFLAGS),
863 GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_vi_root", 0,
864 RV1106_VICLKGATE_CON(1), 12, GFLAGS),
865 GATE(CLK_SDMMC_DETN_FLT, "clk_sdmmc_detn_flt", "xin24m", 0,
866 RV1106_VICLKGATE_CON(1), 13, GFLAGS),
867 GATE(PCLK_VI_RTC_TEST, "pclk_vi_rtc_test", "pclk_vi_rtc_root", 0,
868 RV1106_VICLKGATE_CON(2), 5, GFLAGS),
869 GATE(PCLK_VI_RTC_PHY, "pclk_vi_rtc_phy", "pclk_vi_rtc_root", 0,
870 RV1106_VICLKGATE_CON(2), 6, GFLAGS),
871 COMPOSITE_NODIV(DCLK_VICAP, "dclk_vicap", mux_339m_200m_100m_24m_p, 0,
872 RV1106_VICLKSEL_CON(0), 9, 2, MFLAGS,
873 RV1106_VICLKGATE_CON(0), 10, GFLAGS),
874 GATE(ACLK_VICAP, "aclk_vicap", "aclk_vi_root", 0,
875 RV1106_VICLKGATE_CON(0), 12, GFLAGS),
876 GATE(HCLK_VICAP, "hclk_vicap", "hclk_vi_root", 0,
877 RV1106_VICLKGATE_CON(0), 13, GFLAGS),
878
879 /* PD_VO */
880 COMPOSITE_NODIV(ACLK_MAC_ROOT, "aclk_mac_root", mux_300m_200m_100m_24m_p, 0,
881 RV1106_VOCLKSEL_CON(1), 12, 2, MFLAGS,
882 RV1106_VOCLKGATE_CON(1), 4, GFLAGS),
883 COMPOSITE_NODIV(ACLK_VO_ROOT, "aclk_vo_root", mux_400m_200m_100m_24m_p, CLK_IS_CRITICAL,
884 RV1106_VOCLKSEL_CON(0), 0, 2, MFLAGS,
885 RV1106_VOCLKGATE_CON(0), 0, GFLAGS),
886 COMPOSITE_NODIV(HCLK_VO_ROOT, "hclk_vo_root", mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL,
887 RV1106_VOCLKSEL_CON(0), 2, 2, MFLAGS,
888 RV1106_VOCLKGATE_CON(0), 1, GFLAGS),
889 COMPOSITE_NODIV(PCLK_VO_ROOT, "pclk_vo_root", mux_150m_100m_50m_24m_p, CLK_IS_CRITICAL,
890 RV1106_VOCLKSEL_CON(0), 4, 2, MFLAGS,
891 RV1106_VOCLKGATE_CON(0), 2, GFLAGS),
892 COMPOSITE_NODIV(ACLK_VOP_ROOT, "aclk_vop_root", mux_300m_200m_100m_24m_p, 0,
893 RV1106_VOCLKSEL_CON(1), 10, 2, MFLAGS,
894 RV1106_VOCLKGATE_CON(0), 11, GFLAGS),
895
896 GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_vo_root", 0,
897 RV1106_VOCLKGATE_CON(3), 0, GFLAGS),
898 GATE(DBCLK_GPIO2, "dbclk_gpio2", "xin24m", 0,
899 RV1106_VOCLKGATE_CON(3), 1, GFLAGS),
900 GATE(ACLK_MAC, "aclk_mac", "aclk_mac_root", 0,
901 RV1106_VOCLKGATE_CON(1), 8, GFLAGS),
902 GATE(PCLK_MAC, "pclk_mac", "pclk_vo_root", 0,
903 RV1106_VOCLKGATE_CON(1), 9, GFLAGS),
904 FACTOR(CLK_GMAC0_50M_O, "clk_gmac0_50m_o", "clk_50m_src", 0, 1, 1),
905 FACTOR(CLK_GMAC0_REF_50M, "clk_gmac0_ref_50m", "clk_gmac0_50m_o", 0, 1, 1),
906 DIV(CLK_GMAC0_TX_50M_O, "clk_gmac0_tx_50m_o", "clk_gmac0_50m_o", 0,
907 RV1106_VOCLKSEL_CON(2), 1, 6, DFLAGS),
908 GATE(CLK_MACPHY, "clk_macphy", "xin24m", 0,
909 RV1106_VOCLKGATE_CON(2), 13, GFLAGS),
910 GATE(CLK_OTPC_ARB, "clk_otpc_arb", "xin24m", 0,
911 RV1106_VOCLKGATE_CON(2), 11, GFLAGS),
912 GATE(PCLK_OTPC_NS, "pclk_otpc_ns", "pclk_vo_root", 0,
913 RV1106_VOCLKGATE_CON(2), 3, GFLAGS),
914 GATE(CLK_SBPI_OTPC_NS, "clk_sbpi_otpc_ns", "xin24m", 0,
915 RV1106_VOCLKGATE_CON(2), 5, GFLAGS),
916 COMPOSITE_NOMUX(CLK_USER_OTPC_NS, "clk_user_otpc_ns", "xin24m", 0,
917 RV1106_VOCLKSEL_CON(3), 10, 3, DFLAGS,
918 RV1106_VOCLKGATE_CON(2), 6, GFLAGS),
919 GATE(PCLK_OTPC_S, "pclk_otpc_s", "pclk_vo_root", 0,
920 RV1106_VOCLKGATE_CON(2), 7, GFLAGS),
921 GATE(CLK_SBPI_OTPC_S, "clk_sbpi_otpc_s", "xin24m", 0,
922 RV1106_VOCLKGATE_CON(2), 9, GFLAGS),
923 COMPOSITE_NOMUX(CLK_USER_OTPC_S, "clk_user_otpc_s", "xin24m", 0,
924 RV1106_VOCLKSEL_CON(3), 13, 3, DFLAGS,
925 RV1106_VOCLKGATE_CON(2), 10, GFLAGS),
926 GATE(PCLK_OTP_MASK, "pclk_otp_mask", "pclk_vo_root", 0,
927 RV1106_VOCLKGATE_CON(2), 14, GFLAGS),
928 GATE(CLK_PMC_OTP, "clk_pmc_otp", "clk_sbpi_otpc_s", 0,
929 RV1106_VOCLKGATE_CON(2), 15, GFLAGS),
930 GATE(HCLK_RGA2E, "hclk_rga2e", "hclk_vo_root", 0,
931 RV1106_VOCLKGATE_CON(0), 7, GFLAGS),
932 GATE(ACLK_RGA2E, "aclk_rga2e", "aclk_vo_root", 0,
933 RV1106_VOCLKGATE_CON(0), 8, GFLAGS),
934 COMPOSITE_NODIV(CLK_CORE_RGA2E, "clk_core_rga2e", mux_400m_200m_100m_24m_p, 0,
935 RV1106_VOCLKSEL_CON(1), 8, 2, MFLAGS,
936 RV1106_VOCLKGATE_CON(0), 9, GFLAGS),
937 COMPOSITE(CCLK_SRC_SDIO, "cclk_src_sdio", mux_400m_24m_p, 0,
938 RV1106_VOCLKSEL_CON(2), 13, 1, MFLAGS, 7, 6, DFLAGS,
939 RV1106_VOCLKGATE_CON(1), 14, GFLAGS),
940 GATE(HCLK_SDIO, "hclk_sdio", "hclk_vo_root", 0,
941 RV1106_VOCLKGATE_CON(1), 15, GFLAGS),
942 GATE(PCLK_TSADC, "pclk_tsadc", "pclk_vo_root", 0,
943 RV1106_VOCLKGATE_CON(2), 0, GFLAGS),
944 COMPOSITE_NOMUX(CLK_TSADC, "clk_tsadc", "xin24m", 0,
945 RV1106_VOCLKSEL_CON(3), 0, 5, DFLAGS,
946 RV1106_VOCLKGATE_CON(2), 1, GFLAGS),
947 COMPOSITE_NOMUX(CLK_TSADC_TSEN, "clk_tsadc_tsen", "xin24m", 0,
948 RV1106_VOCLKSEL_CON(3), 5, 5, DFLAGS,
949 RV1106_VOCLKGATE_CON(2), 2, GFLAGS),
950 GATE(HCLK_VOP, "hclk_vop", "hclk_vo_root", 0,
951 RV1106_VOCLKGATE_CON(0), 13, GFLAGS),
952 GATE(DCLK_VOP, "dclk_vop", "dclk_vop_src", 0,
953 RV1106_VOCLKGATE_CON(0), 14, GFLAGS),
954 GATE(ACLK_VOP, "aclk_vop", "aclk_vop_root", 0,
955 RV1106_VOCLKGATE_CON(0), 15, GFLAGS),
956
957 /* IO CLK */
958 GATE(RX0PCLK_VICAP, "rx0pclk_vicap", "rx0pclk_vicap_io", 0,
959 RV1106_VICLKGATE_CON(1), 0, GFLAGS),
960 GATE(RX1PCLK_VICAP, "rx1pclk_vicap", "rx1pclk_vicap_io", 0,
961 RV1106_VICLKGATE_CON(1), 1, GFLAGS),
962 GATE(ISP0CLK_VICAP, "isp0clk_vicap", "isp0clk_vicap_io", 0,
963 RV1106_VICLKGATE_CON(1), 2, GFLAGS),
964 GATE(I0CLK_VICAP, "i0clk_vicap", "i0clk_vicap_io", 0,
965 RV1106_VICLKGATE_CON(0), 14, GFLAGS),
966 GATE(I1CLK_VICAP, "i1clk_vicap", "i1clk_vicap_io", 0,
967 RV1106_VICLKGATE_CON(0), 15, GFLAGS),
968 GATE(PCLK_VICAP, "pclk_vicap", "pclk_vicap_io", 0,
969 RV1106_VICLKGATE_CON(0), 11, GFLAGS),
970 GATE(CLK_RXBYTECLKHS_0, "clk_rxbyteclkhs_0", "clk_rxbyteclkhs_0_io", 0,
971 RV1106_VICLKGATE_CON(1), 4, GFLAGS),
972 GATE(CLK_RXBYTECLKHS_1, "clk_rxbyteclkhs_1", "clk_rxbyteclkhs_1_io", 0,
973 RV1106_VICLKGATE_CON(1), 6, GFLAGS),
974
975 GATE(PCLK_VICAP_VEPU, "pclk_vicap_vepu", "pclk_vicap_vepu_io", 0,
976 RV1106_VEPUCLKGATE_CON(0), 14, GFLAGS),
977 GATE(SCLK_IN_SPI0, "sclk_in_spi0", "sclk_in_spi0_io", 0,
978 RV1106_VEPUCLKGATE_CON(1), 4, GFLAGS),
979
980 GATE(CLK_UTMI_USBOTG, "clk_utmi_usbotg", "clk_utmi_usbotg_io", 0,
981 RV1106_PERICLKGATE_CON(4), 9, GFLAGS),
982 };
983
984 static struct rockchip_clk_branch rv1106_grf_clk_branches[] __initdata = {
985 MMC_GRF(SCLK_EMMC_DRV, "emmc_drv", "cclk_src_emmc",
986 RV1106_EMMC_CON0, 1, grf_type_sys),
987 MMC_GRF(SCLK_EMMC_SAMPLE, "emmc_sample", "cclk_src_emmc",
988 RV1106_EMMC_CON1, 1, grf_type_sys),
989 MMC_GRF(SCLK_SDMMC_DRV, "sdmmc_drv", "cclk_src_sdmmc",
990 RV1106_SDMMC_CON0, 1, grf_type_sys),
991 MMC_GRF(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "cclk_src_sdmmc",
992 RV1106_SDMMC_CON1, 1, grf_type_sys),
993 MMC_GRF(SCLK_SDIO_DRV, "sdio_drv", "cclk_src_sdio",
994 RV1106_SDIO_CON0, 1, grf_type_sys),
995 MMC_GRF(SCLK_SDIO_SAMPLE, "sdio_sample", "cclk_src_sdio",
996 RV1106_SDIO_CON1, 1, grf_type_sys),
997 };
998
rv1106_pvtpll_init(struct rockchip_clk_provider * ctx)999 static void __init rv1106_pvtpll_init(struct rockchip_clk_provider *ctx)
1000 {
1001 /* set pvtpll ref clk mux */
1002 writel_relaxed(CPU_PVTPLL_PATH_CORE, ctx->reg_base + CPU_CLK_PATH_BASE);
1003
1004 if (!IS_ERR(ctx->grf)) {
1005 regmap_write(ctx->grf, CPU_PVTPLL_CON0_H,
1006 HIWORD_UPDATE(0x7, PVTPLL_LENGTH_SEL_MASK,
1007 PVTPLL_LENGTH_SEL_SHIFT));
1008 regmap_write(ctx->grf, CPU_PVTPLL_CON0_L,
1009 HIWORD_UPDATE(0x1, PVTPLL_RING_SEL_MASK,
1010 PVTPLL_RING_SEL_SHIFT));
1011 regmap_write(ctx->grf, CPU_PVTPLL_CON0_L,
1012 HIWORD_UPDATE(0x3, PVTPLL_EN_MASK,
1013 PVTPLL_EN_SHIFT));
1014 }
1015
1016 writel_relaxed(0x007f0000, ctx->reg_base + CRU_PVTPLL0_CON0_H);
1017 writel_relaxed(0xffff0018, ctx->reg_base + CRU_PVTPLL0_CON1_L);
1018 writel_relaxed(0xffff0004, ctx->reg_base + CRU_PVTPLL0_CON2_H);
1019 writel_relaxed(0x00030003, ctx->reg_base + CRU_PVTPLL0_CON0_L);
1020
1021 writel_relaxed(0x007f0000, ctx->reg_base + CRU_PVTPLL1_CON0_H);
1022 writel_relaxed(0xffff0018, ctx->reg_base + CRU_PVTPLL1_CON1_L);
1023 writel_relaxed(0xffff0004, ctx->reg_base + CRU_PVTPLL1_CON2_H);
1024 writel_relaxed(0x00030003, ctx->reg_base + CRU_PVTPLL1_CON0_L);
1025 }
1026
clk_rv1106_probe(struct platform_device * pdev)1027 static int __init clk_rv1106_probe(struct platform_device *pdev)
1028 {
1029 struct device *dev = &pdev->dev;
1030 struct device_node *np = dev->of_node;
1031 struct rockchip_clk_provider *ctx;
1032 unsigned long clk_nr;
1033 void __iomem *reg_base;
1034 int ret;
1035
1036 clk_nr = rockchip_clk_find_max_clk_id(rv1106_clk_branches,
1037 ARRAY_SIZE(rv1106_clk_branches)) + 1;
1038 clk_nr = max(clk_nr,
1039 rockchip_clk_find_max_clk_id(rv1106_grf_clk_branches,
1040 ARRAY_SIZE(rv1106_grf_clk_branches)) + 1);
1041 reg_base = devm_platform_ioremap_resource(pdev, 0);
1042 if (IS_ERR(reg_base))
1043 return dev_err_probe(dev, PTR_ERR(reg_base),
1044 "could not map cru region");
1045
1046 ctx = rockchip_clk_init(np, reg_base, clk_nr);
1047 if (IS_ERR(ctx))
1048 return dev_err_probe(dev, PTR_ERR(ctx),
1049 "rockchip clk init failed");
1050
1051 rv1106_pvtpll_init(ctx);
1052
1053 rockchip_clk_register_plls(ctx, rv1106_pll_clks,
1054 ARRAY_SIZE(rv1106_pll_clks),
1055 RV1106_GRF_SOC_STATUS0);
1056
1057 rockchip_clk_register_armclk(ctx, ARMCLK, "armclk",
1058 mux_armclk_p, ARRAY_SIZE(mux_armclk_p),
1059 &rv1106_cpuclk_data, rv1106_cpuclk_rates,
1060 ARRAY_SIZE(rv1106_cpuclk_rates));
1061
1062 rockchip_clk_register_branches(ctx, rv1106_clk_branches,
1063 ARRAY_SIZE(rv1106_clk_branches));
1064
1065 /*
1066 * The MMC drive and sample phase clocks have their control
1067 * registers in the GRF region, so they can only be provided when
1068 * the rockchip,grf property points at a valid syscon.
1069 */
1070 if (!IS_ERR(ctx->grf)) {
1071 ret = rockchip_clk_add_grf(ctx, ctx->grf, grf_type_sys);
1072 if (ret)
1073 dev_err(dev, "failed to add grf: %d\n", ret);
1074 else
1075 rockchip_clk_register_branches(ctx,
1076 rv1106_grf_clk_branches,
1077 ARRAY_SIZE(rv1106_grf_clk_branches));
1078 }
1079
1080 rockchip_register_restart_notifier(ctx, RV1106_GLB_SRST_FST, NULL);
1081
1082 rockchip_clk_of_add_provider(np, ctx);
1083
1084 return 0;
1085 }
1086
1087 static const struct of_device_id clk_rv1106_match_table[] = {
1088 { .compatible = "rockchip,rv1106-cru" },
1089 { /* end */ }
1090 };
1091
1092 static struct platform_driver clk_rv1106_driver = {
1093 .driver = {
1094 .name = "clk-rv1106",
1095 .of_match_table = clk_rv1106_match_table,
1096 .suppress_bind_attrs = true,
1097 },
1098 };
1099 builtin_platform_driver_probe(clk_rv1106_driver, clk_rv1106_probe);
1100