1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2021 Rockchip Electronics Co. Ltd. 4 * Author: Elaine Zhang <zhangqing@rock-chips.com> 5 */ 6 7 #include <linux/clk-provider.h> 8 #include <linux/module.h> 9 #include <linux/of.h> 10 #include <linux/of_address.h> 11 #include <linux/platform_device.h> 12 #include <linux/syscore_ops.h> 13 #include <dt-bindings/clock/rk3568-cru.h> 14 #include "clk.h" 15 16 #define RK3568_GRF_SOC_STATUS0 0x580 17 18 enum rk3568_pmu_plls { 19 ppll, hpll, 20 }; 21 22 enum rk3568_plls { 23 apll, dpll, gpll, cpll, npll, vpll, 24 }; 25 26 static struct rockchip_pll_rate_table rk3568_pll_rates[] = { 27 /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */ 28 RK3036_PLL_RATE(2208000000, 1, 92, 1, 1, 1, 0), 29 RK3036_PLL_RATE(2184000000, 1, 91, 1, 1, 1, 0), 30 RK3036_PLL_RATE(2160000000, 1, 90, 1, 1, 1, 0), 31 RK3036_PLL_RATE(2088000000, 1, 87, 1, 1, 1, 0), 32 RK3036_PLL_RATE(2064000000, 1, 86, 1, 1, 1, 0), 33 RK3036_PLL_RATE(2040000000, 1, 85, 1, 1, 1, 0), 34 RK3036_PLL_RATE(2016000000, 1, 84, 1, 1, 1, 0), 35 RK3036_PLL_RATE(1992000000, 1, 83, 1, 1, 1, 0), 36 RK3036_PLL_RATE(1920000000, 1, 80, 1, 1, 1, 0), 37 RK3036_PLL_RATE(1896000000, 1, 79, 1, 1, 1, 0), 38 RK3036_PLL_RATE(1800000000, 1, 75, 1, 1, 1, 0), 39 RK3036_PLL_RATE(1704000000, 1, 71, 1, 1, 1, 0), 40 RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0), 41 RK3036_PLL_RATE(1600000000, 3, 200, 1, 1, 1, 0), 42 RK3036_PLL_RATE(1584000000, 1, 132, 2, 1, 1, 0), 43 RK3036_PLL_RATE(1560000000, 1, 130, 2, 1, 1, 0), 44 RK3036_PLL_RATE(1536000000, 1, 128, 2, 1, 1, 0), 45 RK3036_PLL_RATE(1512000000, 1, 126, 2, 1, 1, 0), 46 RK3036_PLL_RATE(1488000000, 1, 124, 2, 1, 1, 0), 47 RK3036_PLL_RATE(1464000000, 1, 122, 2, 1, 1, 0), 48 RK3036_PLL_RATE(1440000000, 1, 120, 2, 1, 1, 0), 49 RK3036_PLL_RATE(1416000000, 1, 118, 2, 1, 1, 0), 50 RK3036_PLL_RATE(1400000000, 3, 350, 2, 1, 1, 0), 51 RK3036_PLL_RATE(1392000000, 1, 116, 2, 1, 1, 0), 52 RK3036_PLL_RATE(1368000000, 1, 114, 2, 1, 1, 0), 53 RK3036_PLL_RATE(1344000000, 1, 112, 2, 1, 1, 0), 54 RK3036_PLL_RATE(1320000000, 1, 110, 2, 1, 1, 0), 55 RK3036_PLL_RATE(1296000000, 1, 108, 2, 1, 1, 0), 56 RK3036_PLL_RATE(1272000000, 1, 106, 2, 1, 1, 0), 57 RK3036_PLL_RATE(1248000000, 1, 104, 2, 1, 1, 0), 58 RK3036_PLL_RATE(1200000000, 1, 100, 2, 1, 1, 0), 59 RK3036_PLL_RATE(1188000000, 1, 99, 2, 1, 1, 0), 60 RK3036_PLL_RATE(1104000000, 1, 92, 2, 1, 1, 0), 61 RK3036_PLL_RATE(1100000000, 3, 275, 2, 1, 1, 0), 62 RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0), 63 RK3036_PLL_RATE(1000000000, 3, 250, 2, 1, 1, 0), 64 RK3036_PLL_RATE(912000000, 1, 76, 2, 1, 1, 0), 65 RK3036_PLL_RATE(816000000, 1, 68, 2, 1, 1, 0), 66 RK3036_PLL_RATE(800000000, 3, 200, 2, 1, 1, 0), 67 RK3036_PLL_RATE(700000000, 3, 350, 4, 1, 1, 0), 68 RK3036_PLL_RATE(696000000, 1, 116, 4, 1, 1, 0), 69 RK3036_PLL_RATE(600000000, 1, 100, 4, 1, 1, 0), 70 RK3036_PLL_RATE(594000000, 1, 99, 4, 1, 1, 0), 71 RK3036_PLL_RATE(500000000, 1, 125, 6, 1, 1, 0), 72 RK3036_PLL_RATE(408000000, 1, 68, 2, 2, 1, 0), 73 RK3036_PLL_RATE(312000000, 1, 78, 6, 1, 1, 0), 74 RK3036_PLL_RATE(297000000, 2, 99, 4, 1, 1, 0), 75 RK3036_PLL_RATE(292500000, 1, 195, 4, 4, 1, 0), 76 RK3036_PLL_RATE(241500000, 2, 161, 4, 2, 1, 0), 77 RK3036_PLL_RATE(216000000, 1, 72, 4, 2, 1, 0), 78 RK3036_PLL_RATE(200000000, 1, 100, 3, 4, 1, 0), 79 RK3036_PLL_RATE(148500000, 1, 99, 4, 4, 1, 0), 80 RK3036_PLL_RATE(135000000, 2, 45, 4, 1, 1, 0), 81 RK3036_PLL_RATE(126400000, 1, 79, 5, 3, 1, 0), 82 RK3036_PLL_RATE(119000000, 3, 119, 4, 2, 1, 0), 83 RK3036_PLL_RATE(115200000, 1, 24, 5, 1, 1, 0), 84 RK3036_PLL_RATE(108000000, 2, 45, 5, 1, 1, 0), 85 RK3036_PLL_RATE(101000000, 1, 101, 6, 4, 1, 0), 86 RK3036_PLL_RATE(100000000, 1, 150, 6, 6, 1, 0), 87 RK3036_PLL_RATE(96000000, 1, 96, 6, 4, 1, 0), 88 RK3036_PLL_RATE(78750000, 4, 315, 6, 4, 1, 0), 89 RK3036_PLL_RATE(74250000, 2, 99, 4, 4, 1, 0), 90 { /* sentinel */ }, 91 }; 92 93 #define RK3568_DIV_ATCLK_CORE_MASK 0x1f 94 #define RK3568_DIV_ATCLK_CORE_SHIFT 0 95 #define RK3568_DIV_GICCLK_CORE_MASK 0x1f 96 #define RK3568_DIV_GICCLK_CORE_SHIFT 8 97 #define RK3568_DIV_PCLK_CORE_MASK 0x1f 98 #define RK3568_DIV_PCLK_CORE_SHIFT 0 99 #define RK3568_DIV_PERIPHCLK_CORE_MASK 0x1f 100 #define RK3568_DIV_PERIPHCLK_CORE_SHIFT 8 101 #define RK3568_DIV_ACLK_CORE_MASK 0x1f 102 #define RK3568_DIV_ACLK_CORE_SHIFT 8 103 104 #define RK3568_DIV_SCLK_CORE_MASK 0xf 105 #define RK3568_DIV_SCLK_CORE_SHIFT 0 106 #define RK3568_MUX_SCLK_CORE_MASK 0x3 107 #define RK3568_MUX_SCLK_CORE_SHIFT 8 108 #define RK3568_MUX_SCLK_CORE_NPLL_MASK 0x1 109 #define RK3568_MUX_SCLK_CORE_NPLL_SHIFT 15 110 #define RK3568_MUX_CLK_CORE_APLL_MASK 0x1 111 #define RK3568_MUX_CLK_CORE_APLL_SHIFT 7 112 #define RK3568_MUX_CLK_PVTPLL_MASK 0x1 113 #define RK3568_MUX_CLK_PVTPLL_SHIFT 15 114 115 #define RK3568_CLKSEL1(_sclk_core) \ 116 { \ 117 .reg = RK3568_CLKSEL_CON(2), \ 118 .val = HIWORD_UPDATE(_sclk_core, RK3568_MUX_SCLK_CORE_NPLL_MASK, \ 119 RK3568_MUX_SCLK_CORE_NPLL_SHIFT) | \ 120 HIWORD_UPDATE(_sclk_core, RK3568_MUX_SCLK_CORE_MASK, \ 121 RK3568_MUX_SCLK_CORE_SHIFT) | \ 122 HIWORD_UPDATE(1, RK3568_DIV_SCLK_CORE_MASK, \ 123 RK3568_DIV_SCLK_CORE_SHIFT), \ 124 } 125 126 #define RK3568_CLKSEL2(_aclk_core) \ 127 { \ 128 .reg = RK3568_CLKSEL_CON(5), \ 129 .val = HIWORD_UPDATE(_aclk_core, RK3568_DIV_ACLK_CORE_MASK, \ 130 RK3568_DIV_ACLK_CORE_SHIFT), \ 131 } 132 133 #define RK3568_CLKSEL3(_atclk_core, _gic_core) \ 134 { \ 135 .reg = RK3568_CLKSEL_CON(3), \ 136 .val = HIWORD_UPDATE(_atclk_core, RK3568_DIV_ATCLK_CORE_MASK, \ 137 RK3568_DIV_ATCLK_CORE_SHIFT) | \ 138 HIWORD_UPDATE(_gic_core, RK3568_DIV_GICCLK_CORE_MASK, \ 139 RK3568_DIV_GICCLK_CORE_SHIFT), \ 140 } 141 142 #define RK3568_CLKSEL4(_pclk_core, _periph_core) \ 143 { \ 144 .reg = RK3568_CLKSEL_CON(4), \ 145 .val = HIWORD_UPDATE(_pclk_core, RK3568_DIV_PCLK_CORE_MASK, \ 146 RK3568_DIV_PCLK_CORE_SHIFT) | \ 147 HIWORD_UPDATE(_periph_core, RK3568_DIV_PERIPHCLK_CORE_MASK, \ 148 RK3568_DIV_PERIPHCLK_CORE_SHIFT), \ 149 } 150 151 #define RK3568_CPUCLK_RATE(_prate, _sclk, _acore, _atcore, _gicclk, _pclk, _periph) \ 152 { \ 153 .prate = _prate##U, \ 154 .divs = { \ 155 RK3568_CLKSEL1(_sclk), \ 156 RK3568_CLKSEL2(_acore), \ 157 RK3568_CLKSEL3(_atcore, _gicclk), \ 158 RK3568_CLKSEL4(_pclk, _periph), \ 159 }, \ 160 } 161 162 static struct rockchip_cpuclk_rate_table rk3568_cpuclk_rates[] __initdata = { 163 RK3568_CPUCLK_RATE(1800000000, 0, 1, 7, 7, 7, 7), 164 RK3568_CPUCLK_RATE(1704000000, 0, 1, 7, 7, 7, 7), 165 RK3568_CPUCLK_RATE(1608000000, 0, 1, 5, 5, 5, 5), 166 RK3568_CPUCLK_RATE(1584000000, 0, 1, 5, 5, 5, 5), 167 RK3568_CPUCLK_RATE(1560000000, 0, 1, 5, 5, 5, 5), 168 RK3568_CPUCLK_RATE(1536000000, 0, 1, 5, 5, 5, 5), 169 RK3568_CPUCLK_RATE(1512000000, 0, 1, 5, 5, 5, 5), 170 RK3568_CPUCLK_RATE(1488000000, 0, 1, 5, 5, 5, 5), 171 RK3568_CPUCLK_RATE(1464000000, 0, 1, 5, 5, 5, 5), 172 RK3568_CPUCLK_RATE(1440000000, 0, 1, 5, 5, 5, 5), 173 RK3568_CPUCLK_RATE(1416000000, 0, 1, 5, 5, 5, 5), 174 RK3568_CPUCLK_RATE(1392000000, 0, 1, 5, 5, 5, 5), 175 RK3568_CPUCLK_RATE(1368000000, 0, 1, 5, 5, 5, 5), 176 RK3568_CPUCLK_RATE(1344000000, 0, 1, 5, 5, 5, 5), 177 RK3568_CPUCLK_RATE(1320000000, 0, 1, 5, 5, 5, 5), 178 RK3568_CPUCLK_RATE(1296000000, 0, 1, 5, 5, 5, 5), 179 RK3568_CPUCLK_RATE(1272000000, 0, 1, 5, 5, 5, 5), 180 RK3568_CPUCLK_RATE(1248000000, 0, 1, 5, 5, 5, 5), 181 RK3568_CPUCLK_RATE(1224000000, 0, 1, 5, 5, 5, 5), 182 RK3568_CPUCLK_RATE(1200000000, 0, 1, 3, 3, 3, 3), 183 RK3568_CPUCLK_RATE(1104000000, 0, 1, 3, 3, 3, 3), 184 RK3568_CPUCLK_RATE(1008000000, 0, 1, 3, 3, 3, 3), 185 RK3568_CPUCLK_RATE(912000000, 0, 1, 3, 3, 3, 3), 186 RK3568_CPUCLK_RATE(816000000, 0, 1, 3, 3, 3, 3), 187 RK3568_CPUCLK_RATE(696000000, 0, 1, 3, 3, 3, 3), 188 RK3568_CPUCLK_RATE(600000000, 0, 1, 3, 3, 3, 3), 189 RK3568_CPUCLK_RATE(408000000, 0, 1, 3, 3, 3, 3), 190 RK3568_CPUCLK_RATE(312000000, 0, 1, 3, 3, 3, 3), 191 RK3568_CPUCLK_RATE(216000000, 0, 1, 3, 3, 3, 3), 192 RK3568_CPUCLK_RATE(96000000, 0, 1, 3, 3, 3, 3), 193 }; 194 195 static const struct rockchip_cpuclk_reg_data rk3568_cpuclk_data = { 196 .core_reg[0] = RK3568_CLKSEL_CON(0), 197 .div_core_shift[0] = 0, 198 .div_core_mask[0] = 0x1f, 199 .core_reg[1] = RK3568_CLKSEL_CON(0), 200 .div_core_shift[1] = 8, 201 .div_core_mask[1] = 0x1f, 202 .core_reg[2] = RK3568_CLKSEL_CON(1), 203 .div_core_shift[2] = 0, 204 .div_core_mask[2] = 0x1f, 205 .core_reg[3] = RK3568_CLKSEL_CON(1), 206 .div_core_shift[3] = 8, 207 .div_core_mask[3] = 0x1f, 208 .num_cores = 4, 209 .mux_core_alt = 1, 210 .mux_core_main = 0, 211 .mux_core_shift = 6, 212 .mux_core_mask = 0x1, 213 }; 214 215 PNAME(mux_pll_p) = { "xin24m" }; 216 PNAME(mux_usb480m_p) = { "xin24m", "usb480m_phy", "clk_rtc_32k" }; 217 PNAME(mux_armclk_p) = { "apll", "gpll" }; 218 PNAME(clk_i2s0_8ch_tx_p) = { "clk_i2s0_8ch_tx_src", "clk_i2s0_8ch_tx_frac", "i2s0_mclkin", "xin_osc0_half" }; 219 PNAME(clk_i2s0_8ch_rx_p) = { "clk_i2s0_8ch_rx_src", "clk_i2s0_8ch_rx_frac", "i2s0_mclkin", "xin_osc0_half" }; 220 PNAME(clk_i2s1_8ch_tx_p) = { "clk_i2s1_8ch_tx_src", "clk_i2s1_8ch_tx_frac", "i2s1_mclkin", "xin_osc0_half" }; 221 PNAME(clk_i2s1_8ch_rx_p) = { "clk_i2s1_8ch_rx_src", "clk_i2s1_8ch_rx_frac", "i2s1_mclkin", "xin_osc0_half" }; 222 PNAME(clk_i2s2_2ch_p) = { "clk_i2s2_2ch_src", "clk_i2s2_2ch_frac", "i2s2_mclkin", "xin_osc0_half "}; 223 PNAME(clk_i2s3_2ch_tx_p) = { "clk_i2s3_2ch_tx_src", "clk_i2s3_2ch_tx_frac", "i2s3_mclkin", "xin_osc0_half" }; 224 PNAME(clk_i2s3_2ch_rx_p) = { "clk_i2s3_2ch_rx_src", "clk_i2s3_2ch_rx_frac", "i2s3_mclkin", "xin_osc0_half" }; 225 PNAME(mclk_spdif_8ch_p) = { "mclk_spdif_8ch_src", "mclk_spdif_8ch_frac" }; 226 PNAME(sclk_audpwm_p) = { "sclk_audpwm_src", "sclk_audpwm_frac" }; 227 PNAME(sclk_uart1_p) = { "clk_uart1_src", "clk_uart1_frac", "xin24m" }; 228 PNAME(sclk_uart2_p) = { "clk_uart2_src", "clk_uart2_frac", "xin24m" }; 229 PNAME(sclk_uart3_p) = { "clk_uart3_src", "clk_uart3_frac", "xin24m" }; 230 PNAME(sclk_uart4_p) = { "clk_uart4_src", "clk_uart4_frac", "xin24m" }; 231 PNAME(sclk_uart5_p) = { "clk_uart5_src", "clk_uart5_frac", "xin24m" }; 232 PNAME(sclk_uart6_p) = { "clk_uart6_src", "clk_uart6_frac", "xin24m" }; 233 PNAME(sclk_uart7_p) = { "clk_uart7_src", "clk_uart7_frac", "xin24m" }; 234 PNAME(sclk_uart8_p) = { "clk_uart8_src", "clk_uart8_frac", "xin24m" }; 235 PNAME(sclk_uart9_p) = { "clk_uart9_src", "clk_uart9_frac", "xin24m" }; 236 PNAME(sclk_uart0_p) = { "sclk_uart0_div", "sclk_uart0_frac", "xin24m" }; 237 PNAME(clk_rtc32k_pmu_p) = { "clk_32k_pvtm", "xin32k", "clk_rtc32k_frac" }; 238 PNAME(mpll_gpll_cpll_npll_p) = { "mpll", "gpll", "cpll", "npll" }; 239 PNAME(gpll_cpll_npll_p) = { "gpll", "cpll", "npll" }; 240 PNAME(npll_gpll_p) = { "npll", "gpll" }; 241 PNAME(cpll_gpll_p) = { "cpll", "gpll" }; 242 PNAME(gpll_cpll_p) = { "gpll", "cpll" }; 243 PNAME(gpll_cpll_npll_vpll_p) = { "gpll", "cpll", "npll", "vpll" }; 244 PNAME(apll_gpll_npll_p) = { "apll", "gpll", "npll" }; 245 PNAME(sclk_core_pre_p) = { "sclk_core_src", "npll" }; 246 PNAME(gpll150_gpll100_gpll75_xin24m_p) = { "gpll_150m", "gpll_100m", "gpll_75m", "xin24m" }; 247 PNAME(clk_gpu_pre_mux_p) = { "clk_gpu_src", "gpu_pvtpll_out" }; 248 PNAME(clk_npu_pre_ndft_p) = { "clk_npu_src", "dummy"}; 249 PNAME(clk_npu_p) = { "clk_npu_pre_ndft", "npu_pvtpll_out" }; 250 PNAME(dpll_gpll_cpll_p) = { "dpll", "gpll", "cpll" }; 251 PNAME(clk_ddr1x_p) = { "clk_ddrphy1x_src", "dpll" }; 252 PNAME(gpll200_gpll150_gpll100_xin24m_p) = { "gpll_200m", "gpll_150m", "gpll_100m", "xin24m" }; 253 PNAME(gpll100_gpll75_gpll50_p) = { "gpll_100m", "gpll_75m", "cpll_50m" }; 254 PNAME(i2s0_mclkout_tx_p) = { "clk_i2s0_8ch_tx", "xin_osc0_half" }; 255 PNAME(i2s0_mclkout_rx_p) = { "clk_i2s0_8ch_rx", "xin_osc0_half" }; 256 PNAME(i2s1_mclkout_tx_p) = { "clk_i2s1_8ch_tx", "xin_osc0_half" }; 257 PNAME(i2s1_mclkout_rx_p) = { "clk_i2s1_8ch_rx", "xin_osc0_half" }; 258 PNAME(i2s2_mclkout_p) = { "clk_i2s2_2ch", "xin_osc0_half" }; 259 PNAME(i2s3_mclkout_tx_p) = { "clk_i2s3_2ch_tx", "xin_osc0_half" }; 260 PNAME(i2s3_mclkout_rx_p) = { "clk_i2s3_2ch_rx", "xin_osc0_half" }; 261 PNAME(mclk_pdm_p) = { "gpll_300m", "cpll_250m", "gpll_200m", "gpll_100m" }; 262 PNAME(clk_i2c_p) = { "gpll_200m", "gpll_100m", "xin24m", "cpll_100m" }; 263 PNAME(gpll200_gpll150_gpll100_p) = { "gpll_200m", "gpll_150m", "gpll_100m" }; 264 PNAME(gpll300_gpll200_gpll100_p) = { "gpll_300m", "gpll_200m", "gpll_100m" }; 265 PNAME(clk_nandc_p) = { "gpll_200m", "gpll_150m", "cpll_100m", "xin24m" }; 266 PNAME(sclk_sfc_p) = { "xin24m", "cpll_50m", "gpll_75m", "gpll_100m", "cpll_125m", "gpll_150m" }; 267 PNAME(gpll200_gpll150_cpll125_p) = { "gpll_200m", "gpll_150m", "cpll_125m" }; 268 PNAME(cclk_emmc_p) = { "xin24m", "gpll_200m", "gpll_150m", "cpll_100m", "cpll_50m", "clk_osc0_div_375k" }; 269 PNAME(aclk_pipe_p) = { "gpll_400m", "gpll_300m", "gpll_200m", "xin24m" }; 270 PNAME(gpll200_cpll125_p) = { "gpll_200m", "cpll_125m" }; 271 PNAME(gpll300_gpll200_gpll100_xin24m_p) = { "gpll_300m", "gpll_200m", "gpll_100m", "xin24m" }; 272 PNAME(clk_sdmmc_p) = { "xin24m", "gpll_400m", "gpll_300m", "cpll_100m", "cpll_50m", "clk_osc0_div_750k" }; 273 PNAME(cpll125_cpll50_cpll25_xin24m_p) = { "cpll_125m", "cpll_50m", "cpll_25m", "xin24m" }; 274 PNAME(clk_gmac_ptp_p) = { "cpll_62p5", "gpll_100m", "cpll_50m", "xin24m" }; 275 PNAME(cpll333_gpll300_gpll200_p) = { "cpll_333m", "gpll_300m", "gpll_200m" }; 276 PNAME(cpll_gpll_hpll_p) = { "cpll", "gpll", "hpll" }; 277 PNAME(gpll_usb480m_xin24m_p) = { "gpll", "usb480m", "xin24m", "xin24m" }; 278 PNAME(gpll300_cpll250_gpll100_xin24m_p) = { "gpll_300m", "cpll_250m", "gpll_100m", "xin24m" }; 279 PNAME(cpll_gpll_hpll_vpll_p) = { "cpll", "gpll", "hpll", "vpll" }; 280 PNAME(hpll_vpll_gpll_cpll_p) = { "hpll", "vpll", "gpll", "cpll" }; 281 PNAME(gpll400_cpll333_gpll200_p) = { "gpll_400m", "cpll_333m", "gpll_200m" }; 282 PNAME(gpll100_gpll75_cpll50_xin24m_p) = { "gpll_100m", "gpll_75m", "cpll_50m", "xin24m" }; 283 PNAME(xin24m_gpll100_cpll100_p) = { "xin24m", "gpll_100m", "cpll_100m" }; 284 PNAME(gpll_cpll_usb480m_p) = { "gpll", "cpll", "usb480m" }; 285 PNAME(gpll100_xin24m_cpll100_p) = { "gpll_100m", "xin24m", "cpll_100m" }; 286 PNAME(gpll200_xin24m_cpll100_p) = { "gpll_200m", "xin24m", "cpll_100m" }; 287 PNAME(xin24m_32k_p) = { "xin24m", "clk_rtc_32k" }; 288 PNAME(cpll500_gpll400_gpll300_xin24m_p) = { "cpll_500m", "gpll_400m", "gpll_300m", "xin24m" }; 289 PNAME(gpll400_gpll300_gpll200_xin24m_p) = { "gpll_400m", "gpll_300m", "gpll_200m", "xin24m" }; 290 PNAME(xin24m_cpll100_p) = { "xin24m", "cpll_100m" }; 291 PNAME(ppll_usb480m_cpll_gpll_p) = { "ppll", "usb480m", "cpll", "gpll"}; 292 PNAME(clk_usbphy0_ref_p) = { "clk_ref24m", "xin_osc0_usbphy0_g" }; 293 PNAME(clk_usbphy1_ref_p) = { "clk_ref24m", "xin_osc0_usbphy1_g" }; 294 PNAME(clk_mipidsiphy0_ref_p) = { "clk_ref24m", "xin_osc0_mipidsiphy0_g" }; 295 PNAME(clk_mipidsiphy1_ref_p) = { "clk_ref24m", "xin_osc0_mipidsiphy1_g" }; 296 PNAME(clk_wifi_p) = { "clk_wifi_osc0", "clk_wifi_div" }; 297 PNAME(clk_pciephy0_ref_p) = { "clk_pciephy0_osc0", "clk_pciephy0_div" }; 298 PNAME(clk_pciephy1_ref_p) = { "clk_pciephy1_osc0", "clk_pciephy1_div" }; 299 PNAME(clk_pciephy2_ref_p) = { "clk_pciephy2_osc0", "clk_pciephy2_div" }; 300 PNAME(mux_gmac0_p) = { "clk_mac0_2top", "gmac0_clkin" }; 301 PNAME(mux_gmac0_rgmii_speed_p) = { "clk_gmac0", "clk_gmac0", "clk_gmac0_tx_div50", "clk_gmac0_tx_div5" }; 302 PNAME(mux_gmac0_rmii_speed_p) = { "clk_gmac0_rx_div20", "clk_gmac0_rx_div2" }; 303 PNAME(mux_gmac0_rx_tx_p) = { "clk_gmac0_rgmii_speed", "clk_gmac0_rmii_speed", "clk_gmac0_xpcs_mii" }; 304 PNAME(mux_gmac1_p) = { "clk_mac1_2top", "gmac1_clkin" }; 305 PNAME(mux_gmac1_rgmii_speed_p) = { "clk_gmac1", "clk_gmac1", "clk_gmac1_tx_div50", "clk_gmac1_tx_div5" }; 306 PNAME(mux_gmac1_rmii_speed_p) = { "clk_gmac1_rx_div20", "clk_gmac1_rx_div2" }; 307 PNAME(mux_gmac1_rx_tx_p) = { "clk_gmac1_rgmii_speed", "clk_gmac1_rmii_speed", "clk_gmac1_xpcs_mii" }; 308 PNAME(clk_hdmi_ref_p) = { "hpll", "hpll_ph0" }; 309 PNAME(clk_pdpmu_p) = { "ppll", "gpll" }; 310 PNAME(clk_mac_2top_p) = { "cpll_125m", "cpll_50m", "cpll_25m", "ppll" }; 311 PNAME(clk_pwm0_p) = { "xin24m", "clk_pdpmu" }; 312 PNAME(aclk_rkvdec_pre_p) = { "gpll", "cpll" }; 313 PNAME(clk_rkvdec_core_p) = { "gpll", "cpll", "dummy_npll", "dummy_vpll" }; 314 315 static struct rockchip_pll_clock rk3568_pmu_pll_clks[] __initdata = { 316 [ppll] = PLL(pll_rk3328, PLL_PPLL, "ppll", mux_pll_p, 317 0, RK3568_PMU_PLL_CON(0), 318 RK3568_PMU_MODE_CON0, 0, 4, 0, rk3568_pll_rates), 319 [hpll] = PLL(pll_rk3328, PLL_HPLL, "hpll", mux_pll_p, 320 0, RK3568_PMU_PLL_CON(16), 321 RK3568_PMU_MODE_CON0, 2, 7, 0, rk3568_pll_rates), 322 }; 323 324 static struct rockchip_pll_clock rk3568_pll_clks[] __initdata = { 325 [apll] = PLL(pll_rk3328, PLL_APLL, "apll", mux_pll_p, 326 0, RK3568_PLL_CON(0), 327 RK3568_MODE_CON0, 0, 0, 0, rk3568_pll_rates), 328 [dpll] = PLL(pll_rk3328, PLL_DPLL, "dpll", mux_pll_p, 329 0, RK3568_PLL_CON(8), 330 RK3568_MODE_CON0, 2, 1, 0, NULL), 331 [cpll] = PLL(pll_rk3328, PLL_CPLL, "cpll", mux_pll_p, 332 0, RK3568_PLL_CON(24), 333 RK3568_MODE_CON0, 4, 2, 0, rk3568_pll_rates), 334 [gpll] = PLL(pll_rk3328, PLL_GPLL, "gpll", mux_pll_p, 335 0, RK3568_PLL_CON(16), 336 RK3568_MODE_CON0, 6, 3, 0, rk3568_pll_rates), 337 [npll] = PLL(pll_rk3328, PLL_NPLL, "npll", mux_pll_p, 338 0, RK3568_PLL_CON(32), 339 RK3568_MODE_CON0, 10, 5, 0, rk3568_pll_rates), 340 [vpll] = PLL(pll_rk3328, PLL_VPLL, "vpll", mux_pll_p, 341 0, RK3568_PLL_CON(40), 342 RK3568_MODE_CON0, 12, 6, 0, rk3568_pll_rates), 343 }; 344 345 #define MFLAGS CLK_MUX_HIWORD_MASK 346 #define DFLAGS CLK_DIVIDER_HIWORD_MASK 347 #define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE) 348 349 static struct rockchip_clk_branch rk3568_i2s0_8ch_tx_fracmux __initdata = 350 MUX(CLK_I2S0_8CH_TX, "clk_i2s0_8ch_tx", clk_i2s0_8ch_tx_p, CLK_SET_RATE_PARENT, 351 RK3568_CLKSEL_CON(11), 10, 2, MFLAGS); 352 353 static struct rockchip_clk_branch rk3568_i2s0_8ch_rx_fracmux __initdata = 354 MUX(CLK_I2S0_8CH_RX, "clk_i2s0_8ch_rx", clk_i2s0_8ch_rx_p, CLK_SET_RATE_PARENT, 355 RK3568_CLKSEL_CON(13), 10, 2, MFLAGS); 356 357 static struct rockchip_clk_branch rk3568_i2s1_8ch_tx_fracmux __initdata = 358 MUX(CLK_I2S1_8CH_TX, "clk_i2s1_8ch_tx", clk_i2s1_8ch_tx_p, CLK_SET_RATE_PARENT, 359 RK3568_CLKSEL_CON(15), 10, 2, MFLAGS); 360 361 static struct rockchip_clk_branch rk3568_i2s1_8ch_rx_fracmux __initdata = 362 MUX(CLK_I2S1_8CH_RX, "clk_i2s1_8ch_rx", clk_i2s1_8ch_rx_p, CLK_SET_RATE_PARENT, 363 RK3568_CLKSEL_CON(17), 10, 2, MFLAGS); 364 365 static struct rockchip_clk_branch rk3568_i2s2_2ch_fracmux __initdata = 366 MUX(CLK_I2S2_2CH, "clk_i2s2_2ch", clk_i2s2_2ch_p, CLK_SET_RATE_PARENT, 367 RK3568_CLKSEL_CON(19), 10, 2, MFLAGS); 368 369 static struct rockchip_clk_branch rk3568_i2s3_2ch_tx_fracmux __initdata = 370 MUX(CLK_I2S3_2CH_TX, "clk_i2s3_2ch_tx", clk_i2s3_2ch_tx_p, CLK_SET_RATE_PARENT, 371 RK3568_CLKSEL_CON(21), 10, 2, MFLAGS); 372 373 static struct rockchip_clk_branch rk3568_i2s3_2ch_rx_fracmux __initdata = 374 MUX(CLK_I2S3_2CH_RX, "clk_i2s3_2ch_rx", clk_i2s3_2ch_rx_p, CLK_SET_RATE_PARENT, 375 RK3568_CLKSEL_CON(83), 10, 2, MFLAGS); 376 377 static struct rockchip_clk_branch rk3568_spdif_8ch_fracmux __initdata = 378 MUX(MCLK_SPDIF_8CH, "mclk_spdif_8ch", mclk_spdif_8ch_p, CLK_SET_RATE_PARENT, 379 RK3568_CLKSEL_CON(23), 15, 1, MFLAGS); 380 381 static struct rockchip_clk_branch rk3568_audpwm_fracmux __initdata = 382 MUX(SCLK_AUDPWM, "sclk_audpwm", sclk_audpwm_p, CLK_SET_RATE_PARENT, 383 RK3568_CLKSEL_CON(25), 15, 1, MFLAGS); 384 385 static struct rockchip_clk_branch rk3568_uart1_fracmux __initdata = 386 MUX(0, "sclk_uart1_mux", sclk_uart1_p, CLK_SET_RATE_PARENT, 387 RK3568_CLKSEL_CON(52), 12, 2, MFLAGS); 388 389 static struct rockchip_clk_branch rk3568_uart2_fracmux __initdata = 390 MUX(0, "sclk_uart2_mux", sclk_uart2_p, CLK_SET_RATE_PARENT, 391 RK3568_CLKSEL_CON(54), 12, 2, MFLAGS); 392 393 static struct rockchip_clk_branch rk3568_uart3_fracmux __initdata = 394 MUX(0, "sclk_uart3_mux", sclk_uart3_p, CLK_SET_RATE_PARENT, 395 RK3568_CLKSEL_CON(56), 12, 2, MFLAGS); 396 397 static struct rockchip_clk_branch rk3568_uart4_fracmux __initdata = 398 MUX(0, "sclk_uart4_mux", sclk_uart4_p, CLK_SET_RATE_PARENT, 399 RK3568_CLKSEL_CON(58), 12, 2, MFLAGS); 400 401 static struct rockchip_clk_branch rk3568_uart5_fracmux __initdata = 402 MUX(0, "sclk_uart5_mux", sclk_uart5_p, CLK_SET_RATE_PARENT, 403 RK3568_CLKSEL_CON(60), 12, 2, MFLAGS); 404 405 static struct rockchip_clk_branch rk3568_uart6_fracmux __initdata = 406 MUX(0, "sclk_uart6_mux", sclk_uart6_p, CLK_SET_RATE_PARENT, 407 RK3568_CLKSEL_CON(62), 12, 2, MFLAGS); 408 409 static struct rockchip_clk_branch rk3568_uart7_fracmux __initdata = 410 MUX(0, "sclk_uart7_mux", sclk_uart7_p, CLK_SET_RATE_PARENT, 411 RK3568_CLKSEL_CON(64), 12, 2, MFLAGS); 412 413 static struct rockchip_clk_branch rk3568_uart8_fracmux __initdata = 414 MUX(0, "sclk_uart8_mux", sclk_uart8_p, CLK_SET_RATE_PARENT, 415 RK3568_CLKSEL_CON(66), 12, 2, MFLAGS); 416 417 static struct rockchip_clk_branch rk3568_uart9_fracmux __initdata = 418 MUX(0, "sclk_uart9_mux", sclk_uart9_p, CLK_SET_RATE_PARENT, 419 RK3568_CLKSEL_CON(68), 12, 2, MFLAGS); 420 421 static struct rockchip_clk_branch rk3568_uart0_fracmux __initdata = 422 MUX(0, "sclk_uart0_mux", sclk_uart0_p, CLK_SET_RATE_PARENT, 423 RK3568_PMU_CLKSEL_CON(4), 10, 2, MFLAGS); 424 425 static struct rockchip_clk_branch rk3568_rtc32k_pmu_fracmux __initdata = 426 MUX(CLK_RTC_32K, "clk_rtc_32k", clk_rtc32k_pmu_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 427 RK3568_PMU_CLKSEL_CON(0), 6, 2, MFLAGS); 428 429 static struct rockchip_clk_branch rk3568_clk_branches[] __initdata = { 430 /* 431 * Clock-Architecture Diagram 1 432 */ 433 /* SRC_CLK */ 434 COMPOSITE_NOMUX(0, "gpll_400m", "gpll", CLK_IGNORE_UNUSED, 435 RK3568_CLKSEL_CON(75), 0, 5, DFLAGS, 436 RK3568_CLKGATE_CON(35), 0, GFLAGS), 437 COMPOSITE_NOMUX(0, "gpll_300m", "gpll", CLK_IGNORE_UNUSED, 438 RK3568_CLKSEL_CON(75), 8, 5, DFLAGS, 439 RK3568_CLKGATE_CON(35), 1, GFLAGS), 440 COMPOSITE_NOMUX(0, "gpll_200m", "gpll", CLK_IGNORE_UNUSED, 441 RK3568_CLKSEL_CON(76), 0, 5, DFLAGS, 442 RK3568_CLKGATE_CON(35), 2, GFLAGS), 443 COMPOSITE_NOMUX(0, "gpll_150m", "gpll", CLK_IGNORE_UNUSED, 444 RK3568_CLKSEL_CON(76), 8, 5, DFLAGS, 445 RK3568_CLKGATE_CON(35), 3, GFLAGS), 446 COMPOSITE_NOMUX(0, "gpll_100m", "gpll", CLK_IGNORE_UNUSED, 447 RK3568_CLKSEL_CON(77), 0, 5, DFLAGS, 448 RK3568_CLKGATE_CON(35), 4, GFLAGS), 449 COMPOSITE_NOMUX(0, "gpll_75m", "gpll", CLK_IGNORE_UNUSED, 450 RK3568_CLKSEL_CON(77), 8, 5, DFLAGS, 451 RK3568_CLKGATE_CON(35), 5, GFLAGS), 452 COMPOSITE_NOMUX(0, "gpll_20m", "gpll", CLK_IGNORE_UNUSED, 453 RK3568_CLKSEL_CON(78), 0, 6, DFLAGS, 454 RK3568_CLKGATE_CON(35), 6, GFLAGS), 455 COMPOSITE_NOMUX(CPLL_500M, "cpll_500m", "cpll", CLK_IGNORE_UNUSED, 456 RK3568_CLKSEL_CON(78), 8, 5, DFLAGS, 457 RK3568_CLKGATE_CON(35), 7, GFLAGS), 458 COMPOSITE_NOMUX(CPLL_333M, "cpll_333m", "cpll", CLK_IGNORE_UNUSED, 459 RK3568_CLKSEL_CON(79), 0, 5, DFLAGS, 460 RK3568_CLKGATE_CON(35), 8, GFLAGS), 461 COMPOSITE_NOMUX(CPLL_250M, "cpll_250m", "cpll", CLK_IGNORE_UNUSED, 462 RK3568_CLKSEL_CON(79), 8, 5, DFLAGS, 463 RK3568_CLKGATE_CON(35), 9, GFLAGS), 464 COMPOSITE_NOMUX(CPLL_125M, "cpll_125m", "cpll", CLK_IGNORE_UNUSED, 465 RK3568_CLKSEL_CON(80), 0, 5, DFLAGS, 466 RK3568_CLKGATE_CON(35), 10, GFLAGS), 467 COMPOSITE_NOMUX(CPLL_100M, "cpll_100m", "cpll", CLK_IGNORE_UNUSED, 468 RK3568_CLKSEL_CON(82), 0, 5, DFLAGS, 469 RK3568_CLKGATE_CON(35), 11, GFLAGS), 470 COMPOSITE_NOMUX(CPLL_62P5M, "cpll_62p5", "cpll", CLK_IGNORE_UNUSED, 471 RK3568_CLKSEL_CON(80), 8, 5, DFLAGS, 472 RK3568_CLKGATE_CON(35), 12, GFLAGS), 473 COMPOSITE_NOMUX(CPLL_50M, "cpll_50m", "cpll", CLK_IGNORE_UNUSED, 474 RK3568_CLKSEL_CON(81), 0, 5, DFLAGS, 475 RK3568_CLKGATE_CON(35), 13, GFLAGS), 476 COMPOSITE_NOMUX(CPLL_25M, "cpll_25m", "cpll", CLK_IGNORE_UNUSED, 477 RK3568_CLKSEL_CON(81), 8, 6, DFLAGS, 478 RK3568_CLKGATE_CON(35), 14, GFLAGS), 479 COMPOSITE_NOMUX(0, "clk_osc0_div_750k", "xin24m", CLK_IGNORE_UNUSED, 480 RK3568_CLKSEL_CON(82), 8, 6, DFLAGS, 481 RK3568_CLKGATE_CON(35), 15, GFLAGS), 482 FACTOR(0, "clk_osc0_div_375k", "clk_osc0_div_750k", 0, 1, 2), 483 FACTOR(0, "xin_osc0_half", "xin24m", 0, 1, 2), 484 MUX(USB480M, "usb480m", mux_usb480m_p, CLK_SET_RATE_PARENT, 485 RK3568_MODE_CON0, 14, 2, MFLAGS), 486 487 /* PD_CORE */ 488 COMPOSITE(0, "sclk_core_src", apll_gpll_npll_p, CLK_IGNORE_UNUSED, 489 RK3568_CLKSEL_CON(2), 8, 2, MFLAGS, 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY, 490 RK3568_CLKGATE_CON(0), 5, GFLAGS), 491 COMPOSITE_NODIV(0, "sclk_core", sclk_core_pre_p, CLK_IGNORE_UNUSED, 492 RK3568_CLKSEL_CON(2), 15, 1, MFLAGS, 493 RK3568_CLKGATE_CON(0), 7, GFLAGS), 494 495 COMPOSITE_NOMUX(0, "atclk_core", "armclk", CLK_IGNORE_UNUSED, 496 RK3568_CLKSEL_CON(3), 0, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, 497 RK3568_CLKGATE_CON(0), 8, GFLAGS), 498 COMPOSITE_NOMUX(0, "gicclk_core", "armclk", CLK_IGNORE_UNUSED, 499 RK3568_CLKSEL_CON(3), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, 500 RK3568_CLKGATE_CON(0), 9, GFLAGS), 501 COMPOSITE_NOMUX(0, "pclk_core_pre", "armclk", CLK_IGNORE_UNUSED, 502 RK3568_CLKSEL_CON(4), 0, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, 503 RK3568_CLKGATE_CON(0), 10, GFLAGS), 504 COMPOSITE_NOMUX(0, "periphclk_core_pre", "armclk", CLK_IGNORE_UNUSED, 505 RK3568_CLKSEL_CON(4), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, 506 RK3568_CLKGATE_CON(0), 11, GFLAGS), 507 COMPOSITE_NOMUX(0, "tsclk_core", "periphclk_core_pre", CLK_IGNORE_UNUSED, 508 RK3568_CLKSEL_CON(5), 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY, 509 RK3568_CLKGATE_CON(0), 14, GFLAGS), 510 COMPOSITE_NOMUX(0, "cntclk_core", "periphclk_core_pre", CLK_IGNORE_UNUSED, 511 RK3568_CLKSEL_CON(5), 4, 4, DFLAGS | CLK_DIVIDER_READ_ONLY, 512 RK3568_CLKGATE_CON(0), 15, GFLAGS), 513 COMPOSITE_NOMUX(0, "aclk_core", "sclk_core", CLK_IGNORE_UNUSED, 514 RK3568_CLKSEL_CON(5), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, 515 RK3568_CLKGATE_CON(1), 0, GFLAGS), 516 517 COMPOSITE_NODIV(ACLK_CORE_NIU2BUS, "aclk_core_niu2bus", gpll150_gpll100_gpll75_xin24m_p, CLK_IGNORE_UNUSED, 518 RK3568_CLKSEL_CON(5), 14, 2, MFLAGS, 519 RK3568_CLKGATE_CON(1), 2, GFLAGS), 520 521 GATE(CLK_CORE_PVTM, "clk_core_pvtm", "xin24m", 0, 522 RK3568_CLKGATE_CON(1), 10, GFLAGS), 523 GATE(CLK_CORE_PVTM_CORE, "clk_core_pvtm_core", "armclk", 0, 524 RK3568_CLKGATE_CON(1), 11, GFLAGS), 525 GATE(CLK_CORE_PVTPLL, "clk_core_pvtpll", "armclk", CLK_IGNORE_UNUSED, 526 RK3568_CLKGATE_CON(1), 12, GFLAGS), 527 GATE(PCLK_CORE_PVTM, "pclk_core_pvtm", "pclk_core_pre", 0, 528 RK3568_CLKGATE_CON(1), 9, GFLAGS), 529 530 /* PD_GPU */ 531 COMPOSITE(CLK_GPU_SRC, "clk_gpu_src", mpll_gpll_cpll_npll_p, 0, 532 RK3568_CLKSEL_CON(6), 6, 2, MFLAGS | CLK_MUX_READ_ONLY, 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY, 533 RK3568_CLKGATE_CON(2), 0, GFLAGS), 534 MUX(CLK_GPU_PRE_MUX, "clk_gpu_pre_mux", clk_gpu_pre_mux_p, CLK_SET_RATE_PARENT, 535 RK3568_CLKSEL_CON(6), 11, 1, MFLAGS | CLK_MUX_READ_ONLY), 536 DIV(ACLK_GPU_PRE, "aclk_gpu_pre", "clk_gpu_pre_mux", 0, 537 RK3568_CLKSEL_CON(6), 8, 2, DFLAGS), 538 DIV(PCLK_GPU_PRE, "pclk_gpu_pre", "clk_gpu_pre_mux", 0, 539 RK3568_CLKSEL_CON(6), 12, 4, DFLAGS), 540 GATE(CLK_GPU, "clk_gpu", "clk_gpu_pre_mux", 0, 541 RK3568_CLKGATE_CON(2), 3, GFLAGS), 542 543 GATE(PCLK_GPU_PVTM, "pclk_gpu_pvtm", "pclk_gpu_pre", 0, 544 RK3568_CLKGATE_CON(2), 6, GFLAGS), 545 GATE(CLK_GPU_PVTM, "clk_gpu_pvtm", "xin24m", 0, 546 RK3568_CLKGATE_CON(2), 7, GFLAGS), 547 GATE(CLK_GPU_PVTM_CORE, "clk_gpu_pvtm_core", "clk_gpu_src", 0, 548 RK3568_CLKGATE_CON(2), 8, GFLAGS), 549 GATE(CLK_GPU_PVTPLL, "clk_gpu_pvtpll", "clk_gpu_src", CLK_IGNORE_UNUSED, 550 RK3568_CLKGATE_CON(2), 9, GFLAGS), 551 552 /* PD_NPU */ 553 COMPOSITE(CLK_NPU_SRC, "clk_npu_src", npll_gpll_p, 0, 554 RK3568_CLKSEL_CON(7), 6, 1, MFLAGS, 0, 4, DFLAGS, 555 RK3568_CLKGATE_CON(3), 0, GFLAGS), 556 MUX(CLK_NPU_PRE_NDFT, "clk_npu_pre_ndft", clk_npu_pre_ndft_p, CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, 557 RK3568_CLKSEL_CON(7), 8, 1, MFLAGS), 558 MUX(CLK_NPU, "clk_npu", clk_npu_p, CLK_SET_RATE_PARENT, 559 RK3568_CLKSEL_CON(7), 15, 1, MFLAGS), 560 COMPOSITE_NOMUX(HCLK_NPU_PRE, "hclk_npu_pre", "clk_npu", 0, 561 RK3568_CLKSEL_CON(8), 0, 4, DFLAGS, 562 RK3568_CLKGATE_CON(3), 2, GFLAGS), 563 COMPOSITE_NOMUX(PCLK_NPU_PRE, "pclk_npu_pre", "clk_npu", 0, 564 RK3568_CLKSEL_CON(8), 4, 4, DFLAGS, 565 RK3568_CLKGATE_CON(3), 3, GFLAGS), 566 GATE(ACLK_NPU_PRE, "aclk_npu_pre", "clk_npu", 0, 567 RK3568_CLKGATE_CON(3), 4, GFLAGS), 568 GATE(ACLK_NPU, "aclk_npu", "aclk_npu_pre", 0, 569 RK3568_CLKGATE_CON(3), 7, GFLAGS), 570 GATE(HCLK_NPU, "hclk_npu", "hclk_npu_pre", 0, 571 RK3568_CLKGATE_CON(3), 8, GFLAGS), 572 573 GATE(PCLK_NPU_PVTM, "pclk_npu_pvtm", "pclk_npu_pre", 0, 574 RK3568_CLKGATE_CON(3), 9, GFLAGS), 575 GATE(CLK_NPU_PVTM, "clk_npu_pvtm", "xin24m", 0, 576 RK3568_CLKGATE_CON(3), 10, GFLAGS), 577 GATE(CLK_NPU_PVTM_CORE, "clk_npu_pvtm_core", "clk_npu_pre_ndft", 0, 578 RK3568_CLKGATE_CON(3), 11, GFLAGS), 579 GATE(CLK_NPU_PVTPLL, "clk_npu_pvtpll", "clk_npu_pre_ndft", CLK_IGNORE_UNUSED, 580 RK3568_CLKGATE_CON(3), 12, GFLAGS), 581 582 /* PD_DDR */ 583 COMPOSITE(CLK_DDRPHY1X_SRC, "clk_ddrphy1x_src", dpll_gpll_cpll_p, CLK_IGNORE_UNUSED, 584 RK3568_CLKSEL_CON(9), 6, 2, MFLAGS, 0, 5, DFLAGS, 585 RK3568_CLKGATE_CON(4), 0, GFLAGS), 586 MUXGRF(CLK_DDR1X, "clk_ddr1x", clk_ddr1x_p, CLK_SET_RATE_PARENT, 587 RK3568_CLKSEL_CON(9), 15, 1, MFLAGS), 588 589 COMPOSITE_NOMUX(CLK_MSCH, "clk_msch", "clk_ddr1x", CLK_IGNORE_UNUSED, 590 RK3568_CLKSEL_CON(10), 0, 2, DFLAGS, 591 RK3568_CLKGATE_CON(4), 2, GFLAGS), 592 GATE(CLK24_DDRMON, "clk24_ddrmon", "xin24m", CLK_IGNORE_UNUSED, 593 RK3568_CLKGATE_CON(4), 15, GFLAGS), 594 595 /* PD_GIC_AUDIO */ 596 COMPOSITE_NODIV(ACLK_GIC_AUDIO, "aclk_gic_audio", gpll200_gpll150_gpll100_xin24m_p, CLK_IGNORE_UNUSED, 597 RK3568_CLKSEL_CON(10), 8, 2, MFLAGS, 598 RK3568_CLKGATE_CON(5), 0, GFLAGS), 599 COMPOSITE_NODIV(HCLK_GIC_AUDIO, "hclk_gic_audio", gpll150_gpll100_gpll75_xin24m_p, CLK_IGNORE_UNUSED, 600 RK3568_CLKSEL_CON(10), 10, 2, MFLAGS, 601 RK3568_CLKGATE_CON(5), 1, GFLAGS), 602 GATE(HCLK_SDMMC_BUFFER, "hclk_sdmmc_buffer", "hclk_gic_audio", 0, 603 RK3568_CLKGATE_CON(5), 8, GFLAGS), 604 COMPOSITE_NODIV(DCLK_SDMMC_BUFFER, "dclk_sdmmc_buffer", gpll100_gpll75_gpll50_p, 0, 605 RK3568_CLKSEL_CON(10), 12, 2, MFLAGS, 606 RK3568_CLKGATE_CON(5), 9, GFLAGS), 607 GATE(ACLK_GIC600, "aclk_gic600", "aclk_gic_audio", CLK_IGNORE_UNUSED, 608 RK3568_CLKGATE_CON(5), 4, GFLAGS), 609 GATE(ACLK_SPINLOCK, "aclk_spinlock", "aclk_gic_audio", CLK_IGNORE_UNUSED, 610 RK3568_CLKGATE_CON(5), 7, GFLAGS), 611 GATE(HCLK_I2S0_8CH, "hclk_i2s0_8ch", "hclk_gic_audio", 0, 612 RK3568_CLKGATE_CON(5), 10, GFLAGS), 613 GATE(HCLK_I2S1_8CH, "hclk_i2s1_8ch", "hclk_gic_audio", 0, 614 RK3568_CLKGATE_CON(5), 11, GFLAGS), 615 GATE(HCLK_I2S2_2CH, "hclk_i2s2_2ch", "hclk_gic_audio", 0, 616 RK3568_CLKGATE_CON(5), 12, GFLAGS), 617 GATE(HCLK_I2S3_2CH, "hclk_i2s3_2ch", "hclk_gic_audio", 0, 618 RK3568_CLKGATE_CON(5), 13, GFLAGS), 619 620 COMPOSITE(CLK_I2S0_8CH_TX_SRC, "clk_i2s0_8ch_tx_src", gpll_cpll_npll_p, 0, 621 RK3568_CLKSEL_CON(11), 8, 2, MFLAGS, 0, 7, DFLAGS, 622 RK3568_CLKGATE_CON(6), 0, GFLAGS), 623 COMPOSITE_FRACMUX(CLK_I2S0_8CH_TX_FRAC, "clk_i2s0_8ch_tx_frac", "clk_i2s0_8ch_tx_src", CLK_SET_RATE_PARENT, 624 RK3568_CLKSEL_CON(12), 0, 625 RK3568_CLKGATE_CON(6), 1, GFLAGS, 626 &rk3568_i2s0_8ch_tx_fracmux), 627 GATE(MCLK_I2S0_8CH_TX, "mclk_i2s0_8ch_tx", "clk_i2s0_8ch_tx", 0, 628 RK3568_CLKGATE_CON(6), 2, GFLAGS), 629 COMPOSITE_NODIV(I2S0_MCLKOUT_TX, "i2s0_mclkout_tx", i2s0_mclkout_tx_p, CLK_SET_RATE_PARENT, 630 RK3568_CLKSEL_CON(11), 15, 1, MFLAGS, 631 RK3568_CLKGATE_CON(6), 3, GFLAGS), 632 633 COMPOSITE(CLK_I2S0_8CH_RX_SRC, "clk_i2s0_8ch_rx_src", gpll_cpll_npll_p, 0, 634 RK3568_CLKSEL_CON(13), 8, 2, MFLAGS, 0, 7, DFLAGS, 635 RK3568_CLKGATE_CON(6), 4, GFLAGS), 636 COMPOSITE_FRACMUX(CLK_I2S0_8CH_RX_FRAC, "clk_i2s0_8ch_rx_frac", "clk_i2s0_8ch_rx_src", CLK_SET_RATE_PARENT, 637 RK3568_CLKSEL_CON(14), 0, 638 RK3568_CLKGATE_CON(6), 5, GFLAGS, 639 &rk3568_i2s0_8ch_rx_fracmux), 640 GATE(MCLK_I2S0_8CH_RX, "mclk_i2s0_8ch_rx", "clk_i2s0_8ch_rx", 0, 641 RK3568_CLKGATE_CON(6), 6, GFLAGS), 642 COMPOSITE_NODIV(I2S0_MCLKOUT_RX, "i2s0_mclkout_rx", i2s0_mclkout_rx_p, CLK_SET_RATE_PARENT, 643 RK3568_CLKSEL_CON(13), 15, 1, MFLAGS, 644 RK3568_CLKGATE_CON(6), 7, GFLAGS), 645 646 COMPOSITE(CLK_I2S1_8CH_TX_SRC, "clk_i2s1_8ch_tx_src", gpll_cpll_npll_p, 0, 647 RK3568_CLKSEL_CON(15), 8, 2, MFLAGS, 0, 7, DFLAGS, 648 RK3568_CLKGATE_CON(6), 8, GFLAGS), 649 COMPOSITE_FRACMUX(CLK_I2S1_8CH_TX_FRAC, "clk_i2s1_8ch_tx_frac", "clk_i2s1_8ch_tx_src", CLK_SET_RATE_PARENT, 650 RK3568_CLKSEL_CON(16), 0, 651 RK3568_CLKGATE_CON(6), 9, GFLAGS, 652 &rk3568_i2s1_8ch_tx_fracmux), 653 GATE(MCLK_I2S1_8CH_TX, "mclk_i2s1_8ch_tx", "clk_i2s1_8ch_tx", 0, 654 RK3568_CLKGATE_CON(6), 10, GFLAGS), 655 COMPOSITE_NODIV(I2S1_MCLKOUT_TX, "i2s1_mclkout_tx", i2s1_mclkout_tx_p, CLK_SET_RATE_PARENT, 656 RK3568_CLKSEL_CON(15), 15, 1, MFLAGS, 657 RK3568_CLKGATE_CON(6), 11, GFLAGS), 658 659 COMPOSITE(CLK_I2S1_8CH_RX_SRC, "clk_i2s1_8ch_rx_src", gpll_cpll_npll_p, 0, 660 RK3568_CLKSEL_CON(17), 8, 2, MFLAGS, 0, 7, DFLAGS, 661 RK3568_CLKGATE_CON(6), 12, GFLAGS), 662 COMPOSITE_FRACMUX(CLK_I2S1_8CH_RX_FRAC, "clk_i2s1_8ch_rx_frac", "clk_i2s1_8ch_rx_src", CLK_SET_RATE_PARENT, 663 RK3568_CLKSEL_CON(18), 0, 664 RK3568_CLKGATE_CON(6), 13, GFLAGS, 665 &rk3568_i2s1_8ch_rx_fracmux), 666 GATE(MCLK_I2S1_8CH_RX, "mclk_i2s1_8ch_rx", "clk_i2s1_8ch_rx", 0, 667 RK3568_CLKGATE_CON(6), 14, GFLAGS), 668 COMPOSITE_NODIV(I2S1_MCLKOUT_RX, "i2s1_mclkout_rx", i2s1_mclkout_rx_p, CLK_SET_RATE_PARENT, 669 RK3568_CLKSEL_CON(17), 15, 1, MFLAGS, 670 RK3568_CLKGATE_CON(6), 15, GFLAGS), 671 672 COMPOSITE(CLK_I2S2_2CH_SRC, "clk_i2s2_2ch_src", gpll_cpll_npll_p, 0, 673 RK3568_CLKSEL_CON(19), 8, 2, MFLAGS, 0, 7, DFLAGS, 674 RK3568_CLKGATE_CON(7), 0, GFLAGS), 675 COMPOSITE_FRACMUX(CLK_I2S2_2CH_FRAC, "clk_i2s2_2ch_frac", "clk_i2s2_2ch_src", CLK_SET_RATE_PARENT, 676 RK3568_CLKSEL_CON(20), 0, 677 RK3568_CLKGATE_CON(7), 1, GFLAGS, 678 &rk3568_i2s2_2ch_fracmux), 679 GATE(MCLK_I2S2_2CH, "mclk_i2s2_2ch", "clk_i2s2_2ch", 0, 680 RK3568_CLKGATE_CON(7), 2, GFLAGS), 681 COMPOSITE_NODIV(I2S2_MCLKOUT, "i2s2_mclkout", i2s2_mclkout_p, CLK_SET_RATE_PARENT, 682 RK3568_CLKSEL_CON(19), 15, 1, MFLAGS, 683 RK3568_CLKGATE_CON(7), 3, GFLAGS), 684 685 COMPOSITE(CLK_I2S3_2CH_TX_SRC, "clk_i2s3_2ch_tx_src", gpll_cpll_npll_p, 0, 686 RK3568_CLKSEL_CON(21), 8, 2, MFLAGS, 0, 7, DFLAGS, 687 RK3568_CLKGATE_CON(7), 4, GFLAGS), 688 COMPOSITE_FRACMUX(CLK_I2S3_2CH_TX_FRAC, "clk_i2s3_2ch_tx_frac", "clk_i2s3_2ch_tx_src", CLK_SET_RATE_PARENT, 689 RK3568_CLKSEL_CON(22), 0, 690 RK3568_CLKGATE_CON(7), 5, GFLAGS, 691 &rk3568_i2s3_2ch_tx_fracmux), 692 GATE(MCLK_I2S3_2CH_TX, "mclk_i2s3_2ch_tx", "clk_i2s3_2ch_tx", 0, 693 RK3568_CLKGATE_CON(7), 6, GFLAGS), 694 COMPOSITE_NODIV(I2S3_MCLKOUT_TX, "i2s3_mclkout_tx", i2s3_mclkout_tx_p, CLK_SET_RATE_PARENT, 695 RK3568_CLKSEL_CON(21), 15, 1, MFLAGS, 696 RK3568_CLKGATE_CON(7), 7, GFLAGS), 697 698 COMPOSITE(CLK_I2S3_2CH_RX_SRC, "clk_i2s3_2ch_rx_src", gpll_cpll_npll_p, 0, 699 RK3568_CLKSEL_CON(83), 8, 2, MFLAGS, 0, 7, DFLAGS, 700 RK3568_CLKGATE_CON(7), 8, GFLAGS), 701 COMPOSITE_FRACMUX(CLK_I2S3_2CH_RX_FRAC, "clk_i2s3_2ch_rx_frac", "clk_i2s3_2ch_rx_src", CLK_SET_RATE_PARENT, 702 RK3568_CLKSEL_CON(84), 0, 703 RK3568_CLKGATE_CON(7), 9, GFLAGS, 704 &rk3568_i2s3_2ch_rx_fracmux), 705 GATE(MCLK_I2S3_2CH_RX, "mclk_i2s3_2ch_rx", "clk_i2s3_2ch_rx", 0, 706 RK3568_CLKGATE_CON(7), 10, GFLAGS), 707 COMPOSITE_NODIV(I2S3_MCLKOUT_RX, "i2s3_mclkout_rx", i2s3_mclkout_rx_p, CLK_SET_RATE_PARENT, 708 RK3568_CLKSEL_CON(83), 15, 1, MFLAGS, 709 RK3568_CLKGATE_CON(7), 11, GFLAGS), 710 711 GATE(HCLK_PDM, "hclk_pdm", "hclk_gic_audio", 0, 712 RK3568_CLKGATE_CON(5), 14, GFLAGS), 713 COMPOSITE_NODIV(MCLK_PDM, "mclk_pdm", mclk_pdm_p, 0, 714 RK3568_CLKSEL_CON(23), 8, 2, MFLAGS, 715 RK3568_CLKGATE_CON(5), 15, GFLAGS), 716 GATE(HCLK_VAD, "hclk_vad", "hclk_gic_audio", 0, 717 RK3568_CLKGATE_CON(7), 12, GFLAGS), 718 GATE(HCLK_SPDIF_8CH, "hclk_spdif_8ch", "hclk_gic_audio", 0, 719 RK3568_CLKGATE_CON(7), 13, GFLAGS), 720 721 COMPOSITE(MCLK_SPDIF_8CH_SRC, "mclk_spdif_8ch_src", cpll_gpll_p, 0, 722 RK3568_CLKSEL_CON(23), 14, 1, MFLAGS, 0, 7, DFLAGS, 723 RK3568_CLKGATE_CON(7), 14, GFLAGS), 724 COMPOSITE_FRACMUX(MCLK_SPDIF_8CH_FRAC, "mclk_spdif_8ch_frac", "mclk_spdif_8ch_src", CLK_SET_RATE_PARENT, 725 RK3568_CLKSEL_CON(24), 0, 726 RK3568_CLKGATE_CON(7), 15, GFLAGS, 727 &rk3568_spdif_8ch_fracmux), 728 729 GATE(HCLK_AUDPWM, "hclk_audpwm", "hclk_gic_audio", 0, 730 RK3568_CLKGATE_CON(8), 0, GFLAGS), 731 COMPOSITE(SCLK_AUDPWM_SRC, "sclk_audpwm_src", gpll_cpll_p, 0, 732 RK3568_CLKSEL_CON(25), 14, 1, MFLAGS, 0, 6, DFLAGS, 733 RK3568_CLKGATE_CON(8), 1, GFLAGS), 734 COMPOSITE_FRACMUX(SCLK_AUDPWM_FRAC, "sclk_audpwm_frac", "sclk_audpwm_src", CLK_SET_RATE_PARENT, 735 RK3568_CLKSEL_CON(26), 0, 736 RK3568_CLKGATE_CON(8), 2, GFLAGS, 737 &rk3568_audpwm_fracmux), 738 739 GATE(HCLK_ACDCDIG, "hclk_acdcdig", "hclk_gic_audio", 0, 740 RK3568_CLKGATE_CON(8), 3, GFLAGS), 741 COMPOSITE_NODIV(CLK_ACDCDIG_I2C, "clk_acdcdig_i2c", clk_i2c_p, 0, 742 RK3568_CLKSEL_CON(23), 10, 2, MFLAGS, 743 RK3568_CLKGATE_CON(8), 4, GFLAGS), 744 GATE(CLK_ACDCDIG_DAC, "clk_acdcdig_dac", "mclk_i2s3_2ch_tx", 0, 745 RK3568_CLKGATE_CON(8), 5, GFLAGS), 746 GATE(CLK_ACDCDIG_ADC, "clk_acdcdig_adc", "mclk_i2s3_2ch_rx", 0, 747 RK3568_CLKGATE_CON(8), 6, GFLAGS), 748 749 /* PD_SECURE_FLASH */ 750 COMPOSITE_NODIV(ACLK_SECURE_FLASH, "aclk_secure_flash", gpll200_gpll150_gpll100_xin24m_p, 0, 751 RK3568_CLKSEL_CON(27), 0, 2, MFLAGS, 752 RK3568_CLKGATE_CON(8), 7, GFLAGS), 753 COMPOSITE_NODIV(HCLK_SECURE_FLASH, "hclk_secure_flash", gpll150_gpll100_gpll75_xin24m_p, 0, 754 RK3568_CLKSEL_CON(27), 2, 2, MFLAGS, 755 RK3568_CLKGATE_CON(8), 8, GFLAGS), 756 GATE(ACLK_CRYPTO_NS, "aclk_crypto_ns", "aclk_secure_flash", 0, 757 RK3568_CLKGATE_CON(8), 11, GFLAGS), 758 GATE(HCLK_CRYPTO_NS, "hclk_crypto_ns", "hclk_secure_flash", 0, 759 RK3568_CLKGATE_CON(8), 12, GFLAGS), 760 COMPOSITE_NODIV(CLK_CRYPTO_NS_CORE, "clk_crypto_ns_core", gpll200_gpll150_gpll100_p, 0, 761 RK3568_CLKSEL_CON(27), 4, 2, MFLAGS, 762 RK3568_CLKGATE_CON(8), 13, GFLAGS), 763 COMPOSITE_NODIV(CLK_CRYPTO_NS_PKA, "clk_crypto_ns_pka", gpll300_gpll200_gpll100_p, 0, 764 RK3568_CLKSEL_CON(27), 6, 2, MFLAGS, 765 RK3568_CLKGATE_CON(8), 14, GFLAGS), 766 GATE(CLK_CRYPTO_NS_RNG, "clk_crypto_ns_rng", "hclk_secure_flash", 0, 767 RK3568_CLKGATE_CON(8), 15, GFLAGS), 768 GATE(HCLK_TRNG_NS, "hclk_trng_ns", "hclk_secure_flash", CLK_IGNORE_UNUSED, 769 RK3568_CLKGATE_CON(9), 10, GFLAGS), 770 GATE(CLK_TRNG_NS, "clk_trng_ns", "hclk_secure_flash", CLK_IGNORE_UNUSED, 771 RK3568_CLKGATE_CON(9), 11, GFLAGS), 772 GATE(PCLK_OTPC_NS, "pclk_otpc_ns", "hclk_secure_flash", 0, 773 RK3568_CLKGATE_CON(26), 9, GFLAGS), 774 GATE(CLK_OTPC_NS_SBPI, "clk_otpc_ns_sbpi", "xin24m", 0, 775 RK3568_CLKGATE_CON(26), 10, GFLAGS), 776 GATE(CLK_OTPC_NS_USR, "clk_otpc_ns_usr", "xin_osc0_half", 0, 777 RK3568_CLKGATE_CON(26), 11, GFLAGS), 778 GATE(HCLK_NANDC, "hclk_nandc", "hclk_secure_flash", 0, 779 RK3568_CLKGATE_CON(9), 0, GFLAGS), 780 COMPOSITE_NODIV(NCLK_NANDC, "nclk_nandc", clk_nandc_p, 0, 781 RK3568_CLKSEL_CON(28), 0, 2, MFLAGS, 782 RK3568_CLKGATE_CON(9), 1, GFLAGS), 783 GATE(HCLK_SFC, "hclk_sfc", "hclk_secure_flash", 0, 784 RK3568_CLKGATE_CON(9), 2, GFLAGS), 785 GATE(HCLK_SFC_XIP, "hclk_sfc_xip", "hclk_secure_flash", 0, 786 RK3568_CLKGATE_CON(9), 3, GFLAGS), 787 COMPOSITE_NODIV(SCLK_SFC, "sclk_sfc", sclk_sfc_p, 0, 788 RK3568_CLKSEL_CON(28), 4, 3, MFLAGS, 789 RK3568_CLKGATE_CON(9), 4, GFLAGS), 790 GATE(ACLK_EMMC, "aclk_emmc", "aclk_secure_flash", 0, 791 RK3568_CLKGATE_CON(9), 5, GFLAGS), 792 GATE(HCLK_EMMC, "hclk_emmc", "hclk_secure_flash", 0, 793 RK3568_CLKGATE_CON(9), 6, GFLAGS), 794 COMPOSITE_NODIV(BCLK_EMMC, "bclk_emmc", gpll200_gpll150_cpll125_p, 0, 795 RK3568_CLKSEL_CON(28), 8, 2, MFLAGS, 796 RK3568_CLKGATE_CON(9), 7, GFLAGS), 797 COMPOSITE_NODIV(CCLK_EMMC, "cclk_emmc", cclk_emmc_p, 0, 798 RK3568_CLKSEL_CON(28), 12, 3, MFLAGS, 799 RK3568_CLKGATE_CON(9), 8, GFLAGS), 800 GATE(TCLK_EMMC, "tclk_emmc", "xin24m", 0, 801 RK3568_CLKGATE_CON(9), 9, GFLAGS), 802 MMC(SCLK_EMMC_DRV, "emmc_drv", "cclk_emmc", RK3568_EMMC_CON0, 1), 803 MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "cclk_emmc", RK3568_EMMC_CON1, 1), 804 805 /* PD_PIPE */ 806 COMPOSITE_NODIV(ACLK_PIPE, "aclk_pipe", aclk_pipe_p, 0, 807 RK3568_CLKSEL_CON(29), 0, 2, MFLAGS, 808 RK3568_CLKGATE_CON(10), 0, GFLAGS), 809 COMPOSITE_NOMUX(PCLK_PIPE, "pclk_pipe", "aclk_pipe", 0, 810 RK3568_CLKSEL_CON(29), 4, 4, DFLAGS, 811 RK3568_CLKGATE_CON(10), 1, GFLAGS), 812 GATE(ACLK_PCIE20_MST, "aclk_pcie20_mst", "aclk_pipe", 0, 813 RK3568_CLKGATE_CON(12), 0, GFLAGS), 814 GATE(ACLK_PCIE20_SLV, "aclk_pcie20_slv", "aclk_pipe", 0, 815 RK3568_CLKGATE_CON(12), 1, GFLAGS), 816 GATE(ACLK_PCIE20_DBI, "aclk_pcie20_dbi", "aclk_pipe", 0, 817 RK3568_CLKGATE_CON(12), 2, GFLAGS), 818 GATE(PCLK_PCIE20, "pclk_pcie20", "pclk_pipe", 0, 819 RK3568_CLKGATE_CON(12), 3, GFLAGS), 820 GATE(CLK_PCIE20_AUX_NDFT, "clk_pcie20_aux_ndft", "xin24m", 0, 821 RK3568_CLKGATE_CON(12), 4, GFLAGS), 822 GATE(ACLK_PCIE30X1_MST, "aclk_pcie30x1_mst", "aclk_pipe", 0, 823 RK3568_CLKGATE_CON(12), 8, GFLAGS), 824 GATE(ACLK_PCIE30X1_SLV, "aclk_pcie30x1_slv", "aclk_pipe", 0, 825 RK3568_CLKGATE_CON(12), 9, GFLAGS), 826 GATE(ACLK_PCIE30X1_DBI, "aclk_pcie30x1_dbi", "aclk_pipe", 0, 827 RK3568_CLKGATE_CON(12), 10, GFLAGS), 828 GATE(PCLK_PCIE30X1, "pclk_pcie30x1", "pclk_pipe", 0, 829 RK3568_CLKGATE_CON(12), 11, GFLAGS), 830 GATE(CLK_PCIE30X1_AUX_NDFT, "clk_pcie30x1_aux_ndft", "xin24m", 0, 831 RK3568_CLKGATE_CON(12), 12, GFLAGS), 832 GATE(ACLK_PCIE30X2_MST, "aclk_pcie30x2_mst", "aclk_pipe", 0, 833 RK3568_CLKGATE_CON(13), 0, GFLAGS), 834 GATE(ACLK_PCIE30X2_SLV, "aclk_pcie30x2_slv", "aclk_pipe", 0, 835 RK3568_CLKGATE_CON(13), 1, GFLAGS), 836 GATE(ACLK_PCIE30X2_DBI, "aclk_pcie30x2_dbi", "aclk_pipe", 0, 837 RK3568_CLKGATE_CON(13), 2, GFLAGS), 838 GATE(PCLK_PCIE30X2, "pclk_pcie30x2", "pclk_pipe", 0, 839 RK3568_CLKGATE_CON(13), 3, GFLAGS), 840 GATE(CLK_PCIE30X2_AUX_NDFT, "clk_pcie30x2_aux_ndft", "xin24m", 0, 841 RK3568_CLKGATE_CON(13), 4, GFLAGS), 842 GATE(ACLK_SATA0, "aclk_sata0", "aclk_pipe", 0, 843 RK3568_CLKGATE_CON(11), 0, GFLAGS), 844 GATE(CLK_SATA0_PMALIVE, "clk_sata0_pmalive", "gpll_20m", 0, 845 RK3568_CLKGATE_CON(11), 1, GFLAGS), 846 GATE(CLK_SATA0_RXOOB, "clk_sata0_rxoob", "cpll_50m", 0, 847 RK3568_CLKGATE_CON(11), 2, GFLAGS), 848 GATE(ACLK_SATA1, "aclk_sata1", "aclk_pipe", 0, 849 RK3568_CLKGATE_CON(11), 4, GFLAGS), 850 GATE(CLK_SATA1_PMALIVE, "clk_sata1_pmalive", "gpll_20m", 0, 851 RK3568_CLKGATE_CON(11), 5, GFLAGS), 852 GATE(CLK_SATA1_RXOOB, "clk_sata1_rxoob", "cpll_50m", 0, 853 RK3568_CLKGATE_CON(11), 6, GFLAGS), 854 GATE(ACLK_SATA2, "aclk_sata2", "aclk_pipe", 0, 855 RK3568_CLKGATE_CON(11), 8, GFLAGS), 856 GATE(CLK_SATA2_PMALIVE, "clk_sata2_pmalive", "gpll_20m", 0, 857 RK3568_CLKGATE_CON(11), 9, GFLAGS), 858 GATE(CLK_SATA2_RXOOB, "clk_sata2_rxoob", "cpll_50m", 0, 859 RK3568_CLKGATE_CON(11), 10, GFLAGS), 860 GATE(ACLK_USB3OTG0, "aclk_usb3otg0", "aclk_pipe", 0, 861 RK3568_CLKGATE_CON(10), 8, GFLAGS), 862 GATE(CLK_USB3OTG0_REF, "clk_usb3otg0_ref", "xin24m", 0, 863 RK3568_CLKGATE_CON(10), 9, GFLAGS), 864 COMPOSITE_NODIV(CLK_USB3OTG0_SUSPEND, "clk_usb3otg0_suspend", xin24m_32k_p, 0, 865 RK3568_CLKSEL_CON(29), 8, 1, MFLAGS, 866 RK3568_CLKGATE_CON(10), 10, GFLAGS), 867 GATE(ACLK_USB3OTG1, "aclk_usb3otg1", "aclk_pipe", 0, 868 RK3568_CLKGATE_CON(10), 12, GFLAGS), 869 GATE(CLK_USB3OTG1_REF, "clk_usb3otg1_ref", "xin24m", 0, 870 RK3568_CLKGATE_CON(10), 13, GFLAGS), 871 COMPOSITE_NODIV(CLK_USB3OTG1_SUSPEND, "clk_usb3otg1_suspend", xin24m_32k_p, 0, 872 RK3568_CLKSEL_CON(29), 9, 1, MFLAGS, 873 RK3568_CLKGATE_CON(10), 14, GFLAGS), 874 COMPOSITE_NODIV(CLK_XPCS_EEE, "clk_xpcs_eee", gpll200_cpll125_p, 0, 875 RK3568_CLKSEL_CON(29), 13, 1, MFLAGS, 876 RK3568_CLKGATE_CON(10), 4, GFLAGS), 877 GATE(PCLK_XPCS, "pclk_xpcs", "pclk_pipe", 0, 878 RK3568_CLKGATE_CON(13), 6, GFLAGS), 879 880 /* PD_PHP */ 881 COMPOSITE_NODIV(ACLK_PHP, "aclk_php", gpll300_gpll200_gpll100_xin24m_p, 0, 882 RK3568_CLKSEL_CON(30), 0, 2, MFLAGS, 883 RK3568_CLKGATE_CON(14), 8, GFLAGS), 884 COMPOSITE_NODIV(HCLK_PHP, "hclk_php", gpll150_gpll100_gpll75_xin24m_p, 0, 885 RK3568_CLKSEL_CON(30), 2, 2, MFLAGS, 886 RK3568_CLKGATE_CON(14), 9, GFLAGS), 887 COMPOSITE_NOMUX(PCLK_PHP, "pclk_php", "aclk_php", 0, 888 RK3568_CLKSEL_CON(30), 4, 4, DFLAGS, 889 RK3568_CLKGATE_CON(14), 10, GFLAGS), 890 GATE(HCLK_SDMMC0, "hclk_sdmmc0", "hclk_php", 0, 891 RK3568_CLKGATE_CON(15), 0, GFLAGS), 892 COMPOSITE_NODIV(CLK_SDMMC0, "clk_sdmmc0", clk_sdmmc_p, 0, 893 RK3568_CLKSEL_CON(30), 8, 3, MFLAGS, 894 RK3568_CLKGATE_CON(15), 1, GFLAGS), 895 MMC(SCLK_SDMMC0_DRV, "sdmmc0_drv", "clk_sdmmc0", RK3568_SDMMC0_CON0, 1), 896 MMC(SCLK_SDMMC0_SAMPLE, "sdmmc0_sample", "clk_sdmmc0", RK3568_SDMMC0_CON1, 1), 897 898 GATE(HCLK_SDMMC1, "hclk_sdmmc1", "hclk_php", 0, 899 RK3568_CLKGATE_CON(15), 2, GFLAGS), 900 COMPOSITE_NODIV(CLK_SDMMC1, "clk_sdmmc1", clk_sdmmc_p, 0, 901 RK3568_CLKSEL_CON(30), 12, 3, MFLAGS, 902 RK3568_CLKGATE_CON(15), 3, GFLAGS), 903 MMC(SCLK_SDMMC1_DRV, "sdmmc1_drv", "clk_sdmmc1", RK3568_SDMMC1_CON0, 1), 904 MMC(SCLK_SDMMC1_SAMPLE, "sdmmc1_sample", "clk_sdmmc1", RK3568_SDMMC1_CON1, 1), 905 906 GATE(ACLK_GMAC0, "aclk_gmac0", "aclk_php", 0, 907 RK3568_CLKGATE_CON(15), 5, GFLAGS), 908 GATE(PCLK_GMAC0, "pclk_gmac0", "pclk_php", 0, 909 RK3568_CLKGATE_CON(15), 6, GFLAGS), 910 COMPOSITE_NODIV(CLK_MAC0_2TOP, "clk_mac0_2top", clk_mac_2top_p, 0, 911 RK3568_CLKSEL_CON(31), 8, 2, MFLAGS, 912 RK3568_CLKGATE_CON(15), 7, GFLAGS), 913 COMPOSITE_NODIV(CLK_MAC0_OUT, "clk_mac0_out", cpll125_cpll50_cpll25_xin24m_p, 0, 914 RK3568_CLKSEL_CON(31), 14, 2, MFLAGS, 915 RK3568_CLKGATE_CON(15), 8, GFLAGS), 916 GATE(CLK_MAC0_REFOUT, "clk_mac0_refout", "clk_mac0_2top", 0, 917 RK3568_CLKGATE_CON(15), 12, GFLAGS), 918 COMPOSITE_NODIV(CLK_GMAC0_PTP_REF, "clk_gmac0_ptp_ref", clk_gmac_ptp_p, 0, 919 RK3568_CLKSEL_CON(31), 12, 2, MFLAGS, 920 RK3568_CLKGATE_CON(15), 4, GFLAGS), 921 MUX(SCLK_GMAC0, "clk_gmac0", mux_gmac0_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 922 RK3568_CLKSEL_CON(31), 2, 1, MFLAGS), 923 FACTOR(0, "clk_gmac0_tx_div5", "clk_gmac0", 0, 1, 5), 924 FACTOR(0, "clk_gmac0_tx_div50", "clk_gmac0", 0, 1, 50), 925 FACTOR(0, "clk_gmac0_rx_div2", "clk_gmac0", 0, 1, 2), 926 FACTOR(0, "clk_gmac0_rx_div20", "clk_gmac0", 0, 1, 20), 927 MUX(SCLK_GMAC0_RGMII_SPEED, "clk_gmac0_rgmii_speed", mux_gmac0_rgmii_speed_p, 0, 928 RK3568_CLKSEL_CON(31), 4, 2, MFLAGS), 929 MUX(SCLK_GMAC0_RMII_SPEED, "clk_gmac0_rmii_speed", mux_gmac0_rmii_speed_p, 0, 930 RK3568_CLKSEL_CON(31), 3, 1, MFLAGS), 931 MUX(SCLK_GMAC0_RX_TX, "clk_gmac0_rx_tx", mux_gmac0_rx_tx_p, CLK_SET_RATE_PARENT, 932 RK3568_CLKSEL_CON(31), 0, 2, MFLAGS), 933 934 /* PD_USB */ 935 COMPOSITE_NODIV(ACLK_USB, "aclk_usb", gpll300_gpll200_gpll100_xin24m_p, 0, 936 RK3568_CLKSEL_CON(32), 0, 2, MFLAGS, 937 RK3568_CLKGATE_CON(16), 0, GFLAGS), 938 COMPOSITE_NODIV(HCLK_USB, "hclk_usb", gpll150_gpll100_gpll75_xin24m_p, 0, 939 RK3568_CLKSEL_CON(32), 2, 2, MFLAGS, 940 RK3568_CLKGATE_CON(16), 1, GFLAGS), 941 COMPOSITE_NOMUX(PCLK_USB, "pclk_usb", "aclk_usb", 0, 942 RK3568_CLKSEL_CON(32), 4, 4, DFLAGS, 943 RK3568_CLKGATE_CON(16), 2, GFLAGS), 944 GATE(HCLK_USB2HOST0, "hclk_usb2host0", "hclk_usb", 0, 945 RK3568_CLKGATE_CON(16), 12, GFLAGS), 946 GATE(HCLK_USB2HOST0_ARB, "hclk_usb2host0_arb", "hclk_usb", 0, 947 RK3568_CLKGATE_CON(16), 13, GFLAGS), 948 GATE(HCLK_USB2HOST1, "hclk_usb2host1", "hclk_usb", 0, 949 RK3568_CLKGATE_CON(16), 14, GFLAGS), 950 GATE(HCLK_USB2HOST1_ARB, "hclk_usb2host1_arb", "hclk_usb", 0, 951 RK3568_CLKGATE_CON(16), 15, GFLAGS), 952 GATE(HCLK_SDMMC2, "hclk_sdmmc2", "hclk_usb", 0, 953 RK3568_CLKGATE_CON(17), 0, GFLAGS), 954 COMPOSITE_NODIV(CLK_SDMMC2, "clk_sdmmc2", clk_sdmmc_p, 0, 955 RK3568_CLKSEL_CON(32), 8, 3, MFLAGS, 956 RK3568_CLKGATE_CON(17), 1, GFLAGS), 957 MMC(SCLK_SDMMC2_DRV, "sdmmc2_drv", "clk_sdmmc2", RK3568_SDMMC2_CON0, 1), 958 MMC(SCLK_SDMMC2_SAMPLE, "sdmmc2_sample", "clk_sdmmc2", RK3568_SDMMC2_CON1, 1), 959 960 GATE(ACLK_GMAC1, "aclk_gmac1", "aclk_usb", 0, 961 RK3568_CLKGATE_CON(17), 3, GFLAGS), 962 GATE(PCLK_GMAC1, "pclk_gmac1", "pclk_usb", 0, 963 RK3568_CLKGATE_CON(17), 4, GFLAGS), 964 COMPOSITE_NODIV(CLK_MAC1_2TOP, "clk_mac1_2top", clk_mac_2top_p, 0, 965 RK3568_CLKSEL_CON(33), 8, 2, MFLAGS, 966 RK3568_CLKGATE_CON(17), 5, GFLAGS), 967 COMPOSITE_NODIV(CLK_MAC1_OUT, "clk_mac1_out", cpll125_cpll50_cpll25_xin24m_p, 0, 968 RK3568_CLKSEL_CON(33), 14, 2, MFLAGS, 969 RK3568_CLKGATE_CON(17), 6, GFLAGS), 970 GATE(CLK_MAC1_REFOUT, "clk_mac1_refout", "clk_mac1_2top", 0, 971 RK3568_CLKGATE_CON(17), 10, GFLAGS), 972 COMPOSITE_NODIV(CLK_GMAC1_PTP_REF, "clk_gmac1_ptp_ref", clk_gmac_ptp_p, 0, 973 RK3568_CLKSEL_CON(33), 12, 2, MFLAGS, 974 RK3568_CLKGATE_CON(17), 2, GFLAGS), 975 MUX(SCLK_GMAC1, "clk_gmac1", mux_gmac1_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 976 RK3568_CLKSEL_CON(33), 2, 1, MFLAGS), 977 FACTOR(0, "clk_gmac1_tx_div5", "clk_gmac1", 0, 1, 5), 978 FACTOR(0, "clk_gmac1_tx_div50", "clk_gmac1", 0, 1, 50), 979 FACTOR(0, "clk_gmac1_rx_div2", "clk_gmac1", 0, 1, 2), 980 FACTOR(0, "clk_gmac1_rx_div20", "clk_gmac1", 0, 1, 20), 981 MUX(SCLK_GMAC1_RGMII_SPEED, "clk_gmac1_rgmii_speed", mux_gmac1_rgmii_speed_p, 0, 982 RK3568_CLKSEL_CON(33), 4, 2, MFLAGS), 983 MUX(SCLK_GMAC1_RMII_SPEED, "clk_gmac1_rmii_speed", mux_gmac1_rmii_speed_p, 0, 984 RK3568_CLKSEL_CON(33), 3, 1, MFLAGS), 985 MUX(SCLK_GMAC1_RX_TX, "clk_gmac1_rx_tx", mux_gmac1_rx_tx_p, CLK_SET_RATE_PARENT, 986 RK3568_CLKSEL_CON(33), 0, 2, MFLAGS), 987 988 /* PD_PERI */ 989 COMPOSITE_NODIV(ACLK_PERIMID, "aclk_perimid", gpll300_gpll200_gpll100_xin24m_p, CLK_IGNORE_UNUSED, 990 RK3568_CLKSEL_CON(10), 4, 2, MFLAGS, 991 RK3568_CLKGATE_CON(14), 0, GFLAGS), 992 COMPOSITE_NODIV(HCLK_PERIMID, "hclk_perimid", gpll150_gpll100_gpll75_xin24m_p, CLK_IGNORE_UNUSED, 993 RK3568_CLKSEL_CON(10), 6, 2, MFLAGS, 994 RK3568_CLKGATE_CON(14), 1, GFLAGS), 995 996 /* PD_VI */ 997 COMPOSITE_NODIV(ACLK_VI, "aclk_vi", gpll400_gpll300_gpll200_xin24m_p, 0, 998 RK3568_CLKSEL_CON(34), 0, 2, MFLAGS, 999 RK3568_CLKGATE_CON(18), 0, GFLAGS), 1000 COMPOSITE_NOMUX(HCLK_VI, "hclk_vi", "aclk_vi", 0, 1001 RK3568_CLKSEL_CON(34), 4, 4, DFLAGS, 1002 RK3568_CLKGATE_CON(18), 1, GFLAGS), 1003 COMPOSITE_NOMUX(PCLK_VI, "pclk_vi", "aclk_vi", 0, 1004 RK3568_CLKSEL_CON(34), 8, 4, DFLAGS, 1005 RK3568_CLKGATE_CON(18), 2, GFLAGS), 1006 GATE(ACLK_VICAP, "aclk_vicap", "aclk_vi", 0, 1007 RK3568_CLKGATE_CON(18), 9, GFLAGS), 1008 GATE(HCLK_VICAP, "hclk_vicap", "hclk_vi", 0, 1009 RK3568_CLKGATE_CON(18), 10, GFLAGS), 1010 COMPOSITE_NODIV(DCLK_VICAP, "dclk_vicap", cpll333_gpll300_gpll200_p, 0, 1011 RK3568_CLKSEL_CON(34), 14, 2, MFLAGS, 1012 RK3568_CLKGATE_CON(18), 11, GFLAGS), 1013 GATE(ICLK_VICAP_G, "iclk_vicap_g", "iclk_vicap", 0, 1014 RK3568_CLKGATE_CON(18), 13, GFLAGS), 1015 GATE(ACLK_ISP, "aclk_isp", "aclk_vi", 0, 1016 RK3568_CLKGATE_CON(19), 0, GFLAGS), 1017 GATE(HCLK_ISP, "hclk_isp", "hclk_vi", 0, 1018 RK3568_CLKGATE_CON(19), 1, GFLAGS), 1019 COMPOSITE(CLK_ISP, "clk_isp", cpll_gpll_hpll_p, 0, 1020 RK3568_CLKSEL_CON(35), 6, 2, MFLAGS, 0, 5, DFLAGS, 1021 RK3568_CLKGATE_CON(19), 2, GFLAGS), 1022 GATE(PCLK_CSI2HOST1, "pclk_csi2host1", "pclk_vi", 0, 1023 RK3568_CLKGATE_CON(19), 4, GFLAGS), 1024 COMPOSITE(CLK_CIF_OUT, "clk_cif_out", gpll_usb480m_xin24m_p, 0, 1025 RK3568_CLKSEL_CON(35), 14, 2, MFLAGS, 8, 6, DFLAGS, 1026 RK3568_CLKGATE_CON(19), 8, GFLAGS), 1027 COMPOSITE(CLK_CAM0_OUT, "clk_cam0_out", gpll_usb480m_xin24m_p, 0, 1028 RK3568_CLKSEL_CON(36), 6, 2, MFLAGS, 0, 6, DFLAGS, 1029 RK3568_CLKGATE_CON(19), 9, GFLAGS), 1030 COMPOSITE(CLK_CAM1_OUT, "clk_cam1_out", gpll_usb480m_xin24m_p, 0, 1031 RK3568_CLKSEL_CON(36), 14, 2, MFLAGS, 8, 6, DFLAGS, 1032 RK3568_CLKGATE_CON(19), 10, GFLAGS), 1033 1034 /* PD_VO */ 1035 COMPOSITE_NODIV(ACLK_VO, "aclk_vo", gpll300_cpll250_gpll100_xin24m_p, 0, 1036 RK3568_CLKSEL_CON(37), 0, 2, MFLAGS, 1037 RK3568_CLKGATE_CON(20), 0, GFLAGS), 1038 COMPOSITE_NOMUX(HCLK_VO, "hclk_vo", "aclk_vo", 0, 1039 RK3568_CLKSEL_CON(37), 8, 4, DFLAGS, 1040 RK3568_CLKGATE_CON(20), 1, GFLAGS), 1041 COMPOSITE_NOMUX(PCLK_VO, "pclk_vo", "aclk_vo", 0, 1042 RK3568_CLKSEL_CON(37), 12, 4, DFLAGS, 1043 RK3568_CLKGATE_CON(20), 2, GFLAGS), 1044 COMPOSITE(ACLK_VOP_PRE, "aclk_vop_pre", cpll_gpll_hpll_vpll_p, 0, 1045 RK3568_CLKSEL_CON(38), 6, 2, MFLAGS, 0, 5, DFLAGS, 1046 RK3568_CLKGATE_CON(20), 6, GFLAGS), 1047 GATE(ACLK_VOP, "aclk_vop", "aclk_vop_pre", 0, 1048 RK3568_CLKGATE_CON(20), 8, GFLAGS), 1049 GATE(HCLK_VOP, "hclk_vop", "hclk_vo", 0, 1050 RK3568_CLKGATE_CON(20), 9, GFLAGS), 1051 COMPOSITE(DCLK_VOP0, "dclk_vop0", hpll_vpll_gpll_cpll_p, CLK_SET_RATE_NO_REPARENT, 1052 RK3568_CLKSEL_CON(39), 10, 2, MFLAGS, 0, 8, DFLAGS, 1053 RK3568_CLKGATE_CON(20), 10, GFLAGS), 1054 COMPOSITE(DCLK_VOP1, "dclk_vop1", hpll_vpll_gpll_cpll_p, CLK_SET_RATE_NO_REPARENT, 1055 RK3568_CLKSEL_CON(40), 10, 2, MFLAGS, 0, 8, DFLAGS, 1056 RK3568_CLKGATE_CON(20), 11, GFLAGS), 1057 COMPOSITE(DCLK_VOP2, "dclk_vop2", hpll_vpll_gpll_cpll_p, CLK_SET_RATE_NO_REPARENT, 1058 RK3568_CLKSEL_CON(41), 10, 2, MFLAGS, 0, 8, DFLAGS, 1059 RK3568_CLKGATE_CON(20), 12, GFLAGS), 1060 GATE(CLK_VOP_PWM, "clk_vop_pwm", "xin24m", 0, 1061 RK3568_CLKGATE_CON(20), 13, GFLAGS), 1062 GATE(ACLK_HDCP, "aclk_hdcp", "aclk_vo", 0, 1063 RK3568_CLKGATE_CON(21), 0, GFLAGS), 1064 GATE(HCLK_HDCP, "hclk_hdcp", "hclk_vo", 0, 1065 RK3568_CLKGATE_CON(21), 1, GFLAGS), 1066 GATE(PCLK_HDCP, "pclk_hdcp", "pclk_vo", 0, 1067 RK3568_CLKGATE_CON(21), 2, GFLAGS), 1068 GATE(PCLK_HDMI_HOST, "pclk_hdmi_host", "pclk_vo", 0, 1069 RK3568_CLKGATE_CON(21), 3, GFLAGS), 1070 GATE(CLK_HDMI_SFR, "clk_hdmi_sfr", "xin24m", 0, 1071 RK3568_CLKGATE_CON(21), 4, GFLAGS), 1072 GATE(CLK_HDMI_CEC, "clk_hdmi_cec", "clk_rtc_32k", 0, 1073 RK3568_CLKGATE_CON(21), 5, GFLAGS), 1074 GATE(PCLK_DSITX_0, "pclk_dsitx_0", "pclk_vo", 0, 1075 RK3568_CLKGATE_CON(21), 6, GFLAGS), 1076 GATE(PCLK_DSITX_1, "pclk_dsitx_1", "pclk_vo", 0, 1077 RK3568_CLKGATE_CON(21), 7, GFLAGS), 1078 GATE(PCLK_EDP_CTRL, "pclk_edp_ctrl", "pclk_vo", 0, 1079 RK3568_CLKGATE_CON(21), 8, GFLAGS), 1080 COMPOSITE_NODIV(CLK_EDP_200M, "clk_edp_200m", gpll200_gpll150_cpll125_p, 0, 1081 RK3568_CLKSEL_CON(38), 8, 2, MFLAGS, 1082 RK3568_CLKGATE_CON(21), 9, GFLAGS), 1083 1084 /* PD_VPU */ 1085 COMPOSITE(ACLK_VPU_PRE, "aclk_vpu_pre", gpll_cpll_p, 0, 1086 RK3568_CLKSEL_CON(42), 7, 1, MFLAGS, 0, 5, DFLAGS, 1087 RK3568_CLKGATE_CON(22), 0, GFLAGS), 1088 COMPOSITE_NOMUX(HCLK_VPU_PRE, "hclk_vpu_pre", "aclk_vpu_pre", 0, 1089 RK3568_CLKSEL_CON(42), 8, 4, DFLAGS, 1090 RK3568_CLKGATE_CON(22), 1, GFLAGS), 1091 GATE(ACLK_VPU, "aclk_vpu", "aclk_vpu_pre", 0, 1092 RK3568_CLKGATE_CON(22), 4, GFLAGS), 1093 GATE(HCLK_VPU, "hclk_vpu", "hclk_vpu_pre", 0, 1094 RK3568_CLKGATE_CON(22), 5, GFLAGS), 1095 1096 /* PD_RGA */ 1097 COMPOSITE_NODIV(ACLK_RGA_PRE, "aclk_rga_pre", gpll300_cpll250_gpll100_xin24m_p, 0, 1098 RK3568_CLKSEL_CON(43), 0, 2, MFLAGS, 1099 RK3568_CLKGATE_CON(23), 0, GFLAGS), 1100 COMPOSITE_NOMUX(HCLK_RGA_PRE, "hclk_rga_pre", "aclk_rga_pre", 0, 1101 RK3568_CLKSEL_CON(43), 8, 4, DFLAGS, 1102 RK3568_CLKGATE_CON(23), 1, GFLAGS), 1103 COMPOSITE_NOMUX(PCLK_RGA_PRE, "pclk_rga_pre", "aclk_rga_pre", 0, 1104 RK3568_CLKSEL_CON(43), 12, 4, DFLAGS, 1105 RK3568_CLKGATE_CON(22), 12, GFLAGS), 1106 GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre", 0, 1107 RK3568_CLKGATE_CON(23), 4, GFLAGS), 1108 GATE(HCLK_RGA, "hclk_rga", "hclk_rga_pre", 0, 1109 RK3568_CLKGATE_CON(23), 5, GFLAGS), 1110 COMPOSITE_NODIV(CLK_RGA_CORE, "clk_rga_core", gpll300_gpll200_gpll100_p, 0, 1111 RK3568_CLKSEL_CON(43), 2, 2, MFLAGS, 1112 RK3568_CLKGATE_CON(23), 6, GFLAGS), 1113 GATE(ACLK_IEP, "aclk_iep", "aclk_rga_pre", 0, 1114 RK3568_CLKGATE_CON(23), 7, GFLAGS), 1115 GATE(HCLK_IEP, "hclk_iep", "hclk_rga_pre", 0, 1116 RK3568_CLKGATE_CON(23), 8, GFLAGS), 1117 COMPOSITE_NODIV(CLK_IEP_CORE, "clk_iep_core", gpll300_gpll200_gpll100_p, 0, 1118 RK3568_CLKSEL_CON(43), 4, 2, MFLAGS, 1119 RK3568_CLKGATE_CON(23), 9, GFLAGS), 1120 GATE(HCLK_EBC, "hclk_ebc", "hclk_rga_pre", 0, RK3568_CLKGATE_CON(23), 10, GFLAGS), 1121 COMPOSITE_NODIV(DCLK_EBC, "dclk_ebc", gpll400_cpll333_gpll200_p, 0, 1122 RK3568_CLKSEL_CON(43), 6, 2, MFLAGS, 1123 RK3568_CLKGATE_CON(23), 11, GFLAGS), 1124 GATE(ACLK_JDEC, "aclk_jdec", "aclk_rga_pre", 0, 1125 RK3568_CLKGATE_CON(23), 12, GFLAGS), 1126 GATE(HCLK_JDEC, "hclk_jdec", "hclk_rga_pre", 0, 1127 RK3568_CLKGATE_CON(23), 13, GFLAGS), 1128 GATE(ACLK_JENC, "aclk_jenc", "aclk_rga_pre", 0, 1129 RK3568_CLKGATE_CON(23), 14, GFLAGS), 1130 GATE(HCLK_JENC, "hclk_jenc", "hclk_rga_pre", 0, 1131 RK3568_CLKGATE_CON(23), 15, GFLAGS), 1132 GATE(PCLK_EINK, "pclk_eink", "pclk_rga_pre", 0, 1133 RK3568_CLKGATE_CON(22), 14, GFLAGS), 1134 GATE(HCLK_EINK, "hclk_eink", "hclk_rga_pre", 0, 1135 RK3568_CLKGATE_CON(22), 15, GFLAGS), 1136 1137 /* PD_RKVENC */ 1138 COMPOSITE(ACLK_RKVENC_PRE, "aclk_rkvenc_pre", gpll_cpll_npll_p, 0, 1139 RK3568_CLKSEL_CON(44), 6, 2, MFLAGS, 0, 5, DFLAGS, 1140 RK3568_CLKGATE_CON(24), 0, GFLAGS), 1141 COMPOSITE_NOMUX(HCLK_RKVENC_PRE, "hclk_rkvenc_pre", "aclk_rkvenc_pre", 0, 1142 RK3568_CLKSEL_CON(44), 8, 4, DFLAGS, 1143 RK3568_CLKGATE_CON(24), 1, GFLAGS), 1144 GATE(ACLK_RKVENC, "aclk_rkvenc", "aclk_rkvenc_pre", 0, 1145 RK3568_CLKGATE_CON(24), 6, GFLAGS), 1146 GATE(HCLK_RKVENC, "hclk_rkvenc", "hclk_rkvenc_pre", 0, 1147 RK3568_CLKGATE_CON(24), 7, GFLAGS), 1148 COMPOSITE(CLK_RKVENC_CORE, "clk_rkvenc_core", gpll_cpll_npll_vpll_p, 0, 1149 RK3568_CLKSEL_CON(45), 14, 2, MFLAGS, 0, 5, DFLAGS, 1150 RK3568_CLKGATE_CON(24), 8, GFLAGS), 1151 COMPOSITE(ACLK_RKVDEC_PRE, "aclk_rkvdec_pre", aclk_rkvdec_pre_p, CLK_SET_RATE_NO_REPARENT, 1152 RK3568_CLKSEL_CON(47), 7, 1, MFLAGS, 0, 5, DFLAGS, 1153 RK3568_CLKGATE_CON(25), 0, GFLAGS), 1154 COMPOSITE_NOMUX(HCLK_RKVDEC_PRE, "hclk_rkvdec_pre", "aclk_rkvdec_pre", 0, 1155 RK3568_CLKSEL_CON(47), 8, 4, DFLAGS, 1156 RK3568_CLKGATE_CON(25), 1, GFLAGS), 1157 GATE(ACLK_RKVDEC, "aclk_rkvdec", "aclk_rkvdec_pre", 0, 1158 RK3568_CLKGATE_CON(25), 4, GFLAGS), 1159 GATE(HCLK_RKVDEC, "hclk_rkvdec", "hclk_rkvdec_pre", 0, 1160 RK3568_CLKGATE_CON(25), 5, GFLAGS), 1161 COMPOSITE(CLK_RKVDEC_CA, "clk_rkvdec_ca", gpll_cpll_npll_vpll_p, 0, 1162 RK3568_CLKSEL_CON(48), 6, 2, MFLAGS, 0, 5, DFLAGS, 1163 RK3568_CLKGATE_CON(25), 6, GFLAGS), 1164 COMPOSITE(CLK_RKVDEC_CORE, "clk_rkvdec_core", clk_rkvdec_core_p, CLK_SET_RATE_NO_REPARENT, 1165 RK3568_CLKSEL_CON(49), 14, 2, MFLAGS, 8, 5, DFLAGS, 1166 RK3568_CLKGATE_CON(25), 7, GFLAGS), 1167 COMPOSITE(CLK_RKVDEC_HEVC_CA, "clk_rkvdec_hevc_ca", gpll_cpll_npll_vpll_p, 0, 1168 RK3568_CLKSEL_CON(49), 6, 2, MFLAGS, 0, 5, DFLAGS, 1169 RK3568_CLKGATE_CON(25), 8, GFLAGS), 1170 1171 /* PD_BUS */ 1172 COMPOSITE_NODIV(ACLK_BUS, "aclk_bus", gpll200_gpll150_gpll100_xin24m_p, 0, 1173 RK3568_CLKSEL_CON(50), 0, 2, MFLAGS, 1174 RK3568_CLKGATE_CON(26), 0, GFLAGS), 1175 COMPOSITE_NODIV(PCLK_BUS, "pclk_bus", gpll100_gpll75_cpll50_xin24m_p, 0, 1176 RK3568_CLKSEL_CON(50), 4, 2, MFLAGS, 1177 RK3568_CLKGATE_CON(26), 1, GFLAGS), 1178 GATE(PCLK_TSADC, "pclk_tsadc", "pclk_bus", 0, 1179 RK3568_CLKGATE_CON(26), 4, GFLAGS), 1180 COMPOSITE(CLK_TSADC_TSEN, "clk_tsadc_tsen", xin24m_gpll100_cpll100_p, 0, 1181 RK3568_CLKSEL_CON(51), 4, 2, MFLAGS, 0, 3, DFLAGS, 1182 RK3568_CLKGATE_CON(26), 5, GFLAGS), 1183 COMPOSITE_NOMUX(CLK_TSADC, "clk_tsadc", "clk_tsadc_tsen", 0, 1184 RK3568_CLKSEL_CON(51), 8, 7, DFLAGS, 1185 RK3568_CLKGATE_CON(26), 6, GFLAGS), 1186 GATE(PCLK_SARADC, "pclk_saradc", "pclk_bus", 0, 1187 RK3568_CLKGATE_CON(26), 7, GFLAGS), 1188 GATE(CLK_SARADC, "clk_saradc", "xin24m", 0, 1189 RK3568_CLKGATE_CON(26), 8, GFLAGS), 1190 GATE(PCLK_SCR, "pclk_scr", "pclk_bus", CLK_IGNORE_UNUSED, 1191 RK3568_CLKGATE_CON(26), 12, GFLAGS), 1192 GATE(PCLK_WDT_NS, "pclk_wdt_ns", "pclk_bus", 0, 1193 RK3568_CLKGATE_CON(26), 13, GFLAGS), 1194 GATE(TCLK_WDT_NS, "tclk_wdt_ns", "xin24m", 0, 1195 RK3568_CLKGATE_CON(26), 14, GFLAGS), 1196 GATE(ACLK_MCU, "aclk_mcu", "aclk_bus", CLK_IGNORE_UNUSED, 1197 RK3568_CLKGATE_CON(32), 13, GFLAGS), 1198 GATE(PCLK_INTMUX, "pclk_intmux", "pclk_bus", CLK_IGNORE_UNUSED, 1199 RK3568_CLKGATE_CON(32), 14, GFLAGS), 1200 GATE(PCLK_MAILBOX, "pclk_mailbox", "pclk_bus", 0, 1201 RK3568_CLKGATE_CON(32), 15, GFLAGS), 1202 1203 GATE(PCLK_UART1, "pclk_uart1", "pclk_bus", 0, 1204 RK3568_CLKGATE_CON(27), 12, GFLAGS), 1205 COMPOSITE(CLK_UART1_SRC, "clk_uart1_src", gpll_cpll_usb480m_p, 0, 1206 RK3568_CLKSEL_CON(52), 8, 2, MFLAGS, 0, 7, DFLAGS, 1207 RK3568_CLKGATE_CON(27), 13, GFLAGS), 1208 COMPOSITE_FRACMUX(CLK_UART1_FRAC, "clk_uart1_frac", "clk_uart1_src", CLK_SET_RATE_PARENT, 1209 RK3568_CLKSEL_CON(53), 0, 1210 RK3568_CLKGATE_CON(27), 14, GFLAGS, 1211 &rk3568_uart1_fracmux), 1212 GATE(SCLK_UART1, "sclk_uart1", "sclk_uart1_mux", 0, 1213 RK3568_CLKGATE_CON(27), 15, GFLAGS), 1214 1215 GATE(PCLK_UART2, "pclk_uart2", "pclk_bus", 0, 1216 RK3568_CLKGATE_CON(28), 0, GFLAGS), 1217 COMPOSITE(CLK_UART2_SRC, "clk_uart2_src", gpll_cpll_usb480m_p, 0, 1218 RK3568_CLKSEL_CON(54), 8, 2, MFLAGS, 0, 7, DFLAGS, 1219 RK3568_CLKGATE_CON(28), 1, GFLAGS), 1220 COMPOSITE_FRACMUX(CLK_UART2_FRAC, "clk_uart2_frac", "clk_uart2_src", CLK_SET_RATE_PARENT, 1221 RK3568_CLKSEL_CON(55), 0, 1222 RK3568_CLKGATE_CON(28), 2, GFLAGS, 1223 &rk3568_uart2_fracmux), 1224 GATE(SCLK_UART2, "sclk_uart2", "sclk_uart2_mux", 0, 1225 RK3568_CLKGATE_CON(28), 3, GFLAGS), 1226 1227 GATE(PCLK_UART3, "pclk_uart3", "pclk_bus", 0, 1228 RK3568_CLKGATE_CON(28), 4, GFLAGS), 1229 COMPOSITE(CLK_UART3_SRC, "clk_uart3_src", gpll_cpll_usb480m_p, 0, 1230 RK3568_CLKSEL_CON(56), 8, 2, MFLAGS, 0, 7, DFLAGS, 1231 RK3568_CLKGATE_CON(28), 5, GFLAGS), 1232 COMPOSITE_FRACMUX(CLK_UART3_FRAC, "clk_uart3_frac", "clk_uart3_src", CLK_SET_RATE_PARENT, 1233 RK3568_CLKSEL_CON(57), 0, 1234 RK3568_CLKGATE_CON(28), 6, GFLAGS, 1235 &rk3568_uart3_fracmux), 1236 GATE(SCLK_UART3, "sclk_uart3", "sclk_uart3_mux", 0, 1237 RK3568_CLKGATE_CON(28), 7, GFLAGS), 1238 1239 GATE(PCLK_UART4, "pclk_uart4", "pclk_bus", 0, 1240 RK3568_CLKGATE_CON(28), 8, GFLAGS), 1241 COMPOSITE(CLK_UART4_SRC, "clk_uart4_src", gpll_cpll_usb480m_p, 0, 1242 RK3568_CLKSEL_CON(58), 8, 2, MFLAGS, 0, 7, DFLAGS, 1243 RK3568_CLKGATE_CON(28), 9, GFLAGS), 1244 COMPOSITE_FRACMUX(CLK_UART4_FRAC, "clk_uart4_frac", "clk_uart4_src", CLK_SET_RATE_PARENT, 1245 RK3568_CLKSEL_CON(59), 0, 1246 RK3568_CLKGATE_CON(28), 10, GFLAGS, 1247 &rk3568_uart4_fracmux), 1248 GATE(SCLK_UART4, "sclk_uart4", "sclk_uart4_mux", 0, 1249 RK3568_CLKGATE_CON(28), 11, GFLAGS), 1250 1251 GATE(PCLK_UART5, "pclk_uart5", "pclk_bus", 0, 1252 RK3568_CLKGATE_CON(28), 12, GFLAGS), 1253 COMPOSITE(CLK_UART5_SRC, "clk_uart5_src", gpll_cpll_usb480m_p, 0, 1254 RK3568_CLKSEL_CON(60), 8, 2, MFLAGS, 0, 7, DFLAGS, 1255 RK3568_CLKGATE_CON(28), 13, GFLAGS), 1256 COMPOSITE_FRACMUX(CLK_UART5_FRAC, "clk_uart5_frac", "clk_uart5_src", CLK_SET_RATE_PARENT, 1257 RK3568_CLKSEL_CON(61), 0, 1258 RK3568_CLKGATE_CON(28), 14, GFLAGS, 1259 &rk3568_uart5_fracmux), 1260 GATE(SCLK_UART5, "sclk_uart5", "sclk_uart5_mux", 0, 1261 RK3568_CLKGATE_CON(28), 15, GFLAGS), 1262 1263 GATE(PCLK_UART6, "pclk_uart6", "pclk_bus", 0, 1264 RK3568_CLKGATE_CON(29), 0, GFLAGS), 1265 COMPOSITE(CLK_UART6_SRC, "clk_uart6_src", gpll_cpll_usb480m_p, 0, 1266 RK3568_CLKSEL_CON(62), 8, 2, MFLAGS, 0, 7, DFLAGS, 1267 RK3568_CLKGATE_CON(29), 1, GFLAGS), 1268 COMPOSITE_FRACMUX(CLK_UART6_FRAC, "clk_uart6_frac", "clk_uart6_src", CLK_SET_RATE_PARENT, 1269 RK3568_CLKSEL_CON(63), 0, 1270 RK3568_CLKGATE_CON(29), 2, GFLAGS, 1271 &rk3568_uart6_fracmux), 1272 GATE(SCLK_UART6, "sclk_uart6", "sclk_uart6_mux", 0, 1273 RK3568_CLKGATE_CON(29), 3, GFLAGS), 1274 1275 GATE(PCLK_UART7, "pclk_uart7", "pclk_bus", 0, 1276 RK3568_CLKGATE_CON(29), 4, GFLAGS), 1277 COMPOSITE(CLK_UART7_SRC, "clk_uart7_src", gpll_cpll_usb480m_p, 0, 1278 RK3568_CLKSEL_CON(64), 8, 2, MFLAGS, 0, 7, DFLAGS, 1279 RK3568_CLKGATE_CON(29), 5, GFLAGS), 1280 COMPOSITE_FRACMUX(CLK_UART7_FRAC, "clk_uart7_frac", "clk_uart7_src", CLK_SET_RATE_PARENT, 1281 RK3568_CLKSEL_CON(65), 0, 1282 RK3568_CLKGATE_CON(29), 6, GFLAGS, 1283 &rk3568_uart7_fracmux), 1284 GATE(SCLK_UART7, "sclk_uart7", "sclk_uart7_mux", 0, 1285 RK3568_CLKGATE_CON(29), 7, GFLAGS), 1286 1287 GATE(PCLK_UART8, "pclk_uart8", "pclk_bus", 0, 1288 RK3568_CLKGATE_CON(29), 8, GFLAGS), 1289 COMPOSITE(CLK_UART8_SRC, "clk_uart8_src", gpll_cpll_usb480m_p, 0, 1290 RK3568_CLKSEL_CON(66), 8, 2, MFLAGS, 0, 7, DFLAGS, 1291 RK3568_CLKGATE_CON(29), 9, GFLAGS), 1292 COMPOSITE_FRACMUX(CLK_UART8_FRAC, "clk_uart8_frac", "clk_uart8_src", CLK_SET_RATE_PARENT, 1293 RK3568_CLKSEL_CON(67), 0, 1294 RK3568_CLKGATE_CON(29), 10, GFLAGS, 1295 &rk3568_uart8_fracmux), 1296 GATE(SCLK_UART8, "sclk_uart8", "sclk_uart8_mux", 0, 1297 RK3568_CLKGATE_CON(29), 11, GFLAGS), 1298 1299 GATE(PCLK_UART9, "pclk_uart9", "pclk_bus", 0, 1300 RK3568_CLKGATE_CON(29), 12, GFLAGS), 1301 COMPOSITE(CLK_UART9_SRC, "clk_uart9_src", gpll_cpll_usb480m_p, 0, 1302 RK3568_CLKSEL_CON(68), 8, 2, MFLAGS, 0, 7, DFLAGS, 1303 RK3568_CLKGATE_CON(29), 13, GFLAGS), 1304 COMPOSITE_FRACMUX(CLK_UART9_FRAC, "clk_uart9_frac", "clk_uart9_src", CLK_SET_RATE_PARENT, 1305 RK3568_CLKSEL_CON(69), 0, 1306 RK3568_CLKGATE_CON(29), 14, GFLAGS, 1307 &rk3568_uart9_fracmux), 1308 GATE(SCLK_UART9, "sclk_uart9", "sclk_uart9_mux", 0, 1309 RK3568_CLKGATE_CON(29), 15, GFLAGS), 1310 1311 GATE(PCLK_CAN0, "pclk_can0", "pclk_bus", 0, 1312 RK3568_CLKGATE_CON(27), 5, GFLAGS), 1313 COMPOSITE(CLK_CAN0, "clk_can0", gpll_cpll_p, 0, 1314 RK3568_CLKSEL_CON(70), 7, 1, MFLAGS, 0, 5, DFLAGS, 1315 RK3568_CLKGATE_CON(27), 6, GFLAGS), 1316 GATE(PCLK_CAN1, "pclk_can1", "pclk_bus", 0, 1317 RK3568_CLKGATE_CON(27), 7, GFLAGS), 1318 COMPOSITE(CLK_CAN1, "clk_can1", gpll_cpll_p, 0, 1319 RK3568_CLKSEL_CON(70), 15, 1, MFLAGS, 8, 5, DFLAGS, 1320 RK3568_CLKGATE_CON(27), 8, GFLAGS), 1321 GATE(PCLK_CAN2, "pclk_can2", "pclk_bus", 0, 1322 RK3568_CLKGATE_CON(27), 9, GFLAGS), 1323 COMPOSITE(CLK_CAN2, "clk_can2", gpll_cpll_p, 0, 1324 RK3568_CLKSEL_CON(71), 7, 1, MFLAGS, 0, 5, DFLAGS, 1325 RK3568_CLKGATE_CON(27), 10, GFLAGS), 1326 COMPOSITE_NODIV(CLK_I2C, "clk_i2c", clk_i2c_p, 0, 1327 RK3568_CLKSEL_CON(71), 8, 2, MFLAGS, 1328 RK3568_CLKGATE_CON(32), 10, GFLAGS), 1329 GATE(PCLK_I2C1, "pclk_i2c1", "pclk_bus", 0, 1330 RK3568_CLKGATE_CON(30), 0, GFLAGS), 1331 GATE(CLK_I2C1, "clk_i2c1", "clk_i2c", 0, 1332 RK3568_CLKGATE_CON(30), 1, GFLAGS), 1333 GATE(PCLK_I2C2, "pclk_i2c2", "pclk_bus", 0, 1334 RK3568_CLKGATE_CON(30), 2, GFLAGS), 1335 GATE(CLK_I2C2, "clk_i2c2", "clk_i2c", 0, 1336 RK3568_CLKGATE_CON(30), 3, GFLAGS), 1337 GATE(PCLK_I2C3, "pclk_i2c3", "pclk_bus", 0, 1338 RK3568_CLKGATE_CON(30), 4, GFLAGS), 1339 GATE(CLK_I2C3, "clk_i2c3", "clk_i2c", 0, 1340 RK3568_CLKGATE_CON(30), 5, GFLAGS), 1341 GATE(PCLK_I2C4, "pclk_i2c4", "pclk_bus", 0, 1342 RK3568_CLKGATE_CON(30), 6, GFLAGS), 1343 GATE(CLK_I2C4, "clk_i2c4", "clk_i2c", 0, 1344 RK3568_CLKGATE_CON(30), 7, GFLAGS), 1345 GATE(PCLK_I2C5, "pclk_i2c5", "pclk_bus", 0, 1346 RK3568_CLKGATE_CON(30), 8, GFLAGS), 1347 GATE(CLK_I2C5, "clk_i2c5", "clk_i2c", 0, 1348 RK3568_CLKGATE_CON(30), 9, GFLAGS), 1349 GATE(PCLK_SPI0, "pclk_spi0", "pclk_bus", 0, 1350 RK3568_CLKGATE_CON(30), 10, GFLAGS), 1351 COMPOSITE_NODIV(CLK_SPI0, "clk_spi0", gpll200_xin24m_cpll100_p, 0, 1352 RK3568_CLKSEL_CON(72), 0, 1, MFLAGS, 1353 RK3568_CLKGATE_CON(30), 11, GFLAGS), 1354 GATE(PCLK_SPI1, "pclk_spi1", "pclk_bus", 0, 1355 RK3568_CLKGATE_CON(30), 12, GFLAGS), 1356 COMPOSITE_NODIV(CLK_SPI1, "clk_spi1", gpll200_xin24m_cpll100_p, 0, 1357 RK3568_CLKSEL_CON(72), 2, 1, MFLAGS, 1358 RK3568_CLKGATE_CON(30), 13, GFLAGS), 1359 GATE(PCLK_SPI2, "pclk_spi2", "pclk_bus", 0, 1360 RK3568_CLKGATE_CON(30), 14, GFLAGS), 1361 COMPOSITE_NODIV(CLK_SPI2, "clk_spi2", gpll200_xin24m_cpll100_p, 0, 1362 RK3568_CLKSEL_CON(72), 4, 1, MFLAGS, 1363 RK3568_CLKGATE_CON(30), 15, GFLAGS), 1364 GATE(PCLK_SPI3, "pclk_spi3", "pclk_bus", 0, 1365 RK3568_CLKGATE_CON(31), 0, GFLAGS), 1366 COMPOSITE_NODIV(CLK_SPI3, "clk_spi3", gpll200_xin24m_cpll100_p, 0, 1367 RK3568_CLKSEL_CON(72), 6, 1, MFLAGS, RK3568_CLKGATE_CON(31), 1, GFLAGS), 1368 GATE(PCLK_PWM1, "pclk_pwm1", "pclk_bus", 0, RK3568_CLKGATE_CON(31), 10, GFLAGS), 1369 COMPOSITE_NODIV(CLK_PWM1, "clk_pwm1", gpll100_xin24m_cpll100_p, 0, 1370 RK3568_CLKSEL_CON(72), 8, 1, MFLAGS, 1371 RK3568_CLKGATE_CON(31), 11, GFLAGS), 1372 GATE(CLK_PWM1_CAPTURE, "clk_pwm1_capture", "xin24m", 0, 1373 RK3568_CLKGATE_CON(31), 12, GFLAGS), 1374 GATE(PCLK_PWM2, "pclk_pwm2", "pclk_bus", 0, 1375 RK3568_CLKGATE_CON(31), 13, GFLAGS), 1376 COMPOSITE_NODIV(CLK_PWM2, "clk_pwm2", gpll100_xin24m_cpll100_p, 0, 1377 RK3568_CLKSEL_CON(72), 10, 1, MFLAGS, 1378 RK3568_CLKGATE_CON(31), 14, GFLAGS), 1379 GATE(CLK_PWM2_CAPTURE, "clk_pwm2_capture", "xin24m", 0, 1380 RK3568_CLKGATE_CON(31), 15, GFLAGS), 1381 GATE(PCLK_PWM3, "pclk_pwm3", "pclk_bus", 0, 1382 RK3568_CLKGATE_CON(32), 0, GFLAGS), 1383 COMPOSITE_NODIV(CLK_PWM3, "clk_pwm3", gpll100_xin24m_cpll100_p, 0, 1384 RK3568_CLKSEL_CON(72), 12, 1, MFLAGS, 1385 RK3568_CLKGATE_CON(32), 1, GFLAGS), 1386 GATE(CLK_PWM3_CAPTURE, "clk_pwm3_capture", "xin24m", 0, 1387 RK3568_CLKGATE_CON(32), 2, GFLAGS), 1388 COMPOSITE_NODIV(DBCLK_GPIO, "dbclk_gpio", xin24m_32k_p, 0, 1389 RK3568_CLKSEL_CON(72), 14, 1, MFLAGS, 1390 RK3568_CLKGATE_CON(32), 11, GFLAGS), 1391 GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_bus", 0, 1392 RK3568_CLKGATE_CON(31), 2, GFLAGS), 1393 GATE(DBCLK_GPIO1, "dbclk_gpio1", "dbclk_gpio", 0, 1394 RK3568_CLKGATE_CON(31), 3, GFLAGS), 1395 GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_bus", 0, 1396 RK3568_CLKGATE_CON(31), 4, GFLAGS), 1397 GATE(DBCLK_GPIO2, "dbclk_gpio2", "dbclk_gpio", 0, 1398 RK3568_CLKGATE_CON(31), 5, GFLAGS), 1399 GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_bus", 0, 1400 RK3568_CLKGATE_CON(31), 6, GFLAGS), 1401 GATE(DBCLK_GPIO3, "dbclk_gpio3", "dbclk_gpio", 0, 1402 RK3568_CLKGATE_CON(31), 7, GFLAGS), 1403 GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_bus", 0, 1404 RK3568_CLKGATE_CON(31), 8, GFLAGS), 1405 GATE(DBCLK_GPIO4, "dbclk_gpio4", "dbclk_gpio", 0, 1406 RK3568_CLKGATE_CON(31), 9, GFLAGS), 1407 GATE(PCLK_TIMER, "pclk_timer", "pclk_bus", 0, 1408 RK3568_CLKGATE_CON(32), 3, GFLAGS), 1409 GATE(CLK_TIMER0, "clk_timer0", "xin24m", 0, 1410 RK3568_CLKGATE_CON(32), 4, GFLAGS), 1411 GATE(CLK_TIMER1, "clk_timer1", "xin24m", 0, 1412 RK3568_CLKGATE_CON(32), 5, GFLAGS), 1413 GATE(CLK_TIMER2, "clk_timer2", "xin24m", 0, 1414 RK3568_CLKGATE_CON(32), 6, GFLAGS), 1415 GATE(CLK_TIMER3, "clk_timer3", "xin24m", 0, 1416 RK3568_CLKGATE_CON(32), 7, GFLAGS), 1417 GATE(CLK_TIMER4, "clk_timer4", "xin24m", 0, 1418 RK3568_CLKGATE_CON(32), 8, GFLAGS), 1419 GATE(CLK_TIMER5, "clk_timer5", "xin24m", 0, 1420 RK3568_CLKGATE_CON(32), 9, GFLAGS), 1421 1422 /* PD_TOP */ 1423 COMPOSITE_NODIV(ACLK_TOP_HIGH, "aclk_top_high", cpll500_gpll400_gpll300_xin24m_p, 0, 1424 RK3568_CLKSEL_CON(73), 0, 2, MFLAGS, 1425 RK3568_CLKGATE_CON(33), 0, GFLAGS), 1426 COMPOSITE_NODIV(ACLK_TOP_LOW, "aclk_top_low", gpll400_gpll300_gpll200_xin24m_p, 0, 1427 RK3568_CLKSEL_CON(73), 4, 2, MFLAGS, 1428 RK3568_CLKGATE_CON(33), 1, GFLAGS), 1429 COMPOSITE_NODIV(HCLK_TOP, "hclk_top", gpll150_gpll100_gpll75_xin24m_p, 0, 1430 RK3568_CLKSEL_CON(73), 8, 2, MFLAGS, 1431 RK3568_CLKGATE_CON(33), 2, GFLAGS), 1432 COMPOSITE_NODIV(PCLK_TOP, "pclk_top", gpll100_gpll75_cpll50_xin24m_p, 0, 1433 RK3568_CLKSEL_CON(73), 12, 2, MFLAGS, 1434 RK3568_CLKGATE_CON(33), 3, GFLAGS), 1435 GATE(PCLK_PCIE30PHY, "pclk_pcie30phy", "pclk_top", 0, 1436 RK3568_CLKGATE_CON(33), 8, GFLAGS), 1437 COMPOSITE_NODIV(CLK_OPTC_ARB, "clk_optc_arb", xin24m_cpll100_p, 0, 1438 RK3568_CLKSEL_CON(73), 15, 1, MFLAGS, 1439 RK3568_CLKGATE_CON(33), 9, GFLAGS), 1440 GATE(PCLK_MIPICSIPHY, "pclk_mipicsiphy", "pclk_top", 0, 1441 RK3568_CLKGATE_CON(33), 13, GFLAGS), 1442 GATE(PCLK_MIPIDSIPHY0, "pclk_mipidsiphy0", "pclk_top", 0, 1443 RK3568_CLKGATE_CON(33), 14, GFLAGS), 1444 GATE(PCLK_MIPIDSIPHY1, "pclk_mipidsiphy1", "pclk_top", 0, 1445 RK3568_CLKGATE_CON(33), 15, GFLAGS), 1446 GATE(PCLK_PIPEPHY0, "pclk_pipephy0", "pclk_top", 0, 1447 RK3568_CLKGATE_CON(34), 4, GFLAGS), 1448 GATE(PCLK_PIPEPHY1, "pclk_pipephy1", "pclk_top", 0, 1449 RK3568_CLKGATE_CON(34), 5, GFLAGS), 1450 GATE(PCLK_PIPEPHY2, "pclk_pipephy2", "pclk_top", 0, 1451 RK3568_CLKGATE_CON(34), 6, GFLAGS), 1452 GATE(PCLK_CPU_BOOST, "pclk_cpu_boost", "pclk_top", 0, 1453 RK3568_CLKGATE_CON(34), 11, GFLAGS), 1454 GATE(CLK_CPU_BOOST, "clk_cpu_boost", "xin24m", 0, 1455 RK3568_CLKGATE_CON(34), 12, GFLAGS), 1456 GATE(PCLK_OTPPHY, "pclk_otpphy", "pclk_top", 0, 1457 RK3568_CLKGATE_CON(34), 13, GFLAGS), 1458 GATE(PCLK_EDPPHY_GRF, "pclk_edpphy_grf", "pclk_top", 0, 1459 RK3568_CLKGATE_CON(34), 14, GFLAGS), 1460 }; 1461 1462 static struct rockchip_clk_branch rk3568_clk_pmu_branches[] __initdata = { 1463 /* PD_PMU */ 1464 FACTOR(0, "ppll_ph0", "ppll", 0, 1, 2), 1465 FACTOR(0, "ppll_ph180", "ppll", 0, 1, 2), 1466 FACTOR(0, "hpll_ph0", "hpll", 0, 1, 2), 1467 1468 MUX(CLK_PDPMU, "clk_pdpmu", clk_pdpmu_p, 0, 1469 RK3568_PMU_CLKSEL_CON(2), 15, 1, MFLAGS), 1470 COMPOSITE_NOMUX(PCLK_PDPMU, "pclk_pdpmu", "clk_pdpmu", 0, 1471 RK3568_PMU_CLKSEL_CON(2), 0, 5, DFLAGS, 1472 RK3568_PMU_CLKGATE_CON(0), 2, GFLAGS), 1473 GATE(PCLK_PMU, "pclk_pmu", "pclk_pdpmu", 0, 1474 RK3568_PMU_CLKGATE_CON(0), 6, GFLAGS), 1475 GATE(CLK_PMU, "clk_pmu", "xin24m", 0, 1476 RK3568_PMU_CLKGATE_CON(0), 7, GFLAGS), 1477 GATE(PCLK_I2C0, "pclk_i2c0", "pclk_pdpmu", 0, 1478 RK3568_PMU_CLKGATE_CON(1), 0, GFLAGS), 1479 COMPOSITE_NOMUX(CLK_I2C0, "clk_i2c0", "clk_pdpmu", 0, 1480 RK3568_PMU_CLKSEL_CON(3), 0, 7, DFLAGS, 1481 RK3568_PMU_CLKGATE_CON(1), 1, GFLAGS), 1482 GATE(PCLK_UART0, "pclk_uart0", "pclk_pdpmu", 0, 1483 RK3568_PMU_CLKGATE_CON(1), 2, GFLAGS), 1484 1485 COMPOSITE_FRACMUX(CLK_RTC32K_FRAC, "clk_rtc32k_frac", "xin24m", CLK_IGNORE_UNUSED, 1486 RK3568_PMU_CLKSEL_CON(1), 0, 1487 RK3568_PMU_CLKGATE_CON(0), 1, GFLAGS, 1488 &rk3568_rtc32k_pmu_fracmux), 1489 1490 COMPOSITE_NOMUX(XIN_OSC0_DIV, "xin_osc0_div", "xin24m", CLK_IGNORE_UNUSED, 1491 RK3568_PMU_CLKSEL_CON(0), 0, 5, DFLAGS, 1492 RK3568_PMU_CLKGATE_CON(0), 0, GFLAGS), 1493 1494 COMPOSITE(CLK_UART0_DIV, "sclk_uart0_div", ppll_usb480m_cpll_gpll_p, 0, 1495 RK3568_PMU_CLKSEL_CON(4), 8, 2, MFLAGS, 0, 7, DFLAGS, 1496 RK3568_PMU_CLKGATE_CON(1), 3, GFLAGS), 1497 COMPOSITE_FRACMUX(CLK_UART0_FRAC, "sclk_uart0_frac", "sclk_uart0_div", CLK_SET_RATE_PARENT, 1498 RK3568_PMU_CLKSEL_CON(5), 0, 1499 RK3568_PMU_CLKGATE_CON(1), 4, GFLAGS, 1500 &rk3568_uart0_fracmux), 1501 GATE(SCLK_UART0, "sclk_uart0", "sclk_uart0_mux", 0, 1502 RK3568_PMU_CLKGATE_CON(1), 5, GFLAGS), 1503 1504 GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_pdpmu", 0, 1505 RK3568_PMU_CLKGATE_CON(1), 9, GFLAGS), 1506 COMPOSITE_NODIV(DBCLK_GPIO0, "dbclk_gpio0", xin24m_32k_p, 0, 1507 RK3568_PMU_CLKSEL_CON(6), 15, 1, MFLAGS, 1508 RK3568_PMU_CLKGATE_CON(1), 10, GFLAGS), 1509 GATE(PCLK_PWM0, "pclk_pwm0", "pclk_pdpmu", 0, 1510 RK3568_PMU_CLKGATE_CON(1), 6, GFLAGS), 1511 COMPOSITE(CLK_PWM0, "clk_pwm0", clk_pwm0_p, 0, 1512 RK3568_PMU_CLKSEL_CON(6), 7, 1, MFLAGS, 0, 7, DFLAGS, 1513 RK3568_PMU_CLKGATE_CON(1), 7, GFLAGS), 1514 GATE(CLK_CAPTURE_PWM0_NDFT, "clk_capture_pwm0_ndft", "xin24m", 0, 1515 RK3568_PMU_CLKGATE_CON(1), 8, GFLAGS), 1516 GATE(PCLK_PMUPVTM, "pclk_pmupvtm", "pclk_pdpmu", 0, 1517 RK3568_PMU_CLKGATE_CON(1), 11, GFLAGS), 1518 GATE(CLK_PMUPVTM, "clk_pmupvtm", "xin24m", 0, 1519 RK3568_PMU_CLKGATE_CON(1), 12, GFLAGS), 1520 GATE(CLK_CORE_PMUPVTM, "clk_core_pmupvtm", "xin24m", 0, 1521 RK3568_PMU_CLKGATE_CON(1), 13, GFLAGS), 1522 COMPOSITE_NOMUX(CLK_REF24M, "clk_ref24m", "clk_pdpmu", 0, 1523 RK3568_PMU_CLKSEL_CON(7), 0, 6, DFLAGS, 1524 RK3568_PMU_CLKGATE_CON(2), 0, GFLAGS), 1525 GATE(XIN_OSC0_USBPHY0_G, "xin_osc0_usbphy0_g", "xin24m", 0, 1526 RK3568_PMU_CLKGATE_CON(2), 1, GFLAGS), 1527 MUX(CLK_USBPHY0_REF, "clk_usbphy0_ref", clk_usbphy0_ref_p, 0, 1528 RK3568_PMU_CLKSEL_CON(8), 0, 1, MFLAGS), 1529 GATE(XIN_OSC0_USBPHY1_G, "xin_osc0_usbphy1_g", "xin24m", 0, 1530 RK3568_PMU_CLKGATE_CON(2), 2, GFLAGS), 1531 MUX(CLK_USBPHY1_REF, "clk_usbphy1_ref", clk_usbphy1_ref_p, 0, 1532 RK3568_PMU_CLKSEL_CON(8), 1, 1, MFLAGS), 1533 GATE(XIN_OSC0_MIPIDSIPHY0_G, "xin_osc0_mipidsiphy0_g", "xin24m", 0, 1534 RK3568_PMU_CLKGATE_CON(2), 3, GFLAGS), 1535 MUX(CLK_MIPIDSIPHY0_REF, "clk_mipidsiphy0_ref", clk_mipidsiphy0_ref_p, 0, 1536 RK3568_PMU_CLKSEL_CON(8), 2, 1, MFLAGS), 1537 GATE(XIN_OSC0_MIPIDSIPHY1_G, "xin_osc0_mipidsiphy1_g", "xin24m", 0, 1538 RK3568_PMU_CLKGATE_CON(2), 4, GFLAGS), 1539 MUX(CLK_MIPIDSIPHY1_REF, "clk_mipidsiphy1_ref", clk_mipidsiphy1_ref_p, 0, 1540 RK3568_PMU_CLKSEL_CON(8), 3, 1, MFLAGS), 1541 COMPOSITE_NOMUX(CLK_WIFI_DIV, "clk_wifi_div", "clk_pdpmu", 0, 1542 RK3568_PMU_CLKSEL_CON(8), 8, 6, DFLAGS, 1543 RK3568_PMU_CLKGATE_CON(2), 5, GFLAGS), 1544 GATE(CLK_WIFI_OSC0, "clk_wifi_osc0", "xin24m", 0, 1545 RK3568_PMU_CLKGATE_CON(2), 6, GFLAGS), 1546 MUX(CLK_WIFI, "clk_wifi", clk_wifi_p, CLK_SET_RATE_PARENT, 1547 RK3568_PMU_CLKSEL_CON(8), 15, 1, MFLAGS), 1548 COMPOSITE_NOMUX(CLK_PCIEPHY0_DIV, "clk_pciephy0_div", "ppll_ph0", 0, 1549 RK3568_PMU_CLKSEL_CON(9), 0, 3, DFLAGS, 1550 RK3568_PMU_CLKGATE_CON(2), 7, GFLAGS), 1551 GATE(CLK_PCIEPHY0_OSC0, "clk_pciephy0_osc0", "xin24m", 0, 1552 RK3568_PMU_CLKGATE_CON(2), 8, GFLAGS), 1553 MUX(CLK_PCIEPHY0_REF, "clk_pciephy0_ref", clk_pciephy0_ref_p, CLK_SET_RATE_PARENT, 1554 RK3568_PMU_CLKSEL_CON(9), 3, 1, MFLAGS), 1555 COMPOSITE_NOMUX(CLK_PCIEPHY1_DIV, "clk_pciephy1_div", "ppll_ph0", 0, 1556 RK3568_PMU_CLKSEL_CON(9), 4, 3, DFLAGS, 1557 RK3568_PMU_CLKGATE_CON(2), 9, GFLAGS), 1558 GATE(CLK_PCIEPHY1_OSC0, "clk_pciephy1_osc0", "xin24m", 0, 1559 RK3568_PMU_CLKGATE_CON(2), 10, GFLAGS), 1560 MUX(CLK_PCIEPHY1_REF, "clk_pciephy1_ref", clk_pciephy1_ref_p, CLK_SET_RATE_PARENT, 1561 RK3568_PMU_CLKSEL_CON(9), 7, 1, MFLAGS), 1562 COMPOSITE_NOMUX(CLK_PCIEPHY2_DIV, "clk_pciephy2_div", "ppll_ph0", 0, 1563 RK3568_PMU_CLKSEL_CON(9), 8, 3, DFLAGS, 1564 RK3568_PMU_CLKGATE_CON(2), 11, GFLAGS), 1565 GATE(CLK_PCIEPHY2_OSC0, "clk_pciephy2_osc0", "xin24m", 0, 1566 RK3568_PMU_CLKGATE_CON(2), 12, GFLAGS), 1567 MUX(CLK_PCIEPHY2_REF, "clk_pciephy2_ref", clk_pciephy2_ref_p, CLK_SET_RATE_PARENT, 1568 RK3568_PMU_CLKSEL_CON(9), 11, 1, MFLAGS), 1569 GATE(CLK_PCIE30PHY_REF_M, "clk_pcie30phy_ref_m", "ppll_ph0", 0, 1570 RK3568_PMU_CLKGATE_CON(2), 13, GFLAGS), 1571 GATE(CLK_PCIE30PHY_REF_N, "clk_pcie30phy_ref_n", "ppll_ph180", 0, 1572 RK3568_PMU_CLKGATE_CON(2), 14, GFLAGS), 1573 GATE(XIN_OSC0_EDPPHY_G, "xin_osc0_edpphy_g", "xin24m", 0, 1574 RK3568_PMU_CLKGATE_CON(2), 15, GFLAGS), 1575 MUX(CLK_HDMI_REF, "clk_hdmi_ref", clk_hdmi_ref_p, CLK_SET_RATE_PARENT, 1576 RK3568_PMU_CLKSEL_CON(8), 7, 1, MFLAGS), 1577 }; 1578 1579 static const char *const rk3568_cru_critical_clocks[] __initconst = { 1580 "armclk", 1581 "pclk_core_pre", 1582 "aclk_bus", 1583 "pclk_bus", 1584 "aclk_top_high", 1585 "aclk_top_low", 1586 "hclk_top", 1587 "pclk_top", 1588 "aclk_perimid", 1589 "hclk_perimid", 1590 "aclk_secure_flash", 1591 "hclk_secure_flash", 1592 "aclk_core_niu2bus", 1593 "npll", 1594 "clk_optc_arb", 1595 "hclk_php", 1596 "pclk_php", 1597 "hclk_usb", 1598 "pclk_usb", 1599 "hclk_vo", 1600 }; 1601 1602 static const char *const rk3568_pmucru_critical_clocks[] __initconst = { 1603 "pclk_pdpmu", 1604 "pclk_pmu", 1605 "clk_pmu", 1606 }; 1607 1608 static void __init rk3568_pmu_clk_init(struct device_node *np) 1609 { 1610 struct rockchip_clk_provider *ctx; 1611 void __iomem *reg_base; 1612 1613 reg_base = of_iomap(np, 0); 1614 if (!reg_base) { 1615 pr_err("%s: could not map cru pmu region\n", __func__); 1616 return; 1617 } 1618 1619 ctx = rockchip_clk_init(np, reg_base, CLKPMU_NR_CLKS); 1620 if (IS_ERR(ctx)) { 1621 pr_err("%s: rockchip pmu clk init failed\n", __func__); 1622 return; 1623 } 1624 1625 rockchip_clk_register_plls(ctx, rk3568_pmu_pll_clks, 1626 ARRAY_SIZE(rk3568_pmu_pll_clks), 1627 RK3568_GRF_SOC_STATUS0); 1628 1629 rockchip_clk_register_branches(ctx, rk3568_clk_pmu_branches, 1630 ARRAY_SIZE(rk3568_clk_pmu_branches)); 1631 1632 rockchip_register_softrst(np, 1, reg_base + RK3568_PMU_SOFTRST_CON(0), 1633 ROCKCHIP_SOFTRST_HIWORD_MASK); 1634 1635 rockchip_clk_protect_critical(rk3568_pmucru_critical_clocks, 1636 ARRAY_SIZE(rk3568_pmucru_critical_clocks)); 1637 1638 rockchip_clk_of_add_provider(np, ctx); 1639 } 1640 1641 CLK_OF_DECLARE(rk3568_cru_pmu, "rockchip,rk3568-pmucru", rk3568_pmu_clk_init); 1642 1643 static void __init rk3568_clk_init(struct device_node *np) 1644 { 1645 struct rockchip_clk_provider *ctx; 1646 void __iomem *reg_base; 1647 1648 reg_base = of_iomap(np, 0); 1649 if (!reg_base) { 1650 pr_err("%s: could not map cru region\n", __func__); 1651 return; 1652 } 1653 1654 ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS); 1655 if (IS_ERR(ctx)) { 1656 pr_err("%s: rockchip clk init failed\n", __func__); 1657 iounmap(reg_base); 1658 return; 1659 } 1660 1661 rockchip_clk_register_plls(ctx, rk3568_pll_clks, 1662 ARRAY_SIZE(rk3568_pll_clks), 1663 RK3568_GRF_SOC_STATUS0); 1664 1665 rockchip_clk_register_armclk(ctx, ARMCLK, "armclk", 1666 mux_armclk_p, ARRAY_SIZE(mux_armclk_p), 1667 &rk3568_cpuclk_data, rk3568_cpuclk_rates, 1668 ARRAY_SIZE(rk3568_cpuclk_rates)); 1669 1670 rockchip_clk_register_branches(ctx, rk3568_clk_branches, 1671 ARRAY_SIZE(rk3568_clk_branches)); 1672 1673 rockchip_register_softrst(np, 30, reg_base + RK3568_SOFTRST_CON(0), 1674 ROCKCHIP_SOFTRST_HIWORD_MASK); 1675 1676 rockchip_register_restart_notifier(ctx, RK3568_GLB_SRST_FST, NULL); 1677 1678 rockchip_clk_protect_critical(rk3568_cru_critical_clocks, 1679 ARRAY_SIZE(rk3568_cru_critical_clocks)); 1680 1681 rockchip_clk_of_add_provider(np, ctx); 1682 } 1683 1684 CLK_OF_DECLARE(rk3568_cru, "rockchip,rk3568-cru", rk3568_clk_init); 1685 1686 struct clk_rk3568_inits { 1687 void (*inits)(struct device_node *np); 1688 }; 1689 1690 static const struct clk_rk3568_inits clk_rk3568_pmucru_init = { 1691 .inits = rk3568_pmu_clk_init, 1692 }; 1693 1694 static const struct clk_rk3568_inits clk_3568_cru_init = { 1695 .inits = rk3568_clk_init, 1696 }; 1697 1698 static const struct of_device_id clk_rk3568_match_table[] = { 1699 { 1700 .compatible = "rockchip,rk3568-cru", 1701 .data = &clk_3568_cru_init, 1702 }, { 1703 .compatible = "rockchip,rk3568-pmucru", 1704 .data = &clk_rk3568_pmucru_init, 1705 }, 1706 { } 1707 }; 1708 1709 static int __init clk_rk3568_probe(struct platform_device *pdev) 1710 { 1711 struct device_node *np = pdev->dev.of_node; 1712 const struct clk_rk3568_inits *init_data; 1713 1714 init_data = (struct clk_rk3568_inits *)of_device_get_match_data(&pdev->dev); 1715 if (!init_data) 1716 return -EINVAL; 1717 1718 if (init_data->inits) 1719 init_data->inits(np); 1720 1721 return 0; 1722 } 1723 1724 static struct platform_driver clk_rk3568_driver = { 1725 .driver = { 1726 .name = "clk-rk3568", 1727 .of_match_table = clk_rk3568_match_table, 1728 .suppress_bind_attrs = true, 1729 }, 1730 }; 1731 builtin_platform_driver_probe(clk_rk3568_driver, clk_rk3568_probe); 1732