1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2021 Rockchip Electronics Co. Ltd.
4 * Author: Elaine Zhang <zhangqing@rock-chips.com>
5 */
6
7 #include <linux/clk-provider.h>
8 #include <linux/module.h>
9 #include <linux/of.h>
10 #include <linux/of_address.h>
11 #include <linux/platform_device.h>
12 #include <linux/syscore_ops.h>
13 #include <dt-bindings/clock/rk3568-cru.h>
14 #include "clk.h"
15
16 #define RK3568_GRF_SOC_STATUS0 0x580
17
18 enum rk3568_pmu_plls {
19 ppll, hpll,
20 };
21
22 enum rk3568_plls {
23 apll, dpll, gpll, cpll, npll, vpll,
24 };
25
26 static struct rockchip_pll_rate_table rk3568_pll_rates[] = {
27 /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
28 RK3036_PLL_RATE(2208000000, 1, 92, 1, 1, 1, 0),
29 RK3036_PLL_RATE(2184000000, 1, 91, 1, 1, 1, 0),
30 RK3036_PLL_RATE(2160000000, 1, 90, 1, 1, 1, 0),
31 RK3036_PLL_RATE(2088000000, 1, 87, 1, 1, 1, 0),
32 RK3036_PLL_RATE(2064000000, 1, 86, 1, 1, 1, 0),
33 RK3036_PLL_RATE(2040000000, 1, 85, 1, 1, 1, 0),
34 RK3036_PLL_RATE(2016000000, 1, 84, 1, 1, 1, 0),
35 RK3036_PLL_RATE(1992000000, 1, 83, 1, 1, 1, 0),
36 RK3036_PLL_RATE(1920000000, 1, 80, 1, 1, 1, 0),
37 RK3036_PLL_RATE(1896000000, 1, 79, 1, 1, 1, 0),
38 RK3036_PLL_RATE(1800000000, 1, 75, 1, 1, 1, 0),
39 RK3036_PLL_RATE(1704000000, 1, 71, 1, 1, 1, 0),
40 RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0),
41 RK3036_PLL_RATE(1600000000, 3, 200, 1, 1, 1, 0),
42 RK3036_PLL_RATE(1584000000, 1, 132, 2, 1, 1, 0),
43 RK3036_PLL_RATE(1560000000, 1, 130, 2, 1, 1, 0),
44 RK3036_PLL_RATE(1536000000, 1, 128, 2, 1, 1, 0),
45 RK3036_PLL_RATE(1512000000, 1, 126, 2, 1, 1, 0),
46 RK3036_PLL_RATE(1488000000, 1, 124, 2, 1, 1, 0),
47 RK3036_PLL_RATE(1464000000, 1, 122, 2, 1, 1, 0),
48 RK3036_PLL_RATE(1440000000, 1, 120, 2, 1, 1, 0),
49 RK3036_PLL_RATE(1416000000, 1, 118, 2, 1, 1, 0),
50 RK3036_PLL_RATE(1400000000, 3, 350, 2, 1, 1, 0),
51 RK3036_PLL_RATE(1392000000, 1, 116, 2, 1, 1, 0),
52 RK3036_PLL_RATE(1368000000, 1, 114, 2, 1, 1, 0),
53 RK3036_PLL_RATE(1344000000, 1, 112, 2, 1, 1, 0),
54 RK3036_PLL_RATE(1320000000, 1, 110, 2, 1, 1, 0),
55 RK3036_PLL_RATE(1296000000, 1, 108, 2, 1, 1, 0),
56 RK3036_PLL_RATE(1272000000, 1, 106, 2, 1, 1, 0),
57 RK3036_PLL_RATE(1248000000, 1, 104, 2, 1, 1, 0),
58 RK3036_PLL_RATE(1200000000, 1, 100, 2, 1, 1, 0),
59 RK3036_PLL_RATE(1188000000, 1, 99, 2, 1, 1, 0),
60 RK3036_PLL_RATE(1104000000, 1, 92, 2, 1, 1, 0),
61 RK3036_PLL_RATE(1100000000, 3, 275, 2, 1, 1, 0),
62 RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0),
63 RK3036_PLL_RATE(1000000000, 3, 250, 2, 1, 1, 0),
64 RK3036_PLL_RATE(912000000, 1, 76, 2, 1, 1, 0),
65 RK3036_PLL_RATE(816000000, 1, 68, 2, 1, 1, 0),
66 RK3036_PLL_RATE(800000000, 3, 200, 2, 1, 1, 0),
67 RK3036_PLL_RATE(724000000, 3, 181, 2, 1, 1, 0),
68 RK3036_PLL_RATE(700000000, 3, 350, 4, 1, 1, 0),
69 RK3036_PLL_RATE(696000000, 1, 116, 4, 1, 1, 0),
70 RK3036_PLL_RATE(600000000, 1, 100, 4, 1, 1, 0),
71 RK3036_PLL_RATE(594000000, 1, 99, 4, 1, 1, 0),
72 RK3036_PLL_RATE(500000000, 1, 125, 6, 1, 1, 0),
73 RK3036_PLL_RATE(408000000, 1, 68, 2, 2, 1, 0),
74 RK3036_PLL_RATE(312000000, 1, 78, 6, 1, 1, 0),
75 RK3036_PLL_RATE(297000000, 2, 99, 4, 1, 1, 0),
76 RK3036_PLL_RATE(292500000, 1, 195, 4, 4, 1, 0),
77 RK3036_PLL_RATE(241500000, 2, 161, 4, 2, 1, 0),
78 RK3036_PLL_RATE(216000000, 1, 72, 4, 2, 1, 0),
79 RK3036_PLL_RATE(200000000, 1, 100, 3, 4, 1, 0),
80 RK3036_PLL_RATE(148500000, 1, 99, 4, 4, 1, 0),
81 RK3036_PLL_RATE(135000000, 2, 45, 4, 1, 1, 0),
82 RK3036_PLL_RATE(128000000, 1, 16, 3, 1, 1, 0),
83 RK3036_PLL_RATE(126400000, 1, 79, 5, 3, 1, 0),
84 RK3036_PLL_RATE(119000000, 3, 119, 4, 2, 1, 0),
85 RK3036_PLL_RATE(115200000, 1, 24, 5, 1, 1, 0),
86 RK3036_PLL_RATE(108000000, 2, 45, 5, 1, 1, 0),
87 RK3036_PLL_RATE(101000000, 1, 101, 6, 4, 1, 0),
88 RK3036_PLL_RATE(100000000, 1, 150, 6, 6, 1, 0),
89 RK3036_PLL_RATE(96000000, 1, 96, 6, 4, 1, 0),
90 RK3036_PLL_RATE(78750000, 4, 315, 6, 4, 1, 0),
91 RK3036_PLL_RATE(74250000, 2, 99, 4, 4, 1, 0),
92 { /* sentinel */ },
93 };
94
95 #define RK3568_DIV_ATCLK_CORE_MASK 0x1f
96 #define RK3568_DIV_ATCLK_CORE_SHIFT 0
97 #define RK3568_DIV_GICCLK_CORE_MASK 0x1f
98 #define RK3568_DIV_GICCLK_CORE_SHIFT 8
99 #define RK3568_DIV_PCLK_CORE_MASK 0x1f
100 #define RK3568_DIV_PCLK_CORE_SHIFT 0
101 #define RK3568_DIV_PERIPHCLK_CORE_MASK 0x1f
102 #define RK3568_DIV_PERIPHCLK_CORE_SHIFT 8
103 #define RK3568_DIV_ACLK_CORE_MASK 0x1f
104 #define RK3568_DIV_ACLK_CORE_SHIFT 8
105
106 #define RK3568_DIV_SCLK_CORE_MASK 0xf
107 #define RK3568_DIV_SCLK_CORE_SHIFT 0
108 #define RK3568_MUX_SCLK_CORE_MASK 0x3
109 #define RK3568_MUX_SCLK_CORE_SHIFT 8
110 #define RK3568_MUX_SCLK_CORE_NPLL_MASK 0x1
111 #define RK3568_MUX_SCLK_CORE_NPLL_SHIFT 15
112 #define RK3568_MUX_CLK_CORE_APLL_MASK 0x1
113 #define RK3568_MUX_CLK_CORE_APLL_SHIFT 7
114 #define RK3568_MUX_CLK_PVTPLL_MASK 0x1
115 #define RK3568_MUX_CLK_PVTPLL_SHIFT 15
116
117 #define RK3568_CLKSEL1(_sclk_core) \
118 { \
119 .reg = RK3568_CLKSEL_CON(2), \
120 .val = HIWORD_UPDATE(_sclk_core, RK3568_MUX_SCLK_CORE_NPLL_MASK, \
121 RK3568_MUX_SCLK_CORE_NPLL_SHIFT) | \
122 HIWORD_UPDATE(_sclk_core, RK3568_MUX_SCLK_CORE_MASK, \
123 RK3568_MUX_SCLK_CORE_SHIFT) | \
124 HIWORD_UPDATE(1, RK3568_DIV_SCLK_CORE_MASK, \
125 RK3568_DIV_SCLK_CORE_SHIFT), \
126 }
127
128 #define RK3568_CLKSEL2(_aclk_core) \
129 { \
130 .reg = RK3568_CLKSEL_CON(5), \
131 .val = HIWORD_UPDATE(_aclk_core, RK3568_DIV_ACLK_CORE_MASK, \
132 RK3568_DIV_ACLK_CORE_SHIFT), \
133 }
134
135 #define RK3568_CLKSEL3(_atclk_core, _gic_core) \
136 { \
137 .reg = RK3568_CLKSEL_CON(3), \
138 .val = HIWORD_UPDATE(_atclk_core, RK3568_DIV_ATCLK_CORE_MASK, \
139 RK3568_DIV_ATCLK_CORE_SHIFT) | \
140 HIWORD_UPDATE(_gic_core, RK3568_DIV_GICCLK_CORE_MASK, \
141 RK3568_DIV_GICCLK_CORE_SHIFT), \
142 }
143
144 #define RK3568_CLKSEL4(_pclk_core, _periph_core) \
145 { \
146 .reg = RK3568_CLKSEL_CON(4), \
147 .val = HIWORD_UPDATE(_pclk_core, RK3568_DIV_PCLK_CORE_MASK, \
148 RK3568_DIV_PCLK_CORE_SHIFT) | \
149 HIWORD_UPDATE(_periph_core, RK3568_DIV_PERIPHCLK_CORE_MASK, \
150 RK3568_DIV_PERIPHCLK_CORE_SHIFT), \
151 }
152
153 #define RK3568_CPUCLK_RATE(_prate, _sclk, _acore, _atcore, _gicclk, _pclk, _periph) \
154 { \
155 .prate = _prate##U, \
156 .divs = { \
157 RK3568_CLKSEL1(_sclk), \
158 RK3568_CLKSEL2(_acore), \
159 RK3568_CLKSEL3(_atcore, _gicclk), \
160 RK3568_CLKSEL4(_pclk, _periph), \
161 }, \
162 }
163
164 static struct rockchip_cpuclk_rate_table rk3568_cpuclk_rates[] __initdata = {
165 RK3568_CPUCLK_RATE(1800000000, 0, 1, 7, 7, 7, 7),
166 RK3568_CPUCLK_RATE(1704000000, 0, 1, 7, 7, 7, 7),
167 RK3568_CPUCLK_RATE(1608000000, 0, 1, 5, 5, 5, 5),
168 RK3568_CPUCLK_RATE(1584000000, 0, 1, 5, 5, 5, 5),
169 RK3568_CPUCLK_RATE(1560000000, 0, 1, 5, 5, 5, 5),
170 RK3568_CPUCLK_RATE(1536000000, 0, 1, 5, 5, 5, 5),
171 RK3568_CPUCLK_RATE(1512000000, 0, 1, 5, 5, 5, 5),
172 RK3568_CPUCLK_RATE(1488000000, 0, 1, 5, 5, 5, 5),
173 RK3568_CPUCLK_RATE(1464000000, 0, 1, 5, 5, 5, 5),
174 RK3568_CPUCLK_RATE(1440000000, 0, 1, 5, 5, 5, 5),
175 RK3568_CPUCLK_RATE(1416000000, 0, 1, 5, 5, 5, 5),
176 RK3568_CPUCLK_RATE(1392000000, 0, 1, 5, 5, 5, 5),
177 RK3568_CPUCLK_RATE(1368000000, 0, 1, 5, 5, 5, 5),
178 RK3568_CPUCLK_RATE(1344000000, 0, 1, 5, 5, 5, 5),
179 RK3568_CPUCLK_RATE(1320000000, 0, 1, 5, 5, 5, 5),
180 RK3568_CPUCLK_RATE(1296000000, 0, 1, 5, 5, 5, 5),
181 RK3568_CPUCLK_RATE(1272000000, 0, 1, 5, 5, 5, 5),
182 RK3568_CPUCLK_RATE(1248000000, 0, 1, 5, 5, 5, 5),
183 RK3568_CPUCLK_RATE(1224000000, 0, 1, 5, 5, 5, 5),
184 RK3568_CPUCLK_RATE(1200000000, 0, 1, 3, 3, 3, 3),
185 RK3568_CPUCLK_RATE(1104000000, 0, 1, 3, 3, 3, 3),
186 RK3568_CPUCLK_RATE(1008000000, 0, 1, 3, 3, 3, 3),
187 RK3568_CPUCLK_RATE(912000000, 0, 1, 3, 3, 3, 3),
188 RK3568_CPUCLK_RATE(816000000, 0, 1, 3, 3, 3, 3),
189 RK3568_CPUCLK_RATE(696000000, 0, 1, 3, 3, 3, 3),
190 RK3568_CPUCLK_RATE(600000000, 0, 1, 3, 3, 3, 3),
191 RK3568_CPUCLK_RATE(408000000, 0, 1, 3, 3, 3, 3),
192 RK3568_CPUCLK_RATE(312000000, 0, 1, 3, 3, 3, 3),
193 RK3568_CPUCLK_RATE(216000000, 0, 1, 3, 3, 3, 3),
194 RK3568_CPUCLK_RATE(96000000, 0, 1, 3, 3, 3, 3),
195 };
196
197 static const struct rockchip_cpuclk_reg_data rk3568_cpuclk_data = {
198 .core_reg[0] = RK3568_CLKSEL_CON(0),
199 .div_core_shift[0] = 0,
200 .div_core_mask[0] = 0x1f,
201 .core_reg[1] = RK3568_CLKSEL_CON(0),
202 .div_core_shift[1] = 8,
203 .div_core_mask[1] = 0x1f,
204 .core_reg[2] = RK3568_CLKSEL_CON(1),
205 .div_core_shift[2] = 0,
206 .div_core_mask[2] = 0x1f,
207 .core_reg[3] = RK3568_CLKSEL_CON(1),
208 .div_core_shift[3] = 8,
209 .div_core_mask[3] = 0x1f,
210 .num_cores = 4,
211 .mux_core_alt = 1,
212 .mux_core_main = 0,
213 .mux_core_shift = 6,
214 .mux_core_mask = 0x1,
215 };
216
217 PNAME(mux_pll_p) = { "xin24m" };
218 PNAME(mux_usb480m_p) = { "xin24m", "usb480m_phy", "clk_rtc_32k" };
219 PNAME(mux_usb480m_phy_p) = { "clk_usbphy0_480m", "clk_usbphy1_480m"};
220 PNAME(mux_armclk_p) = { "apll", "gpll" };
221 PNAME(clk_i2s0_8ch_tx_p) = { "clk_i2s0_8ch_tx_src", "clk_i2s0_8ch_tx_frac", "i2s0_mclkin", "xin_osc0_half" };
222 PNAME(clk_i2s0_8ch_rx_p) = { "clk_i2s0_8ch_rx_src", "clk_i2s0_8ch_rx_frac", "i2s0_mclkin", "xin_osc0_half" };
223 PNAME(clk_i2s1_8ch_tx_p) = { "clk_i2s1_8ch_tx_src", "clk_i2s1_8ch_tx_frac", "i2s1_mclkin", "xin_osc0_half" };
224 PNAME(clk_i2s1_8ch_rx_p) = { "clk_i2s1_8ch_rx_src", "clk_i2s1_8ch_rx_frac", "i2s1_mclkin", "xin_osc0_half" };
225 PNAME(clk_i2s2_2ch_p) = { "clk_i2s2_2ch_src", "clk_i2s2_2ch_frac", "i2s2_mclkin", "xin_osc0_half "};
226 PNAME(clk_i2s3_2ch_tx_p) = { "clk_i2s3_2ch_tx_src", "clk_i2s3_2ch_tx_frac", "i2s3_mclkin", "xin_osc0_half" };
227 PNAME(clk_i2s3_2ch_rx_p) = { "clk_i2s3_2ch_rx_src", "clk_i2s3_2ch_rx_frac", "i2s3_mclkin", "xin_osc0_half" };
228 PNAME(mclk_spdif_8ch_p) = { "mclk_spdif_8ch_src", "mclk_spdif_8ch_frac" };
229 PNAME(sclk_audpwm_p) = { "sclk_audpwm_src", "sclk_audpwm_frac" };
230 PNAME(sclk_uart1_p) = { "clk_uart1_src", "clk_uart1_frac", "xin24m" };
231 PNAME(sclk_uart2_p) = { "clk_uart2_src", "clk_uart2_frac", "xin24m" };
232 PNAME(sclk_uart3_p) = { "clk_uart3_src", "clk_uart3_frac", "xin24m" };
233 PNAME(sclk_uart4_p) = { "clk_uart4_src", "clk_uart4_frac", "xin24m" };
234 PNAME(sclk_uart5_p) = { "clk_uart5_src", "clk_uart5_frac", "xin24m" };
235 PNAME(sclk_uart6_p) = { "clk_uart6_src", "clk_uart6_frac", "xin24m" };
236 PNAME(sclk_uart7_p) = { "clk_uart7_src", "clk_uart7_frac", "xin24m" };
237 PNAME(sclk_uart8_p) = { "clk_uart8_src", "clk_uart8_frac", "xin24m" };
238 PNAME(sclk_uart9_p) = { "clk_uart9_src", "clk_uart9_frac", "xin24m" };
239 PNAME(sclk_uart0_p) = { "sclk_uart0_div", "sclk_uart0_frac", "xin24m" };
240 PNAME(clk_rtc32k_pmu_p) = { "clk_32k_pvtm", "xin32k", "clk_rtc32k_frac" };
241 PNAME(mpll_gpll_cpll_npll_p) = { "mpll", "gpll", "cpll", "npll" };
242 PNAME(gpll_cpll_npll_p) = { "gpll", "cpll", "npll" };
243 PNAME(npll_gpll_p) = { "npll", "gpll" };
244 PNAME(cpll_gpll_p) = { "cpll", "gpll" };
245 PNAME(gpll_cpll_p) = { "gpll", "cpll" };
246 PNAME(gpll_cpll_npll_vpll_p) = { "gpll", "cpll", "npll", "vpll" };
247 PNAME(apll_gpll_npll_p) = { "apll", "gpll", "npll" };
248 PNAME(sclk_core_pre_p) = { "sclk_core_src", "npll" };
249 PNAME(gpll150_gpll100_gpll75_xin24m_p) = { "gpll_150m", "gpll_100m", "gpll_75m", "xin24m" };
250 PNAME(clk_gpu_pre_mux_p) = { "clk_gpu_src", "gpu_pvtpll_out" };
251 PNAME(clk_npu_pre_ndft_p) = { "clk_npu_src", "dummy"};
252 PNAME(clk_npu_p) = { "clk_npu_pre_ndft", "npu_pvtpll_out" };
253 PNAME(dpll_gpll_cpll_p) = { "dpll", "gpll", "cpll" };
254 PNAME(clk_ddr1x_p) = { "clk_ddrphy1x_src", "dpll" };
255 PNAME(gpll200_gpll150_gpll100_xin24m_p) = { "gpll_200m", "gpll_150m", "gpll_100m", "xin24m" };
256 PNAME(gpll100_gpll75_gpll50_p) = { "gpll_100m", "gpll_75m", "cpll_50m" };
257 PNAME(i2s0_mclkout_tx_p) = { "clk_i2s0_8ch_tx", "xin_osc0_half" };
258 PNAME(i2s0_mclkout_rx_p) = { "clk_i2s0_8ch_rx", "xin_osc0_half" };
259 PNAME(i2s1_mclkout_tx_p) = { "clk_i2s1_8ch_tx", "xin_osc0_half" };
260 PNAME(i2s1_mclkout_rx_p) = { "clk_i2s1_8ch_rx", "xin_osc0_half" };
261 PNAME(i2s2_mclkout_p) = { "clk_i2s2_2ch", "xin_osc0_half" };
262 PNAME(i2s3_mclkout_tx_p) = { "clk_i2s3_2ch_tx", "xin_osc0_half" };
263 PNAME(i2s3_mclkout_rx_p) = { "clk_i2s3_2ch_rx", "xin_osc0_half" };
264 PNAME(mclk_pdm_p) = { "gpll_300m", "cpll_250m", "gpll_200m", "gpll_100m" };
265 PNAME(clk_i2c_p) = { "gpll_200m", "gpll_100m", "xin24m", "cpll_100m" };
266 PNAME(gpll200_gpll150_gpll100_p) = { "gpll_200m", "gpll_150m", "gpll_100m" };
267 PNAME(gpll300_gpll200_gpll100_p) = { "gpll_300m", "gpll_200m", "gpll_100m" };
268 PNAME(clk_nandc_p) = { "gpll_200m", "gpll_150m", "cpll_100m", "xin24m" };
269 PNAME(sclk_sfc_p) = { "xin24m", "cpll_50m", "gpll_75m", "gpll_100m", "cpll_125m", "gpll_150m" };
270 PNAME(gpll200_gpll150_cpll125_p) = { "gpll_200m", "gpll_150m", "cpll_125m" };
271 PNAME(cclk_emmc_p) = { "xin24m", "gpll_200m", "gpll_150m", "cpll_100m", "cpll_50m", "clk_osc0_div_375k" };
272 PNAME(aclk_pipe_p) = { "gpll_400m", "gpll_300m", "gpll_200m", "xin24m" };
273 PNAME(gpll200_cpll125_p) = { "gpll_200m", "cpll_125m" };
274 PNAME(gpll300_gpll200_gpll100_xin24m_p) = { "gpll_300m", "gpll_200m", "gpll_100m", "xin24m" };
275 PNAME(clk_sdmmc_p) = { "xin24m", "gpll_400m", "gpll_300m", "cpll_100m", "cpll_50m", "clk_osc0_div_750k" };
276 PNAME(cpll125_cpll50_cpll25_xin24m_p) = { "cpll_125m", "cpll_50m", "cpll_25m", "xin24m" };
277 PNAME(clk_gmac_ptp_p) = { "cpll_62p5", "gpll_100m", "cpll_50m", "xin24m" };
278 PNAME(cpll333_gpll300_gpll200_p) = { "cpll_333m", "gpll_300m", "gpll_200m" };
279 PNAME(cpll_gpll_hpll_p) = { "cpll", "gpll", "hpll" };
280 PNAME(gpll_usb480m_xin24m_p) = { "gpll", "usb480m", "xin24m", "xin24m" };
281 PNAME(gpll300_cpll250_gpll100_xin24m_p) = { "gpll_300m", "cpll_250m", "gpll_100m", "xin24m" };
282 PNAME(cpll_gpll_hpll_vpll_p) = { "cpll", "gpll", "hpll", "vpll" };
283 PNAME(hpll_vpll_gpll_cpll_p) = { "hpll", "vpll", "gpll", "cpll" };
284 PNAME(gpll400_cpll333_gpll200_p) = { "gpll_400m", "cpll_333m", "gpll_200m" };
285 PNAME(gpll100_gpll75_cpll50_xin24m_p) = { "gpll_100m", "gpll_75m", "cpll_50m", "xin24m" };
286 PNAME(xin24m_gpll100_cpll100_p) = { "xin24m", "gpll_100m", "cpll_100m" };
287 PNAME(gpll_cpll_usb480m_p) = { "gpll", "cpll", "usb480m" };
288 PNAME(gpll100_xin24m_cpll100_p) = { "gpll_100m", "xin24m", "cpll_100m" };
289 PNAME(gpll200_xin24m_cpll100_p) = { "gpll_200m", "xin24m", "cpll_100m" };
290 PNAME(xin24m_32k_p) = { "xin24m", "clk_rtc_32k" };
291 PNAME(cpll500_gpll400_gpll300_xin24m_p) = { "cpll_500m", "gpll_400m", "gpll_300m", "xin24m" };
292 PNAME(gpll400_gpll300_gpll200_xin24m_p) = { "gpll_400m", "gpll_300m", "gpll_200m", "xin24m" };
293 PNAME(xin24m_cpll100_p) = { "xin24m", "cpll_100m" };
294 PNAME(ppll_usb480m_cpll_gpll_p) = { "ppll", "usb480m", "cpll", "gpll"};
295 PNAME(clk_usbphy0_ref_p) = { "clk_ref24m", "xin_osc0_usbphy0_g" };
296 PNAME(clk_usbphy1_ref_p) = { "clk_ref24m", "xin_osc0_usbphy1_g" };
297 PNAME(clk_mipidsiphy0_ref_p) = { "clk_ref24m", "xin_osc0_mipidsiphy0_g" };
298 PNAME(clk_mipidsiphy1_ref_p) = { "clk_ref24m", "xin_osc0_mipidsiphy1_g" };
299 PNAME(clk_wifi_p) = { "clk_wifi_osc0", "clk_wifi_div" };
300 PNAME(clk_pciephy0_ref_p) = { "clk_pciephy0_osc0", "clk_pciephy0_div" };
301 PNAME(clk_pciephy1_ref_p) = { "clk_pciephy1_osc0", "clk_pciephy1_div" };
302 PNAME(clk_pciephy2_ref_p) = { "clk_pciephy2_osc0", "clk_pciephy2_div" };
303 PNAME(mux_gmac0_p) = { "clk_mac0_2top", "gmac0_clkin" };
304 PNAME(mux_gmac0_rgmii_speed_p) = { "clk_gmac0", "clk_gmac0", "clk_gmac0_tx_div50", "clk_gmac0_tx_div5" };
305 PNAME(mux_gmac0_rmii_speed_p) = { "clk_gmac0_rx_div20", "clk_gmac0_rx_div2" };
306 PNAME(mux_gmac0_rx_tx_p) = { "clk_gmac0_rgmii_speed", "clk_gmac0_rmii_speed", "clk_gmac0_xpcs_mii" };
307 PNAME(mux_gmac1_p) = { "clk_mac1_2top", "gmac1_clkin" };
308 PNAME(mux_gmac1_rgmii_speed_p) = { "clk_gmac1", "clk_gmac1", "clk_gmac1_tx_div50", "clk_gmac1_tx_div5" };
309 PNAME(mux_gmac1_rmii_speed_p) = { "clk_gmac1_rx_div20", "clk_gmac1_rx_div2" };
310 PNAME(mux_gmac1_rx_tx_p) = { "clk_gmac1_rgmii_speed", "clk_gmac1_rmii_speed", "clk_gmac1_xpcs_mii" };
311 PNAME(clk_hdmi_ref_p) = { "hpll", "hpll_ph0" };
312 PNAME(clk_pdpmu_p) = { "ppll", "gpll" };
313 PNAME(clk_mac_2top_p) = { "cpll_125m", "cpll_50m", "cpll_25m", "ppll" };
314 PNAME(clk_pwm0_p) = { "xin24m", "clk_pdpmu" };
315 PNAME(aclk_rkvdec_pre_p) = { "gpll", "cpll" };
316 PNAME(clk_rkvdec_core_p) = { "gpll", "cpll", "dummy_npll", "dummy_vpll" };
317
318 static struct rockchip_pll_clock rk3568_pmu_pll_clks[] __initdata = {
319 [ppll] = PLL(pll_rk3328, PLL_PPLL, "ppll", mux_pll_p,
320 0, RK3568_PMU_PLL_CON(0),
321 RK3568_PMU_MODE_CON0, 0, 4, 0, rk3568_pll_rates),
322 [hpll] = PLL(pll_rk3328, PLL_HPLL, "hpll", mux_pll_p,
323 0, RK3568_PMU_PLL_CON(16),
324 RK3568_PMU_MODE_CON0, 2, 7, 0, rk3568_pll_rates),
325 };
326
327 static struct rockchip_pll_clock rk3568_pll_clks[] __initdata = {
328 [apll] = PLL(pll_rk3328, PLL_APLL, "apll", mux_pll_p,
329 0, RK3568_PLL_CON(0),
330 RK3568_MODE_CON0, 0, 0, 0, rk3568_pll_rates),
331 [dpll] = PLL(pll_rk3328, PLL_DPLL, "dpll", mux_pll_p,
332 0, RK3568_PLL_CON(8),
333 RK3568_MODE_CON0, 2, 1, 0, NULL),
334 [cpll] = PLL(pll_rk3328, PLL_CPLL, "cpll", mux_pll_p,
335 0, RK3568_PLL_CON(24),
336 RK3568_MODE_CON0, 4, 2, 0, rk3568_pll_rates),
337 [gpll] = PLL(pll_rk3328, PLL_GPLL, "gpll", mux_pll_p,
338 0, RK3568_PLL_CON(16),
339 RK3568_MODE_CON0, 6, 3, 0, rk3568_pll_rates),
340 [npll] = PLL(pll_rk3328, PLL_NPLL, "npll", mux_pll_p,
341 0, RK3568_PLL_CON(32),
342 RK3568_MODE_CON0, 10, 5, 0, rk3568_pll_rates),
343 [vpll] = PLL(pll_rk3328, PLL_VPLL, "vpll", mux_pll_p,
344 0, RK3568_PLL_CON(40),
345 RK3568_MODE_CON0, 12, 6, 0, rk3568_pll_rates),
346 };
347
348 #define MFLAGS CLK_MUX_HIWORD_MASK
349 #define DFLAGS CLK_DIVIDER_HIWORD_MASK
350 #define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
351
352 static struct rockchip_clk_branch rk3568_i2s0_8ch_tx_fracmux __initdata =
353 MUX(CLK_I2S0_8CH_TX, "clk_i2s0_8ch_tx", clk_i2s0_8ch_tx_p, CLK_SET_RATE_PARENT,
354 RK3568_CLKSEL_CON(11), 10, 2, MFLAGS);
355
356 static struct rockchip_clk_branch rk3568_i2s0_8ch_rx_fracmux __initdata =
357 MUX(CLK_I2S0_8CH_RX, "clk_i2s0_8ch_rx", clk_i2s0_8ch_rx_p, CLK_SET_RATE_PARENT,
358 RK3568_CLKSEL_CON(13), 10, 2, MFLAGS);
359
360 static struct rockchip_clk_branch rk3568_i2s1_8ch_tx_fracmux __initdata =
361 MUX(CLK_I2S1_8CH_TX, "clk_i2s1_8ch_tx", clk_i2s1_8ch_tx_p, CLK_SET_RATE_PARENT,
362 RK3568_CLKSEL_CON(15), 10, 2, MFLAGS);
363
364 static struct rockchip_clk_branch rk3568_i2s1_8ch_rx_fracmux __initdata =
365 MUX(CLK_I2S1_8CH_RX, "clk_i2s1_8ch_rx", clk_i2s1_8ch_rx_p, CLK_SET_RATE_PARENT,
366 RK3568_CLKSEL_CON(17), 10, 2, MFLAGS);
367
368 static struct rockchip_clk_branch rk3568_i2s2_2ch_fracmux __initdata =
369 MUX(CLK_I2S2_2CH, "clk_i2s2_2ch", clk_i2s2_2ch_p, CLK_SET_RATE_PARENT,
370 RK3568_CLKSEL_CON(19), 10, 2, MFLAGS);
371
372 static struct rockchip_clk_branch rk3568_i2s3_2ch_tx_fracmux __initdata =
373 MUX(CLK_I2S3_2CH_TX, "clk_i2s3_2ch_tx", clk_i2s3_2ch_tx_p, CLK_SET_RATE_PARENT,
374 RK3568_CLKSEL_CON(21), 10, 2, MFLAGS);
375
376 static struct rockchip_clk_branch rk3568_i2s3_2ch_rx_fracmux __initdata =
377 MUX(CLK_I2S3_2CH_RX, "clk_i2s3_2ch_rx", clk_i2s3_2ch_rx_p, CLK_SET_RATE_PARENT,
378 RK3568_CLKSEL_CON(83), 10, 2, MFLAGS);
379
380 static struct rockchip_clk_branch rk3568_spdif_8ch_fracmux __initdata =
381 MUX(MCLK_SPDIF_8CH, "mclk_spdif_8ch", mclk_spdif_8ch_p, CLK_SET_RATE_PARENT,
382 RK3568_CLKSEL_CON(23), 15, 1, MFLAGS);
383
384 static struct rockchip_clk_branch rk3568_audpwm_fracmux __initdata =
385 MUX(SCLK_AUDPWM, "sclk_audpwm", sclk_audpwm_p, CLK_SET_RATE_PARENT,
386 RK3568_CLKSEL_CON(25), 15, 1, MFLAGS);
387
388 static struct rockchip_clk_branch rk3568_uart1_fracmux __initdata =
389 MUX(0, "sclk_uart1_mux", sclk_uart1_p, CLK_SET_RATE_PARENT,
390 RK3568_CLKSEL_CON(52), 12, 2, MFLAGS);
391
392 static struct rockchip_clk_branch rk3568_uart2_fracmux __initdata =
393 MUX(0, "sclk_uart2_mux", sclk_uart2_p, CLK_SET_RATE_PARENT,
394 RK3568_CLKSEL_CON(54), 12, 2, MFLAGS);
395
396 static struct rockchip_clk_branch rk3568_uart3_fracmux __initdata =
397 MUX(0, "sclk_uart3_mux", sclk_uart3_p, CLK_SET_RATE_PARENT,
398 RK3568_CLKSEL_CON(56), 12, 2, MFLAGS);
399
400 static struct rockchip_clk_branch rk3568_uart4_fracmux __initdata =
401 MUX(0, "sclk_uart4_mux", sclk_uart4_p, CLK_SET_RATE_PARENT,
402 RK3568_CLKSEL_CON(58), 12, 2, MFLAGS);
403
404 static struct rockchip_clk_branch rk3568_uart5_fracmux __initdata =
405 MUX(0, "sclk_uart5_mux", sclk_uart5_p, CLK_SET_RATE_PARENT,
406 RK3568_CLKSEL_CON(60), 12, 2, MFLAGS);
407
408 static struct rockchip_clk_branch rk3568_uart6_fracmux __initdata =
409 MUX(0, "sclk_uart6_mux", sclk_uart6_p, CLK_SET_RATE_PARENT,
410 RK3568_CLKSEL_CON(62), 12, 2, MFLAGS);
411
412 static struct rockchip_clk_branch rk3568_uart7_fracmux __initdata =
413 MUX(0, "sclk_uart7_mux", sclk_uart7_p, CLK_SET_RATE_PARENT,
414 RK3568_CLKSEL_CON(64), 12, 2, MFLAGS);
415
416 static struct rockchip_clk_branch rk3568_uart8_fracmux __initdata =
417 MUX(0, "sclk_uart8_mux", sclk_uart8_p, CLK_SET_RATE_PARENT,
418 RK3568_CLKSEL_CON(66), 12, 2, MFLAGS);
419
420 static struct rockchip_clk_branch rk3568_uart9_fracmux __initdata =
421 MUX(0, "sclk_uart9_mux", sclk_uart9_p, CLK_SET_RATE_PARENT,
422 RK3568_CLKSEL_CON(68), 12, 2, MFLAGS);
423
424 static struct rockchip_clk_branch rk3568_uart0_fracmux __initdata =
425 MUX(0, "sclk_uart0_mux", sclk_uart0_p, CLK_SET_RATE_PARENT,
426 RK3568_PMU_CLKSEL_CON(4), 10, 2, MFLAGS);
427
428 static struct rockchip_clk_branch rk3568_rtc32k_pmu_fracmux __initdata =
429 MUX(CLK_RTC_32K, "clk_rtc_32k", clk_rtc32k_pmu_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
430 RK3568_PMU_CLKSEL_CON(0), 6, 2, MFLAGS);
431
432 static struct rockchip_clk_branch rk3568_clk_branches[] __initdata = {
433 /*
434 * Clock-Architecture Diagram 1
435 */
436 /* SRC_CLK */
437 COMPOSITE_NOMUX(0, "gpll_400m", "gpll", CLK_IGNORE_UNUSED,
438 RK3568_CLKSEL_CON(75), 0, 5, DFLAGS,
439 RK3568_CLKGATE_CON(35), 0, GFLAGS),
440 COMPOSITE_NOMUX(0, "gpll_300m", "gpll", CLK_IGNORE_UNUSED,
441 RK3568_CLKSEL_CON(75), 8, 5, DFLAGS,
442 RK3568_CLKGATE_CON(35), 1, GFLAGS),
443 COMPOSITE_NOMUX(0, "gpll_200m", "gpll", CLK_IGNORE_UNUSED,
444 RK3568_CLKSEL_CON(76), 0, 5, DFLAGS,
445 RK3568_CLKGATE_CON(35), 2, GFLAGS),
446 COMPOSITE_NOMUX(0, "gpll_150m", "gpll", CLK_IGNORE_UNUSED,
447 RK3568_CLKSEL_CON(76), 8, 5, DFLAGS,
448 RK3568_CLKGATE_CON(35), 3, GFLAGS),
449 COMPOSITE_NOMUX(0, "gpll_100m", "gpll", CLK_IGNORE_UNUSED,
450 RK3568_CLKSEL_CON(77), 0, 5, DFLAGS,
451 RK3568_CLKGATE_CON(35), 4, GFLAGS),
452 COMPOSITE_NOMUX(0, "gpll_75m", "gpll", CLK_IGNORE_UNUSED,
453 RK3568_CLKSEL_CON(77), 8, 5, DFLAGS,
454 RK3568_CLKGATE_CON(35), 5, GFLAGS),
455 COMPOSITE_NOMUX(0, "gpll_20m", "gpll", CLK_IGNORE_UNUSED,
456 RK3568_CLKSEL_CON(78), 0, 6, DFLAGS,
457 RK3568_CLKGATE_CON(35), 6, GFLAGS),
458 COMPOSITE_NOMUX(CPLL_500M, "cpll_500m", "cpll", CLK_IGNORE_UNUSED,
459 RK3568_CLKSEL_CON(78), 8, 5, DFLAGS,
460 RK3568_CLKGATE_CON(35), 7, GFLAGS),
461 COMPOSITE_NOMUX(CPLL_333M, "cpll_333m", "cpll", CLK_IGNORE_UNUSED,
462 RK3568_CLKSEL_CON(79), 0, 5, DFLAGS,
463 RK3568_CLKGATE_CON(35), 8, GFLAGS),
464 COMPOSITE_NOMUX(CPLL_250M, "cpll_250m", "cpll", CLK_IGNORE_UNUSED,
465 RK3568_CLKSEL_CON(79), 8, 5, DFLAGS,
466 RK3568_CLKGATE_CON(35), 9, GFLAGS),
467 COMPOSITE_NOMUX(CPLL_125M, "cpll_125m", "cpll", CLK_IGNORE_UNUSED,
468 RK3568_CLKSEL_CON(80), 0, 5, DFLAGS,
469 RK3568_CLKGATE_CON(35), 10, GFLAGS),
470 COMPOSITE_NOMUX(CPLL_100M, "cpll_100m", "cpll", CLK_IGNORE_UNUSED,
471 RK3568_CLKSEL_CON(82), 0, 5, DFLAGS,
472 RK3568_CLKGATE_CON(35), 11, GFLAGS),
473 COMPOSITE_NOMUX(CPLL_62P5M, "cpll_62p5", "cpll", CLK_IGNORE_UNUSED,
474 RK3568_CLKSEL_CON(80), 8, 5, DFLAGS,
475 RK3568_CLKGATE_CON(35), 12, GFLAGS),
476 COMPOSITE_NOMUX(CPLL_50M, "cpll_50m", "cpll", CLK_IGNORE_UNUSED,
477 RK3568_CLKSEL_CON(81), 0, 5, DFLAGS,
478 RK3568_CLKGATE_CON(35), 13, GFLAGS),
479 COMPOSITE_NOMUX(CPLL_25M, "cpll_25m", "cpll", CLK_IGNORE_UNUSED,
480 RK3568_CLKSEL_CON(81), 8, 6, DFLAGS,
481 RK3568_CLKGATE_CON(35), 14, GFLAGS),
482 COMPOSITE_NOMUX(0, "clk_osc0_div_750k", "xin24m", CLK_IGNORE_UNUSED,
483 RK3568_CLKSEL_CON(82), 8, 6, DFLAGS,
484 RK3568_CLKGATE_CON(35), 15, GFLAGS),
485 FACTOR(0, "clk_osc0_div_375k", "clk_osc0_div_750k", 0, 1, 2),
486 FACTOR(0, "xin_osc0_half", "xin24m", 0, 1, 2),
487 MUX(USB480M, "usb480m", mux_usb480m_p, CLK_SET_RATE_PARENT,
488 RK3568_MODE_CON0, 14, 2, MFLAGS),
489
490 MUX(USB480M_PHY, "usb480m_phy", mux_usb480m_phy_p, CLK_SET_RATE_PARENT,
491 RK3568_MISC_CON2, 15, 1, MFLAGS),
492
493 /* PD_CORE */
494 COMPOSITE(0, "sclk_core_src", apll_gpll_npll_p, CLK_IGNORE_UNUSED,
495 RK3568_CLKSEL_CON(2), 8, 2, MFLAGS, 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
496 RK3568_CLKGATE_CON(0), 5, GFLAGS),
497 COMPOSITE_NODIV(0, "sclk_core", sclk_core_pre_p, CLK_IGNORE_UNUSED,
498 RK3568_CLKSEL_CON(2), 15, 1, MFLAGS,
499 RK3568_CLKGATE_CON(0), 7, GFLAGS),
500
501 COMPOSITE_NOMUX(0, "atclk_core", "armclk", CLK_IGNORE_UNUSED,
502 RK3568_CLKSEL_CON(3), 0, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
503 RK3568_CLKGATE_CON(0), 8, GFLAGS),
504 COMPOSITE_NOMUX(0, "gicclk_core", "armclk", CLK_IGNORE_UNUSED,
505 RK3568_CLKSEL_CON(3), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
506 RK3568_CLKGATE_CON(0), 9, GFLAGS),
507 COMPOSITE_NOMUX(0, "pclk_core_pre", "armclk", CLK_IGNORE_UNUSED,
508 RK3568_CLKSEL_CON(4), 0, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
509 RK3568_CLKGATE_CON(0), 10, GFLAGS),
510 COMPOSITE_NOMUX(0, "periphclk_core_pre", "armclk", CLK_IGNORE_UNUSED,
511 RK3568_CLKSEL_CON(4), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
512 RK3568_CLKGATE_CON(0), 11, GFLAGS),
513 COMPOSITE_NOMUX(0, "tsclk_core", "periphclk_core_pre", CLK_IGNORE_UNUSED,
514 RK3568_CLKSEL_CON(5), 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
515 RK3568_CLKGATE_CON(0), 14, GFLAGS),
516 COMPOSITE_NOMUX(0, "cntclk_core", "periphclk_core_pre", CLK_IGNORE_UNUSED,
517 RK3568_CLKSEL_CON(5), 4, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
518 RK3568_CLKGATE_CON(0), 15, GFLAGS),
519 COMPOSITE_NOMUX(0, "aclk_core", "sclk_core", CLK_IGNORE_UNUSED,
520 RK3568_CLKSEL_CON(5), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
521 RK3568_CLKGATE_CON(1), 0, GFLAGS),
522
523 COMPOSITE_NODIV(ACLK_CORE_NIU2BUS, "aclk_core_niu2bus", gpll150_gpll100_gpll75_xin24m_p, CLK_IGNORE_UNUSED,
524 RK3568_CLKSEL_CON(5), 14, 2, MFLAGS,
525 RK3568_CLKGATE_CON(1), 2, GFLAGS),
526
527 GATE(CLK_CORE_PVTM, "clk_core_pvtm", "xin24m", 0,
528 RK3568_CLKGATE_CON(1), 10, GFLAGS),
529 GATE(CLK_CORE_PVTM_CORE, "clk_core_pvtm_core", "armclk", 0,
530 RK3568_CLKGATE_CON(1), 11, GFLAGS),
531 GATE(CLK_CORE_PVTPLL, "clk_core_pvtpll", "armclk", CLK_IGNORE_UNUSED,
532 RK3568_CLKGATE_CON(1), 12, GFLAGS),
533 GATE(PCLK_CORE_PVTM, "pclk_core_pvtm", "pclk_core_pre", 0,
534 RK3568_CLKGATE_CON(1), 9, GFLAGS),
535
536 /* PD_GPU */
537 COMPOSITE(CLK_GPU_SRC, "clk_gpu_src", mpll_gpll_cpll_npll_p, 0,
538 RK3568_CLKSEL_CON(6), 6, 2, MFLAGS | CLK_MUX_READ_ONLY, 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
539 RK3568_CLKGATE_CON(2), 0, GFLAGS),
540 MUX(CLK_GPU_PRE_MUX, "clk_gpu_pre_mux", clk_gpu_pre_mux_p, CLK_SET_RATE_PARENT,
541 RK3568_CLKSEL_CON(6), 11, 1, MFLAGS | CLK_MUX_READ_ONLY),
542 DIV(ACLK_GPU_PRE, "aclk_gpu_pre", "clk_gpu_pre_mux", 0,
543 RK3568_CLKSEL_CON(6), 8, 2, DFLAGS),
544 DIV(PCLK_GPU_PRE, "pclk_gpu_pre", "clk_gpu_pre_mux", 0,
545 RK3568_CLKSEL_CON(6), 12, 4, DFLAGS),
546 GATE(CLK_GPU, "clk_gpu", "clk_gpu_pre_mux", 0,
547 RK3568_CLKGATE_CON(2), 3, GFLAGS),
548
549 GATE(PCLK_GPU_PVTM, "pclk_gpu_pvtm", "pclk_gpu_pre", 0,
550 RK3568_CLKGATE_CON(2), 6, GFLAGS),
551 GATE(CLK_GPU_PVTM, "clk_gpu_pvtm", "xin24m", 0,
552 RK3568_CLKGATE_CON(2), 7, GFLAGS),
553 GATE(CLK_GPU_PVTM_CORE, "clk_gpu_pvtm_core", "clk_gpu_src", 0,
554 RK3568_CLKGATE_CON(2), 8, GFLAGS),
555 GATE(CLK_GPU_PVTPLL, "clk_gpu_pvtpll", "clk_gpu_src", CLK_IGNORE_UNUSED,
556 RK3568_CLKGATE_CON(2), 9, GFLAGS),
557
558 /* PD_NPU */
559 COMPOSITE(CLK_NPU_SRC, "clk_npu_src", npll_gpll_p, 0,
560 RK3568_CLKSEL_CON(7), 6, 1, MFLAGS, 0, 4, DFLAGS,
561 RK3568_CLKGATE_CON(3), 0, GFLAGS),
562 MUX(CLK_NPU_PRE_NDFT, "clk_npu_pre_ndft", clk_npu_pre_ndft_p, CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
563 RK3568_CLKSEL_CON(7), 8, 1, MFLAGS),
564 MUX(CLK_NPU, "clk_npu", clk_npu_p, CLK_SET_RATE_PARENT,
565 RK3568_CLKSEL_CON(7), 15, 1, MFLAGS),
566 COMPOSITE_NOMUX(HCLK_NPU_PRE, "hclk_npu_pre", "clk_npu", 0,
567 RK3568_CLKSEL_CON(8), 0, 4, DFLAGS,
568 RK3568_CLKGATE_CON(3), 2, GFLAGS),
569 COMPOSITE_NOMUX(PCLK_NPU_PRE, "pclk_npu_pre", "clk_npu", 0,
570 RK3568_CLKSEL_CON(8), 4, 4, DFLAGS,
571 RK3568_CLKGATE_CON(3), 3, GFLAGS),
572 GATE(ACLK_NPU_PRE, "aclk_npu_pre", "clk_npu", 0,
573 RK3568_CLKGATE_CON(3), 4, GFLAGS),
574 GATE(ACLK_NPU, "aclk_npu", "aclk_npu_pre", 0,
575 RK3568_CLKGATE_CON(3), 7, GFLAGS),
576 GATE(HCLK_NPU, "hclk_npu", "hclk_npu_pre", 0,
577 RK3568_CLKGATE_CON(3), 8, GFLAGS),
578
579 GATE(PCLK_NPU_PVTM, "pclk_npu_pvtm", "pclk_npu_pre", 0,
580 RK3568_CLKGATE_CON(3), 9, GFLAGS),
581 GATE(CLK_NPU_PVTM, "clk_npu_pvtm", "xin24m", 0,
582 RK3568_CLKGATE_CON(3), 10, GFLAGS),
583 GATE(CLK_NPU_PVTM_CORE, "clk_npu_pvtm_core", "clk_npu_pre_ndft", 0,
584 RK3568_CLKGATE_CON(3), 11, GFLAGS),
585 GATE(CLK_NPU_PVTPLL, "clk_npu_pvtpll", "clk_npu_pre_ndft", CLK_IGNORE_UNUSED,
586 RK3568_CLKGATE_CON(3), 12, GFLAGS),
587
588 /* PD_DDR */
589 COMPOSITE(CLK_DDRPHY1X_SRC, "clk_ddrphy1x_src", dpll_gpll_cpll_p, CLK_IGNORE_UNUSED,
590 RK3568_CLKSEL_CON(9), 6, 2, MFLAGS, 0, 5, DFLAGS,
591 RK3568_CLKGATE_CON(4), 0, GFLAGS),
592 MUXGRF(CLK_DDR1X, "clk_ddr1x", clk_ddr1x_p, CLK_SET_RATE_PARENT,
593 RK3568_CLKSEL_CON(9), 15, 1, MFLAGS),
594
595 COMPOSITE_NOMUX(CLK_MSCH, "clk_msch", "clk_ddr1x", CLK_IGNORE_UNUSED,
596 RK3568_CLKSEL_CON(10), 0, 2, DFLAGS,
597 RK3568_CLKGATE_CON(4), 2, GFLAGS),
598 GATE(CLK24_DDRMON, "clk24_ddrmon", "xin24m", CLK_IGNORE_UNUSED,
599 RK3568_CLKGATE_CON(4), 15, GFLAGS),
600
601 /* PD_GIC_AUDIO */
602 COMPOSITE_NODIV(ACLK_GIC_AUDIO, "aclk_gic_audio", gpll200_gpll150_gpll100_xin24m_p, CLK_IGNORE_UNUSED,
603 RK3568_CLKSEL_CON(10), 8, 2, MFLAGS,
604 RK3568_CLKGATE_CON(5), 0, GFLAGS),
605 COMPOSITE_NODIV(HCLK_GIC_AUDIO, "hclk_gic_audio", gpll150_gpll100_gpll75_xin24m_p, CLK_IGNORE_UNUSED,
606 RK3568_CLKSEL_CON(10), 10, 2, MFLAGS,
607 RK3568_CLKGATE_CON(5), 1, GFLAGS),
608 GATE(HCLK_SDMMC_BUFFER, "hclk_sdmmc_buffer", "hclk_gic_audio", 0,
609 RK3568_CLKGATE_CON(5), 8, GFLAGS),
610 COMPOSITE_NODIV(DCLK_SDMMC_BUFFER, "dclk_sdmmc_buffer", gpll100_gpll75_gpll50_p, 0,
611 RK3568_CLKSEL_CON(10), 12, 2, MFLAGS,
612 RK3568_CLKGATE_CON(5), 9, GFLAGS),
613 GATE(ACLK_GIC600, "aclk_gic600", "aclk_gic_audio", CLK_IGNORE_UNUSED,
614 RK3568_CLKGATE_CON(5), 4, GFLAGS),
615 GATE(ACLK_SPINLOCK, "aclk_spinlock", "aclk_gic_audio", CLK_IGNORE_UNUSED,
616 RK3568_CLKGATE_CON(5), 7, GFLAGS),
617 GATE(HCLK_I2S0_8CH, "hclk_i2s0_8ch", "hclk_gic_audio", 0,
618 RK3568_CLKGATE_CON(5), 10, GFLAGS),
619 GATE(HCLK_I2S1_8CH, "hclk_i2s1_8ch", "hclk_gic_audio", 0,
620 RK3568_CLKGATE_CON(5), 11, GFLAGS),
621 GATE(HCLK_I2S2_2CH, "hclk_i2s2_2ch", "hclk_gic_audio", 0,
622 RK3568_CLKGATE_CON(5), 12, GFLAGS),
623 GATE(HCLK_I2S3_2CH, "hclk_i2s3_2ch", "hclk_gic_audio", 0,
624 RK3568_CLKGATE_CON(5), 13, GFLAGS),
625
626 COMPOSITE(CLK_I2S0_8CH_TX_SRC, "clk_i2s0_8ch_tx_src", gpll_cpll_npll_p, 0,
627 RK3568_CLKSEL_CON(11), 8, 2, MFLAGS, 0, 7, DFLAGS,
628 RK3568_CLKGATE_CON(6), 0, GFLAGS),
629 COMPOSITE_FRACMUX(CLK_I2S0_8CH_TX_FRAC, "clk_i2s0_8ch_tx_frac", "clk_i2s0_8ch_tx_src", CLK_SET_RATE_PARENT,
630 RK3568_CLKSEL_CON(12), 0,
631 RK3568_CLKGATE_CON(6), 1, GFLAGS,
632 &rk3568_i2s0_8ch_tx_fracmux),
633 GATE(MCLK_I2S0_8CH_TX, "mclk_i2s0_8ch_tx", "clk_i2s0_8ch_tx", 0,
634 RK3568_CLKGATE_CON(6), 2, GFLAGS),
635 COMPOSITE_NODIV(I2S0_MCLKOUT_TX, "i2s0_mclkout_tx", i2s0_mclkout_tx_p, CLK_SET_RATE_PARENT,
636 RK3568_CLKSEL_CON(11), 15, 1, MFLAGS,
637 RK3568_CLKGATE_CON(6), 3, GFLAGS),
638
639 COMPOSITE(CLK_I2S0_8CH_RX_SRC, "clk_i2s0_8ch_rx_src", gpll_cpll_npll_p, 0,
640 RK3568_CLKSEL_CON(13), 8, 2, MFLAGS, 0, 7, DFLAGS,
641 RK3568_CLKGATE_CON(6), 4, GFLAGS),
642 COMPOSITE_FRACMUX(CLK_I2S0_8CH_RX_FRAC, "clk_i2s0_8ch_rx_frac", "clk_i2s0_8ch_rx_src", CLK_SET_RATE_PARENT,
643 RK3568_CLKSEL_CON(14), 0,
644 RK3568_CLKGATE_CON(6), 5, GFLAGS,
645 &rk3568_i2s0_8ch_rx_fracmux),
646 GATE(MCLK_I2S0_8CH_RX, "mclk_i2s0_8ch_rx", "clk_i2s0_8ch_rx", 0,
647 RK3568_CLKGATE_CON(6), 6, GFLAGS),
648 COMPOSITE_NODIV(I2S0_MCLKOUT_RX, "i2s0_mclkout_rx", i2s0_mclkout_rx_p, CLK_SET_RATE_PARENT,
649 RK3568_CLKSEL_CON(13), 15, 1, MFLAGS,
650 RK3568_CLKGATE_CON(6), 7, GFLAGS),
651
652 COMPOSITE(CLK_I2S1_8CH_TX_SRC, "clk_i2s1_8ch_tx_src", gpll_cpll_npll_p, 0,
653 RK3568_CLKSEL_CON(15), 8, 2, MFLAGS, 0, 7, DFLAGS,
654 RK3568_CLKGATE_CON(6), 8, GFLAGS),
655 COMPOSITE_FRACMUX(CLK_I2S1_8CH_TX_FRAC, "clk_i2s1_8ch_tx_frac", "clk_i2s1_8ch_tx_src", CLK_SET_RATE_PARENT,
656 RK3568_CLKSEL_CON(16), 0,
657 RK3568_CLKGATE_CON(6), 9, GFLAGS,
658 &rk3568_i2s1_8ch_tx_fracmux),
659 GATE(MCLK_I2S1_8CH_TX, "mclk_i2s1_8ch_tx", "clk_i2s1_8ch_tx", 0,
660 RK3568_CLKGATE_CON(6), 10, GFLAGS),
661 COMPOSITE_NODIV(I2S1_MCLKOUT_TX, "i2s1_mclkout_tx", i2s1_mclkout_tx_p, CLK_SET_RATE_PARENT,
662 RK3568_CLKSEL_CON(15), 15, 1, MFLAGS,
663 RK3568_CLKGATE_CON(6), 11, GFLAGS),
664
665 COMPOSITE(CLK_I2S1_8CH_RX_SRC, "clk_i2s1_8ch_rx_src", gpll_cpll_npll_p, 0,
666 RK3568_CLKSEL_CON(17), 8, 2, MFLAGS, 0, 7, DFLAGS,
667 RK3568_CLKGATE_CON(6), 12, GFLAGS),
668 COMPOSITE_FRACMUX(CLK_I2S1_8CH_RX_FRAC, "clk_i2s1_8ch_rx_frac", "clk_i2s1_8ch_rx_src", CLK_SET_RATE_PARENT,
669 RK3568_CLKSEL_CON(18), 0,
670 RK3568_CLKGATE_CON(6), 13, GFLAGS,
671 &rk3568_i2s1_8ch_rx_fracmux),
672 GATE(MCLK_I2S1_8CH_RX, "mclk_i2s1_8ch_rx", "clk_i2s1_8ch_rx", 0,
673 RK3568_CLKGATE_CON(6), 14, GFLAGS),
674 COMPOSITE_NODIV(I2S1_MCLKOUT_RX, "i2s1_mclkout_rx", i2s1_mclkout_rx_p, CLK_SET_RATE_PARENT,
675 RK3568_CLKSEL_CON(17), 15, 1, MFLAGS,
676 RK3568_CLKGATE_CON(6), 15, GFLAGS),
677
678 COMPOSITE(CLK_I2S2_2CH_SRC, "clk_i2s2_2ch_src", gpll_cpll_npll_p, 0,
679 RK3568_CLKSEL_CON(19), 8, 2, MFLAGS, 0, 7, DFLAGS,
680 RK3568_CLKGATE_CON(7), 0, GFLAGS),
681 COMPOSITE_FRACMUX(CLK_I2S2_2CH_FRAC, "clk_i2s2_2ch_frac", "clk_i2s2_2ch_src", CLK_SET_RATE_PARENT,
682 RK3568_CLKSEL_CON(20), 0,
683 RK3568_CLKGATE_CON(7), 1, GFLAGS,
684 &rk3568_i2s2_2ch_fracmux),
685 GATE(MCLK_I2S2_2CH, "mclk_i2s2_2ch", "clk_i2s2_2ch", 0,
686 RK3568_CLKGATE_CON(7), 2, GFLAGS),
687 COMPOSITE_NODIV(I2S2_MCLKOUT, "i2s2_mclkout", i2s2_mclkout_p, CLK_SET_RATE_PARENT,
688 RK3568_CLKSEL_CON(19), 15, 1, MFLAGS,
689 RK3568_CLKGATE_CON(7), 3, GFLAGS),
690
691 COMPOSITE(CLK_I2S3_2CH_TX_SRC, "clk_i2s3_2ch_tx_src", gpll_cpll_npll_p, 0,
692 RK3568_CLKSEL_CON(21), 8, 2, MFLAGS, 0, 7, DFLAGS,
693 RK3568_CLKGATE_CON(7), 4, GFLAGS),
694 COMPOSITE_FRACMUX(CLK_I2S3_2CH_TX_FRAC, "clk_i2s3_2ch_tx_frac", "clk_i2s3_2ch_tx_src", CLK_SET_RATE_PARENT,
695 RK3568_CLKSEL_CON(22), 0,
696 RK3568_CLKGATE_CON(7), 5, GFLAGS,
697 &rk3568_i2s3_2ch_tx_fracmux),
698 GATE(MCLK_I2S3_2CH_TX, "mclk_i2s3_2ch_tx", "clk_i2s3_2ch_tx", 0,
699 RK3568_CLKGATE_CON(7), 6, GFLAGS),
700 COMPOSITE_NODIV(I2S3_MCLKOUT_TX, "i2s3_mclkout_tx", i2s3_mclkout_tx_p, CLK_SET_RATE_PARENT,
701 RK3568_CLKSEL_CON(21), 15, 1, MFLAGS,
702 RK3568_CLKGATE_CON(7), 7, GFLAGS),
703
704 COMPOSITE(CLK_I2S3_2CH_RX_SRC, "clk_i2s3_2ch_rx_src", gpll_cpll_npll_p, 0,
705 RK3568_CLKSEL_CON(83), 8, 2, MFLAGS, 0, 7, DFLAGS,
706 RK3568_CLKGATE_CON(7), 8, GFLAGS),
707 COMPOSITE_FRACMUX(CLK_I2S3_2CH_RX_FRAC, "clk_i2s3_2ch_rx_frac", "clk_i2s3_2ch_rx_src", CLK_SET_RATE_PARENT,
708 RK3568_CLKSEL_CON(84), 0,
709 RK3568_CLKGATE_CON(7), 9, GFLAGS,
710 &rk3568_i2s3_2ch_rx_fracmux),
711 GATE(MCLK_I2S3_2CH_RX, "mclk_i2s3_2ch_rx", "clk_i2s3_2ch_rx", 0,
712 RK3568_CLKGATE_CON(7), 10, GFLAGS),
713 COMPOSITE_NODIV(I2S3_MCLKOUT_RX, "i2s3_mclkout_rx", i2s3_mclkout_rx_p, CLK_SET_RATE_PARENT,
714 RK3568_CLKSEL_CON(83), 15, 1, MFLAGS,
715 RK3568_CLKGATE_CON(7), 11, GFLAGS),
716
717 GATE(HCLK_PDM, "hclk_pdm", "hclk_gic_audio", 0,
718 RK3568_CLKGATE_CON(5), 14, GFLAGS),
719 COMPOSITE_NODIV(MCLK_PDM, "mclk_pdm", mclk_pdm_p, 0,
720 RK3568_CLKSEL_CON(23), 8, 2, MFLAGS,
721 RK3568_CLKGATE_CON(5), 15, GFLAGS),
722 GATE(HCLK_VAD, "hclk_vad", "hclk_gic_audio", 0,
723 RK3568_CLKGATE_CON(7), 12, GFLAGS),
724 GATE(HCLK_SPDIF_8CH, "hclk_spdif_8ch", "hclk_gic_audio", 0,
725 RK3568_CLKGATE_CON(7), 13, GFLAGS),
726
727 COMPOSITE(MCLK_SPDIF_8CH_SRC, "mclk_spdif_8ch_src", cpll_gpll_p, 0,
728 RK3568_CLKSEL_CON(23), 14, 1, MFLAGS, 0, 7, DFLAGS,
729 RK3568_CLKGATE_CON(7), 14, GFLAGS),
730 COMPOSITE_FRACMUX(MCLK_SPDIF_8CH_FRAC, "mclk_spdif_8ch_frac", "mclk_spdif_8ch_src", CLK_SET_RATE_PARENT,
731 RK3568_CLKSEL_CON(24), 0,
732 RK3568_CLKGATE_CON(7), 15, GFLAGS,
733 &rk3568_spdif_8ch_fracmux),
734
735 GATE(HCLK_AUDPWM, "hclk_audpwm", "hclk_gic_audio", 0,
736 RK3568_CLKGATE_CON(8), 0, GFLAGS),
737 COMPOSITE(SCLK_AUDPWM_SRC, "sclk_audpwm_src", gpll_cpll_p, 0,
738 RK3568_CLKSEL_CON(25), 14, 1, MFLAGS, 0, 6, DFLAGS,
739 RK3568_CLKGATE_CON(8), 1, GFLAGS),
740 COMPOSITE_FRACMUX(SCLK_AUDPWM_FRAC, "sclk_audpwm_frac", "sclk_audpwm_src", CLK_SET_RATE_PARENT,
741 RK3568_CLKSEL_CON(26), 0,
742 RK3568_CLKGATE_CON(8), 2, GFLAGS,
743 &rk3568_audpwm_fracmux),
744
745 GATE(HCLK_ACDCDIG, "hclk_acdcdig", "hclk_gic_audio", 0,
746 RK3568_CLKGATE_CON(8), 3, GFLAGS),
747 COMPOSITE_NODIV(CLK_ACDCDIG_I2C, "clk_acdcdig_i2c", clk_i2c_p, 0,
748 RK3568_CLKSEL_CON(23), 10, 2, MFLAGS,
749 RK3568_CLKGATE_CON(8), 4, GFLAGS),
750 GATE(CLK_ACDCDIG_DAC, "clk_acdcdig_dac", "mclk_i2s3_2ch_tx", 0,
751 RK3568_CLKGATE_CON(8), 5, GFLAGS),
752 GATE(CLK_ACDCDIG_ADC, "clk_acdcdig_adc", "mclk_i2s3_2ch_rx", 0,
753 RK3568_CLKGATE_CON(8), 6, GFLAGS),
754
755 /* PD_SECURE_FLASH */
756 COMPOSITE_NODIV(ACLK_SECURE_FLASH, "aclk_secure_flash", gpll200_gpll150_gpll100_xin24m_p, 0,
757 RK3568_CLKSEL_CON(27), 0, 2, MFLAGS,
758 RK3568_CLKGATE_CON(8), 7, GFLAGS),
759 COMPOSITE_NODIV(HCLK_SECURE_FLASH, "hclk_secure_flash", gpll150_gpll100_gpll75_xin24m_p, 0,
760 RK3568_CLKSEL_CON(27), 2, 2, MFLAGS,
761 RK3568_CLKGATE_CON(8), 8, GFLAGS),
762 GATE(ACLK_CRYPTO_NS, "aclk_crypto_ns", "aclk_secure_flash", 0,
763 RK3568_CLKGATE_CON(8), 11, GFLAGS),
764 GATE(HCLK_CRYPTO_NS, "hclk_crypto_ns", "hclk_secure_flash", 0,
765 RK3568_CLKGATE_CON(8), 12, GFLAGS),
766 COMPOSITE_NODIV(CLK_CRYPTO_NS_CORE, "clk_crypto_ns_core", gpll200_gpll150_gpll100_p, 0,
767 RK3568_CLKSEL_CON(27), 4, 2, MFLAGS,
768 RK3568_CLKGATE_CON(8), 13, GFLAGS),
769 COMPOSITE_NODIV(CLK_CRYPTO_NS_PKA, "clk_crypto_ns_pka", gpll300_gpll200_gpll100_p, 0,
770 RK3568_CLKSEL_CON(27), 6, 2, MFLAGS,
771 RK3568_CLKGATE_CON(8), 14, GFLAGS),
772 GATE(CLK_CRYPTO_NS_RNG, "clk_crypto_ns_rng", "hclk_secure_flash", 0,
773 RK3568_CLKGATE_CON(8), 15, GFLAGS),
774 GATE(HCLK_TRNG_NS, "hclk_trng_ns", "hclk_secure_flash", CLK_IGNORE_UNUSED,
775 RK3568_CLKGATE_CON(9), 10, GFLAGS),
776 GATE(CLK_TRNG_NS, "clk_trng_ns", "hclk_secure_flash", CLK_IGNORE_UNUSED,
777 RK3568_CLKGATE_CON(9), 11, GFLAGS),
778 GATE(PCLK_OTPC_NS, "pclk_otpc_ns", "hclk_secure_flash", 0,
779 RK3568_CLKGATE_CON(26), 9, GFLAGS),
780 GATE(CLK_OTPC_NS_SBPI, "clk_otpc_ns_sbpi", "xin24m", 0,
781 RK3568_CLKGATE_CON(26), 10, GFLAGS),
782 GATE(CLK_OTPC_NS_USR, "clk_otpc_ns_usr", "xin_osc0_half", 0,
783 RK3568_CLKGATE_CON(26), 11, GFLAGS),
784 GATE(HCLK_NANDC, "hclk_nandc", "hclk_secure_flash", 0,
785 RK3568_CLKGATE_CON(9), 0, GFLAGS),
786 COMPOSITE_NODIV(NCLK_NANDC, "nclk_nandc", clk_nandc_p, 0,
787 RK3568_CLKSEL_CON(28), 0, 2, MFLAGS,
788 RK3568_CLKGATE_CON(9), 1, GFLAGS),
789 GATE(HCLK_SFC, "hclk_sfc", "hclk_secure_flash", 0,
790 RK3568_CLKGATE_CON(9), 2, GFLAGS),
791 GATE(HCLK_SFC_XIP, "hclk_sfc_xip", "hclk_secure_flash", 0,
792 RK3568_CLKGATE_CON(9), 3, GFLAGS),
793 COMPOSITE_NODIV(SCLK_SFC, "sclk_sfc", sclk_sfc_p, 0,
794 RK3568_CLKSEL_CON(28), 4, 3, MFLAGS,
795 RK3568_CLKGATE_CON(9), 4, GFLAGS),
796 GATE(ACLK_EMMC, "aclk_emmc", "aclk_secure_flash", 0,
797 RK3568_CLKGATE_CON(9), 5, GFLAGS),
798 GATE(HCLK_EMMC, "hclk_emmc", "hclk_secure_flash", 0,
799 RK3568_CLKGATE_CON(9), 6, GFLAGS),
800 COMPOSITE_NODIV(BCLK_EMMC, "bclk_emmc", gpll200_gpll150_cpll125_p, 0,
801 RK3568_CLKSEL_CON(28), 8, 2, MFLAGS,
802 RK3568_CLKGATE_CON(9), 7, GFLAGS),
803 COMPOSITE_NODIV(CCLK_EMMC, "cclk_emmc", cclk_emmc_p, 0,
804 RK3568_CLKSEL_CON(28), 12, 3, MFLAGS,
805 RK3568_CLKGATE_CON(9), 8, GFLAGS),
806 GATE(TCLK_EMMC, "tclk_emmc", "xin24m", 0,
807 RK3568_CLKGATE_CON(9), 9, GFLAGS),
808 MMC(SCLK_EMMC_DRV, "emmc_drv", "cclk_emmc", RK3568_EMMC_CON0, 1),
809 MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "cclk_emmc", RK3568_EMMC_CON1, 1),
810
811 /* PD_PIPE */
812 COMPOSITE_NODIV(ACLK_PIPE, "aclk_pipe", aclk_pipe_p, 0,
813 RK3568_CLKSEL_CON(29), 0, 2, MFLAGS,
814 RK3568_CLKGATE_CON(10), 0, GFLAGS),
815 COMPOSITE_NOMUX(PCLK_PIPE, "pclk_pipe", "aclk_pipe", 0,
816 RK3568_CLKSEL_CON(29), 4, 4, DFLAGS,
817 RK3568_CLKGATE_CON(10), 1, GFLAGS),
818 GATE(ACLK_PCIE20_MST, "aclk_pcie20_mst", "aclk_pipe", 0,
819 RK3568_CLKGATE_CON(12), 0, GFLAGS),
820 GATE(ACLK_PCIE20_SLV, "aclk_pcie20_slv", "aclk_pipe", 0,
821 RK3568_CLKGATE_CON(12), 1, GFLAGS),
822 GATE(ACLK_PCIE20_DBI, "aclk_pcie20_dbi", "aclk_pipe", 0,
823 RK3568_CLKGATE_CON(12), 2, GFLAGS),
824 GATE(PCLK_PCIE20, "pclk_pcie20", "pclk_pipe", 0,
825 RK3568_CLKGATE_CON(12), 3, GFLAGS),
826 GATE(CLK_PCIE20_AUX_NDFT, "clk_pcie20_aux_ndft", "xin24m", 0,
827 RK3568_CLKGATE_CON(12), 4, GFLAGS),
828 GATE(ACLK_PCIE30X1_MST, "aclk_pcie30x1_mst", "aclk_pipe", 0,
829 RK3568_CLKGATE_CON(12), 8, GFLAGS),
830 GATE(ACLK_PCIE30X1_SLV, "aclk_pcie30x1_slv", "aclk_pipe", 0,
831 RK3568_CLKGATE_CON(12), 9, GFLAGS),
832 GATE(ACLK_PCIE30X1_DBI, "aclk_pcie30x1_dbi", "aclk_pipe", 0,
833 RK3568_CLKGATE_CON(12), 10, GFLAGS),
834 GATE(PCLK_PCIE30X1, "pclk_pcie30x1", "pclk_pipe", 0,
835 RK3568_CLKGATE_CON(12), 11, GFLAGS),
836 GATE(CLK_PCIE30X1_AUX_NDFT, "clk_pcie30x1_aux_ndft", "xin24m", 0,
837 RK3568_CLKGATE_CON(12), 12, GFLAGS),
838 GATE(ACLK_PCIE30X2_MST, "aclk_pcie30x2_mst", "aclk_pipe", 0,
839 RK3568_CLKGATE_CON(13), 0, GFLAGS),
840 GATE(ACLK_PCIE30X2_SLV, "aclk_pcie30x2_slv", "aclk_pipe", 0,
841 RK3568_CLKGATE_CON(13), 1, GFLAGS),
842 GATE(ACLK_PCIE30X2_DBI, "aclk_pcie30x2_dbi", "aclk_pipe", 0,
843 RK3568_CLKGATE_CON(13), 2, GFLAGS),
844 GATE(PCLK_PCIE30X2, "pclk_pcie30x2", "pclk_pipe", 0,
845 RK3568_CLKGATE_CON(13), 3, GFLAGS),
846 GATE(CLK_PCIE30X2_AUX_NDFT, "clk_pcie30x2_aux_ndft", "xin24m", 0,
847 RK3568_CLKGATE_CON(13), 4, GFLAGS),
848 GATE(ACLK_SATA0, "aclk_sata0", "aclk_pipe", 0,
849 RK3568_CLKGATE_CON(11), 0, GFLAGS),
850 GATE(CLK_SATA0_PMALIVE, "clk_sata0_pmalive", "gpll_20m", 0,
851 RK3568_CLKGATE_CON(11), 1, GFLAGS),
852 GATE(CLK_SATA0_RXOOB, "clk_sata0_rxoob", "cpll_50m", 0,
853 RK3568_CLKGATE_CON(11), 2, GFLAGS),
854 GATE(ACLK_SATA1, "aclk_sata1", "aclk_pipe", 0,
855 RK3568_CLKGATE_CON(11), 4, GFLAGS),
856 GATE(CLK_SATA1_PMALIVE, "clk_sata1_pmalive", "gpll_20m", 0,
857 RK3568_CLKGATE_CON(11), 5, GFLAGS),
858 GATE(CLK_SATA1_RXOOB, "clk_sata1_rxoob", "cpll_50m", 0,
859 RK3568_CLKGATE_CON(11), 6, GFLAGS),
860 GATE(ACLK_SATA2, "aclk_sata2", "aclk_pipe", 0,
861 RK3568_CLKGATE_CON(11), 8, GFLAGS),
862 GATE(CLK_SATA2_PMALIVE, "clk_sata2_pmalive", "gpll_20m", 0,
863 RK3568_CLKGATE_CON(11), 9, GFLAGS),
864 GATE(CLK_SATA2_RXOOB, "clk_sata2_rxoob", "cpll_50m", 0,
865 RK3568_CLKGATE_CON(11), 10, GFLAGS),
866 GATE(ACLK_USB3OTG0, "aclk_usb3otg0", "aclk_pipe", 0,
867 RK3568_CLKGATE_CON(10), 8, GFLAGS),
868 GATE(CLK_USB3OTG0_REF, "clk_usb3otg0_ref", "xin24m", 0,
869 RK3568_CLKGATE_CON(10), 9, GFLAGS),
870 COMPOSITE_NODIV(CLK_USB3OTG0_SUSPEND, "clk_usb3otg0_suspend", xin24m_32k_p, 0,
871 RK3568_CLKSEL_CON(29), 8, 1, MFLAGS,
872 RK3568_CLKGATE_CON(10), 10, GFLAGS),
873 GATE(ACLK_USB3OTG1, "aclk_usb3otg1", "aclk_pipe", 0,
874 RK3568_CLKGATE_CON(10), 12, GFLAGS),
875 GATE(CLK_USB3OTG1_REF, "clk_usb3otg1_ref", "xin24m", 0,
876 RK3568_CLKGATE_CON(10), 13, GFLAGS),
877 COMPOSITE_NODIV(CLK_USB3OTG1_SUSPEND, "clk_usb3otg1_suspend", xin24m_32k_p, 0,
878 RK3568_CLKSEL_CON(29), 9, 1, MFLAGS,
879 RK3568_CLKGATE_CON(10), 14, GFLAGS),
880 COMPOSITE_NODIV(CLK_XPCS_EEE, "clk_xpcs_eee", gpll200_cpll125_p, 0,
881 RK3568_CLKSEL_CON(29), 13, 1, MFLAGS,
882 RK3568_CLKGATE_CON(10), 4, GFLAGS),
883 GATE(PCLK_XPCS, "pclk_xpcs", "pclk_pipe", 0,
884 RK3568_CLKGATE_CON(13), 6, GFLAGS),
885
886 /* PD_PHP */
887 COMPOSITE_NODIV(ACLK_PHP, "aclk_php", gpll300_gpll200_gpll100_xin24m_p, 0,
888 RK3568_CLKSEL_CON(30), 0, 2, MFLAGS,
889 RK3568_CLKGATE_CON(14), 8, GFLAGS),
890 COMPOSITE_NODIV(HCLK_PHP, "hclk_php", gpll150_gpll100_gpll75_xin24m_p, 0,
891 RK3568_CLKSEL_CON(30), 2, 2, MFLAGS,
892 RK3568_CLKGATE_CON(14), 9, GFLAGS),
893 COMPOSITE_NOMUX(PCLK_PHP, "pclk_php", "aclk_php", 0,
894 RK3568_CLKSEL_CON(30), 4, 4, DFLAGS,
895 RK3568_CLKGATE_CON(14), 10, GFLAGS),
896 GATE(HCLK_SDMMC0, "hclk_sdmmc0", "hclk_php", 0,
897 RK3568_CLKGATE_CON(15), 0, GFLAGS),
898 COMPOSITE_NODIV(CLK_SDMMC0, "clk_sdmmc0", clk_sdmmc_p, 0,
899 RK3568_CLKSEL_CON(30), 8, 3, MFLAGS,
900 RK3568_CLKGATE_CON(15), 1, GFLAGS),
901 MMC(SCLK_SDMMC0_DRV, "sdmmc0_drv", "clk_sdmmc0", RK3568_SDMMC0_CON0, 1),
902 MMC(SCLK_SDMMC0_SAMPLE, "sdmmc0_sample", "clk_sdmmc0", RK3568_SDMMC0_CON1, 1),
903
904 GATE(HCLK_SDMMC1, "hclk_sdmmc1", "hclk_php", 0,
905 RK3568_CLKGATE_CON(15), 2, GFLAGS),
906 COMPOSITE_NODIV(CLK_SDMMC1, "clk_sdmmc1", clk_sdmmc_p, 0,
907 RK3568_CLKSEL_CON(30), 12, 3, MFLAGS,
908 RK3568_CLKGATE_CON(15), 3, GFLAGS),
909 MMC(SCLK_SDMMC1_DRV, "sdmmc1_drv", "clk_sdmmc1", RK3568_SDMMC1_CON0, 1),
910 MMC(SCLK_SDMMC1_SAMPLE, "sdmmc1_sample", "clk_sdmmc1", RK3568_SDMMC1_CON1, 1),
911
912 GATE(ACLK_GMAC0, "aclk_gmac0", "aclk_php", 0,
913 RK3568_CLKGATE_CON(15), 5, GFLAGS),
914 GATE(PCLK_GMAC0, "pclk_gmac0", "pclk_php", 0,
915 RK3568_CLKGATE_CON(15), 6, GFLAGS),
916 COMPOSITE_NODIV(CLK_MAC0_2TOP, "clk_mac0_2top", clk_mac_2top_p, 0,
917 RK3568_CLKSEL_CON(31), 8, 2, MFLAGS,
918 RK3568_CLKGATE_CON(15), 7, GFLAGS),
919 COMPOSITE_NODIV(CLK_MAC0_OUT, "clk_mac0_out", cpll125_cpll50_cpll25_xin24m_p, 0,
920 RK3568_CLKSEL_CON(31), 14, 2, MFLAGS,
921 RK3568_CLKGATE_CON(15), 8, GFLAGS),
922 GATE(CLK_MAC0_REFOUT, "clk_mac0_refout", "clk_mac0_2top", 0,
923 RK3568_CLKGATE_CON(15), 12, GFLAGS),
924 COMPOSITE_NODIV(CLK_GMAC0_PTP_REF, "clk_gmac0_ptp_ref", clk_gmac_ptp_p, 0,
925 RK3568_CLKSEL_CON(31), 12, 2, MFLAGS,
926 RK3568_CLKGATE_CON(15), 4, GFLAGS),
927 MUX(SCLK_GMAC0, "clk_gmac0", mux_gmac0_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
928 RK3568_CLKSEL_CON(31), 2, 1, MFLAGS),
929 FACTOR(0, "clk_gmac0_tx_div5", "clk_gmac0", 0, 1, 5),
930 FACTOR(0, "clk_gmac0_tx_div50", "clk_gmac0", 0, 1, 50),
931 FACTOR(0, "clk_gmac0_rx_div2", "clk_gmac0", 0, 1, 2),
932 FACTOR(0, "clk_gmac0_rx_div20", "clk_gmac0", 0, 1, 20),
933 MUX(SCLK_GMAC0_RGMII_SPEED, "clk_gmac0_rgmii_speed", mux_gmac0_rgmii_speed_p, 0,
934 RK3568_CLKSEL_CON(31), 4, 2, MFLAGS),
935 MUX(SCLK_GMAC0_RMII_SPEED, "clk_gmac0_rmii_speed", mux_gmac0_rmii_speed_p, 0,
936 RK3568_CLKSEL_CON(31), 3, 1, MFLAGS),
937 MUX(SCLK_GMAC0_RX_TX, "clk_gmac0_rx_tx", mux_gmac0_rx_tx_p, CLK_SET_RATE_PARENT,
938 RK3568_CLKSEL_CON(31), 0, 2, MFLAGS),
939
940 /* PD_USB */
941 COMPOSITE_NODIV(ACLK_USB, "aclk_usb", gpll300_gpll200_gpll100_xin24m_p, 0,
942 RK3568_CLKSEL_CON(32), 0, 2, MFLAGS,
943 RK3568_CLKGATE_CON(16), 0, GFLAGS),
944 COMPOSITE_NODIV(HCLK_USB, "hclk_usb", gpll150_gpll100_gpll75_xin24m_p, 0,
945 RK3568_CLKSEL_CON(32), 2, 2, MFLAGS,
946 RK3568_CLKGATE_CON(16), 1, GFLAGS),
947 COMPOSITE_NOMUX(PCLK_USB, "pclk_usb", "aclk_usb", 0,
948 RK3568_CLKSEL_CON(32), 4, 4, DFLAGS,
949 RK3568_CLKGATE_CON(16), 2, GFLAGS),
950 GATE(HCLK_USB2HOST0, "hclk_usb2host0", "hclk_usb", 0,
951 RK3568_CLKGATE_CON(16), 12, GFLAGS),
952 GATE(HCLK_USB2HOST0_ARB, "hclk_usb2host0_arb", "hclk_usb", 0,
953 RK3568_CLKGATE_CON(16), 13, GFLAGS),
954 GATE(HCLK_USB2HOST1, "hclk_usb2host1", "hclk_usb", 0,
955 RK3568_CLKGATE_CON(16), 14, GFLAGS),
956 GATE(HCLK_USB2HOST1_ARB, "hclk_usb2host1_arb", "hclk_usb", 0,
957 RK3568_CLKGATE_CON(16), 15, GFLAGS),
958 GATE(HCLK_SDMMC2, "hclk_sdmmc2", "hclk_usb", 0,
959 RK3568_CLKGATE_CON(17), 0, GFLAGS),
960 COMPOSITE_NODIV(CLK_SDMMC2, "clk_sdmmc2", clk_sdmmc_p, 0,
961 RK3568_CLKSEL_CON(32), 8, 3, MFLAGS,
962 RK3568_CLKGATE_CON(17), 1, GFLAGS),
963 MMC(SCLK_SDMMC2_DRV, "sdmmc2_drv", "clk_sdmmc2", RK3568_SDMMC2_CON0, 1),
964 MMC(SCLK_SDMMC2_SAMPLE, "sdmmc2_sample", "clk_sdmmc2", RK3568_SDMMC2_CON1, 1),
965
966 GATE(ACLK_GMAC1, "aclk_gmac1", "aclk_usb", 0,
967 RK3568_CLKGATE_CON(17), 3, GFLAGS),
968 GATE(PCLK_GMAC1, "pclk_gmac1", "pclk_usb", 0,
969 RK3568_CLKGATE_CON(17), 4, GFLAGS),
970 COMPOSITE_NODIV(CLK_MAC1_2TOP, "clk_mac1_2top", clk_mac_2top_p, 0,
971 RK3568_CLKSEL_CON(33), 8, 2, MFLAGS,
972 RK3568_CLKGATE_CON(17), 5, GFLAGS),
973 COMPOSITE_NODIV(CLK_MAC1_OUT, "clk_mac1_out", cpll125_cpll50_cpll25_xin24m_p, 0,
974 RK3568_CLKSEL_CON(33), 14, 2, MFLAGS,
975 RK3568_CLKGATE_CON(17), 6, GFLAGS),
976 GATE(CLK_MAC1_REFOUT, "clk_mac1_refout", "clk_mac1_2top", 0,
977 RK3568_CLKGATE_CON(17), 10, GFLAGS),
978 COMPOSITE_NODIV(CLK_GMAC1_PTP_REF, "clk_gmac1_ptp_ref", clk_gmac_ptp_p, 0,
979 RK3568_CLKSEL_CON(33), 12, 2, MFLAGS,
980 RK3568_CLKGATE_CON(17), 2, GFLAGS),
981 MUX(SCLK_GMAC1, "clk_gmac1", mux_gmac1_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
982 RK3568_CLKSEL_CON(33), 2, 1, MFLAGS),
983 FACTOR(0, "clk_gmac1_tx_div5", "clk_gmac1", 0, 1, 5),
984 FACTOR(0, "clk_gmac1_tx_div50", "clk_gmac1", 0, 1, 50),
985 FACTOR(0, "clk_gmac1_rx_div2", "clk_gmac1", 0, 1, 2),
986 FACTOR(0, "clk_gmac1_rx_div20", "clk_gmac1", 0, 1, 20),
987 MUX(SCLK_GMAC1_RGMII_SPEED, "clk_gmac1_rgmii_speed", mux_gmac1_rgmii_speed_p, 0,
988 RK3568_CLKSEL_CON(33), 4, 2, MFLAGS),
989 MUX(SCLK_GMAC1_RMII_SPEED, "clk_gmac1_rmii_speed", mux_gmac1_rmii_speed_p, 0,
990 RK3568_CLKSEL_CON(33), 3, 1, MFLAGS),
991 MUX(SCLK_GMAC1_RX_TX, "clk_gmac1_rx_tx", mux_gmac1_rx_tx_p, CLK_SET_RATE_PARENT,
992 RK3568_CLKSEL_CON(33), 0, 2, MFLAGS),
993
994 /* PD_PERI */
995 COMPOSITE_NODIV(ACLK_PERIMID, "aclk_perimid", gpll300_gpll200_gpll100_xin24m_p, CLK_IGNORE_UNUSED,
996 RK3568_CLKSEL_CON(10), 4, 2, MFLAGS,
997 RK3568_CLKGATE_CON(14), 0, GFLAGS),
998 COMPOSITE_NODIV(HCLK_PERIMID, "hclk_perimid", gpll150_gpll100_gpll75_xin24m_p, CLK_IGNORE_UNUSED,
999 RK3568_CLKSEL_CON(10), 6, 2, MFLAGS,
1000 RK3568_CLKGATE_CON(14), 1, GFLAGS),
1001
1002 /* PD_VI */
1003 COMPOSITE_NODIV(ACLK_VI, "aclk_vi", gpll400_gpll300_gpll200_xin24m_p, 0,
1004 RK3568_CLKSEL_CON(34), 0, 2, MFLAGS,
1005 RK3568_CLKGATE_CON(18), 0, GFLAGS),
1006 COMPOSITE_NOMUX(HCLK_VI, "hclk_vi", "aclk_vi", 0,
1007 RK3568_CLKSEL_CON(34), 4, 4, DFLAGS,
1008 RK3568_CLKGATE_CON(18), 1, GFLAGS),
1009 COMPOSITE_NOMUX(PCLK_VI, "pclk_vi", "aclk_vi", 0,
1010 RK3568_CLKSEL_CON(34), 8, 4, DFLAGS,
1011 RK3568_CLKGATE_CON(18), 2, GFLAGS),
1012 GATE(ACLK_VICAP, "aclk_vicap", "aclk_vi", 0,
1013 RK3568_CLKGATE_CON(18), 9, GFLAGS),
1014 GATE(HCLK_VICAP, "hclk_vicap", "hclk_vi", 0,
1015 RK3568_CLKGATE_CON(18), 10, GFLAGS),
1016 COMPOSITE_NODIV(DCLK_VICAP, "dclk_vicap", cpll333_gpll300_gpll200_p, 0,
1017 RK3568_CLKSEL_CON(34), 14, 2, MFLAGS,
1018 RK3568_CLKGATE_CON(18), 11, GFLAGS),
1019 GATE(ICLK_VICAP_G, "iclk_vicap_g", "iclk_vicap", 0,
1020 RK3568_CLKGATE_CON(18), 13, GFLAGS),
1021 GATE(ACLK_ISP, "aclk_isp", "aclk_vi", 0,
1022 RK3568_CLKGATE_CON(19), 0, GFLAGS),
1023 GATE(HCLK_ISP, "hclk_isp", "hclk_vi", 0,
1024 RK3568_CLKGATE_CON(19), 1, GFLAGS),
1025 COMPOSITE(CLK_ISP, "clk_isp", cpll_gpll_hpll_p, 0,
1026 RK3568_CLKSEL_CON(35), 6, 2, MFLAGS, 0, 5, DFLAGS,
1027 RK3568_CLKGATE_CON(19), 2, GFLAGS),
1028 GATE(PCLK_CSI2HOST1, "pclk_csi2host1", "pclk_vi", 0,
1029 RK3568_CLKGATE_CON(19), 4, GFLAGS),
1030 COMPOSITE(CLK_CIF_OUT, "clk_cif_out", gpll_usb480m_xin24m_p, 0,
1031 RK3568_CLKSEL_CON(35), 14, 2, MFLAGS, 8, 6, DFLAGS,
1032 RK3568_CLKGATE_CON(19), 8, GFLAGS),
1033 COMPOSITE(CLK_CAM0_OUT, "clk_cam0_out", gpll_usb480m_xin24m_p, 0,
1034 RK3568_CLKSEL_CON(36), 6, 2, MFLAGS, 0, 6, DFLAGS,
1035 RK3568_CLKGATE_CON(19), 9, GFLAGS),
1036 COMPOSITE(CLK_CAM1_OUT, "clk_cam1_out", gpll_usb480m_xin24m_p, 0,
1037 RK3568_CLKSEL_CON(36), 14, 2, MFLAGS, 8, 6, DFLAGS,
1038 RK3568_CLKGATE_CON(19), 10, GFLAGS),
1039
1040 /* PD_VO */
1041 COMPOSITE_NODIV(ACLK_VO, "aclk_vo", gpll300_cpll250_gpll100_xin24m_p, 0,
1042 RK3568_CLKSEL_CON(37), 0, 2, MFLAGS,
1043 RK3568_CLKGATE_CON(20), 0, GFLAGS),
1044 COMPOSITE_NOMUX(HCLK_VO, "hclk_vo", "aclk_vo", 0,
1045 RK3568_CLKSEL_CON(37), 8, 4, DFLAGS,
1046 RK3568_CLKGATE_CON(20), 1, GFLAGS),
1047 COMPOSITE_NOMUX(PCLK_VO, "pclk_vo", "aclk_vo", 0,
1048 RK3568_CLKSEL_CON(37), 12, 4, DFLAGS,
1049 RK3568_CLKGATE_CON(20), 2, GFLAGS),
1050 COMPOSITE(ACLK_VOP_PRE, "aclk_vop_pre", cpll_gpll_hpll_vpll_p, 0,
1051 RK3568_CLKSEL_CON(38), 6, 2, MFLAGS, 0, 5, DFLAGS,
1052 RK3568_CLKGATE_CON(20), 6, GFLAGS),
1053 GATE(ACLK_VOP, "aclk_vop", "aclk_vop_pre", 0,
1054 RK3568_CLKGATE_CON(20), 8, GFLAGS),
1055 GATE(HCLK_VOP, "hclk_vop", "hclk_vo", 0,
1056 RK3568_CLKGATE_CON(20), 9, GFLAGS),
1057 COMPOSITE(DCLK_VOP0, "dclk_vop0", hpll_vpll_gpll_cpll_p, CLK_SET_RATE_NO_REPARENT,
1058 RK3568_CLKSEL_CON(39), 10, 2, MFLAGS, 0, 8, DFLAGS,
1059 RK3568_CLKGATE_CON(20), 10, GFLAGS),
1060 COMPOSITE(DCLK_VOP1, "dclk_vop1", hpll_vpll_gpll_cpll_p, CLK_SET_RATE_NO_REPARENT,
1061 RK3568_CLKSEL_CON(40), 10, 2, MFLAGS, 0, 8, DFLAGS,
1062 RK3568_CLKGATE_CON(20), 11, GFLAGS),
1063 COMPOSITE(DCLK_VOP2, "dclk_vop2", hpll_vpll_gpll_cpll_p, CLK_SET_RATE_NO_REPARENT,
1064 RK3568_CLKSEL_CON(41), 10, 2, MFLAGS, 0, 8, DFLAGS,
1065 RK3568_CLKGATE_CON(20), 12, GFLAGS),
1066 GATE(CLK_VOP_PWM, "clk_vop_pwm", "xin24m", 0,
1067 RK3568_CLKGATE_CON(20), 13, GFLAGS),
1068 GATE(ACLK_HDCP, "aclk_hdcp", "aclk_vo", 0,
1069 RK3568_CLKGATE_CON(21), 0, GFLAGS),
1070 GATE(HCLK_HDCP, "hclk_hdcp", "hclk_vo", 0,
1071 RK3568_CLKGATE_CON(21), 1, GFLAGS),
1072 GATE(PCLK_HDCP, "pclk_hdcp", "pclk_vo", 0,
1073 RK3568_CLKGATE_CON(21), 2, GFLAGS),
1074 GATE(PCLK_HDMI_HOST, "pclk_hdmi_host", "pclk_vo", 0,
1075 RK3568_CLKGATE_CON(21), 3, GFLAGS),
1076 GATE(CLK_HDMI_SFR, "clk_hdmi_sfr", "xin24m", 0,
1077 RK3568_CLKGATE_CON(21), 4, GFLAGS),
1078 GATE(CLK_HDMI_CEC, "clk_hdmi_cec", "clk_rtc_32k", 0,
1079 RK3568_CLKGATE_CON(21), 5, GFLAGS),
1080 GATE(PCLK_DSITX_0, "pclk_dsitx_0", "pclk_vo", 0,
1081 RK3568_CLKGATE_CON(21), 6, GFLAGS),
1082 GATE(PCLK_DSITX_1, "pclk_dsitx_1", "pclk_vo", 0,
1083 RK3568_CLKGATE_CON(21), 7, GFLAGS),
1084 GATE(PCLK_EDP_CTRL, "pclk_edp_ctrl", "pclk_vo", 0,
1085 RK3568_CLKGATE_CON(21), 8, GFLAGS),
1086 COMPOSITE_NODIV(CLK_EDP_200M, "clk_edp_200m", gpll200_gpll150_cpll125_p, 0,
1087 RK3568_CLKSEL_CON(38), 8, 2, MFLAGS,
1088 RK3568_CLKGATE_CON(21), 9, GFLAGS),
1089
1090 /* PD_VPU */
1091 COMPOSITE(ACLK_VPU_PRE, "aclk_vpu_pre", gpll_cpll_p, 0,
1092 RK3568_CLKSEL_CON(42), 7, 1, MFLAGS, 0, 5, DFLAGS,
1093 RK3568_CLKGATE_CON(22), 0, GFLAGS),
1094 COMPOSITE_NOMUX(HCLK_VPU_PRE, "hclk_vpu_pre", "aclk_vpu_pre", 0,
1095 RK3568_CLKSEL_CON(42), 8, 4, DFLAGS,
1096 RK3568_CLKGATE_CON(22), 1, GFLAGS),
1097 GATE(ACLK_VPU, "aclk_vpu", "aclk_vpu_pre", 0,
1098 RK3568_CLKGATE_CON(22), 4, GFLAGS),
1099 GATE(HCLK_VPU, "hclk_vpu", "hclk_vpu_pre", 0,
1100 RK3568_CLKGATE_CON(22), 5, GFLAGS),
1101
1102 /* PD_RGA */
1103 COMPOSITE_NODIV(ACLK_RGA_PRE, "aclk_rga_pre", gpll300_cpll250_gpll100_xin24m_p, 0,
1104 RK3568_CLKSEL_CON(43), 0, 2, MFLAGS,
1105 RK3568_CLKGATE_CON(23), 0, GFLAGS),
1106 COMPOSITE_NOMUX(HCLK_RGA_PRE, "hclk_rga_pre", "aclk_rga_pre", 0,
1107 RK3568_CLKSEL_CON(43), 8, 4, DFLAGS,
1108 RK3568_CLKGATE_CON(23), 1, GFLAGS),
1109 COMPOSITE_NOMUX(PCLK_RGA_PRE, "pclk_rga_pre", "aclk_rga_pre", 0,
1110 RK3568_CLKSEL_CON(43), 12, 4, DFLAGS,
1111 RK3568_CLKGATE_CON(22), 12, GFLAGS),
1112 GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre", 0,
1113 RK3568_CLKGATE_CON(23), 4, GFLAGS),
1114 GATE(HCLK_RGA, "hclk_rga", "hclk_rga_pre", 0,
1115 RK3568_CLKGATE_CON(23), 5, GFLAGS),
1116 COMPOSITE_NODIV(CLK_RGA_CORE, "clk_rga_core", gpll300_gpll200_gpll100_p, 0,
1117 RK3568_CLKSEL_CON(43), 2, 2, MFLAGS,
1118 RK3568_CLKGATE_CON(23), 6, GFLAGS),
1119 GATE(ACLK_IEP, "aclk_iep", "aclk_rga_pre", 0,
1120 RK3568_CLKGATE_CON(23), 7, GFLAGS),
1121 GATE(HCLK_IEP, "hclk_iep", "hclk_rga_pre", 0,
1122 RK3568_CLKGATE_CON(23), 8, GFLAGS),
1123 COMPOSITE_NODIV(CLK_IEP_CORE, "clk_iep_core", gpll300_gpll200_gpll100_p, 0,
1124 RK3568_CLKSEL_CON(43), 4, 2, MFLAGS,
1125 RK3568_CLKGATE_CON(23), 9, GFLAGS),
1126 GATE(HCLK_EBC, "hclk_ebc", "hclk_rga_pre", 0, RK3568_CLKGATE_CON(23), 10, GFLAGS),
1127 COMPOSITE_NODIV(DCLK_EBC, "dclk_ebc", gpll400_cpll333_gpll200_p, 0,
1128 RK3568_CLKSEL_CON(43), 6, 2, MFLAGS,
1129 RK3568_CLKGATE_CON(23), 11, GFLAGS),
1130 GATE(ACLK_JDEC, "aclk_jdec", "aclk_rga_pre", 0,
1131 RK3568_CLKGATE_CON(23), 12, GFLAGS),
1132 GATE(HCLK_JDEC, "hclk_jdec", "hclk_rga_pre", 0,
1133 RK3568_CLKGATE_CON(23), 13, GFLAGS),
1134 GATE(ACLK_JENC, "aclk_jenc", "aclk_rga_pre", 0,
1135 RK3568_CLKGATE_CON(23), 14, GFLAGS),
1136 GATE(HCLK_JENC, "hclk_jenc", "hclk_rga_pre", 0,
1137 RK3568_CLKGATE_CON(23), 15, GFLAGS),
1138 GATE(PCLK_EINK, "pclk_eink", "pclk_rga_pre", 0,
1139 RK3568_CLKGATE_CON(22), 14, GFLAGS),
1140 GATE(HCLK_EINK, "hclk_eink", "hclk_rga_pre", 0,
1141 RK3568_CLKGATE_CON(22), 15, GFLAGS),
1142
1143 /* PD_RKVENC */
1144 COMPOSITE(ACLK_RKVENC_PRE, "aclk_rkvenc_pre", gpll_cpll_npll_p, 0,
1145 RK3568_CLKSEL_CON(44), 6, 2, MFLAGS, 0, 5, DFLAGS,
1146 RK3568_CLKGATE_CON(24), 0, GFLAGS),
1147 COMPOSITE_NOMUX(HCLK_RKVENC_PRE, "hclk_rkvenc_pre", "aclk_rkvenc_pre", 0,
1148 RK3568_CLKSEL_CON(44), 8, 4, DFLAGS,
1149 RK3568_CLKGATE_CON(24), 1, GFLAGS),
1150 GATE(ACLK_RKVENC, "aclk_rkvenc", "aclk_rkvenc_pre", 0,
1151 RK3568_CLKGATE_CON(24), 6, GFLAGS),
1152 GATE(HCLK_RKVENC, "hclk_rkvenc", "hclk_rkvenc_pre", 0,
1153 RK3568_CLKGATE_CON(24), 7, GFLAGS),
1154 COMPOSITE(CLK_RKVENC_CORE, "clk_rkvenc_core", gpll_cpll_npll_vpll_p, 0,
1155 RK3568_CLKSEL_CON(45), 14, 2, MFLAGS, 0, 5, DFLAGS,
1156 RK3568_CLKGATE_CON(24), 8, GFLAGS),
1157 COMPOSITE(ACLK_RKVDEC_PRE, "aclk_rkvdec_pre", aclk_rkvdec_pre_p, CLK_SET_RATE_NO_REPARENT,
1158 RK3568_CLKSEL_CON(47), 7, 1, MFLAGS, 0, 5, DFLAGS,
1159 RK3568_CLKGATE_CON(25), 0, GFLAGS),
1160 COMPOSITE_NOMUX(HCLK_RKVDEC_PRE, "hclk_rkvdec_pre", "aclk_rkvdec_pre", 0,
1161 RK3568_CLKSEL_CON(47), 8, 4, DFLAGS,
1162 RK3568_CLKGATE_CON(25), 1, GFLAGS),
1163 GATE(ACLK_RKVDEC, "aclk_rkvdec", "aclk_rkvdec_pre", 0,
1164 RK3568_CLKGATE_CON(25), 4, GFLAGS),
1165 GATE(HCLK_RKVDEC, "hclk_rkvdec", "hclk_rkvdec_pre", 0,
1166 RK3568_CLKGATE_CON(25), 5, GFLAGS),
1167 COMPOSITE(CLK_RKVDEC_CA, "clk_rkvdec_ca", gpll_cpll_npll_vpll_p, 0,
1168 RK3568_CLKSEL_CON(48), 6, 2, MFLAGS, 0, 5, DFLAGS,
1169 RK3568_CLKGATE_CON(25), 6, GFLAGS),
1170 COMPOSITE(CLK_RKVDEC_CORE, "clk_rkvdec_core", clk_rkvdec_core_p, CLK_SET_RATE_NO_REPARENT,
1171 RK3568_CLKSEL_CON(49), 14, 2, MFLAGS, 8, 5, DFLAGS,
1172 RK3568_CLKGATE_CON(25), 7, GFLAGS),
1173 COMPOSITE(CLK_RKVDEC_HEVC_CA, "clk_rkvdec_hevc_ca", gpll_cpll_npll_vpll_p, 0,
1174 RK3568_CLKSEL_CON(49), 6, 2, MFLAGS, 0, 5, DFLAGS,
1175 RK3568_CLKGATE_CON(25), 8, GFLAGS),
1176
1177 /* PD_BUS */
1178 COMPOSITE_NODIV(ACLK_BUS, "aclk_bus", gpll200_gpll150_gpll100_xin24m_p, 0,
1179 RK3568_CLKSEL_CON(50), 0, 2, MFLAGS,
1180 RK3568_CLKGATE_CON(26), 0, GFLAGS),
1181 COMPOSITE_NODIV(PCLK_BUS, "pclk_bus", gpll100_gpll75_cpll50_xin24m_p, 0,
1182 RK3568_CLKSEL_CON(50), 4, 2, MFLAGS,
1183 RK3568_CLKGATE_CON(26), 1, GFLAGS),
1184 GATE(PCLK_TSADC, "pclk_tsadc", "pclk_bus", 0,
1185 RK3568_CLKGATE_CON(26), 4, GFLAGS),
1186 COMPOSITE(CLK_TSADC_TSEN, "clk_tsadc_tsen", xin24m_gpll100_cpll100_p, 0,
1187 RK3568_CLKSEL_CON(51), 4, 2, MFLAGS, 0, 3, DFLAGS,
1188 RK3568_CLKGATE_CON(26), 5, GFLAGS),
1189 COMPOSITE_NOMUX(CLK_TSADC, "clk_tsadc", "clk_tsadc_tsen", 0,
1190 RK3568_CLKSEL_CON(51), 8, 7, DFLAGS,
1191 RK3568_CLKGATE_CON(26), 6, GFLAGS),
1192 GATE(PCLK_SARADC, "pclk_saradc", "pclk_bus", 0,
1193 RK3568_CLKGATE_CON(26), 7, GFLAGS),
1194 GATE(CLK_SARADC, "clk_saradc", "xin24m", 0,
1195 RK3568_CLKGATE_CON(26), 8, GFLAGS),
1196 GATE(PCLK_SCR, "pclk_scr", "pclk_bus", CLK_IGNORE_UNUSED,
1197 RK3568_CLKGATE_CON(26), 12, GFLAGS),
1198 GATE(PCLK_WDT_NS, "pclk_wdt_ns", "pclk_bus", 0,
1199 RK3568_CLKGATE_CON(26), 13, GFLAGS),
1200 GATE(TCLK_WDT_NS, "tclk_wdt_ns", "xin24m", 0,
1201 RK3568_CLKGATE_CON(26), 14, GFLAGS),
1202 GATE(ACLK_MCU, "aclk_mcu", "aclk_bus", CLK_IGNORE_UNUSED,
1203 RK3568_CLKGATE_CON(32), 13, GFLAGS),
1204 GATE(PCLK_INTMUX, "pclk_intmux", "pclk_bus", CLK_IGNORE_UNUSED,
1205 RK3568_CLKGATE_CON(32), 14, GFLAGS),
1206 GATE(PCLK_MAILBOX, "pclk_mailbox", "pclk_bus", 0,
1207 RK3568_CLKGATE_CON(32), 15, GFLAGS),
1208
1209 GATE(PCLK_UART1, "pclk_uart1", "pclk_bus", 0,
1210 RK3568_CLKGATE_CON(27), 12, GFLAGS),
1211 COMPOSITE(CLK_UART1_SRC, "clk_uart1_src", gpll_cpll_usb480m_p, 0,
1212 RK3568_CLKSEL_CON(52), 8, 2, MFLAGS, 0, 7, DFLAGS,
1213 RK3568_CLKGATE_CON(27), 13, GFLAGS),
1214 COMPOSITE_FRACMUX(CLK_UART1_FRAC, "clk_uart1_frac", "clk_uart1_src", CLK_SET_RATE_PARENT,
1215 RK3568_CLKSEL_CON(53), 0,
1216 RK3568_CLKGATE_CON(27), 14, GFLAGS,
1217 &rk3568_uart1_fracmux),
1218 GATE(SCLK_UART1, "sclk_uart1", "sclk_uart1_mux", 0,
1219 RK3568_CLKGATE_CON(27), 15, GFLAGS),
1220
1221 GATE(PCLK_UART2, "pclk_uart2", "pclk_bus", 0,
1222 RK3568_CLKGATE_CON(28), 0, GFLAGS),
1223 COMPOSITE(CLK_UART2_SRC, "clk_uart2_src", gpll_cpll_usb480m_p, 0,
1224 RK3568_CLKSEL_CON(54), 8, 2, MFLAGS, 0, 7, DFLAGS,
1225 RK3568_CLKGATE_CON(28), 1, GFLAGS),
1226 COMPOSITE_FRACMUX(CLK_UART2_FRAC, "clk_uart2_frac", "clk_uart2_src", CLK_SET_RATE_PARENT,
1227 RK3568_CLKSEL_CON(55), 0,
1228 RK3568_CLKGATE_CON(28), 2, GFLAGS,
1229 &rk3568_uart2_fracmux),
1230 GATE(SCLK_UART2, "sclk_uart2", "sclk_uart2_mux", 0,
1231 RK3568_CLKGATE_CON(28), 3, GFLAGS),
1232
1233 GATE(PCLK_UART3, "pclk_uart3", "pclk_bus", 0,
1234 RK3568_CLKGATE_CON(28), 4, GFLAGS),
1235 COMPOSITE(CLK_UART3_SRC, "clk_uart3_src", gpll_cpll_usb480m_p, 0,
1236 RK3568_CLKSEL_CON(56), 8, 2, MFLAGS, 0, 7, DFLAGS,
1237 RK3568_CLKGATE_CON(28), 5, GFLAGS),
1238 COMPOSITE_FRACMUX(CLK_UART3_FRAC, "clk_uart3_frac", "clk_uart3_src", CLK_SET_RATE_PARENT,
1239 RK3568_CLKSEL_CON(57), 0,
1240 RK3568_CLKGATE_CON(28), 6, GFLAGS,
1241 &rk3568_uart3_fracmux),
1242 GATE(SCLK_UART3, "sclk_uart3", "sclk_uart3_mux", 0,
1243 RK3568_CLKGATE_CON(28), 7, GFLAGS),
1244
1245 GATE(PCLK_UART4, "pclk_uart4", "pclk_bus", 0,
1246 RK3568_CLKGATE_CON(28), 8, GFLAGS),
1247 COMPOSITE(CLK_UART4_SRC, "clk_uart4_src", gpll_cpll_usb480m_p, 0,
1248 RK3568_CLKSEL_CON(58), 8, 2, MFLAGS, 0, 7, DFLAGS,
1249 RK3568_CLKGATE_CON(28), 9, GFLAGS),
1250 COMPOSITE_FRACMUX(CLK_UART4_FRAC, "clk_uart4_frac", "clk_uart4_src", CLK_SET_RATE_PARENT,
1251 RK3568_CLKSEL_CON(59), 0,
1252 RK3568_CLKGATE_CON(28), 10, GFLAGS,
1253 &rk3568_uart4_fracmux),
1254 GATE(SCLK_UART4, "sclk_uart4", "sclk_uart4_mux", 0,
1255 RK3568_CLKGATE_CON(28), 11, GFLAGS),
1256
1257 GATE(PCLK_UART5, "pclk_uart5", "pclk_bus", 0,
1258 RK3568_CLKGATE_CON(28), 12, GFLAGS),
1259 COMPOSITE(CLK_UART5_SRC, "clk_uart5_src", gpll_cpll_usb480m_p, 0,
1260 RK3568_CLKSEL_CON(60), 8, 2, MFLAGS, 0, 7, DFLAGS,
1261 RK3568_CLKGATE_CON(28), 13, GFLAGS),
1262 COMPOSITE_FRACMUX(CLK_UART5_FRAC, "clk_uart5_frac", "clk_uart5_src", CLK_SET_RATE_PARENT,
1263 RK3568_CLKSEL_CON(61), 0,
1264 RK3568_CLKGATE_CON(28), 14, GFLAGS,
1265 &rk3568_uart5_fracmux),
1266 GATE(SCLK_UART5, "sclk_uart5", "sclk_uart5_mux", 0,
1267 RK3568_CLKGATE_CON(28), 15, GFLAGS),
1268
1269 GATE(PCLK_UART6, "pclk_uart6", "pclk_bus", 0,
1270 RK3568_CLKGATE_CON(29), 0, GFLAGS),
1271 COMPOSITE(CLK_UART6_SRC, "clk_uart6_src", gpll_cpll_usb480m_p, 0,
1272 RK3568_CLKSEL_CON(62), 8, 2, MFLAGS, 0, 7, DFLAGS,
1273 RK3568_CLKGATE_CON(29), 1, GFLAGS),
1274 COMPOSITE_FRACMUX(CLK_UART6_FRAC, "clk_uart6_frac", "clk_uart6_src", CLK_SET_RATE_PARENT,
1275 RK3568_CLKSEL_CON(63), 0,
1276 RK3568_CLKGATE_CON(29), 2, GFLAGS,
1277 &rk3568_uart6_fracmux),
1278 GATE(SCLK_UART6, "sclk_uart6", "sclk_uart6_mux", 0,
1279 RK3568_CLKGATE_CON(29), 3, GFLAGS),
1280
1281 GATE(PCLK_UART7, "pclk_uart7", "pclk_bus", 0,
1282 RK3568_CLKGATE_CON(29), 4, GFLAGS),
1283 COMPOSITE(CLK_UART7_SRC, "clk_uart7_src", gpll_cpll_usb480m_p, 0,
1284 RK3568_CLKSEL_CON(64), 8, 2, MFLAGS, 0, 7, DFLAGS,
1285 RK3568_CLKGATE_CON(29), 5, GFLAGS),
1286 COMPOSITE_FRACMUX(CLK_UART7_FRAC, "clk_uart7_frac", "clk_uart7_src", CLK_SET_RATE_PARENT,
1287 RK3568_CLKSEL_CON(65), 0,
1288 RK3568_CLKGATE_CON(29), 6, GFLAGS,
1289 &rk3568_uart7_fracmux),
1290 GATE(SCLK_UART7, "sclk_uart7", "sclk_uart7_mux", 0,
1291 RK3568_CLKGATE_CON(29), 7, GFLAGS),
1292
1293 GATE(PCLK_UART8, "pclk_uart8", "pclk_bus", 0,
1294 RK3568_CLKGATE_CON(29), 8, GFLAGS),
1295 COMPOSITE(CLK_UART8_SRC, "clk_uart8_src", gpll_cpll_usb480m_p, 0,
1296 RK3568_CLKSEL_CON(66), 8, 2, MFLAGS, 0, 7, DFLAGS,
1297 RK3568_CLKGATE_CON(29), 9, GFLAGS),
1298 COMPOSITE_FRACMUX(CLK_UART8_FRAC, "clk_uart8_frac", "clk_uart8_src", CLK_SET_RATE_PARENT,
1299 RK3568_CLKSEL_CON(67), 0,
1300 RK3568_CLKGATE_CON(29), 10, GFLAGS,
1301 &rk3568_uart8_fracmux),
1302 GATE(SCLK_UART8, "sclk_uart8", "sclk_uart8_mux", 0,
1303 RK3568_CLKGATE_CON(29), 11, GFLAGS),
1304
1305 GATE(PCLK_UART9, "pclk_uart9", "pclk_bus", 0,
1306 RK3568_CLKGATE_CON(29), 12, GFLAGS),
1307 COMPOSITE(CLK_UART9_SRC, "clk_uart9_src", gpll_cpll_usb480m_p, 0,
1308 RK3568_CLKSEL_CON(68), 8, 2, MFLAGS, 0, 7, DFLAGS,
1309 RK3568_CLKGATE_CON(29), 13, GFLAGS),
1310 COMPOSITE_FRACMUX(CLK_UART9_FRAC, "clk_uart9_frac", "clk_uart9_src", CLK_SET_RATE_PARENT,
1311 RK3568_CLKSEL_CON(69), 0,
1312 RK3568_CLKGATE_CON(29), 14, GFLAGS,
1313 &rk3568_uart9_fracmux),
1314 GATE(SCLK_UART9, "sclk_uart9", "sclk_uart9_mux", 0,
1315 RK3568_CLKGATE_CON(29), 15, GFLAGS),
1316
1317 GATE(PCLK_CAN0, "pclk_can0", "pclk_bus", 0,
1318 RK3568_CLKGATE_CON(27), 5, GFLAGS),
1319 COMPOSITE(CLK_CAN0, "clk_can0", gpll_cpll_p, 0,
1320 RK3568_CLKSEL_CON(70), 7, 1, MFLAGS, 0, 5, DFLAGS,
1321 RK3568_CLKGATE_CON(27), 6, GFLAGS),
1322 GATE(PCLK_CAN1, "pclk_can1", "pclk_bus", 0,
1323 RK3568_CLKGATE_CON(27), 7, GFLAGS),
1324 COMPOSITE(CLK_CAN1, "clk_can1", gpll_cpll_p, 0,
1325 RK3568_CLKSEL_CON(70), 15, 1, MFLAGS, 8, 5, DFLAGS,
1326 RK3568_CLKGATE_CON(27), 8, GFLAGS),
1327 GATE(PCLK_CAN2, "pclk_can2", "pclk_bus", 0,
1328 RK3568_CLKGATE_CON(27), 9, GFLAGS),
1329 COMPOSITE(CLK_CAN2, "clk_can2", gpll_cpll_p, 0,
1330 RK3568_CLKSEL_CON(71), 7, 1, MFLAGS, 0, 5, DFLAGS,
1331 RK3568_CLKGATE_CON(27), 10, GFLAGS),
1332 COMPOSITE_NODIV(CLK_I2C, "clk_i2c", clk_i2c_p, 0,
1333 RK3568_CLKSEL_CON(71), 8, 2, MFLAGS,
1334 RK3568_CLKGATE_CON(32), 10, GFLAGS),
1335 GATE(PCLK_I2C1, "pclk_i2c1", "pclk_bus", 0,
1336 RK3568_CLKGATE_CON(30), 0, GFLAGS),
1337 GATE(CLK_I2C1, "clk_i2c1", "clk_i2c", 0,
1338 RK3568_CLKGATE_CON(30), 1, GFLAGS),
1339 GATE(PCLK_I2C2, "pclk_i2c2", "pclk_bus", 0,
1340 RK3568_CLKGATE_CON(30), 2, GFLAGS),
1341 GATE(CLK_I2C2, "clk_i2c2", "clk_i2c", 0,
1342 RK3568_CLKGATE_CON(30), 3, GFLAGS),
1343 GATE(PCLK_I2C3, "pclk_i2c3", "pclk_bus", 0,
1344 RK3568_CLKGATE_CON(30), 4, GFLAGS),
1345 GATE(CLK_I2C3, "clk_i2c3", "clk_i2c", 0,
1346 RK3568_CLKGATE_CON(30), 5, GFLAGS),
1347 GATE(PCLK_I2C4, "pclk_i2c4", "pclk_bus", 0,
1348 RK3568_CLKGATE_CON(30), 6, GFLAGS),
1349 GATE(CLK_I2C4, "clk_i2c4", "clk_i2c", 0,
1350 RK3568_CLKGATE_CON(30), 7, GFLAGS),
1351 GATE(PCLK_I2C5, "pclk_i2c5", "pclk_bus", 0,
1352 RK3568_CLKGATE_CON(30), 8, GFLAGS),
1353 GATE(CLK_I2C5, "clk_i2c5", "clk_i2c", 0,
1354 RK3568_CLKGATE_CON(30), 9, GFLAGS),
1355 GATE(PCLK_SPI0, "pclk_spi0", "pclk_bus", 0,
1356 RK3568_CLKGATE_CON(30), 10, GFLAGS),
1357 COMPOSITE_NODIV(CLK_SPI0, "clk_spi0", gpll200_xin24m_cpll100_p, 0,
1358 RK3568_CLKSEL_CON(72), 0, 1, MFLAGS,
1359 RK3568_CLKGATE_CON(30), 11, GFLAGS),
1360 GATE(PCLK_SPI1, "pclk_spi1", "pclk_bus", 0,
1361 RK3568_CLKGATE_CON(30), 12, GFLAGS),
1362 COMPOSITE_NODIV(CLK_SPI1, "clk_spi1", gpll200_xin24m_cpll100_p, 0,
1363 RK3568_CLKSEL_CON(72), 2, 1, MFLAGS,
1364 RK3568_CLKGATE_CON(30), 13, GFLAGS),
1365 GATE(PCLK_SPI2, "pclk_spi2", "pclk_bus", 0,
1366 RK3568_CLKGATE_CON(30), 14, GFLAGS),
1367 COMPOSITE_NODIV(CLK_SPI2, "clk_spi2", gpll200_xin24m_cpll100_p, 0,
1368 RK3568_CLKSEL_CON(72), 4, 1, MFLAGS,
1369 RK3568_CLKGATE_CON(30), 15, GFLAGS),
1370 GATE(PCLK_SPI3, "pclk_spi3", "pclk_bus", 0,
1371 RK3568_CLKGATE_CON(31), 0, GFLAGS),
1372 COMPOSITE_NODIV(CLK_SPI3, "clk_spi3", gpll200_xin24m_cpll100_p, 0,
1373 RK3568_CLKSEL_CON(72), 6, 1, MFLAGS, RK3568_CLKGATE_CON(31), 1, GFLAGS),
1374 GATE(PCLK_PWM1, "pclk_pwm1", "pclk_bus", 0, RK3568_CLKGATE_CON(31), 10, GFLAGS),
1375 COMPOSITE_NODIV(CLK_PWM1, "clk_pwm1", gpll100_xin24m_cpll100_p, 0,
1376 RK3568_CLKSEL_CON(72), 8, 1, MFLAGS,
1377 RK3568_CLKGATE_CON(31), 11, GFLAGS),
1378 GATE(CLK_PWM1_CAPTURE, "clk_pwm1_capture", "xin24m", 0,
1379 RK3568_CLKGATE_CON(31), 12, GFLAGS),
1380 GATE(PCLK_PWM2, "pclk_pwm2", "pclk_bus", 0,
1381 RK3568_CLKGATE_CON(31), 13, GFLAGS),
1382 COMPOSITE_NODIV(CLK_PWM2, "clk_pwm2", gpll100_xin24m_cpll100_p, 0,
1383 RK3568_CLKSEL_CON(72), 10, 1, MFLAGS,
1384 RK3568_CLKGATE_CON(31), 14, GFLAGS),
1385 GATE(CLK_PWM2_CAPTURE, "clk_pwm2_capture", "xin24m", 0,
1386 RK3568_CLKGATE_CON(31), 15, GFLAGS),
1387 GATE(PCLK_PWM3, "pclk_pwm3", "pclk_bus", 0,
1388 RK3568_CLKGATE_CON(32), 0, GFLAGS),
1389 COMPOSITE_NODIV(CLK_PWM3, "clk_pwm3", gpll100_xin24m_cpll100_p, 0,
1390 RK3568_CLKSEL_CON(72), 12, 1, MFLAGS,
1391 RK3568_CLKGATE_CON(32), 1, GFLAGS),
1392 GATE(CLK_PWM3_CAPTURE, "clk_pwm3_capture", "xin24m", 0,
1393 RK3568_CLKGATE_CON(32), 2, GFLAGS),
1394 COMPOSITE_NODIV(DBCLK_GPIO, "dbclk_gpio", xin24m_32k_p, 0,
1395 RK3568_CLKSEL_CON(72), 14, 1, MFLAGS,
1396 RK3568_CLKGATE_CON(32), 11, GFLAGS),
1397 GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_bus", 0,
1398 RK3568_CLKGATE_CON(31), 2, GFLAGS),
1399 GATE(DBCLK_GPIO1, "dbclk_gpio1", "dbclk_gpio", 0,
1400 RK3568_CLKGATE_CON(31), 3, GFLAGS),
1401 GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_bus", 0,
1402 RK3568_CLKGATE_CON(31), 4, GFLAGS),
1403 GATE(DBCLK_GPIO2, "dbclk_gpio2", "dbclk_gpio", 0,
1404 RK3568_CLKGATE_CON(31), 5, GFLAGS),
1405 GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_bus", 0,
1406 RK3568_CLKGATE_CON(31), 6, GFLAGS),
1407 GATE(DBCLK_GPIO3, "dbclk_gpio3", "dbclk_gpio", 0,
1408 RK3568_CLKGATE_CON(31), 7, GFLAGS),
1409 GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_bus", 0,
1410 RK3568_CLKGATE_CON(31), 8, GFLAGS),
1411 GATE(DBCLK_GPIO4, "dbclk_gpio4", "dbclk_gpio", 0,
1412 RK3568_CLKGATE_CON(31), 9, GFLAGS),
1413 GATE(PCLK_TIMER, "pclk_timer", "pclk_bus", 0,
1414 RK3568_CLKGATE_CON(32), 3, GFLAGS),
1415 GATE(CLK_TIMER0, "clk_timer0", "xin24m", 0,
1416 RK3568_CLKGATE_CON(32), 4, GFLAGS),
1417 GATE(CLK_TIMER1, "clk_timer1", "xin24m", 0,
1418 RK3568_CLKGATE_CON(32), 5, GFLAGS),
1419 GATE(CLK_TIMER2, "clk_timer2", "xin24m", 0,
1420 RK3568_CLKGATE_CON(32), 6, GFLAGS),
1421 GATE(CLK_TIMER3, "clk_timer3", "xin24m", 0,
1422 RK3568_CLKGATE_CON(32), 7, GFLAGS),
1423 GATE(CLK_TIMER4, "clk_timer4", "xin24m", 0,
1424 RK3568_CLKGATE_CON(32), 8, GFLAGS),
1425 GATE(CLK_TIMER5, "clk_timer5", "xin24m", 0,
1426 RK3568_CLKGATE_CON(32), 9, GFLAGS),
1427
1428 /* PD_TOP */
1429 COMPOSITE_NODIV(ACLK_TOP_HIGH, "aclk_top_high", cpll500_gpll400_gpll300_xin24m_p, 0,
1430 RK3568_CLKSEL_CON(73), 0, 2, MFLAGS,
1431 RK3568_CLKGATE_CON(33), 0, GFLAGS),
1432 COMPOSITE_NODIV(ACLK_TOP_LOW, "aclk_top_low", gpll400_gpll300_gpll200_xin24m_p, 0,
1433 RK3568_CLKSEL_CON(73), 4, 2, MFLAGS,
1434 RK3568_CLKGATE_CON(33), 1, GFLAGS),
1435 COMPOSITE_NODIV(HCLK_TOP, "hclk_top", gpll150_gpll100_gpll75_xin24m_p, 0,
1436 RK3568_CLKSEL_CON(73), 8, 2, MFLAGS,
1437 RK3568_CLKGATE_CON(33), 2, GFLAGS),
1438 COMPOSITE_NODIV(PCLK_TOP, "pclk_top", gpll100_gpll75_cpll50_xin24m_p, 0,
1439 RK3568_CLKSEL_CON(73), 12, 2, MFLAGS,
1440 RK3568_CLKGATE_CON(33), 3, GFLAGS),
1441 GATE(PCLK_PCIE30PHY, "pclk_pcie30phy", "pclk_top", 0,
1442 RK3568_CLKGATE_CON(33), 8, GFLAGS),
1443 COMPOSITE_NODIV(CLK_OPTC_ARB, "clk_optc_arb", xin24m_cpll100_p, 0,
1444 RK3568_CLKSEL_CON(73), 15, 1, MFLAGS,
1445 RK3568_CLKGATE_CON(33), 9, GFLAGS),
1446 GATE(PCLK_MIPICSIPHY, "pclk_mipicsiphy", "pclk_top", 0,
1447 RK3568_CLKGATE_CON(33), 13, GFLAGS),
1448 GATE(PCLK_MIPIDSIPHY0, "pclk_mipidsiphy0", "pclk_top", 0,
1449 RK3568_CLKGATE_CON(33), 14, GFLAGS),
1450 GATE(PCLK_MIPIDSIPHY1, "pclk_mipidsiphy1", "pclk_top", 0,
1451 RK3568_CLKGATE_CON(33), 15, GFLAGS),
1452 GATE(PCLK_PIPEPHY0, "pclk_pipephy0", "pclk_top", 0,
1453 RK3568_CLKGATE_CON(34), 4, GFLAGS),
1454 GATE(PCLK_PIPEPHY1, "pclk_pipephy1", "pclk_top", 0,
1455 RK3568_CLKGATE_CON(34), 5, GFLAGS),
1456 GATE(PCLK_PIPEPHY2, "pclk_pipephy2", "pclk_top", 0,
1457 RK3568_CLKGATE_CON(34), 6, GFLAGS),
1458 GATE(PCLK_CPU_BOOST, "pclk_cpu_boost", "pclk_top", 0,
1459 RK3568_CLKGATE_CON(34), 11, GFLAGS),
1460 GATE(CLK_CPU_BOOST, "clk_cpu_boost", "xin24m", 0,
1461 RK3568_CLKGATE_CON(34), 12, GFLAGS),
1462 GATE(PCLK_OTPPHY, "pclk_otpphy", "pclk_top", 0,
1463 RK3568_CLKGATE_CON(34), 13, GFLAGS),
1464 GATE(PCLK_EDPPHY_GRF, "pclk_edpphy_grf", "pclk_top", 0,
1465 RK3568_CLKGATE_CON(34), 14, GFLAGS),
1466 };
1467
1468 static struct rockchip_clk_branch rk3568_clk_pmu_branches[] __initdata = {
1469 /* PD_PMU */
1470 FACTOR(0, "ppll_ph0", "ppll", 0, 1, 2),
1471 FACTOR(0, "ppll_ph180", "ppll", 0, 1, 2),
1472 FACTOR(0, "hpll_ph0", "hpll", 0, 1, 2),
1473
1474 MUX(CLK_PDPMU, "clk_pdpmu", clk_pdpmu_p, 0,
1475 RK3568_PMU_CLKSEL_CON(2), 15, 1, MFLAGS),
1476 COMPOSITE_NOMUX(PCLK_PDPMU, "pclk_pdpmu", "clk_pdpmu", 0,
1477 RK3568_PMU_CLKSEL_CON(2), 0, 5, DFLAGS,
1478 RK3568_PMU_CLKGATE_CON(0), 2, GFLAGS),
1479 GATE(PCLK_PMU, "pclk_pmu", "pclk_pdpmu", 0,
1480 RK3568_PMU_CLKGATE_CON(0), 6, GFLAGS),
1481 GATE(CLK_PMU, "clk_pmu", "xin24m", 0,
1482 RK3568_PMU_CLKGATE_CON(0), 7, GFLAGS),
1483 GATE(PCLK_I2C0, "pclk_i2c0", "pclk_pdpmu", 0,
1484 RK3568_PMU_CLKGATE_CON(1), 0, GFLAGS),
1485 COMPOSITE_NOMUX(CLK_I2C0, "clk_i2c0", "clk_pdpmu", 0,
1486 RK3568_PMU_CLKSEL_CON(3), 0, 7, DFLAGS,
1487 RK3568_PMU_CLKGATE_CON(1), 1, GFLAGS),
1488 GATE(PCLK_UART0, "pclk_uart0", "pclk_pdpmu", 0,
1489 RK3568_PMU_CLKGATE_CON(1), 2, GFLAGS),
1490
1491 COMPOSITE_FRACMUX(CLK_RTC32K_FRAC, "clk_rtc32k_frac", "xin24m", CLK_IGNORE_UNUSED,
1492 RK3568_PMU_CLKSEL_CON(1), 0,
1493 RK3568_PMU_CLKGATE_CON(0), 1, GFLAGS,
1494 &rk3568_rtc32k_pmu_fracmux),
1495
1496 COMPOSITE_NOMUX(XIN_OSC0_DIV, "xin_osc0_div", "xin24m", CLK_IGNORE_UNUSED,
1497 RK3568_PMU_CLKSEL_CON(0), 0, 5, DFLAGS,
1498 RK3568_PMU_CLKGATE_CON(0), 0, GFLAGS),
1499
1500 COMPOSITE(CLK_UART0_DIV, "sclk_uart0_div", ppll_usb480m_cpll_gpll_p, 0,
1501 RK3568_PMU_CLKSEL_CON(4), 8, 2, MFLAGS, 0, 7, DFLAGS,
1502 RK3568_PMU_CLKGATE_CON(1), 3, GFLAGS),
1503 COMPOSITE_FRACMUX(CLK_UART0_FRAC, "sclk_uart0_frac", "sclk_uart0_div", CLK_SET_RATE_PARENT,
1504 RK3568_PMU_CLKSEL_CON(5), 0,
1505 RK3568_PMU_CLKGATE_CON(1), 4, GFLAGS,
1506 &rk3568_uart0_fracmux),
1507 GATE(SCLK_UART0, "sclk_uart0", "sclk_uart0_mux", 0,
1508 RK3568_PMU_CLKGATE_CON(1), 5, GFLAGS),
1509
1510 GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_pdpmu", 0,
1511 RK3568_PMU_CLKGATE_CON(1), 9, GFLAGS),
1512 COMPOSITE_NODIV(DBCLK_GPIO0, "dbclk_gpio0", xin24m_32k_p, 0,
1513 RK3568_PMU_CLKSEL_CON(6), 15, 1, MFLAGS,
1514 RK3568_PMU_CLKGATE_CON(1), 10, GFLAGS),
1515 GATE(PCLK_PWM0, "pclk_pwm0", "pclk_pdpmu", 0,
1516 RK3568_PMU_CLKGATE_CON(1), 6, GFLAGS),
1517 COMPOSITE(CLK_PWM0, "clk_pwm0", clk_pwm0_p, 0,
1518 RK3568_PMU_CLKSEL_CON(6), 7, 1, MFLAGS, 0, 7, DFLAGS,
1519 RK3568_PMU_CLKGATE_CON(1), 7, GFLAGS),
1520 GATE(CLK_CAPTURE_PWM0_NDFT, "clk_capture_pwm0_ndft", "xin24m", 0,
1521 RK3568_PMU_CLKGATE_CON(1), 8, GFLAGS),
1522 GATE(PCLK_PMUPVTM, "pclk_pmupvtm", "pclk_pdpmu", 0,
1523 RK3568_PMU_CLKGATE_CON(1), 11, GFLAGS),
1524 GATE(CLK_PMUPVTM, "clk_pmupvtm", "xin24m", 0,
1525 RK3568_PMU_CLKGATE_CON(1), 12, GFLAGS),
1526 GATE(CLK_CORE_PMUPVTM, "clk_core_pmupvtm", "xin24m", 0,
1527 RK3568_PMU_CLKGATE_CON(1), 13, GFLAGS),
1528 COMPOSITE_NOMUX(CLK_REF24M, "clk_ref24m", "clk_pdpmu", 0,
1529 RK3568_PMU_CLKSEL_CON(7), 0, 6, DFLAGS,
1530 RK3568_PMU_CLKGATE_CON(2), 0, GFLAGS),
1531 GATE(XIN_OSC0_USBPHY0_G, "xin_osc0_usbphy0_g", "xin24m", 0,
1532 RK3568_PMU_CLKGATE_CON(2), 1, GFLAGS),
1533 MUX(CLK_USBPHY0_REF, "clk_usbphy0_ref", clk_usbphy0_ref_p, 0,
1534 RK3568_PMU_CLKSEL_CON(8), 0, 1, MFLAGS),
1535 GATE(XIN_OSC0_USBPHY1_G, "xin_osc0_usbphy1_g", "xin24m", 0,
1536 RK3568_PMU_CLKGATE_CON(2), 2, GFLAGS),
1537 MUX(CLK_USBPHY1_REF, "clk_usbphy1_ref", clk_usbphy1_ref_p, 0,
1538 RK3568_PMU_CLKSEL_CON(8), 1, 1, MFLAGS),
1539 GATE(XIN_OSC0_MIPIDSIPHY0_G, "xin_osc0_mipidsiphy0_g", "xin24m", 0,
1540 RK3568_PMU_CLKGATE_CON(2), 3, GFLAGS),
1541 MUX(CLK_MIPIDSIPHY0_REF, "clk_mipidsiphy0_ref", clk_mipidsiphy0_ref_p, 0,
1542 RK3568_PMU_CLKSEL_CON(8), 2, 1, MFLAGS),
1543 GATE(XIN_OSC0_MIPIDSIPHY1_G, "xin_osc0_mipidsiphy1_g", "xin24m", 0,
1544 RK3568_PMU_CLKGATE_CON(2), 4, GFLAGS),
1545 MUX(CLK_MIPIDSIPHY1_REF, "clk_mipidsiphy1_ref", clk_mipidsiphy1_ref_p, 0,
1546 RK3568_PMU_CLKSEL_CON(8), 3, 1, MFLAGS),
1547 COMPOSITE_NOMUX(CLK_WIFI_DIV, "clk_wifi_div", "clk_pdpmu", 0,
1548 RK3568_PMU_CLKSEL_CON(8), 8, 6, DFLAGS,
1549 RK3568_PMU_CLKGATE_CON(2), 5, GFLAGS),
1550 GATE(CLK_WIFI_OSC0, "clk_wifi_osc0", "xin24m", 0,
1551 RK3568_PMU_CLKGATE_CON(2), 6, GFLAGS),
1552 MUX(CLK_WIFI, "clk_wifi", clk_wifi_p, CLK_SET_RATE_PARENT,
1553 RK3568_PMU_CLKSEL_CON(8), 15, 1, MFLAGS),
1554 COMPOSITE_NOMUX(CLK_PCIEPHY0_DIV, "clk_pciephy0_div", "ppll_ph0", 0,
1555 RK3568_PMU_CLKSEL_CON(9), 0, 3, DFLAGS,
1556 RK3568_PMU_CLKGATE_CON(2), 7, GFLAGS),
1557 GATE(CLK_PCIEPHY0_OSC0, "clk_pciephy0_osc0", "xin24m", 0,
1558 RK3568_PMU_CLKGATE_CON(2), 8, GFLAGS),
1559 MUX(CLK_PCIEPHY0_REF, "clk_pciephy0_ref", clk_pciephy0_ref_p, CLK_SET_RATE_PARENT,
1560 RK3568_PMU_CLKSEL_CON(9), 3, 1, MFLAGS),
1561 COMPOSITE_NOMUX(CLK_PCIEPHY1_DIV, "clk_pciephy1_div", "ppll_ph0", 0,
1562 RK3568_PMU_CLKSEL_CON(9), 4, 3, DFLAGS,
1563 RK3568_PMU_CLKGATE_CON(2), 9, GFLAGS),
1564 GATE(CLK_PCIEPHY1_OSC0, "clk_pciephy1_osc0", "xin24m", 0,
1565 RK3568_PMU_CLKGATE_CON(2), 10, GFLAGS),
1566 MUX(CLK_PCIEPHY1_REF, "clk_pciephy1_ref", clk_pciephy1_ref_p, CLK_SET_RATE_PARENT,
1567 RK3568_PMU_CLKSEL_CON(9), 7, 1, MFLAGS),
1568 COMPOSITE_NOMUX(CLK_PCIEPHY2_DIV, "clk_pciephy2_div", "ppll_ph0", 0,
1569 RK3568_PMU_CLKSEL_CON(9), 8, 3, DFLAGS,
1570 RK3568_PMU_CLKGATE_CON(2), 11, GFLAGS),
1571 GATE(CLK_PCIEPHY2_OSC0, "clk_pciephy2_osc0", "xin24m", 0,
1572 RK3568_PMU_CLKGATE_CON(2), 12, GFLAGS),
1573 MUX(CLK_PCIEPHY2_REF, "clk_pciephy2_ref", clk_pciephy2_ref_p, CLK_SET_RATE_PARENT,
1574 RK3568_PMU_CLKSEL_CON(9), 11, 1, MFLAGS),
1575 GATE(CLK_PCIE30PHY_REF_M, "clk_pcie30phy_ref_m", "ppll_ph0", 0,
1576 RK3568_PMU_CLKGATE_CON(2), 13, GFLAGS),
1577 GATE(CLK_PCIE30PHY_REF_N, "clk_pcie30phy_ref_n", "ppll_ph180", 0,
1578 RK3568_PMU_CLKGATE_CON(2), 14, GFLAGS),
1579 GATE(XIN_OSC0_EDPPHY_G, "xin_osc0_edpphy_g", "xin24m", 0,
1580 RK3568_PMU_CLKGATE_CON(2), 15, GFLAGS),
1581 MUX(CLK_HDMI_REF, "clk_hdmi_ref", clk_hdmi_ref_p, CLK_SET_RATE_PARENT,
1582 RK3568_PMU_CLKSEL_CON(8), 7, 1, MFLAGS),
1583 };
1584
1585 static const char *const rk3568_cru_critical_clocks[] __initconst = {
1586 "armclk",
1587 "pclk_core_pre",
1588 "aclk_bus",
1589 "pclk_bus",
1590 "aclk_top_high",
1591 "aclk_top_low",
1592 "hclk_top",
1593 "pclk_top",
1594 "aclk_perimid",
1595 "hclk_perimid",
1596 "aclk_secure_flash",
1597 "hclk_secure_flash",
1598 "aclk_core_niu2bus",
1599 "npll",
1600 "clk_optc_arb",
1601 "hclk_php",
1602 "pclk_php",
1603 "hclk_usb",
1604 "pclk_usb",
1605 "hclk_vo",
1606 };
1607
1608 static const char *const rk3568_pmucru_critical_clocks[] __initconst = {
1609 "pclk_pdpmu",
1610 "pclk_pmu",
1611 "clk_pmu",
1612 };
1613
rk3568_pmu_clk_init(struct device_node * np)1614 static void __init rk3568_pmu_clk_init(struct device_node *np)
1615 {
1616 struct rockchip_clk_provider *ctx;
1617 void __iomem *reg_base;
1618
1619 reg_base = of_iomap(np, 0);
1620 if (!reg_base) {
1621 pr_err("%s: could not map cru pmu region\n", __func__);
1622 return;
1623 }
1624
1625 ctx = rockchip_clk_init(np, reg_base, CLKPMU_NR_CLKS);
1626 if (IS_ERR(ctx)) {
1627 pr_err("%s: rockchip pmu clk init failed\n", __func__);
1628 return;
1629 }
1630
1631 rockchip_clk_register_plls(ctx, rk3568_pmu_pll_clks,
1632 ARRAY_SIZE(rk3568_pmu_pll_clks),
1633 RK3568_GRF_SOC_STATUS0);
1634
1635 rockchip_clk_register_branches(ctx, rk3568_clk_pmu_branches,
1636 ARRAY_SIZE(rk3568_clk_pmu_branches));
1637
1638 rockchip_register_softrst(np, 1, reg_base + RK3568_PMU_SOFTRST_CON(0),
1639 ROCKCHIP_SOFTRST_HIWORD_MASK);
1640
1641 rockchip_clk_protect_critical(rk3568_pmucru_critical_clocks,
1642 ARRAY_SIZE(rk3568_pmucru_critical_clocks));
1643
1644 rockchip_clk_of_add_provider(np, ctx);
1645 }
1646
1647 CLK_OF_DECLARE(rk3568_cru_pmu, "rockchip,rk3568-pmucru", rk3568_pmu_clk_init);
1648
rk3568_clk_init(struct device_node * np)1649 static void __init rk3568_clk_init(struct device_node *np)
1650 {
1651 struct rockchip_clk_provider *ctx;
1652 void __iomem *reg_base;
1653
1654 reg_base = of_iomap(np, 0);
1655 if (!reg_base) {
1656 pr_err("%s: could not map cru region\n", __func__);
1657 return;
1658 }
1659
1660 ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
1661 if (IS_ERR(ctx)) {
1662 pr_err("%s: rockchip clk init failed\n", __func__);
1663 iounmap(reg_base);
1664 return;
1665 }
1666
1667 rockchip_clk_register_plls(ctx, rk3568_pll_clks,
1668 ARRAY_SIZE(rk3568_pll_clks),
1669 RK3568_GRF_SOC_STATUS0);
1670
1671 rockchip_clk_register_armclk(ctx, ARMCLK, "armclk",
1672 mux_armclk_p, ARRAY_SIZE(mux_armclk_p),
1673 &rk3568_cpuclk_data, rk3568_cpuclk_rates,
1674 ARRAY_SIZE(rk3568_cpuclk_rates));
1675
1676 rockchip_clk_register_branches(ctx, rk3568_clk_branches,
1677 ARRAY_SIZE(rk3568_clk_branches));
1678
1679 rockchip_register_softrst(np, 30, reg_base + RK3568_SOFTRST_CON(0),
1680 ROCKCHIP_SOFTRST_HIWORD_MASK);
1681
1682 rockchip_register_restart_notifier(ctx, RK3568_GLB_SRST_FST, NULL);
1683
1684 rockchip_clk_protect_critical(rk3568_cru_critical_clocks,
1685 ARRAY_SIZE(rk3568_cru_critical_clocks));
1686
1687 rockchip_clk_of_add_provider(np, ctx);
1688 }
1689
1690 CLK_OF_DECLARE(rk3568_cru, "rockchip,rk3568-cru", rk3568_clk_init);
1691
1692 struct clk_rk3568_inits {
1693 void (*inits)(struct device_node *np);
1694 };
1695
1696 static const struct clk_rk3568_inits clk_rk3568_pmucru_init = {
1697 .inits = rk3568_pmu_clk_init,
1698 };
1699
1700 static const struct clk_rk3568_inits clk_3568_cru_init = {
1701 .inits = rk3568_clk_init,
1702 };
1703
1704 static const struct of_device_id clk_rk3568_match_table[] = {
1705 {
1706 .compatible = "rockchip,rk3568-cru",
1707 .data = &clk_3568_cru_init,
1708 }, {
1709 .compatible = "rockchip,rk3568-pmucru",
1710 .data = &clk_rk3568_pmucru_init,
1711 },
1712 { }
1713 };
1714
clk_rk3568_probe(struct platform_device * pdev)1715 static int __init clk_rk3568_probe(struct platform_device *pdev)
1716 {
1717 struct device_node *np = pdev->dev.of_node;
1718 const struct clk_rk3568_inits *init_data;
1719
1720 init_data = (struct clk_rk3568_inits *)of_device_get_match_data(&pdev->dev);
1721 if (!init_data)
1722 return -EINVAL;
1723
1724 if (init_data->inits)
1725 init_data->inits(np);
1726
1727 return 0;
1728 }
1729
1730 static struct platform_driver clk_rk3568_driver = {
1731 .driver = {
1732 .name = "clk-rk3568",
1733 .of_match_table = clk_rk3568_match_table,
1734 .suppress_bind_attrs = true,
1735 },
1736 };
1737 builtin_platform_driver_probe(clk_rk3568_driver, clk_rk3568_probe);
1738