1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2021 Rockchip Electronics Co. Ltd. 4 * Author: Elaine Zhang <zhangqing@rock-chips.com> 5 */ 6 7 #include <linux/clk-provider.h> 8 #include <linux/module.h> 9 #include <linux/of.h> 10 #include <linux/of_address.h> 11 #include <linux/platform_device.h> 12 #include <linux/syscore_ops.h> 13 #include <dt-bindings/clock/rk3568-cru.h> 14 #include "clk.h" 15 16 #define RK3568_GRF_SOC_STATUS0 0x580 17 18 enum rk3568_pmu_plls { 19 ppll, hpll, 20 }; 21 22 enum rk3568_plls { 23 apll, dpll, gpll, cpll, npll, vpll, 24 }; 25 26 static struct rockchip_pll_rate_table rk3568_pll_rates[] = { 27 /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */ 28 RK3036_PLL_RATE(2208000000, 1, 92, 1, 1, 1, 0), 29 RK3036_PLL_RATE(2184000000, 1, 91, 1, 1, 1, 0), 30 RK3036_PLL_RATE(2160000000, 1, 90, 1, 1, 1, 0), 31 RK3036_PLL_RATE(2088000000, 1, 87, 1, 1, 1, 0), 32 RK3036_PLL_RATE(2064000000, 1, 86, 1, 1, 1, 0), 33 RK3036_PLL_RATE(2040000000, 1, 85, 1, 1, 1, 0), 34 RK3036_PLL_RATE(2016000000, 1, 84, 1, 1, 1, 0), 35 RK3036_PLL_RATE(1992000000, 1, 83, 1, 1, 1, 0), 36 RK3036_PLL_RATE(1920000000, 1, 80, 1, 1, 1, 0), 37 RK3036_PLL_RATE(1896000000, 1, 79, 1, 1, 1, 0), 38 RK3036_PLL_RATE(1800000000, 1, 75, 1, 1, 1, 0), 39 RK3036_PLL_RATE(1704000000, 1, 71, 1, 1, 1, 0), 40 RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0), 41 RK3036_PLL_RATE(1600000000, 3, 200, 1, 1, 1, 0), 42 RK3036_PLL_RATE(1584000000, 1, 132, 2, 1, 1, 0), 43 RK3036_PLL_RATE(1560000000, 1, 130, 2, 1, 1, 0), 44 RK3036_PLL_RATE(1536000000, 1, 128, 2, 1, 1, 0), 45 RK3036_PLL_RATE(1512000000, 1, 126, 2, 1, 1, 0), 46 RK3036_PLL_RATE(1488000000, 1, 124, 2, 1, 1, 0), 47 RK3036_PLL_RATE(1464000000, 1, 122, 2, 1, 1, 0), 48 RK3036_PLL_RATE(1440000000, 1, 120, 2, 1, 1, 0), 49 RK3036_PLL_RATE(1416000000, 1, 118, 2, 1, 1, 0), 50 RK3036_PLL_RATE(1400000000, 3, 350, 2, 1, 1, 0), 51 RK3036_PLL_RATE(1392000000, 1, 116, 2, 1, 1, 0), 52 RK3036_PLL_RATE(1368000000, 1, 114, 2, 1, 1, 0), 53 RK3036_PLL_RATE(1344000000, 1, 112, 2, 1, 1, 0), 54 RK3036_PLL_RATE(1320000000, 1, 110, 2, 1, 1, 0), 55 RK3036_PLL_RATE(1296000000, 1, 108, 2, 1, 1, 0), 56 RK3036_PLL_RATE(1272000000, 1, 106, 2, 1, 1, 0), 57 RK3036_PLL_RATE(1248000000, 1, 104, 2, 1, 1, 0), 58 RK3036_PLL_RATE(1200000000, 1, 100, 2, 1, 1, 0), 59 RK3036_PLL_RATE(1188000000, 1, 99, 2, 1, 1, 0), 60 RK3036_PLL_RATE(1104000000, 1, 92, 2, 1, 1, 0), 61 RK3036_PLL_RATE(1100000000, 3, 275, 2, 1, 1, 0), 62 RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0), 63 RK3036_PLL_RATE(1000000000, 3, 250, 2, 1, 1, 0), 64 RK3036_PLL_RATE(912000000, 1, 76, 2, 1, 1, 0), 65 RK3036_PLL_RATE(816000000, 1, 68, 2, 1, 1, 0), 66 RK3036_PLL_RATE(800000000, 3, 200, 2, 1, 1, 0), 67 RK3036_PLL_RATE(700000000, 3, 350, 4, 1, 1, 0), 68 RK3036_PLL_RATE(696000000, 1, 116, 4, 1, 1, 0), 69 RK3036_PLL_RATE(600000000, 1, 100, 4, 1, 1, 0), 70 RK3036_PLL_RATE(594000000, 1, 99, 4, 1, 1, 0), 71 RK3036_PLL_RATE(500000000, 1, 125, 6, 1, 1, 0), 72 RK3036_PLL_RATE(408000000, 1, 68, 2, 2, 1, 0), 73 RK3036_PLL_RATE(312000000, 1, 78, 6, 1, 1, 0), 74 RK3036_PLL_RATE(297000000, 2, 99, 4, 1, 1, 0), 75 RK3036_PLL_RATE(292500000, 1, 195, 4, 4, 1, 0), 76 RK3036_PLL_RATE(241500000, 2, 161, 4, 2, 1, 0), 77 RK3036_PLL_RATE(216000000, 1, 72, 4, 2, 1, 0), 78 RK3036_PLL_RATE(200000000, 1, 100, 3, 4, 1, 0), 79 RK3036_PLL_RATE(148500000, 1, 99, 4, 4, 1, 0), 80 RK3036_PLL_RATE(135000000, 2, 45, 4, 1, 1, 0), 81 RK3036_PLL_RATE(128000000, 1, 16, 3, 1, 1, 0), 82 RK3036_PLL_RATE(126400000, 1, 79, 5, 3, 1, 0), 83 RK3036_PLL_RATE(119000000, 3, 119, 4, 2, 1, 0), 84 RK3036_PLL_RATE(115200000, 1, 24, 5, 1, 1, 0), 85 RK3036_PLL_RATE(108000000, 2, 45, 5, 1, 1, 0), 86 RK3036_PLL_RATE(101000000, 1, 101, 6, 4, 1, 0), 87 RK3036_PLL_RATE(100000000, 1, 150, 6, 6, 1, 0), 88 RK3036_PLL_RATE(96000000, 1, 96, 6, 4, 1, 0), 89 RK3036_PLL_RATE(78750000, 4, 315, 6, 4, 1, 0), 90 RK3036_PLL_RATE(74250000, 2, 99, 4, 4, 1, 0), 91 { /* sentinel */ }, 92 }; 93 94 #define RK3568_DIV_ATCLK_CORE_MASK 0x1f 95 #define RK3568_DIV_ATCLK_CORE_SHIFT 0 96 #define RK3568_DIV_GICCLK_CORE_MASK 0x1f 97 #define RK3568_DIV_GICCLK_CORE_SHIFT 8 98 #define RK3568_DIV_PCLK_CORE_MASK 0x1f 99 #define RK3568_DIV_PCLK_CORE_SHIFT 0 100 #define RK3568_DIV_PERIPHCLK_CORE_MASK 0x1f 101 #define RK3568_DIV_PERIPHCLK_CORE_SHIFT 8 102 #define RK3568_DIV_ACLK_CORE_MASK 0x1f 103 #define RK3568_DIV_ACLK_CORE_SHIFT 8 104 105 #define RK3568_DIV_SCLK_CORE_MASK 0xf 106 #define RK3568_DIV_SCLK_CORE_SHIFT 0 107 #define RK3568_MUX_SCLK_CORE_MASK 0x3 108 #define RK3568_MUX_SCLK_CORE_SHIFT 8 109 #define RK3568_MUX_SCLK_CORE_NPLL_MASK 0x1 110 #define RK3568_MUX_SCLK_CORE_NPLL_SHIFT 15 111 #define RK3568_MUX_CLK_CORE_APLL_MASK 0x1 112 #define RK3568_MUX_CLK_CORE_APLL_SHIFT 7 113 #define RK3568_MUX_CLK_PVTPLL_MASK 0x1 114 #define RK3568_MUX_CLK_PVTPLL_SHIFT 15 115 116 #define RK3568_CLKSEL1(_sclk_core) \ 117 { \ 118 .reg = RK3568_CLKSEL_CON(2), \ 119 .val = HIWORD_UPDATE(_sclk_core, RK3568_MUX_SCLK_CORE_NPLL_MASK, \ 120 RK3568_MUX_SCLK_CORE_NPLL_SHIFT) | \ 121 HIWORD_UPDATE(_sclk_core, RK3568_MUX_SCLK_CORE_MASK, \ 122 RK3568_MUX_SCLK_CORE_SHIFT) | \ 123 HIWORD_UPDATE(1, RK3568_DIV_SCLK_CORE_MASK, \ 124 RK3568_DIV_SCLK_CORE_SHIFT), \ 125 } 126 127 #define RK3568_CLKSEL2(_aclk_core) \ 128 { \ 129 .reg = RK3568_CLKSEL_CON(5), \ 130 .val = HIWORD_UPDATE(_aclk_core, RK3568_DIV_ACLK_CORE_MASK, \ 131 RK3568_DIV_ACLK_CORE_SHIFT), \ 132 } 133 134 #define RK3568_CLKSEL3(_atclk_core, _gic_core) \ 135 { \ 136 .reg = RK3568_CLKSEL_CON(3), \ 137 .val = HIWORD_UPDATE(_atclk_core, RK3568_DIV_ATCLK_CORE_MASK, \ 138 RK3568_DIV_ATCLK_CORE_SHIFT) | \ 139 HIWORD_UPDATE(_gic_core, RK3568_DIV_GICCLK_CORE_MASK, \ 140 RK3568_DIV_GICCLK_CORE_SHIFT), \ 141 } 142 143 #define RK3568_CLKSEL4(_pclk_core, _periph_core) \ 144 { \ 145 .reg = RK3568_CLKSEL_CON(4), \ 146 .val = HIWORD_UPDATE(_pclk_core, RK3568_DIV_PCLK_CORE_MASK, \ 147 RK3568_DIV_PCLK_CORE_SHIFT) | \ 148 HIWORD_UPDATE(_periph_core, RK3568_DIV_PERIPHCLK_CORE_MASK, \ 149 RK3568_DIV_PERIPHCLK_CORE_SHIFT), \ 150 } 151 152 #define RK3568_CPUCLK_RATE(_prate, _sclk, _acore, _atcore, _gicclk, _pclk, _periph) \ 153 { \ 154 .prate = _prate##U, \ 155 .divs = { \ 156 RK3568_CLKSEL1(_sclk), \ 157 RK3568_CLKSEL2(_acore), \ 158 RK3568_CLKSEL3(_atcore, _gicclk), \ 159 RK3568_CLKSEL4(_pclk, _periph), \ 160 }, \ 161 } 162 163 static struct rockchip_cpuclk_rate_table rk3568_cpuclk_rates[] __initdata = { 164 RK3568_CPUCLK_RATE(1800000000, 0, 1, 7, 7, 7, 7), 165 RK3568_CPUCLK_RATE(1704000000, 0, 1, 7, 7, 7, 7), 166 RK3568_CPUCLK_RATE(1608000000, 0, 1, 5, 5, 5, 5), 167 RK3568_CPUCLK_RATE(1584000000, 0, 1, 5, 5, 5, 5), 168 RK3568_CPUCLK_RATE(1560000000, 0, 1, 5, 5, 5, 5), 169 RK3568_CPUCLK_RATE(1536000000, 0, 1, 5, 5, 5, 5), 170 RK3568_CPUCLK_RATE(1512000000, 0, 1, 5, 5, 5, 5), 171 RK3568_CPUCLK_RATE(1488000000, 0, 1, 5, 5, 5, 5), 172 RK3568_CPUCLK_RATE(1464000000, 0, 1, 5, 5, 5, 5), 173 RK3568_CPUCLK_RATE(1440000000, 0, 1, 5, 5, 5, 5), 174 RK3568_CPUCLK_RATE(1416000000, 0, 1, 5, 5, 5, 5), 175 RK3568_CPUCLK_RATE(1392000000, 0, 1, 5, 5, 5, 5), 176 RK3568_CPUCLK_RATE(1368000000, 0, 1, 5, 5, 5, 5), 177 RK3568_CPUCLK_RATE(1344000000, 0, 1, 5, 5, 5, 5), 178 RK3568_CPUCLK_RATE(1320000000, 0, 1, 5, 5, 5, 5), 179 RK3568_CPUCLK_RATE(1296000000, 0, 1, 5, 5, 5, 5), 180 RK3568_CPUCLK_RATE(1272000000, 0, 1, 5, 5, 5, 5), 181 RK3568_CPUCLK_RATE(1248000000, 0, 1, 5, 5, 5, 5), 182 RK3568_CPUCLK_RATE(1224000000, 0, 1, 5, 5, 5, 5), 183 RK3568_CPUCLK_RATE(1200000000, 0, 1, 3, 3, 3, 3), 184 RK3568_CPUCLK_RATE(1104000000, 0, 1, 3, 3, 3, 3), 185 RK3568_CPUCLK_RATE(1008000000, 0, 1, 3, 3, 3, 3), 186 RK3568_CPUCLK_RATE(912000000, 0, 1, 3, 3, 3, 3), 187 RK3568_CPUCLK_RATE(816000000, 0, 1, 3, 3, 3, 3), 188 RK3568_CPUCLK_RATE(696000000, 0, 1, 3, 3, 3, 3), 189 RK3568_CPUCLK_RATE(600000000, 0, 1, 3, 3, 3, 3), 190 RK3568_CPUCLK_RATE(408000000, 0, 1, 3, 3, 3, 3), 191 RK3568_CPUCLK_RATE(312000000, 0, 1, 3, 3, 3, 3), 192 RK3568_CPUCLK_RATE(216000000, 0, 1, 3, 3, 3, 3), 193 RK3568_CPUCLK_RATE(96000000, 0, 1, 3, 3, 3, 3), 194 }; 195 196 static const struct rockchip_cpuclk_reg_data rk3568_cpuclk_data = { 197 .core_reg[0] = RK3568_CLKSEL_CON(0), 198 .div_core_shift[0] = 0, 199 .div_core_mask[0] = 0x1f, 200 .core_reg[1] = RK3568_CLKSEL_CON(0), 201 .div_core_shift[1] = 8, 202 .div_core_mask[1] = 0x1f, 203 .core_reg[2] = RK3568_CLKSEL_CON(1), 204 .div_core_shift[2] = 0, 205 .div_core_mask[2] = 0x1f, 206 .core_reg[3] = RK3568_CLKSEL_CON(1), 207 .div_core_shift[3] = 8, 208 .div_core_mask[3] = 0x1f, 209 .num_cores = 4, 210 .mux_core_alt = 1, 211 .mux_core_main = 0, 212 .mux_core_shift = 6, 213 .mux_core_mask = 0x1, 214 }; 215 216 PNAME(mux_pll_p) = { "xin24m" }; 217 PNAME(mux_usb480m_p) = { "xin24m", "usb480m_phy", "clk_rtc_32k" }; 218 PNAME(mux_armclk_p) = { "apll", "gpll" }; 219 PNAME(clk_i2s0_8ch_tx_p) = { "clk_i2s0_8ch_tx_src", "clk_i2s0_8ch_tx_frac", "i2s0_mclkin", "xin_osc0_half" }; 220 PNAME(clk_i2s0_8ch_rx_p) = { "clk_i2s0_8ch_rx_src", "clk_i2s0_8ch_rx_frac", "i2s0_mclkin", "xin_osc0_half" }; 221 PNAME(clk_i2s1_8ch_tx_p) = { "clk_i2s1_8ch_tx_src", "clk_i2s1_8ch_tx_frac", "i2s1_mclkin", "xin_osc0_half" }; 222 PNAME(clk_i2s1_8ch_rx_p) = { "clk_i2s1_8ch_rx_src", "clk_i2s1_8ch_rx_frac", "i2s1_mclkin", "xin_osc0_half" }; 223 PNAME(clk_i2s2_2ch_p) = { "clk_i2s2_2ch_src", "clk_i2s2_2ch_frac", "i2s2_mclkin", "xin_osc0_half "}; 224 PNAME(clk_i2s3_2ch_tx_p) = { "clk_i2s3_2ch_tx_src", "clk_i2s3_2ch_tx_frac", "i2s3_mclkin", "xin_osc0_half" }; 225 PNAME(clk_i2s3_2ch_rx_p) = { "clk_i2s3_2ch_rx_src", "clk_i2s3_2ch_rx_frac", "i2s3_mclkin", "xin_osc0_half" }; 226 PNAME(mclk_spdif_8ch_p) = { "mclk_spdif_8ch_src", "mclk_spdif_8ch_frac" }; 227 PNAME(sclk_audpwm_p) = { "sclk_audpwm_src", "sclk_audpwm_frac" }; 228 PNAME(sclk_uart1_p) = { "clk_uart1_src", "clk_uart1_frac", "xin24m" }; 229 PNAME(sclk_uart2_p) = { "clk_uart2_src", "clk_uart2_frac", "xin24m" }; 230 PNAME(sclk_uart3_p) = { "clk_uart3_src", "clk_uart3_frac", "xin24m" }; 231 PNAME(sclk_uart4_p) = { "clk_uart4_src", "clk_uart4_frac", "xin24m" }; 232 PNAME(sclk_uart5_p) = { "clk_uart5_src", "clk_uart5_frac", "xin24m" }; 233 PNAME(sclk_uart6_p) = { "clk_uart6_src", "clk_uart6_frac", "xin24m" }; 234 PNAME(sclk_uart7_p) = { "clk_uart7_src", "clk_uart7_frac", "xin24m" }; 235 PNAME(sclk_uart8_p) = { "clk_uart8_src", "clk_uart8_frac", "xin24m" }; 236 PNAME(sclk_uart9_p) = { "clk_uart9_src", "clk_uart9_frac", "xin24m" }; 237 PNAME(sclk_uart0_p) = { "sclk_uart0_div", "sclk_uart0_frac", "xin24m" }; 238 PNAME(clk_rtc32k_pmu_p) = { "clk_32k_pvtm", "xin32k", "clk_rtc32k_frac" }; 239 PNAME(mpll_gpll_cpll_npll_p) = { "mpll", "gpll", "cpll", "npll" }; 240 PNAME(gpll_cpll_npll_p) = { "gpll", "cpll", "npll" }; 241 PNAME(npll_gpll_p) = { "npll", "gpll" }; 242 PNAME(cpll_gpll_p) = { "cpll", "gpll" }; 243 PNAME(gpll_cpll_p) = { "gpll", "cpll" }; 244 PNAME(gpll_cpll_npll_vpll_p) = { "gpll", "cpll", "npll", "vpll" }; 245 PNAME(apll_gpll_npll_p) = { "apll", "gpll", "npll" }; 246 PNAME(sclk_core_pre_p) = { "sclk_core_src", "npll" }; 247 PNAME(gpll150_gpll100_gpll75_xin24m_p) = { "gpll_150m", "gpll_100m", "gpll_75m", "xin24m" }; 248 PNAME(clk_gpu_pre_mux_p) = { "clk_gpu_src", "gpu_pvtpll_out" }; 249 PNAME(clk_npu_pre_ndft_p) = { "clk_npu_src", "dummy"}; 250 PNAME(clk_npu_p) = { "clk_npu_pre_ndft", "npu_pvtpll_out" }; 251 PNAME(dpll_gpll_cpll_p) = { "dpll", "gpll", "cpll" }; 252 PNAME(clk_ddr1x_p) = { "clk_ddrphy1x_src", "dpll" }; 253 PNAME(gpll200_gpll150_gpll100_xin24m_p) = { "gpll_200m", "gpll_150m", "gpll_100m", "xin24m" }; 254 PNAME(gpll100_gpll75_gpll50_p) = { "gpll_100m", "gpll_75m", "cpll_50m" }; 255 PNAME(i2s0_mclkout_tx_p) = { "clk_i2s0_8ch_tx", "xin_osc0_half" }; 256 PNAME(i2s0_mclkout_rx_p) = { "clk_i2s0_8ch_rx", "xin_osc0_half" }; 257 PNAME(i2s1_mclkout_tx_p) = { "clk_i2s1_8ch_tx", "xin_osc0_half" }; 258 PNAME(i2s1_mclkout_rx_p) = { "clk_i2s1_8ch_rx", "xin_osc0_half" }; 259 PNAME(i2s2_mclkout_p) = { "clk_i2s2_2ch", "xin_osc0_half" }; 260 PNAME(i2s3_mclkout_tx_p) = { "clk_i2s3_2ch_tx", "xin_osc0_half" }; 261 PNAME(i2s3_mclkout_rx_p) = { "clk_i2s3_2ch_rx", "xin_osc0_half" }; 262 PNAME(mclk_pdm_p) = { "gpll_300m", "cpll_250m", "gpll_200m", "gpll_100m" }; 263 PNAME(clk_i2c_p) = { "gpll_200m", "gpll_100m", "xin24m", "cpll_100m" }; 264 PNAME(gpll200_gpll150_gpll100_p) = { "gpll_200m", "gpll_150m", "gpll_100m" }; 265 PNAME(gpll300_gpll200_gpll100_p) = { "gpll_300m", "gpll_200m", "gpll_100m" }; 266 PNAME(clk_nandc_p) = { "gpll_200m", "gpll_150m", "cpll_100m", "xin24m" }; 267 PNAME(sclk_sfc_p) = { "xin24m", "cpll_50m", "gpll_75m", "gpll_100m", "cpll_125m", "gpll_150m" }; 268 PNAME(gpll200_gpll150_cpll125_p) = { "gpll_200m", "gpll_150m", "cpll_125m" }; 269 PNAME(cclk_emmc_p) = { "xin24m", "gpll_200m", "gpll_150m", "cpll_100m", "cpll_50m", "clk_osc0_div_375k" }; 270 PNAME(aclk_pipe_p) = { "gpll_400m", "gpll_300m", "gpll_200m", "xin24m" }; 271 PNAME(gpll200_cpll125_p) = { "gpll_200m", "cpll_125m" }; 272 PNAME(gpll300_gpll200_gpll100_xin24m_p) = { "gpll_300m", "gpll_200m", "gpll_100m", "xin24m" }; 273 PNAME(clk_sdmmc_p) = { "xin24m", "gpll_400m", "gpll_300m", "cpll_100m", "cpll_50m", "clk_osc0_div_750k" }; 274 PNAME(cpll125_cpll50_cpll25_xin24m_p) = { "cpll_125m", "cpll_50m", "cpll_25m", "xin24m" }; 275 PNAME(clk_gmac_ptp_p) = { "cpll_62p5", "gpll_100m", "cpll_50m", "xin24m" }; 276 PNAME(cpll333_gpll300_gpll200_p) = { "cpll_333m", "gpll_300m", "gpll_200m" }; 277 PNAME(cpll_gpll_hpll_p) = { "cpll", "gpll", "hpll" }; 278 PNAME(gpll_usb480m_xin24m_p) = { "gpll", "usb480m", "xin24m", "xin24m" }; 279 PNAME(gpll300_cpll250_gpll100_xin24m_p) = { "gpll_300m", "cpll_250m", "gpll_100m", "xin24m" }; 280 PNAME(cpll_gpll_hpll_vpll_p) = { "cpll", "gpll", "hpll", "vpll" }; 281 PNAME(hpll_vpll_gpll_cpll_p) = { "hpll", "vpll", "gpll", "cpll" }; 282 PNAME(gpll400_cpll333_gpll200_p) = { "gpll_400m", "cpll_333m", "gpll_200m" }; 283 PNAME(gpll100_gpll75_cpll50_xin24m_p) = { "gpll_100m", "gpll_75m", "cpll_50m", "xin24m" }; 284 PNAME(xin24m_gpll100_cpll100_p) = { "xin24m", "gpll_100m", "cpll_100m" }; 285 PNAME(gpll_cpll_usb480m_p) = { "gpll", "cpll", "usb480m" }; 286 PNAME(gpll100_xin24m_cpll100_p) = { "gpll_100m", "xin24m", "cpll_100m" }; 287 PNAME(gpll200_xin24m_cpll100_p) = { "gpll_200m", "xin24m", "cpll_100m" }; 288 PNAME(xin24m_32k_p) = { "xin24m", "clk_rtc_32k" }; 289 PNAME(cpll500_gpll400_gpll300_xin24m_p) = { "cpll_500m", "gpll_400m", "gpll_300m", "xin24m" }; 290 PNAME(gpll400_gpll300_gpll200_xin24m_p) = { "gpll_400m", "gpll_300m", "gpll_200m", "xin24m" }; 291 PNAME(xin24m_cpll100_p) = { "xin24m", "cpll_100m" }; 292 PNAME(ppll_usb480m_cpll_gpll_p) = { "ppll", "usb480m", "cpll", "gpll"}; 293 PNAME(clk_usbphy0_ref_p) = { "clk_ref24m", "xin_osc0_usbphy0_g" }; 294 PNAME(clk_usbphy1_ref_p) = { "clk_ref24m", "xin_osc0_usbphy1_g" }; 295 PNAME(clk_mipidsiphy0_ref_p) = { "clk_ref24m", "xin_osc0_mipidsiphy0_g" }; 296 PNAME(clk_mipidsiphy1_ref_p) = { "clk_ref24m", "xin_osc0_mipidsiphy1_g" }; 297 PNAME(clk_wifi_p) = { "clk_wifi_osc0", "clk_wifi_div" }; 298 PNAME(clk_pciephy0_ref_p) = { "clk_pciephy0_osc0", "clk_pciephy0_div" }; 299 PNAME(clk_pciephy1_ref_p) = { "clk_pciephy1_osc0", "clk_pciephy1_div" }; 300 PNAME(clk_pciephy2_ref_p) = { "clk_pciephy2_osc0", "clk_pciephy2_div" }; 301 PNAME(mux_gmac0_p) = { "clk_mac0_2top", "gmac0_clkin" }; 302 PNAME(mux_gmac0_rgmii_speed_p) = { "clk_gmac0", "clk_gmac0", "clk_gmac0_tx_div50", "clk_gmac0_tx_div5" }; 303 PNAME(mux_gmac0_rmii_speed_p) = { "clk_gmac0_rx_div20", "clk_gmac0_rx_div2" }; 304 PNAME(mux_gmac0_rx_tx_p) = { "clk_gmac0_rgmii_speed", "clk_gmac0_rmii_speed", "clk_gmac0_xpcs_mii" }; 305 PNAME(mux_gmac1_p) = { "clk_mac1_2top", "gmac1_clkin" }; 306 PNAME(mux_gmac1_rgmii_speed_p) = { "clk_gmac1", "clk_gmac1", "clk_gmac1_tx_div50", "clk_gmac1_tx_div5" }; 307 PNAME(mux_gmac1_rmii_speed_p) = { "clk_gmac1_rx_div20", "clk_gmac1_rx_div2" }; 308 PNAME(mux_gmac1_rx_tx_p) = { "clk_gmac1_rgmii_speed", "clk_gmac1_rmii_speed", "clk_gmac1_xpcs_mii" }; 309 PNAME(clk_hdmi_ref_p) = { "hpll", "hpll_ph0" }; 310 PNAME(clk_pdpmu_p) = { "ppll", "gpll" }; 311 PNAME(clk_mac_2top_p) = { "cpll_125m", "cpll_50m", "cpll_25m", "ppll" }; 312 PNAME(clk_pwm0_p) = { "xin24m", "clk_pdpmu" }; 313 PNAME(aclk_rkvdec_pre_p) = { "gpll", "cpll" }; 314 PNAME(clk_rkvdec_core_p) = { "gpll", "cpll", "dummy_npll", "dummy_vpll" }; 315 316 static struct rockchip_pll_clock rk3568_pmu_pll_clks[] __initdata = { 317 [ppll] = PLL(pll_rk3328, PLL_PPLL, "ppll", mux_pll_p, 318 0, RK3568_PMU_PLL_CON(0), 319 RK3568_PMU_MODE_CON0, 0, 4, 0, rk3568_pll_rates), 320 [hpll] = PLL(pll_rk3328, PLL_HPLL, "hpll", mux_pll_p, 321 0, RK3568_PMU_PLL_CON(16), 322 RK3568_PMU_MODE_CON0, 2, 7, 0, rk3568_pll_rates), 323 }; 324 325 static struct rockchip_pll_clock rk3568_pll_clks[] __initdata = { 326 [apll] = PLL(pll_rk3328, PLL_APLL, "apll", mux_pll_p, 327 0, RK3568_PLL_CON(0), 328 RK3568_MODE_CON0, 0, 0, 0, rk3568_pll_rates), 329 [dpll] = PLL(pll_rk3328, PLL_DPLL, "dpll", mux_pll_p, 330 0, RK3568_PLL_CON(8), 331 RK3568_MODE_CON0, 2, 1, 0, NULL), 332 [cpll] = PLL(pll_rk3328, PLL_CPLL, "cpll", mux_pll_p, 333 0, RK3568_PLL_CON(24), 334 RK3568_MODE_CON0, 4, 2, 0, rk3568_pll_rates), 335 [gpll] = PLL(pll_rk3328, PLL_GPLL, "gpll", mux_pll_p, 336 0, RK3568_PLL_CON(16), 337 RK3568_MODE_CON0, 6, 3, 0, rk3568_pll_rates), 338 [npll] = PLL(pll_rk3328, PLL_NPLL, "npll", mux_pll_p, 339 0, RK3568_PLL_CON(32), 340 RK3568_MODE_CON0, 10, 5, 0, rk3568_pll_rates), 341 [vpll] = PLL(pll_rk3328, PLL_VPLL, "vpll", mux_pll_p, 342 0, RK3568_PLL_CON(40), 343 RK3568_MODE_CON0, 12, 6, 0, rk3568_pll_rates), 344 }; 345 346 #define MFLAGS CLK_MUX_HIWORD_MASK 347 #define DFLAGS CLK_DIVIDER_HIWORD_MASK 348 #define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE) 349 350 static struct rockchip_clk_branch rk3568_i2s0_8ch_tx_fracmux __initdata = 351 MUX(CLK_I2S0_8CH_TX, "clk_i2s0_8ch_tx", clk_i2s0_8ch_tx_p, CLK_SET_RATE_PARENT, 352 RK3568_CLKSEL_CON(11), 10, 2, MFLAGS); 353 354 static struct rockchip_clk_branch rk3568_i2s0_8ch_rx_fracmux __initdata = 355 MUX(CLK_I2S0_8CH_RX, "clk_i2s0_8ch_rx", clk_i2s0_8ch_rx_p, CLK_SET_RATE_PARENT, 356 RK3568_CLKSEL_CON(13), 10, 2, MFLAGS); 357 358 static struct rockchip_clk_branch rk3568_i2s1_8ch_tx_fracmux __initdata = 359 MUX(CLK_I2S1_8CH_TX, "clk_i2s1_8ch_tx", clk_i2s1_8ch_tx_p, CLK_SET_RATE_PARENT, 360 RK3568_CLKSEL_CON(15), 10, 2, MFLAGS); 361 362 static struct rockchip_clk_branch rk3568_i2s1_8ch_rx_fracmux __initdata = 363 MUX(CLK_I2S1_8CH_RX, "clk_i2s1_8ch_rx", clk_i2s1_8ch_rx_p, CLK_SET_RATE_PARENT, 364 RK3568_CLKSEL_CON(17), 10, 2, MFLAGS); 365 366 static struct rockchip_clk_branch rk3568_i2s2_2ch_fracmux __initdata = 367 MUX(CLK_I2S2_2CH, "clk_i2s2_2ch", clk_i2s2_2ch_p, CLK_SET_RATE_PARENT, 368 RK3568_CLKSEL_CON(19), 10, 2, MFLAGS); 369 370 static struct rockchip_clk_branch rk3568_i2s3_2ch_tx_fracmux __initdata = 371 MUX(CLK_I2S3_2CH_TX, "clk_i2s3_2ch_tx", clk_i2s3_2ch_tx_p, CLK_SET_RATE_PARENT, 372 RK3568_CLKSEL_CON(21), 10, 2, MFLAGS); 373 374 static struct rockchip_clk_branch rk3568_i2s3_2ch_rx_fracmux __initdata = 375 MUX(CLK_I2S3_2CH_RX, "clk_i2s3_2ch_rx", clk_i2s3_2ch_rx_p, CLK_SET_RATE_PARENT, 376 RK3568_CLKSEL_CON(83), 10, 2, MFLAGS); 377 378 static struct rockchip_clk_branch rk3568_spdif_8ch_fracmux __initdata = 379 MUX(MCLK_SPDIF_8CH, "mclk_spdif_8ch", mclk_spdif_8ch_p, CLK_SET_RATE_PARENT, 380 RK3568_CLKSEL_CON(23), 15, 1, MFLAGS); 381 382 static struct rockchip_clk_branch rk3568_audpwm_fracmux __initdata = 383 MUX(SCLK_AUDPWM, "sclk_audpwm", sclk_audpwm_p, CLK_SET_RATE_PARENT, 384 RK3568_CLKSEL_CON(25), 15, 1, MFLAGS); 385 386 static struct rockchip_clk_branch rk3568_uart1_fracmux __initdata = 387 MUX(0, "sclk_uart1_mux", sclk_uart1_p, CLK_SET_RATE_PARENT, 388 RK3568_CLKSEL_CON(52), 12, 2, MFLAGS); 389 390 static struct rockchip_clk_branch rk3568_uart2_fracmux __initdata = 391 MUX(0, "sclk_uart2_mux", sclk_uart2_p, CLK_SET_RATE_PARENT, 392 RK3568_CLKSEL_CON(54), 12, 2, MFLAGS); 393 394 static struct rockchip_clk_branch rk3568_uart3_fracmux __initdata = 395 MUX(0, "sclk_uart3_mux", sclk_uart3_p, CLK_SET_RATE_PARENT, 396 RK3568_CLKSEL_CON(56), 12, 2, MFLAGS); 397 398 static struct rockchip_clk_branch rk3568_uart4_fracmux __initdata = 399 MUX(0, "sclk_uart4_mux", sclk_uart4_p, CLK_SET_RATE_PARENT, 400 RK3568_CLKSEL_CON(58), 12, 2, MFLAGS); 401 402 static struct rockchip_clk_branch rk3568_uart5_fracmux __initdata = 403 MUX(0, "sclk_uart5_mux", sclk_uart5_p, CLK_SET_RATE_PARENT, 404 RK3568_CLKSEL_CON(60), 12, 2, MFLAGS); 405 406 static struct rockchip_clk_branch rk3568_uart6_fracmux __initdata = 407 MUX(0, "sclk_uart6_mux", sclk_uart6_p, CLK_SET_RATE_PARENT, 408 RK3568_CLKSEL_CON(62), 12, 2, MFLAGS); 409 410 static struct rockchip_clk_branch rk3568_uart7_fracmux __initdata = 411 MUX(0, "sclk_uart7_mux", sclk_uart7_p, CLK_SET_RATE_PARENT, 412 RK3568_CLKSEL_CON(64), 12, 2, MFLAGS); 413 414 static struct rockchip_clk_branch rk3568_uart8_fracmux __initdata = 415 MUX(0, "sclk_uart8_mux", sclk_uart8_p, CLK_SET_RATE_PARENT, 416 RK3568_CLKSEL_CON(66), 12, 2, MFLAGS); 417 418 static struct rockchip_clk_branch rk3568_uart9_fracmux __initdata = 419 MUX(0, "sclk_uart9_mux", sclk_uart9_p, CLK_SET_RATE_PARENT, 420 RK3568_CLKSEL_CON(68), 12, 2, MFLAGS); 421 422 static struct rockchip_clk_branch rk3568_uart0_fracmux __initdata = 423 MUX(0, "sclk_uart0_mux", sclk_uart0_p, CLK_SET_RATE_PARENT, 424 RK3568_PMU_CLKSEL_CON(4), 10, 2, MFLAGS); 425 426 static struct rockchip_clk_branch rk3568_rtc32k_pmu_fracmux __initdata = 427 MUX(CLK_RTC_32K, "clk_rtc_32k", clk_rtc32k_pmu_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 428 RK3568_PMU_CLKSEL_CON(0), 6, 2, MFLAGS); 429 430 static struct rockchip_clk_branch rk3568_clk_branches[] __initdata = { 431 /* 432 * Clock-Architecture Diagram 1 433 */ 434 /* SRC_CLK */ 435 COMPOSITE_NOMUX(0, "gpll_400m", "gpll", CLK_IGNORE_UNUSED, 436 RK3568_CLKSEL_CON(75), 0, 5, DFLAGS, 437 RK3568_CLKGATE_CON(35), 0, GFLAGS), 438 COMPOSITE_NOMUX(0, "gpll_300m", "gpll", CLK_IGNORE_UNUSED, 439 RK3568_CLKSEL_CON(75), 8, 5, DFLAGS, 440 RK3568_CLKGATE_CON(35), 1, GFLAGS), 441 COMPOSITE_NOMUX(0, "gpll_200m", "gpll", CLK_IGNORE_UNUSED, 442 RK3568_CLKSEL_CON(76), 0, 5, DFLAGS, 443 RK3568_CLKGATE_CON(35), 2, GFLAGS), 444 COMPOSITE_NOMUX(0, "gpll_150m", "gpll", CLK_IGNORE_UNUSED, 445 RK3568_CLKSEL_CON(76), 8, 5, DFLAGS, 446 RK3568_CLKGATE_CON(35), 3, GFLAGS), 447 COMPOSITE_NOMUX(0, "gpll_100m", "gpll", CLK_IGNORE_UNUSED, 448 RK3568_CLKSEL_CON(77), 0, 5, DFLAGS, 449 RK3568_CLKGATE_CON(35), 4, GFLAGS), 450 COMPOSITE_NOMUX(0, "gpll_75m", "gpll", CLK_IGNORE_UNUSED, 451 RK3568_CLKSEL_CON(77), 8, 5, DFLAGS, 452 RK3568_CLKGATE_CON(35), 5, GFLAGS), 453 COMPOSITE_NOMUX(0, "gpll_20m", "gpll", CLK_IGNORE_UNUSED, 454 RK3568_CLKSEL_CON(78), 0, 6, DFLAGS, 455 RK3568_CLKGATE_CON(35), 6, GFLAGS), 456 COMPOSITE_NOMUX(CPLL_500M, "cpll_500m", "cpll", CLK_IGNORE_UNUSED, 457 RK3568_CLKSEL_CON(78), 8, 5, DFLAGS, 458 RK3568_CLKGATE_CON(35), 7, GFLAGS), 459 COMPOSITE_NOMUX(CPLL_333M, "cpll_333m", "cpll", CLK_IGNORE_UNUSED, 460 RK3568_CLKSEL_CON(79), 0, 5, DFLAGS, 461 RK3568_CLKGATE_CON(35), 8, GFLAGS), 462 COMPOSITE_NOMUX(CPLL_250M, "cpll_250m", "cpll", CLK_IGNORE_UNUSED, 463 RK3568_CLKSEL_CON(79), 8, 5, DFLAGS, 464 RK3568_CLKGATE_CON(35), 9, GFLAGS), 465 COMPOSITE_NOMUX(CPLL_125M, "cpll_125m", "cpll", CLK_IGNORE_UNUSED, 466 RK3568_CLKSEL_CON(80), 0, 5, DFLAGS, 467 RK3568_CLKGATE_CON(35), 10, GFLAGS), 468 COMPOSITE_NOMUX(CPLL_100M, "cpll_100m", "cpll", CLK_IGNORE_UNUSED, 469 RK3568_CLKSEL_CON(82), 0, 5, DFLAGS, 470 RK3568_CLKGATE_CON(35), 11, GFLAGS), 471 COMPOSITE_NOMUX(CPLL_62P5M, "cpll_62p5", "cpll", CLK_IGNORE_UNUSED, 472 RK3568_CLKSEL_CON(80), 8, 5, DFLAGS, 473 RK3568_CLKGATE_CON(35), 12, GFLAGS), 474 COMPOSITE_NOMUX(CPLL_50M, "cpll_50m", "cpll", CLK_IGNORE_UNUSED, 475 RK3568_CLKSEL_CON(81), 0, 5, DFLAGS, 476 RK3568_CLKGATE_CON(35), 13, GFLAGS), 477 COMPOSITE_NOMUX(CPLL_25M, "cpll_25m", "cpll", CLK_IGNORE_UNUSED, 478 RK3568_CLKSEL_CON(81), 8, 6, DFLAGS, 479 RK3568_CLKGATE_CON(35), 14, GFLAGS), 480 COMPOSITE_NOMUX(0, "clk_osc0_div_750k", "xin24m", CLK_IGNORE_UNUSED, 481 RK3568_CLKSEL_CON(82), 8, 6, DFLAGS, 482 RK3568_CLKGATE_CON(35), 15, GFLAGS), 483 FACTOR(0, "clk_osc0_div_375k", "clk_osc0_div_750k", 0, 1, 2), 484 FACTOR(0, "xin_osc0_half", "xin24m", 0, 1, 2), 485 MUX(USB480M, "usb480m", mux_usb480m_p, CLK_SET_RATE_PARENT, 486 RK3568_MODE_CON0, 14, 2, MFLAGS), 487 488 /* PD_CORE */ 489 COMPOSITE(0, "sclk_core_src", apll_gpll_npll_p, CLK_IGNORE_UNUSED, 490 RK3568_CLKSEL_CON(2), 8, 2, MFLAGS, 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY, 491 RK3568_CLKGATE_CON(0), 5, GFLAGS), 492 COMPOSITE_NODIV(0, "sclk_core", sclk_core_pre_p, CLK_IGNORE_UNUSED, 493 RK3568_CLKSEL_CON(2), 15, 1, MFLAGS, 494 RK3568_CLKGATE_CON(0), 7, GFLAGS), 495 496 COMPOSITE_NOMUX(0, "atclk_core", "armclk", CLK_IGNORE_UNUSED, 497 RK3568_CLKSEL_CON(3), 0, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, 498 RK3568_CLKGATE_CON(0), 8, GFLAGS), 499 COMPOSITE_NOMUX(0, "gicclk_core", "armclk", CLK_IGNORE_UNUSED, 500 RK3568_CLKSEL_CON(3), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, 501 RK3568_CLKGATE_CON(0), 9, GFLAGS), 502 COMPOSITE_NOMUX(0, "pclk_core_pre", "armclk", CLK_IGNORE_UNUSED, 503 RK3568_CLKSEL_CON(4), 0, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, 504 RK3568_CLKGATE_CON(0), 10, GFLAGS), 505 COMPOSITE_NOMUX(0, "periphclk_core_pre", "armclk", CLK_IGNORE_UNUSED, 506 RK3568_CLKSEL_CON(4), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, 507 RK3568_CLKGATE_CON(0), 11, GFLAGS), 508 COMPOSITE_NOMUX(0, "tsclk_core", "periphclk_core_pre", CLK_IGNORE_UNUSED, 509 RK3568_CLKSEL_CON(5), 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY, 510 RK3568_CLKGATE_CON(0), 14, GFLAGS), 511 COMPOSITE_NOMUX(0, "cntclk_core", "periphclk_core_pre", CLK_IGNORE_UNUSED, 512 RK3568_CLKSEL_CON(5), 4, 4, DFLAGS | CLK_DIVIDER_READ_ONLY, 513 RK3568_CLKGATE_CON(0), 15, GFLAGS), 514 COMPOSITE_NOMUX(0, "aclk_core", "sclk_core", CLK_IGNORE_UNUSED, 515 RK3568_CLKSEL_CON(5), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, 516 RK3568_CLKGATE_CON(1), 0, GFLAGS), 517 518 COMPOSITE_NODIV(ACLK_CORE_NIU2BUS, "aclk_core_niu2bus", gpll150_gpll100_gpll75_xin24m_p, CLK_IGNORE_UNUSED, 519 RK3568_CLKSEL_CON(5), 14, 2, MFLAGS, 520 RK3568_CLKGATE_CON(1), 2, GFLAGS), 521 522 GATE(CLK_CORE_PVTM, "clk_core_pvtm", "xin24m", 0, 523 RK3568_CLKGATE_CON(1), 10, GFLAGS), 524 GATE(CLK_CORE_PVTM_CORE, "clk_core_pvtm_core", "armclk", 0, 525 RK3568_CLKGATE_CON(1), 11, GFLAGS), 526 GATE(CLK_CORE_PVTPLL, "clk_core_pvtpll", "armclk", CLK_IGNORE_UNUSED, 527 RK3568_CLKGATE_CON(1), 12, GFLAGS), 528 GATE(PCLK_CORE_PVTM, "pclk_core_pvtm", "pclk_core_pre", 0, 529 RK3568_CLKGATE_CON(1), 9, GFLAGS), 530 531 /* PD_GPU */ 532 COMPOSITE(CLK_GPU_SRC, "clk_gpu_src", mpll_gpll_cpll_npll_p, 0, 533 RK3568_CLKSEL_CON(6), 6, 2, MFLAGS | CLK_MUX_READ_ONLY, 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY, 534 RK3568_CLKGATE_CON(2), 0, GFLAGS), 535 MUX(CLK_GPU_PRE_MUX, "clk_gpu_pre_mux", clk_gpu_pre_mux_p, CLK_SET_RATE_PARENT, 536 RK3568_CLKSEL_CON(6), 11, 1, MFLAGS | CLK_MUX_READ_ONLY), 537 DIV(ACLK_GPU_PRE, "aclk_gpu_pre", "clk_gpu_pre_mux", 0, 538 RK3568_CLKSEL_CON(6), 8, 2, DFLAGS), 539 DIV(PCLK_GPU_PRE, "pclk_gpu_pre", "clk_gpu_pre_mux", 0, 540 RK3568_CLKSEL_CON(6), 12, 4, DFLAGS), 541 GATE(CLK_GPU, "clk_gpu", "clk_gpu_pre_mux", 0, 542 RK3568_CLKGATE_CON(2), 3, GFLAGS), 543 544 GATE(PCLK_GPU_PVTM, "pclk_gpu_pvtm", "pclk_gpu_pre", 0, 545 RK3568_CLKGATE_CON(2), 6, GFLAGS), 546 GATE(CLK_GPU_PVTM, "clk_gpu_pvtm", "xin24m", 0, 547 RK3568_CLKGATE_CON(2), 7, GFLAGS), 548 GATE(CLK_GPU_PVTM_CORE, "clk_gpu_pvtm_core", "clk_gpu_src", 0, 549 RK3568_CLKGATE_CON(2), 8, GFLAGS), 550 GATE(CLK_GPU_PVTPLL, "clk_gpu_pvtpll", "clk_gpu_src", CLK_IGNORE_UNUSED, 551 RK3568_CLKGATE_CON(2), 9, GFLAGS), 552 553 /* PD_NPU */ 554 COMPOSITE(CLK_NPU_SRC, "clk_npu_src", npll_gpll_p, 0, 555 RK3568_CLKSEL_CON(7), 6, 1, MFLAGS, 0, 4, DFLAGS, 556 RK3568_CLKGATE_CON(3), 0, GFLAGS), 557 MUX(CLK_NPU_PRE_NDFT, "clk_npu_pre_ndft", clk_npu_pre_ndft_p, CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, 558 RK3568_CLKSEL_CON(7), 8, 1, MFLAGS), 559 MUX(CLK_NPU, "clk_npu", clk_npu_p, CLK_SET_RATE_PARENT, 560 RK3568_CLKSEL_CON(7), 15, 1, MFLAGS), 561 COMPOSITE_NOMUX(HCLK_NPU_PRE, "hclk_npu_pre", "clk_npu", 0, 562 RK3568_CLKSEL_CON(8), 0, 4, DFLAGS, 563 RK3568_CLKGATE_CON(3), 2, GFLAGS), 564 COMPOSITE_NOMUX(PCLK_NPU_PRE, "pclk_npu_pre", "clk_npu", 0, 565 RK3568_CLKSEL_CON(8), 4, 4, DFLAGS, 566 RK3568_CLKGATE_CON(3), 3, GFLAGS), 567 GATE(ACLK_NPU_PRE, "aclk_npu_pre", "clk_npu", 0, 568 RK3568_CLKGATE_CON(3), 4, GFLAGS), 569 GATE(ACLK_NPU, "aclk_npu", "aclk_npu_pre", 0, 570 RK3568_CLKGATE_CON(3), 7, GFLAGS), 571 GATE(HCLK_NPU, "hclk_npu", "hclk_npu_pre", 0, 572 RK3568_CLKGATE_CON(3), 8, GFLAGS), 573 574 GATE(PCLK_NPU_PVTM, "pclk_npu_pvtm", "pclk_npu_pre", 0, 575 RK3568_CLKGATE_CON(3), 9, GFLAGS), 576 GATE(CLK_NPU_PVTM, "clk_npu_pvtm", "xin24m", 0, 577 RK3568_CLKGATE_CON(3), 10, GFLAGS), 578 GATE(CLK_NPU_PVTM_CORE, "clk_npu_pvtm_core", "clk_npu_pre_ndft", 0, 579 RK3568_CLKGATE_CON(3), 11, GFLAGS), 580 GATE(CLK_NPU_PVTPLL, "clk_npu_pvtpll", "clk_npu_pre_ndft", CLK_IGNORE_UNUSED, 581 RK3568_CLKGATE_CON(3), 12, GFLAGS), 582 583 /* PD_DDR */ 584 COMPOSITE(CLK_DDRPHY1X_SRC, "clk_ddrphy1x_src", dpll_gpll_cpll_p, CLK_IGNORE_UNUSED, 585 RK3568_CLKSEL_CON(9), 6, 2, MFLAGS, 0, 5, DFLAGS, 586 RK3568_CLKGATE_CON(4), 0, GFLAGS), 587 MUXGRF(CLK_DDR1X, "clk_ddr1x", clk_ddr1x_p, CLK_SET_RATE_PARENT, 588 RK3568_CLKSEL_CON(9), 15, 1, MFLAGS), 589 590 COMPOSITE_NOMUX(CLK_MSCH, "clk_msch", "clk_ddr1x", CLK_IGNORE_UNUSED, 591 RK3568_CLKSEL_CON(10), 0, 2, DFLAGS, 592 RK3568_CLKGATE_CON(4), 2, GFLAGS), 593 GATE(CLK24_DDRMON, "clk24_ddrmon", "xin24m", CLK_IGNORE_UNUSED, 594 RK3568_CLKGATE_CON(4), 15, GFLAGS), 595 596 /* PD_GIC_AUDIO */ 597 COMPOSITE_NODIV(ACLK_GIC_AUDIO, "aclk_gic_audio", gpll200_gpll150_gpll100_xin24m_p, CLK_IGNORE_UNUSED, 598 RK3568_CLKSEL_CON(10), 8, 2, MFLAGS, 599 RK3568_CLKGATE_CON(5), 0, GFLAGS), 600 COMPOSITE_NODIV(HCLK_GIC_AUDIO, "hclk_gic_audio", gpll150_gpll100_gpll75_xin24m_p, CLK_IGNORE_UNUSED, 601 RK3568_CLKSEL_CON(10), 10, 2, MFLAGS, 602 RK3568_CLKGATE_CON(5), 1, GFLAGS), 603 GATE(HCLK_SDMMC_BUFFER, "hclk_sdmmc_buffer", "hclk_gic_audio", 0, 604 RK3568_CLKGATE_CON(5), 8, GFLAGS), 605 COMPOSITE_NODIV(DCLK_SDMMC_BUFFER, "dclk_sdmmc_buffer", gpll100_gpll75_gpll50_p, 0, 606 RK3568_CLKSEL_CON(10), 12, 2, MFLAGS, 607 RK3568_CLKGATE_CON(5), 9, GFLAGS), 608 GATE(ACLK_GIC600, "aclk_gic600", "aclk_gic_audio", CLK_IGNORE_UNUSED, 609 RK3568_CLKGATE_CON(5), 4, GFLAGS), 610 GATE(ACLK_SPINLOCK, "aclk_spinlock", "aclk_gic_audio", CLK_IGNORE_UNUSED, 611 RK3568_CLKGATE_CON(5), 7, GFLAGS), 612 GATE(HCLK_I2S0_8CH, "hclk_i2s0_8ch", "hclk_gic_audio", 0, 613 RK3568_CLKGATE_CON(5), 10, GFLAGS), 614 GATE(HCLK_I2S1_8CH, "hclk_i2s1_8ch", "hclk_gic_audio", 0, 615 RK3568_CLKGATE_CON(5), 11, GFLAGS), 616 GATE(HCLK_I2S2_2CH, "hclk_i2s2_2ch", "hclk_gic_audio", 0, 617 RK3568_CLKGATE_CON(5), 12, GFLAGS), 618 GATE(HCLK_I2S3_2CH, "hclk_i2s3_2ch", "hclk_gic_audio", 0, 619 RK3568_CLKGATE_CON(5), 13, GFLAGS), 620 621 COMPOSITE(CLK_I2S0_8CH_TX_SRC, "clk_i2s0_8ch_tx_src", gpll_cpll_npll_p, 0, 622 RK3568_CLKSEL_CON(11), 8, 2, MFLAGS, 0, 7, DFLAGS, 623 RK3568_CLKGATE_CON(6), 0, GFLAGS), 624 COMPOSITE_FRACMUX(CLK_I2S0_8CH_TX_FRAC, "clk_i2s0_8ch_tx_frac", "clk_i2s0_8ch_tx_src", CLK_SET_RATE_PARENT, 625 RK3568_CLKSEL_CON(12), 0, 626 RK3568_CLKGATE_CON(6), 1, GFLAGS, 627 &rk3568_i2s0_8ch_tx_fracmux), 628 GATE(MCLK_I2S0_8CH_TX, "mclk_i2s0_8ch_tx", "clk_i2s0_8ch_tx", 0, 629 RK3568_CLKGATE_CON(6), 2, GFLAGS), 630 COMPOSITE_NODIV(I2S0_MCLKOUT_TX, "i2s0_mclkout_tx", i2s0_mclkout_tx_p, CLK_SET_RATE_PARENT, 631 RK3568_CLKSEL_CON(11), 15, 1, MFLAGS, 632 RK3568_CLKGATE_CON(6), 3, GFLAGS), 633 634 COMPOSITE(CLK_I2S0_8CH_RX_SRC, "clk_i2s0_8ch_rx_src", gpll_cpll_npll_p, 0, 635 RK3568_CLKSEL_CON(13), 8, 2, MFLAGS, 0, 7, DFLAGS, 636 RK3568_CLKGATE_CON(6), 4, GFLAGS), 637 COMPOSITE_FRACMUX(CLK_I2S0_8CH_RX_FRAC, "clk_i2s0_8ch_rx_frac", "clk_i2s0_8ch_rx_src", CLK_SET_RATE_PARENT, 638 RK3568_CLKSEL_CON(14), 0, 639 RK3568_CLKGATE_CON(6), 5, GFLAGS, 640 &rk3568_i2s0_8ch_rx_fracmux), 641 GATE(MCLK_I2S0_8CH_RX, "mclk_i2s0_8ch_rx", "clk_i2s0_8ch_rx", 0, 642 RK3568_CLKGATE_CON(6), 6, GFLAGS), 643 COMPOSITE_NODIV(I2S0_MCLKOUT_RX, "i2s0_mclkout_rx", i2s0_mclkout_rx_p, CLK_SET_RATE_PARENT, 644 RK3568_CLKSEL_CON(13), 15, 1, MFLAGS, 645 RK3568_CLKGATE_CON(6), 7, GFLAGS), 646 647 COMPOSITE(CLK_I2S1_8CH_TX_SRC, "clk_i2s1_8ch_tx_src", gpll_cpll_npll_p, 0, 648 RK3568_CLKSEL_CON(15), 8, 2, MFLAGS, 0, 7, DFLAGS, 649 RK3568_CLKGATE_CON(6), 8, GFLAGS), 650 COMPOSITE_FRACMUX(CLK_I2S1_8CH_TX_FRAC, "clk_i2s1_8ch_tx_frac", "clk_i2s1_8ch_tx_src", CLK_SET_RATE_PARENT, 651 RK3568_CLKSEL_CON(16), 0, 652 RK3568_CLKGATE_CON(6), 9, GFLAGS, 653 &rk3568_i2s1_8ch_tx_fracmux), 654 GATE(MCLK_I2S1_8CH_TX, "mclk_i2s1_8ch_tx", "clk_i2s1_8ch_tx", 0, 655 RK3568_CLKGATE_CON(6), 10, GFLAGS), 656 COMPOSITE_NODIV(I2S1_MCLKOUT_TX, "i2s1_mclkout_tx", i2s1_mclkout_tx_p, CLK_SET_RATE_PARENT, 657 RK3568_CLKSEL_CON(15), 15, 1, MFLAGS, 658 RK3568_CLKGATE_CON(6), 11, GFLAGS), 659 660 COMPOSITE(CLK_I2S1_8CH_RX_SRC, "clk_i2s1_8ch_rx_src", gpll_cpll_npll_p, 0, 661 RK3568_CLKSEL_CON(17), 8, 2, MFLAGS, 0, 7, DFLAGS, 662 RK3568_CLKGATE_CON(6), 12, GFLAGS), 663 COMPOSITE_FRACMUX(CLK_I2S1_8CH_RX_FRAC, "clk_i2s1_8ch_rx_frac", "clk_i2s1_8ch_rx_src", CLK_SET_RATE_PARENT, 664 RK3568_CLKSEL_CON(18), 0, 665 RK3568_CLKGATE_CON(6), 13, GFLAGS, 666 &rk3568_i2s1_8ch_rx_fracmux), 667 GATE(MCLK_I2S1_8CH_RX, "mclk_i2s1_8ch_rx", "clk_i2s1_8ch_rx", 0, 668 RK3568_CLKGATE_CON(6), 14, GFLAGS), 669 COMPOSITE_NODIV(I2S1_MCLKOUT_RX, "i2s1_mclkout_rx", i2s1_mclkout_rx_p, CLK_SET_RATE_PARENT, 670 RK3568_CLKSEL_CON(17), 15, 1, MFLAGS, 671 RK3568_CLKGATE_CON(6), 15, GFLAGS), 672 673 COMPOSITE(CLK_I2S2_2CH_SRC, "clk_i2s2_2ch_src", gpll_cpll_npll_p, 0, 674 RK3568_CLKSEL_CON(19), 8, 2, MFLAGS, 0, 7, DFLAGS, 675 RK3568_CLKGATE_CON(7), 0, GFLAGS), 676 COMPOSITE_FRACMUX(CLK_I2S2_2CH_FRAC, "clk_i2s2_2ch_frac", "clk_i2s2_2ch_src", CLK_SET_RATE_PARENT, 677 RK3568_CLKSEL_CON(20), 0, 678 RK3568_CLKGATE_CON(7), 1, GFLAGS, 679 &rk3568_i2s2_2ch_fracmux), 680 GATE(MCLK_I2S2_2CH, "mclk_i2s2_2ch", "clk_i2s2_2ch", 0, 681 RK3568_CLKGATE_CON(7), 2, GFLAGS), 682 COMPOSITE_NODIV(I2S2_MCLKOUT, "i2s2_mclkout", i2s2_mclkout_p, CLK_SET_RATE_PARENT, 683 RK3568_CLKSEL_CON(19), 15, 1, MFLAGS, 684 RK3568_CLKGATE_CON(7), 3, GFLAGS), 685 686 COMPOSITE(CLK_I2S3_2CH_TX_SRC, "clk_i2s3_2ch_tx_src", gpll_cpll_npll_p, 0, 687 RK3568_CLKSEL_CON(21), 8, 2, MFLAGS, 0, 7, DFLAGS, 688 RK3568_CLKGATE_CON(7), 4, GFLAGS), 689 COMPOSITE_FRACMUX(CLK_I2S3_2CH_TX_FRAC, "clk_i2s3_2ch_tx_frac", "clk_i2s3_2ch_tx_src", CLK_SET_RATE_PARENT, 690 RK3568_CLKSEL_CON(22), 0, 691 RK3568_CLKGATE_CON(7), 5, GFLAGS, 692 &rk3568_i2s3_2ch_tx_fracmux), 693 GATE(MCLK_I2S3_2CH_TX, "mclk_i2s3_2ch_tx", "clk_i2s3_2ch_tx", 0, 694 RK3568_CLKGATE_CON(7), 6, GFLAGS), 695 COMPOSITE_NODIV(I2S3_MCLKOUT_TX, "i2s3_mclkout_tx", i2s3_mclkout_tx_p, CLK_SET_RATE_PARENT, 696 RK3568_CLKSEL_CON(21), 15, 1, MFLAGS, 697 RK3568_CLKGATE_CON(7), 7, GFLAGS), 698 699 COMPOSITE(CLK_I2S3_2CH_RX_SRC, "clk_i2s3_2ch_rx_src", gpll_cpll_npll_p, 0, 700 RK3568_CLKSEL_CON(83), 8, 2, MFLAGS, 0, 7, DFLAGS, 701 RK3568_CLKGATE_CON(7), 8, GFLAGS), 702 COMPOSITE_FRACMUX(CLK_I2S3_2CH_RX_FRAC, "clk_i2s3_2ch_rx_frac", "clk_i2s3_2ch_rx_src", CLK_SET_RATE_PARENT, 703 RK3568_CLKSEL_CON(84), 0, 704 RK3568_CLKGATE_CON(7), 9, GFLAGS, 705 &rk3568_i2s3_2ch_rx_fracmux), 706 GATE(MCLK_I2S3_2CH_RX, "mclk_i2s3_2ch_rx", "clk_i2s3_2ch_rx", 0, 707 RK3568_CLKGATE_CON(7), 10, GFLAGS), 708 COMPOSITE_NODIV(I2S3_MCLKOUT_RX, "i2s3_mclkout_rx", i2s3_mclkout_rx_p, CLK_SET_RATE_PARENT, 709 RK3568_CLKSEL_CON(83), 15, 1, MFLAGS, 710 RK3568_CLKGATE_CON(7), 11, GFLAGS), 711 712 GATE(HCLK_PDM, "hclk_pdm", "hclk_gic_audio", 0, 713 RK3568_CLKGATE_CON(5), 14, GFLAGS), 714 COMPOSITE_NODIV(MCLK_PDM, "mclk_pdm", mclk_pdm_p, 0, 715 RK3568_CLKSEL_CON(23), 8, 2, MFLAGS, 716 RK3568_CLKGATE_CON(5), 15, GFLAGS), 717 GATE(HCLK_VAD, "hclk_vad", "hclk_gic_audio", 0, 718 RK3568_CLKGATE_CON(7), 12, GFLAGS), 719 GATE(HCLK_SPDIF_8CH, "hclk_spdif_8ch", "hclk_gic_audio", 0, 720 RK3568_CLKGATE_CON(7), 13, GFLAGS), 721 722 COMPOSITE(MCLK_SPDIF_8CH_SRC, "mclk_spdif_8ch_src", cpll_gpll_p, 0, 723 RK3568_CLKSEL_CON(23), 14, 1, MFLAGS, 0, 7, DFLAGS, 724 RK3568_CLKGATE_CON(7), 14, GFLAGS), 725 COMPOSITE_FRACMUX(MCLK_SPDIF_8CH_FRAC, "mclk_spdif_8ch_frac", "mclk_spdif_8ch_src", CLK_SET_RATE_PARENT, 726 RK3568_CLKSEL_CON(24), 0, 727 RK3568_CLKGATE_CON(7), 15, GFLAGS, 728 &rk3568_spdif_8ch_fracmux), 729 730 GATE(HCLK_AUDPWM, "hclk_audpwm", "hclk_gic_audio", 0, 731 RK3568_CLKGATE_CON(8), 0, GFLAGS), 732 COMPOSITE(SCLK_AUDPWM_SRC, "sclk_audpwm_src", gpll_cpll_p, 0, 733 RK3568_CLKSEL_CON(25), 14, 1, MFLAGS, 0, 6, DFLAGS, 734 RK3568_CLKGATE_CON(8), 1, GFLAGS), 735 COMPOSITE_FRACMUX(SCLK_AUDPWM_FRAC, "sclk_audpwm_frac", "sclk_audpwm_src", CLK_SET_RATE_PARENT, 736 RK3568_CLKSEL_CON(26), 0, 737 RK3568_CLKGATE_CON(8), 2, GFLAGS, 738 &rk3568_audpwm_fracmux), 739 740 GATE(HCLK_ACDCDIG, "hclk_acdcdig", "hclk_gic_audio", 0, 741 RK3568_CLKGATE_CON(8), 3, GFLAGS), 742 COMPOSITE_NODIV(CLK_ACDCDIG_I2C, "clk_acdcdig_i2c", clk_i2c_p, 0, 743 RK3568_CLKSEL_CON(23), 10, 2, MFLAGS, 744 RK3568_CLKGATE_CON(8), 4, GFLAGS), 745 GATE(CLK_ACDCDIG_DAC, "clk_acdcdig_dac", "mclk_i2s3_2ch_tx", 0, 746 RK3568_CLKGATE_CON(8), 5, GFLAGS), 747 GATE(CLK_ACDCDIG_ADC, "clk_acdcdig_adc", "mclk_i2s3_2ch_rx", 0, 748 RK3568_CLKGATE_CON(8), 6, GFLAGS), 749 750 /* PD_SECURE_FLASH */ 751 COMPOSITE_NODIV(ACLK_SECURE_FLASH, "aclk_secure_flash", gpll200_gpll150_gpll100_xin24m_p, 0, 752 RK3568_CLKSEL_CON(27), 0, 2, MFLAGS, 753 RK3568_CLKGATE_CON(8), 7, GFLAGS), 754 COMPOSITE_NODIV(HCLK_SECURE_FLASH, "hclk_secure_flash", gpll150_gpll100_gpll75_xin24m_p, 0, 755 RK3568_CLKSEL_CON(27), 2, 2, MFLAGS, 756 RK3568_CLKGATE_CON(8), 8, GFLAGS), 757 GATE(ACLK_CRYPTO_NS, "aclk_crypto_ns", "aclk_secure_flash", 0, 758 RK3568_CLKGATE_CON(8), 11, GFLAGS), 759 GATE(HCLK_CRYPTO_NS, "hclk_crypto_ns", "hclk_secure_flash", 0, 760 RK3568_CLKGATE_CON(8), 12, GFLAGS), 761 COMPOSITE_NODIV(CLK_CRYPTO_NS_CORE, "clk_crypto_ns_core", gpll200_gpll150_gpll100_p, 0, 762 RK3568_CLKSEL_CON(27), 4, 2, MFLAGS, 763 RK3568_CLKGATE_CON(8), 13, GFLAGS), 764 COMPOSITE_NODIV(CLK_CRYPTO_NS_PKA, "clk_crypto_ns_pka", gpll300_gpll200_gpll100_p, 0, 765 RK3568_CLKSEL_CON(27), 6, 2, MFLAGS, 766 RK3568_CLKGATE_CON(8), 14, GFLAGS), 767 GATE(CLK_CRYPTO_NS_RNG, "clk_crypto_ns_rng", "hclk_secure_flash", 0, 768 RK3568_CLKGATE_CON(8), 15, GFLAGS), 769 GATE(HCLK_TRNG_NS, "hclk_trng_ns", "hclk_secure_flash", CLK_IGNORE_UNUSED, 770 RK3568_CLKGATE_CON(9), 10, GFLAGS), 771 GATE(CLK_TRNG_NS, "clk_trng_ns", "hclk_secure_flash", CLK_IGNORE_UNUSED, 772 RK3568_CLKGATE_CON(9), 11, GFLAGS), 773 GATE(PCLK_OTPC_NS, "pclk_otpc_ns", "hclk_secure_flash", 0, 774 RK3568_CLKGATE_CON(26), 9, GFLAGS), 775 GATE(CLK_OTPC_NS_SBPI, "clk_otpc_ns_sbpi", "xin24m", 0, 776 RK3568_CLKGATE_CON(26), 10, GFLAGS), 777 GATE(CLK_OTPC_NS_USR, "clk_otpc_ns_usr", "xin_osc0_half", 0, 778 RK3568_CLKGATE_CON(26), 11, GFLAGS), 779 GATE(HCLK_NANDC, "hclk_nandc", "hclk_secure_flash", 0, 780 RK3568_CLKGATE_CON(9), 0, GFLAGS), 781 COMPOSITE_NODIV(NCLK_NANDC, "nclk_nandc", clk_nandc_p, 0, 782 RK3568_CLKSEL_CON(28), 0, 2, MFLAGS, 783 RK3568_CLKGATE_CON(9), 1, GFLAGS), 784 GATE(HCLK_SFC, "hclk_sfc", "hclk_secure_flash", 0, 785 RK3568_CLKGATE_CON(9), 2, GFLAGS), 786 GATE(HCLK_SFC_XIP, "hclk_sfc_xip", "hclk_secure_flash", 0, 787 RK3568_CLKGATE_CON(9), 3, GFLAGS), 788 COMPOSITE_NODIV(SCLK_SFC, "sclk_sfc", sclk_sfc_p, 0, 789 RK3568_CLKSEL_CON(28), 4, 3, MFLAGS, 790 RK3568_CLKGATE_CON(9), 4, GFLAGS), 791 GATE(ACLK_EMMC, "aclk_emmc", "aclk_secure_flash", 0, 792 RK3568_CLKGATE_CON(9), 5, GFLAGS), 793 GATE(HCLK_EMMC, "hclk_emmc", "hclk_secure_flash", 0, 794 RK3568_CLKGATE_CON(9), 6, GFLAGS), 795 COMPOSITE_NODIV(BCLK_EMMC, "bclk_emmc", gpll200_gpll150_cpll125_p, 0, 796 RK3568_CLKSEL_CON(28), 8, 2, MFLAGS, 797 RK3568_CLKGATE_CON(9), 7, GFLAGS), 798 COMPOSITE_NODIV(CCLK_EMMC, "cclk_emmc", cclk_emmc_p, 0, 799 RK3568_CLKSEL_CON(28), 12, 3, MFLAGS, 800 RK3568_CLKGATE_CON(9), 8, GFLAGS), 801 GATE(TCLK_EMMC, "tclk_emmc", "xin24m", 0, 802 RK3568_CLKGATE_CON(9), 9, GFLAGS), 803 MMC(SCLK_EMMC_DRV, "emmc_drv", "cclk_emmc", RK3568_EMMC_CON0, 1), 804 MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "cclk_emmc", RK3568_EMMC_CON1, 1), 805 806 /* PD_PIPE */ 807 COMPOSITE_NODIV(ACLK_PIPE, "aclk_pipe", aclk_pipe_p, 0, 808 RK3568_CLKSEL_CON(29), 0, 2, MFLAGS, 809 RK3568_CLKGATE_CON(10), 0, GFLAGS), 810 COMPOSITE_NOMUX(PCLK_PIPE, "pclk_pipe", "aclk_pipe", 0, 811 RK3568_CLKSEL_CON(29), 4, 4, DFLAGS, 812 RK3568_CLKGATE_CON(10), 1, GFLAGS), 813 GATE(ACLK_PCIE20_MST, "aclk_pcie20_mst", "aclk_pipe", 0, 814 RK3568_CLKGATE_CON(12), 0, GFLAGS), 815 GATE(ACLK_PCIE20_SLV, "aclk_pcie20_slv", "aclk_pipe", 0, 816 RK3568_CLKGATE_CON(12), 1, GFLAGS), 817 GATE(ACLK_PCIE20_DBI, "aclk_pcie20_dbi", "aclk_pipe", 0, 818 RK3568_CLKGATE_CON(12), 2, GFLAGS), 819 GATE(PCLK_PCIE20, "pclk_pcie20", "pclk_pipe", 0, 820 RK3568_CLKGATE_CON(12), 3, GFLAGS), 821 GATE(CLK_PCIE20_AUX_NDFT, "clk_pcie20_aux_ndft", "xin24m", 0, 822 RK3568_CLKGATE_CON(12), 4, GFLAGS), 823 GATE(ACLK_PCIE30X1_MST, "aclk_pcie30x1_mst", "aclk_pipe", 0, 824 RK3568_CLKGATE_CON(12), 8, GFLAGS), 825 GATE(ACLK_PCIE30X1_SLV, "aclk_pcie30x1_slv", "aclk_pipe", 0, 826 RK3568_CLKGATE_CON(12), 9, GFLAGS), 827 GATE(ACLK_PCIE30X1_DBI, "aclk_pcie30x1_dbi", "aclk_pipe", 0, 828 RK3568_CLKGATE_CON(12), 10, GFLAGS), 829 GATE(PCLK_PCIE30X1, "pclk_pcie30x1", "pclk_pipe", 0, 830 RK3568_CLKGATE_CON(12), 11, GFLAGS), 831 GATE(CLK_PCIE30X1_AUX_NDFT, "clk_pcie30x1_aux_ndft", "xin24m", 0, 832 RK3568_CLKGATE_CON(12), 12, GFLAGS), 833 GATE(ACLK_PCIE30X2_MST, "aclk_pcie30x2_mst", "aclk_pipe", 0, 834 RK3568_CLKGATE_CON(13), 0, GFLAGS), 835 GATE(ACLK_PCIE30X2_SLV, "aclk_pcie30x2_slv", "aclk_pipe", 0, 836 RK3568_CLKGATE_CON(13), 1, GFLAGS), 837 GATE(ACLK_PCIE30X2_DBI, "aclk_pcie30x2_dbi", "aclk_pipe", 0, 838 RK3568_CLKGATE_CON(13), 2, GFLAGS), 839 GATE(PCLK_PCIE30X2, "pclk_pcie30x2", "pclk_pipe", 0, 840 RK3568_CLKGATE_CON(13), 3, GFLAGS), 841 GATE(CLK_PCIE30X2_AUX_NDFT, "clk_pcie30x2_aux_ndft", "xin24m", 0, 842 RK3568_CLKGATE_CON(13), 4, GFLAGS), 843 GATE(ACLK_SATA0, "aclk_sata0", "aclk_pipe", 0, 844 RK3568_CLKGATE_CON(11), 0, GFLAGS), 845 GATE(CLK_SATA0_PMALIVE, "clk_sata0_pmalive", "gpll_20m", 0, 846 RK3568_CLKGATE_CON(11), 1, GFLAGS), 847 GATE(CLK_SATA0_RXOOB, "clk_sata0_rxoob", "cpll_50m", 0, 848 RK3568_CLKGATE_CON(11), 2, GFLAGS), 849 GATE(ACLK_SATA1, "aclk_sata1", "aclk_pipe", 0, 850 RK3568_CLKGATE_CON(11), 4, GFLAGS), 851 GATE(CLK_SATA1_PMALIVE, "clk_sata1_pmalive", "gpll_20m", 0, 852 RK3568_CLKGATE_CON(11), 5, GFLAGS), 853 GATE(CLK_SATA1_RXOOB, "clk_sata1_rxoob", "cpll_50m", 0, 854 RK3568_CLKGATE_CON(11), 6, GFLAGS), 855 GATE(ACLK_SATA2, "aclk_sata2", "aclk_pipe", 0, 856 RK3568_CLKGATE_CON(11), 8, GFLAGS), 857 GATE(CLK_SATA2_PMALIVE, "clk_sata2_pmalive", "gpll_20m", 0, 858 RK3568_CLKGATE_CON(11), 9, GFLAGS), 859 GATE(CLK_SATA2_RXOOB, "clk_sata2_rxoob", "cpll_50m", 0, 860 RK3568_CLKGATE_CON(11), 10, GFLAGS), 861 GATE(ACLK_USB3OTG0, "aclk_usb3otg0", "aclk_pipe", 0, 862 RK3568_CLKGATE_CON(10), 8, GFLAGS), 863 GATE(CLK_USB3OTG0_REF, "clk_usb3otg0_ref", "xin24m", 0, 864 RK3568_CLKGATE_CON(10), 9, GFLAGS), 865 COMPOSITE_NODIV(CLK_USB3OTG0_SUSPEND, "clk_usb3otg0_suspend", xin24m_32k_p, 0, 866 RK3568_CLKSEL_CON(29), 8, 1, MFLAGS, 867 RK3568_CLKGATE_CON(10), 10, GFLAGS), 868 GATE(ACLK_USB3OTG1, "aclk_usb3otg1", "aclk_pipe", 0, 869 RK3568_CLKGATE_CON(10), 12, GFLAGS), 870 GATE(CLK_USB3OTG1_REF, "clk_usb3otg1_ref", "xin24m", 0, 871 RK3568_CLKGATE_CON(10), 13, GFLAGS), 872 COMPOSITE_NODIV(CLK_USB3OTG1_SUSPEND, "clk_usb3otg1_suspend", xin24m_32k_p, 0, 873 RK3568_CLKSEL_CON(29), 9, 1, MFLAGS, 874 RK3568_CLKGATE_CON(10), 14, GFLAGS), 875 COMPOSITE_NODIV(CLK_XPCS_EEE, "clk_xpcs_eee", gpll200_cpll125_p, 0, 876 RK3568_CLKSEL_CON(29), 13, 1, MFLAGS, 877 RK3568_CLKGATE_CON(10), 4, GFLAGS), 878 GATE(PCLK_XPCS, "pclk_xpcs", "pclk_pipe", 0, 879 RK3568_CLKGATE_CON(13), 6, GFLAGS), 880 881 /* PD_PHP */ 882 COMPOSITE_NODIV(ACLK_PHP, "aclk_php", gpll300_gpll200_gpll100_xin24m_p, 0, 883 RK3568_CLKSEL_CON(30), 0, 2, MFLAGS, 884 RK3568_CLKGATE_CON(14), 8, GFLAGS), 885 COMPOSITE_NODIV(HCLK_PHP, "hclk_php", gpll150_gpll100_gpll75_xin24m_p, 0, 886 RK3568_CLKSEL_CON(30), 2, 2, MFLAGS, 887 RK3568_CLKGATE_CON(14), 9, GFLAGS), 888 COMPOSITE_NOMUX(PCLK_PHP, "pclk_php", "aclk_php", 0, 889 RK3568_CLKSEL_CON(30), 4, 4, DFLAGS, 890 RK3568_CLKGATE_CON(14), 10, GFLAGS), 891 GATE(HCLK_SDMMC0, "hclk_sdmmc0", "hclk_php", 0, 892 RK3568_CLKGATE_CON(15), 0, GFLAGS), 893 COMPOSITE_NODIV(CLK_SDMMC0, "clk_sdmmc0", clk_sdmmc_p, 0, 894 RK3568_CLKSEL_CON(30), 8, 3, MFLAGS, 895 RK3568_CLKGATE_CON(15), 1, GFLAGS), 896 MMC(SCLK_SDMMC0_DRV, "sdmmc0_drv", "clk_sdmmc0", RK3568_SDMMC0_CON0, 1), 897 MMC(SCLK_SDMMC0_SAMPLE, "sdmmc0_sample", "clk_sdmmc0", RK3568_SDMMC0_CON1, 1), 898 899 GATE(HCLK_SDMMC1, "hclk_sdmmc1", "hclk_php", 0, 900 RK3568_CLKGATE_CON(15), 2, GFLAGS), 901 COMPOSITE_NODIV(CLK_SDMMC1, "clk_sdmmc1", clk_sdmmc_p, 0, 902 RK3568_CLKSEL_CON(30), 12, 3, MFLAGS, 903 RK3568_CLKGATE_CON(15), 3, GFLAGS), 904 MMC(SCLK_SDMMC1_DRV, "sdmmc1_drv", "clk_sdmmc1", RK3568_SDMMC1_CON0, 1), 905 MMC(SCLK_SDMMC1_SAMPLE, "sdmmc1_sample", "clk_sdmmc1", RK3568_SDMMC1_CON1, 1), 906 907 GATE(ACLK_GMAC0, "aclk_gmac0", "aclk_php", 0, 908 RK3568_CLKGATE_CON(15), 5, GFLAGS), 909 GATE(PCLK_GMAC0, "pclk_gmac0", "pclk_php", 0, 910 RK3568_CLKGATE_CON(15), 6, GFLAGS), 911 COMPOSITE_NODIV(CLK_MAC0_2TOP, "clk_mac0_2top", clk_mac_2top_p, 0, 912 RK3568_CLKSEL_CON(31), 8, 2, MFLAGS, 913 RK3568_CLKGATE_CON(15), 7, GFLAGS), 914 COMPOSITE_NODIV(CLK_MAC0_OUT, "clk_mac0_out", cpll125_cpll50_cpll25_xin24m_p, 0, 915 RK3568_CLKSEL_CON(31), 14, 2, MFLAGS, 916 RK3568_CLKGATE_CON(15), 8, GFLAGS), 917 GATE(CLK_MAC0_REFOUT, "clk_mac0_refout", "clk_mac0_2top", 0, 918 RK3568_CLKGATE_CON(15), 12, GFLAGS), 919 COMPOSITE_NODIV(CLK_GMAC0_PTP_REF, "clk_gmac0_ptp_ref", clk_gmac_ptp_p, 0, 920 RK3568_CLKSEL_CON(31), 12, 2, MFLAGS, 921 RK3568_CLKGATE_CON(15), 4, GFLAGS), 922 MUX(SCLK_GMAC0, "clk_gmac0", mux_gmac0_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 923 RK3568_CLKSEL_CON(31), 2, 1, MFLAGS), 924 FACTOR(0, "clk_gmac0_tx_div5", "clk_gmac0", 0, 1, 5), 925 FACTOR(0, "clk_gmac0_tx_div50", "clk_gmac0", 0, 1, 50), 926 FACTOR(0, "clk_gmac0_rx_div2", "clk_gmac0", 0, 1, 2), 927 FACTOR(0, "clk_gmac0_rx_div20", "clk_gmac0", 0, 1, 20), 928 MUX(SCLK_GMAC0_RGMII_SPEED, "clk_gmac0_rgmii_speed", mux_gmac0_rgmii_speed_p, 0, 929 RK3568_CLKSEL_CON(31), 4, 2, MFLAGS), 930 MUX(SCLK_GMAC0_RMII_SPEED, "clk_gmac0_rmii_speed", mux_gmac0_rmii_speed_p, 0, 931 RK3568_CLKSEL_CON(31), 3, 1, MFLAGS), 932 MUX(SCLK_GMAC0_RX_TX, "clk_gmac0_rx_tx", mux_gmac0_rx_tx_p, CLK_SET_RATE_PARENT, 933 RK3568_CLKSEL_CON(31), 0, 2, MFLAGS), 934 935 /* PD_USB */ 936 COMPOSITE_NODIV(ACLK_USB, "aclk_usb", gpll300_gpll200_gpll100_xin24m_p, 0, 937 RK3568_CLKSEL_CON(32), 0, 2, MFLAGS, 938 RK3568_CLKGATE_CON(16), 0, GFLAGS), 939 COMPOSITE_NODIV(HCLK_USB, "hclk_usb", gpll150_gpll100_gpll75_xin24m_p, 0, 940 RK3568_CLKSEL_CON(32), 2, 2, MFLAGS, 941 RK3568_CLKGATE_CON(16), 1, GFLAGS), 942 COMPOSITE_NOMUX(PCLK_USB, "pclk_usb", "aclk_usb", 0, 943 RK3568_CLKSEL_CON(32), 4, 4, DFLAGS, 944 RK3568_CLKGATE_CON(16), 2, GFLAGS), 945 GATE(HCLK_USB2HOST0, "hclk_usb2host0", "hclk_usb", 0, 946 RK3568_CLKGATE_CON(16), 12, GFLAGS), 947 GATE(HCLK_USB2HOST0_ARB, "hclk_usb2host0_arb", "hclk_usb", 0, 948 RK3568_CLKGATE_CON(16), 13, GFLAGS), 949 GATE(HCLK_USB2HOST1, "hclk_usb2host1", "hclk_usb", 0, 950 RK3568_CLKGATE_CON(16), 14, GFLAGS), 951 GATE(HCLK_USB2HOST1_ARB, "hclk_usb2host1_arb", "hclk_usb", 0, 952 RK3568_CLKGATE_CON(16), 15, GFLAGS), 953 GATE(HCLK_SDMMC2, "hclk_sdmmc2", "hclk_usb", 0, 954 RK3568_CLKGATE_CON(17), 0, GFLAGS), 955 COMPOSITE_NODIV(CLK_SDMMC2, "clk_sdmmc2", clk_sdmmc_p, 0, 956 RK3568_CLKSEL_CON(32), 8, 3, MFLAGS, 957 RK3568_CLKGATE_CON(17), 1, GFLAGS), 958 MMC(SCLK_SDMMC2_DRV, "sdmmc2_drv", "clk_sdmmc2", RK3568_SDMMC2_CON0, 1), 959 MMC(SCLK_SDMMC2_SAMPLE, "sdmmc2_sample", "clk_sdmmc2", RK3568_SDMMC2_CON1, 1), 960 961 GATE(ACLK_GMAC1, "aclk_gmac1", "aclk_usb", 0, 962 RK3568_CLKGATE_CON(17), 3, GFLAGS), 963 GATE(PCLK_GMAC1, "pclk_gmac1", "pclk_usb", 0, 964 RK3568_CLKGATE_CON(17), 4, GFLAGS), 965 COMPOSITE_NODIV(CLK_MAC1_2TOP, "clk_mac1_2top", clk_mac_2top_p, 0, 966 RK3568_CLKSEL_CON(33), 8, 2, MFLAGS, 967 RK3568_CLKGATE_CON(17), 5, GFLAGS), 968 COMPOSITE_NODIV(CLK_MAC1_OUT, "clk_mac1_out", cpll125_cpll50_cpll25_xin24m_p, 0, 969 RK3568_CLKSEL_CON(33), 14, 2, MFLAGS, 970 RK3568_CLKGATE_CON(17), 6, GFLAGS), 971 GATE(CLK_MAC1_REFOUT, "clk_mac1_refout", "clk_mac1_2top", 0, 972 RK3568_CLKGATE_CON(17), 10, GFLAGS), 973 COMPOSITE_NODIV(CLK_GMAC1_PTP_REF, "clk_gmac1_ptp_ref", clk_gmac_ptp_p, 0, 974 RK3568_CLKSEL_CON(33), 12, 2, MFLAGS, 975 RK3568_CLKGATE_CON(17), 2, GFLAGS), 976 MUX(SCLK_GMAC1, "clk_gmac1", mux_gmac1_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 977 RK3568_CLKSEL_CON(33), 2, 1, MFLAGS), 978 FACTOR(0, "clk_gmac1_tx_div5", "clk_gmac1", 0, 1, 5), 979 FACTOR(0, "clk_gmac1_tx_div50", "clk_gmac1", 0, 1, 50), 980 FACTOR(0, "clk_gmac1_rx_div2", "clk_gmac1", 0, 1, 2), 981 FACTOR(0, "clk_gmac1_rx_div20", "clk_gmac1", 0, 1, 20), 982 MUX(SCLK_GMAC1_RGMII_SPEED, "clk_gmac1_rgmii_speed", mux_gmac1_rgmii_speed_p, 0, 983 RK3568_CLKSEL_CON(33), 4, 2, MFLAGS), 984 MUX(SCLK_GMAC1_RMII_SPEED, "clk_gmac1_rmii_speed", mux_gmac1_rmii_speed_p, 0, 985 RK3568_CLKSEL_CON(33), 3, 1, MFLAGS), 986 MUX(SCLK_GMAC1_RX_TX, "clk_gmac1_rx_tx", mux_gmac1_rx_tx_p, CLK_SET_RATE_PARENT, 987 RK3568_CLKSEL_CON(33), 0, 2, MFLAGS), 988 989 /* PD_PERI */ 990 COMPOSITE_NODIV(ACLK_PERIMID, "aclk_perimid", gpll300_gpll200_gpll100_xin24m_p, CLK_IGNORE_UNUSED, 991 RK3568_CLKSEL_CON(10), 4, 2, MFLAGS, 992 RK3568_CLKGATE_CON(14), 0, GFLAGS), 993 COMPOSITE_NODIV(HCLK_PERIMID, "hclk_perimid", gpll150_gpll100_gpll75_xin24m_p, CLK_IGNORE_UNUSED, 994 RK3568_CLKSEL_CON(10), 6, 2, MFLAGS, 995 RK3568_CLKGATE_CON(14), 1, GFLAGS), 996 997 /* PD_VI */ 998 COMPOSITE_NODIV(ACLK_VI, "aclk_vi", gpll400_gpll300_gpll200_xin24m_p, 0, 999 RK3568_CLKSEL_CON(34), 0, 2, MFLAGS, 1000 RK3568_CLKGATE_CON(18), 0, GFLAGS), 1001 COMPOSITE_NOMUX(HCLK_VI, "hclk_vi", "aclk_vi", 0, 1002 RK3568_CLKSEL_CON(34), 4, 4, DFLAGS, 1003 RK3568_CLKGATE_CON(18), 1, GFLAGS), 1004 COMPOSITE_NOMUX(PCLK_VI, "pclk_vi", "aclk_vi", 0, 1005 RK3568_CLKSEL_CON(34), 8, 4, DFLAGS, 1006 RK3568_CLKGATE_CON(18), 2, GFLAGS), 1007 GATE(ACLK_VICAP, "aclk_vicap", "aclk_vi", 0, 1008 RK3568_CLKGATE_CON(18), 9, GFLAGS), 1009 GATE(HCLK_VICAP, "hclk_vicap", "hclk_vi", 0, 1010 RK3568_CLKGATE_CON(18), 10, GFLAGS), 1011 COMPOSITE_NODIV(DCLK_VICAP, "dclk_vicap", cpll333_gpll300_gpll200_p, 0, 1012 RK3568_CLKSEL_CON(34), 14, 2, MFLAGS, 1013 RK3568_CLKGATE_CON(18), 11, GFLAGS), 1014 GATE(ICLK_VICAP_G, "iclk_vicap_g", "iclk_vicap", 0, 1015 RK3568_CLKGATE_CON(18), 13, GFLAGS), 1016 GATE(ACLK_ISP, "aclk_isp", "aclk_vi", 0, 1017 RK3568_CLKGATE_CON(19), 0, GFLAGS), 1018 GATE(HCLK_ISP, "hclk_isp", "hclk_vi", 0, 1019 RK3568_CLKGATE_CON(19), 1, GFLAGS), 1020 COMPOSITE(CLK_ISP, "clk_isp", cpll_gpll_hpll_p, 0, 1021 RK3568_CLKSEL_CON(35), 6, 2, MFLAGS, 0, 5, DFLAGS, 1022 RK3568_CLKGATE_CON(19), 2, GFLAGS), 1023 GATE(PCLK_CSI2HOST1, "pclk_csi2host1", "pclk_vi", 0, 1024 RK3568_CLKGATE_CON(19), 4, GFLAGS), 1025 COMPOSITE(CLK_CIF_OUT, "clk_cif_out", gpll_usb480m_xin24m_p, 0, 1026 RK3568_CLKSEL_CON(35), 14, 2, MFLAGS, 8, 6, DFLAGS, 1027 RK3568_CLKGATE_CON(19), 8, GFLAGS), 1028 COMPOSITE(CLK_CAM0_OUT, "clk_cam0_out", gpll_usb480m_xin24m_p, 0, 1029 RK3568_CLKSEL_CON(36), 6, 2, MFLAGS, 0, 6, DFLAGS, 1030 RK3568_CLKGATE_CON(19), 9, GFLAGS), 1031 COMPOSITE(CLK_CAM1_OUT, "clk_cam1_out", gpll_usb480m_xin24m_p, 0, 1032 RK3568_CLKSEL_CON(36), 14, 2, MFLAGS, 8, 6, DFLAGS, 1033 RK3568_CLKGATE_CON(19), 10, GFLAGS), 1034 1035 /* PD_VO */ 1036 COMPOSITE_NODIV(ACLK_VO, "aclk_vo", gpll300_cpll250_gpll100_xin24m_p, 0, 1037 RK3568_CLKSEL_CON(37), 0, 2, MFLAGS, 1038 RK3568_CLKGATE_CON(20), 0, GFLAGS), 1039 COMPOSITE_NOMUX(HCLK_VO, "hclk_vo", "aclk_vo", 0, 1040 RK3568_CLKSEL_CON(37), 8, 4, DFLAGS, 1041 RK3568_CLKGATE_CON(20), 1, GFLAGS), 1042 COMPOSITE_NOMUX(PCLK_VO, "pclk_vo", "aclk_vo", 0, 1043 RK3568_CLKSEL_CON(37), 12, 4, DFLAGS, 1044 RK3568_CLKGATE_CON(20), 2, GFLAGS), 1045 COMPOSITE(ACLK_VOP_PRE, "aclk_vop_pre", cpll_gpll_hpll_vpll_p, 0, 1046 RK3568_CLKSEL_CON(38), 6, 2, MFLAGS, 0, 5, DFLAGS, 1047 RK3568_CLKGATE_CON(20), 6, GFLAGS), 1048 GATE(ACLK_VOP, "aclk_vop", "aclk_vop_pre", 0, 1049 RK3568_CLKGATE_CON(20), 8, GFLAGS), 1050 GATE(HCLK_VOP, "hclk_vop", "hclk_vo", 0, 1051 RK3568_CLKGATE_CON(20), 9, GFLAGS), 1052 COMPOSITE(DCLK_VOP0, "dclk_vop0", hpll_vpll_gpll_cpll_p, CLK_SET_RATE_NO_REPARENT, 1053 RK3568_CLKSEL_CON(39), 10, 2, MFLAGS, 0, 8, DFLAGS, 1054 RK3568_CLKGATE_CON(20), 10, GFLAGS), 1055 COMPOSITE(DCLK_VOP1, "dclk_vop1", hpll_vpll_gpll_cpll_p, CLK_SET_RATE_NO_REPARENT, 1056 RK3568_CLKSEL_CON(40), 10, 2, MFLAGS, 0, 8, DFLAGS, 1057 RK3568_CLKGATE_CON(20), 11, GFLAGS), 1058 COMPOSITE(DCLK_VOP2, "dclk_vop2", hpll_vpll_gpll_cpll_p, CLK_SET_RATE_NO_REPARENT, 1059 RK3568_CLKSEL_CON(41), 10, 2, MFLAGS, 0, 8, DFLAGS, 1060 RK3568_CLKGATE_CON(20), 12, GFLAGS), 1061 GATE(CLK_VOP_PWM, "clk_vop_pwm", "xin24m", 0, 1062 RK3568_CLKGATE_CON(20), 13, GFLAGS), 1063 GATE(ACLK_HDCP, "aclk_hdcp", "aclk_vo", 0, 1064 RK3568_CLKGATE_CON(21), 0, GFLAGS), 1065 GATE(HCLK_HDCP, "hclk_hdcp", "hclk_vo", 0, 1066 RK3568_CLKGATE_CON(21), 1, GFLAGS), 1067 GATE(PCLK_HDCP, "pclk_hdcp", "pclk_vo", 0, 1068 RK3568_CLKGATE_CON(21), 2, GFLAGS), 1069 GATE(PCLK_HDMI_HOST, "pclk_hdmi_host", "pclk_vo", 0, 1070 RK3568_CLKGATE_CON(21), 3, GFLAGS), 1071 GATE(CLK_HDMI_SFR, "clk_hdmi_sfr", "xin24m", 0, 1072 RK3568_CLKGATE_CON(21), 4, GFLAGS), 1073 GATE(CLK_HDMI_CEC, "clk_hdmi_cec", "clk_rtc_32k", 0, 1074 RK3568_CLKGATE_CON(21), 5, GFLAGS), 1075 GATE(PCLK_DSITX_0, "pclk_dsitx_0", "pclk_vo", 0, 1076 RK3568_CLKGATE_CON(21), 6, GFLAGS), 1077 GATE(PCLK_DSITX_1, "pclk_dsitx_1", "pclk_vo", 0, 1078 RK3568_CLKGATE_CON(21), 7, GFLAGS), 1079 GATE(PCLK_EDP_CTRL, "pclk_edp_ctrl", "pclk_vo", 0, 1080 RK3568_CLKGATE_CON(21), 8, GFLAGS), 1081 COMPOSITE_NODIV(CLK_EDP_200M, "clk_edp_200m", gpll200_gpll150_cpll125_p, 0, 1082 RK3568_CLKSEL_CON(38), 8, 2, MFLAGS, 1083 RK3568_CLKGATE_CON(21), 9, GFLAGS), 1084 1085 /* PD_VPU */ 1086 COMPOSITE(ACLK_VPU_PRE, "aclk_vpu_pre", gpll_cpll_p, 0, 1087 RK3568_CLKSEL_CON(42), 7, 1, MFLAGS, 0, 5, DFLAGS, 1088 RK3568_CLKGATE_CON(22), 0, GFLAGS), 1089 COMPOSITE_NOMUX(HCLK_VPU_PRE, "hclk_vpu_pre", "aclk_vpu_pre", 0, 1090 RK3568_CLKSEL_CON(42), 8, 4, DFLAGS, 1091 RK3568_CLKGATE_CON(22), 1, GFLAGS), 1092 GATE(ACLK_VPU, "aclk_vpu", "aclk_vpu_pre", 0, 1093 RK3568_CLKGATE_CON(22), 4, GFLAGS), 1094 GATE(HCLK_VPU, "hclk_vpu", "hclk_vpu_pre", 0, 1095 RK3568_CLKGATE_CON(22), 5, GFLAGS), 1096 1097 /* PD_RGA */ 1098 COMPOSITE_NODIV(ACLK_RGA_PRE, "aclk_rga_pre", gpll300_cpll250_gpll100_xin24m_p, 0, 1099 RK3568_CLKSEL_CON(43), 0, 2, MFLAGS, 1100 RK3568_CLKGATE_CON(23), 0, GFLAGS), 1101 COMPOSITE_NOMUX(HCLK_RGA_PRE, "hclk_rga_pre", "aclk_rga_pre", 0, 1102 RK3568_CLKSEL_CON(43), 8, 4, DFLAGS, 1103 RK3568_CLKGATE_CON(23), 1, GFLAGS), 1104 COMPOSITE_NOMUX(PCLK_RGA_PRE, "pclk_rga_pre", "aclk_rga_pre", 0, 1105 RK3568_CLKSEL_CON(43), 12, 4, DFLAGS, 1106 RK3568_CLKGATE_CON(22), 12, GFLAGS), 1107 GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre", 0, 1108 RK3568_CLKGATE_CON(23), 4, GFLAGS), 1109 GATE(HCLK_RGA, "hclk_rga", "hclk_rga_pre", 0, 1110 RK3568_CLKGATE_CON(23), 5, GFLAGS), 1111 COMPOSITE_NODIV(CLK_RGA_CORE, "clk_rga_core", gpll300_gpll200_gpll100_p, 0, 1112 RK3568_CLKSEL_CON(43), 2, 2, MFLAGS, 1113 RK3568_CLKGATE_CON(23), 6, GFLAGS), 1114 GATE(ACLK_IEP, "aclk_iep", "aclk_rga_pre", 0, 1115 RK3568_CLKGATE_CON(23), 7, GFLAGS), 1116 GATE(HCLK_IEP, "hclk_iep", "hclk_rga_pre", 0, 1117 RK3568_CLKGATE_CON(23), 8, GFLAGS), 1118 COMPOSITE_NODIV(CLK_IEP_CORE, "clk_iep_core", gpll300_gpll200_gpll100_p, 0, 1119 RK3568_CLKSEL_CON(43), 4, 2, MFLAGS, 1120 RK3568_CLKGATE_CON(23), 9, GFLAGS), 1121 GATE(HCLK_EBC, "hclk_ebc", "hclk_rga_pre", 0, RK3568_CLKGATE_CON(23), 10, GFLAGS), 1122 COMPOSITE_NODIV(DCLK_EBC, "dclk_ebc", gpll400_cpll333_gpll200_p, 0, 1123 RK3568_CLKSEL_CON(43), 6, 2, MFLAGS, 1124 RK3568_CLKGATE_CON(23), 11, GFLAGS), 1125 GATE(ACLK_JDEC, "aclk_jdec", "aclk_rga_pre", 0, 1126 RK3568_CLKGATE_CON(23), 12, GFLAGS), 1127 GATE(HCLK_JDEC, "hclk_jdec", "hclk_rga_pre", 0, 1128 RK3568_CLKGATE_CON(23), 13, GFLAGS), 1129 GATE(ACLK_JENC, "aclk_jenc", "aclk_rga_pre", 0, 1130 RK3568_CLKGATE_CON(23), 14, GFLAGS), 1131 GATE(HCLK_JENC, "hclk_jenc", "hclk_rga_pre", 0, 1132 RK3568_CLKGATE_CON(23), 15, GFLAGS), 1133 GATE(PCLK_EINK, "pclk_eink", "pclk_rga_pre", 0, 1134 RK3568_CLKGATE_CON(22), 14, GFLAGS), 1135 GATE(HCLK_EINK, "hclk_eink", "hclk_rga_pre", 0, 1136 RK3568_CLKGATE_CON(22), 15, GFLAGS), 1137 1138 /* PD_RKVENC */ 1139 COMPOSITE(ACLK_RKVENC_PRE, "aclk_rkvenc_pre", gpll_cpll_npll_p, 0, 1140 RK3568_CLKSEL_CON(44), 6, 2, MFLAGS, 0, 5, DFLAGS, 1141 RK3568_CLKGATE_CON(24), 0, GFLAGS), 1142 COMPOSITE_NOMUX(HCLK_RKVENC_PRE, "hclk_rkvenc_pre", "aclk_rkvenc_pre", 0, 1143 RK3568_CLKSEL_CON(44), 8, 4, DFLAGS, 1144 RK3568_CLKGATE_CON(24), 1, GFLAGS), 1145 GATE(ACLK_RKVENC, "aclk_rkvenc", "aclk_rkvenc_pre", 0, 1146 RK3568_CLKGATE_CON(24), 6, GFLAGS), 1147 GATE(HCLK_RKVENC, "hclk_rkvenc", "hclk_rkvenc_pre", 0, 1148 RK3568_CLKGATE_CON(24), 7, GFLAGS), 1149 COMPOSITE(CLK_RKVENC_CORE, "clk_rkvenc_core", gpll_cpll_npll_vpll_p, 0, 1150 RK3568_CLKSEL_CON(45), 14, 2, MFLAGS, 0, 5, DFLAGS, 1151 RK3568_CLKGATE_CON(24), 8, GFLAGS), 1152 COMPOSITE(ACLK_RKVDEC_PRE, "aclk_rkvdec_pre", aclk_rkvdec_pre_p, CLK_SET_RATE_NO_REPARENT, 1153 RK3568_CLKSEL_CON(47), 7, 1, MFLAGS, 0, 5, DFLAGS, 1154 RK3568_CLKGATE_CON(25), 0, GFLAGS), 1155 COMPOSITE_NOMUX(HCLK_RKVDEC_PRE, "hclk_rkvdec_pre", "aclk_rkvdec_pre", 0, 1156 RK3568_CLKSEL_CON(47), 8, 4, DFLAGS, 1157 RK3568_CLKGATE_CON(25), 1, GFLAGS), 1158 GATE(ACLK_RKVDEC, "aclk_rkvdec", "aclk_rkvdec_pre", 0, 1159 RK3568_CLKGATE_CON(25), 4, GFLAGS), 1160 GATE(HCLK_RKVDEC, "hclk_rkvdec", "hclk_rkvdec_pre", 0, 1161 RK3568_CLKGATE_CON(25), 5, GFLAGS), 1162 COMPOSITE(CLK_RKVDEC_CA, "clk_rkvdec_ca", gpll_cpll_npll_vpll_p, 0, 1163 RK3568_CLKSEL_CON(48), 6, 2, MFLAGS, 0, 5, DFLAGS, 1164 RK3568_CLKGATE_CON(25), 6, GFLAGS), 1165 COMPOSITE(CLK_RKVDEC_CORE, "clk_rkvdec_core", clk_rkvdec_core_p, CLK_SET_RATE_NO_REPARENT, 1166 RK3568_CLKSEL_CON(49), 14, 2, MFLAGS, 8, 5, DFLAGS, 1167 RK3568_CLKGATE_CON(25), 7, GFLAGS), 1168 COMPOSITE(CLK_RKVDEC_HEVC_CA, "clk_rkvdec_hevc_ca", gpll_cpll_npll_vpll_p, 0, 1169 RK3568_CLKSEL_CON(49), 6, 2, MFLAGS, 0, 5, DFLAGS, 1170 RK3568_CLKGATE_CON(25), 8, GFLAGS), 1171 1172 /* PD_BUS */ 1173 COMPOSITE_NODIV(ACLK_BUS, "aclk_bus", gpll200_gpll150_gpll100_xin24m_p, 0, 1174 RK3568_CLKSEL_CON(50), 0, 2, MFLAGS, 1175 RK3568_CLKGATE_CON(26), 0, GFLAGS), 1176 COMPOSITE_NODIV(PCLK_BUS, "pclk_bus", gpll100_gpll75_cpll50_xin24m_p, 0, 1177 RK3568_CLKSEL_CON(50), 4, 2, MFLAGS, 1178 RK3568_CLKGATE_CON(26), 1, GFLAGS), 1179 GATE(PCLK_TSADC, "pclk_tsadc", "pclk_bus", 0, 1180 RK3568_CLKGATE_CON(26), 4, GFLAGS), 1181 COMPOSITE(CLK_TSADC_TSEN, "clk_tsadc_tsen", xin24m_gpll100_cpll100_p, 0, 1182 RK3568_CLKSEL_CON(51), 4, 2, MFLAGS, 0, 3, DFLAGS, 1183 RK3568_CLKGATE_CON(26), 5, GFLAGS), 1184 COMPOSITE_NOMUX(CLK_TSADC, "clk_tsadc", "clk_tsadc_tsen", 0, 1185 RK3568_CLKSEL_CON(51), 8, 7, DFLAGS, 1186 RK3568_CLKGATE_CON(26), 6, GFLAGS), 1187 GATE(PCLK_SARADC, "pclk_saradc", "pclk_bus", 0, 1188 RK3568_CLKGATE_CON(26), 7, GFLAGS), 1189 GATE(CLK_SARADC, "clk_saradc", "xin24m", 0, 1190 RK3568_CLKGATE_CON(26), 8, GFLAGS), 1191 GATE(PCLK_SCR, "pclk_scr", "pclk_bus", CLK_IGNORE_UNUSED, 1192 RK3568_CLKGATE_CON(26), 12, GFLAGS), 1193 GATE(PCLK_WDT_NS, "pclk_wdt_ns", "pclk_bus", 0, 1194 RK3568_CLKGATE_CON(26), 13, GFLAGS), 1195 GATE(TCLK_WDT_NS, "tclk_wdt_ns", "xin24m", 0, 1196 RK3568_CLKGATE_CON(26), 14, GFLAGS), 1197 GATE(ACLK_MCU, "aclk_mcu", "aclk_bus", CLK_IGNORE_UNUSED, 1198 RK3568_CLKGATE_CON(32), 13, GFLAGS), 1199 GATE(PCLK_INTMUX, "pclk_intmux", "pclk_bus", CLK_IGNORE_UNUSED, 1200 RK3568_CLKGATE_CON(32), 14, GFLAGS), 1201 GATE(PCLK_MAILBOX, "pclk_mailbox", "pclk_bus", 0, 1202 RK3568_CLKGATE_CON(32), 15, GFLAGS), 1203 1204 GATE(PCLK_UART1, "pclk_uart1", "pclk_bus", 0, 1205 RK3568_CLKGATE_CON(27), 12, GFLAGS), 1206 COMPOSITE(CLK_UART1_SRC, "clk_uart1_src", gpll_cpll_usb480m_p, 0, 1207 RK3568_CLKSEL_CON(52), 8, 2, MFLAGS, 0, 7, DFLAGS, 1208 RK3568_CLKGATE_CON(27), 13, GFLAGS), 1209 COMPOSITE_FRACMUX(CLK_UART1_FRAC, "clk_uart1_frac", "clk_uart1_src", CLK_SET_RATE_PARENT, 1210 RK3568_CLKSEL_CON(53), 0, 1211 RK3568_CLKGATE_CON(27), 14, GFLAGS, 1212 &rk3568_uart1_fracmux), 1213 GATE(SCLK_UART1, "sclk_uart1", "sclk_uart1_mux", 0, 1214 RK3568_CLKGATE_CON(27), 15, GFLAGS), 1215 1216 GATE(PCLK_UART2, "pclk_uart2", "pclk_bus", 0, 1217 RK3568_CLKGATE_CON(28), 0, GFLAGS), 1218 COMPOSITE(CLK_UART2_SRC, "clk_uart2_src", gpll_cpll_usb480m_p, 0, 1219 RK3568_CLKSEL_CON(54), 8, 2, MFLAGS, 0, 7, DFLAGS, 1220 RK3568_CLKGATE_CON(28), 1, GFLAGS), 1221 COMPOSITE_FRACMUX(CLK_UART2_FRAC, "clk_uart2_frac", "clk_uart2_src", CLK_SET_RATE_PARENT, 1222 RK3568_CLKSEL_CON(55), 0, 1223 RK3568_CLKGATE_CON(28), 2, GFLAGS, 1224 &rk3568_uart2_fracmux), 1225 GATE(SCLK_UART2, "sclk_uart2", "sclk_uart2_mux", 0, 1226 RK3568_CLKGATE_CON(28), 3, GFLAGS), 1227 1228 GATE(PCLK_UART3, "pclk_uart3", "pclk_bus", 0, 1229 RK3568_CLKGATE_CON(28), 4, GFLAGS), 1230 COMPOSITE(CLK_UART3_SRC, "clk_uart3_src", gpll_cpll_usb480m_p, 0, 1231 RK3568_CLKSEL_CON(56), 8, 2, MFLAGS, 0, 7, DFLAGS, 1232 RK3568_CLKGATE_CON(28), 5, GFLAGS), 1233 COMPOSITE_FRACMUX(CLK_UART3_FRAC, "clk_uart3_frac", "clk_uart3_src", CLK_SET_RATE_PARENT, 1234 RK3568_CLKSEL_CON(57), 0, 1235 RK3568_CLKGATE_CON(28), 6, GFLAGS, 1236 &rk3568_uart3_fracmux), 1237 GATE(SCLK_UART3, "sclk_uart3", "sclk_uart3_mux", 0, 1238 RK3568_CLKGATE_CON(28), 7, GFLAGS), 1239 1240 GATE(PCLK_UART4, "pclk_uart4", "pclk_bus", 0, 1241 RK3568_CLKGATE_CON(28), 8, GFLAGS), 1242 COMPOSITE(CLK_UART4_SRC, "clk_uart4_src", gpll_cpll_usb480m_p, 0, 1243 RK3568_CLKSEL_CON(58), 8, 2, MFLAGS, 0, 7, DFLAGS, 1244 RK3568_CLKGATE_CON(28), 9, GFLAGS), 1245 COMPOSITE_FRACMUX(CLK_UART4_FRAC, "clk_uart4_frac", "clk_uart4_src", CLK_SET_RATE_PARENT, 1246 RK3568_CLKSEL_CON(59), 0, 1247 RK3568_CLKGATE_CON(28), 10, GFLAGS, 1248 &rk3568_uart4_fracmux), 1249 GATE(SCLK_UART4, "sclk_uart4", "sclk_uart4_mux", 0, 1250 RK3568_CLKGATE_CON(28), 11, GFLAGS), 1251 1252 GATE(PCLK_UART5, "pclk_uart5", "pclk_bus", 0, 1253 RK3568_CLKGATE_CON(28), 12, GFLAGS), 1254 COMPOSITE(CLK_UART5_SRC, "clk_uart5_src", gpll_cpll_usb480m_p, 0, 1255 RK3568_CLKSEL_CON(60), 8, 2, MFLAGS, 0, 7, DFLAGS, 1256 RK3568_CLKGATE_CON(28), 13, GFLAGS), 1257 COMPOSITE_FRACMUX(CLK_UART5_FRAC, "clk_uart5_frac", "clk_uart5_src", CLK_SET_RATE_PARENT, 1258 RK3568_CLKSEL_CON(61), 0, 1259 RK3568_CLKGATE_CON(28), 14, GFLAGS, 1260 &rk3568_uart5_fracmux), 1261 GATE(SCLK_UART5, "sclk_uart5", "sclk_uart5_mux", 0, 1262 RK3568_CLKGATE_CON(28), 15, GFLAGS), 1263 1264 GATE(PCLK_UART6, "pclk_uart6", "pclk_bus", 0, 1265 RK3568_CLKGATE_CON(29), 0, GFLAGS), 1266 COMPOSITE(CLK_UART6_SRC, "clk_uart6_src", gpll_cpll_usb480m_p, 0, 1267 RK3568_CLKSEL_CON(62), 8, 2, MFLAGS, 0, 7, DFLAGS, 1268 RK3568_CLKGATE_CON(29), 1, GFLAGS), 1269 COMPOSITE_FRACMUX(CLK_UART6_FRAC, "clk_uart6_frac", "clk_uart6_src", CLK_SET_RATE_PARENT, 1270 RK3568_CLKSEL_CON(63), 0, 1271 RK3568_CLKGATE_CON(29), 2, GFLAGS, 1272 &rk3568_uart6_fracmux), 1273 GATE(SCLK_UART6, "sclk_uart6", "sclk_uart6_mux", 0, 1274 RK3568_CLKGATE_CON(29), 3, GFLAGS), 1275 1276 GATE(PCLK_UART7, "pclk_uart7", "pclk_bus", 0, 1277 RK3568_CLKGATE_CON(29), 4, GFLAGS), 1278 COMPOSITE(CLK_UART7_SRC, "clk_uart7_src", gpll_cpll_usb480m_p, 0, 1279 RK3568_CLKSEL_CON(64), 8, 2, MFLAGS, 0, 7, DFLAGS, 1280 RK3568_CLKGATE_CON(29), 5, GFLAGS), 1281 COMPOSITE_FRACMUX(CLK_UART7_FRAC, "clk_uart7_frac", "clk_uart7_src", CLK_SET_RATE_PARENT, 1282 RK3568_CLKSEL_CON(65), 0, 1283 RK3568_CLKGATE_CON(29), 6, GFLAGS, 1284 &rk3568_uart7_fracmux), 1285 GATE(SCLK_UART7, "sclk_uart7", "sclk_uart7_mux", 0, 1286 RK3568_CLKGATE_CON(29), 7, GFLAGS), 1287 1288 GATE(PCLK_UART8, "pclk_uart8", "pclk_bus", 0, 1289 RK3568_CLKGATE_CON(29), 8, GFLAGS), 1290 COMPOSITE(CLK_UART8_SRC, "clk_uart8_src", gpll_cpll_usb480m_p, 0, 1291 RK3568_CLKSEL_CON(66), 8, 2, MFLAGS, 0, 7, DFLAGS, 1292 RK3568_CLKGATE_CON(29), 9, GFLAGS), 1293 COMPOSITE_FRACMUX(CLK_UART8_FRAC, "clk_uart8_frac", "clk_uart8_src", CLK_SET_RATE_PARENT, 1294 RK3568_CLKSEL_CON(67), 0, 1295 RK3568_CLKGATE_CON(29), 10, GFLAGS, 1296 &rk3568_uart8_fracmux), 1297 GATE(SCLK_UART8, "sclk_uart8", "sclk_uart8_mux", 0, 1298 RK3568_CLKGATE_CON(29), 11, GFLAGS), 1299 1300 GATE(PCLK_UART9, "pclk_uart9", "pclk_bus", 0, 1301 RK3568_CLKGATE_CON(29), 12, GFLAGS), 1302 COMPOSITE(CLK_UART9_SRC, "clk_uart9_src", gpll_cpll_usb480m_p, 0, 1303 RK3568_CLKSEL_CON(68), 8, 2, MFLAGS, 0, 7, DFLAGS, 1304 RK3568_CLKGATE_CON(29), 13, GFLAGS), 1305 COMPOSITE_FRACMUX(CLK_UART9_FRAC, "clk_uart9_frac", "clk_uart9_src", CLK_SET_RATE_PARENT, 1306 RK3568_CLKSEL_CON(69), 0, 1307 RK3568_CLKGATE_CON(29), 14, GFLAGS, 1308 &rk3568_uart9_fracmux), 1309 GATE(SCLK_UART9, "sclk_uart9", "sclk_uart9_mux", 0, 1310 RK3568_CLKGATE_CON(29), 15, GFLAGS), 1311 1312 GATE(PCLK_CAN0, "pclk_can0", "pclk_bus", 0, 1313 RK3568_CLKGATE_CON(27), 5, GFLAGS), 1314 COMPOSITE(CLK_CAN0, "clk_can0", gpll_cpll_p, 0, 1315 RK3568_CLKSEL_CON(70), 7, 1, MFLAGS, 0, 5, DFLAGS, 1316 RK3568_CLKGATE_CON(27), 6, GFLAGS), 1317 GATE(PCLK_CAN1, "pclk_can1", "pclk_bus", 0, 1318 RK3568_CLKGATE_CON(27), 7, GFLAGS), 1319 COMPOSITE(CLK_CAN1, "clk_can1", gpll_cpll_p, 0, 1320 RK3568_CLKSEL_CON(70), 15, 1, MFLAGS, 8, 5, DFLAGS, 1321 RK3568_CLKGATE_CON(27), 8, GFLAGS), 1322 GATE(PCLK_CAN2, "pclk_can2", "pclk_bus", 0, 1323 RK3568_CLKGATE_CON(27), 9, GFLAGS), 1324 COMPOSITE(CLK_CAN2, "clk_can2", gpll_cpll_p, 0, 1325 RK3568_CLKSEL_CON(71), 7, 1, MFLAGS, 0, 5, DFLAGS, 1326 RK3568_CLKGATE_CON(27), 10, GFLAGS), 1327 COMPOSITE_NODIV(CLK_I2C, "clk_i2c", clk_i2c_p, 0, 1328 RK3568_CLKSEL_CON(71), 8, 2, MFLAGS, 1329 RK3568_CLKGATE_CON(32), 10, GFLAGS), 1330 GATE(PCLK_I2C1, "pclk_i2c1", "pclk_bus", 0, 1331 RK3568_CLKGATE_CON(30), 0, GFLAGS), 1332 GATE(CLK_I2C1, "clk_i2c1", "clk_i2c", 0, 1333 RK3568_CLKGATE_CON(30), 1, GFLAGS), 1334 GATE(PCLK_I2C2, "pclk_i2c2", "pclk_bus", 0, 1335 RK3568_CLKGATE_CON(30), 2, GFLAGS), 1336 GATE(CLK_I2C2, "clk_i2c2", "clk_i2c", 0, 1337 RK3568_CLKGATE_CON(30), 3, GFLAGS), 1338 GATE(PCLK_I2C3, "pclk_i2c3", "pclk_bus", 0, 1339 RK3568_CLKGATE_CON(30), 4, GFLAGS), 1340 GATE(CLK_I2C3, "clk_i2c3", "clk_i2c", 0, 1341 RK3568_CLKGATE_CON(30), 5, GFLAGS), 1342 GATE(PCLK_I2C4, "pclk_i2c4", "pclk_bus", 0, 1343 RK3568_CLKGATE_CON(30), 6, GFLAGS), 1344 GATE(CLK_I2C4, "clk_i2c4", "clk_i2c", 0, 1345 RK3568_CLKGATE_CON(30), 7, GFLAGS), 1346 GATE(PCLK_I2C5, "pclk_i2c5", "pclk_bus", 0, 1347 RK3568_CLKGATE_CON(30), 8, GFLAGS), 1348 GATE(CLK_I2C5, "clk_i2c5", "clk_i2c", 0, 1349 RK3568_CLKGATE_CON(30), 9, GFLAGS), 1350 GATE(PCLK_SPI0, "pclk_spi0", "pclk_bus", 0, 1351 RK3568_CLKGATE_CON(30), 10, GFLAGS), 1352 COMPOSITE_NODIV(CLK_SPI0, "clk_spi0", gpll200_xin24m_cpll100_p, 0, 1353 RK3568_CLKSEL_CON(72), 0, 1, MFLAGS, 1354 RK3568_CLKGATE_CON(30), 11, GFLAGS), 1355 GATE(PCLK_SPI1, "pclk_spi1", "pclk_bus", 0, 1356 RK3568_CLKGATE_CON(30), 12, GFLAGS), 1357 COMPOSITE_NODIV(CLK_SPI1, "clk_spi1", gpll200_xin24m_cpll100_p, 0, 1358 RK3568_CLKSEL_CON(72), 2, 1, MFLAGS, 1359 RK3568_CLKGATE_CON(30), 13, GFLAGS), 1360 GATE(PCLK_SPI2, "pclk_spi2", "pclk_bus", 0, 1361 RK3568_CLKGATE_CON(30), 14, GFLAGS), 1362 COMPOSITE_NODIV(CLK_SPI2, "clk_spi2", gpll200_xin24m_cpll100_p, 0, 1363 RK3568_CLKSEL_CON(72), 4, 1, MFLAGS, 1364 RK3568_CLKGATE_CON(30), 15, GFLAGS), 1365 GATE(PCLK_SPI3, "pclk_spi3", "pclk_bus", 0, 1366 RK3568_CLKGATE_CON(31), 0, GFLAGS), 1367 COMPOSITE_NODIV(CLK_SPI3, "clk_spi3", gpll200_xin24m_cpll100_p, 0, 1368 RK3568_CLKSEL_CON(72), 6, 1, MFLAGS, RK3568_CLKGATE_CON(31), 1, GFLAGS), 1369 GATE(PCLK_PWM1, "pclk_pwm1", "pclk_bus", 0, RK3568_CLKGATE_CON(31), 10, GFLAGS), 1370 COMPOSITE_NODIV(CLK_PWM1, "clk_pwm1", gpll100_xin24m_cpll100_p, 0, 1371 RK3568_CLKSEL_CON(72), 8, 1, MFLAGS, 1372 RK3568_CLKGATE_CON(31), 11, GFLAGS), 1373 GATE(CLK_PWM1_CAPTURE, "clk_pwm1_capture", "xin24m", 0, 1374 RK3568_CLKGATE_CON(31), 12, GFLAGS), 1375 GATE(PCLK_PWM2, "pclk_pwm2", "pclk_bus", 0, 1376 RK3568_CLKGATE_CON(31), 13, GFLAGS), 1377 COMPOSITE_NODIV(CLK_PWM2, "clk_pwm2", gpll100_xin24m_cpll100_p, 0, 1378 RK3568_CLKSEL_CON(72), 10, 1, MFLAGS, 1379 RK3568_CLKGATE_CON(31), 14, GFLAGS), 1380 GATE(CLK_PWM2_CAPTURE, "clk_pwm2_capture", "xin24m", 0, 1381 RK3568_CLKGATE_CON(31), 15, GFLAGS), 1382 GATE(PCLK_PWM3, "pclk_pwm3", "pclk_bus", 0, 1383 RK3568_CLKGATE_CON(32), 0, GFLAGS), 1384 COMPOSITE_NODIV(CLK_PWM3, "clk_pwm3", gpll100_xin24m_cpll100_p, 0, 1385 RK3568_CLKSEL_CON(72), 12, 1, MFLAGS, 1386 RK3568_CLKGATE_CON(32), 1, GFLAGS), 1387 GATE(CLK_PWM3_CAPTURE, "clk_pwm3_capture", "xin24m", 0, 1388 RK3568_CLKGATE_CON(32), 2, GFLAGS), 1389 COMPOSITE_NODIV(DBCLK_GPIO, "dbclk_gpio", xin24m_32k_p, 0, 1390 RK3568_CLKSEL_CON(72), 14, 1, MFLAGS, 1391 RK3568_CLKGATE_CON(32), 11, GFLAGS), 1392 GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_bus", 0, 1393 RK3568_CLKGATE_CON(31), 2, GFLAGS), 1394 GATE(DBCLK_GPIO1, "dbclk_gpio1", "dbclk_gpio", 0, 1395 RK3568_CLKGATE_CON(31), 3, GFLAGS), 1396 GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_bus", 0, 1397 RK3568_CLKGATE_CON(31), 4, GFLAGS), 1398 GATE(DBCLK_GPIO2, "dbclk_gpio2", "dbclk_gpio", 0, 1399 RK3568_CLKGATE_CON(31), 5, GFLAGS), 1400 GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_bus", 0, 1401 RK3568_CLKGATE_CON(31), 6, GFLAGS), 1402 GATE(DBCLK_GPIO3, "dbclk_gpio3", "dbclk_gpio", 0, 1403 RK3568_CLKGATE_CON(31), 7, GFLAGS), 1404 GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_bus", 0, 1405 RK3568_CLKGATE_CON(31), 8, GFLAGS), 1406 GATE(DBCLK_GPIO4, "dbclk_gpio4", "dbclk_gpio", 0, 1407 RK3568_CLKGATE_CON(31), 9, GFLAGS), 1408 GATE(PCLK_TIMER, "pclk_timer", "pclk_bus", 0, 1409 RK3568_CLKGATE_CON(32), 3, GFLAGS), 1410 GATE(CLK_TIMER0, "clk_timer0", "xin24m", 0, 1411 RK3568_CLKGATE_CON(32), 4, GFLAGS), 1412 GATE(CLK_TIMER1, "clk_timer1", "xin24m", 0, 1413 RK3568_CLKGATE_CON(32), 5, GFLAGS), 1414 GATE(CLK_TIMER2, "clk_timer2", "xin24m", 0, 1415 RK3568_CLKGATE_CON(32), 6, GFLAGS), 1416 GATE(CLK_TIMER3, "clk_timer3", "xin24m", 0, 1417 RK3568_CLKGATE_CON(32), 7, GFLAGS), 1418 GATE(CLK_TIMER4, "clk_timer4", "xin24m", 0, 1419 RK3568_CLKGATE_CON(32), 8, GFLAGS), 1420 GATE(CLK_TIMER5, "clk_timer5", "xin24m", 0, 1421 RK3568_CLKGATE_CON(32), 9, GFLAGS), 1422 1423 /* PD_TOP */ 1424 COMPOSITE_NODIV(ACLK_TOP_HIGH, "aclk_top_high", cpll500_gpll400_gpll300_xin24m_p, 0, 1425 RK3568_CLKSEL_CON(73), 0, 2, MFLAGS, 1426 RK3568_CLKGATE_CON(33), 0, GFLAGS), 1427 COMPOSITE_NODIV(ACLK_TOP_LOW, "aclk_top_low", gpll400_gpll300_gpll200_xin24m_p, 0, 1428 RK3568_CLKSEL_CON(73), 4, 2, MFLAGS, 1429 RK3568_CLKGATE_CON(33), 1, GFLAGS), 1430 COMPOSITE_NODIV(HCLK_TOP, "hclk_top", gpll150_gpll100_gpll75_xin24m_p, 0, 1431 RK3568_CLKSEL_CON(73), 8, 2, MFLAGS, 1432 RK3568_CLKGATE_CON(33), 2, GFLAGS), 1433 COMPOSITE_NODIV(PCLK_TOP, "pclk_top", gpll100_gpll75_cpll50_xin24m_p, 0, 1434 RK3568_CLKSEL_CON(73), 12, 2, MFLAGS, 1435 RK3568_CLKGATE_CON(33), 3, GFLAGS), 1436 GATE(PCLK_PCIE30PHY, "pclk_pcie30phy", "pclk_top", 0, 1437 RK3568_CLKGATE_CON(33), 8, GFLAGS), 1438 COMPOSITE_NODIV(CLK_OPTC_ARB, "clk_optc_arb", xin24m_cpll100_p, 0, 1439 RK3568_CLKSEL_CON(73), 15, 1, MFLAGS, 1440 RK3568_CLKGATE_CON(33), 9, GFLAGS), 1441 GATE(PCLK_MIPICSIPHY, "pclk_mipicsiphy", "pclk_top", 0, 1442 RK3568_CLKGATE_CON(33), 13, GFLAGS), 1443 GATE(PCLK_MIPIDSIPHY0, "pclk_mipidsiphy0", "pclk_top", 0, 1444 RK3568_CLKGATE_CON(33), 14, GFLAGS), 1445 GATE(PCLK_MIPIDSIPHY1, "pclk_mipidsiphy1", "pclk_top", 0, 1446 RK3568_CLKGATE_CON(33), 15, GFLAGS), 1447 GATE(PCLK_PIPEPHY0, "pclk_pipephy0", "pclk_top", 0, 1448 RK3568_CLKGATE_CON(34), 4, GFLAGS), 1449 GATE(PCLK_PIPEPHY1, "pclk_pipephy1", "pclk_top", 0, 1450 RK3568_CLKGATE_CON(34), 5, GFLAGS), 1451 GATE(PCLK_PIPEPHY2, "pclk_pipephy2", "pclk_top", 0, 1452 RK3568_CLKGATE_CON(34), 6, GFLAGS), 1453 GATE(PCLK_CPU_BOOST, "pclk_cpu_boost", "pclk_top", 0, 1454 RK3568_CLKGATE_CON(34), 11, GFLAGS), 1455 GATE(CLK_CPU_BOOST, "clk_cpu_boost", "xin24m", 0, 1456 RK3568_CLKGATE_CON(34), 12, GFLAGS), 1457 GATE(PCLK_OTPPHY, "pclk_otpphy", "pclk_top", 0, 1458 RK3568_CLKGATE_CON(34), 13, GFLAGS), 1459 GATE(PCLK_EDPPHY_GRF, "pclk_edpphy_grf", "pclk_top", 0, 1460 RK3568_CLKGATE_CON(34), 14, GFLAGS), 1461 }; 1462 1463 static struct rockchip_clk_branch rk3568_clk_pmu_branches[] __initdata = { 1464 /* PD_PMU */ 1465 FACTOR(0, "ppll_ph0", "ppll", 0, 1, 2), 1466 FACTOR(0, "ppll_ph180", "ppll", 0, 1, 2), 1467 FACTOR(0, "hpll_ph0", "hpll", 0, 1, 2), 1468 1469 MUX(CLK_PDPMU, "clk_pdpmu", clk_pdpmu_p, 0, 1470 RK3568_PMU_CLKSEL_CON(2), 15, 1, MFLAGS), 1471 COMPOSITE_NOMUX(PCLK_PDPMU, "pclk_pdpmu", "clk_pdpmu", 0, 1472 RK3568_PMU_CLKSEL_CON(2), 0, 5, DFLAGS, 1473 RK3568_PMU_CLKGATE_CON(0), 2, GFLAGS), 1474 GATE(PCLK_PMU, "pclk_pmu", "pclk_pdpmu", 0, 1475 RK3568_PMU_CLKGATE_CON(0), 6, GFLAGS), 1476 GATE(CLK_PMU, "clk_pmu", "xin24m", 0, 1477 RK3568_PMU_CLKGATE_CON(0), 7, GFLAGS), 1478 GATE(PCLK_I2C0, "pclk_i2c0", "pclk_pdpmu", 0, 1479 RK3568_PMU_CLKGATE_CON(1), 0, GFLAGS), 1480 COMPOSITE_NOMUX(CLK_I2C0, "clk_i2c0", "clk_pdpmu", 0, 1481 RK3568_PMU_CLKSEL_CON(3), 0, 7, DFLAGS, 1482 RK3568_PMU_CLKGATE_CON(1), 1, GFLAGS), 1483 GATE(PCLK_UART0, "pclk_uart0", "pclk_pdpmu", 0, 1484 RK3568_PMU_CLKGATE_CON(1), 2, GFLAGS), 1485 1486 COMPOSITE_FRACMUX(CLK_RTC32K_FRAC, "clk_rtc32k_frac", "xin24m", CLK_IGNORE_UNUSED, 1487 RK3568_PMU_CLKSEL_CON(1), 0, 1488 RK3568_PMU_CLKGATE_CON(0), 1, GFLAGS, 1489 &rk3568_rtc32k_pmu_fracmux), 1490 1491 COMPOSITE_NOMUX(XIN_OSC0_DIV, "xin_osc0_div", "xin24m", CLK_IGNORE_UNUSED, 1492 RK3568_PMU_CLKSEL_CON(0), 0, 5, DFLAGS, 1493 RK3568_PMU_CLKGATE_CON(0), 0, GFLAGS), 1494 1495 COMPOSITE(CLK_UART0_DIV, "sclk_uart0_div", ppll_usb480m_cpll_gpll_p, 0, 1496 RK3568_PMU_CLKSEL_CON(4), 8, 2, MFLAGS, 0, 7, DFLAGS, 1497 RK3568_PMU_CLKGATE_CON(1), 3, GFLAGS), 1498 COMPOSITE_FRACMUX(CLK_UART0_FRAC, "sclk_uart0_frac", "sclk_uart0_div", CLK_SET_RATE_PARENT, 1499 RK3568_PMU_CLKSEL_CON(5), 0, 1500 RK3568_PMU_CLKGATE_CON(1), 4, GFLAGS, 1501 &rk3568_uart0_fracmux), 1502 GATE(SCLK_UART0, "sclk_uart0", "sclk_uart0_mux", 0, 1503 RK3568_PMU_CLKGATE_CON(1), 5, GFLAGS), 1504 1505 GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_pdpmu", 0, 1506 RK3568_PMU_CLKGATE_CON(1), 9, GFLAGS), 1507 COMPOSITE_NODIV(DBCLK_GPIO0, "dbclk_gpio0", xin24m_32k_p, 0, 1508 RK3568_PMU_CLKSEL_CON(6), 15, 1, MFLAGS, 1509 RK3568_PMU_CLKGATE_CON(1), 10, GFLAGS), 1510 GATE(PCLK_PWM0, "pclk_pwm0", "pclk_pdpmu", 0, 1511 RK3568_PMU_CLKGATE_CON(1), 6, GFLAGS), 1512 COMPOSITE(CLK_PWM0, "clk_pwm0", clk_pwm0_p, 0, 1513 RK3568_PMU_CLKSEL_CON(6), 7, 1, MFLAGS, 0, 7, DFLAGS, 1514 RK3568_PMU_CLKGATE_CON(1), 7, GFLAGS), 1515 GATE(CLK_CAPTURE_PWM0_NDFT, "clk_capture_pwm0_ndft", "xin24m", 0, 1516 RK3568_PMU_CLKGATE_CON(1), 8, GFLAGS), 1517 GATE(PCLK_PMUPVTM, "pclk_pmupvtm", "pclk_pdpmu", 0, 1518 RK3568_PMU_CLKGATE_CON(1), 11, GFLAGS), 1519 GATE(CLK_PMUPVTM, "clk_pmupvtm", "xin24m", 0, 1520 RK3568_PMU_CLKGATE_CON(1), 12, GFLAGS), 1521 GATE(CLK_CORE_PMUPVTM, "clk_core_pmupvtm", "xin24m", 0, 1522 RK3568_PMU_CLKGATE_CON(1), 13, GFLAGS), 1523 COMPOSITE_NOMUX(CLK_REF24M, "clk_ref24m", "clk_pdpmu", 0, 1524 RK3568_PMU_CLKSEL_CON(7), 0, 6, DFLAGS, 1525 RK3568_PMU_CLKGATE_CON(2), 0, GFLAGS), 1526 GATE(XIN_OSC0_USBPHY0_G, "xin_osc0_usbphy0_g", "xin24m", 0, 1527 RK3568_PMU_CLKGATE_CON(2), 1, GFLAGS), 1528 MUX(CLK_USBPHY0_REF, "clk_usbphy0_ref", clk_usbphy0_ref_p, 0, 1529 RK3568_PMU_CLKSEL_CON(8), 0, 1, MFLAGS), 1530 GATE(XIN_OSC0_USBPHY1_G, "xin_osc0_usbphy1_g", "xin24m", 0, 1531 RK3568_PMU_CLKGATE_CON(2), 2, GFLAGS), 1532 MUX(CLK_USBPHY1_REF, "clk_usbphy1_ref", clk_usbphy1_ref_p, 0, 1533 RK3568_PMU_CLKSEL_CON(8), 1, 1, MFLAGS), 1534 GATE(XIN_OSC0_MIPIDSIPHY0_G, "xin_osc0_mipidsiphy0_g", "xin24m", 0, 1535 RK3568_PMU_CLKGATE_CON(2), 3, GFLAGS), 1536 MUX(CLK_MIPIDSIPHY0_REF, "clk_mipidsiphy0_ref", clk_mipidsiphy0_ref_p, 0, 1537 RK3568_PMU_CLKSEL_CON(8), 2, 1, MFLAGS), 1538 GATE(XIN_OSC0_MIPIDSIPHY1_G, "xin_osc0_mipidsiphy1_g", "xin24m", 0, 1539 RK3568_PMU_CLKGATE_CON(2), 4, GFLAGS), 1540 MUX(CLK_MIPIDSIPHY1_REF, "clk_mipidsiphy1_ref", clk_mipidsiphy1_ref_p, 0, 1541 RK3568_PMU_CLKSEL_CON(8), 3, 1, MFLAGS), 1542 COMPOSITE_NOMUX(CLK_WIFI_DIV, "clk_wifi_div", "clk_pdpmu", 0, 1543 RK3568_PMU_CLKSEL_CON(8), 8, 6, DFLAGS, 1544 RK3568_PMU_CLKGATE_CON(2), 5, GFLAGS), 1545 GATE(CLK_WIFI_OSC0, "clk_wifi_osc0", "xin24m", 0, 1546 RK3568_PMU_CLKGATE_CON(2), 6, GFLAGS), 1547 MUX(CLK_WIFI, "clk_wifi", clk_wifi_p, CLK_SET_RATE_PARENT, 1548 RK3568_PMU_CLKSEL_CON(8), 15, 1, MFLAGS), 1549 COMPOSITE_NOMUX(CLK_PCIEPHY0_DIV, "clk_pciephy0_div", "ppll_ph0", 0, 1550 RK3568_PMU_CLKSEL_CON(9), 0, 3, DFLAGS, 1551 RK3568_PMU_CLKGATE_CON(2), 7, GFLAGS), 1552 GATE(CLK_PCIEPHY0_OSC0, "clk_pciephy0_osc0", "xin24m", 0, 1553 RK3568_PMU_CLKGATE_CON(2), 8, GFLAGS), 1554 MUX(CLK_PCIEPHY0_REF, "clk_pciephy0_ref", clk_pciephy0_ref_p, CLK_SET_RATE_PARENT, 1555 RK3568_PMU_CLKSEL_CON(9), 3, 1, MFLAGS), 1556 COMPOSITE_NOMUX(CLK_PCIEPHY1_DIV, "clk_pciephy1_div", "ppll_ph0", 0, 1557 RK3568_PMU_CLKSEL_CON(9), 4, 3, DFLAGS, 1558 RK3568_PMU_CLKGATE_CON(2), 9, GFLAGS), 1559 GATE(CLK_PCIEPHY1_OSC0, "clk_pciephy1_osc0", "xin24m", 0, 1560 RK3568_PMU_CLKGATE_CON(2), 10, GFLAGS), 1561 MUX(CLK_PCIEPHY1_REF, "clk_pciephy1_ref", clk_pciephy1_ref_p, CLK_SET_RATE_PARENT, 1562 RK3568_PMU_CLKSEL_CON(9), 7, 1, MFLAGS), 1563 COMPOSITE_NOMUX(CLK_PCIEPHY2_DIV, "clk_pciephy2_div", "ppll_ph0", 0, 1564 RK3568_PMU_CLKSEL_CON(9), 8, 3, DFLAGS, 1565 RK3568_PMU_CLKGATE_CON(2), 11, GFLAGS), 1566 GATE(CLK_PCIEPHY2_OSC0, "clk_pciephy2_osc0", "xin24m", 0, 1567 RK3568_PMU_CLKGATE_CON(2), 12, GFLAGS), 1568 MUX(CLK_PCIEPHY2_REF, "clk_pciephy2_ref", clk_pciephy2_ref_p, CLK_SET_RATE_PARENT, 1569 RK3568_PMU_CLKSEL_CON(9), 11, 1, MFLAGS), 1570 GATE(CLK_PCIE30PHY_REF_M, "clk_pcie30phy_ref_m", "ppll_ph0", 0, 1571 RK3568_PMU_CLKGATE_CON(2), 13, GFLAGS), 1572 GATE(CLK_PCIE30PHY_REF_N, "clk_pcie30phy_ref_n", "ppll_ph180", 0, 1573 RK3568_PMU_CLKGATE_CON(2), 14, GFLAGS), 1574 GATE(XIN_OSC0_EDPPHY_G, "xin_osc0_edpphy_g", "xin24m", 0, 1575 RK3568_PMU_CLKGATE_CON(2), 15, GFLAGS), 1576 MUX(CLK_HDMI_REF, "clk_hdmi_ref", clk_hdmi_ref_p, CLK_SET_RATE_PARENT, 1577 RK3568_PMU_CLKSEL_CON(8), 7, 1, MFLAGS), 1578 }; 1579 1580 static const char *const rk3568_cru_critical_clocks[] __initconst = { 1581 "armclk", 1582 "pclk_core_pre", 1583 "aclk_bus", 1584 "pclk_bus", 1585 "aclk_top_high", 1586 "aclk_top_low", 1587 "hclk_top", 1588 "pclk_top", 1589 "aclk_perimid", 1590 "hclk_perimid", 1591 "aclk_secure_flash", 1592 "hclk_secure_flash", 1593 "aclk_core_niu2bus", 1594 "npll", 1595 "clk_optc_arb", 1596 "hclk_php", 1597 "pclk_php", 1598 "hclk_usb", 1599 "pclk_usb", 1600 "hclk_vo", 1601 }; 1602 1603 static const char *const rk3568_pmucru_critical_clocks[] __initconst = { 1604 "pclk_pdpmu", 1605 "pclk_pmu", 1606 "clk_pmu", 1607 }; 1608 1609 static void __init rk3568_pmu_clk_init(struct device_node *np) 1610 { 1611 struct rockchip_clk_provider *ctx; 1612 void __iomem *reg_base; 1613 1614 reg_base = of_iomap(np, 0); 1615 if (!reg_base) { 1616 pr_err("%s: could not map cru pmu region\n", __func__); 1617 return; 1618 } 1619 1620 ctx = rockchip_clk_init(np, reg_base, CLKPMU_NR_CLKS); 1621 if (IS_ERR(ctx)) { 1622 pr_err("%s: rockchip pmu clk init failed\n", __func__); 1623 return; 1624 } 1625 1626 rockchip_clk_register_plls(ctx, rk3568_pmu_pll_clks, 1627 ARRAY_SIZE(rk3568_pmu_pll_clks), 1628 RK3568_GRF_SOC_STATUS0); 1629 1630 rockchip_clk_register_branches(ctx, rk3568_clk_pmu_branches, 1631 ARRAY_SIZE(rk3568_clk_pmu_branches)); 1632 1633 rockchip_register_softrst(np, 1, reg_base + RK3568_PMU_SOFTRST_CON(0), 1634 ROCKCHIP_SOFTRST_HIWORD_MASK); 1635 1636 rockchip_clk_protect_critical(rk3568_pmucru_critical_clocks, 1637 ARRAY_SIZE(rk3568_pmucru_critical_clocks)); 1638 1639 rockchip_clk_of_add_provider(np, ctx); 1640 } 1641 1642 CLK_OF_DECLARE(rk3568_cru_pmu, "rockchip,rk3568-pmucru", rk3568_pmu_clk_init); 1643 1644 static void __init rk3568_clk_init(struct device_node *np) 1645 { 1646 struct rockchip_clk_provider *ctx; 1647 void __iomem *reg_base; 1648 1649 reg_base = of_iomap(np, 0); 1650 if (!reg_base) { 1651 pr_err("%s: could not map cru region\n", __func__); 1652 return; 1653 } 1654 1655 ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS); 1656 if (IS_ERR(ctx)) { 1657 pr_err("%s: rockchip clk init failed\n", __func__); 1658 iounmap(reg_base); 1659 return; 1660 } 1661 1662 rockchip_clk_register_plls(ctx, rk3568_pll_clks, 1663 ARRAY_SIZE(rk3568_pll_clks), 1664 RK3568_GRF_SOC_STATUS0); 1665 1666 rockchip_clk_register_armclk(ctx, ARMCLK, "armclk", 1667 mux_armclk_p, ARRAY_SIZE(mux_armclk_p), 1668 &rk3568_cpuclk_data, rk3568_cpuclk_rates, 1669 ARRAY_SIZE(rk3568_cpuclk_rates)); 1670 1671 rockchip_clk_register_branches(ctx, rk3568_clk_branches, 1672 ARRAY_SIZE(rk3568_clk_branches)); 1673 1674 rockchip_register_softrst(np, 30, reg_base + RK3568_SOFTRST_CON(0), 1675 ROCKCHIP_SOFTRST_HIWORD_MASK); 1676 1677 rockchip_register_restart_notifier(ctx, RK3568_GLB_SRST_FST, NULL); 1678 1679 rockchip_clk_protect_critical(rk3568_cru_critical_clocks, 1680 ARRAY_SIZE(rk3568_cru_critical_clocks)); 1681 1682 rockchip_clk_of_add_provider(np, ctx); 1683 } 1684 1685 CLK_OF_DECLARE(rk3568_cru, "rockchip,rk3568-cru", rk3568_clk_init); 1686 1687 struct clk_rk3568_inits { 1688 void (*inits)(struct device_node *np); 1689 }; 1690 1691 static const struct clk_rk3568_inits clk_rk3568_pmucru_init = { 1692 .inits = rk3568_pmu_clk_init, 1693 }; 1694 1695 static const struct clk_rk3568_inits clk_3568_cru_init = { 1696 .inits = rk3568_clk_init, 1697 }; 1698 1699 static const struct of_device_id clk_rk3568_match_table[] = { 1700 { 1701 .compatible = "rockchip,rk3568-cru", 1702 .data = &clk_3568_cru_init, 1703 }, { 1704 .compatible = "rockchip,rk3568-pmucru", 1705 .data = &clk_rk3568_pmucru_init, 1706 }, 1707 { } 1708 }; 1709 1710 static int __init clk_rk3568_probe(struct platform_device *pdev) 1711 { 1712 struct device_node *np = pdev->dev.of_node; 1713 const struct clk_rk3568_inits *init_data; 1714 1715 init_data = (struct clk_rk3568_inits *)of_device_get_match_data(&pdev->dev); 1716 if (!init_data) 1717 return -EINVAL; 1718 1719 if (init_data->inits) 1720 init_data->inits(np); 1721 1722 return 0; 1723 } 1724 1725 static struct platform_driver clk_rk3568_driver = { 1726 .driver = { 1727 .name = "clk-rk3568", 1728 .of_match_table = clk_rk3568_match_table, 1729 .suppress_bind_attrs = true, 1730 }, 1731 }; 1732 builtin_platform_driver_probe(clk_rk3568_driver, clk_rk3568_probe); 1733