xref: /linux/drivers/clk/renesas/r9a09g047-cpg.c (revision 746680ec6696585e30db3e18c93a63df9cbec39c)
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Renesas RZ/G3E CPG driver
4  *
5  * Copyright (C) 2024 Renesas Electronics Corp.
6  */
7 
8 #include <linux/clk-provider.h>
9 #include <linux/device.h>
10 #include <linux/init.h>
11 #include <linux/kernel.h>
12 
13 #include <dt-bindings/clock/renesas,r9a09g047-cpg.h>
14 
15 #include "rzv2h-cpg.h"
16 
17 enum clk_ids {
18 	/* Core Clock Outputs exported to DT */
19 	LAST_DT_CORE_CLK = R9A09G047_GBETH_1_CLK_PTP_REF_I,
20 
21 	/* External Input Clocks */
22 	CLK_AUDIO_EXTAL,
23 	CLK_RTXIN,
24 	CLK_QEXTAL,
25 
26 	/* PLL Clocks */
27 	CLK_PLLCM33,
28 	CLK_PLLCLN,
29 	CLK_PLLDTY,
30 	CLK_PLLCA55,
31 	CLK_PLLVDO,
32 	CLK_PLLETH,
33 
34 	/* Internal Core Clocks */
35 	CLK_PLLCM33_DIV3,
36 	CLK_PLLCM33_DIV4,
37 	CLK_PLLCM33_DIV5,
38 	CLK_PLLCM33_DIV16,
39 	CLK_PLLCM33_GEAR,
40 	CLK_SMUX2_XSPI_CLK0,
41 	CLK_SMUX2_XSPI_CLK1,
42 	CLK_PLLCM33_XSPI,
43 	CLK_PLLCLN_DIV2,
44 	CLK_PLLCLN_DIV8,
45 	CLK_PLLCLN_DIV16,
46 	CLK_PLLCLN_DIV20,
47 	CLK_PLLDTY_ACPU,
48 	CLK_PLLDTY_ACPU_DIV2,
49 	CLK_PLLDTY_ACPU_DIV4,
50 	CLK_PLLDTY_DIV8,
51 	CLK_PLLETH_DIV_250_FIX,
52 	CLK_PLLETH_DIV_125_FIX,
53 	CLK_CSDIV_PLLETH_GBE0,
54 	CLK_CSDIV_PLLETH_GBE1,
55 	CLK_SMUX2_GBE0_TXCLK,
56 	CLK_SMUX2_GBE0_RXCLK,
57 	CLK_SMUX2_GBE1_TXCLK,
58 	CLK_SMUX2_GBE1_RXCLK,
59 	CLK_PLLDTY_DIV16,
60 	CLK_PLLVDO_CRU0,
61 	CLK_PLLVDO_GPU,
62 
63 	/* Module Clocks */
64 	MOD_CLK_BASE,
65 };
66 
67 static const struct clk_div_table dtable_1_8[] = {
68 	{0, 1},
69 	{1, 2},
70 	{2, 4},
71 	{3, 8},
72 	{0, 0},
73 };
74 
75 static const struct clk_div_table dtable_2_4[] = {
76 	{0, 2},
77 	{1, 4},
78 	{0, 0},
79 };
80 
81 static const struct clk_div_table dtable_2_16[] = {
82 	{0, 2},
83 	{1, 4},
84 	{2, 8},
85 	{3, 16},
86 	{0, 0},
87 };
88 
89 static const struct clk_div_table dtable_2_64[] = {
90 	{0, 2},
91 	{1, 4},
92 	{2, 8},
93 	{3, 16},
94 	{4, 64},
95 	{0, 0},
96 };
97 
98 static const struct clk_div_table dtable_2_100[] = {
99 	{0, 2},
100 	{1, 10},
101 	{2, 100},
102 	{0, 0},
103 };
104 
105 /* Mux clock tables */
106 static const char * const smux2_gbe0_rxclk[] = { ".plleth_gbe0", "et0_rxclk" };
107 static const char * const smux2_gbe0_txclk[] = { ".plleth_gbe0", "et0_txclk" };
108 static const char * const smux2_gbe1_rxclk[] = { ".plleth_gbe1", "et1_rxclk" };
109 static const char * const smux2_gbe1_txclk[] = { ".plleth_gbe1", "et1_txclk" };
110 static const char * const smux2_xspi_clk0[] = { ".pllcm33_div3", ".pllcm33_div4" };
111 static const char * const smux2_xspi_clk1[] = { ".smux2_xspi_clk0", ".pllcm33_div5" };
112 
113 static const struct cpg_core_clk r9a09g047_core_clks[] __initconst = {
114 	/* External Clock Inputs */
115 	DEF_INPUT("audio_extal", CLK_AUDIO_EXTAL),
116 	DEF_INPUT("rtxin", CLK_RTXIN),
117 	DEF_INPUT("qextal", CLK_QEXTAL),
118 
119 	/* PLL Clocks */
120 	DEF_FIXED(".pllcm33", CLK_PLLCM33, CLK_QEXTAL, 200, 3),
121 	DEF_FIXED(".pllcln", CLK_PLLCLN, CLK_QEXTAL, 200, 3),
122 	DEF_FIXED(".plldty", CLK_PLLDTY, CLK_QEXTAL, 200, 3),
123 	DEF_PLL(".pllca55", CLK_PLLCA55, CLK_QEXTAL, PLLCA55),
124 	DEF_FIXED(".plleth", CLK_PLLETH, CLK_QEXTAL, 125, 3),
125 	DEF_FIXED(".pllvdo", CLK_PLLVDO, CLK_QEXTAL, 105, 2),
126 
127 	/* Internal Core Clocks */
128 	DEF_FIXED(".pllcm33_div3", CLK_PLLCM33_DIV3, CLK_PLLCM33, 1, 3),
129 	DEF_FIXED(".pllcm33_div4", CLK_PLLCM33_DIV4, CLK_PLLCM33, 1, 4),
130 	DEF_FIXED(".pllcm33_div5", CLK_PLLCM33_DIV5, CLK_PLLCM33, 1, 5),
131 	DEF_FIXED(".pllcm33_div16", CLK_PLLCM33_DIV16, CLK_PLLCM33, 1, 16),
132 
133 	DEF_DDIV(".pllcm33_gear", CLK_PLLCM33_GEAR, CLK_PLLCM33_DIV4, CDDIV0_DIVCTL1, dtable_2_64),
134 
135 	DEF_SMUX(".smux2_xspi_clk0", CLK_SMUX2_XSPI_CLK0, SSEL1_SELCTL2, smux2_xspi_clk0),
136 	DEF_SMUX(".smux2_xspi_clk1", CLK_SMUX2_XSPI_CLK1, SSEL1_SELCTL3, smux2_xspi_clk1),
137 	DEF_CSDIV(".pllcm33_xspi", CLK_PLLCM33_XSPI, CLK_SMUX2_XSPI_CLK1, CSDIV0_DIVCTL3,
138 		  dtable_2_16),
139 	DEF_FIXED(".pllcln_div2", CLK_PLLCLN_DIV2, CLK_PLLCLN, 1, 2),
140 	DEF_FIXED(".pllcln_div8", CLK_PLLCLN_DIV8, CLK_PLLCLN, 1, 8),
141 	DEF_FIXED(".pllcln_div16", CLK_PLLCLN_DIV16, CLK_PLLCLN, 1, 16),
142 	DEF_FIXED(".pllcln_div20", CLK_PLLCLN_DIV20, CLK_PLLCLN, 1, 20),
143 
144 	DEF_DDIV(".plldty_acpu", CLK_PLLDTY_ACPU, CLK_PLLDTY, CDDIV0_DIVCTL2, dtable_2_64),
145 	DEF_FIXED(".plldty_acpu_div2", CLK_PLLDTY_ACPU_DIV2, CLK_PLLDTY_ACPU, 1, 2),
146 	DEF_FIXED(".plldty_acpu_div4", CLK_PLLDTY_ACPU_DIV4, CLK_PLLDTY_ACPU, 1, 4),
147 	DEF_FIXED(".plldty_div8", CLK_PLLDTY_DIV8, CLK_PLLDTY, 1, 8),
148 
149 	DEF_FIXED(".plleth_250_fix", CLK_PLLETH_DIV_250_FIX, CLK_PLLETH, 1, 4),
150 	DEF_FIXED(".plleth_125_fix", CLK_PLLETH_DIV_125_FIX, CLK_PLLETH_DIV_250_FIX, 1, 2),
151 	DEF_CSDIV(".plleth_gbe0", CLK_CSDIV_PLLETH_GBE0, CLK_PLLETH_DIV_250_FIX,
152 		  CSDIV0_DIVCTL0, dtable_2_100),
153 	DEF_CSDIV(".plleth_gbe1", CLK_CSDIV_PLLETH_GBE1, CLK_PLLETH_DIV_250_FIX,
154 		  CSDIV0_DIVCTL1, dtable_2_100),
155 	DEF_SMUX(".smux2_gbe0_txclk", CLK_SMUX2_GBE0_TXCLK, SSEL0_SELCTL2, smux2_gbe0_txclk),
156 	DEF_SMUX(".smux2_gbe0_rxclk", CLK_SMUX2_GBE0_RXCLK, SSEL0_SELCTL3, smux2_gbe0_rxclk),
157 	DEF_SMUX(".smux2_gbe1_txclk", CLK_SMUX2_GBE1_TXCLK, SSEL1_SELCTL0, smux2_gbe1_txclk),
158 	DEF_SMUX(".smux2_gbe1_rxclk", CLK_SMUX2_GBE1_RXCLK, SSEL1_SELCTL1, smux2_gbe1_rxclk),
159 	DEF_FIXED(".plldty_div16", CLK_PLLDTY_DIV16, CLK_PLLDTY, 1, 16),
160 
161 	DEF_DDIV(".pllvdo_cru0", CLK_PLLVDO_CRU0, CLK_PLLVDO, CDDIV3_DIVCTL3, dtable_2_4),
162 	DEF_DDIV(".pllvdo_gpu", CLK_PLLVDO_GPU, CLK_PLLVDO, CDDIV3_DIVCTL1, dtable_2_64),
163 
164 	/* Core Clocks */
165 	DEF_FIXED("sys_0_pclk", R9A09G047_SYS_0_PCLK, CLK_QEXTAL, 1, 1),
166 	DEF_DDIV("ca55_0_coreclk0", R9A09G047_CA55_0_CORECLK0, CLK_PLLCA55,
167 		 CDDIV1_DIVCTL0, dtable_1_8),
168 	DEF_DDIV("ca55_0_coreclk1", R9A09G047_CA55_0_CORECLK1, CLK_PLLCA55,
169 		 CDDIV1_DIVCTL1, dtable_1_8),
170 	DEF_DDIV("ca55_0_coreclk2", R9A09G047_CA55_0_CORECLK2, CLK_PLLCA55,
171 		 CDDIV1_DIVCTL2, dtable_1_8),
172 	DEF_DDIV("ca55_0_coreclk3", R9A09G047_CA55_0_CORECLK3, CLK_PLLCA55,
173 		 CDDIV1_DIVCTL3, dtable_1_8),
174 	DEF_FIXED("iotop_0_shclk", R9A09G047_IOTOP_0_SHCLK, CLK_PLLCM33_DIV16, 1, 1),
175 	DEF_FIXED("spi_clk_spi", R9A09G047_SPI_CLK_SPI, CLK_PLLCM33_XSPI, 1, 2),
176 	DEF_FIXED("gbeth_0_clk_ptp_ref_i", R9A09G047_GBETH_0_CLK_PTP_REF_I,
177 		  CLK_PLLETH_DIV_125_FIX, 1, 1),
178 	DEF_FIXED("gbeth_1_clk_ptp_ref_i", R9A09G047_GBETH_1_CLK_PTP_REF_I,
179 		  CLK_PLLETH_DIV_125_FIX, 1, 1),
180 };
181 
182 static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = {
183 	DEF_MOD_CRITICAL("icu_0_pclk_i",	CLK_PLLCM33_DIV16, 0, 5, 0, 5,
184 						BUS_MSTOP_NONE),
185 	DEF_MOD_CRITICAL("gic_0_gicclk",	CLK_PLLDTY_ACPU_DIV4, 1, 3, 0, 19,
186 						BUS_MSTOP(3, BIT(5))),
187 	DEF_MOD("wdt_1_clkp",			CLK_PLLCLN_DIV16, 4, 13, 2, 13,
188 						BUS_MSTOP(1, BIT(0))),
189 	DEF_MOD("wdt_1_clk_loco",		CLK_QEXTAL, 4, 14, 2, 14,
190 						BUS_MSTOP(1, BIT(0))),
191 	DEF_MOD("wdt_2_clkp",			CLK_PLLCLN_DIV16, 4, 15, 2, 15,
192 						BUS_MSTOP(5, BIT(12))),
193 	DEF_MOD("wdt_2_clk_loco",		CLK_QEXTAL, 5, 0, 2, 16,
194 						BUS_MSTOP(5, BIT(12))),
195 	DEF_MOD("wdt_3_clkp",			CLK_PLLCLN_DIV16, 5, 1, 2, 17,
196 						BUS_MSTOP(5, BIT(13))),
197 	DEF_MOD("wdt_3_clk_loco",		CLK_QEXTAL, 5, 2, 2, 18,
198 						BUS_MSTOP(5, BIT(13))),
199 	DEF_MOD("scif_0_clk_pck",		CLK_PLLCM33_DIV16, 8, 15, 4, 15,
200 						BUS_MSTOP(3, BIT(14))),
201 	DEF_MOD("i3c_0_pclkrw",			CLK_PLLCLN_DIV16, 9, 0, 4, 16,
202 						BUS_MSTOP(10, BIT(15))),
203 	DEF_MOD("i3c_0_pclk",			CLK_PLLCLN_DIV16, 9, 1, 4, 17,
204 						BUS_MSTOP(10, BIT(15))),
205 	DEF_MOD("i3c_0_tclk",			CLK_PLLCLN_DIV8, 9, 2, 4, 18,
206 						BUS_MSTOP(10, BIT(15))),
207 	DEF_MOD("riic_8_ckm",			CLK_PLLCM33_DIV16, 9, 3, 4, 19,
208 						BUS_MSTOP(3, BIT(13))),
209 	DEF_MOD("riic_0_ckm",			CLK_PLLCLN_DIV16, 9, 4, 4, 20,
210 						BUS_MSTOP(1, BIT(1))),
211 	DEF_MOD("riic_1_ckm",			CLK_PLLCLN_DIV16, 9, 5, 4, 21,
212 						BUS_MSTOP(1, BIT(2))),
213 	DEF_MOD("riic_2_ckm",			CLK_PLLCLN_DIV16, 9, 6, 4, 22,
214 						BUS_MSTOP(1, BIT(3))),
215 	DEF_MOD("riic_3_ckm",			CLK_PLLCLN_DIV16, 9, 7, 4, 23,
216 						BUS_MSTOP(1, BIT(4))),
217 	DEF_MOD("riic_4_ckm",			CLK_PLLCLN_DIV16, 9, 8, 4, 24,
218 						BUS_MSTOP(1, BIT(5))),
219 	DEF_MOD("riic_5_ckm",			CLK_PLLCLN_DIV16, 9, 9, 4, 25,
220 						BUS_MSTOP(1, BIT(6))),
221 	DEF_MOD("riic_6_ckm",			CLK_PLLCLN_DIV16, 9, 10, 4, 26,
222 						BUS_MSTOP(1, BIT(7))),
223 	DEF_MOD("riic_7_ckm",			CLK_PLLCLN_DIV16, 9, 11, 4, 27,
224 						BUS_MSTOP(1, BIT(8))),
225 	DEF_MOD("canfd_0_pclk",			CLK_PLLCLN_DIV16, 9, 12, 4, 28,
226 						BUS_MSTOP(10, BIT(14))),
227 	DEF_MOD("canfd_0_clk_ram",		CLK_PLLCLN_DIV8, 9, 13, 4, 29,
228 						BUS_MSTOP(10, BIT(14))),
229 	DEF_MOD("canfd_0_clkc",			CLK_PLLCLN_DIV20, 9, 14, 4, 30,
230 						BUS_MSTOP(10, BIT(14))),
231 	DEF_MOD("spi_hclk",			CLK_PLLCM33_GEAR, 9, 15, 4, 31,
232 						BUS_MSTOP(4, BIT(5))),
233 	DEF_MOD("spi_aclk",			CLK_PLLCM33_GEAR, 10, 0, 5, 0,
234 						BUS_MSTOP(4, BIT(5))),
235 	DEF_MOD_NO_PM("spi_clk_spix2",		CLK_PLLCM33_XSPI, 10, 1, 5, 2,
236 						BUS_MSTOP(4, BIT(5))),
237 	DEF_MOD("sdhi_0_imclk",			CLK_PLLCLN_DIV8, 10, 3, 5, 3,
238 						BUS_MSTOP(8, BIT(2))),
239 	DEF_MOD("sdhi_0_imclk2",		CLK_PLLCLN_DIV8, 10, 4, 5, 4,
240 						BUS_MSTOP(8, BIT(2))),
241 	DEF_MOD("sdhi_0_clk_hs",		CLK_PLLCLN_DIV2, 10, 5, 5, 5,
242 						BUS_MSTOP(8, BIT(2))),
243 	DEF_MOD("sdhi_0_aclk",			CLK_PLLDTY_ACPU_DIV4, 10, 6, 5, 6,
244 						BUS_MSTOP(8, BIT(2))),
245 	DEF_MOD("sdhi_1_imclk",			CLK_PLLCLN_DIV8, 10, 7, 5, 7,
246 						BUS_MSTOP(8, BIT(3))),
247 	DEF_MOD("sdhi_1_imclk2",		CLK_PLLCLN_DIV8, 10, 8, 5, 8,
248 						BUS_MSTOP(8, BIT(3))),
249 	DEF_MOD("sdhi_1_clk_hs",		CLK_PLLCLN_DIV2, 10, 9, 5, 9,
250 						BUS_MSTOP(8, BIT(3))),
251 	DEF_MOD("sdhi_1_aclk",			CLK_PLLDTY_ACPU_DIV4, 10, 10, 5, 10,
252 						BUS_MSTOP(8, BIT(3))),
253 	DEF_MOD("sdhi_2_imclk",			CLK_PLLCLN_DIV8, 10, 11, 5, 11,
254 						BUS_MSTOP(8, BIT(4))),
255 	DEF_MOD("sdhi_2_imclk2",		CLK_PLLCLN_DIV8, 10, 12, 5, 12,
256 						BUS_MSTOP(8, BIT(4))),
257 	DEF_MOD("sdhi_2_clk_hs",		CLK_PLLCLN_DIV2, 10, 13, 5, 13,
258 						BUS_MSTOP(8, BIT(4))),
259 	DEF_MOD("sdhi_2_aclk",			CLK_PLLDTY_ACPU_DIV4, 10, 14, 5, 14,
260 						BUS_MSTOP(8, BIT(4))),
261 	DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_tx_i", CLK_SMUX2_GBE0_TXCLK, 11, 8, 5, 24,
262 						BUS_MSTOP(8, BIT(5)), 1),
263 	DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_rx_i", CLK_SMUX2_GBE0_RXCLK, 11, 9, 5, 25,
264 						BUS_MSTOP(8, BIT(5)), 1),
265 	DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_tx_180_i", CLK_SMUX2_GBE0_TXCLK, 11, 10, 5, 26,
266 						BUS_MSTOP(8, BIT(5)), 1),
267 	DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_rx_180_i", CLK_SMUX2_GBE0_RXCLK, 11, 11, 5, 27,
268 						BUS_MSTOP(8, BIT(5)), 1),
269 	DEF_MOD("gbeth_0_aclk_csr_i",		CLK_PLLDTY_DIV8, 11, 12, 5, 28,
270 						BUS_MSTOP(8, BIT(5))),
271 	DEF_MOD("gbeth_0_aclk_i",		CLK_PLLDTY_DIV8, 11, 13, 5, 29,
272 						BUS_MSTOP(8, BIT(5))),
273 	DEF_MOD_MUX_EXTERNAL("gbeth_1_clk_tx_i", CLK_SMUX2_GBE1_TXCLK, 11, 14, 5, 30,
274 						BUS_MSTOP(8, BIT(6)), 1),
275 	DEF_MOD_MUX_EXTERNAL("gbeth_1_clk_rx_i", CLK_SMUX2_GBE1_RXCLK, 11, 15, 5, 31,
276 						BUS_MSTOP(8, BIT(6)), 1),
277 	DEF_MOD_MUX_EXTERNAL("gbeth_1_clk_tx_180_i", CLK_SMUX2_GBE1_TXCLK, 12, 0, 6, 0,
278 						BUS_MSTOP(8, BIT(6)), 1),
279 	DEF_MOD_MUX_EXTERNAL("gbeth_1_clk_rx_180_i", CLK_SMUX2_GBE1_RXCLK, 12, 1, 6, 1,
280 						BUS_MSTOP(8, BIT(6)), 1),
281 	DEF_MOD("gbeth_1_aclk_csr_i",		CLK_PLLDTY_DIV8, 12, 2, 6, 2,
282 						BUS_MSTOP(8, BIT(6))),
283 	DEF_MOD("gbeth_1_aclk_i",		CLK_PLLDTY_DIV8, 12, 3, 6, 3,
284 						BUS_MSTOP(8, BIT(6))),
285 	DEF_MOD("cru_0_aclk",			CLK_PLLDTY_ACPU_DIV2, 13, 2, 6, 18,
286 						BUS_MSTOP(9, BIT(4))),
287 	DEF_MOD_NO_PM("cru_0_vclk",		CLK_PLLVDO_CRU0, 13, 3, 6, 19,
288 						BUS_MSTOP(9, BIT(4))),
289 	DEF_MOD("cru_0_pclk",			CLK_PLLDTY_DIV16, 13, 4, 6, 20,
290 						BUS_MSTOP(9, BIT(4))),
291 	DEF_MOD("ge3d_clk",			CLK_PLLVDO_GPU, 15, 0, 7, 16,
292 						BUS_MSTOP(3, BIT(4))),
293 	DEF_MOD("ge3d_axi_clk",			CLK_PLLDTY_ACPU_DIV2, 15, 1, 7, 17,
294 						BUS_MSTOP(3, BIT(4))),
295 	DEF_MOD("ge3d_ace_clk",			CLK_PLLDTY_ACPU_DIV2, 15, 2, 7, 18,
296 						BUS_MSTOP(3, BIT(4))),
297 	DEF_MOD("tsu_1_pclk",			CLK_QEXTAL, 16, 10, 8, 10,
298 						BUS_MSTOP(2, BIT(15))),
299 };
300 
301 static const struct rzv2h_reset r9a09g047_resets[] __initconst = {
302 	DEF_RST(3, 0, 1, 1),		/* SYS_0_PRESETN */
303 	DEF_RST(3, 6, 1, 7),		/* ICU_0_PRESETN_I */
304 	DEF_RST(3, 8, 1, 9),		/* GIC_0_GICRESET_N */
305 	DEF_RST(3, 9, 1, 10),		/* GIC_0_DBG_GICRESET_N */
306 	DEF_RST(7, 6, 3, 7),		/* WDT_1_RESET */
307 	DEF_RST(7, 7, 3, 8),		/* WDT_2_RESET */
308 	DEF_RST(7, 8, 3, 9),		/* WDT_3_RESET */
309 	DEF_RST(9, 5, 4, 6),		/* SCIF_0_RST_SYSTEM_N */
310 	DEF_RST(9, 6, 4, 7),		/* I3C_0_PRESETN */
311 	DEF_RST(9, 7, 4, 8),		/* I3C_0_TRESETN */
312 	DEF_RST(9, 8, 4, 9),		/* RIIC_0_MRST */
313 	DEF_RST(9, 9, 4, 10),		/* RIIC_1_MRST */
314 	DEF_RST(9, 10, 4, 11),		/* RIIC_2_MRST */
315 	DEF_RST(9, 11, 4, 12),		/* RIIC_3_MRST */
316 	DEF_RST(9, 12, 4, 13),		/* RIIC_4_MRST */
317 	DEF_RST(9, 13, 4, 14),		/* RIIC_5_MRST */
318 	DEF_RST(9, 14, 4, 15),		/* RIIC_6_MRST */
319 	DEF_RST(9, 15, 4, 16),		/* RIIC_7_MRST */
320 	DEF_RST(10, 0, 4, 17),		/* RIIC_8_MRST */
321 	DEF_RST(10, 1, 4, 18),		/* CANFD_0_RSTP_N */
322 	DEF_RST(10, 2, 4, 19),		/* CANFD_0_RSTC_N */
323 	DEF_RST(10, 3, 4, 20),		/* SPI_HRESETN */
324 	DEF_RST(10, 4, 4, 21),		/* SPI_ARESETN */
325 	DEF_RST(10, 7, 4, 24),		/* SDHI_0_IXRST */
326 	DEF_RST(10, 8, 4, 25),		/* SDHI_1_IXRST */
327 	DEF_RST(10, 9, 4, 26),		/* SDHI_2_IXRST */
328 	DEF_RST(11, 0, 5, 1),		/* GBETH_0_ARESETN_I */
329 	DEF_RST(11, 1, 5, 2),		/* GBETH_1_ARESETN_I */
330 	DEF_RST(12, 5, 5, 22),		/* CRU_0_PRESETN */
331 	DEF_RST(12, 6, 5, 23),		/* CRU_0_ARESETN */
332 	DEF_RST(12, 7, 5, 24),		/* CRU_0_S_RESETN */
333 	DEF_RST(13, 13, 6, 14),		/* GE3D_RESETN */
334 	DEF_RST(13, 14, 6, 15),		/* GE3D_AXI_RESETN */
335 	DEF_RST(13, 15, 6, 16),		/* GE3D_ACE_RESETN */
336 	DEF_RST(15, 8, 7, 9),		/* TSU_1_PRESETN */
337 };
338 
339 const struct rzv2h_cpg_info r9a09g047_cpg_info __initconst = {
340 	/* Core Clocks */
341 	.core_clks = r9a09g047_core_clks,
342 	.num_core_clks = ARRAY_SIZE(r9a09g047_core_clks),
343 	.last_dt_core_clk = LAST_DT_CORE_CLK,
344 	.num_total_core_clks = MOD_CLK_BASE,
345 
346 	/* Module Clocks */
347 	.mod_clks = r9a09g047_mod_clks,
348 	.num_mod_clks = ARRAY_SIZE(r9a09g047_mod_clks),
349 	.num_hw_mod_clks = 28 * 16,
350 
351 	/* Resets */
352 	.resets = r9a09g047_resets,
353 	.num_resets = ARRAY_SIZE(r9a09g047_resets),
354 
355 	.num_mstop_bits = 208,
356 };
357