1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Renesas RZ/G3E CPG driver 4 * 5 * Copyright (C) 2024 Renesas Electronics Corp. 6 */ 7 8 #include <linux/clk-provider.h> 9 #include <linux/device.h> 10 #include <linux/init.h> 11 #include <linux/kernel.h> 12 13 #include <dt-bindings/clock/renesas,r9a09g047-cpg.h> 14 15 #include "rzv2h-cpg.h" 16 17 enum clk_ids { 18 /* Core Clock Outputs exported to DT */ 19 LAST_DT_CORE_CLK = R9A09G047_GBETH_1_CLK_PTP_REF_I, 20 21 /* External Input Clocks */ 22 CLK_AUDIO_EXTAL, 23 CLK_RTXIN, 24 CLK_QEXTAL, 25 26 /* PLL Clocks */ 27 CLK_PLLCM33, 28 CLK_PLLCLN, 29 CLK_PLLDTY, 30 CLK_PLLCA55, 31 CLK_PLLVDO, 32 33 /* Internal Core Clocks */ 34 CLK_PLLCM33_DIV3, 35 CLK_PLLCM33_DIV4, 36 CLK_PLLCM33_DIV5, 37 CLK_PLLCM33_DIV16, 38 CLK_PLLCM33_GEAR, 39 CLK_SMUX2_XSPI_CLK0, 40 CLK_SMUX2_XSPI_CLK1, 41 CLK_PLLCM33_XSPI, 42 CLK_PLLCLN_DIV2, 43 CLK_PLLCLN_DIV8, 44 CLK_PLLCLN_DIV16, 45 CLK_PLLCLN_DIV20, 46 CLK_PLLDTY_ACPU, 47 CLK_PLLDTY_ACPU_DIV2, 48 CLK_PLLDTY_ACPU_DIV4, 49 CLK_PLLDTY_DIV16, 50 CLK_PLLVDO_CRU0, 51 CLK_PLLVDO_GPU, 52 53 /* Module Clocks */ 54 MOD_CLK_BASE, 55 }; 56 57 static const struct clk_div_table dtable_1_8[] = { 58 {0, 1}, 59 {1, 2}, 60 {2, 4}, 61 {3, 8}, 62 {0, 0}, 63 }; 64 65 static const struct clk_div_table dtable_2_4[] = { 66 {0, 2}, 67 {1, 4}, 68 {0, 0}, 69 }; 70 71 static const struct clk_div_table dtable_2_16[] = { 72 {0, 2}, 73 {1, 4}, 74 {2, 8}, 75 {3, 16}, 76 {0, 0}, 77 }; 78 79 static const struct clk_div_table dtable_2_64[] = { 80 {0, 2}, 81 {1, 4}, 82 {2, 8}, 83 {3, 16}, 84 {4, 64}, 85 {0, 0}, 86 }; 87 88 /* Mux clock tables */ 89 static const char * const smux2_xspi_clk0[] = { ".pllcm33_div3", ".pllcm33_div4" }; 90 static const char * const smux2_xspi_clk1[] = { ".smux2_xspi_clk0", ".pllcm33_div5" }; 91 92 static const struct cpg_core_clk r9a09g047_core_clks[] __initconst = { 93 /* External Clock Inputs */ 94 DEF_INPUT("audio_extal", CLK_AUDIO_EXTAL), 95 DEF_INPUT("rtxin", CLK_RTXIN), 96 DEF_INPUT("qextal", CLK_QEXTAL), 97 98 /* PLL Clocks */ 99 DEF_FIXED(".pllcm33", CLK_PLLCM33, CLK_QEXTAL, 200, 3), 100 DEF_FIXED(".pllcln", CLK_PLLCLN, CLK_QEXTAL, 200, 3), 101 DEF_FIXED(".plldty", CLK_PLLDTY, CLK_QEXTAL, 200, 3), 102 DEF_PLL(".pllca55", CLK_PLLCA55, CLK_QEXTAL, PLLCA55), 103 DEF_FIXED(".pllvdo", CLK_PLLVDO, CLK_QEXTAL, 105, 2), 104 105 /* Internal Core Clocks */ 106 DEF_FIXED(".pllcm33_div3", CLK_PLLCM33_DIV3, CLK_PLLCM33, 1, 3), 107 DEF_FIXED(".pllcm33_div4", CLK_PLLCM33_DIV4, CLK_PLLCM33, 1, 4), 108 DEF_FIXED(".pllcm33_div5", CLK_PLLCM33_DIV5, CLK_PLLCM33, 1, 5), 109 DEF_FIXED(".pllcm33_div16", CLK_PLLCM33_DIV16, CLK_PLLCM33, 1, 16), 110 111 DEF_DDIV(".pllcm33_gear", CLK_PLLCM33_GEAR, CLK_PLLCM33_DIV4, CDDIV0_DIVCTL1, dtable_2_64), 112 113 DEF_SMUX(".smux2_xspi_clk0", CLK_SMUX2_XSPI_CLK0, SSEL1_SELCTL2, smux2_xspi_clk0), 114 DEF_SMUX(".smux2_xspi_clk1", CLK_SMUX2_XSPI_CLK1, SSEL1_SELCTL3, smux2_xspi_clk1), 115 DEF_CSDIV(".pllcm33_xspi", CLK_PLLCM33_XSPI, CLK_SMUX2_XSPI_CLK1, CSDIV0_DIVCTL3, 116 dtable_2_16), 117 DEF_FIXED(".pllcln_div2", CLK_PLLCLN_DIV2, CLK_PLLCLN, 1, 2), 118 DEF_FIXED(".pllcln_div8", CLK_PLLCLN_DIV8, CLK_PLLCLN, 1, 8), 119 DEF_FIXED(".pllcln_div16", CLK_PLLCLN_DIV16, CLK_PLLCLN, 1, 16), 120 DEF_FIXED(".pllcln_div20", CLK_PLLCLN_DIV20, CLK_PLLCLN, 1, 20), 121 122 DEF_DDIV(".plldty_acpu", CLK_PLLDTY_ACPU, CLK_PLLDTY, CDDIV0_DIVCTL2, dtable_2_64), 123 DEF_FIXED(".plldty_acpu_div2", CLK_PLLDTY_ACPU_DIV2, CLK_PLLDTY_ACPU, 1, 2), 124 DEF_FIXED(".plldty_acpu_div4", CLK_PLLDTY_ACPU_DIV4, CLK_PLLDTY_ACPU, 1, 4), 125 DEF_FIXED(".plldty_div16", CLK_PLLDTY_DIV16, CLK_PLLDTY, 1, 16), 126 127 DEF_DDIV(".pllvdo_cru0", CLK_PLLVDO_CRU0, CLK_PLLVDO, CDDIV3_DIVCTL3, dtable_2_4), 128 DEF_DDIV(".pllvdo_gpu", CLK_PLLVDO_GPU, CLK_PLLVDO, CDDIV3_DIVCTL1, dtable_2_64), 129 130 /* Core Clocks */ 131 DEF_FIXED("sys_0_pclk", R9A09G047_SYS_0_PCLK, CLK_QEXTAL, 1, 1), 132 DEF_DDIV("ca55_0_coreclk0", R9A09G047_CA55_0_CORECLK0, CLK_PLLCA55, 133 CDDIV1_DIVCTL0, dtable_1_8), 134 DEF_DDIV("ca55_0_coreclk1", R9A09G047_CA55_0_CORECLK1, CLK_PLLCA55, 135 CDDIV1_DIVCTL1, dtable_1_8), 136 DEF_DDIV("ca55_0_coreclk2", R9A09G047_CA55_0_CORECLK2, CLK_PLLCA55, 137 CDDIV1_DIVCTL2, dtable_1_8), 138 DEF_DDIV("ca55_0_coreclk3", R9A09G047_CA55_0_CORECLK3, CLK_PLLCA55, 139 CDDIV1_DIVCTL3, dtable_1_8), 140 DEF_FIXED("iotop_0_shclk", R9A09G047_IOTOP_0_SHCLK, CLK_PLLCM33_DIV16, 1, 1), 141 DEF_FIXED("spi_clk_spi", R9A09G047_SPI_CLK_SPI, CLK_PLLCM33_XSPI, 1, 2), 142 }; 143 144 static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = { 145 DEF_MOD_CRITICAL("icu_0_pclk_i", CLK_PLLCM33_DIV16, 0, 5, 0, 5, 146 BUS_MSTOP_NONE), 147 DEF_MOD_CRITICAL("gic_0_gicclk", CLK_PLLDTY_ACPU_DIV4, 1, 3, 0, 19, 148 BUS_MSTOP(3, BIT(5))), 149 DEF_MOD("wdt_1_clkp", CLK_PLLCLN_DIV16, 4, 13, 2, 13, 150 BUS_MSTOP(1, BIT(0))), 151 DEF_MOD("wdt_1_clk_loco", CLK_QEXTAL, 4, 14, 2, 14, 152 BUS_MSTOP(1, BIT(0))), 153 DEF_MOD("wdt_2_clkp", CLK_PLLCLN_DIV16, 4, 15, 2, 15, 154 BUS_MSTOP(5, BIT(12))), 155 DEF_MOD("wdt_2_clk_loco", CLK_QEXTAL, 5, 0, 2, 16, 156 BUS_MSTOP(5, BIT(12))), 157 DEF_MOD("wdt_3_clkp", CLK_PLLCLN_DIV16, 5, 1, 2, 17, 158 BUS_MSTOP(5, BIT(13))), 159 DEF_MOD("wdt_3_clk_loco", CLK_QEXTAL, 5, 2, 2, 18, 160 BUS_MSTOP(5, BIT(13))), 161 DEF_MOD("scif_0_clk_pck", CLK_PLLCM33_DIV16, 8, 15, 4, 15, 162 BUS_MSTOP(3, BIT(14))), 163 DEF_MOD("riic_8_ckm", CLK_PLLCM33_DIV16, 9, 3, 4, 19, 164 BUS_MSTOP(3, BIT(13))), 165 DEF_MOD("riic_0_ckm", CLK_PLLCLN_DIV16, 9, 4, 4, 20, 166 BUS_MSTOP(1, BIT(1))), 167 DEF_MOD("riic_1_ckm", CLK_PLLCLN_DIV16, 9, 5, 4, 21, 168 BUS_MSTOP(1, BIT(2))), 169 DEF_MOD("riic_2_ckm", CLK_PLLCLN_DIV16, 9, 6, 4, 22, 170 BUS_MSTOP(1, BIT(3))), 171 DEF_MOD("riic_3_ckm", CLK_PLLCLN_DIV16, 9, 7, 4, 23, 172 BUS_MSTOP(1, BIT(4))), 173 DEF_MOD("riic_4_ckm", CLK_PLLCLN_DIV16, 9, 8, 4, 24, 174 BUS_MSTOP(1, BIT(5))), 175 DEF_MOD("riic_5_ckm", CLK_PLLCLN_DIV16, 9, 9, 4, 25, 176 BUS_MSTOP(1, BIT(6))), 177 DEF_MOD("riic_6_ckm", CLK_PLLCLN_DIV16, 9, 10, 4, 26, 178 BUS_MSTOP(1, BIT(7))), 179 DEF_MOD("riic_7_ckm", CLK_PLLCLN_DIV16, 9, 11, 4, 27, 180 BUS_MSTOP(1, BIT(8))), 181 DEF_MOD("canfd_0_pclk", CLK_PLLCLN_DIV16, 9, 12, 4, 28, 182 BUS_MSTOP(10, BIT(14))), 183 DEF_MOD("canfd_0_clk_ram", CLK_PLLCLN_DIV8, 9, 13, 4, 29, 184 BUS_MSTOP(10, BIT(14))), 185 DEF_MOD("canfd_0_clkc", CLK_PLLCLN_DIV20, 9, 14, 4, 30, 186 BUS_MSTOP(10, BIT(14))), 187 DEF_MOD("spi_hclk", CLK_PLLCM33_GEAR, 9, 15, 4, 31, 188 BUS_MSTOP(4, BIT(5))), 189 DEF_MOD("spi_aclk", CLK_PLLCM33_GEAR, 10, 0, 5, 0, 190 BUS_MSTOP(4, BIT(5))), 191 DEF_MOD_NO_PM("spi_clk_spix2", CLK_PLLCM33_XSPI, 10, 1, 5, 2, 192 BUS_MSTOP(4, BIT(5))), 193 DEF_MOD("sdhi_0_imclk", CLK_PLLCLN_DIV8, 10, 3, 5, 3, 194 BUS_MSTOP(8, BIT(2))), 195 DEF_MOD("sdhi_0_imclk2", CLK_PLLCLN_DIV8, 10, 4, 5, 4, 196 BUS_MSTOP(8, BIT(2))), 197 DEF_MOD("sdhi_0_clk_hs", CLK_PLLCLN_DIV2, 10, 5, 5, 5, 198 BUS_MSTOP(8, BIT(2))), 199 DEF_MOD("sdhi_0_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 6, 5, 6, 200 BUS_MSTOP(8, BIT(2))), 201 DEF_MOD("sdhi_1_imclk", CLK_PLLCLN_DIV8, 10, 7, 5, 7, 202 BUS_MSTOP(8, BIT(3))), 203 DEF_MOD("sdhi_1_imclk2", CLK_PLLCLN_DIV8, 10, 8, 5, 8, 204 BUS_MSTOP(8, BIT(3))), 205 DEF_MOD("sdhi_1_clk_hs", CLK_PLLCLN_DIV2, 10, 9, 5, 9, 206 BUS_MSTOP(8, BIT(3))), 207 DEF_MOD("sdhi_1_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 10, 5, 10, 208 BUS_MSTOP(8, BIT(3))), 209 DEF_MOD("sdhi_2_imclk", CLK_PLLCLN_DIV8, 10, 11, 5, 11, 210 BUS_MSTOP(8, BIT(4))), 211 DEF_MOD("sdhi_2_imclk2", CLK_PLLCLN_DIV8, 10, 12, 5, 12, 212 BUS_MSTOP(8, BIT(4))), 213 DEF_MOD("sdhi_2_clk_hs", CLK_PLLCLN_DIV2, 10, 13, 5, 13, 214 BUS_MSTOP(8, BIT(4))), 215 DEF_MOD("sdhi_2_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 14, 5, 14, 216 BUS_MSTOP(8, BIT(4))), 217 DEF_MOD("cru_0_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 2, 6, 18, 218 BUS_MSTOP(9, BIT(4))), 219 DEF_MOD_NO_PM("cru_0_vclk", CLK_PLLVDO_CRU0, 13, 3, 6, 19, 220 BUS_MSTOP(9, BIT(4))), 221 DEF_MOD("cru_0_pclk", CLK_PLLDTY_DIV16, 13, 4, 6, 20, 222 BUS_MSTOP(9, BIT(4))), 223 DEF_MOD("ge3d_clk", CLK_PLLVDO_GPU, 15, 0, 7, 16, 224 BUS_MSTOP(3, BIT(4))), 225 DEF_MOD("ge3d_axi_clk", CLK_PLLDTY_ACPU_DIV2, 15, 1, 7, 17, 226 BUS_MSTOP(3, BIT(4))), 227 DEF_MOD("ge3d_ace_clk", CLK_PLLDTY_ACPU_DIV2, 15, 2, 7, 18, 228 BUS_MSTOP(3, BIT(4))), 229 DEF_MOD("tsu_1_pclk", CLK_QEXTAL, 16, 10, 8, 10, 230 BUS_MSTOP(2, BIT(15))), 231 }; 232 233 static const struct rzv2h_reset r9a09g047_resets[] __initconst = { 234 DEF_RST(3, 0, 1, 1), /* SYS_0_PRESETN */ 235 DEF_RST(3, 6, 1, 7), /* ICU_0_PRESETN_I */ 236 DEF_RST(3, 8, 1, 9), /* GIC_0_GICRESET_N */ 237 DEF_RST(3, 9, 1, 10), /* GIC_0_DBG_GICRESET_N */ 238 DEF_RST(7, 6, 3, 7), /* WDT_1_RESET */ 239 DEF_RST(7, 7, 3, 8), /* WDT_2_RESET */ 240 DEF_RST(7, 8, 3, 9), /* WDT_3_RESET */ 241 DEF_RST(9, 5, 4, 6), /* SCIF_0_RST_SYSTEM_N */ 242 DEF_RST(9, 8, 4, 9), /* RIIC_0_MRST */ 243 DEF_RST(9, 9, 4, 10), /* RIIC_1_MRST */ 244 DEF_RST(9, 10, 4, 11), /* RIIC_2_MRST */ 245 DEF_RST(9, 11, 4, 12), /* RIIC_3_MRST */ 246 DEF_RST(9, 12, 4, 13), /* RIIC_4_MRST */ 247 DEF_RST(9, 13, 4, 14), /* RIIC_5_MRST */ 248 DEF_RST(9, 14, 4, 15), /* RIIC_6_MRST */ 249 DEF_RST(9, 15, 4, 16), /* RIIC_7_MRST */ 250 DEF_RST(10, 0, 4, 17), /* RIIC_8_MRST */ 251 DEF_RST(10, 1, 4, 18), /* CANFD_0_RSTP_N */ 252 DEF_RST(10, 2, 4, 19), /* CANFD_0_RSTC_N */ 253 DEF_RST(10, 3, 4, 20), /* SPI_HRESETN */ 254 DEF_RST(10, 4, 4, 21), /* SPI_ARESETN */ 255 DEF_RST(10, 7, 4, 24), /* SDHI_0_IXRST */ 256 DEF_RST(10, 8, 4, 25), /* SDHI_1_IXRST */ 257 DEF_RST(10, 9, 4, 26), /* SDHI_2_IXRST */ 258 DEF_RST(12, 5, 5, 22), /* CRU_0_PRESETN */ 259 DEF_RST(12, 6, 5, 23), /* CRU_0_ARESETN */ 260 DEF_RST(12, 7, 5, 24), /* CRU_0_S_RESETN */ 261 DEF_RST(13, 13, 6, 14), /* GE3D_RESETN */ 262 DEF_RST(13, 14, 6, 15), /* GE3D_AXI_RESETN */ 263 DEF_RST(13, 15, 6, 16), /* GE3D_ACE_RESETN */ 264 DEF_RST(15, 8, 7, 9), /* TSU_1_PRESETN */ 265 }; 266 267 const struct rzv2h_cpg_info r9a09g047_cpg_info __initconst = { 268 /* Core Clocks */ 269 .core_clks = r9a09g047_core_clks, 270 .num_core_clks = ARRAY_SIZE(r9a09g047_core_clks), 271 .last_dt_core_clk = LAST_DT_CORE_CLK, 272 .num_total_core_clks = MOD_CLK_BASE, 273 274 /* Module Clocks */ 275 .mod_clks = r9a09g047_mod_clks, 276 .num_mod_clks = ARRAY_SIZE(r9a09g047_mod_clks), 277 .num_hw_mod_clks = 28 * 16, 278 279 /* Resets */ 280 .resets = r9a09g047_resets, 281 .num_resets = ARRAY_SIZE(r9a09g047_resets), 282 283 .num_mstop_bits = 208, 284 }; 285