1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 4 */ 5 6 #include <linux/clk-provider.h> 7 #include <linux/mod_devicetable.h> 8 #include <linux/module.h> 9 #include <linux/platform_device.h> 10 #include <linux/regmap.h> 11 12 #include <dt-bindings/clock/qcom,x1p42100-videocc.h> 13 14 #include "clk-alpha-pll.h" 15 #include "clk-branch.h" 16 #include "clk-rcg.h" 17 #include "clk-regmap.h" 18 #include "clk-regmap-divider.h" 19 #include "common.h" 20 #include "gdsc.h" 21 #include "reset.h" 22 23 enum { 24 DT_BI_TCXO, 25 }; 26 27 enum { 28 P_BI_TCXO, 29 P_VIDEO_CC_PLL0_OUT_MAIN, 30 P_VIDEO_CC_PLL1_OUT_MAIN, 31 }; 32 33 static const struct pll_vco lucid_ole_vco[] = { 34 { 249600000, 2300000000, 0 }, 35 }; 36 37 /* 420.0 MHz Configuration */ 38 static const struct alpha_pll_config video_cc_pll0_config = { 39 .l = 0x15, 40 .alpha = 0xe000, 41 .config_ctl_val = 0x20485699, 42 .config_ctl_hi_val = 0x00182261, 43 .config_ctl_hi1_val = 0x82aa299c, 44 .test_ctl_val = 0x00000000, 45 .test_ctl_hi_val = 0x00000003, 46 .test_ctl_hi1_val = 0x00009000, 47 .test_ctl_hi2_val = 0x00000034, 48 .user_ctl_val = 0x00000000, 49 .user_ctl_hi_val = 0x00000005, 50 }; 51 52 static struct clk_alpha_pll video_cc_pll0 = { 53 .offset = 0x0, 54 .config = &video_cc_pll0_config, 55 .vco_table = lucid_ole_vco, 56 .num_vco = ARRAY_SIZE(lucid_ole_vco), 57 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 58 .clkr = { 59 .hw.init = &(const struct clk_init_data) { 60 .name = "video_cc_pll0", 61 .parent_data = &(const struct clk_parent_data) { 62 .index = DT_BI_TCXO, 63 }, 64 .num_parents = 1, 65 .ops = &clk_alpha_pll_lucid_evo_ops, 66 }, 67 }, 68 }; 69 70 /* 1050.0 MHz Configuration */ 71 static const struct alpha_pll_config video_cc_pll1_config = { 72 .l = 0x36, 73 .alpha = 0xb000, 74 .config_ctl_val = 0x20485699, 75 .config_ctl_hi_val = 0x00182261, 76 .config_ctl_hi1_val = 0x82aa299c, 77 .test_ctl_val = 0x00000000, 78 .test_ctl_hi_val = 0x00000003, 79 .test_ctl_hi1_val = 0x00009000, 80 .test_ctl_hi2_val = 0x00000034, 81 .user_ctl_val = 0x00000000, 82 .user_ctl_hi_val = 0x00000005, 83 }; 84 85 static struct clk_alpha_pll video_cc_pll1 = { 86 .offset = 0x1000, 87 .config = &video_cc_pll1_config, 88 .vco_table = lucid_ole_vco, 89 .num_vco = ARRAY_SIZE(lucid_ole_vco), 90 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 91 .clkr = { 92 .hw.init = &(const struct clk_init_data) { 93 .name = "video_cc_pll1", 94 .parent_data = &(const struct clk_parent_data) { 95 .index = DT_BI_TCXO, 96 }, 97 .num_parents = 1, 98 .ops = &clk_alpha_pll_lucid_evo_ops, 99 }, 100 }, 101 }; 102 103 static const struct parent_map video_cc_parent_map_0[] = { 104 { P_BI_TCXO, 0 }, 105 }; 106 107 static const struct clk_parent_data video_cc_parent_data_0[] = { 108 { .index = DT_BI_TCXO }, 109 }; 110 111 static const struct parent_map video_cc_parent_map_1[] = { 112 { P_BI_TCXO, 0 }, 113 { P_VIDEO_CC_PLL0_OUT_MAIN, 1 }, 114 }; 115 116 static const struct clk_parent_data video_cc_parent_data_1[] = { 117 { .index = DT_BI_TCXO }, 118 { .hw = &video_cc_pll0.clkr.hw }, 119 }; 120 121 static const struct parent_map video_cc_parent_map_2[] = { 122 { P_BI_TCXO, 0 }, 123 { P_VIDEO_CC_PLL1_OUT_MAIN, 1 }, 124 }; 125 126 static const struct clk_parent_data video_cc_parent_data_2[] = { 127 { .index = DT_BI_TCXO }, 128 { .hw = &video_cc_pll1.clkr.hw }, 129 }; 130 131 static const struct freq_tbl ftbl_video_cc_mvs0_bse_clk_src[] = { 132 F(420000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), 133 F(600000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), 134 F(670000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), 135 F(848000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), 136 F(920000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), 137 { } 138 }; 139 140 static struct clk_rcg2 video_cc_mvs0_bse_clk_src = { 141 .cmd_rcgr = 0x8154, 142 .mnd_width = 0, 143 .hid_width = 5, 144 .parent_map = video_cc_parent_map_1, 145 .freq_tbl = ftbl_video_cc_mvs0_bse_clk_src, 146 .hw_clk_ctrl = true, 147 .clkr.hw.init = &(const struct clk_init_data) { 148 .name = "video_cc_mvs0_bse_clk_src", 149 .parent_data = video_cc_parent_data_1, 150 .num_parents = ARRAY_SIZE(video_cc_parent_data_1), 151 .flags = CLK_SET_RATE_PARENT, 152 .ops = &clk_rcg2_shared_ops, 153 }, 154 }; 155 156 static const struct freq_tbl ftbl_video_cc_mvs0_clk_src[] = { 157 F(210000000, P_VIDEO_CC_PLL0_OUT_MAIN, 2, 0, 0), 158 F(300000000, P_VIDEO_CC_PLL0_OUT_MAIN, 2, 0, 0), 159 F(335000000, P_VIDEO_CC_PLL0_OUT_MAIN, 2, 0, 0), 160 F(424000000, P_VIDEO_CC_PLL0_OUT_MAIN, 2, 0, 0), 161 F(460000000, P_VIDEO_CC_PLL0_OUT_MAIN, 2, 0, 0), 162 { } 163 }; 164 165 static struct clk_rcg2 video_cc_mvs0_clk_src = { 166 .cmd_rcgr = 0x8000, 167 .mnd_width = 0, 168 .hid_width = 5, 169 .parent_map = video_cc_parent_map_1, 170 .freq_tbl = ftbl_video_cc_mvs0_clk_src, 171 .hw_clk_ctrl = true, 172 .clkr.hw.init = &(const struct clk_init_data) { 173 .name = "video_cc_mvs0_clk_src", 174 .parent_data = video_cc_parent_data_1, 175 .num_parents = ARRAY_SIZE(video_cc_parent_data_1), 176 .flags = CLK_SET_RATE_PARENT, 177 .ops = &clk_rcg2_shared_ops, 178 }, 179 }; 180 181 static const struct freq_tbl ftbl_video_cc_mvs1_clk_src[] = { 182 F(1050000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0), 183 F(1350000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0), 184 F(1650000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0), 185 { } 186 }; 187 188 static struct clk_rcg2 video_cc_mvs1_clk_src = { 189 .cmd_rcgr = 0x8018, 190 .mnd_width = 0, 191 .hid_width = 5, 192 .parent_map = video_cc_parent_map_2, 193 .freq_tbl = ftbl_video_cc_mvs1_clk_src, 194 .hw_clk_ctrl = true, 195 .clkr.hw.init = &(const struct clk_init_data) { 196 .name = "video_cc_mvs1_clk_src", 197 .parent_data = video_cc_parent_data_2, 198 .num_parents = ARRAY_SIZE(video_cc_parent_data_2), 199 .flags = CLK_SET_RATE_PARENT, 200 .ops = &clk_rcg2_shared_ops, 201 }, 202 }; 203 204 static const struct freq_tbl ftbl_video_cc_xo_clk_src[] = { 205 F(19200000, P_BI_TCXO, 1, 0, 0), 206 { } 207 }; 208 209 static struct clk_rcg2 video_cc_xo_clk_src = { 210 .cmd_rcgr = 0x810c, 211 .mnd_width = 0, 212 .hid_width = 5, 213 .parent_map = video_cc_parent_map_0, 214 .freq_tbl = ftbl_video_cc_xo_clk_src, 215 .clkr.hw.init = &(const struct clk_init_data) { 216 .name = "video_cc_xo_clk_src", 217 .parent_data = video_cc_parent_data_0, 218 .num_parents = ARRAY_SIZE(video_cc_parent_data_0), 219 .flags = CLK_SET_RATE_PARENT, 220 .ops = &clk_rcg2_shared_ops, 221 }, 222 }; 223 224 static struct clk_regmap_div video_cc_mvs0_bse_div4_div_clk_src = { 225 .reg = 0x817c, 226 .shift = 0, 227 .width = 4, 228 .clkr.hw.init = &(const struct clk_init_data) { 229 .name = "video_cc_mvs0_bse_div4_div_clk_src", 230 .parent_hws = (const struct clk_hw*[]) { 231 &video_cc_mvs0_bse_clk_src.clkr.hw, 232 }, 233 .num_parents = 1, 234 .flags = CLK_SET_RATE_PARENT, 235 .ops = &clk_regmap_div_ro_ops, 236 }, 237 }; 238 239 static struct clk_regmap_div video_cc_mvs1_div_clk_src = { 240 .reg = 0x80ec, 241 .shift = 0, 242 .width = 4, 243 .clkr.hw.init = &(const struct clk_init_data) { 244 .name = "video_cc_mvs1_div_clk_src", 245 .parent_hws = (const struct clk_hw*[]) { 246 &video_cc_mvs1_clk_src.clkr.hw, 247 }, 248 .num_parents = 1, 249 .flags = CLK_SET_RATE_PARENT, 250 .ops = &clk_regmap_div_ro_ops, 251 }, 252 }; 253 254 static struct clk_regmap_div video_cc_mvs1c_div2_div_clk_src = { 255 .reg = 0x809c, 256 .shift = 0, 257 .width = 4, 258 .clkr.hw.init = &(const struct clk_init_data) { 259 .name = "video_cc_mvs1c_div2_div_clk_src", 260 .parent_hws = (const struct clk_hw*[]) { 261 &video_cc_mvs1_clk_src.clkr.hw, 262 }, 263 .num_parents = 1, 264 .flags = CLK_SET_RATE_PARENT, 265 .ops = &clk_regmap_div_ro_ops, 266 }, 267 }; 268 269 static struct clk_branch video_cc_mvs0_bse_clk = { 270 .halt_reg = 0x8170, 271 .halt_check = BRANCH_HALT, 272 .clkr = { 273 .enable_reg = 0x8170, 274 .enable_mask = BIT(0), 275 .hw.init = &(const struct clk_init_data) { 276 .name = "video_cc_mvs0_bse_clk", 277 .parent_hws = (const struct clk_hw*[]) { 278 &video_cc_mvs0_bse_div4_div_clk_src.clkr.hw, 279 }, 280 .num_parents = 1, 281 .flags = CLK_SET_RATE_PARENT, 282 .ops = &clk_branch2_ops, 283 }, 284 }, 285 }; 286 287 static struct clk_branch video_cc_mvs0_clk = { 288 .halt_reg = 0x80b8, 289 .halt_check = BRANCH_HALT_VOTED, 290 .hwcg_reg = 0x80b8, 291 .hwcg_bit = 1, 292 .clkr = { 293 .enable_reg = 0x80b8, 294 .enable_mask = BIT(0), 295 .hw.init = &(const struct clk_init_data) { 296 .name = "video_cc_mvs0_clk", 297 .parent_hws = (const struct clk_hw*[]) { 298 &video_cc_mvs0_clk_src.clkr.hw, 299 }, 300 .num_parents = 1, 301 .flags = CLK_SET_RATE_PARENT, 302 .ops = &clk_branch2_ops, 303 }, 304 }, 305 }; 306 307 static struct clk_branch video_cc_mvs0_shift_clk = { 308 .halt_reg = 0x8128, 309 .halt_check = BRANCH_HALT_VOTED, 310 .clkr = { 311 .enable_reg = 0x8128, 312 .enable_mask = BIT(0), 313 .hw.init = &(const struct clk_init_data) { 314 .name = "video_cc_mvs0_shift_clk", 315 .parent_hws = (const struct clk_hw*[]) { 316 &video_cc_xo_clk_src.clkr.hw, 317 }, 318 .num_parents = 1, 319 .flags = CLK_SET_RATE_PARENT, 320 .ops = &clk_branch2_ops, 321 }, 322 }, 323 }; 324 325 static struct clk_branch video_cc_mvs0c_clk = { 326 .halt_reg = 0x8064, 327 .halt_check = BRANCH_HALT, 328 .clkr = { 329 .enable_reg = 0x8064, 330 .enable_mask = BIT(0), 331 .hw.init = &(const struct clk_init_data) { 332 .name = "video_cc_mvs0c_clk", 333 .parent_hws = (const struct clk_hw*[]) { 334 &video_cc_mvs0_clk_src.clkr.hw, 335 }, 336 .num_parents = 1, 337 .flags = CLK_SET_RATE_PARENT, 338 .ops = &clk_branch2_ops, 339 }, 340 }, 341 }; 342 343 static struct clk_branch video_cc_mvs0c_shift_clk = { 344 .halt_reg = 0x812c, 345 .halt_check = BRANCH_HALT_VOTED, 346 .clkr = { 347 .enable_reg = 0x812c, 348 .enable_mask = BIT(0), 349 .hw.init = &(const struct clk_init_data) { 350 .name = "video_cc_mvs0c_shift_clk", 351 .parent_hws = (const struct clk_hw*[]) { 352 &video_cc_xo_clk_src.clkr.hw, 353 }, 354 .num_parents = 1, 355 .flags = CLK_SET_RATE_PARENT, 356 .ops = &clk_branch2_ops, 357 }, 358 }, 359 }; 360 361 static struct clk_branch video_cc_mvs1_clk = { 362 .halt_reg = 0x80e0, 363 .halt_check = BRANCH_HALT_VOTED, 364 .hwcg_reg = 0x80e0, 365 .hwcg_bit = 1, 366 .clkr = { 367 .enable_reg = 0x80e0, 368 .enable_mask = BIT(0), 369 .hw.init = &(const struct clk_init_data) { 370 .name = "video_cc_mvs1_clk", 371 .parent_hws = (const struct clk_hw*[]) { 372 &video_cc_mvs1_div_clk_src.clkr.hw, 373 }, 374 .num_parents = 1, 375 .flags = CLK_SET_RATE_PARENT, 376 .ops = &clk_branch2_ops, 377 }, 378 }, 379 }; 380 381 static struct clk_branch video_cc_mvs1_shift_clk = { 382 .halt_reg = 0x8130, 383 .halt_check = BRANCH_HALT_VOTED, 384 .clkr = { 385 .enable_reg = 0x8130, 386 .enable_mask = BIT(0), 387 .hw.init = &(const struct clk_init_data) { 388 .name = "video_cc_mvs1_shift_clk", 389 .parent_hws = (const struct clk_hw*[]) { 390 &video_cc_xo_clk_src.clkr.hw, 391 }, 392 .num_parents = 1, 393 .flags = CLK_SET_RATE_PARENT, 394 .ops = &clk_branch2_ops, 395 }, 396 }, 397 }; 398 399 static struct clk_branch video_cc_mvs1c_clk = { 400 .halt_reg = 0x8090, 401 .halt_check = BRANCH_HALT, 402 .clkr = { 403 .enable_reg = 0x8090, 404 .enable_mask = BIT(0), 405 .hw.init = &(const struct clk_init_data) { 406 .name = "video_cc_mvs1c_clk", 407 .parent_hws = (const struct clk_hw*[]) { 408 &video_cc_mvs1c_div2_div_clk_src.clkr.hw, 409 }, 410 .num_parents = 1, 411 .flags = CLK_SET_RATE_PARENT, 412 .ops = &clk_branch2_ops, 413 }, 414 }, 415 }; 416 417 static struct clk_branch video_cc_mvs1c_shift_clk = { 418 .halt_reg = 0x8134, 419 .halt_check = BRANCH_HALT_VOTED, 420 .clkr = { 421 .enable_reg = 0x8134, 422 .enable_mask = BIT(0), 423 .hw.init = &(const struct clk_init_data) { 424 .name = "video_cc_mvs1c_shift_clk", 425 .parent_hws = (const struct clk_hw*[]) { 426 &video_cc_xo_clk_src.clkr.hw, 427 }, 428 .num_parents = 1, 429 .flags = CLK_SET_RATE_PARENT, 430 .ops = &clk_branch2_ops, 431 }, 432 }, 433 }; 434 435 static struct gdsc video_cc_mvs0c_gdsc = { 436 .gdscr = 0x804c, 437 .en_rest_wait_val = 0x2, 438 .en_few_wait_val = 0x2, 439 .clk_dis_wait_val = 0x6, 440 .pd = { 441 .name = "video_cc_mvs0c_gdsc", 442 }, 443 .pwrsts = PWRSTS_OFF_ON, 444 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 445 }; 446 447 static struct gdsc video_cc_mvs0_gdsc = { 448 .gdscr = 0x80a4, 449 .en_rest_wait_val = 0x2, 450 .en_few_wait_val = 0x2, 451 .clk_dis_wait_val = 0x6, 452 .pd = { 453 .name = "video_cc_mvs0_gdsc", 454 }, 455 .pwrsts = PWRSTS_OFF_ON, 456 .parent = &video_cc_mvs0c_gdsc.pd, 457 .flags = HW_CTRL_TRIGGER | POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 458 }; 459 460 static struct gdsc video_cc_mvs1c_gdsc = { 461 .gdscr = 0x8078, 462 .en_rest_wait_val = 0x2, 463 .en_few_wait_val = 0x2, 464 .clk_dis_wait_val = 0xf, 465 .pd = { 466 .name = "video_cc_mvs1c_gdsc", 467 }, 468 .pwrsts = PWRSTS_OFF_ON, 469 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 470 }; 471 472 static struct gdsc video_cc_mvs1_gdsc = { 473 .gdscr = 0x80cc, 474 .en_rest_wait_val = 0x2, 475 .en_few_wait_val = 0x2, 476 .clk_dis_wait_val = 0xf, 477 .pd = { 478 .name = "video_cc_mvs1_gdsc", 479 }, 480 .pwrsts = PWRSTS_OFF_ON, 481 .parent = &video_cc_mvs1c_gdsc.pd, 482 .flags = HW_CTRL_TRIGGER | POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 483 }; 484 485 static struct clk_regmap *video_cc_x1p42100_clocks[] = { 486 [VIDEO_CC_MVS0_BSE_CLK] = &video_cc_mvs0_bse_clk.clkr, 487 [VIDEO_CC_MVS0_BSE_CLK_SRC] = &video_cc_mvs0_bse_clk_src.clkr, 488 [VIDEO_CC_MVS0_BSE_DIV4_DIV_CLK_SRC] = &video_cc_mvs0_bse_div4_div_clk_src.clkr, 489 [VIDEO_CC_MVS0_CLK] = &video_cc_mvs0_clk.clkr, 490 [VIDEO_CC_MVS0_CLK_SRC] = &video_cc_mvs0_clk_src.clkr, 491 [VIDEO_CC_MVS0_SHIFT_CLK] = &video_cc_mvs0_shift_clk.clkr, 492 [VIDEO_CC_MVS0C_CLK] = &video_cc_mvs0c_clk.clkr, 493 [VIDEO_CC_MVS0C_SHIFT_CLK] = &video_cc_mvs0c_shift_clk.clkr, 494 [VIDEO_CC_MVS1_CLK] = &video_cc_mvs1_clk.clkr, 495 [VIDEO_CC_MVS1_CLK_SRC] = &video_cc_mvs1_clk_src.clkr, 496 [VIDEO_CC_MVS1_DIV_CLK_SRC] = &video_cc_mvs1_div_clk_src.clkr, 497 [VIDEO_CC_MVS1_SHIFT_CLK] = &video_cc_mvs1_shift_clk.clkr, 498 [VIDEO_CC_MVS1C_CLK] = &video_cc_mvs1c_clk.clkr, 499 [VIDEO_CC_MVS1C_DIV2_DIV_CLK_SRC] = &video_cc_mvs1c_div2_div_clk_src.clkr, 500 [VIDEO_CC_MVS1C_SHIFT_CLK] = &video_cc_mvs1c_shift_clk.clkr, 501 [VIDEO_CC_PLL0] = &video_cc_pll0.clkr, 502 [VIDEO_CC_PLL1] = &video_cc_pll1.clkr, 503 [VIDEO_CC_XO_CLK_SRC] = &video_cc_xo_clk_src.clkr, 504 }; 505 506 static struct gdsc *video_cc_x1p42100_gdscs[] = { 507 [VIDEO_CC_MVS0_GDSC] = &video_cc_mvs0_gdsc, 508 [VIDEO_CC_MVS0C_GDSC] = &video_cc_mvs0c_gdsc, 509 [VIDEO_CC_MVS1_GDSC] = &video_cc_mvs1_gdsc, 510 [VIDEO_CC_MVS1C_GDSC] = &video_cc_mvs1c_gdsc, 511 }; 512 513 static const struct qcom_reset_map video_cc_x1p42100_resets[] = { 514 [CVP_VIDEO_CC_INTERFACE_BCR] = { 0x80f0 }, 515 [CVP_VIDEO_CC_MVS0_BCR] = { 0x80a0 }, 516 [CVP_VIDEO_CC_MVS0C_BCR] = { 0x8048 }, 517 [CVP_VIDEO_CC_MVS1_BCR] = { 0x80c8 }, 518 [CVP_VIDEO_CC_MVS1C_BCR] = { 0x8074 }, 519 [VIDEO_CC_MVS0_BSE_BCR] = { 0x816c }, 520 [VIDEO_CC_MVS0C_CLK_ARES] = { 0x8064, 2 }, 521 [VIDEO_CC_MVS1C_CLK_ARES] = { 0x8090, 2 }, 522 [VIDEO_CC_XO_CLK_ARES] = { 0x8124, 2 }, 523 }; 524 525 static struct clk_alpha_pll *video_cc_x1p42100_plls[] = { 526 &video_cc_pll0, 527 &video_cc_pll1, 528 }; 529 530 static u32 video_cc_x1p42100_critical_cbcrs[] = { 531 0x80f4, /* VIDEO_CC_AHB_CLK */ 532 0x8150, /* VIDEO_CC_SLEEP_CLK */ 533 0x8124, /* VIDEO_CC_XO_CLK */ 534 }; 535 536 static const struct regmap_config video_cc_x1p42100_regmap_config = { 537 .reg_bits = 32, 538 .reg_stride = 4, 539 .val_bits = 32, 540 .max_register = 0x9f54, 541 .fast_io = true, 542 }; 543 544 static struct qcom_cc_driver_data video_cc_x1p42100_driver_data = { 545 .alpha_plls = video_cc_x1p42100_plls, 546 .num_alpha_plls = ARRAY_SIZE(video_cc_x1p42100_plls), 547 .clk_cbcrs = video_cc_x1p42100_critical_cbcrs, 548 .num_clk_cbcrs = ARRAY_SIZE(video_cc_x1p42100_critical_cbcrs), 549 }; 550 551 static const struct qcom_cc_desc video_cc_x1p42100_desc = { 552 .config = &video_cc_x1p42100_regmap_config, 553 .clks = video_cc_x1p42100_clocks, 554 .num_clks = ARRAY_SIZE(video_cc_x1p42100_clocks), 555 .resets = video_cc_x1p42100_resets, 556 .num_resets = ARRAY_SIZE(video_cc_x1p42100_resets), 557 .gdscs = video_cc_x1p42100_gdscs, 558 .num_gdscs = ARRAY_SIZE(video_cc_x1p42100_gdscs), 559 .use_rpm = true, 560 .driver_data = &video_cc_x1p42100_driver_data, 561 }; 562 563 static const struct of_device_id video_cc_x1p42100_match_table[] = { 564 { .compatible = "qcom,x1p42100-videocc" }, 565 { } 566 }; 567 MODULE_DEVICE_TABLE(of, video_cc_x1p42100_match_table); 568 569 static int video_cc_x1p42100_probe(struct platform_device *pdev) 570 { 571 return qcom_cc_probe(pdev, &video_cc_x1p42100_desc); 572 } 573 574 static struct platform_driver video_cc_x1p42100_driver = { 575 .probe = video_cc_x1p42100_probe, 576 .driver = { 577 .name = "videocc-x1p42100", 578 .of_match_table = video_cc_x1p42100_match_table, 579 }, 580 }; 581 582 module_platform_driver(video_cc_x1p42100_driver); 583 584 MODULE_DESCRIPTION("QTI VIDEOCC X1P42100 Driver"); 585 MODULE_LICENSE("GPL"); 586