1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 6 #include <linux/clk-provider.h> 7 #include <linux/module.h> 8 #include <linux/of.h> 9 #include <linux/platform_device.h> 10 #include <linux/regmap.h> 11 12 #include <dt-bindings/clock/qcom,qcs615-videocc.h> 13 14 #include "clk-alpha-pll.h" 15 #include "clk-branch.h" 16 #include "clk-pll.h" 17 #include "clk-rcg.h" 18 #include "clk-regmap.h" 19 #include "clk-regmap-divider.h" 20 #include "clk-regmap-mux.h" 21 #include "common.h" 22 #include "gdsc.h" 23 #include "reset.h" 24 25 enum { 26 DT_BI_TCXO, 27 DT_SLEEP_CLK, 28 }; 29 30 enum { 31 P_BI_TCXO, 32 P_SLEEP_CLK, 33 P_VIDEO_PLL0_OUT_AUX, 34 P_VIDEO_PLL0_OUT_AUX2, 35 P_VIDEO_PLL0_OUT_MAIN, 36 }; 37 38 static const struct pll_vco video_cc_pll0_vco[] = { 39 { 500000000, 1000000000, 2 }, 40 }; 41 42 /* 600MHz configuration VCO - 2 */ 43 static struct alpha_pll_config video_pll0_config = { 44 .l = 0x1f, 45 .alpha_hi = 0x40, 46 .alpha = 0x00, 47 .alpha_en_mask = BIT(24), 48 .vco_val = BIT(21), 49 .vco_mask = GENMASK(21, 20), 50 .main_output_mask = BIT(0), 51 .config_ctl_val = 0x4001055b, 52 .test_ctl_hi_val = 0x1, 53 .test_ctl_hi_mask = 0x1, 54 }; 55 56 static struct clk_alpha_pll video_pll0 = { 57 .offset = 0x42c, 58 .config = &video_pll0_config, 59 .vco_table = video_cc_pll0_vco, 60 .num_vco = ARRAY_SIZE(video_cc_pll0_vco), 61 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 62 .clkr = { 63 .hw.init = &(const struct clk_init_data) { 64 .name = "video_pll0", 65 .parent_data = &(const struct clk_parent_data) { 66 .index = DT_BI_TCXO, 67 }, 68 .num_parents = 1, 69 .ops = &clk_alpha_pll_slew_ops, 70 }, 71 }, 72 }; 73 74 static const struct parent_map video_cc_parent_map_0[] = { 75 { P_SLEEP_CLK, 0 }, 76 }; 77 78 static const struct clk_parent_data video_cc_parent_data_0_ao[] = { 79 { .index = DT_SLEEP_CLK }, 80 }; 81 82 static const struct parent_map video_cc_parent_map_1[] = { 83 { P_BI_TCXO, 0 }, 84 { P_VIDEO_PLL0_OUT_MAIN, 1 }, 85 { P_VIDEO_PLL0_OUT_AUX, 2 }, 86 { P_VIDEO_PLL0_OUT_AUX2, 3 }, 87 }; 88 89 static const struct clk_parent_data video_cc_parent_data_1[] = { 90 { .index = DT_BI_TCXO }, 91 { .hw = &video_pll0.clkr.hw }, 92 { .hw = &video_pll0.clkr.hw }, 93 { .hw = &video_pll0.clkr.hw }, 94 }; 95 96 static const struct freq_tbl ftbl_video_cc_sleep_clk_src[] = { 97 F(32000, P_SLEEP_CLK, 1, 0, 0), 98 { } 99 }; 100 101 static struct clk_rcg2 video_cc_sleep_clk_src = { 102 .cmd_rcgr = 0xaf8, 103 .mnd_width = 0, 104 .hid_width = 5, 105 .parent_map = video_cc_parent_map_0, 106 .freq_tbl = ftbl_video_cc_sleep_clk_src, 107 .clkr.hw.init = &(const struct clk_init_data) { 108 .name = "video_cc_sleep_clk_src", 109 .parent_data = video_cc_parent_data_0_ao, 110 .num_parents = ARRAY_SIZE(video_cc_parent_data_0_ao), 111 .ops = &clk_rcg2_ops, 112 }, 113 }; 114 115 static const struct freq_tbl ftbl_video_cc_venus_clk_src[] = { 116 F(19200000, P_BI_TCXO, 1, 0, 0), 117 F(133333333, P_VIDEO_PLL0_OUT_MAIN, 4.5, 0, 0), 118 F(240000000, P_VIDEO_PLL0_OUT_MAIN, 2.5, 0, 0), 119 F(300000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0), 120 F(380000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0), 121 F(410000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0), 122 F(460000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0), 123 { } 124 }; 125 126 static struct clk_rcg2 video_cc_venus_clk_src = { 127 .cmd_rcgr = 0x7f0, 128 .mnd_width = 0, 129 .hid_width = 5, 130 .parent_map = video_cc_parent_map_1, 131 .freq_tbl = ftbl_video_cc_venus_clk_src, 132 .clkr.hw.init = &(const struct clk_init_data) { 133 .name = "video_cc_venus_clk_src", 134 .parent_data = video_cc_parent_data_1, 135 .num_parents = ARRAY_SIZE(video_cc_parent_data_1), 136 .flags = CLK_SET_RATE_PARENT, 137 .ops = &clk_rcg2_shared_ops, 138 }, 139 }; 140 141 static struct clk_branch video_cc_sleep_clk = { 142 .halt_reg = 0xb18, 143 .halt_check = BRANCH_HALT, 144 .clkr = { 145 .enable_reg = 0xb18, 146 .enable_mask = BIT(0), 147 .hw.init = &(struct clk_init_data){ 148 .name = "video_cc_sleep_clk", 149 .parent_data = &(const struct clk_parent_data){ 150 .hw = &video_cc_sleep_clk_src.clkr.hw, 151 }, 152 .num_parents = 1, 153 .flags = CLK_SET_RATE_PARENT, 154 .ops = &clk_branch2_ops, 155 }, 156 }, 157 }; 158 159 static struct clk_branch video_cc_vcodec0_axi_clk = { 160 .halt_reg = 0x8f0, 161 .halt_check = BRANCH_HALT, 162 .clkr = { 163 .enable_reg = 0x8f0, 164 .enable_mask = BIT(0), 165 .hw.init = &(const struct clk_init_data) { 166 .name = "video_cc_vcodec0_axi_clk", 167 .ops = &clk_branch2_ops, 168 }, 169 }, 170 }; 171 172 static struct clk_branch video_cc_vcodec0_core_clk = { 173 .halt_reg = 0x890, 174 .halt_check = BRANCH_HALT_VOTED, 175 .clkr = { 176 .enable_reg = 0x890, 177 .enable_mask = BIT(0), 178 .hw.init = &(const struct clk_init_data) { 179 .name = "video_cc_vcodec0_core_clk", 180 .parent_hws = (const struct clk_hw*[]) { 181 &video_cc_venus_clk_src.clkr.hw, 182 }, 183 .num_parents = 1, 184 .flags = CLK_SET_RATE_PARENT, 185 .ops = &clk_branch2_ops, 186 }, 187 }, 188 }; 189 190 static struct clk_branch video_cc_venus_ahb_clk = { 191 .halt_reg = 0x9b0, 192 .halt_check = BRANCH_HALT, 193 .clkr = { 194 .enable_reg = 0x9b0, 195 .enable_mask = BIT(0), 196 .hw.init = &(const struct clk_init_data) { 197 .name = "video_cc_venus_ahb_clk", 198 .ops = &clk_branch2_ops, 199 }, 200 }, 201 }; 202 203 static struct clk_branch video_cc_venus_ctl_axi_clk = { 204 .halt_reg = 0x8d0, 205 .halt_check = BRANCH_HALT, 206 .clkr = { 207 .enable_reg = 0x8d0, 208 .enable_mask = BIT(0), 209 .hw.init = &(const struct clk_init_data) { 210 .name = "video_cc_venus_ctl_axi_clk", 211 .ops = &clk_branch2_ops, 212 }, 213 }, 214 }; 215 216 static struct clk_branch video_cc_venus_ctl_core_clk = { 217 .halt_reg = 0x850, 218 .halt_check = BRANCH_HALT, 219 .clkr = { 220 .enable_reg = 0x850, 221 .enable_mask = BIT(0), 222 .hw.init = &(const struct clk_init_data) { 223 .name = "video_cc_venus_ctl_core_clk", 224 .parent_hws = (const struct clk_hw*[]) { 225 &video_cc_venus_clk_src.clkr.hw, 226 }, 227 .num_parents = 1, 228 .flags = CLK_SET_RATE_PARENT, 229 .ops = &clk_branch2_ops, 230 }, 231 }, 232 }; 233 234 static struct gdsc vcodec0_gdsc = { 235 .gdscr = 0x874, 236 .en_rest_wait_val = 0x2, 237 .en_few_wait_val = 0x2, 238 .clk_dis_wait_val = 0x6, 239 .pd = { 240 .name = "vcodec0_gdsc", 241 }, 242 .pwrsts = PWRSTS_OFF_ON, 243 .flags = HW_CTRL_TRIGGER | POLL_CFG_GDSCR, 244 }; 245 246 static struct gdsc venus_gdsc = { 247 .gdscr = 0x814, 248 .en_rest_wait_val = 0x2, 249 .en_few_wait_val = 0x2, 250 .clk_dis_wait_val = 0x6, 251 .pd = { 252 .name = "venus_gdsc", 253 }, 254 .pwrsts = PWRSTS_OFF_ON, 255 .flags = POLL_CFG_GDSCR, 256 }; 257 258 static struct clk_regmap *video_cc_qcs615_clocks[] = { 259 [VIDEO_CC_SLEEP_CLK] = &video_cc_sleep_clk.clkr, 260 [VIDEO_CC_SLEEP_CLK_SRC] = &video_cc_sleep_clk_src.clkr, 261 [VIDEO_CC_VCODEC0_AXI_CLK] = &video_cc_vcodec0_axi_clk.clkr, 262 [VIDEO_CC_VCODEC0_CORE_CLK] = &video_cc_vcodec0_core_clk.clkr, 263 [VIDEO_CC_VENUS_AHB_CLK] = &video_cc_venus_ahb_clk.clkr, 264 [VIDEO_CC_VENUS_CLK_SRC] = &video_cc_venus_clk_src.clkr, 265 [VIDEO_CC_VENUS_CTL_AXI_CLK] = &video_cc_venus_ctl_axi_clk.clkr, 266 [VIDEO_CC_VENUS_CTL_CORE_CLK] = &video_cc_venus_ctl_core_clk.clkr, 267 [VIDEO_PLL0] = &video_pll0.clkr, 268 }; 269 270 static struct gdsc *video_cc_qcs615_gdscs[] = { 271 [VCODEC0_GDSC] = &vcodec0_gdsc, 272 [VENUS_GDSC] = &venus_gdsc, 273 }; 274 275 static const struct qcom_reset_map video_cc_qcs615_resets[] = { 276 [VIDEO_CC_INTERFACE_BCR] = { 0x8b0 }, 277 [VIDEO_CC_VCODEC0_BCR] = { 0x870 }, 278 [VIDEO_CC_VENUS_BCR] = { 0x810 }, 279 }; 280 281 static struct clk_alpha_pll *video_cc_qcs615_plls[] = { 282 &video_pll0, 283 }; 284 285 static const u32 video_cc_qcs615_critical_cbcrs[] = { 286 0xab8, /* VIDEO_CC_XO_CLK */ 287 }; 288 289 static const struct regmap_config video_cc_qcs615_regmap_config = { 290 .reg_bits = 32, 291 .reg_stride = 4, 292 .val_bits = 32, 293 .max_register = 0xb94, 294 .fast_io = true, 295 }; 296 297 static const struct qcom_cc_driver_data video_cc_qcs615_driver_data = { 298 .alpha_plls = video_cc_qcs615_plls, 299 .num_alpha_plls = ARRAY_SIZE(video_cc_qcs615_plls), 300 .clk_cbcrs = video_cc_qcs615_critical_cbcrs, 301 .num_clk_cbcrs = ARRAY_SIZE(video_cc_qcs615_critical_cbcrs), 302 }; 303 304 static const struct qcom_cc_desc video_cc_qcs615_desc = { 305 .config = &video_cc_qcs615_regmap_config, 306 .clks = video_cc_qcs615_clocks, 307 .num_clks = ARRAY_SIZE(video_cc_qcs615_clocks), 308 .resets = video_cc_qcs615_resets, 309 .num_resets = ARRAY_SIZE(video_cc_qcs615_resets), 310 .gdscs = video_cc_qcs615_gdscs, 311 .num_gdscs = ARRAY_SIZE(video_cc_qcs615_gdscs), 312 .driver_data = &video_cc_qcs615_driver_data, 313 }; 314 315 static const struct of_device_id video_cc_qcs615_match_table[] = { 316 { .compatible = "qcom,qcs615-videocc" }, 317 { } 318 }; 319 MODULE_DEVICE_TABLE(of, video_cc_qcs615_match_table); 320 321 static int video_cc_qcs615_probe(struct platform_device *pdev) 322 { 323 return qcom_cc_probe(pdev, &video_cc_qcs615_desc); 324 } 325 326 static struct platform_driver video_cc_qcs615_driver = { 327 .probe = video_cc_qcs615_probe, 328 .driver = { 329 .name = "videocc-qcs615", 330 .of_match_table = video_cc_qcs615_match_table, 331 }, 332 }; 333 334 module_platform_driver(video_cc_qcs615_driver); 335 336 MODULE_DESCRIPTION("QTI VIDEOCC QCS615 Driver"); 337 MODULE_LICENSE("GPL"); 338