1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 6 #include <linux/clk-provider.h> 7 #include <linux/module.h> 8 #include <linux/mod_devicetable.h> 9 #include <linux/of.h> 10 #include <linux/platform_device.h> 11 #include <linux/regmap.h> 12 13 #include <dt-bindings/clock/qcom,qcs615-videocc.h> 14 15 #include "clk-alpha-pll.h" 16 #include "clk-branch.h" 17 #include "clk-pll.h" 18 #include "clk-rcg.h" 19 #include "clk-regmap.h" 20 #include "clk-regmap-divider.h" 21 #include "clk-regmap-mux.h" 22 #include "common.h" 23 #include "gdsc.h" 24 #include "reset.h" 25 26 enum { 27 DT_BI_TCXO, 28 DT_SLEEP_CLK, 29 }; 30 31 enum { 32 P_BI_TCXO, 33 P_SLEEP_CLK, 34 P_VIDEO_PLL0_OUT_AUX, 35 P_VIDEO_PLL0_OUT_AUX2, 36 P_VIDEO_PLL0_OUT_MAIN, 37 }; 38 39 static const struct pll_vco video_cc_pll0_vco[] = { 40 { 500000000, 1000000000, 2 }, 41 }; 42 43 /* 600MHz configuration VCO - 2 */ 44 static struct alpha_pll_config video_pll0_config = { 45 .l = 0x1f, 46 .alpha_hi = 0x40, 47 .alpha = 0x00, 48 .alpha_en_mask = BIT(24), 49 .vco_val = BIT(21), 50 .vco_mask = GENMASK(21, 20), 51 .main_output_mask = BIT(0), 52 .config_ctl_val = 0x4001055b, 53 .test_ctl_hi_val = 0x1, 54 .test_ctl_hi_mask = 0x1, 55 }; 56 57 static struct clk_alpha_pll video_pll0 = { 58 .offset = 0x42c, 59 .config = &video_pll0_config, 60 .vco_table = video_cc_pll0_vco, 61 .num_vco = ARRAY_SIZE(video_cc_pll0_vco), 62 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 63 .clkr = { 64 .hw.init = &(const struct clk_init_data) { 65 .name = "video_pll0", 66 .parent_data = &(const struct clk_parent_data) { 67 .index = DT_BI_TCXO, 68 }, 69 .num_parents = 1, 70 .ops = &clk_alpha_pll_slew_ops, 71 }, 72 }, 73 }; 74 75 static const struct parent_map video_cc_parent_map_0[] = { 76 { P_SLEEP_CLK, 0 }, 77 }; 78 79 static const struct clk_parent_data video_cc_parent_data_0_ao[] = { 80 { .index = DT_SLEEP_CLK }, 81 }; 82 83 static const struct parent_map video_cc_parent_map_1[] = { 84 { P_BI_TCXO, 0 }, 85 { P_VIDEO_PLL0_OUT_MAIN, 1 }, 86 { P_VIDEO_PLL0_OUT_AUX, 2 }, 87 { P_VIDEO_PLL0_OUT_AUX2, 3 }, 88 }; 89 90 static const struct clk_parent_data video_cc_parent_data_1[] = { 91 { .index = DT_BI_TCXO }, 92 { .hw = &video_pll0.clkr.hw }, 93 { .hw = &video_pll0.clkr.hw }, 94 { .hw = &video_pll0.clkr.hw }, 95 }; 96 97 static const struct freq_tbl ftbl_video_cc_sleep_clk_src[] = { 98 F(32000, P_SLEEP_CLK, 1, 0, 0), 99 { } 100 }; 101 102 static struct clk_rcg2 video_cc_sleep_clk_src = { 103 .cmd_rcgr = 0xaf8, 104 .mnd_width = 0, 105 .hid_width = 5, 106 .parent_map = video_cc_parent_map_0, 107 .freq_tbl = ftbl_video_cc_sleep_clk_src, 108 .clkr.hw.init = &(const struct clk_init_data) { 109 .name = "video_cc_sleep_clk_src", 110 .parent_data = video_cc_parent_data_0_ao, 111 .num_parents = ARRAY_SIZE(video_cc_parent_data_0_ao), 112 .ops = &clk_rcg2_ops, 113 }, 114 }; 115 116 static const struct freq_tbl ftbl_video_cc_venus_clk_src[] = { 117 F(19200000, P_BI_TCXO, 1, 0, 0), 118 F(133333333, P_VIDEO_PLL0_OUT_MAIN, 4.5, 0, 0), 119 F(240000000, P_VIDEO_PLL0_OUT_MAIN, 2.5, 0, 0), 120 F(300000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0), 121 F(380000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0), 122 F(410000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0), 123 F(460000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0), 124 { } 125 }; 126 127 static struct clk_rcg2 video_cc_venus_clk_src = { 128 .cmd_rcgr = 0x7f0, 129 .mnd_width = 0, 130 .hid_width = 5, 131 .parent_map = video_cc_parent_map_1, 132 .freq_tbl = ftbl_video_cc_venus_clk_src, 133 .clkr.hw.init = &(const struct clk_init_data) { 134 .name = "video_cc_venus_clk_src", 135 .parent_data = video_cc_parent_data_1, 136 .num_parents = ARRAY_SIZE(video_cc_parent_data_1), 137 .flags = CLK_SET_RATE_PARENT, 138 .ops = &clk_rcg2_shared_ops, 139 }, 140 }; 141 142 static struct clk_branch video_cc_sleep_clk = { 143 .halt_reg = 0xb18, 144 .halt_check = BRANCH_HALT, 145 .clkr = { 146 .enable_reg = 0xb18, 147 .enable_mask = BIT(0), 148 .hw.init = &(struct clk_init_data){ 149 .name = "video_cc_sleep_clk", 150 .parent_data = &(const struct clk_parent_data){ 151 .hw = &video_cc_sleep_clk_src.clkr.hw, 152 }, 153 .num_parents = 1, 154 .flags = CLK_SET_RATE_PARENT, 155 .ops = &clk_branch2_ops, 156 }, 157 }, 158 }; 159 160 static struct clk_branch video_cc_vcodec0_axi_clk = { 161 .halt_reg = 0x8f0, 162 .halt_check = BRANCH_HALT, 163 .clkr = { 164 .enable_reg = 0x8f0, 165 .enable_mask = BIT(0), 166 .hw.init = &(const struct clk_init_data) { 167 .name = "video_cc_vcodec0_axi_clk", 168 .ops = &clk_branch2_ops, 169 }, 170 }, 171 }; 172 173 static struct clk_branch video_cc_vcodec0_core_clk = { 174 .halt_reg = 0x890, 175 .halt_check = BRANCH_HALT_VOTED, 176 .clkr = { 177 .enable_reg = 0x890, 178 .enable_mask = BIT(0), 179 .hw.init = &(const struct clk_init_data) { 180 .name = "video_cc_vcodec0_core_clk", 181 .parent_hws = (const struct clk_hw*[]) { 182 &video_cc_venus_clk_src.clkr.hw, 183 }, 184 .num_parents = 1, 185 .flags = CLK_SET_RATE_PARENT, 186 .ops = &clk_branch2_ops, 187 }, 188 }, 189 }; 190 191 static struct clk_branch video_cc_venus_ahb_clk = { 192 .halt_reg = 0x9b0, 193 .halt_check = BRANCH_HALT, 194 .clkr = { 195 .enable_reg = 0x9b0, 196 .enable_mask = BIT(0), 197 .hw.init = &(const struct clk_init_data) { 198 .name = "video_cc_venus_ahb_clk", 199 .ops = &clk_branch2_ops, 200 }, 201 }, 202 }; 203 204 static struct clk_branch video_cc_venus_ctl_axi_clk = { 205 .halt_reg = 0x8d0, 206 .halt_check = BRANCH_HALT, 207 .clkr = { 208 .enable_reg = 0x8d0, 209 .enable_mask = BIT(0), 210 .hw.init = &(const struct clk_init_data) { 211 .name = "video_cc_venus_ctl_axi_clk", 212 .ops = &clk_branch2_ops, 213 }, 214 }, 215 }; 216 217 static struct clk_branch video_cc_venus_ctl_core_clk = { 218 .halt_reg = 0x850, 219 .halt_check = BRANCH_HALT, 220 .clkr = { 221 .enable_reg = 0x850, 222 .enable_mask = BIT(0), 223 .hw.init = &(const struct clk_init_data) { 224 .name = "video_cc_venus_ctl_core_clk", 225 .parent_hws = (const struct clk_hw*[]) { 226 &video_cc_venus_clk_src.clkr.hw, 227 }, 228 .num_parents = 1, 229 .flags = CLK_SET_RATE_PARENT, 230 .ops = &clk_branch2_ops, 231 }, 232 }, 233 }; 234 235 static struct gdsc vcodec0_gdsc = { 236 .gdscr = 0x874, 237 .en_rest_wait_val = 0x2, 238 .en_few_wait_val = 0x2, 239 .clk_dis_wait_val = 0x6, 240 .pd = { 241 .name = "vcodec0_gdsc", 242 }, 243 .pwrsts = PWRSTS_OFF_ON, 244 .flags = HW_CTRL_TRIGGER | POLL_CFG_GDSCR, 245 }; 246 247 static struct gdsc venus_gdsc = { 248 .gdscr = 0x814, 249 .en_rest_wait_val = 0x2, 250 .en_few_wait_val = 0x2, 251 .clk_dis_wait_val = 0x6, 252 .pd = { 253 .name = "venus_gdsc", 254 }, 255 .pwrsts = PWRSTS_OFF_ON, 256 .flags = POLL_CFG_GDSCR, 257 }; 258 259 static struct clk_regmap *video_cc_qcs615_clocks[] = { 260 [VIDEO_CC_SLEEP_CLK] = &video_cc_sleep_clk.clkr, 261 [VIDEO_CC_SLEEP_CLK_SRC] = &video_cc_sleep_clk_src.clkr, 262 [VIDEO_CC_VCODEC0_AXI_CLK] = &video_cc_vcodec0_axi_clk.clkr, 263 [VIDEO_CC_VCODEC0_CORE_CLK] = &video_cc_vcodec0_core_clk.clkr, 264 [VIDEO_CC_VENUS_AHB_CLK] = &video_cc_venus_ahb_clk.clkr, 265 [VIDEO_CC_VENUS_CLK_SRC] = &video_cc_venus_clk_src.clkr, 266 [VIDEO_CC_VENUS_CTL_AXI_CLK] = &video_cc_venus_ctl_axi_clk.clkr, 267 [VIDEO_CC_VENUS_CTL_CORE_CLK] = &video_cc_venus_ctl_core_clk.clkr, 268 [VIDEO_PLL0] = &video_pll0.clkr, 269 }; 270 271 static struct gdsc *video_cc_qcs615_gdscs[] = { 272 [VCODEC0_GDSC] = &vcodec0_gdsc, 273 [VENUS_GDSC] = &venus_gdsc, 274 }; 275 276 static const struct qcom_reset_map video_cc_qcs615_resets[] = { 277 [VIDEO_CC_INTERFACE_BCR] = { 0x8b0 }, 278 [VIDEO_CC_VCODEC0_BCR] = { 0x870 }, 279 [VIDEO_CC_VENUS_BCR] = { 0x810 }, 280 }; 281 282 static struct clk_alpha_pll *video_cc_qcs615_plls[] = { 283 &video_pll0, 284 }; 285 286 static u32 video_cc_qcs615_critical_cbcrs[] = { 287 0xab8, /* VIDEO_CC_XO_CLK */ 288 }; 289 290 static const struct regmap_config video_cc_qcs615_regmap_config = { 291 .reg_bits = 32, 292 .reg_stride = 4, 293 .val_bits = 32, 294 .max_register = 0xb94, 295 .fast_io = true, 296 }; 297 298 static struct qcom_cc_driver_data video_cc_qcs615_driver_data = { 299 .alpha_plls = video_cc_qcs615_plls, 300 .num_alpha_plls = ARRAY_SIZE(video_cc_qcs615_plls), 301 .clk_cbcrs = video_cc_qcs615_critical_cbcrs, 302 .num_clk_cbcrs = ARRAY_SIZE(video_cc_qcs615_critical_cbcrs), 303 }; 304 305 static const struct qcom_cc_desc video_cc_qcs615_desc = { 306 .config = &video_cc_qcs615_regmap_config, 307 .clks = video_cc_qcs615_clocks, 308 .num_clks = ARRAY_SIZE(video_cc_qcs615_clocks), 309 .resets = video_cc_qcs615_resets, 310 .num_resets = ARRAY_SIZE(video_cc_qcs615_resets), 311 .gdscs = video_cc_qcs615_gdscs, 312 .num_gdscs = ARRAY_SIZE(video_cc_qcs615_gdscs), 313 .driver_data = &video_cc_qcs615_driver_data, 314 }; 315 316 static const struct of_device_id video_cc_qcs615_match_table[] = { 317 { .compatible = "qcom,qcs615-videocc" }, 318 { } 319 }; 320 MODULE_DEVICE_TABLE(of, video_cc_qcs615_match_table); 321 322 static int video_cc_qcs615_probe(struct platform_device *pdev) 323 { 324 return qcom_cc_probe(pdev, &video_cc_qcs615_desc); 325 } 326 327 static struct platform_driver video_cc_qcs615_driver = { 328 .probe = video_cc_qcs615_probe, 329 .driver = { 330 .name = "videocc-qcs615", 331 .of_match_table = video_cc_qcs615_match_table, 332 }, 333 }; 334 335 module_platform_driver(video_cc_qcs615_driver); 336 337 MODULE_DESCRIPTION("QTI VIDEOCC QCS615 Driver"); 338 MODULE_LICENSE("GPL"); 339