1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 4 */ 5 6 #include <linux/clk-provider.h> 7 #include <linux/mod_devicetable.h> 8 #include <linux/module.h> 9 #include <linux/platform_device.h> 10 #include <linux/regmap.h> 11 12 #include <dt-bindings/clock/qcom,nord-segcc.h> 13 14 #include "clk-alpha-pll.h" 15 #include "clk-branch.h" 16 #include "clk-pll.h" 17 #include "clk-rcg.h" 18 #include "clk-regmap.h" 19 #include "clk-regmap-divider.h" 20 #include "common.h" 21 #include "gdsc.h" 22 #include "reset.h" 23 24 enum { 25 DT_BI_TCXO, 26 DT_SLEEP_CLK, 27 }; 28 29 enum { 30 P_BI_TCXO, 31 P_SE_GCC_GPLL0_OUT_EVEN, 32 P_SE_GCC_GPLL0_OUT_MAIN, 33 P_SE_GCC_GPLL2_OUT_MAIN, 34 P_SE_GCC_GPLL4_OUT_MAIN, 35 P_SE_GCC_GPLL5_OUT_MAIN, 36 P_SLEEP_CLK, 37 }; 38 39 static struct clk_alpha_pll se_gcc_gpll0 = { 40 .offset = 0x0, 41 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 42 .clkr = { 43 .enable_reg = 0x0, 44 .enable_mask = BIT(0), 45 .hw.init = &(const struct clk_init_data) { 46 .name = "se_gcc_gpll0", 47 .parent_data = &(const struct clk_parent_data) { 48 .index = DT_BI_TCXO, 49 }, 50 .num_parents = 1, 51 .ops = &clk_alpha_pll_fixed_lucid_ole_ops, 52 }, 53 }, 54 }; 55 56 static const struct clk_div_table post_div_table_se_gcc_gpll0_out_even[] = { 57 { 0x1, 2 }, 58 { } 59 }; 60 61 static struct clk_alpha_pll_postdiv se_gcc_gpll0_out_even = { 62 .offset = 0x0, 63 .post_div_shift = 10, 64 .post_div_table = post_div_table_se_gcc_gpll0_out_even, 65 .num_post_div = ARRAY_SIZE(post_div_table_se_gcc_gpll0_out_even), 66 .width = 4, 67 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 68 .clkr.hw.init = &(const struct clk_init_data) { 69 .name = "se_gcc_gpll0_out_even", 70 .parent_hws = (const struct clk_hw*[]) { 71 &se_gcc_gpll0.clkr.hw, 72 }, 73 .num_parents = 1, 74 .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, 75 }, 76 }; 77 78 static struct clk_alpha_pll se_gcc_gpll2 = { 79 .offset = 0x2000, 80 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 81 .clkr = { 82 .enable_reg = 0x0, 83 .enable_mask = BIT(2), 84 .hw.init = &(const struct clk_init_data) { 85 .name = "se_gcc_gpll2", 86 .parent_data = &(const struct clk_parent_data) { 87 .index = DT_BI_TCXO, 88 }, 89 .num_parents = 1, 90 .ops = &clk_alpha_pll_fixed_lucid_ole_ops, 91 }, 92 }, 93 }; 94 95 static struct clk_alpha_pll se_gcc_gpll4 = { 96 .offset = 0x4000, 97 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 98 .clkr = { 99 .enable_reg = 0x0, 100 .enable_mask = BIT(4), 101 .hw.init = &(const struct clk_init_data) { 102 .name = "se_gcc_gpll4", 103 .parent_data = &(const struct clk_parent_data) { 104 .index = DT_BI_TCXO, 105 }, 106 .num_parents = 1, 107 .ops = &clk_alpha_pll_fixed_lucid_ole_ops, 108 }, 109 }, 110 }; 111 112 static struct clk_alpha_pll se_gcc_gpll5 = { 113 .offset = 0x5000, 114 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 115 .clkr = { 116 .enable_reg = 0x0, 117 .enable_mask = BIT(5), 118 .hw.init = &(const struct clk_init_data) { 119 .name = "se_gcc_gpll5", 120 .parent_data = &(const struct clk_parent_data) { 121 .index = DT_BI_TCXO, 122 }, 123 .num_parents = 1, 124 .ops = &clk_alpha_pll_fixed_lucid_ole_ops, 125 }, 126 }, 127 }; 128 129 static const struct parent_map se_gcc_parent_map_0[] = { 130 { P_BI_TCXO, 0 }, 131 { P_SE_GCC_GPLL0_OUT_MAIN, 1 }, 132 { P_SE_GCC_GPLL0_OUT_EVEN, 2 }, 133 }; 134 135 static const struct clk_parent_data se_gcc_parent_data_0[] = { 136 { .index = DT_BI_TCXO }, 137 { .hw = &se_gcc_gpll0.clkr.hw }, 138 { .hw = &se_gcc_gpll0_out_even.clkr.hw }, 139 }; 140 141 static const struct parent_map se_gcc_parent_map_1[] = { 142 { P_BI_TCXO, 0 }, 143 { P_SE_GCC_GPLL0_OUT_MAIN, 1 }, 144 }; 145 146 static const struct clk_parent_data se_gcc_parent_data_1[] = { 147 { .index = DT_BI_TCXO }, 148 { .hw = &se_gcc_gpll0.clkr.hw }, 149 }; 150 151 static const struct parent_map se_gcc_parent_map_2[] = { 152 { P_BI_TCXO, 0 }, 153 { P_SE_GCC_GPLL0_OUT_MAIN, 1 }, 154 { P_SLEEP_CLK, 5 }, 155 }; 156 157 static const struct clk_parent_data se_gcc_parent_data_2[] = { 158 { .index = DT_BI_TCXO }, 159 { .hw = &se_gcc_gpll0.clkr.hw }, 160 { .index = DT_SLEEP_CLK }, 161 }; 162 163 static const struct parent_map se_gcc_parent_map_3[] = { 164 { P_BI_TCXO, 0 }, 165 { P_SE_GCC_GPLL0_OUT_MAIN, 1 }, 166 { P_SE_GCC_GPLL5_OUT_MAIN, 3 }, 167 { P_SE_GCC_GPLL4_OUT_MAIN, 5 }, 168 { P_SE_GCC_GPLL2_OUT_MAIN, 6 }, 169 }; 170 171 static const struct clk_parent_data se_gcc_parent_data_3[] = { 172 { .index = DT_BI_TCXO }, 173 { .hw = &se_gcc_gpll0.clkr.hw }, 174 { .hw = &se_gcc_gpll5.clkr.hw }, 175 { .hw = &se_gcc_gpll4.clkr.hw }, 176 { .hw = &se_gcc_gpll2.clkr.hw }, 177 }; 178 179 static const struct parent_map se_gcc_parent_map_4[] = { 180 { P_BI_TCXO, 0 }, 181 { P_SE_GCC_GPLL0_OUT_MAIN, 1 }, 182 { P_SE_GCC_GPLL0_OUT_EVEN, 2 }, 183 { P_SLEEP_CLK, 5 }, 184 }; 185 186 static const struct clk_parent_data se_gcc_parent_data_4[] = { 187 { .index = DT_BI_TCXO }, 188 { .hw = &se_gcc_gpll0.clkr.hw }, 189 { .hw = &se_gcc_gpll0_out_even.clkr.hw }, 190 { .index = DT_SLEEP_CLK }, 191 }; 192 193 static const struct freq_tbl ftbl_se_gcc_eee_emac0_clk_src[] = { 194 F(66666667, P_SE_GCC_GPLL0_OUT_MAIN, 9, 0, 0), 195 F(100000000, P_SE_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 196 { } 197 }; 198 199 static struct clk_rcg2 se_gcc_eee_emac0_clk_src = { 200 .cmd_rcgr = 0x240b8, 201 .mnd_width = 16, 202 .hid_width = 5, 203 .parent_map = se_gcc_parent_map_2, 204 .freq_tbl = ftbl_se_gcc_eee_emac0_clk_src, 205 .hw_clk_ctrl = true, 206 .clkr.hw.init = &(const struct clk_init_data) { 207 .name = "se_gcc_eee_emac0_clk_src", 208 .parent_data = se_gcc_parent_data_2, 209 .num_parents = ARRAY_SIZE(se_gcc_parent_data_2), 210 .flags = CLK_SET_RATE_PARENT, 211 .ops = &clk_rcg2_shared_ops, 212 }, 213 }; 214 215 static struct clk_rcg2 se_gcc_eee_emac1_clk_src = { 216 .cmd_rcgr = 0x250b8, 217 .mnd_width = 16, 218 .hid_width = 5, 219 .parent_map = se_gcc_parent_map_2, 220 .freq_tbl = ftbl_se_gcc_eee_emac0_clk_src, 221 .hw_clk_ctrl = true, 222 .clkr.hw.init = &(const struct clk_init_data) { 223 .name = "se_gcc_eee_emac1_clk_src", 224 .parent_data = se_gcc_parent_data_2, 225 .num_parents = ARRAY_SIZE(se_gcc_parent_data_2), 226 .flags = CLK_SET_RATE_PARENT, 227 .ops = &clk_rcg2_shared_ops, 228 }, 229 }; 230 231 static const struct freq_tbl ftbl_se_gcc_emac0_phy_aux_clk_src[] = { 232 F(19200000, P_BI_TCXO, 1, 0, 0), 233 { } 234 }; 235 236 static struct clk_rcg2 se_gcc_emac0_phy_aux_clk_src = { 237 .cmd_rcgr = 0x24030, 238 .mnd_width = 0, 239 .hid_width = 5, 240 .parent_map = se_gcc_parent_map_2, 241 .freq_tbl = ftbl_se_gcc_emac0_phy_aux_clk_src, 242 .hw_clk_ctrl = true, 243 .clkr.hw.init = &(const struct clk_init_data) { 244 .name = "se_gcc_emac0_phy_aux_clk_src", 245 .parent_data = se_gcc_parent_data_2, 246 .num_parents = ARRAY_SIZE(se_gcc_parent_data_2), 247 .flags = CLK_SET_RATE_PARENT, 248 .ops = &clk_rcg2_shared_ops, 249 }, 250 }; 251 252 static const struct freq_tbl ftbl_se_gcc_emac0_ptp_clk_src[] = { 253 F(150000000, P_SE_GCC_GPLL0_OUT_MAIN, 4, 0, 0), 254 F(250000000, P_SE_GCC_GPLL5_OUT_MAIN, 4, 0, 0), 255 { } 256 }; 257 258 static struct clk_rcg2 se_gcc_emac0_ptp_clk_src = { 259 .cmd_rcgr = 0x24084, 260 .mnd_width = 16, 261 .hid_width = 5, 262 .parent_map = se_gcc_parent_map_3, 263 .freq_tbl = ftbl_se_gcc_emac0_ptp_clk_src, 264 .hw_clk_ctrl = true, 265 .clkr.hw.init = &(const struct clk_init_data) { 266 .name = "se_gcc_emac0_ptp_clk_src", 267 .parent_data = se_gcc_parent_data_3, 268 .num_parents = ARRAY_SIZE(se_gcc_parent_data_3), 269 .flags = CLK_SET_RATE_PARENT, 270 .ops = &clk_rcg2_shared_ops, 271 }, 272 }; 273 274 static const struct freq_tbl ftbl_se_gcc_emac0_rgmii_clk_src[] = { 275 F(75000000, P_SE_GCC_GPLL0_OUT_MAIN, 8, 0, 0), 276 F(120000000, P_SE_GCC_GPLL0_OUT_MAIN, 5, 0, 0), 277 F(250000000, P_SE_GCC_GPLL5_OUT_MAIN, 4, 0, 0), 278 { } 279 }; 280 281 static struct clk_rcg2 se_gcc_emac0_rgmii_clk_src = { 282 .cmd_rcgr = 0x2406c, 283 .mnd_width = 16, 284 .hid_width = 5, 285 .parent_map = se_gcc_parent_map_3, 286 .freq_tbl = ftbl_se_gcc_emac0_rgmii_clk_src, 287 .hw_clk_ctrl = true, 288 .clkr.hw.init = &(const struct clk_init_data) { 289 .name = "se_gcc_emac0_rgmii_clk_src", 290 .parent_data = se_gcc_parent_data_3, 291 .num_parents = ARRAY_SIZE(se_gcc_parent_data_3), 292 .flags = CLK_SET_RATE_PARENT, 293 .ops = &clk_rcg2_shared_ops, 294 }, 295 }; 296 297 static struct clk_rcg2 se_gcc_emac1_phy_aux_clk_src = { 298 .cmd_rcgr = 0x25030, 299 .mnd_width = 0, 300 .hid_width = 5, 301 .parent_map = se_gcc_parent_map_2, 302 .freq_tbl = ftbl_se_gcc_emac0_phy_aux_clk_src, 303 .hw_clk_ctrl = true, 304 .clkr.hw.init = &(const struct clk_init_data) { 305 .name = "se_gcc_emac1_phy_aux_clk_src", 306 .parent_data = se_gcc_parent_data_2, 307 .num_parents = ARRAY_SIZE(se_gcc_parent_data_2), 308 .flags = CLK_SET_RATE_PARENT, 309 .ops = &clk_rcg2_shared_ops, 310 }, 311 }; 312 313 static struct clk_rcg2 se_gcc_emac1_ptp_clk_src = { 314 .cmd_rcgr = 0x25084, 315 .mnd_width = 16, 316 .hid_width = 5, 317 .parent_map = se_gcc_parent_map_3, 318 .freq_tbl = ftbl_se_gcc_emac0_ptp_clk_src, 319 .hw_clk_ctrl = true, 320 .clkr.hw.init = &(const struct clk_init_data) { 321 .name = "se_gcc_emac1_ptp_clk_src", 322 .parent_data = se_gcc_parent_data_3, 323 .num_parents = ARRAY_SIZE(se_gcc_parent_data_3), 324 .flags = CLK_SET_RATE_PARENT, 325 .ops = &clk_rcg2_shared_ops, 326 }, 327 }; 328 329 static struct clk_rcg2 se_gcc_emac1_rgmii_clk_src = { 330 .cmd_rcgr = 0x2506c, 331 .mnd_width = 16, 332 .hid_width = 5, 333 .parent_map = se_gcc_parent_map_3, 334 .freq_tbl = ftbl_se_gcc_emac0_rgmii_clk_src, 335 .hw_clk_ctrl = true, 336 .clkr.hw.init = &(const struct clk_init_data) { 337 .name = "se_gcc_emac1_rgmii_clk_src", 338 .parent_data = se_gcc_parent_data_3, 339 .num_parents = ARRAY_SIZE(se_gcc_parent_data_3), 340 .flags = CLK_SET_RATE_PARENT, 341 .ops = &clk_rcg2_shared_ops, 342 }, 343 }; 344 345 static const struct freq_tbl ftbl_se_gcc_gp1_clk_src[] = { 346 F(66666667, P_SE_GCC_GPLL0_OUT_MAIN, 9, 0, 0), 347 F(100000000, P_SE_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 348 F(200000000, P_SE_GCC_GPLL0_OUT_MAIN, 3, 0, 0), 349 { } 350 }; 351 352 static struct clk_rcg2 se_gcc_gp1_clk_src = { 353 .cmd_rcgr = 0x19004, 354 .mnd_width = 16, 355 .hid_width = 5, 356 .parent_map = se_gcc_parent_map_4, 357 .freq_tbl = ftbl_se_gcc_gp1_clk_src, 358 .hw_clk_ctrl = true, 359 .clkr.hw.init = &(const struct clk_init_data) { 360 .name = "se_gcc_gp1_clk_src", 361 .parent_data = se_gcc_parent_data_4, 362 .num_parents = ARRAY_SIZE(se_gcc_parent_data_4), 363 .flags = CLK_SET_RATE_PARENT, 364 .ops = &clk_rcg2_shared_ops, 365 }, 366 }; 367 368 static struct clk_rcg2 se_gcc_gp2_clk_src = { 369 .cmd_rcgr = 0x1a004, 370 .mnd_width = 16, 371 .hid_width = 5, 372 .parent_map = se_gcc_parent_map_4, 373 .freq_tbl = ftbl_se_gcc_gp1_clk_src, 374 .hw_clk_ctrl = true, 375 .clkr.hw.init = &(const struct clk_init_data) { 376 .name = "se_gcc_gp2_clk_src", 377 .parent_data = se_gcc_parent_data_4, 378 .num_parents = ARRAY_SIZE(se_gcc_parent_data_4), 379 .flags = CLK_SET_RATE_PARENT, 380 .ops = &clk_rcg2_shared_ops, 381 }, 382 }; 383 384 static const struct freq_tbl ftbl_se_gcc_qupv3_wrap0_s0_clk_src[] = { 385 F(7372800, P_SE_GCC_GPLL0_OUT_MAIN, 1, 192, 15625), 386 F(14745600, P_SE_GCC_GPLL0_OUT_MAIN, 1, 384, 15625), 387 F(19200000, P_BI_TCXO, 1, 0, 0), 388 F(29491200, P_SE_GCC_GPLL0_OUT_MAIN, 1, 768, 15625), 389 F(32000000, P_SE_GCC_GPLL0_OUT_MAIN, 1, 4, 75), 390 F(48000000, P_SE_GCC_GPLL0_OUT_MAIN, 1, 2, 25), 391 F(51200000, P_SE_GCC_GPLL0_OUT_MAIN, 1, 32, 375), 392 F(64000000, P_SE_GCC_GPLL0_OUT_MAIN, 1, 8, 75), 393 F(66666667, P_SE_GCC_GPLL0_OUT_MAIN, 9, 0, 0), 394 F(75000000, P_SE_GCC_GPLL0_OUT_MAIN, 8, 0, 0), 395 F(80000000, P_SE_GCC_GPLL0_OUT_MAIN, 1, 2, 15), 396 F(96000000, P_SE_GCC_GPLL0_OUT_MAIN, 1, 4, 25), 397 F(100000000, P_SE_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 398 F(102400000, P_SE_GCC_GPLL0_OUT_MAIN, 1, 64, 375), 399 F(112000000, P_SE_GCC_GPLL0_OUT_MAIN, 1, 14, 75), 400 F(117964800, P_SE_GCC_GPLL0_OUT_MAIN, 1, 3072, 15625), 401 F(120000000, P_SE_GCC_GPLL0_OUT_MAIN, 5, 0, 0), 402 { } 403 }; 404 405 static struct clk_init_data se_gcc_qupv3_wrap0_s0_clk_src_init = { 406 .name = "se_gcc_qupv3_wrap0_s0_clk_src", 407 .parent_data = se_gcc_parent_data_1, 408 .num_parents = ARRAY_SIZE(se_gcc_parent_data_1), 409 .flags = CLK_SET_RATE_PARENT, 410 .ops = &clk_rcg2_shared_no_init_park_ops, 411 }; 412 413 static struct clk_rcg2 se_gcc_qupv3_wrap0_s0_clk_src = { 414 .cmd_rcgr = 0x2616c, 415 .mnd_width = 16, 416 .hid_width = 5, 417 .parent_map = se_gcc_parent_map_1, 418 .freq_tbl = ftbl_se_gcc_qupv3_wrap0_s0_clk_src, 419 .hw_clk_ctrl = true, 420 .clkr.hw.init = &se_gcc_qupv3_wrap0_s0_clk_src_init, 421 }; 422 423 static struct clk_init_data se_gcc_qupv3_wrap0_s1_clk_src_init = { 424 .name = "se_gcc_qupv3_wrap0_s1_clk_src", 425 .parent_data = se_gcc_parent_data_1, 426 .num_parents = ARRAY_SIZE(se_gcc_parent_data_1), 427 .flags = CLK_SET_RATE_PARENT, 428 .ops = &clk_rcg2_shared_no_init_park_ops, 429 }; 430 431 static struct clk_rcg2 se_gcc_qupv3_wrap0_s1_clk_src = { 432 .cmd_rcgr = 0x262a8, 433 .mnd_width = 16, 434 .hid_width = 5, 435 .parent_map = se_gcc_parent_map_1, 436 .freq_tbl = ftbl_se_gcc_qupv3_wrap0_s0_clk_src, 437 .hw_clk_ctrl = true, 438 .clkr.hw.init = &se_gcc_qupv3_wrap0_s1_clk_src_init, 439 }; 440 441 static const struct freq_tbl ftbl_se_gcc_qupv3_wrap0_s2_clk_src[] = { 442 F(7372800, P_SE_GCC_GPLL0_OUT_MAIN, 1, 192, 15625), 443 F(14745600, P_SE_GCC_GPLL0_OUT_MAIN, 1, 384, 15625), 444 F(19200000, P_BI_TCXO, 1, 0, 0), 445 F(29491200, P_SE_GCC_GPLL0_OUT_MAIN, 1, 768, 15625), 446 F(32000000, P_SE_GCC_GPLL0_OUT_MAIN, 1, 4, 75), 447 F(48000000, P_SE_GCC_GPLL0_OUT_MAIN, 1, 2, 25), 448 F(51200000, P_SE_GCC_GPLL0_OUT_MAIN, 1, 32, 375), 449 F(64000000, P_SE_GCC_GPLL0_OUT_MAIN, 1, 8, 75), 450 F(66666667, P_SE_GCC_GPLL0_OUT_MAIN, 9, 0, 0), 451 F(75000000, P_SE_GCC_GPLL0_OUT_MAIN, 8, 0, 0), 452 F(80000000, P_SE_GCC_GPLL0_OUT_MAIN, 1, 2, 15), 453 F(96000000, P_SE_GCC_GPLL0_OUT_MAIN, 1, 4, 25), 454 F(100000000, P_SE_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 455 { } 456 }; 457 458 static struct clk_init_data se_gcc_qupv3_wrap0_s2_clk_src_init = { 459 .name = "se_gcc_qupv3_wrap0_s2_clk_src", 460 .parent_data = se_gcc_parent_data_1, 461 .num_parents = ARRAY_SIZE(se_gcc_parent_data_1), 462 .flags = CLK_SET_RATE_PARENT, 463 .ops = &clk_rcg2_shared_no_init_park_ops, 464 }; 465 466 static struct clk_rcg2 se_gcc_qupv3_wrap0_s2_clk_src = { 467 .cmd_rcgr = 0x263e4, 468 .mnd_width = 16, 469 .hid_width = 5, 470 .parent_map = se_gcc_parent_map_1, 471 .freq_tbl = ftbl_se_gcc_qupv3_wrap0_s2_clk_src, 472 .hw_clk_ctrl = true, 473 .clkr.hw.init = &se_gcc_qupv3_wrap0_s2_clk_src_init, 474 }; 475 476 static struct clk_init_data se_gcc_qupv3_wrap0_s3_clk_src_init = { 477 .name = "se_gcc_qupv3_wrap0_s3_clk_src", 478 .parent_data = se_gcc_parent_data_1, 479 .num_parents = ARRAY_SIZE(se_gcc_parent_data_1), 480 .flags = CLK_SET_RATE_PARENT, 481 .ops = &clk_rcg2_shared_no_init_park_ops, 482 }; 483 484 static struct clk_rcg2 se_gcc_qupv3_wrap0_s3_clk_src = { 485 .cmd_rcgr = 0x26520, 486 .mnd_width = 16, 487 .hid_width = 5, 488 .parent_map = se_gcc_parent_map_1, 489 .freq_tbl = ftbl_se_gcc_qupv3_wrap0_s2_clk_src, 490 .hw_clk_ctrl = true, 491 .clkr.hw.init = &se_gcc_qupv3_wrap0_s3_clk_src_init, 492 }; 493 494 static struct clk_init_data se_gcc_qupv3_wrap0_s4_clk_src_init = { 495 .name = "se_gcc_qupv3_wrap0_s4_clk_src", 496 .parent_data = se_gcc_parent_data_1, 497 .num_parents = ARRAY_SIZE(se_gcc_parent_data_1), 498 .flags = CLK_SET_RATE_PARENT, 499 .ops = &clk_rcg2_shared_no_init_park_ops, 500 }; 501 502 static struct clk_rcg2 se_gcc_qupv3_wrap0_s4_clk_src = { 503 .cmd_rcgr = 0x2665c, 504 .mnd_width = 16, 505 .hid_width = 5, 506 .parent_map = se_gcc_parent_map_1, 507 .freq_tbl = ftbl_se_gcc_qupv3_wrap0_s2_clk_src, 508 .hw_clk_ctrl = true, 509 .clkr.hw.init = &se_gcc_qupv3_wrap0_s4_clk_src_init, 510 }; 511 512 static struct clk_init_data se_gcc_qupv3_wrap0_s5_clk_src_init = { 513 .name = "se_gcc_qupv3_wrap0_s5_clk_src", 514 .parent_data = se_gcc_parent_data_1, 515 .num_parents = ARRAY_SIZE(se_gcc_parent_data_1), 516 .flags = CLK_SET_RATE_PARENT, 517 .ops = &clk_rcg2_shared_no_init_park_ops, 518 }; 519 520 static struct clk_rcg2 se_gcc_qupv3_wrap0_s5_clk_src = { 521 .cmd_rcgr = 0x26798, 522 .mnd_width = 16, 523 .hid_width = 5, 524 .parent_map = se_gcc_parent_map_1, 525 .freq_tbl = ftbl_se_gcc_qupv3_wrap0_s2_clk_src, 526 .hw_clk_ctrl = true, 527 .clkr.hw.init = &se_gcc_qupv3_wrap0_s5_clk_src_init, 528 }; 529 530 static struct clk_init_data se_gcc_qupv3_wrap0_s6_clk_src_init = { 531 .name = "se_gcc_qupv3_wrap0_s6_clk_src", 532 .parent_data = se_gcc_parent_data_1, 533 .num_parents = ARRAY_SIZE(se_gcc_parent_data_1), 534 .flags = CLK_SET_RATE_PARENT, 535 .ops = &clk_rcg2_shared_no_init_park_ops, 536 }; 537 538 static struct clk_rcg2 se_gcc_qupv3_wrap0_s6_clk_src = { 539 .cmd_rcgr = 0x268d4, 540 .mnd_width = 16, 541 .hid_width = 5, 542 .parent_map = se_gcc_parent_map_1, 543 .freq_tbl = ftbl_se_gcc_qupv3_wrap0_s2_clk_src, 544 .hw_clk_ctrl = true, 545 .clkr.hw.init = &se_gcc_qupv3_wrap0_s6_clk_src_init, 546 }; 547 548 static struct clk_init_data se_gcc_qupv3_wrap1_s0_clk_src_init = { 549 .name = "se_gcc_qupv3_wrap1_s0_clk_src", 550 .parent_data = se_gcc_parent_data_0, 551 .num_parents = ARRAY_SIZE(se_gcc_parent_data_0), 552 .flags = CLK_SET_RATE_PARENT, 553 .ops = &clk_rcg2_shared_no_init_park_ops, 554 }; 555 556 static struct clk_rcg2 se_gcc_qupv3_wrap1_s0_clk_src = { 557 .cmd_rcgr = 0x2716c, 558 .mnd_width = 16, 559 .hid_width = 5, 560 .parent_map = se_gcc_parent_map_0, 561 .freq_tbl = ftbl_se_gcc_qupv3_wrap0_s0_clk_src, 562 .hw_clk_ctrl = true, 563 .clkr.hw.init = &se_gcc_qupv3_wrap1_s0_clk_src_init, 564 }; 565 566 static struct clk_init_data se_gcc_qupv3_wrap1_s1_clk_src_init = { 567 .name = "se_gcc_qupv3_wrap1_s1_clk_src", 568 .parent_data = se_gcc_parent_data_0, 569 .num_parents = ARRAY_SIZE(se_gcc_parent_data_0), 570 .flags = CLK_SET_RATE_PARENT, 571 .ops = &clk_rcg2_shared_no_init_park_ops, 572 }; 573 574 static struct clk_rcg2 se_gcc_qupv3_wrap1_s1_clk_src = { 575 .cmd_rcgr = 0x272a8, 576 .mnd_width = 16, 577 .hid_width = 5, 578 .parent_map = se_gcc_parent_map_0, 579 .freq_tbl = ftbl_se_gcc_qupv3_wrap0_s0_clk_src, 580 .hw_clk_ctrl = true, 581 .clkr.hw.init = &se_gcc_qupv3_wrap1_s1_clk_src_init, 582 }; 583 584 static struct clk_init_data se_gcc_qupv3_wrap1_s2_clk_src_init = { 585 .name = "se_gcc_qupv3_wrap1_s2_clk_src", 586 .parent_data = se_gcc_parent_data_0, 587 .num_parents = ARRAY_SIZE(se_gcc_parent_data_0), 588 .flags = CLK_SET_RATE_PARENT, 589 .ops = &clk_rcg2_shared_no_init_park_ops, 590 }; 591 592 static struct clk_rcg2 se_gcc_qupv3_wrap1_s2_clk_src = { 593 .cmd_rcgr = 0x273e4, 594 .mnd_width = 16, 595 .hid_width = 5, 596 .parent_map = se_gcc_parent_map_0, 597 .freq_tbl = ftbl_se_gcc_qupv3_wrap0_s2_clk_src, 598 .hw_clk_ctrl = true, 599 .clkr.hw.init = &se_gcc_qupv3_wrap1_s2_clk_src_init, 600 }; 601 602 static struct clk_init_data se_gcc_qupv3_wrap1_s3_clk_src_init = { 603 .name = "se_gcc_qupv3_wrap1_s3_clk_src", 604 .parent_data = se_gcc_parent_data_0, 605 .num_parents = ARRAY_SIZE(se_gcc_parent_data_0), 606 .flags = CLK_SET_RATE_PARENT, 607 .ops = &clk_rcg2_shared_no_init_park_ops, 608 }; 609 610 static struct clk_rcg2 se_gcc_qupv3_wrap1_s3_clk_src = { 611 .cmd_rcgr = 0x27520, 612 .mnd_width = 16, 613 .hid_width = 5, 614 .parent_map = se_gcc_parent_map_0, 615 .freq_tbl = ftbl_se_gcc_qupv3_wrap0_s2_clk_src, 616 .hw_clk_ctrl = true, 617 .clkr.hw.init = &se_gcc_qupv3_wrap1_s3_clk_src_init, 618 }; 619 620 static struct clk_init_data se_gcc_qupv3_wrap1_s4_clk_src_init = { 621 .name = "se_gcc_qupv3_wrap1_s4_clk_src", 622 .parent_data = se_gcc_parent_data_0, 623 .num_parents = ARRAY_SIZE(se_gcc_parent_data_0), 624 .flags = CLK_SET_RATE_PARENT, 625 .ops = &clk_rcg2_shared_no_init_park_ops, 626 }; 627 628 static struct clk_rcg2 se_gcc_qupv3_wrap1_s4_clk_src = { 629 .cmd_rcgr = 0x2765c, 630 .mnd_width = 16, 631 .hid_width = 5, 632 .parent_map = se_gcc_parent_map_0, 633 .freq_tbl = ftbl_se_gcc_qupv3_wrap0_s2_clk_src, 634 .hw_clk_ctrl = true, 635 .clkr.hw.init = &se_gcc_qupv3_wrap1_s4_clk_src_init, 636 }; 637 638 static struct clk_init_data se_gcc_qupv3_wrap1_s5_clk_src_init = { 639 .name = "se_gcc_qupv3_wrap1_s5_clk_src", 640 .parent_data = se_gcc_parent_data_0, 641 .num_parents = ARRAY_SIZE(se_gcc_parent_data_0), 642 .flags = CLK_SET_RATE_PARENT, 643 .ops = &clk_rcg2_shared_no_init_park_ops, 644 }; 645 646 static struct clk_rcg2 se_gcc_qupv3_wrap1_s5_clk_src = { 647 .cmd_rcgr = 0x27798, 648 .mnd_width = 16, 649 .hid_width = 5, 650 .parent_map = se_gcc_parent_map_0, 651 .freq_tbl = ftbl_se_gcc_qupv3_wrap0_s2_clk_src, 652 .hw_clk_ctrl = true, 653 .clkr.hw.init = &se_gcc_qupv3_wrap1_s5_clk_src_init, 654 }; 655 656 static struct clk_init_data se_gcc_qupv3_wrap1_s6_clk_src_init = { 657 .name = "se_gcc_qupv3_wrap1_s6_clk_src", 658 .parent_data = se_gcc_parent_data_0, 659 .num_parents = ARRAY_SIZE(se_gcc_parent_data_0), 660 .flags = CLK_SET_RATE_PARENT, 661 .ops = &clk_rcg2_shared_no_init_park_ops, 662 }; 663 664 static struct clk_rcg2 se_gcc_qupv3_wrap1_s6_clk_src = { 665 .cmd_rcgr = 0x278d4, 666 .mnd_width = 16, 667 .hid_width = 5, 668 .parent_map = se_gcc_parent_map_0, 669 .freq_tbl = ftbl_se_gcc_qupv3_wrap0_s2_clk_src, 670 .hw_clk_ctrl = true, 671 .clkr.hw.init = &se_gcc_qupv3_wrap1_s6_clk_src_init, 672 }; 673 674 static struct clk_branch se_gcc_eee_emac0_clk = { 675 .halt_reg = 0x240b4, 676 .halt_check = BRANCH_HALT, 677 .clkr = { 678 .enable_reg = 0x240b4, 679 .enable_mask = BIT(0), 680 .hw.init = &(const struct clk_init_data) { 681 .name = "se_gcc_eee_emac0_clk", 682 .parent_hws = (const struct clk_hw*[]) { 683 &se_gcc_eee_emac0_clk_src.clkr.hw, 684 }, 685 .num_parents = 1, 686 .flags = CLK_SET_RATE_PARENT, 687 .ops = &clk_branch2_ops, 688 }, 689 }, 690 }; 691 692 static struct clk_branch se_gcc_eee_emac1_clk = { 693 .halt_reg = 0x250b4, 694 .halt_check = BRANCH_HALT, 695 .clkr = { 696 .enable_reg = 0x250b4, 697 .enable_mask = BIT(0), 698 .hw.init = &(const struct clk_init_data) { 699 .name = "se_gcc_eee_emac1_clk", 700 .parent_hws = (const struct clk_hw*[]) { 701 &se_gcc_eee_emac1_clk_src.clkr.hw, 702 }, 703 .num_parents = 1, 704 .flags = CLK_SET_RATE_PARENT, 705 .ops = &clk_branch2_ops, 706 }, 707 }, 708 }; 709 710 static struct clk_branch se_gcc_emac0_axi_clk = { 711 .halt_reg = 0x2401c, 712 .halt_check = BRANCH_HALT_VOTED, 713 .hwcg_reg = 0x2401c, 714 .hwcg_bit = 1, 715 .clkr = { 716 .enable_reg = 0x2401c, 717 .enable_mask = BIT(0), 718 .hw.init = &(const struct clk_init_data) { 719 .name = "se_gcc_emac0_axi_clk", 720 .ops = &clk_branch2_ops, 721 }, 722 }, 723 }; 724 725 static struct clk_branch se_gcc_emac0_cc_sgmiiphy_rx_clk = { 726 .halt_reg = 0x24064, 727 .halt_check = BRANCH_HALT, 728 .clkr = { 729 .enable_reg = 0x24064, 730 .enable_mask = BIT(0), 731 .hw.init = &(const struct clk_init_data) { 732 .name = "se_gcc_emac0_cc_sgmiiphy_rx_clk", 733 .ops = &clk_branch2_ops, 734 }, 735 }, 736 }; 737 738 static struct clk_branch se_gcc_emac0_cc_sgmiiphy_tx_clk = { 739 .halt_reg = 0x2405c, 740 .halt_check = BRANCH_HALT, 741 .clkr = { 742 .enable_reg = 0x2405c, 743 .enable_mask = BIT(0), 744 .hw.init = &(const struct clk_init_data) { 745 .name = "se_gcc_emac0_cc_sgmiiphy_tx_clk", 746 .ops = &clk_branch2_ops, 747 }, 748 }, 749 }; 750 751 static struct clk_branch se_gcc_emac0_phy_aux_clk = { 752 .halt_reg = 0x2402c, 753 .halt_check = BRANCH_HALT, 754 .clkr = { 755 .enable_reg = 0x2402c, 756 .enable_mask = BIT(0), 757 .hw.init = &(const struct clk_init_data) { 758 .name = "se_gcc_emac0_phy_aux_clk", 759 .parent_hws = (const struct clk_hw*[]) { 760 &se_gcc_emac0_phy_aux_clk_src.clkr.hw, 761 }, 762 .num_parents = 1, 763 .flags = CLK_SET_RATE_PARENT, 764 .ops = &clk_branch2_ops, 765 }, 766 }, 767 }; 768 769 static struct clk_branch se_gcc_emac0_ptp_clk = { 770 .halt_reg = 0x24048, 771 .halt_check = BRANCH_HALT, 772 .clkr = { 773 .enable_reg = 0x24048, 774 .enable_mask = BIT(0), 775 .hw.init = &(const struct clk_init_data) { 776 .name = "se_gcc_emac0_ptp_clk", 777 .parent_hws = (const struct clk_hw*[]) { 778 &se_gcc_emac0_ptp_clk_src.clkr.hw, 779 }, 780 .num_parents = 1, 781 .flags = CLK_SET_RATE_PARENT, 782 .ops = &clk_branch2_ops, 783 }, 784 }, 785 }; 786 787 static struct clk_branch se_gcc_emac0_rgmii_clk = { 788 .halt_reg = 0x24058, 789 .halt_check = BRANCH_HALT, 790 .clkr = { 791 .enable_reg = 0x24058, 792 .enable_mask = BIT(0), 793 .hw.init = &(const struct clk_init_data) { 794 .name = "se_gcc_emac0_rgmii_clk", 795 .parent_hws = (const struct clk_hw*[]) { 796 &se_gcc_emac0_rgmii_clk_src.clkr.hw, 797 }, 798 .num_parents = 1, 799 .flags = CLK_SET_RATE_PARENT, 800 .ops = &clk_branch2_ops, 801 }, 802 }, 803 }; 804 805 static struct clk_branch se_gcc_emac0_rpcs_rx_clk = { 806 .halt_reg = 0x240a8, 807 .halt_check = BRANCH_HALT, 808 .clkr = { 809 .enable_reg = 0x240a8, 810 .enable_mask = BIT(0), 811 .hw.init = &(const struct clk_init_data) { 812 .name = "se_gcc_emac0_rpcs_rx_clk", 813 .ops = &clk_branch2_ops, 814 }, 815 }, 816 }; 817 818 static struct clk_branch se_gcc_emac0_rpcs_tx_clk = { 819 .halt_reg = 0x240a4, 820 .halt_check = BRANCH_HALT, 821 .clkr = { 822 .enable_reg = 0x240a4, 823 .enable_mask = BIT(0), 824 .hw.init = &(const struct clk_init_data) { 825 .name = "se_gcc_emac0_rpcs_tx_clk", 826 .ops = &clk_branch2_ops, 827 }, 828 }, 829 }; 830 831 static struct clk_branch se_gcc_emac0_xgxs_rx_clk = { 832 .halt_reg = 0x240b0, 833 .halt_check = BRANCH_HALT, 834 .clkr = { 835 .enable_reg = 0x240b0, 836 .enable_mask = BIT(0), 837 .hw.init = &(const struct clk_init_data) { 838 .name = "se_gcc_emac0_xgxs_rx_clk", 839 .ops = &clk_branch2_ops, 840 }, 841 }, 842 }; 843 844 static struct clk_branch se_gcc_emac0_xgxs_tx_clk = { 845 .halt_reg = 0x240ac, 846 .halt_check = BRANCH_HALT, 847 .clkr = { 848 .enable_reg = 0x240ac, 849 .enable_mask = BIT(0), 850 .hw.init = &(const struct clk_init_data) { 851 .name = "se_gcc_emac0_xgxs_tx_clk", 852 .ops = &clk_branch2_ops, 853 }, 854 }, 855 }; 856 857 static struct clk_branch se_gcc_emac1_axi_clk = { 858 .halt_reg = 0x2501c, 859 .halt_check = BRANCH_HALT_VOTED, 860 .hwcg_reg = 0x2501c, 861 .hwcg_bit = 1, 862 .clkr = { 863 .enable_reg = 0x2501c, 864 .enable_mask = BIT(0), 865 .hw.init = &(const struct clk_init_data) { 866 .name = "se_gcc_emac1_axi_clk", 867 .ops = &clk_branch2_ops, 868 }, 869 }, 870 }; 871 872 static struct clk_branch se_gcc_emac1_cc_sgmiiphy_rx_clk = { 873 .halt_reg = 0x25064, 874 .halt_check = BRANCH_HALT, 875 .clkr = { 876 .enable_reg = 0x25064, 877 .enable_mask = BIT(0), 878 .hw.init = &(const struct clk_init_data) { 879 .name = "se_gcc_emac1_cc_sgmiiphy_rx_clk", 880 .ops = &clk_branch2_ops, 881 }, 882 }, 883 }; 884 885 static struct clk_branch se_gcc_emac1_cc_sgmiiphy_tx_clk = { 886 .halt_reg = 0x2505c, 887 .halt_check = BRANCH_HALT, 888 .clkr = { 889 .enable_reg = 0x2505c, 890 .enable_mask = BIT(0), 891 .hw.init = &(const struct clk_init_data) { 892 .name = "se_gcc_emac1_cc_sgmiiphy_tx_clk", 893 .ops = &clk_branch2_ops, 894 }, 895 }, 896 }; 897 898 static struct clk_branch se_gcc_emac1_phy_aux_clk = { 899 .halt_reg = 0x2502c, 900 .halt_check = BRANCH_HALT, 901 .clkr = { 902 .enable_reg = 0x2502c, 903 .enable_mask = BIT(0), 904 .hw.init = &(const struct clk_init_data) { 905 .name = "se_gcc_emac1_phy_aux_clk", 906 .parent_hws = (const struct clk_hw*[]) { 907 &se_gcc_emac1_phy_aux_clk_src.clkr.hw, 908 }, 909 .num_parents = 1, 910 .flags = CLK_SET_RATE_PARENT, 911 .ops = &clk_branch2_ops, 912 }, 913 }, 914 }; 915 916 static struct clk_branch se_gcc_emac1_ptp_clk = { 917 .halt_reg = 0x25048, 918 .halt_check = BRANCH_HALT, 919 .clkr = { 920 .enable_reg = 0x25048, 921 .enable_mask = BIT(0), 922 .hw.init = &(const struct clk_init_data) { 923 .name = "se_gcc_emac1_ptp_clk", 924 .parent_hws = (const struct clk_hw*[]) { 925 &se_gcc_emac1_ptp_clk_src.clkr.hw, 926 }, 927 .num_parents = 1, 928 .flags = CLK_SET_RATE_PARENT, 929 .ops = &clk_branch2_ops, 930 }, 931 }, 932 }; 933 934 static struct clk_branch se_gcc_emac1_rgmii_clk = { 935 .halt_reg = 0x25058, 936 .halt_check = BRANCH_HALT, 937 .clkr = { 938 .enable_reg = 0x25058, 939 .enable_mask = BIT(0), 940 .hw.init = &(const struct clk_init_data) { 941 .name = "se_gcc_emac1_rgmii_clk", 942 .parent_hws = (const struct clk_hw*[]) { 943 &se_gcc_emac1_rgmii_clk_src.clkr.hw, 944 }, 945 .num_parents = 1, 946 .flags = CLK_SET_RATE_PARENT, 947 .ops = &clk_branch2_ops, 948 }, 949 }, 950 }; 951 952 static struct clk_branch se_gcc_emac1_rpcs_rx_clk = { 953 .halt_reg = 0x250a8, 954 .halt_check = BRANCH_HALT, 955 .clkr = { 956 .enable_reg = 0x250a8, 957 .enable_mask = BIT(0), 958 .hw.init = &(const struct clk_init_data) { 959 .name = "se_gcc_emac1_rpcs_rx_clk", 960 .ops = &clk_branch2_ops, 961 }, 962 }, 963 }; 964 965 static struct clk_branch se_gcc_emac1_rpcs_tx_clk = { 966 .halt_reg = 0x250a4, 967 .halt_check = BRANCH_HALT, 968 .clkr = { 969 .enable_reg = 0x250a4, 970 .enable_mask = BIT(0), 971 .hw.init = &(const struct clk_init_data) { 972 .name = "se_gcc_emac1_rpcs_tx_clk", 973 .ops = &clk_branch2_ops, 974 }, 975 }, 976 }; 977 978 static struct clk_branch se_gcc_emac1_xgxs_rx_clk = { 979 .halt_reg = 0x250b0, 980 .halt_check = BRANCH_HALT, 981 .clkr = { 982 .enable_reg = 0x250b0, 983 .enable_mask = BIT(0), 984 .hw.init = &(const struct clk_init_data) { 985 .name = "se_gcc_emac1_xgxs_rx_clk", 986 .ops = &clk_branch2_ops, 987 }, 988 }, 989 }; 990 991 static struct clk_branch se_gcc_emac1_xgxs_tx_clk = { 992 .halt_reg = 0x250ac, 993 .halt_check = BRANCH_HALT, 994 .clkr = { 995 .enable_reg = 0x250ac, 996 .enable_mask = BIT(0), 997 .hw.init = &(const struct clk_init_data) { 998 .name = "se_gcc_emac1_xgxs_tx_clk", 999 .ops = &clk_branch2_ops, 1000 }, 1001 }, 1002 }; 1003 1004 static struct clk_branch se_gcc_frq_measure_ref_clk = { 1005 .halt_reg = 0x18008, 1006 .halt_check = BRANCH_HALT, 1007 .clkr = { 1008 .enable_reg = 0x18008, 1009 .enable_mask = BIT(0), 1010 .hw.init = &(const struct clk_init_data) { 1011 .name = "se_gcc_frq_measure_ref_clk", 1012 .ops = &clk_branch2_ops, 1013 }, 1014 }, 1015 }; 1016 1017 static struct clk_branch se_gcc_gp1_clk = { 1018 .halt_reg = 0x19000, 1019 .halt_check = BRANCH_HALT, 1020 .clkr = { 1021 .enable_reg = 0x19000, 1022 .enable_mask = BIT(0), 1023 .hw.init = &(const struct clk_init_data) { 1024 .name = "se_gcc_gp1_clk", 1025 .parent_hws = (const struct clk_hw*[]) { 1026 &se_gcc_gp1_clk_src.clkr.hw, 1027 }, 1028 .num_parents = 1, 1029 .flags = CLK_SET_RATE_PARENT, 1030 .ops = &clk_branch2_ops, 1031 }, 1032 }, 1033 }; 1034 1035 static struct clk_branch se_gcc_gp2_clk = { 1036 .halt_reg = 0x1a000, 1037 .halt_check = BRANCH_HALT, 1038 .clkr = { 1039 .enable_reg = 0x1a000, 1040 .enable_mask = BIT(0), 1041 .hw.init = &(const struct clk_init_data) { 1042 .name = "se_gcc_gp2_clk", 1043 .parent_hws = (const struct clk_hw*[]) { 1044 &se_gcc_gp2_clk_src.clkr.hw, 1045 }, 1046 .num_parents = 1, 1047 .flags = CLK_SET_RATE_PARENT, 1048 .ops = &clk_branch2_ops, 1049 }, 1050 }, 1051 }; 1052 1053 static struct clk_branch se_gcc_mmu_2_tcu_vote_clk = { 1054 .halt_reg = 0x57040, 1055 .halt_check = BRANCH_HALT_VOTED, 1056 .clkr = { 1057 .enable_reg = 0x57040, 1058 .enable_mask = BIT(0), 1059 .hw.init = &(const struct clk_init_data) { 1060 .name = "se_gcc_mmu_2_tcu_vote_clk", 1061 .ops = &clk_branch2_ops, 1062 }, 1063 }, 1064 }; 1065 1066 static struct clk_branch se_gcc_qupv3_wrap0_core_2x_clk = { 1067 .halt_reg = 0x26020, 1068 .halt_check = BRANCH_HALT_VOTED, 1069 .clkr = { 1070 .enable_reg = 0x57000, 1071 .enable_mask = BIT(15), 1072 .hw.init = &(const struct clk_init_data) { 1073 .name = "se_gcc_qupv3_wrap0_core_2x_clk", 1074 .ops = &clk_branch2_ops, 1075 }, 1076 }, 1077 }; 1078 1079 static struct clk_branch se_gcc_qupv3_wrap0_core_clk = { 1080 .halt_reg = 0x2600c, 1081 .halt_check = BRANCH_HALT_VOTED, 1082 .clkr = { 1083 .enable_reg = 0x57000, 1084 .enable_mask = BIT(14), 1085 .hw.init = &(const struct clk_init_data) { 1086 .name = "se_gcc_qupv3_wrap0_core_clk", 1087 .ops = &clk_branch2_ops, 1088 }, 1089 }, 1090 }; 1091 1092 static struct clk_branch se_gcc_qupv3_wrap0_m_ahb_clk = { 1093 .halt_reg = 0x26004, 1094 .halt_check = BRANCH_HALT_VOTED, 1095 .hwcg_reg = 0x26004, 1096 .hwcg_bit = 1, 1097 .clkr = { 1098 .enable_reg = 0x57000, 1099 .enable_mask = BIT(12), 1100 .hw.init = &(const struct clk_init_data) { 1101 .name = "se_gcc_qupv3_wrap0_m_ahb_clk", 1102 .ops = &clk_branch2_ops, 1103 }, 1104 }, 1105 }; 1106 1107 static struct clk_branch se_gcc_qupv3_wrap0_s0_clk = { 1108 .halt_reg = 0x2615c, 1109 .halt_check = BRANCH_HALT_VOTED, 1110 .clkr = { 1111 .enable_reg = 0x57000, 1112 .enable_mask = BIT(16), 1113 .hw.init = &(const struct clk_init_data) { 1114 .name = "se_gcc_qupv3_wrap0_s0_clk", 1115 .parent_hws = (const struct clk_hw*[]) { 1116 &se_gcc_qupv3_wrap0_s0_clk_src.clkr.hw, 1117 }, 1118 .num_parents = 1, 1119 .flags = CLK_SET_RATE_PARENT, 1120 .ops = &clk_branch2_ops, 1121 }, 1122 }, 1123 }; 1124 1125 static struct clk_branch se_gcc_qupv3_wrap0_s1_clk = { 1126 .halt_reg = 0x26298, 1127 .halt_check = BRANCH_HALT_VOTED, 1128 .clkr = { 1129 .enable_reg = 0x57000, 1130 .enable_mask = BIT(17), 1131 .hw.init = &(const struct clk_init_data) { 1132 .name = "se_gcc_qupv3_wrap0_s1_clk", 1133 .parent_hws = (const struct clk_hw*[]) { 1134 &se_gcc_qupv3_wrap0_s1_clk_src.clkr.hw, 1135 }, 1136 .num_parents = 1, 1137 .flags = CLK_SET_RATE_PARENT, 1138 .ops = &clk_branch2_ops, 1139 }, 1140 }, 1141 }; 1142 1143 static struct clk_branch se_gcc_qupv3_wrap0_s2_clk = { 1144 .halt_reg = 0x263d4, 1145 .halt_check = BRANCH_HALT_VOTED, 1146 .clkr = { 1147 .enable_reg = 0x57000, 1148 .enable_mask = BIT(18), 1149 .hw.init = &(const struct clk_init_data) { 1150 .name = "se_gcc_qupv3_wrap0_s2_clk", 1151 .parent_hws = (const struct clk_hw*[]) { 1152 &se_gcc_qupv3_wrap0_s2_clk_src.clkr.hw, 1153 }, 1154 .num_parents = 1, 1155 .flags = CLK_SET_RATE_PARENT, 1156 .ops = &clk_branch2_ops, 1157 }, 1158 }, 1159 }; 1160 1161 static struct clk_branch se_gcc_qupv3_wrap0_s3_clk = { 1162 .halt_reg = 0x26510, 1163 .halt_check = BRANCH_HALT_VOTED, 1164 .clkr = { 1165 .enable_reg = 0x57000, 1166 .enable_mask = BIT(19), 1167 .hw.init = &(const struct clk_init_data) { 1168 .name = "se_gcc_qupv3_wrap0_s3_clk", 1169 .parent_hws = (const struct clk_hw*[]) { 1170 &se_gcc_qupv3_wrap0_s3_clk_src.clkr.hw, 1171 }, 1172 .num_parents = 1, 1173 .flags = CLK_SET_RATE_PARENT, 1174 .ops = &clk_branch2_ops, 1175 }, 1176 }, 1177 }; 1178 1179 static struct clk_branch se_gcc_qupv3_wrap0_s4_clk = { 1180 .halt_reg = 0x2664c, 1181 .halt_check = BRANCH_HALT_VOTED, 1182 .clkr = { 1183 .enable_reg = 0x57000, 1184 .enable_mask = BIT(20), 1185 .hw.init = &(const struct clk_init_data) { 1186 .name = "se_gcc_qupv3_wrap0_s4_clk", 1187 .parent_hws = (const struct clk_hw*[]) { 1188 &se_gcc_qupv3_wrap0_s4_clk_src.clkr.hw, 1189 }, 1190 .num_parents = 1, 1191 .flags = CLK_SET_RATE_PARENT, 1192 .ops = &clk_branch2_ops, 1193 }, 1194 }, 1195 }; 1196 1197 static struct clk_branch se_gcc_qupv3_wrap0_s5_clk = { 1198 .halt_reg = 0x26788, 1199 .halt_check = BRANCH_HALT_VOTED, 1200 .clkr = { 1201 .enable_reg = 0x57000, 1202 .enable_mask = BIT(21), 1203 .hw.init = &(const struct clk_init_data) { 1204 .name = "se_gcc_qupv3_wrap0_s5_clk", 1205 .parent_hws = (const struct clk_hw*[]) { 1206 &se_gcc_qupv3_wrap0_s5_clk_src.clkr.hw, 1207 }, 1208 .num_parents = 1, 1209 .flags = CLK_SET_RATE_PARENT, 1210 .ops = &clk_branch2_ops, 1211 }, 1212 }, 1213 }; 1214 1215 static struct clk_branch se_gcc_qupv3_wrap0_s6_clk = { 1216 .halt_reg = 0x268c4, 1217 .halt_check = BRANCH_HALT_VOTED, 1218 .clkr = { 1219 .enable_reg = 0x57000, 1220 .enable_mask = BIT(22), 1221 .hw.init = &(const struct clk_init_data) { 1222 .name = "se_gcc_qupv3_wrap0_s6_clk", 1223 .parent_hws = (const struct clk_hw*[]) { 1224 &se_gcc_qupv3_wrap0_s6_clk_src.clkr.hw, 1225 }, 1226 .num_parents = 1, 1227 .flags = CLK_SET_RATE_PARENT, 1228 .ops = &clk_branch2_ops, 1229 }, 1230 }, 1231 }; 1232 1233 static struct clk_branch se_gcc_qupv3_wrap0_s_ahb_clk = { 1234 .halt_reg = 0x26008, 1235 .halt_check = BRANCH_HALT_VOTED, 1236 .hwcg_reg = 0x26008, 1237 .hwcg_bit = 1, 1238 .clkr = { 1239 .enable_reg = 0x57000, 1240 .enable_mask = BIT(13), 1241 .hw.init = &(const struct clk_init_data) { 1242 .name = "se_gcc_qupv3_wrap0_s_ahb_clk", 1243 .ops = &clk_branch2_ops, 1244 }, 1245 }, 1246 }; 1247 1248 static struct clk_branch se_gcc_qupv3_wrap1_core_2x_clk = { 1249 .halt_reg = 0x27020, 1250 .halt_check = BRANCH_HALT_VOTED, 1251 .clkr = { 1252 .enable_reg = 0x57000, 1253 .enable_mask = BIT(26), 1254 .hw.init = &(const struct clk_init_data) { 1255 .name = "se_gcc_qupv3_wrap1_core_2x_clk", 1256 .ops = &clk_branch2_ops, 1257 }, 1258 }, 1259 }; 1260 1261 static struct clk_branch se_gcc_qupv3_wrap1_core_clk = { 1262 .halt_reg = 0x2700c, 1263 .halt_check = BRANCH_HALT_VOTED, 1264 .clkr = { 1265 .enable_reg = 0x57000, 1266 .enable_mask = BIT(25), 1267 .hw.init = &(const struct clk_init_data) { 1268 .name = "se_gcc_qupv3_wrap1_core_clk", 1269 .ops = &clk_branch2_ops, 1270 }, 1271 }, 1272 }; 1273 1274 static struct clk_branch se_gcc_qupv3_wrap1_m_ahb_clk = { 1275 .halt_reg = 0x27004, 1276 .halt_check = BRANCH_HALT_VOTED, 1277 .hwcg_reg = 0x27004, 1278 .hwcg_bit = 1, 1279 .clkr = { 1280 .enable_reg = 0x57000, 1281 .enable_mask = BIT(23), 1282 .hw.init = &(const struct clk_init_data) { 1283 .name = "se_gcc_qupv3_wrap1_m_ahb_clk", 1284 .ops = &clk_branch2_ops, 1285 }, 1286 }, 1287 }; 1288 1289 static struct clk_branch se_gcc_qupv3_wrap1_s0_clk = { 1290 .halt_reg = 0x2715c, 1291 .halt_check = BRANCH_HALT_VOTED, 1292 .clkr = { 1293 .enable_reg = 0x57000, 1294 .enable_mask = BIT(27), 1295 .hw.init = &(const struct clk_init_data) { 1296 .name = "se_gcc_qupv3_wrap1_s0_clk", 1297 .parent_hws = (const struct clk_hw*[]) { 1298 &se_gcc_qupv3_wrap1_s0_clk_src.clkr.hw, 1299 }, 1300 .num_parents = 1, 1301 .flags = CLK_SET_RATE_PARENT, 1302 .ops = &clk_branch2_ops, 1303 }, 1304 }, 1305 }; 1306 1307 static struct clk_branch se_gcc_qupv3_wrap1_s1_clk = { 1308 .halt_reg = 0x27298, 1309 .halt_check = BRANCH_HALT_VOTED, 1310 .clkr = { 1311 .enable_reg = 0x57000, 1312 .enable_mask = BIT(28), 1313 .hw.init = &(const struct clk_init_data) { 1314 .name = "se_gcc_qupv3_wrap1_s1_clk", 1315 .parent_hws = (const struct clk_hw*[]) { 1316 &se_gcc_qupv3_wrap1_s1_clk_src.clkr.hw, 1317 }, 1318 .num_parents = 1, 1319 .flags = CLK_SET_RATE_PARENT, 1320 .ops = &clk_branch2_ops, 1321 }, 1322 }, 1323 }; 1324 1325 static struct clk_branch se_gcc_qupv3_wrap1_s2_clk = { 1326 .halt_reg = 0x273d4, 1327 .halt_check = BRANCH_HALT_VOTED, 1328 .clkr = { 1329 .enable_reg = 0x57000, 1330 .enable_mask = BIT(29), 1331 .hw.init = &(const struct clk_init_data) { 1332 .name = "se_gcc_qupv3_wrap1_s2_clk", 1333 .parent_hws = (const struct clk_hw*[]) { 1334 &se_gcc_qupv3_wrap1_s2_clk_src.clkr.hw, 1335 }, 1336 .num_parents = 1, 1337 .flags = CLK_SET_RATE_PARENT, 1338 .ops = &clk_branch2_ops, 1339 }, 1340 }, 1341 }; 1342 1343 static struct clk_branch se_gcc_qupv3_wrap1_s3_clk = { 1344 .halt_reg = 0x27510, 1345 .halt_check = BRANCH_HALT_VOTED, 1346 .clkr = { 1347 .enable_reg = 0x57000, 1348 .enable_mask = BIT(30), 1349 .hw.init = &(const struct clk_init_data) { 1350 .name = "se_gcc_qupv3_wrap1_s3_clk", 1351 .parent_hws = (const struct clk_hw*[]) { 1352 &se_gcc_qupv3_wrap1_s3_clk_src.clkr.hw, 1353 }, 1354 .num_parents = 1, 1355 .flags = CLK_SET_RATE_PARENT, 1356 .ops = &clk_branch2_ops, 1357 }, 1358 }, 1359 }; 1360 1361 static struct clk_branch se_gcc_qupv3_wrap1_s4_clk = { 1362 .halt_reg = 0x2764c, 1363 .halt_check = BRANCH_HALT_VOTED, 1364 .clkr = { 1365 .enable_reg = 0x57000, 1366 .enable_mask = BIT(31), 1367 .hw.init = &(const struct clk_init_data) { 1368 .name = "se_gcc_qupv3_wrap1_s4_clk", 1369 .parent_hws = (const struct clk_hw*[]) { 1370 &se_gcc_qupv3_wrap1_s4_clk_src.clkr.hw, 1371 }, 1372 .num_parents = 1, 1373 .flags = CLK_SET_RATE_PARENT, 1374 .ops = &clk_branch2_ops, 1375 }, 1376 }, 1377 }; 1378 1379 static struct clk_branch se_gcc_qupv3_wrap1_s5_clk = { 1380 .halt_reg = 0x27788, 1381 .halt_check = BRANCH_HALT_VOTED, 1382 .clkr = { 1383 .enable_reg = 0x57008, 1384 .enable_mask = BIT(0), 1385 .hw.init = &(const struct clk_init_data) { 1386 .name = "se_gcc_qupv3_wrap1_s5_clk", 1387 .parent_hws = (const struct clk_hw*[]) { 1388 &se_gcc_qupv3_wrap1_s5_clk_src.clkr.hw, 1389 }, 1390 .num_parents = 1, 1391 .flags = CLK_SET_RATE_PARENT, 1392 .ops = &clk_branch2_ops, 1393 }, 1394 }, 1395 }; 1396 1397 static struct clk_branch se_gcc_qupv3_wrap1_s6_clk = { 1398 .halt_reg = 0x278c4, 1399 .halt_check = BRANCH_HALT_VOTED, 1400 .clkr = { 1401 .enable_reg = 0x57008, 1402 .enable_mask = BIT(1), 1403 .hw.init = &(const struct clk_init_data) { 1404 .name = "se_gcc_qupv3_wrap1_s6_clk", 1405 .parent_hws = (const struct clk_hw*[]) { 1406 &se_gcc_qupv3_wrap1_s6_clk_src.clkr.hw, 1407 }, 1408 .num_parents = 1, 1409 .flags = CLK_SET_RATE_PARENT, 1410 .ops = &clk_branch2_ops, 1411 }, 1412 }, 1413 }; 1414 1415 static struct clk_branch se_gcc_qupv3_wrap1_s_ahb_clk = { 1416 .halt_reg = 0x27008, 1417 .halt_check = BRANCH_HALT_VOTED, 1418 .hwcg_reg = 0x27008, 1419 .hwcg_bit = 1, 1420 .clkr = { 1421 .enable_reg = 0x57000, 1422 .enable_mask = BIT(24), 1423 .hw.init = &(const struct clk_init_data) { 1424 .name = "se_gcc_qupv3_wrap1_s_ahb_clk", 1425 .ops = &clk_branch2_ops, 1426 }, 1427 }, 1428 }; 1429 1430 static struct gdsc se_gcc_emac0_gdsc = { 1431 .gdscr = 0x24004, 1432 .en_rest_wait_val = 0x2, 1433 .en_few_wait_val = 0x2, 1434 .clk_dis_wait_val = 0xf, 1435 .pd = { 1436 .name = "se_gcc_emac0_gdsc", 1437 }, 1438 .pwrsts = PWRSTS_OFF_ON, 1439 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 1440 }; 1441 1442 static struct gdsc se_gcc_emac1_gdsc = { 1443 .gdscr = 0x25004, 1444 .en_rest_wait_val = 0x2, 1445 .en_few_wait_val = 0x2, 1446 .clk_dis_wait_val = 0xf, 1447 .pd = { 1448 .name = "se_gcc_emac1_gdsc", 1449 }, 1450 .pwrsts = PWRSTS_OFF_ON, 1451 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 1452 }; 1453 1454 static struct clk_regmap *se_gcc_nord_clocks[] = { 1455 [SE_GCC_EEE_EMAC0_CLK] = &se_gcc_eee_emac0_clk.clkr, 1456 [SE_GCC_EEE_EMAC0_CLK_SRC] = &se_gcc_eee_emac0_clk_src.clkr, 1457 [SE_GCC_EEE_EMAC1_CLK] = &se_gcc_eee_emac1_clk.clkr, 1458 [SE_GCC_EEE_EMAC1_CLK_SRC] = &se_gcc_eee_emac1_clk_src.clkr, 1459 [SE_GCC_EMAC0_AXI_CLK] = &se_gcc_emac0_axi_clk.clkr, 1460 [SE_GCC_EMAC0_CC_SGMIIPHY_RX_CLK] = &se_gcc_emac0_cc_sgmiiphy_rx_clk.clkr, 1461 [SE_GCC_EMAC0_CC_SGMIIPHY_TX_CLK] = &se_gcc_emac0_cc_sgmiiphy_tx_clk.clkr, 1462 [SE_GCC_EMAC0_PHY_AUX_CLK] = &se_gcc_emac0_phy_aux_clk.clkr, 1463 [SE_GCC_EMAC0_PHY_AUX_CLK_SRC] = &se_gcc_emac0_phy_aux_clk_src.clkr, 1464 [SE_GCC_EMAC0_PTP_CLK] = &se_gcc_emac0_ptp_clk.clkr, 1465 [SE_GCC_EMAC0_PTP_CLK_SRC] = &se_gcc_emac0_ptp_clk_src.clkr, 1466 [SE_GCC_EMAC0_RGMII_CLK] = &se_gcc_emac0_rgmii_clk.clkr, 1467 [SE_GCC_EMAC0_RGMII_CLK_SRC] = &se_gcc_emac0_rgmii_clk_src.clkr, 1468 [SE_GCC_EMAC0_RPCS_RX_CLK] = &se_gcc_emac0_rpcs_rx_clk.clkr, 1469 [SE_GCC_EMAC0_RPCS_TX_CLK] = &se_gcc_emac0_rpcs_tx_clk.clkr, 1470 [SE_GCC_EMAC0_XGXS_RX_CLK] = &se_gcc_emac0_xgxs_rx_clk.clkr, 1471 [SE_GCC_EMAC0_XGXS_TX_CLK] = &se_gcc_emac0_xgxs_tx_clk.clkr, 1472 [SE_GCC_EMAC1_AXI_CLK] = &se_gcc_emac1_axi_clk.clkr, 1473 [SE_GCC_EMAC1_CC_SGMIIPHY_RX_CLK] = &se_gcc_emac1_cc_sgmiiphy_rx_clk.clkr, 1474 [SE_GCC_EMAC1_CC_SGMIIPHY_TX_CLK] = &se_gcc_emac1_cc_sgmiiphy_tx_clk.clkr, 1475 [SE_GCC_EMAC1_PHY_AUX_CLK] = &se_gcc_emac1_phy_aux_clk.clkr, 1476 [SE_GCC_EMAC1_PHY_AUX_CLK_SRC] = &se_gcc_emac1_phy_aux_clk_src.clkr, 1477 [SE_GCC_EMAC1_PTP_CLK] = &se_gcc_emac1_ptp_clk.clkr, 1478 [SE_GCC_EMAC1_PTP_CLK_SRC] = &se_gcc_emac1_ptp_clk_src.clkr, 1479 [SE_GCC_EMAC1_RGMII_CLK] = &se_gcc_emac1_rgmii_clk.clkr, 1480 [SE_GCC_EMAC1_RGMII_CLK_SRC] = &se_gcc_emac1_rgmii_clk_src.clkr, 1481 [SE_GCC_EMAC1_RPCS_RX_CLK] = &se_gcc_emac1_rpcs_rx_clk.clkr, 1482 [SE_GCC_EMAC1_RPCS_TX_CLK] = &se_gcc_emac1_rpcs_tx_clk.clkr, 1483 [SE_GCC_EMAC1_XGXS_RX_CLK] = &se_gcc_emac1_xgxs_rx_clk.clkr, 1484 [SE_GCC_EMAC1_XGXS_TX_CLK] = &se_gcc_emac1_xgxs_tx_clk.clkr, 1485 [SE_GCC_FRQ_MEASURE_REF_CLK] = &se_gcc_frq_measure_ref_clk.clkr, 1486 [SE_GCC_GP1_CLK] = &se_gcc_gp1_clk.clkr, 1487 [SE_GCC_GP1_CLK_SRC] = &se_gcc_gp1_clk_src.clkr, 1488 [SE_GCC_GP2_CLK] = &se_gcc_gp2_clk.clkr, 1489 [SE_GCC_GP2_CLK_SRC] = &se_gcc_gp2_clk_src.clkr, 1490 [SE_GCC_GPLL0] = &se_gcc_gpll0.clkr, 1491 [SE_GCC_GPLL0_OUT_EVEN] = &se_gcc_gpll0_out_even.clkr, 1492 [SE_GCC_GPLL2] = &se_gcc_gpll2.clkr, 1493 [SE_GCC_GPLL4] = &se_gcc_gpll4.clkr, 1494 [SE_GCC_GPLL5] = &se_gcc_gpll5.clkr, 1495 [SE_GCC_MMU_2_TCU_VOTE_CLK] = &se_gcc_mmu_2_tcu_vote_clk.clkr, 1496 [SE_GCC_QUPV3_WRAP0_CORE_2X_CLK] = &se_gcc_qupv3_wrap0_core_2x_clk.clkr, 1497 [SE_GCC_QUPV3_WRAP0_CORE_CLK] = &se_gcc_qupv3_wrap0_core_clk.clkr, 1498 [SE_GCC_QUPV3_WRAP0_M_AHB_CLK] = &se_gcc_qupv3_wrap0_m_ahb_clk.clkr, 1499 [SE_GCC_QUPV3_WRAP0_S0_CLK] = &se_gcc_qupv3_wrap0_s0_clk.clkr, 1500 [SE_GCC_QUPV3_WRAP0_S0_CLK_SRC] = &se_gcc_qupv3_wrap0_s0_clk_src.clkr, 1501 [SE_GCC_QUPV3_WRAP0_S1_CLK] = &se_gcc_qupv3_wrap0_s1_clk.clkr, 1502 [SE_GCC_QUPV3_WRAP0_S1_CLK_SRC] = &se_gcc_qupv3_wrap0_s1_clk_src.clkr, 1503 [SE_GCC_QUPV3_WRAP0_S2_CLK] = &se_gcc_qupv3_wrap0_s2_clk.clkr, 1504 [SE_GCC_QUPV3_WRAP0_S2_CLK_SRC] = &se_gcc_qupv3_wrap0_s2_clk_src.clkr, 1505 [SE_GCC_QUPV3_WRAP0_S3_CLK] = &se_gcc_qupv3_wrap0_s3_clk.clkr, 1506 [SE_GCC_QUPV3_WRAP0_S3_CLK_SRC] = &se_gcc_qupv3_wrap0_s3_clk_src.clkr, 1507 [SE_GCC_QUPV3_WRAP0_S4_CLK] = &se_gcc_qupv3_wrap0_s4_clk.clkr, 1508 [SE_GCC_QUPV3_WRAP0_S4_CLK_SRC] = &se_gcc_qupv3_wrap0_s4_clk_src.clkr, 1509 [SE_GCC_QUPV3_WRAP0_S5_CLK] = &se_gcc_qupv3_wrap0_s5_clk.clkr, 1510 [SE_GCC_QUPV3_WRAP0_S5_CLK_SRC] = &se_gcc_qupv3_wrap0_s5_clk_src.clkr, 1511 [SE_GCC_QUPV3_WRAP0_S6_CLK] = &se_gcc_qupv3_wrap0_s6_clk.clkr, 1512 [SE_GCC_QUPV3_WRAP0_S6_CLK_SRC] = &se_gcc_qupv3_wrap0_s6_clk_src.clkr, 1513 [SE_GCC_QUPV3_WRAP0_S_AHB_CLK] = &se_gcc_qupv3_wrap0_s_ahb_clk.clkr, 1514 [SE_GCC_QUPV3_WRAP1_CORE_2X_CLK] = &se_gcc_qupv3_wrap1_core_2x_clk.clkr, 1515 [SE_GCC_QUPV3_WRAP1_CORE_CLK] = &se_gcc_qupv3_wrap1_core_clk.clkr, 1516 [SE_GCC_QUPV3_WRAP1_M_AHB_CLK] = &se_gcc_qupv3_wrap1_m_ahb_clk.clkr, 1517 [SE_GCC_QUPV3_WRAP1_S0_CLK] = &se_gcc_qupv3_wrap1_s0_clk.clkr, 1518 [SE_GCC_QUPV3_WRAP1_S0_CLK_SRC] = &se_gcc_qupv3_wrap1_s0_clk_src.clkr, 1519 [SE_GCC_QUPV3_WRAP1_S1_CLK] = &se_gcc_qupv3_wrap1_s1_clk.clkr, 1520 [SE_GCC_QUPV3_WRAP1_S1_CLK_SRC] = &se_gcc_qupv3_wrap1_s1_clk_src.clkr, 1521 [SE_GCC_QUPV3_WRAP1_S2_CLK] = &se_gcc_qupv3_wrap1_s2_clk.clkr, 1522 [SE_GCC_QUPV3_WRAP1_S2_CLK_SRC] = &se_gcc_qupv3_wrap1_s2_clk_src.clkr, 1523 [SE_GCC_QUPV3_WRAP1_S3_CLK] = &se_gcc_qupv3_wrap1_s3_clk.clkr, 1524 [SE_GCC_QUPV3_WRAP1_S3_CLK_SRC] = &se_gcc_qupv3_wrap1_s3_clk_src.clkr, 1525 [SE_GCC_QUPV3_WRAP1_S4_CLK] = &se_gcc_qupv3_wrap1_s4_clk.clkr, 1526 [SE_GCC_QUPV3_WRAP1_S4_CLK_SRC] = &se_gcc_qupv3_wrap1_s4_clk_src.clkr, 1527 [SE_GCC_QUPV3_WRAP1_S5_CLK] = &se_gcc_qupv3_wrap1_s5_clk.clkr, 1528 [SE_GCC_QUPV3_WRAP1_S5_CLK_SRC] = &se_gcc_qupv3_wrap1_s5_clk_src.clkr, 1529 [SE_GCC_QUPV3_WRAP1_S6_CLK] = &se_gcc_qupv3_wrap1_s6_clk.clkr, 1530 [SE_GCC_QUPV3_WRAP1_S6_CLK_SRC] = &se_gcc_qupv3_wrap1_s6_clk_src.clkr, 1531 [SE_GCC_QUPV3_WRAP1_S_AHB_CLK] = &se_gcc_qupv3_wrap1_s_ahb_clk.clkr, 1532 }; 1533 1534 static struct gdsc *se_gcc_nord_gdscs[] = { 1535 [SE_GCC_EMAC0_GDSC] = &se_gcc_emac0_gdsc, 1536 [SE_GCC_EMAC1_GDSC] = &se_gcc_emac1_gdsc, 1537 }; 1538 1539 static const struct qcom_reset_map se_gcc_nord_resets[] = { 1540 [SE_GCC_EMAC0_BCR] = { 0x24000 }, 1541 [SE_GCC_EMAC1_BCR] = { 0x25000 }, 1542 [SE_GCC_QUPV3_WRAPPER_0_BCR] = { 0x26000 }, 1543 [SE_GCC_QUPV3_WRAPPER_1_BCR] = { 0x27000 }, 1544 }; 1545 1546 static const struct clk_rcg_dfs_data se_gcc_nord_dfs_clocks[] = { 1547 DEFINE_RCG_DFS(se_gcc_qupv3_wrap0_s0_clk_src), 1548 DEFINE_RCG_DFS(se_gcc_qupv3_wrap0_s1_clk_src), 1549 DEFINE_RCG_DFS(se_gcc_qupv3_wrap0_s2_clk_src), 1550 DEFINE_RCG_DFS(se_gcc_qupv3_wrap0_s3_clk_src), 1551 DEFINE_RCG_DFS(se_gcc_qupv3_wrap0_s4_clk_src), 1552 DEFINE_RCG_DFS(se_gcc_qupv3_wrap0_s5_clk_src), 1553 DEFINE_RCG_DFS(se_gcc_qupv3_wrap0_s6_clk_src), 1554 DEFINE_RCG_DFS(se_gcc_qupv3_wrap1_s0_clk_src), 1555 DEFINE_RCG_DFS(se_gcc_qupv3_wrap1_s1_clk_src), 1556 DEFINE_RCG_DFS(se_gcc_qupv3_wrap1_s2_clk_src), 1557 DEFINE_RCG_DFS(se_gcc_qupv3_wrap1_s3_clk_src), 1558 DEFINE_RCG_DFS(se_gcc_qupv3_wrap1_s4_clk_src), 1559 DEFINE_RCG_DFS(se_gcc_qupv3_wrap1_s5_clk_src), 1560 DEFINE_RCG_DFS(se_gcc_qupv3_wrap1_s6_clk_src), 1561 }; 1562 1563 static const struct regmap_config se_gcc_nord_regmap_config = { 1564 .reg_bits = 32, 1565 .reg_stride = 4, 1566 .val_bits = 32, 1567 .max_register = 0xf41f0, 1568 .fast_io = true, 1569 }; 1570 1571 static struct qcom_cc_driver_data se_gcc_nord_driver_data = { 1572 .dfs_rcgs = se_gcc_nord_dfs_clocks, 1573 .num_dfs_rcgs = ARRAY_SIZE(se_gcc_nord_dfs_clocks), 1574 }; 1575 1576 static const struct qcom_cc_desc se_gcc_nord_desc = { 1577 .config = &se_gcc_nord_regmap_config, 1578 .clks = se_gcc_nord_clocks, 1579 .num_clks = ARRAY_SIZE(se_gcc_nord_clocks), 1580 .resets = se_gcc_nord_resets, 1581 .num_resets = ARRAY_SIZE(se_gcc_nord_resets), 1582 .gdscs = se_gcc_nord_gdscs, 1583 .num_gdscs = ARRAY_SIZE(se_gcc_nord_gdscs), 1584 .driver_data = &se_gcc_nord_driver_data, 1585 }; 1586 1587 static const struct of_device_id se_gcc_nord_match_table[] = { 1588 { .compatible = "qcom,nord-segcc" }, 1589 { } 1590 }; 1591 MODULE_DEVICE_TABLE(of, se_gcc_nord_match_table); 1592 1593 static int se_gcc_nord_probe(struct platform_device *pdev) 1594 { 1595 return qcom_cc_probe(pdev, &se_gcc_nord_desc); 1596 } 1597 1598 static struct platform_driver se_gcc_nord_driver = { 1599 .probe = se_gcc_nord_probe, 1600 .driver = { 1601 .name = "segcc-nord", 1602 .of_match_table = se_gcc_nord_match_table, 1603 }, 1604 }; 1605 1606 module_platform_driver(se_gcc_nord_driver); 1607 1608 MODULE_DESCRIPTION("QTI SEGCC NORD Driver"); 1609 MODULE_LICENSE("GPL"); 1610