1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 4 */ 5 6 #include <linux/clk-provider.h> 7 #include <linux/module.h> 8 #include <linux/platform_device.h> 9 #include <linux/regmap.h> 10 11 #include <dt-bindings/clock/qcom,nord-negcc.h> 12 13 #include "clk-alpha-pll.h" 14 #include "clk-branch.h" 15 #include "clk-pll.h" 16 #include "clk-rcg.h" 17 #include "clk-regmap.h" 18 #include "clk-regmap-divider.h" 19 #include "clk-regmap-phy-mux.h" 20 #include "common.h" 21 #include "gdsc.h" 22 #include "reset.h" 23 24 enum { 25 DT_BI_TCXO, 26 DT_SLEEP_CLK, 27 DT_UFS_PHY_RX_SYMBOL_0_CLK, 28 DT_UFS_PHY_RX_SYMBOL_1_CLK, 29 DT_UFS_PHY_TX_SYMBOL_0_CLK, 30 DT_USB3_PHY_SEC_WRAPPER_NE_GCC_USB31_PIPE_CLK, 31 DT_USB3_PHY_WRAPPER_NE_GCC_USB31_PIPE_CLK, 32 }; 33 34 enum { 35 P_BI_TCXO, 36 P_NE_GCC_GPLL0_OUT_EVEN, 37 P_NE_GCC_GPLL0_OUT_MAIN, 38 P_NE_GCC_GPLL2_OUT_MAIN, 39 P_SLEEP_CLK, 40 P_UFS_PHY_RX_SYMBOL_0_CLK, 41 P_UFS_PHY_RX_SYMBOL_1_CLK, 42 P_UFS_PHY_TX_SYMBOL_0_CLK, 43 }; 44 45 static struct clk_alpha_pll ne_gcc_gpll0 = { 46 .offset = 0x0, 47 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 48 .clkr = { 49 .enable_reg = 0x0, 50 .enable_mask = BIT(0), 51 .hw.init = &(const struct clk_init_data) { 52 .name = "ne_gcc_gpll0", 53 .parent_data = &(const struct clk_parent_data) { 54 .index = DT_BI_TCXO, 55 }, 56 .num_parents = 1, 57 .ops = &clk_alpha_pll_fixed_lucid_ole_ops, 58 }, 59 }, 60 }; 61 62 static const struct clk_div_table post_div_table_ne_gcc_gpll0_out_even[] = { 63 { 0x1, 2 }, 64 { } 65 }; 66 67 static struct clk_alpha_pll_postdiv ne_gcc_gpll0_out_even = { 68 .offset = 0x0, 69 .post_div_shift = 10, 70 .post_div_table = post_div_table_ne_gcc_gpll0_out_even, 71 .num_post_div = ARRAY_SIZE(post_div_table_ne_gcc_gpll0_out_even), 72 .width = 4, 73 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 74 .clkr.hw.init = &(const struct clk_init_data) { 75 .name = "ne_gcc_gpll0_out_even", 76 .parent_hws = (const struct clk_hw*[]) { 77 &ne_gcc_gpll0.clkr.hw, 78 }, 79 .num_parents = 1, 80 .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, 81 }, 82 }; 83 84 static struct clk_alpha_pll ne_gcc_gpll2 = { 85 .offset = 0x2000, 86 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 87 .clkr = { 88 .enable_reg = 0x0, 89 .enable_mask = BIT(2), 90 .hw.init = &(const struct clk_init_data) { 91 .name = "ne_gcc_gpll2", 92 .parent_data = &(const struct clk_parent_data) { 93 .index = DT_BI_TCXO, 94 }, 95 .num_parents = 1, 96 .ops = &clk_alpha_pll_fixed_lucid_ole_ops, 97 }, 98 }, 99 }; 100 101 static const struct parent_map ne_gcc_parent_map_0[] = { 102 { P_BI_TCXO, 0 }, 103 { P_NE_GCC_GPLL0_OUT_MAIN, 1 }, 104 }; 105 106 static const struct clk_parent_data ne_gcc_parent_data_0[] = { 107 { .index = DT_BI_TCXO }, 108 { .hw = &ne_gcc_gpll0.clkr.hw }, 109 }; 110 111 static const struct parent_map ne_gcc_parent_map_1[] = { 112 { P_BI_TCXO, 0 }, 113 { P_NE_GCC_GPLL0_OUT_MAIN, 1 }, 114 { P_NE_GCC_GPLL0_OUT_EVEN, 5 }, 115 }; 116 117 static const struct clk_parent_data ne_gcc_parent_data_1[] = { 118 { .index = DT_BI_TCXO }, 119 { .hw = &ne_gcc_gpll0.clkr.hw }, 120 { .hw = &ne_gcc_gpll0_out_even.clkr.hw }, 121 }; 122 123 static const struct parent_map ne_gcc_parent_map_2[] = { 124 { P_BI_TCXO, 0 }, 125 { P_NE_GCC_GPLL0_OUT_MAIN, 1 }, 126 { P_NE_GCC_GPLL2_OUT_MAIN, 3 }, 127 }; 128 129 static const struct clk_parent_data ne_gcc_parent_data_2[] = { 130 { .index = DT_BI_TCXO }, 131 { .hw = &ne_gcc_gpll0.clkr.hw }, 132 { .hw = &ne_gcc_gpll2.clkr.hw }, 133 }; 134 135 static const struct parent_map ne_gcc_parent_map_3[] = { 136 { P_BI_TCXO, 0 }, 137 { P_SLEEP_CLK, 5 }, 138 }; 139 140 static const struct clk_parent_data ne_gcc_parent_data_3[] = { 141 { .index = DT_BI_TCXO }, 142 { .index = DT_SLEEP_CLK }, 143 }; 144 145 static const struct parent_map ne_gcc_parent_map_4[] = { 146 { P_BI_TCXO, 0 }, 147 { P_NE_GCC_GPLL0_OUT_MAIN, 1 }, 148 { P_SLEEP_CLK, 5 }, 149 }; 150 151 static const struct clk_parent_data ne_gcc_parent_data_4[] = { 152 { .index = DT_BI_TCXO }, 153 { .hw = &ne_gcc_gpll0.clkr.hw }, 154 { .index = DT_SLEEP_CLK }, 155 }; 156 157 static const struct parent_map ne_gcc_parent_map_5[] = { 158 { P_BI_TCXO, 0 }, 159 }; 160 161 static const struct clk_parent_data ne_gcc_parent_data_5[] = { 162 { .index = DT_BI_TCXO }, 163 }; 164 165 static struct clk_regmap_phy_mux ne_gcc_ufs_phy_rx_symbol_0_clk_src = { 166 .reg = 0x33068, 167 .clkr = { 168 .hw.init = &(const struct clk_init_data) { 169 .name = "ne_gcc_ufs_phy_rx_symbol_0_clk_src", 170 .parent_data = &(const struct clk_parent_data){ 171 .index = DT_UFS_PHY_RX_SYMBOL_0_CLK, 172 }, 173 .num_parents = 1, 174 .ops = &clk_regmap_phy_mux_ops, 175 }, 176 }, 177 }; 178 179 static struct clk_regmap_phy_mux ne_gcc_ufs_phy_rx_symbol_1_clk_src = { 180 .reg = 0x330f0, 181 .clkr = { 182 .hw.init = &(const struct clk_init_data) { 183 .name = "ne_gcc_ufs_phy_rx_symbol_1_clk_src", 184 .parent_data = &(const struct clk_parent_data){ 185 .index = DT_UFS_PHY_RX_SYMBOL_1_CLK, 186 }, 187 .num_parents = 1, 188 .ops = &clk_regmap_phy_mux_ops, 189 }, 190 }, 191 }; 192 193 static struct clk_regmap_phy_mux ne_gcc_ufs_phy_tx_symbol_0_clk_src = { 194 .reg = 0x33058, 195 .clkr = { 196 .hw.init = &(const struct clk_init_data) { 197 .name = "ne_gcc_ufs_phy_tx_symbol_0_clk_src", 198 .parent_data = &(const struct clk_parent_data){ 199 .index = DT_UFS_PHY_TX_SYMBOL_0_CLK, 200 }, 201 .num_parents = 1, 202 .ops = &clk_regmap_phy_mux_ops, 203 }, 204 }, 205 }; 206 207 static struct clk_regmap_phy_mux ne_gcc_usb3_prim_phy_pipe_clk_src = { 208 .reg = 0x2a078, 209 .clkr = { 210 .hw.init = &(const struct clk_init_data) { 211 .name = "ne_gcc_usb3_prim_phy_pipe_clk_src", 212 .parent_data = &(const struct clk_parent_data){ 213 .index = DT_USB3_PHY_WRAPPER_NE_GCC_USB31_PIPE_CLK, 214 }, 215 .num_parents = 1, 216 .ops = &clk_regmap_phy_mux_ops, 217 }, 218 }, 219 }; 220 221 static struct clk_regmap_phy_mux ne_gcc_usb3_sec_phy_pipe_clk_src = { 222 .reg = 0x2c078, 223 .clkr = { 224 .hw.init = &(const struct clk_init_data) { 225 .name = "ne_gcc_usb3_sec_phy_pipe_clk_src", 226 .parent_data = &(const struct clk_parent_data){ 227 .index = DT_USB3_PHY_SEC_WRAPPER_NE_GCC_USB31_PIPE_CLK, 228 }, 229 .num_parents = 1, 230 .ops = &clk_regmap_phy_mux_ops, 231 }, 232 }, 233 }; 234 235 static const struct freq_tbl ftbl_ne_gcc_gp1_clk_src[] = { 236 F(66666667, P_NE_GCC_GPLL0_OUT_MAIN, 9, 0, 0), 237 F(100000000, P_NE_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 238 F(200000000, P_NE_GCC_GPLL0_OUT_MAIN, 3, 0, 0), 239 { } 240 }; 241 242 static struct clk_rcg2 ne_gcc_gp1_clk_src = { 243 .cmd_rcgr = 0x21004, 244 .mnd_width = 16, 245 .hid_width = 5, 246 .parent_map = ne_gcc_parent_map_4, 247 .freq_tbl = ftbl_ne_gcc_gp1_clk_src, 248 .hw_clk_ctrl = true, 249 .clkr.hw.init = &(const struct clk_init_data) { 250 .name = "ne_gcc_gp1_clk_src", 251 .parent_data = ne_gcc_parent_data_4, 252 .num_parents = ARRAY_SIZE(ne_gcc_parent_data_4), 253 .flags = CLK_SET_RATE_PARENT, 254 .ops = &clk_rcg2_shared_ops, 255 }, 256 }; 257 258 static struct clk_rcg2 ne_gcc_gp2_clk_src = { 259 .cmd_rcgr = 0x22004, 260 .mnd_width = 16, 261 .hid_width = 5, 262 .parent_map = ne_gcc_parent_map_4, 263 .freq_tbl = ftbl_ne_gcc_gp1_clk_src, 264 .hw_clk_ctrl = true, 265 .clkr.hw.init = &(const struct clk_init_data) { 266 .name = "ne_gcc_gp2_clk_src", 267 .parent_data = ne_gcc_parent_data_4, 268 .num_parents = ARRAY_SIZE(ne_gcc_parent_data_4), 269 .flags = CLK_SET_RATE_PARENT, 270 .ops = &clk_rcg2_shared_ops, 271 }, 272 }; 273 274 static const struct freq_tbl ftbl_ne_gcc_qupv3_wrap2_s0_clk_src[] = { 275 F(7372800, P_NE_GCC_GPLL0_OUT_MAIN, 1, 192, 15625), 276 F(14745600, P_NE_GCC_GPLL0_OUT_MAIN, 1, 384, 15625), 277 F(19200000, P_BI_TCXO, 1, 0, 0), 278 F(29491200, P_NE_GCC_GPLL0_OUT_MAIN, 1, 768, 15625), 279 F(32000000, P_NE_GCC_GPLL0_OUT_MAIN, 1, 4, 75), 280 F(48000000, P_NE_GCC_GPLL0_OUT_MAIN, 1, 2, 25), 281 F(51200000, P_NE_GCC_GPLL0_OUT_MAIN, 1, 32, 375), 282 F(64000000, P_NE_GCC_GPLL0_OUT_MAIN, 1, 8, 75), 283 F(66666667, P_NE_GCC_GPLL0_OUT_MAIN, 9, 0, 0), 284 F(75000000, P_NE_GCC_GPLL0_OUT_MAIN, 8, 0, 0), 285 F(80000000, P_NE_GCC_GPLL0_OUT_MAIN, 1, 2, 15), 286 F(96000000, P_NE_GCC_GPLL0_OUT_MAIN, 1, 4, 25), 287 F(100000000, P_NE_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 288 F(102400000, P_NE_GCC_GPLL0_OUT_MAIN, 1, 64, 375), 289 F(112000000, P_NE_GCC_GPLL0_OUT_MAIN, 1, 14, 75), 290 F(117964800, P_NE_GCC_GPLL0_OUT_MAIN, 1, 3072, 15625), 291 F(120000000, P_NE_GCC_GPLL0_OUT_MAIN, 5, 0, 0), 292 { } 293 }; 294 295 static struct clk_init_data ne_gcc_qupv3_wrap2_s0_clk_src_init = { 296 .name = "ne_gcc_qupv3_wrap2_s0_clk_src", 297 .parent_data = ne_gcc_parent_data_0, 298 .num_parents = ARRAY_SIZE(ne_gcc_parent_data_0), 299 .flags = CLK_SET_RATE_PARENT, 300 .ops = &clk_rcg2_shared_no_init_park_ops, 301 }; 302 303 static struct clk_rcg2 ne_gcc_qupv3_wrap2_s0_clk_src = { 304 .cmd_rcgr = 0x3816c, 305 .mnd_width = 16, 306 .hid_width = 5, 307 .parent_map = ne_gcc_parent_map_0, 308 .freq_tbl = ftbl_ne_gcc_qupv3_wrap2_s0_clk_src, 309 .hw_clk_ctrl = true, 310 .clkr.hw.init = &ne_gcc_qupv3_wrap2_s0_clk_src_init, 311 }; 312 313 static struct clk_init_data ne_gcc_qupv3_wrap2_s1_clk_src_init = { 314 .name = "ne_gcc_qupv3_wrap2_s1_clk_src", 315 .parent_data = ne_gcc_parent_data_0, 316 .num_parents = ARRAY_SIZE(ne_gcc_parent_data_0), 317 .flags = CLK_SET_RATE_PARENT, 318 .ops = &clk_rcg2_shared_no_init_park_ops, 319 }; 320 321 static struct clk_rcg2 ne_gcc_qupv3_wrap2_s1_clk_src = { 322 .cmd_rcgr = 0x382a8, 323 .mnd_width = 16, 324 .hid_width = 5, 325 .parent_map = ne_gcc_parent_map_0, 326 .freq_tbl = ftbl_ne_gcc_qupv3_wrap2_s0_clk_src, 327 .hw_clk_ctrl = true, 328 .clkr.hw.init = &ne_gcc_qupv3_wrap2_s1_clk_src_init, 329 }; 330 331 static const struct freq_tbl ftbl_ne_gcc_qupv3_wrap2_s2_clk_src[] = { 332 F(7372800, P_NE_GCC_GPLL0_OUT_MAIN, 1, 192, 15625), 333 F(14745600, P_NE_GCC_GPLL0_OUT_MAIN, 1, 384, 15625), 334 F(19200000, P_BI_TCXO, 1, 0, 0), 335 F(29491200, P_NE_GCC_GPLL0_OUT_MAIN, 1, 768, 15625), 336 F(32000000, P_NE_GCC_GPLL0_OUT_MAIN, 1, 4, 75), 337 F(48000000, P_NE_GCC_GPLL0_OUT_MAIN, 1, 2, 25), 338 F(51200000, P_NE_GCC_GPLL0_OUT_MAIN, 1, 32, 375), 339 F(64000000, P_NE_GCC_GPLL0_OUT_MAIN, 1, 8, 75), 340 F(66666667, P_NE_GCC_GPLL0_OUT_MAIN, 9, 0, 0), 341 F(75000000, P_NE_GCC_GPLL0_OUT_MAIN, 8, 0, 0), 342 F(80000000, P_NE_GCC_GPLL0_OUT_MAIN, 1, 2, 15), 343 F(96000000, P_NE_GCC_GPLL0_OUT_MAIN, 1, 4, 25), 344 F(100000000, P_NE_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 345 { } 346 }; 347 348 static struct clk_init_data ne_gcc_qupv3_wrap2_s2_clk_src_init = { 349 .name = "ne_gcc_qupv3_wrap2_s2_clk_src", 350 .parent_data = ne_gcc_parent_data_0, 351 .num_parents = ARRAY_SIZE(ne_gcc_parent_data_0), 352 .flags = CLK_SET_RATE_PARENT, 353 .ops = &clk_rcg2_shared_no_init_park_ops, 354 }; 355 356 static struct clk_rcg2 ne_gcc_qupv3_wrap2_s2_clk_src = { 357 .cmd_rcgr = 0x383e4, 358 .mnd_width = 16, 359 .hid_width = 5, 360 .parent_map = ne_gcc_parent_map_0, 361 .freq_tbl = ftbl_ne_gcc_qupv3_wrap2_s2_clk_src, 362 .hw_clk_ctrl = true, 363 .clkr.hw.init = &ne_gcc_qupv3_wrap2_s2_clk_src_init, 364 }; 365 366 static struct clk_init_data ne_gcc_qupv3_wrap2_s3_clk_src_init = { 367 .name = "ne_gcc_qupv3_wrap2_s3_clk_src", 368 .parent_data = ne_gcc_parent_data_0, 369 .num_parents = ARRAY_SIZE(ne_gcc_parent_data_0), 370 .flags = CLK_SET_RATE_PARENT, 371 .ops = &clk_rcg2_shared_no_init_park_ops, 372 }; 373 374 static struct clk_rcg2 ne_gcc_qupv3_wrap2_s3_clk_src = { 375 .cmd_rcgr = 0x38520, 376 .mnd_width = 16, 377 .hid_width = 5, 378 .parent_map = ne_gcc_parent_map_0, 379 .freq_tbl = ftbl_ne_gcc_qupv3_wrap2_s2_clk_src, 380 .hw_clk_ctrl = true, 381 .clkr.hw.init = &ne_gcc_qupv3_wrap2_s3_clk_src_init, 382 }; 383 384 static struct clk_init_data ne_gcc_qupv3_wrap2_s4_clk_src_init = { 385 .name = "ne_gcc_qupv3_wrap2_s4_clk_src", 386 .parent_data = ne_gcc_parent_data_0, 387 .num_parents = ARRAY_SIZE(ne_gcc_parent_data_0), 388 .flags = CLK_SET_RATE_PARENT, 389 .ops = &clk_rcg2_shared_no_init_park_ops, 390 }; 391 392 static struct clk_rcg2 ne_gcc_qupv3_wrap2_s4_clk_src = { 393 .cmd_rcgr = 0x3865c, 394 .mnd_width = 16, 395 .hid_width = 5, 396 .parent_map = ne_gcc_parent_map_0, 397 .freq_tbl = ftbl_ne_gcc_qupv3_wrap2_s2_clk_src, 398 .hw_clk_ctrl = true, 399 .clkr.hw.init = &ne_gcc_qupv3_wrap2_s4_clk_src_init, 400 }; 401 402 static struct clk_init_data ne_gcc_qupv3_wrap2_s5_clk_src_init = { 403 .name = "ne_gcc_qupv3_wrap2_s5_clk_src", 404 .parent_data = ne_gcc_parent_data_0, 405 .num_parents = ARRAY_SIZE(ne_gcc_parent_data_0), 406 .flags = CLK_SET_RATE_PARENT, 407 .ops = &clk_rcg2_shared_no_init_park_ops, 408 }; 409 410 static struct clk_rcg2 ne_gcc_qupv3_wrap2_s5_clk_src = { 411 .cmd_rcgr = 0x38798, 412 .mnd_width = 16, 413 .hid_width = 5, 414 .parent_map = ne_gcc_parent_map_0, 415 .freq_tbl = ftbl_ne_gcc_qupv3_wrap2_s2_clk_src, 416 .hw_clk_ctrl = true, 417 .clkr.hw.init = &ne_gcc_qupv3_wrap2_s5_clk_src_init, 418 }; 419 420 static struct clk_init_data ne_gcc_qupv3_wrap2_s6_clk_src_init = { 421 .name = "ne_gcc_qupv3_wrap2_s6_clk_src", 422 .parent_data = ne_gcc_parent_data_0, 423 .num_parents = ARRAY_SIZE(ne_gcc_parent_data_0), 424 .flags = CLK_SET_RATE_PARENT, 425 .ops = &clk_rcg2_shared_no_init_park_ops, 426 }; 427 428 static struct clk_rcg2 ne_gcc_qupv3_wrap2_s6_clk_src = { 429 .cmd_rcgr = 0x388d4, 430 .mnd_width = 16, 431 .hid_width = 5, 432 .parent_map = ne_gcc_parent_map_0, 433 .freq_tbl = ftbl_ne_gcc_qupv3_wrap2_s2_clk_src, 434 .hw_clk_ctrl = true, 435 .clkr.hw.init = &ne_gcc_qupv3_wrap2_s6_clk_src_init, 436 }; 437 438 static const struct freq_tbl ftbl_ne_gcc_sdcc4_apps_clk_src[] = { 439 F(37500000, P_NE_GCC_GPLL0_OUT_MAIN, 16, 0, 0), 440 F(50000000, P_NE_GCC_GPLL0_OUT_MAIN, 12, 0, 0), 441 F(100000000, P_NE_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 442 { } 443 }; 444 445 static struct clk_rcg2 ne_gcc_sdcc4_apps_clk_src = { 446 .cmd_rcgr = 0x1801c, 447 .mnd_width = 8, 448 .hid_width = 5, 449 .parent_map = ne_gcc_parent_map_0, 450 .freq_tbl = ftbl_ne_gcc_sdcc4_apps_clk_src, 451 .hw_clk_ctrl = true, 452 .clkr.hw.init = &(const struct clk_init_data) { 453 .name = "ne_gcc_sdcc4_apps_clk_src", 454 .parent_data = ne_gcc_parent_data_0, 455 .num_parents = ARRAY_SIZE(ne_gcc_parent_data_0), 456 .flags = CLK_SET_RATE_PARENT, 457 .ops = &clk_rcg2_shared_floor_ops, 458 }, 459 }; 460 461 static const struct freq_tbl ftbl_ne_gcc_ufs_phy_axi_clk_src[] = { 462 F(120000000, P_NE_GCC_GPLL0_OUT_MAIN, 5, 0, 0), 463 F(201500000, P_NE_GCC_GPLL2_OUT_MAIN, 4, 0, 0), 464 F(300000000, P_NE_GCC_GPLL0_OUT_MAIN, 2, 0, 0), 465 F(403000000, P_NE_GCC_GPLL2_OUT_MAIN, 2, 0, 0), 466 { } 467 }; 468 469 static struct clk_rcg2 ne_gcc_ufs_phy_axi_clk_src = { 470 .cmd_rcgr = 0x33034, 471 .mnd_width = 8, 472 .hid_width = 5, 473 .parent_map = ne_gcc_parent_map_2, 474 .freq_tbl = ftbl_ne_gcc_ufs_phy_axi_clk_src, 475 .hw_clk_ctrl = true, 476 .clkr.hw.init = &(const struct clk_init_data) { 477 .name = "ne_gcc_ufs_phy_axi_clk_src", 478 .parent_data = ne_gcc_parent_data_2, 479 .num_parents = ARRAY_SIZE(ne_gcc_parent_data_2), 480 .flags = CLK_SET_RATE_PARENT, 481 .ops = &clk_rcg2_shared_ops, 482 }, 483 }; 484 485 static struct clk_rcg2 ne_gcc_ufs_phy_ice_core_clk_src = { 486 .cmd_rcgr = 0x3308c, 487 .mnd_width = 0, 488 .hid_width = 5, 489 .parent_map = ne_gcc_parent_map_2, 490 .freq_tbl = ftbl_ne_gcc_ufs_phy_axi_clk_src, 491 .hw_clk_ctrl = true, 492 .clkr.hw.init = &(const struct clk_init_data) { 493 .name = "ne_gcc_ufs_phy_ice_core_clk_src", 494 .parent_data = ne_gcc_parent_data_2, 495 .num_parents = ARRAY_SIZE(ne_gcc_parent_data_2), 496 .flags = CLK_SET_RATE_PARENT, 497 .ops = &clk_rcg2_shared_ops, 498 }, 499 }; 500 501 static const struct freq_tbl ftbl_ne_gcc_ufs_phy_phy_aux_clk_src[] = { 502 F(19200000, P_BI_TCXO, 1, 0, 0), 503 { } 504 }; 505 506 static struct clk_rcg2 ne_gcc_ufs_phy_phy_aux_clk_src = { 507 .cmd_rcgr = 0x330c0, 508 .mnd_width = 0, 509 .hid_width = 5, 510 .parent_map = ne_gcc_parent_map_5, 511 .freq_tbl = ftbl_ne_gcc_ufs_phy_phy_aux_clk_src, 512 .hw_clk_ctrl = true, 513 .clkr.hw.init = &(const struct clk_init_data) { 514 .name = "ne_gcc_ufs_phy_phy_aux_clk_src", 515 .parent_data = ne_gcc_parent_data_5, 516 .num_parents = ARRAY_SIZE(ne_gcc_parent_data_5), 517 .flags = CLK_SET_RATE_PARENT, 518 .ops = &clk_rcg2_shared_ops, 519 }, 520 }; 521 522 static struct clk_rcg2 ne_gcc_ufs_phy_unipro_core_clk_src = { 523 .cmd_rcgr = 0x330a4, 524 .mnd_width = 0, 525 .hid_width = 5, 526 .parent_map = ne_gcc_parent_map_2, 527 .freq_tbl = ftbl_ne_gcc_ufs_phy_axi_clk_src, 528 .hw_clk_ctrl = true, 529 .clkr.hw.init = &(const struct clk_init_data) { 530 .name = "ne_gcc_ufs_phy_unipro_core_clk_src", 531 .parent_data = ne_gcc_parent_data_2, 532 .num_parents = ARRAY_SIZE(ne_gcc_parent_data_2), 533 .flags = CLK_SET_RATE_PARENT, 534 .ops = &clk_rcg2_shared_ops, 535 }, 536 }; 537 538 static const struct freq_tbl ftbl_ne_gcc_usb20_master_clk_src[] = { 539 F(75000000, P_NE_GCC_GPLL0_OUT_MAIN, 8, 0, 0), 540 F(120000000, P_NE_GCC_GPLL0_OUT_MAIN, 5, 0, 0), 541 { } 542 }; 543 544 static struct clk_rcg2 ne_gcc_usb20_master_clk_src = { 545 .cmd_rcgr = 0x31030, 546 .mnd_width = 8, 547 .hid_width = 5, 548 .parent_map = ne_gcc_parent_map_0, 549 .freq_tbl = ftbl_ne_gcc_usb20_master_clk_src, 550 .hw_clk_ctrl = true, 551 .clkr.hw.init = &(const struct clk_init_data) { 552 .name = "ne_gcc_usb20_master_clk_src", 553 .parent_data = ne_gcc_parent_data_0, 554 .num_parents = ARRAY_SIZE(ne_gcc_parent_data_0), 555 .flags = CLK_SET_RATE_PARENT, 556 .ops = &clk_rcg2_shared_ops, 557 }, 558 }; 559 560 static struct clk_rcg2 ne_gcc_usb20_mock_utmi_clk_src = { 561 .cmd_rcgr = 0x31048, 562 .mnd_width = 0, 563 .hid_width = 5, 564 .parent_map = ne_gcc_parent_map_0, 565 .freq_tbl = ftbl_ne_gcc_ufs_phy_phy_aux_clk_src, 566 .hw_clk_ctrl = true, 567 .clkr.hw.init = &(const struct clk_init_data) { 568 .name = "ne_gcc_usb20_mock_utmi_clk_src", 569 .parent_data = ne_gcc_parent_data_0, 570 .num_parents = ARRAY_SIZE(ne_gcc_parent_data_0), 571 .flags = CLK_SET_RATE_PARENT, 572 .ops = &clk_rcg2_shared_ops, 573 }, 574 }; 575 576 static const struct freq_tbl ftbl_ne_gcc_usb31_prim_master_clk_src[] = { 577 F(85714286, P_NE_GCC_GPLL0_OUT_MAIN, 7, 0, 0), 578 F(133333333, P_NE_GCC_GPLL0_OUT_MAIN, 4.5, 0, 0), 579 F(200000000, P_NE_GCC_GPLL0_OUT_MAIN, 3, 0, 0), 580 F(240000000, P_NE_GCC_GPLL0_OUT_MAIN, 2.5, 0, 0), 581 { } 582 }; 583 584 static struct clk_rcg2 ne_gcc_usb31_prim_master_clk_src = { 585 .cmd_rcgr = 0x2a038, 586 .mnd_width = 8, 587 .hid_width = 5, 588 .parent_map = ne_gcc_parent_map_1, 589 .freq_tbl = ftbl_ne_gcc_usb31_prim_master_clk_src, 590 .hw_clk_ctrl = true, 591 .clkr.hw.init = &(const struct clk_init_data) { 592 .name = "ne_gcc_usb31_prim_master_clk_src", 593 .parent_data = ne_gcc_parent_data_1, 594 .num_parents = ARRAY_SIZE(ne_gcc_parent_data_1), 595 .flags = CLK_SET_RATE_PARENT, 596 .ops = &clk_rcg2_shared_ops, 597 }, 598 }; 599 600 static struct clk_rcg2 ne_gcc_usb31_prim_mock_utmi_clk_src = { 601 .cmd_rcgr = 0x2a050, 602 .mnd_width = 0, 603 .hid_width = 5, 604 .parent_map = ne_gcc_parent_map_0, 605 .freq_tbl = ftbl_ne_gcc_ufs_phy_phy_aux_clk_src, 606 .hw_clk_ctrl = true, 607 .clkr.hw.init = &(const struct clk_init_data) { 608 .name = "ne_gcc_usb31_prim_mock_utmi_clk_src", 609 .parent_data = ne_gcc_parent_data_0, 610 .num_parents = ARRAY_SIZE(ne_gcc_parent_data_0), 611 .flags = CLK_SET_RATE_PARENT, 612 .ops = &clk_rcg2_shared_ops, 613 }, 614 }; 615 616 static struct clk_rcg2 ne_gcc_usb31_sec_master_clk_src = { 617 .cmd_rcgr = 0x2c038, 618 .mnd_width = 8, 619 .hid_width = 5, 620 .parent_map = ne_gcc_parent_map_0, 621 .freq_tbl = ftbl_ne_gcc_usb31_prim_master_clk_src, 622 .hw_clk_ctrl = true, 623 .clkr.hw.init = &(const struct clk_init_data) { 624 .name = "ne_gcc_usb31_sec_master_clk_src", 625 .parent_data = ne_gcc_parent_data_0, 626 .num_parents = ARRAY_SIZE(ne_gcc_parent_data_0), 627 .flags = CLK_SET_RATE_PARENT, 628 .ops = &clk_rcg2_shared_ops, 629 }, 630 }; 631 632 static struct clk_rcg2 ne_gcc_usb31_sec_mock_utmi_clk_src = { 633 .cmd_rcgr = 0x2c050, 634 .mnd_width = 0, 635 .hid_width = 5, 636 .parent_map = ne_gcc_parent_map_0, 637 .freq_tbl = ftbl_ne_gcc_ufs_phy_phy_aux_clk_src, 638 .hw_clk_ctrl = true, 639 .clkr.hw.init = &(const struct clk_init_data) { 640 .name = "ne_gcc_usb31_sec_mock_utmi_clk_src", 641 .parent_data = ne_gcc_parent_data_0, 642 .num_parents = ARRAY_SIZE(ne_gcc_parent_data_0), 643 .flags = CLK_SET_RATE_PARENT, 644 .ops = &clk_rcg2_shared_ops, 645 }, 646 }; 647 648 static struct clk_rcg2 ne_gcc_usb3_prim_phy_aux_clk_src = { 649 .cmd_rcgr = 0x2a07c, 650 .mnd_width = 0, 651 .hid_width = 5, 652 .parent_map = ne_gcc_parent_map_3, 653 .freq_tbl = ftbl_ne_gcc_ufs_phy_phy_aux_clk_src, 654 .hw_clk_ctrl = true, 655 .clkr.hw.init = &(const struct clk_init_data) { 656 .name = "ne_gcc_usb3_prim_phy_aux_clk_src", 657 .parent_data = ne_gcc_parent_data_3, 658 .num_parents = ARRAY_SIZE(ne_gcc_parent_data_3), 659 .flags = CLK_SET_RATE_PARENT, 660 .ops = &clk_rcg2_shared_ops, 661 }, 662 }; 663 664 static struct clk_rcg2 ne_gcc_usb3_sec_phy_aux_clk_src = { 665 .cmd_rcgr = 0x2c07c, 666 .mnd_width = 0, 667 .hid_width = 5, 668 .parent_map = ne_gcc_parent_map_3, 669 .freq_tbl = ftbl_ne_gcc_ufs_phy_phy_aux_clk_src, 670 .hw_clk_ctrl = true, 671 .clkr.hw.init = &(const struct clk_init_data) { 672 .name = "ne_gcc_usb3_sec_phy_aux_clk_src", 673 .parent_data = ne_gcc_parent_data_3, 674 .num_parents = ARRAY_SIZE(ne_gcc_parent_data_3), 675 .flags = CLK_SET_RATE_PARENT, 676 .ops = &clk_rcg2_shared_ops, 677 }, 678 }; 679 680 static struct clk_regmap_div ne_gcc_usb20_mock_utmi_postdiv_clk_src = { 681 .reg = 0x31060, 682 .shift = 0, 683 .width = 4, 684 .clkr.hw.init = &(const struct clk_init_data) { 685 .name = "ne_gcc_usb20_mock_utmi_postdiv_clk_src", 686 .parent_hws = (const struct clk_hw*[]) { 687 &ne_gcc_usb20_mock_utmi_clk_src.clkr.hw, 688 }, 689 .num_parents = 1, 690 .flags = CLK_SET_RATE_PARENT, 691 .ops = &clk_regmap_div_ro_ops, 692 }, 693 }; 694 695 static struct clk_regmap_div ne_gcc_usb31_prim_mock_utmi_postdiv_clk_src = { 696 .reg = 0x2a068, 697 .shift = 0, 698 .width = 4, 699 .clkr.hw.init = &(const struct clk_init_data) { 700 .name = "ne_gcc_usb31_prim_mock_utmi_postdiv_clk_src", 701 .parent_hws = (const struct clk_hw*[]) { 702 &ne_gcc_usb31_prim_mock_utmi_clk_src.clkr.hw, 703 }, 704 .num_parents = 1, 705 .flags = CLK_SET_RATE_PARENT, 706 .ops = &clk_regmap_div_ro_ops, 707 }, 708 }; 709 710 static struct clk_regmap_div ne_gcc_usb31_sec_mock_utmi_postdiv_clk_src = { 711 .reg = 0x2c068, 712 .shift = 0, 713 .width = 4, 714 .clkr.hw.init = &(const struct clk_init_data) { 715 .name = "ne_gcc_usb31_sec_mock_utmi_postdiv_clk_src", 716 .parent_hws = (const struct clk_hw*[]) { 717 &ne_gcc_usb31_sec_mock_utmi_clk_src.clkr.hw, 718 }, 719 .num_parents = 1, 720 .flags = CLK_SET_RATE_PARENT, 721 .ops = &clk_regmap_div_ro_ops, 722 }, 723 }; 724 725 static struct clk_branch ne_gcc_aggre_noc_ufs_phy_axi_clk = { 726 .halt_reg = 0x330f4, 727 .halt_check = BRANCH_HALT_VOTED, 728 .hwcg_reg = 0x330f4, 729 .hwcg_bit = 1, 730 .clkr = { 731 .enable_reg = 0x330f4, 732 .enable_mask = BIT(0), 733 .hw.init = &(const struct clk_init_data) { 734 .name = "ne_gcc_aggre_noc_ufs_phy_axi_clk", 735 .parent_hws = (const struct clk_hw*[]) { 736 &ne_gcc_ufs_phy_axi_clk_src.clkr.hw, 737 }, 738 .num_parents = 1, 739 .flags = CLK_SET_RATE_PARENT, 740 .ops = &clk_branch2_ops, 741 }, 742 }, 743 }; 744 745 static struct clk_branch ne_gcc_aggre_noc_usb2_axi_clk = { 746 .halt_reg = 0x31068, 747 .halt_check = BRANCH_HALT_VOTED, 748 .hwcg_reg = 0x31068, 749 .hwcg_bit = 1, 750 .clkr = { 751 .enable_reg = 0x31068, 752 .enable_mask = BIT(0), 753 .hw.init = &(const struct clk_init_data) { 754 .name = "ne_gcc_aggre_noc_usb2_axi_clk", 755 .parent_hws = (const struct clk_hw*[]) { 756 &ne_gcc_usb20_master_clk_src.clkr.hw, 757 }, 758 .num_parents = 1, 759 .flags = CLK_SET_RATE_PARENT, 760 .ops = &clk_branch2_ops, 761 }, 762 }, 763 }; 764 765 static struct clk_branch ne_gcc_aggre_noc_usb3_prim_axi_clk = { 766 .halt_reg = 0x2a098, 767 .halt_check = BRANCH_HALT_VOTED, 768 .hwcg_reg = 0x2a098, 769 .hwcg_bit = 1, 770 .clkr = { 771 .enable_reg = 0x2a098, 772 .enable_mask = BIT(0), 773 .hw.init = &(const struct clk_init_data) { 774 .name = "ne_gcc_aggre_noc_usb3_prim_axi_clk", 775 .parent_hws = (const struct clk_hw*[]) { 776 &ne_gcc_usb31_prim_master_clk_src.clkr.hw, 777 }, 778 .num_parents = 1, 779 .flags = CLK_SET_RATE_PARENT, 780 .ops = &clk_branch2_ops, 781 }, 782 }, 783 }; 784 785 static struct clk_branch ne_gcc_aggre_noc_usb3_sec_axi_clk = { 786 .halt_reg = 0x2c098, 787 .halt_check = BRANCH_HALT_VOTED, 788 .hwcg_reg = 0x2c098, 789 .hwcg_bit = 1, 790 .clkr = { 791 .enable_reg = 0x2c098, 792 .enable_mask = BIT(0), 793 .hw.init = &(const struct clk_init_data) { 794 .name = "ne_gcc_aggre_noc_usb3_sec_axi_clk", 795 .parent_hws = (const struct clk_hw*[]) { 796 &ne_gcc_usb31_sec_master_clk_src.clkr.hw, 797 }, 798 .num_parents = 1, 799 .flags = CLK_SET_RATE_PARENT, 800 .ops = &clk_branch2_ops, 801 }, 802 }, 803 }; 804 805 static struct clk_branch ne_gcc_ahb2phy_clk = { 806 .halt_reg = 0x30004, 807 .halt_check = BRANCH_HALT_VOTED, 808 .hwcg_reg = 0x30004, 809 .hwcg_bit = 1, 810 .clkr = { 811 .enable_reg = 0x30004, 812 .enable_mask = BIT(0), 813 .hw.init = &(const struct clk_init_data) { 814 .name = "ne_gcc_ahb2phy_clk", 815 .ops = &clk_branch2_ops, 816 }, 817 }, 818 }; 819 820 static struct clk_branch ne_gcc_cnoc_usb2_axi_clk = { 821 .halt_reg = 0x31064, 822 .halt_check = BRANCH_HALT_VOTED, 823 .hwcg_reg = 0x31064, 824 .hwcg_bit = 1, 825 .clkr = { 826 .enable_reg = 0x31064, 827 .enable_mask = BIT(0), 828 .hw.init = &(const struct clk_init_data) { 829 .name = "ne_gcc_cnoc_usb2_axi_clk", 830 .parent_hws = (const struct clk_hw*[]) { 831 &ne_gcc_usb20_master_clk_src.clkr.hw, 832 }, 833 .num_parents = 1, 834 .flags = CLK_SET_RATE_PARENT, 835 .ops = &clk_branch2_ops, 836 }, 837 }, 838 }; 839 840 static struct clk_branch ne_gcc_cnoc_usb3_prim_axi_clk = { 841 .halt_reg = 0x2a094, 842 .halt_check = BRANCH_HALT_VOTED, 843 .hwcg_reg = 0x2a094, 844 .hwcg_bit = 1, 845 .clkr = { 846 .enable_reg = 0x2a094, 847 .enable_mask = BIT(0), 848 .hw.init = &(const struct clk_init_data) { 849 .name = "ne_gcc_cnoc_usb3_prim_axi_clk", 850 .parent_hws = (const struct clk_hw*[]) { 851 &ne_gcc_usb31_prim_master_clk_src.clkr.hw, 852 }, 853 .num_parents = 1, 854 .flags = CLK_SET_RATE_PARENT, 855 .ops = &clk_branch2_ops, 856 }, 857 }, 858 }; 859 860 static struct clk_branch ne_gcc_cnoc_usb3_sec_axi_clk = { 861 .halt_reg = 0x2c094, 862 .halt_check = BRANCH_HALT_VOTED, 863 .hwcg_reg = 0x2c094, 864 .hwcg_bit = 1, 865 .clkr = { 866 .enable_reg = 0x2c094, 867 .enable_mask = BIT(0), 868 .hw.init = &(const struct clk_init_data) { 869 .name = "ne_gcc_cnoc_usb3_sec_axi_clk", 870 .parent_hws = (const struct clk_hw*[]) { 871 &ne_gcc_usb31_sec_master_clk_src.clkr.hw, 872 }, 873 .num_parents = 1, 874 .flags = CLK_SET_RATE_PARENT, 875 .ops = &clk_branch2_ops, 876 }, 877 }, 878 }; 879 880 static struct clk_branch ne_gcc_frq_measure_ref_clk = { 881 .halt_reg = 0x20008, 882 .halt_check = BRANCH_HALT, 883 .clkr = { 884 .enable_reg = 0x20008, 885 .enable_mask = BIT(0), 886 .hw.init = &(const struct clk_init_data) { 887 .name = "ne_gcc_frq_measure_ref_clk", 888 .ops = &clk_branch2_ops, 889 }, 890 }, 891 }; 892 893 static struct clk_branch ne_gcc_gp1_clk = { 894 .halt_reg = 0x21000, 895 .halt_check = BRANCH_HALT, 896 .clkr = { 897 .enable_reg = 0x21000, 898 .enable_mask = BIT(0), 899 .hw.init = &(const struct clk_init_data) { 900 .name = "ne_gcc_gp1_clk", 901 .parent_hws = (const struct clk_hw*[]) { 902 &ne_gcc_gp1_clk_src.clkr.hw, 903 }, 904 .num_parents = 1, 905 .flags = CLK_SET_RATE_PARENT, 906 .ops = &clk_branch2_ops, 907 }, 908 }, 909 }; 910 911 static struct clk_branch ne_gcc_gp2_clk = { 912 .halt_reg = 0x22000, 913 .halt_check = BRANCH_HALT, 914 .clkr = { 915 .enable_reg = 0x22000, 916 .enable_mask = BIT(0), 917 .hw.init = &(const struct clk_init_data) { 918 .name = "ne_gcc_gp2_clk", 919 .parent_hws = (const struct clk_hw*[]) { 920 &ne_gcc_gp2_clk_src.clkr.hw, 921 }, 922 .num_parents = 1, 923 .flags = CLK_SET_RATE_PARENT, 924 .ops = &clk_branch2_ops, 925 }, 926 }, 927 }; 928 929 static struct clk_branch ne_gcc_gpu_2_gpll0_clk_src = { 930 .halt_check = BRANCH_HALT_DELAY, 931 .clkr = { 932 .enable_reg = 0x57000, 933 .enable_mask = BIT(19), 934 .hw.init = &(const struct clk_init_data) { 935 .name = "ne_gcc_gpu_2_gpll0_clk_src", 936 .parent_hws = (const struct clk_hw*[]) { 937 &ne_gcc_gpll0.clkr.hw, 938 }, 939 .num_parents = 1, 940 .flags = CLK_SET_RATE_PARENT, 941 .ops = &clk_branch2_ops, 942 }, 943 }, 944 }; 945 946 static struct clk_branch ne_gcc_gpu_2_gpll0_div_clk_src = { 947 .halt_check = BRANCH_HALT_DELAY, 948 .clkr = { 949 .enable_reg = 0x57000, 950 .enable_mask = BIT(20), 951 .hw.init = &(const struct clk_init_data) { 952 .name = "ne_gcc_gpu_2_gpll0_div_clk_src", 953 .parent_hws = (const struct clk_hw*[]) { 954 &ne_gcc_gpll0_out_even.clkr.hw, 955 }, 956 .num_parents = 1, 957 .flags = CLK_SET_RATE_PARENT, 958 .ops = &clk_branch2_ops, 959 }, 960 }, 961 }; 962 963 static struct clk_branch ne_gcc_gpu_2_hscnoc_gfx_clk = { 964 .halt_reg = 0x34014, 965 .halt_check = BRANCH_HALT_VOTED, 966 .hwcg_reg = 0x34014, 967 .hwcg_bit = 1, 968 .clkr = { 969 .enable_reg = 0x34014, 970 .enable_mask = BIT(0), 971 .hw.init = &(const struct clk_init_data) { 972 .name = "ne_gcc_gpu_2_hscnoc_gfx_clk", 973 .ops = &clk_branch2_ops, 974 }, 975 }, 976 }; 977 978 static struct clk_branch ne_gcc_gpu_2_smmu_vote_clk = { 979 .halt_reg = 0x57028, 980 .halt_check = BRANCH_HALT_VOTED, 981 .clkr = { 982 .enable_reg = 0x57028, 983 .enable_mask = BIT(0), 984 .hw.init = &(const struct clk_init_data) { 985 .name = "ne_gcc_gpu_2_smmu_vote_clk", 986 .ops = &clk_branch2_ops, 987 }, 988 }, 989 }; 990 991 static struct clk_branch ne_gcc_qupv3_wrap2_core_2x_clk = { 992 .halt_reg = 0x38020, 993 .halt_check = BRANCH_HALT_VOTED, 994 .clkr = { 995 .enable_reg = 0x57008, 996 .enable_mask = BIT(1), 997 .hw.init = &(const struct clk_init_data) { 998 .name = "ne_gcc_qupv3_wrap2_core_2x_clk", 999 .ops = &clk_branch2_ops, 1000 }, 1001 }, 1002 }; 1003 1004 static struct clk_branch ne_gcc_qupv3_wrap2_core_clk = { 1005 .halt_reg = 0x3800c, 1006 .halt_check = BRANCH_HALT_VOTED, 1007 .clkr = { 1008 .enable_reg = 0x57008, 1009 .enable_mask = BIT(0), 1010 .hw.init = &(const struct clk_init_data) { 1011 .name = "ne_gcc_qupv3_wrap2_core_clk", 1012 .ops = &clk_branch2_ops, 1013 }, 1014 }, 1015 }; 1016 1017 static struct clk_branch ne_gcc_qupv3_wrap2_m_ahb_clk = { 1018 .halt_reg = 0x38004, 1019 .halt_check = BRANCH_HALT_VOTED, 1020 .hwcg_reg = 0x38004, 1021 .hwcg_bit = 1, 1022 .clkr = { 1023 .enable_reg = 0x57000, 1024 .enable_mask = BIT(30), 1025 .hw.init = &(const struct clk_init_data) { 1026 .name = "ne_gcc_qupv3_wrap2_m_ahb_clk", 1027 .ops = &clk_branch2_ops, 1028 }, 1029 }, 1030 }; 1031 1032 static struct clk_branch ne_gcc_qupv3_wrap2_s0_clk = { 1033 .halt_reg = 0x3815c, 1034 .halt_check = BRANCH_HALT_VOTED, 1035 .clkr = { 1036 .enable_reg = 0x57008, 1037 .enable_mask = BIT(2), 1038 .hw.init = &(const struct clk_init_data) { 1039 .name = "ne_gcc_qupv3_wrap2_s0_clk", 1040 .parent_hws = (const struct clk_hw*[]) { 1041 &ne_gcc_qupv3_wrap2_s0_clk_src.clkr.hw, 1042 }, 1043 .num_parents = 1, 1044 .flags = CLK_SET_RATE_PARENT, 1045 .ops = &clk_branch2_ops, 1046 }, 1047 }, 1048 }; 1049 1050 static struct clk_branch ne_gcc_qupv3_wrap2_s1_clk = { 1051 .halt_reg = 0x38298, 1052 .halt_check = BRANCH_HALT_VOTED, 1053 .clkr = { 1054 .enable_reg = 0x57008, 1055 .enable_mask = BIT(3), 1056 .hw.init = &(const struct clk_init_data) { 1057 .name = "ne_gcc_qupv3_wrap2_s1_clk", 1058 .parent_hws = (const struct clk_hw*[]) { 1059 &ne_gcc_qupv3_wrap2_s1_clk_src.clkr.hw, 1060 }, 1061 .num_parents = 1, 1062 .flags = CLK_SET_RATE_PARENT, 1063 .ops = &clk_branch2_ops, 1064 }, 1065 }, 1066 }; 1067 1068 static struct clk_branch ne_gcc_qupv3_wrap2_s2_clk = { 1069 .halt_reg = 0x383d4, 1070 .halt_check = BRANCH_HALT_VOTED, 1071 .clkr = { 1072 .enable_reg = 0x57008, 1073 .enable_mask = BIT(4), 1074 .hw.init = &(const struct clk_init_data) { 1075 .name = "ne_gcc_qupv3_wrap2_s2_clk", 1076 .parent_hws = (const struct clk_hw*[]) { 1077 &ne_gcc_qupv3_wrap2_s2_clk_src.clkr.hw, 1078 }, 1079 .num_parents = 1, 1080 .flags = CLK_SET_RATE_PARENT, 1081 .ops = &clk_branch2_ops, 1082 }, 1083 }, 1084 }; 1085 1086 static struct clk_branch ne_gcc_qupv3_wrap2_s3_clk = { 1087 .halt_reg = 0x38510, 1088 .halt_check = BRANCH_HALT_VOTED, 1089 .clkr = { 1090 .enable_reg = 0x57008, 1091 .enable_mask = BIT(5), 1092 .hw.init = &(const struct clk_init_data) { 1093 .name = "ne_gcc_qupv3_wrap2_s3_clk", 1094 .parent_hws = (const struct clk_hw*[]) { 1095 &ne_gcc_qupv3_wrap2_s3_clk_src.clkr.hw, 1096 }, 1097 .num_parents = 1, 1098 .flags = CLK_SET_RATE_PARENT, 1099 .ops = &clk_branch2_ops, 1100 }, 1101 }, 1102 }; 1103 1104 static struct clk_branch ne_gcc_qupv3_wrap2_s4_clk = { 1105 .halt_reg = 0x3864c, 1106 .halt_check = BRANCH_HALT_VOTED, 1107 .clkr = { 1108 .enable_reg = 0x57008, 1109 .enable_mask = BIT(6), 1110 .hw.init = &(const struct clk_init_data) { 1111 .name = "ne_gcc_qupv3_wrap2_s4_clk", 1112 .parent_hws = (const struct clk_hw*[]) { 1113 &ne_gcc_qupv3_wrap2_s4_clk_src.clkr.hw, 1114 }, 1115 .num_parents = 1, 1116 .flags = CLK_SET_RATE_PARENT, 1117 .ops = &clk_branch2_ops, 1118 }, 1119 }, 1120 }; 1121 1122 static struct clk_branch ne_gcc_qupv3_wrap2_s5_clk = { 1123 .halt_reg = 0x38788, 1124 .halt_check = BRANCH_HALT_VOTED, 1125 .clkr = { 1126 .enable_reg = 0x57008, 1127 .enable_mask = BIT(7), 1128 .hw.init = &(const struct clk_init_data) { 1129 .name = "ne_gcc_qupv3_wrap2_s5_clk", 1130 .parent_hws = (const struct clk_hw*[]) { 1131 &ne_gcc_qupv3_wrap2_s5_clk_src.clkr.hw, 1132 }, 1133 .num_parents = 1, 1134 .flags = CLK_SET_RATE_PARENT, 1135 .ops = &clk_branch2_ops, 1136 }, 1137 }, 1138 }; 1139 1140 static struct clk_branch ne_gcc_qupv3_wrap2_s6_clk = { 1141 .halt_reg = 0x388c4, 1142 .halt_check = BRANCH_HALT_VOTED, 1143 .clkr = { 1144 .enable_reg = 0x57008, 1145 .enable_mask = BIT(8), 1146 .hw.init = &(const struct clk_init_data) { 1147 .name = "ne_gcc_qupv3_wrap2_s6_clk", 1148 .parent_hws = (const struct clk_hw*[]) { 1149 &ne_gcc_qupv3_wrap2_s6_clk_src.clkr.hw, 1150 }, 1151 .num_parents = 1, 1152 .flags = CLK_SET_RATE_PARENT, 1153 .ops = &clk_branch2_ops, 1154 }, 1155 }, 1156 }; 1157 1158 static struct clk_branch ne_gcc_qupv3_wrap2_s_ahb_clk = { 1159 .halt_reg = 0x38008, 1160 .halt_check = BRANCH_HALT_VOTED, 1161 .hwcg_reg = 0x38008, 1162 .hwcg_bit = 1, 1163 .clkr = { 1164 .enable_reg = 0x57000, 1165 .enable_mask = BIT(31), 1166 .hw.init = &(const struct clk_init_data) { 1167 .name = "ne_gcc_qupv3_wrap2_s_ahb_clk", 1168 .ops = &clk_branch2_ops, 1169 }, 1170 }, 1171 }; 1172 1173 static struct clk_branch ne_gcc_sdcc4_apps_clk = { 1174 .halt_reg = 0x18004, 1175 .halt_check = BRANCH_HALT, 1176 .clkr = { 1177 .enable_reg = 0x18004, 1178 .enable_mask = BIT(0), 1179 .hw.init = &(const struct clk_init_data) { 1180 .name = "ne_gcc_sdcc4_apps_clk", 1181 .parent_hws = (const struct clk_hw*[]) { 1182 &ne_gcc_sdcc4_apps_clk_src.clkr.hw, 1183 }, 1184 .num_parents = 1, 1185 .flags = CLK_SET_RATE_PARENT, 1186 .ops = &clk_branch2_ops, 1187 }, 1188 }, 1189 }; 1190 1191 static struct clk_branch ne_gcc_sdcc4_axi_clk = { 1192 .halt_reg = 0x18014, 1193 .halt_check = BRANCH_HALT, 1194 .clkr = { 1195 .enable_reg = 0x18014, 1196 .enable_mask = BIT(0), 1197 .hw.init = &(const struct clk_init_data) { 1198 .name = "ne_gcc_sdcc4_axi_clk", 1199 .ops = &clk_branch2_ops, 1200 }, 1201 }, 1202 }; 1203 1204 static struct clk_branch ne_gcc_ufs_phy_ahb_clk = { 1205 .halt_reg = 0x33028, 1206 .halt_check = BRANCH_HALT_VOTED, 1207 .hwcg_reg = 0x33028, 1208 .hwcg_bit = 1, 1209 .clkr = { 1210 .enable_reg = 0x33028, 1211 .enable_mask = BIT(0), 1212 .hw.init = &(const struct clk_init_data) { 1213 .name = "ne_gcc_ufs_phy_ahb_clk", 1214 .ops = &clk_branch2_ops, 1215 }, 1216 }, 1217 }; 1218 1219 static struct clk_branch ne_gcc_ufs_phy_axi_clk = { 1220 .halt_reg = 0x33018, 1221 .halt_check = BRANCH_HALT_VOTED, 1222 .hwcg_reg = 0x33018, 1223 .hwcg_bit = 1, 1224 .clkr = { 1225 .enable_reg = 0x33018, 1226 .enable_mask = BIT(0), 1227 .hw.init = &(const struct clk_init_data) { 1228 .name = "ne_gcc_ufs_phy_axi_clk", 1229 .parent_hws = (const struct clk_hw*[]) { 1230 &ne_gcc_ufs_phy_axi_clk_src.clkr.hw, 1231 }, 1232 .num_parents = 1, 1233 .flags = CLK_SET_RATE_PARENT, 1234 .ops = &clk_branch2_ops, 1235 }, 1236 }, 1237 }; 1238 1239 static struct clk_branch ne_gcc_ufs_phy_ice_core_clk = { 1240 .halt_reg = 0x3307c, 1241 .halt_check = BRANCH_HALT_VOTED, 1242 .hwcg_reg = 0x3307c, 1243 .hwcg_bit = 1, 1244 .clkr = { 1245 .enable_reg = 0x3307c, 1246 .enable_mask = BIT(0), 1247 .hw.init = &(const struct clk_init_data) { 1248 .name = "ne_gcc_ufs_phy_ice_core_clk", 1249 .parent_hws = (const struct clk_hw*[]) { 1250 &ne_gcc_ufs_phy_ice_core_clk_src.clkr.hw, 1251 }, 1252 .num_parents = 1, 1253 .flags = CLK_SET_RATE_PARENT, 1254 .ops = &clk_branch2_ops, 1255 }, 1256 }, 1257 }; 1258 1259 static struct clk_branch ne_gcc_ufs_phy_phy_aux_clk = { 1260 .halt_reg = 0x330bc, 1261 .halt_check = BRANCH_HALT_VOTED, 1262 .hwcg_reg = 0x330bc, 1263 .hwcg_bit = 1, 1264 .clkr = { 1265 .enable_reg = 0x330bc, 1266 .enable_mask = BIT(0), 1267 .hw.init = &(const struct clk_init_data) { 1268 .name = "ne_gcc_ufs_phy_phy_aux_clk", 1269 .parent_hws = (const struct clk_hw*[]) { 1270 &ne_gcc_ufs_phy_phy_aux_clk_src.clkr.hw, 1271 }, 1272 .num_parents = 1, 1273 .flags = CLK_SET_RATE_PARENT, 1274 .ops = &clk_branch2_ops, 1275 }, 1276 }, 1277 }; 1278 1279 static struct clk_branch ne_gcc_ufs_phy_rx_symbol_0_clk = { 1280 .halt_reg = 0x33030, 1281 .halt_check = BRANCH_HALT_DELAY, 1282 .clkr = { 1283 .enable_reg = 0x33030, 1284 .enable_mask = BIT(0), 1285 .hw.init = &(const struct clk_init_data) { 1286 .name = "ne_gcc_ufs_phy_rx_symbol_0_clk", 1287 .parent_hws = (const struct clk_hw*[]) { 1288 &ne_gcc_ufs_phy_rx_symbol_0_clk_src.clkr.hw, 1289 }, 1290 .num_parents = 1, 1291 .flags = CLK_SET_RATE_PARENT, 1292 .ops = &clk_branch2_ops, 1293 }, 1294 }, 1295 }; 1296 1297 static struct clk_branch ne_gcc_ufs_phy_rx_symbol_1_clk = { 1298 .halt_reg = 0x330d8, 1299 .halt_check = BRANCH_HALT_DELAY, 1300 .clkr = { 1301 .enable_reg = 0x330d8, 1302 .enable_mask = BIT(0), 1303 .hw.init = &(const struct clk_init_data) { 1304 .name = "ne_gcc_ufs_phy_rx_symbol_1_clk", 1305 .parent_hws = (const struct clk_hw*[]) { 1306 &ne_gcc_ufs_phy_rx_symbol_1_clk_src.clkr.hw, 1307 }, 1308 .num_parents = 1, 1309 .flags = CLK_SET_RATE_PARENT, 1310 .ops = &clk_branch2_ops, 1311 }, 1312 }, 1313 }; 1314 1315 static struct clk_branch ne_gcc_ufs_phy_tx_symbol_0_clk = { 1316 .halt_reg = 0x3302c, 1317 .halt_check = BRANCH_HALT_DELAY, 1318 .clkr = { 1319 .enable_reg = 0x3302c, 1320 .enable_mask = BIT(0), 1321 .hw.init = &(const struct clk_init_data) { 1322 .name = "ne_gcc_ufs_phy_tx_symbol_0_clk", 1323 .parent_hws = (const struct clk_hw*[]) { 1324 &ne_gcc_ufs_phy_tx_symbol_0_clk_src.clkr.hw, 1325 }, 1326 .num_parents = 1, 1327 .flags = CLK_SET_RATE_PARENT, 1328 .ops = &clk_branch2_ops, 1329 }, 1330 }, 1331 }; 1332 1333 static struct clk_branch ne_gcc_ufs_phy_unipro_core_clk = { 1334 .halt_reg = 0x3306c, 1335 .halt_check = BRANCH_HALT_VOTED, 1336 .hwcg_reg = 0x3306c, 1337 .hwcg_bit = 1, 1338 .clkr = { 1339 .enable_reg = 0x3306c, 1340 .enable_mask = BIT(0), 1341 .hw.init = &(const struct clk_init_data) { 1342 .name = "ne_gcc_ufs_phy_unipro_core_clk", 1343 .parent_hws = (const struct clk_hw*[]) { 1344 &ne_gcc_ufs_phy_unipro_core_clk_src.clkr.hw, 1345 }, 1346 .num_parents = 1, 1347 .flags = CLK_SET_RATE_PARENT, 1348 .ops = &clk_branch2_ops, 1349 }, 1350 }, 1351 }; 1352 1353 static struct clk_branch ne_gcc_usb20_master_clk = { 1354 .halt_reg = 0x31018, 1355 .halt_check = BRANCH_HALT, 1356 .clkr = { 1357 .enable_reg = 0x31018, 1358 .enable_mask = BIT(0), 1359 .hw.init = &(const struct clk_init_data) { 1360 .name = "ne_gcc_usb20_master_clk", 1361 .parent_hws = (const struct clk_hw*[]) { 1362 &ne_gcc_usb20_master_clk_src.clkr.hw, 1363 }, 1364 .num_parents = 1, 1365 .flags = CLK_SET_RATE_PARENT, 1366 .ops = &clk_branch2_ops, 1367 }, 1368 }, 1369 }; 1370 1371 static struct clk_branch ne_gcc_usb20_mock_utmi_clk = { 1372 .halt_reg = 0x3102c, 1373 .halt_check = BRANCH_HALT, 1374 .clkr = { 1375 .enable_reg = 0x3102c, 1376 .enable_mask = BIT(0), 1377 .hw.init = &(const struct clk_init_data) { 1378 .name = "ne_gcc_usb20_mock_utmi_clk", 1379 .parent_hws = (const struct clk_hw*[]) { 1380 &ne_gcc_usb20_mock_utmi_postdiv_clk_src.clkr.hw, 1381 }, 1382 .num_parents = 1, 1383 .flags = CLK_SET_RATE_PARENT, 1384 .ops = &clk_branch2_ops, 1385 }, 1386 }, 1387 }; 1388 1389 static struct clk_branch ne_gcc_usb20_sleep_clk = { 1390 .halt_reg = 0x31028, 1391 .halt_check = BRANCH_HALT, 1392 .clkr = { 1393 .enable_reg = 0x31028, 1394 .enable_mask = BIT(0), 1395 .hw.init = &(const struct clk_init_data) { 1396 .name = "ne_gcc_usb20_sleep_clk", 1397 .ops = &clk_branch2_ops, 1398 }, 1399 }, 1400 }; 1401 1402 static struct clk_branch ne_gcc_usb31_prim_atb_clk = { 1403 .halt_reg = 0x2a018, 1404 .halt_check = BRANCH_HALT_VOTED, 1405 .clkr = { 1406 .enable_reg = 0x2a018, 1407 .enable_mask = BIT(0), 1408 .hw.init = &(const struct clk_init_data) { 1409 .name = "ne_gcc_usb31_prim_atb_clk", 1410 .parent_hws = (const struct clk_hw*[]) { 1411 &ne_gcc_usb31_prim_master_clk_src.clkr.hw, 1412 }, 1413 .num_parents = 1, 1414 .flags = CLK_SET_RATE_PARENT, 1415 .ops = &clk_branch2_ops, 1416 }, 1417 }, 1418 }; 1419 1420 static struct clk_branch ne_gcc_usb31_prim_eud_ahb_clk = { 1421 .halt_reg = 0x2a02c, 1422 .halt_check = BRANCH_HALT_VOTED, 1423 .hwcg_reg = 0x2a02c, 1424 .hwcg_bit = 1, 1425 .clkr = { 1426 .enable_reg = 0x2a02c, 1427 .enable_mask = BIT(0), 1428 .hw.init = &(const struct clk_init_data) { 1429 .name = "ne_gcc_usb31_prim_eud_ahb_clk", 1430 .ops = &clk_branch2_ops, 1431 }, 1432 }, 1433 }; 1434 1435 static struct clk_branch ne_gcc_usb31_prim_master_clk = { 1436 .halt_reg = 0x2a01c, 1437 .halt_check = BRANCH_HALT, 1438 .clkr = { 1439 .enable_reg = 0x2a01c, 1440 .enable_mask = BIT(0), 1441 .hw.init = &(const struct clk_init_data) { 1442 .name = "ne_gcc_usb31_prim_master_clk", 1443 .parent_hws = (const struct clk_hw*[]) { 1444 &ne_gcc_usb31_prim_master_clk_src.clkr.hw, 1445 }, 1446 .num_parents = 1, 1447 .flags = CLK_SET_RATE_PARENT, 1448 .ops = &clk_branch2_ops, 1449 }, 1450 }, 1451 }; 1452 1453 static struct clk_branch ne_gcc_usb31_prim_mock_utmi_clk = { 1454 .halt_reg = 0x2a034, 1455 .halt_check = BRANCH_HALT, 1456 .clkr = { 1457 .enable_reg = 0x2a034, 1458 .enable_mask = BIT(0), 1459 .hw.init = &(const struct clk_init_data) { 1460 .name = "ne_gcc_usb31_prim_mock_utmi_clk", 1461 .parent_hws = (const struct clk_hw*[]) { 1462 &ne_gcc_usb31_prim_mock_utmi_postdiv_clk_src.clkr.hw, 1463 }, 1464 .num_parents = 1, 1465 .flags = CLK_SET_RATE_PARENT, 1466 .ops = &clk_branch2_ops, 1467 }, 1468 }, 1469 }; 1470 1471 static struct clk_branch ne_gcc_usb31_prim_sleep_clk = { 1472 .halt_reg = 0x2a030, 1473 .halt_check = BRANCH_HALT, 1474 .clkr = { 1475 .enable_reg = 0x2a030, 1476 .enable_mask = BIT(0), 1477 .hw.init = &(const struct clk_init_data) { 1478 .name = "ne_gcc_usb31_prim_sleep_clk", 1479 .ops = &clk_branch2_ops, 1480 }, 1481 }, 1482 }; 1483 1484 static struct clk_branch ne_gcc_usb31_sec_atb_clk = { 1485 .halt_reg = 0x2c018, 1486 .halt_check = BRANCH_HALT_VOTED, 1487 .clkr = { 1488 .enable_reg = 0x2c018, 1489 .enable_mask = BIT(0), 1490 .hw.init = &(const struct clk_init_data) { 1491 .name = "ne_gcc_usb31_sec_atb_clk", 1492 .parent_hws = (const struct clk_hw*[]) { 1493 &ne_gcc_usb31_prim_master_clk_src.clkr.hw, 1494 }, 1495 .num_parents = 1, 1496 .flags = CLK_SET_RATE_PARENT, 1497 .ops = &clk_branch2_ops, 1498 }, 1499 }, 1500 }; 1501 1502 static struct clk_branch ne_gcc_usb31_sec_eud_ahb_clk = { 1503 .halt_reg = 0x2c02c, 1504 .halt_check = BRANCH_HALT_VOTED, 1505 .hwcg_reg = 0x2c02c, 1506 .hwcg_bit = 1, 1507 .clkr = { 1508 .enable_reg = 0x2c02c, 1509 .enable_mask = BIT(0), 1510 .hw.init = &(const struct clk_init_data) { 1511 .name = "ne_gcc_usb31_sec_eud_ahb_clk", 1512 .ops = &clk_branch2_ops, 1513 }, 1514 }, 1515 }; 1516 1517 static struct clk_branch ne_gcc_usb31_sec_master_clk = { 1518 .halt_reg = 0x2c01c, 1519 .halt_check = BRANCH_HALT, 1520 .clkr = { 1521 .enable_reg = 0x2c01c, 1522 .enable_mask = BIT(0), 1523 .hw.init = &(const struct clk_init_data) { 1524 .name = "ne_gcc_usb31_sec_master_clk", 1525 .parent_hws = (const struct clk_hw*[]) { 1526 &ne_gcc_usb31_sec_master_clk_src.clkr.hw, 1527 }, 1528 .num_parents = 1, 1529 .flags = CLK_SET_RATE_PARENT, 1530 .ops = &clk_branch2_ops, 1531 }, 1532 }, 1533 }; 1534 1535 static struct clk_branch ne_gcc_usb31_sec_mock_utmi_clk = { 1536 .halt_reg = 0x2c034, 1537 .halt_check = BRANCH_HALT, 1538 .clkr = { 1539 .enable_reg = 0x2c034, 1540 .enable_mask = BIT(0), 1541 .hw.init = &(const struct clk_init_data) { 1542 .name = "ne_gcc_usb31_sec_mock_utmi_clk", 1543 .parent_hws = (const struct clk_hw*[]) { 1544 &ne_gcc_usb31_sec_mock_utmi_postdiv_clk_src.clkr.hw, 1545 }, 1546 .num_parents = 1, 1547 .flags = CLK_SET_RATE_PARENT, 1548 .ops = &clk_branch2_ops, 1549 }, 1550 }, 1551 }; 1552 1553 static struct clk_branch ne_gcc_usb31_sec_sleep_clk = { 1554 .halt_reg = 0x2c030, 1555 .halt_check = BRANCH_HALT, 1556 .clkr = { 1557 .enable_reg = 0x2c030, 1558 .enable_mask = BIT(0), 1559 .hw.init = &(const struct clk_init_data) { 1560 .name = "ne_gcc_usb31_sec_sleep_clk", 1561 .ops = &clk_branch2_ops, 1562 }, 1563 }, 1564 }; 1565 1566 static struct clk_branch ne_gcc_usb3_prim_phy_aux_clk = { 1567 .halt_reg = 0x2a06c, 1568 .halt_check = BRANCH_HALT, 1569 .clkr = { 1570 .enable_reg = 0x2a06c, 1571 .enable_mask = BIT(0), 1572 .hw.init = &(const struct clk_init_data) { 1573 .name = "ne_gcc_usb3_prim_phy_aux_clk", 1574 .parent_hws = (const struct clk_hw*[]) { 1575 &ne_gcc_usb3_prim_phy_aux_clk_src.clkr.hw, 1576 }, 1577 .num_parents = 1, 1578 .flags = CLK_SET_RATE_PARENT, 1579 .ops = &clk_branch2_ops, 1580 }, 1581 }, 1582 }; 1583 1584 static struct clk_branch ne_gcc_usb3_prim_phy_com_aux_clk = { 1585 .halt_reg = 0x2a070, 1586 .halt_check = BRANCH_HALT, 1587 .clkr = { 1588 .enable_reg = 0x2a070, 1589 .enable_mask = BIT(0), 1590 .hw.init = &(const struct clk_init_data) { 1591 .name = "ne_gcc_usb3_prim_phy_com_aux_clk", 1592 .parent_hws = (const struct clk_hw*[]) { 1593 &ne_gcc_usb3_prim_phy_aux_clk_src.clkr.hw, 1594 }, 1595 .num_parents = 1, 1596 .flags = CLK_SET_RATE_PARENT, 1597 .ops = &clk_branch2_ops, 1598 }, 1599 }, 1600 }; 1601 1602 static struct clk_branch ne_gcc_usb3_prim_phy_pipe_clk = { 1603 .halt_reg = 0x2a074, 1604 .halt_check = BRANCH_HALT_SKIP, 1605 .hwcg_reg = 0x2a074, 1606 .hwcg_bit = 1, 1607 .clkr = { 1608 .enable_reg = 0x2a074, 1609 .enable_mask = BIT(0), 1610 .hw.init = &(const struct clk_init_data) { 1611 .name = "ne_gcc_usb3_prim_phy_pipe_clk", 1612 .parent_hws = (const struct clk_hw*[]) { 1613 &ne_gcc_usb3_prim_phy_pipe_clk_src.clkr.hw, 1614 }, 1615 .num_parents = 1, 1616 .flags = CLK_SET_RATE_PARENT, 1617 .ops = &clk_branch2_ops, 1618 }, 1619 }, 1620 }; 1621 1622 static struct clk_branch ne_gcc_usb3_sec_phy_aux_clk = { 1623 .halt_reg = 0x2c06c, 1624 .halt_check = BRANCH_HALT, 1625 .clkr = { 1626 .enable_reg = 0x2c06c, 1627 .enable_mask = BIT(0), 1628 .hw.init = &(const struct clk_init_data) { 1629 .name = "ne_gcc_usb3_sec_phy_aux_clk", 1630 .parent_hws = (const struct clk_hw*[]) { 1631 &ne_gcc_usb3_sec_phy_aux_clk_src.clkr.hw, 1632 }, 1633 .num_parents = 1, 1634 .flags = CLK_SET_RATE_PARENT, 1635 .ops = &clk_branch2_ops, 1636 }, 1637 }, 1638 }; 1639 1640 static struct clk_branch ne_gcc_usb3_sec_phy_com_aux_clk = { 1641 .halt_reg = 0x2c070, 1642 .halt_check = BRANCH_HALT, 1643 .clkr = { 1644 .enable_reg = 0x2c070, 1645 .enable_mask = BIT(0), 1646 .hw.init = &(const struct clk_init_data) { 1647 .name = "ne_gcc_usb3_sec_phy_com_aux_clk", 1648 .parent_hws = (const struct clk_hw*[]) { 1649 &ne_gcc_usb3_sec_phy_aux_clk_src.clkr.hw, 1650 }, 1651 .num_parents = 1, 1652 .flags = CLK_SET_RATE_PARENT, 1653 .ops = &clk_branch2_ops, 1654 }, 1655 }, 1656 }; 1657 1658 static struct clk_branch ne_gcc_usb3_sec_phy_pipe_clk = { 1659 .halt_reg = 0x2c074, 1660 .halt_check = BRANCH_HALT_SKIP, 1661 .hwcg_reg = 0x2c074, 1662 .hwcg_bit = 1, 1663 .clkr = { 1664 .enable_reg = 0x2c074, 1665 .enable_mask = BIT(0), 1666 .hw.init = &(const struct clk_init_data) { 1667 .name = "ne_gcc_usb3_sec_phy_pipe_clk", 1668 .parent_hws = (const struct clk_hw*[]) { 1669 &ne_gcc_usb3_sec_phy_pipe_clk_src.clkr.hw, 1670 }, 1671 .num_parents = 1, 1672 .flags = CLK_SET_RATE_PARENT, 1673 .ops = &clk_branch2_ops, 1674 }, 1675 }, 1676 }; 1677 1678 static struct gdsc ne_gcc_ufs_mem_phy_gdsc = { 1679 .gdscr = 0x32000, 1680 .en_rest_wait_val = 0x2, 1681 .en_few_wait_val = 0x2, 1682 .clk_dis_wait_val = 0x2, 1683 .pd = { 1684 .name = "ne_gcc_ufs_mem_phy_gdsc", 1685 }, 1686 .pwrsts = PWRSTS_OFF_ON, 1687 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 1688 }; 1689 1690 static struct gdsc ne_gcc_ufs_phy_gdsc = { 1691 .gdscr = 0x33004, 1692 .en_rest_wait_val = 0x2, 1693 .en_few_wait_val = 0x2, 1694 .clk_dis_wait_val = 0xf, 1695 .pd = { 1696 .name = "ne_gcc_ufs_phy_gdsc", 1697 }, 1698 .pwrsts = PWRSTS_OFF_ON, 1699 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 1700 }; 1701 1702 static struct gdsc ne_gcc_usb20_prim_gdsc = { 1703 .gdscr = 0x31004, 1704 .en_rest_wait_val = 0x2, 1705 .en_few_wait_val = 0x2, 1706 .clk_dis_wait_val = 0xf, 1707 .pd = { 1708 .name = "ne_gcc_usb20_prim_gdsc", 1709 }, 1710 .pwrsts = PWRSTS_OFF_ON, 1711 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 1712 }; 1713 1714 static struct gdsc ne_gcc_usb31_prim_gdsc = { 1715 .gdscr = 0x2a004, 1716 .en_rest_wait_val = 0x2, 1717 .en_few_wait_val = 0x2, 1718 .clk_dis_wait_val = 0xf, 1719 .pd = { 1720 .name = "ne_gcc_usb31_prim_gdsc", 1721 }, 1722 .pwrsts = PWRSTS_OFF_ON, 1723 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 1724 }; 1725 1726 static struct gdsc ne_gcc_usb31_sec_gdsc = { 1727 .gdscr = 0x2c004, 1728 .en_rest_wait_val = 0x2, 1729 .en_few_wait_val = 0x2, 1730 .clk_dis_wait_val = 0xf, 1731 .pd = { 1732 .name = "ne_gcc_usb31_sec_gdsc", 1733 }, 1734 .pwrsts = PWRSTS_OFF_ON, 1735 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 1736 }; 1737 1738 static struct gdsc ne_gcc_usb3_phy_gdsc = { 1739 .gdscr = 0x2b00c, 1740 .en_rest_wait_val = 0x2, 1741 .en_few_wait_val = 0x2, 1742 .clk_dis_wait_val = 0x2, 1743 .pd = { 1744 .name = "ne_gcc_usb3_phy_gdsc", 1745 }, 1746 .pwrsts = PWRSTS_OFF_ON, 1747 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 1748 }; 1749 1750 static struct gdsc ne_gcc_usb3_sec_phy_gdsc = { 1751 .gdscr = 0x2d00c, 1752 .en_rest_wait_val = 0x2, 1753 .en_few_wait_val = 0x2, 1754 .clk_dis_wait_val = 0x2, 1755 .pd = { 1756 .name = "ne_gcc_usb3_sec_phy_gdsc", 1757 }, 1758 .pwrsts = PWRSTS_OFF_ON, 1759 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 1760 }; 1761 1762 static struct clk_regmap *ne_gcc_nord_clocks[] = { 1763 [NE_GCC_AGGRE_NOC_UFS_PHY_AXI_CLK] = &ne_gcc_aggre_noc_ufs_phy_axi_clk.clkr, 1764 [NE_GCC_AGGRE_NOC_USB2_AXI_CLK] = &ne_gcc_aggre_noc_usb2_axi_clk.clkr, 1765 [NE_GCC_AGGRE_NOC_USB3_PRIM_AXI_CLK] = &ne_gcc_aggre_noc_usb3_prim_axi_clk.clkr, 1766 [NE_GCC_AGGRE_NOC_USB3_SEC_AXI_CLK] = &ne_gcc_aggre_noc_usb3_sec_axi_clk.clkr, 1767 [NE_GCC_AHB2PHY_CLK] = &ne_gcc_ahb2phy_clk.clkr, 1768 [NE_GCC_CNOC_USB2_AXI_CLK] = &ne_gcc_cnoc_usb2_axi_clk.clkr, 1769 [NE_GCC_CNOC_USB3_PRIM_AXI_CLK] = &ne_gcc_cnoc_usb3_prim_axi_clk.clkr, 1770 [NE_GCC_CNOC_USB3_SEC_AXI_CLK] = &ne_gcc_cnoc_usb3_sec_axi_clk.clkr, 1771 [NE_GCC_FRQ_MEASURE_REF_CLK] = &ne_gcc_frq_measure_ref_clk.clkr, 1772 [NE_GCC_GP1_CLK] = &ne_gcc_gp1_clk.clkr, 1773 [NE_GCC_GP1_CLK_SRC] = &ne_gcc_gp1_clk_src.clkr, 1774 [NE_GCC_GP2_CLK] = &ne_gcc_gp2_clk.clkr, 1775 [NE_GCC_GP2_CLK_SRC] = &ne_gcc_gp2_clk_src.clkr, 1776 [NE_GCC_GPLL0] = &ne_gcc_gpll0.clkr, 1777 [NE_GCC_GPLL0_OUT_EVEN] = &ne_gcc_gpll0_out_even.clkr, 1778 [NE_GCC_GPLL2] = &ne_gcc_gpll2.clkr, 1779 [NE_GCC_GPU_2_GPLL0_CLK_SRC] = &ne_gcc_gpu_2_gpll0_clk_src.clkr, 1780 [NE_GCC_GPU_2_GPLL0_DIV_CLK_SRC] = &ne_gcc_gpu_2_gpll0_div_clk_src.clkr, 1781 [NE_GCC_GPU_2_HSCNOC_GFX_CLK] = &ne_gcc_gpu_2_hscnoc_gfx_clk.clkr, 1782 [NE_GCC_GPU_2_SMMU_VOTE_CLK] = &ne_gcc_gpu_2_smmu_vote_clk.clkr, 1783 [NE_GCC_QUPV3_WRAP2_CORE_2X_CLK] = &ne_gcc_qupv3_wrap2_core_2x_clk.clkr, 1784 [NE_GCC_QUPV3_WRAP2_CORE_CLK] = &ne_gcc_qupv3_wrap2_core_clk.clkr, 1785 [NE_GCC_QUPV3_WRAP2_M_AHB_CLK] = &ne_gcc_qupv3_wrap2_m_ahb_clk.clkr, 1786 [NE_GCC_QUPV3_WRAP2_S0_CLK] = &ne_gcc_qupv3_wrap2_s0_clk.clkr, 1787 [NE_GCC_QUPV3_WRAP2_S0_CLK_SRC] = &ne_gcc_qupv3_wrap2_s0_clk_src.clkr, 1788 [NE_GCC_QUPV3_WRAP2_S1_CLK] = &ne_gcc_qupv3_wrap2_s1_clk.clkr, 1789 [NE_GCC_QUPV3_WRAP2_S1_CLK_SRC] = &ne_gcc_qupv3_wrap2_s1_clk_src.clkr, 1790 [NE_GCC_QUPV3_WRAP2_S2_CLK] = &ne_gcc_qupv3_wrap2_s2_clk.clkr, 1791 [NE_GCC_QUPV3_WRAP2_S2_CLK_SRC] = &ne_gcc_qupv3_wrap2_s2_clk_src.clkr, 1792 [NE_GCC_QUPV3_WRAP2_S3_CLK] = &ne_gcc_qupv3_wrap2_s3_clk.clkr, 1793 [NE_GCC_QUPV3_WRAP2_S3_CLK_SRC] = &ne_gcc_qupv3_wrap2_s3_clk_src.clkr, 1794 [NE_GCC_QUPV3_WRAP2_S4_CLK] = &ne_gcc_qupv3_wrap2_s4_clk.clkr, 1795 [NE_GCC_QUPV3_WRAP2_S4_CLK_SRC] = &ne_gcc_qupv3_wrap2_s4_clk_src.clkr, 1796 [NE_GCC_QUPV3_WRAP2_S5_CLK] = &ne_gcc_qupv3_wrap2_s5_clk.clkr, 1797 [NE_GCC_QUPV3_WRAP2_S5_CLK_SRC] = &ne_gcc_qupv3_wrap2_s5_clk_src.clkr, 1798 [NE_GCC_QUPV3_WRAP2_S6_CLK] = &ne_gcc_qupv3_wrap2_s6_clk.clkr, 1799 [NE_GCC_QUPV3_WRAP2_S6_CLK_SRC] = &ne_gcc_qupv3_wrap2_s6_clk_src.clkr, 1800 [NE_GCC_QUPV3_WRAP2_S_AHB_CLK] = &ne_gcc_qupv3_wrap2_s_ahb_clk.clkr, 1801 [NE_GCC_SDCC4_APPS_CLK] = &ne_gcc_sdcc4_apps_clk.clkr, 1802 [NE_GCC_SDCC4_APPS_CLK_SRC] = &ne_gcc_sdcc4_apps_clk_src.clkr, 1803 [NE_GCC_SDCC4_AXI_CLK] = &ne_gcc_sdcc4_axi_clk.clkr, 1804 [NE_GCC_UFS_PHY_AHB_CLK] = &ne_gcc_ufs_phy_ahb_clk.clkr, 1805 [NE_GCC_UFS_PHY_AXI_CLK] = &ne_gcc_ufs_phy_axi_clk.clkr, 1806 [NE_GCC_UFS_PHY_AXI_CLK_SRC] = &ne_gcc_ufs_phy_axi_clk_src.clkr, 1807 [NE_GCC_UFS_PHY_ICE_CORE_CLK] = &ne_gcc_ufs_phy_ice_core_clk.clkr, 1808 [NE_GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &ne_gcc_ufs_phy_ice_core_clk_src.clkr, 1809 [NE_GCC_UFS_PHY_PHY_AUX_CLK] = &ne_gcc_ufs_phy_phy_aux_clk.clkr, 1810 [NE_GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &ne_gcc_ufs_phy_phy_aux_clk_src.clkr, 1811 [NE_GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &ne_gcc_ufs_phy_rx_symbol_0_clk.clkr, 1812 [NE_GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC] = &ne_gcc_ufs_phy_rx_symbol_0_clk_src.clkr, 1813 [NE_GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &ne_gcc_ufs_phy_rx_symbol_1_clk.clkr, 1814 [NE_GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC] = &ne_gcc_ufs_phy_rx_symbol_1_clk_src.clkr, 1815 [NE_GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &ne_gcc_ufs_phy_tx_symbol_0_clk.clkr, 1816 [NE_GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC] = &ne_gcc_ufs_phy_tx_symbol_0_clk_src.clkr, 1817 [NE_GCC_UFS_PHY_UNIPRO_CORE_CLK] = &ne_gcc_ufs_phy_unipro_core_clk.clkr, 1818 [NE_GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] = &ne_gcc_ufs_phy_unipro_core_clk_src.clkr, 1819 [NE_GCC_USB20_MASTER_CLK] = &ne_gcc_usb20_master_clk.clkr, 1820 [NE_GCC_USB20_MASTER_CLK_SRC] = &ne_gcc_usb20_master_clk_src.clkr, 1821 [NE_GCC_USB20_MOCK_UTMI_CLK] = &ne_gcc_usb20_mock_utmi_clk.clkr, 1822 [NE_GCC_USB20_MOCK_UTMI_CLK_SRC] = &ne_gcc_usb20_mock_utmi_clk_src.clkr, 1823 [NE_GCC_USB20_MOCK_UTMI_POSTDIV_CLK_SRC] = &ne_gcc_usb20_mock_utmi_postdiv_clk_src.clkr, 1824 [NE_GCC_USB20_SLEEP_CLK] = &ne_gcc_usb20_sleep_clk.clkr, 1825 [NE_GCC_USB31_PRIM_ATB_CLK] = &ne_gcc_usb31_prim_atb_clk.clkr, 1826 [NE_GCC_USB31_PRIM_EUD_AHB_CLK] = &ne_gcc_usb31_prim_eud_ahb_clk.clkr, 1827 [NE_GCC_USB31_PRIM_MASTER_CLK] = &ne_gcc_usb31_prim_master_clk.clkr, 1828 [NE_GCC_USB31_PRIM_MASTER_CLK_SRC] = &ne_gcc_usb31_prim_master_clk_src.clkr, 1829 [NE_GCC_USB31_PRIM_MOCK_UTMI_CLK] = &ne_gcc_usb31_prim_mock_utmi_clk.clkr, 1830 [NE_GCC_USB31_PRIM_MOCK_UTMI_CLK_SRC] = &ne_gcc_usb31_prim_mock_utmi_clk_src.clkr, 1831 [NE_GCC_USB31_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC] = 1832 &ne_gcc_usb31_prim_mock_utmi_postdiv_clk_src.clkr, 1833 [NE_GCC_USB31_PRIM_SLEEP_CLK] = &ne_gcc_usb31_prim_sleep_clk.clkr, 1834 [NE_GCC_USB31_SEC_ATB_CLK] = &ne_gcc_usb31_sec_atb_clk.clkr, 1835 [NE_GCC_USB31_SEC_EUD_AHB_CLK] = &ne_gcc_usb31_sec_eud_ahb_clk.clkr, 1836 [NE_GCC_USB31_SEC_MASTER_CLK] = &ne_gcc_usb31_sec_master_clk.clkr, 1837 [NE_GCC_USB31_SEC_MASTER_CLK_SRC] = &ne_gcc_usb31_sec_master_clk_src.clkr, 1838 [NE_GCC_USB31_SEC_MOCK_UTMI_CLK] = &ne_gcc_usb31_sec_mock_utmi_clk.clkr, 1839 [NE_GCC_USB31_SEC_MOCK_UTMI_CLK_SRC] = &ne_gcc_usb31_sec_mock_utmi_clk_src.clkr, 1840 [NE_GCC_USB31_SEC_MOCK_UTMI_POSTDIV_CLK_SRC] = 1841 &ne_gcc_usb31_sec_mock_utmi_postdiv_clk_src.clkr, 1842 [NE_GCC_USB31_SEC_SLEEP_CLK] = &ne_gcc_usb31_sec_sleep_clk.clkr, 1843 [NE_GCC_USB3_PRIM_PHY_AUX_CLK] = &ne_gcc_usb3_prim_phy_aux_clk.clkr, 1844 [NE_GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &ne_gcc_usb3_prim_phy_aux_clk_src.clkr, 1845 [NE_GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &ne_gcc_usb3_prim_phy_com_aux_clk.clkr, 1846 [NE_GCC_USB3_PRIM_PHY_PIPE_CLK] = &ne_gcc_usb3_prim_phy_pipe_clk.clkr, 1847 [NE_GCC_USB3_PRIM_PHY_PIPE_CLK_SRC] = &ne_gcc_usb3_prim_phy_pipe_clk_src.clkr, 1848 [NE_GCC_USB3_SEC_PHY_AUX_CLK] = &ne_gcc_usb3_sec_phy_aux_clk.clkr, 1849 [NE_GCC_USB3_SEC_PHY_AUX_CLK_SRC] = &ne_gcc_usb3_sec_phy_aux_clk_src.clkr, 1850 [NE_GCC_USB3_SEC_PHY_COM_AUX_CLK] = &ne_gcc_usb3_sec_phy_com_aux_clk.clkr, 1851 [NE_GCC_USB3_SEC_PHY_PIPE_CLK] = &ne_gcc_usb3_sec_phy_pipe_clk.clkr, 1852 [NE_GCC_USB3_SEC_PHY_PIPE_CLK_SRC] = &ne_gcc_usb3_sec_phy_pipe_clk_src.clkr, 1853 }; 1854 1855 static struct gdsc *ne_gcc_nord_gdscs[] = { 1856 [NE_GCC_UFS_MEM_PHY_GDSC] = &ne_gcc_ufs_mem_phy_gdsc, 1857 [NE_GCC_UFS_PHY_GDSC] = &ne_gcc_ufs_phy_gdsc, 1858 [NE_GCC_USB20_PRIM_GDSC] = &ne_gcc_usb20_prim_gdsc, 1859 [NE_GCC_USB31_PRIM_GDSC] = &ne_gcc_usb31_prim_gdsc, 1860 [NE_GCC_USB31_SEC_GDSC] = &ne_gcc_usb31_sec_gdsc, 1861 [NE_GCC_USB3_PHY_GDSC] = &ne_gcc_usb3_phy_gdsc, 1862 [NE_GCC_USB3_SEC_PHY_GDSC] = &ne_gcc_usb3_sec_phy_gdsc, 1863 }; 1864 1865 static const struct qcom_reset_map ne_gcc_nord_resets[] = { 1866 [NE_GCC_GPU_2_BCR] = { 0x34000 }, 1867 [NE_GCC_QUPV3_WRAPPER_2_BCR] = { 0x38000 }, 1868 [NE_GCC_SDCC4_BCR] = { 0x18000 }, 1869 [NE_GCC_UFS_PHY_BCR] = { 0x33000 }, 1870 [NE_GCC_USB20_PRIM_BCR] = { 0x31000 }, 1871 [NE_GCC_USB31_PRIM_BCR] = { 0x2a000 }, 1872 [NE_GCC_USB31_SEC_BCR] = { 0x2c000 }, 1873 [NE_GCC_USB3_DP_PHY_PRIM_BCR] = { 0x2b008 }, 1874 [NE_GCC_USB3_DP_PHY_SEC_BCR] = { 0x2d008 }, 1875 [NE_GCC_USB3_PHY_PRIM_BCR] = { 0x2b000 }, 1876 [NE_GCC_USB3_PHY_SEC_BCR] = { 0x2d000 }, 1877 [NE_GCC_USB3PHY_PHY_PRIM_BCR] = { 0x2b004 }, 1878 [NE_GCC_USB3PHY_PHY_SEC_BCR] = { 0x2d004 }, 1879 [NE_GCC_QUSB2PHY_PRIM_BCR] = { 0x2e000 }, 1880 }; 1881 1882 static const struct clk_rcg_dfs_data ne_gcc_nord_dfs_clocks[] = { 1883 DEFINE_RCG_DFS(ne_gcc_qupv3_wrap2_s0_clk_src), 1884 DEFINE_RCG_DFS(ne_gcc_qupv3_wrap2_s1_clk_src), 1885 DEFINE_RCG_DFS(ne_gcc_qupv3_wrap2_s2_clk_src), 1886 DEFINE_RCG_DFS(ne_gcc_qupv3_wrap2_s3_clk_src), 1887 DEFINE_RCG_DFS(ne_gcc_qupv3_wrap2_s4_clk_src), 1888 DEFINE_RCG_DFS(ne_gcc_qupv3_wrap2_s5_clk_src), 1889 DEFINE_RCG_DFS(ne_gcc_qupv3_wrap2_s6_clk_src), 1890 }; 1891 1892 static const struct regmap_config ne_gcc_nord_regmap_config = { 1893 .reg_bits = 32, 1894 .reg_stride = 4, 1895 .val_bits = 32, 1896 .max_register = 0xf41f0, 1897 .fast_io = true, 1898 }; 1899 1900 static void clk_nord_regs_configure(struct device *dev, struct regmap *regmap) 1901 { 1902 /* FORCE_MEM_CORE_ON for ne_gcc_ufs_phy_ice_core_clk and ne_gcc_ufs_phy_axi_clk */ 1903 qcom_branch_set_force_mem_core(regmap, ne_gcc_ufs_phy_ice_core_clk, true); 1904 qcom_branch_set_force_mem_core(regmap, ne_gcc_ufs_phy_axi_clk, true); 1905 } 1906 1907 static const u32 ne_gcc_nord_critical_cbcrs[] = { 1908 0x34004, /* NE_GCC_GPU_2_CFG_CLK */ 1909 }; 1910 1911 static const struct qcom_cc_driver_data ne_gcc_nord_driver_data = { 1912 .dfs_rcgs = ne_gcc_nord_dfs_clocks, 1913 .num_dfs_rcgs = ARRAY_SIZE(ne_gcc_nord_dfs_clocks), 1914 .clk_regs_configure = clk_nord_regs_configure, 1915 .clk_cbcrs = ne_gcc_nord_critical_cbcrs, 1916 .num_clk_cbcrs = ARRAY_SIZE(ne_gcc_nord_critical_cbcrs), 1917 }; 1918 1919 static const struct qcom_cc_desc ne_gcc_nord_desc = { 1920 .config = &ne_gcc_nord_regmap_config, 1921 .clks = ne_gcc_nord_clocks, 1922 .num_clks = ARRAY_SIZE(ne_gcc_nord_clocks), 1923 .resets = ne_gcc_nord_resets, 1924 .num_resets = ARRAY_SIZE(ne_gcc_nord_resets), 1925 .gdscs = ne_gcc_nord_gdscs, 1926 .num_gdscs = ARRAY_SIZE(ne_gcc_nord_gdscs), 1927 .driver_data = &ne_gcc_nord_driver_data, 1928 }; 1929 1930 static const struct of_device_id ne_gcc_nord_match_table[] = { 1931 { .compatible = "qcom,nord-negcc" }, 1932 { } 1933 }; 1934 MODULE_DEVICE_TABLE(of, ne_gcc_nord_match_table); 1935 1936 static int ne_gcc_nord_probe(struct platform_device *pdev) 1937 { 1938 return qcom_cc_probe(pdev, &ne_gcc_nord_desc); 1939 } 1940 1941 static struct platform_driver ne_gcc_nord_driver = { 1942 .probe = ne_gcc_nord_probe, 1943 .driver = { 1944 .name = "negcc-nord", 1945 .of_match_table = ne_gcc_nord_match_table, 1946 }, 1947 }; 1948 1949 module_platform_driver(ne_gcc_nord_driver); 1950 1951 MODULE_DESCRIPTION("QTI NEGCC NORD Driver"); 1952 MODULE_LICENSE("GPL"); 1953