1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 4 */ 5 6 #include <linux/clk-provider.h> 7 #include <linux/mod_devicetable.h> 8 #include <linux/module.h> 9 #include <linux/platform_device.h> 10 #include <linux/regmap.h> 11 12 #include <dt-bindings/clock/qcom,nord-negcc.h> 13 14 #include "clk-alpha-pll.h" 15 #include "clk-branch.h" 16 #include "clk-pll.h" 17 #include "clk-rcg.h" 18 #include "clk-regmap.h" 19 #include "clk-regmap-divider.h" 20 #include "clk-regmap-mux.h" 21 #include "clk-regmap-phy-mux.h" 22 #include "common.h" 23 #include "gdsc.h" 24 #include "reset.h" 25 26 enum { 27 DT_BI_TCXO, 28 DT_SLEEP_CLK, 29 DT_UFS_PHY_RX_SYMBOL_0_CLK, 30 DT_UFS_PHY_RX_SYMBOL_1_CLK, 31 DT_UFS_PHY_TX_SYMBOL_0_CLK, 32 DT_USB3_PHY_SEC_WRAPPER_NE_GCC_USB31_PIPE_CLK, 33 DT_USB3_PHY_WRAPPER_NE_GCC_USB31_PIPE_CLK, 34 }; 35 36 enum { 37 P_BI_TCXO, 38 P_NE_GCC_GPLL0_OUT_EVEN, 39 P_NE_GCC_GPLL0_OUT_MAIN, 40 P_NE_GCC_GPLL2_OUT_MAIN, 41 P_SLEEP_CLK, 42 P_UFS_PHY_RX_SYMBOL_0_CLK, 43 P_UFS_PHY_RX_SYMBOL_1_CLK, 44 P_UFS_PHY_TX_SYMBOL_0_CLK, 45 P_USB3_PHY_SEC_WRAPPER_NE_GCC_USB31_PIPE_CLK, 46 P_USB3_PHY_WRAPPER_NE_GCC_USB31_PIPE_CLK, 47 }; 48 49 static struct clk_alpha_pll ne_gcc_gpll0 = { 50 .offset = 0x0, 51 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 52 .clkr = { 53 .enable_reg = 0x0, 54 .enable_mask = BIT(0), 55 .hw.init = &(const struct clk_init_data) { 56 .name = "ne_gcc_gpll0", 57 .parent_data = &(const struct clk_parent_data) { 58 .index = DT_BI_TCXO, 59 }, 60 .num_parents = 1, 61 .ops = &clk_alpha_pll_fixed_lucid_ole_ops, 62 }, 63 }, 64 }; 65 66 static const struct clk_div_table post_div_table_ne_gcc_gpll0_out_even[] = { 67 { 0x1, 2 }, 68 { } 69 }; 70 71 static struct clk_alpha_pll_postdiv ne_gcc_gpll0_out_even = { 72 .offset = 0x0, 73 .post_div_shift = 10, 74 .post_div_table = post_div_table_ne_gcc_gpll0_out_even, 75 .num_post_div = ARRAY_SIZE(post_div_table_ne_gcc_gpll0_out_even), 76 .width = 4, 77 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 78 .clkr.hw.init = &(const struct clk_init_data) { 79 .name = "ne_gcc_gpll0_out_even", 80 .parent_hws = (const struct clk_hw*[]) { 81 &ne_gcc_gpll0.clkr.hw, 82 }, 83 .num_parents = 1, 84 .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, 85 }, 86 }; 87 88 static struct clk_alpha_pll ne_gcc_gpll2 = { 89 .offset = 0x2000, 90 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 91 .clkr = { 92 .enable_reg = 0x0, 93 .enable_mask = BIT(2), 94 .hw.init = &(const struct clk_init_data) { 95 .name = "ne_gcc_gpll2", 96 .parent_data = &(const struct clk_parent_data) { 97 .index = DT_BI_TCXO, 98 }, 99 .num_parents = 1, 100 .ops = &clk_alpha_pll_fixed_lucid_ole_ops, 101 }, 102 }, 103 }; 104 105 static const struct parent_map ne_gcc_parent_map_0[] = { 106 { P_BI_TCXO, 0 }, 107 { P_NE_GCC_GPLL0_OUT_MAIN, 1 }, 108 }; 109 110 static const struct clk_parent_data ne_gcc_parent_data_0[] = { 111 { .index = DT_BI_TCXO }, 112 { .hw = &ne_gcc_gpll0.clkr.hw }, 113 }; 114 115 static const struct parent_map ne_gcc_parent_map_1[] = { 116 { P_BI_TCXO, 0 }, 117 { P_NE_GCC_GPLL0_OUT_MAIN, 1 }, 118 { P_NE_GCC_GPLL0_OUT_EVEN, 5 }, 119 }; 120 121 static const struct clk_parent_data ne_gcc_parent_data_1[] = { 122 { .index = DT_BI_TCXO }, 123 { .hw = &ne_gcc_gpll0.clkr.hw }, 124 { .hw = &ne_gcc_gpll0_out_even.clkr.hw }, 125 }; 126 127 static const struct parent_map ne_gcc_parent_map_2[] = { 128 { P_BI_TCXO, 0 }, 129 { P_NE_GCC_GPLL0_OUT_MAIN, 1 }, 130 { P_NE_GCC_GPLL2_OUT_MAIN, 3 }, 131 }; 132 133 static const struct clk_parent_data ne_gcc_parent_data_2[] = { 134 { .index = DT_BI_TCXO }, 135 { .hw = &ne_gcc_gpll0.clkr.hw }, 136 { .hw = &ne_gcc_gpll2.clkr.hw }, 137 }; 138 139 static const struct parent_map ne_gcc_parent_map_3[] = { 140 { P_BI_TCXO, 0 }, 141 { P_SLEEP_CLK, 5 }, 142 }; 143 144 static const struct clk_parent_data ne_gcc_parent_data_3[] = { 145 { .index = DT_BI_TCXO }, 146 { .index = DT_SLEEP_CLK }, 147 }; 148 149 static const struct parent_map ne_gcc_parent_map_4[] = { 150 { P_BI_TCXO, 0 }, 151 { P_NE_GCC_GPLL0_OUT_MAIN, 1 }, 152 { P_SLEEP_CLK, 5 }, 153 }; 154 155 static const struct clk_parent_data ne_gcc_parent_data_4[] = { 156 { .index = DT_BI_TCXO }, 157 { .hw = &ne_gcc_gpll0.clkr.hw }, 158 { .index = DT_SLEEP_CLK }, 159 }; 160 161 static const struct parent_map ne_gcc_parent_map_5[] = { 162 { P_BI_TCXO, 0 }, 163 }; 164 165 static const struct clk_parent_data ne_gcc_parent_data_5[] = { 166 { .index = DT_BI_TCXO }, 167 }; 168 169 static const struct parent_map ne_gcc_parent_map_6[] = { 170 { P_USB3_PHY_WRAPPER_NE_GCC_USB31_PIPE_CLK, 0 }, 171 { P_BI_TCXO, 2 }, 172 }; 173 174 static const struct clk_parent_data ne_gcc_parent_data_6[] = { 175 { .index = DT_USB3_PHY_WRAPPER_NE_GCC_USB31_PIPE_CLK }, 176 { .index = DT_BI_TCXO }, 177 }; 178 179 static const struct parent_map ne_gcc_parent_map_7[] = { 180 { P_USB3_PHY_SEC_WRAPPER_NE_GCC_USB31_PIPE_CLK, 0 }, 181 { P_BI_TCXO, 2 }, 182 }; 183 184 static const struct clk_parent_data ne_gcc_parent_data_7[] = { 185 { .index = DT_USB3_PHY_SEC_WRAPPER_NE_GCC_USB31_PIPE_CLK }, 186 { .index = DT_BI_TCXO }, 187 }; 188 189 static struct clk_regmap_phy_mux ne_gcc_ufs_phy_rx_symbol_0_clk_src = { 190 .reg = 0x33068, 191 .clkr = { 192 .hw.init = &(const struct clk_init_data) { 193 .name = "ne_gcc_ufs_phy_rx_symbol_0_clk_src", 194 .parent_data = &(const struct clk_parent_data){ 195 .index = DT_UFS_PHY_RX_SYMBOL_0_CLK, 196 }, 197 .num_parents = 1, 198 .ops = &clk_regmap_phy_mux_ops, 199 }, 200 }, 201 }; 202 203 static struct clk_regmap_phy_mux ne_gcc_ufs_phy_rx_symbol_1_clk_src = { 204 .reg = 0x330f0, 205 .clkr = { 206 .hw.init = &(const struct clk_init_data) { 207 .name = "ne_gcc_ufs_phy_rx_symbol_1_clk_src", 208 .parent_data = &(const struct clk_parent_data){ 209 .index = DT_UFS_PHY_RX_SYMBOL_1_CLK, 210 }, 211 .num_parents = 1, 212 .ops = &clk_regmap_phy_mux_ops, 213 }, 214 }, 215 }; 216 217 static struct clk_regmap_phy_mux ne_gcc_ufs_phy_tx_symbol_0_clk_src = { 218 .reg = 0x33058, 219 .clkr = { 220 .hw.init = &(const struct clk_init_data) { 221 .name = "ne_gcc_ufs_phy_tx_symbol_0_clk_src", 222 .parent_data = &(const struct clk_parent_data){ 223 .index = DT_UFS_PHY_TX_SYMBOL_0_CLK, 224 }, 225 .num_parents = 1, 226 .ops = &clk_regmap_phy_mux_ops, 227 }, 228 }, 229 }; 230 231 static struct clk_regmap_mux ne_gcc_usb3_prim_phy_pipe_clk_src = { 232 .reg = 0x2a078, 233 .shift = 0, 234 .width = 2, 235 .parent_map = ne_gcc_parent_map_6, 236 .clkr = { 237 .hw.init = &(const struct clk_init_data) { 238 .name = "ne_gcc_usb3_prim_phy_pipe_clk_src", 239 .parent_data = ne_gcc_parent_data_6, 240 .num_parents = ARRAY_SIZE(ne_gcc_parent_data_6), 241 .ops = &clk_regmap_mux_closest_ops, 242 }, 243 }, 244 }; 245 246 static struct clk_regmap_mux ne_gcc_usb3_sec_phy_pipe_clk_src = { 247 .reg = 0x2c078, 248 .shift = 0, 249 .width = 2, 250 .parent_map = ne_gcc_parent_map_7, 251 .clkr = { 252 .hw.init = &(const struct clk_init_data) { 253 .name = "ne_gcc_usb3_sec_phy_pipe_clk_src", 254 .parent_data = ne_gcc_parent_data_7, 255 .num_parents = ARRAY_SIZE(ne_gcc_parent_data_7), 256 .ops = &clk_regmap_mux_closest_ops, 257 }, 258 }, 259 }; 260 261 static const struct freq_tbl ftbl_ne_gcc_gp1_clk_src[] = { 262 F(66666667, P_NE_GCC_GPLL0_OUT_MAIN, 9, 0, 0), 263 F(100000000, P_NE_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 264 F(200000000, P_NE_GCC_GPLL0_OUT_MAIN, 3, 0, 0), 265 { } 266 }; 267 268 static struct clk_rcg2 ne_gcc_gp1_clk_src = { 269 .cmd_rcgr = 0x21004, 270 .mnd_width = 16, 271 .hid_width = 5, 272 .parent_map = ne_gcc_parent_map_4, 273 .freq_tbl = ftbl_ne_gcc_gp1_clk_src, 274 .hw_clk_ctrl = true, 275 .clkr.hw.init = &(const struct clk_init_data) { 276 .name = "ne_gcc_gp1_clk_src", 277 .parent_data = ne_gcc_parent_data_4, 278 .num_parents = ARRAY_SIZE(ne_gcc_parent_data_4), 279 .flags = CLK_SET_RATE_PARENT, 280 .ops = &clk_rcg2_shared_ops, 281 }, 282 }; 283 284 static struct clk_rcg2 ne_gcc_gp2_clk_src = { 285 .cmd_rcgr = 0x22004, 286 .mnd_width = 16, 287 .hid_width = 5, 288 .parent_map = ne_gcc_parent_map_4, 289 .freq_tbl = ftbl_ne_gcc_gp1_clk_src, 290 .hw_clk_ctrl = true, 291 .clkr.hw.init = &(const struct clk_init_data) { 292 .name = "ne_gcc_gp2_clk_src", 293 .parent_data = ne_gcc_parent_data_4, 294 .num_parents = ARRAY_SIZE(ne_gcc_parent_data_4), 295 .flags = CLK_SET_RATE_PARENT, 296 .ops = &clk_rcg2_shared_ops, 297 }, 298 }; 299 300 static const struct freq_tbl ftbl_ne_gcc_qupv3_wrap2_s0_clk_src[] = { 301 F(7372800, P_NE_GCC_GPLL0_OUT_MAIN, 1, 192, 15625), 302 F(14745600, P_NE_GCC_GPLL0_OUT_MAIN, 1, 384, 15625), 303 F(19200000, P_BI_TCXO, 1, 0, 0), 304 F(29491200, P_NE_GCC_GPLL0_OUT_MAIN, 1, 768, 15625), 305 F(32000000, P_NE_GCC_GPLL0_OUT_MAIN, 1, 4, 75), 306 F(48000000, P_NE_GCC_GPLL0_OUT_MAIN, 1, 2, 25), 307 F(51200000, P_NE_GCC_GPLL0_OUT_MAIN, 1, 32, 375), 308 F(64000000, P_NE_GCC_GPLL0_OUT_MAIN, 1, 8, 75), 309 F(66666667, P_NE_GCC_GPLL0_OUT_MAIN, 9, 0, 0), 310 F(75000000, P_NE_GCC_GPLL0_OUT_MAIN, 8, 0, 0), 311 F(80000000, P_NE_GCC_GPLL0_OUT_MAIN, 1, 2, 15), 312 F(96000000, P_NE_GCC_GPLL0_OUT_MAIN, 1, 4, 25), 313 F(100000000, P_NE_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 314 F(102400000, P_NE_GCC_GPLL0_OUT_MAIN, 1, 64, 375), 315 F(112000000, P_NE_GCC_GPLL0_OUT_MAIN, 1, 14, 75), 316 F(117964800, P_NE_GCC_GPLL0_OUT_MAIN, 1, 3072, 15625), 317 F(120000000, P_NE_GCC_GPLL0_OUT_MAIN, 5, 0, 0), 318 { } 319 }; 320 321 static struct clk_init_data ne_gcc_qupv3_wrap2_s0_clk_src_init = { 322 .name = "ne_gcc_qupv3_wrap2_s0_clk_src", 323 .parent_data = ne_gcc_parent_data_0, 324 .num_parents = ARRAY_SIZE(ne_gcc_parent_data_0), 325 .flags = CLK_SET_RATE_PARENT, 326 .ops = &clk_rcg2_shared_no_init_park_ops, 327 }; 328 329 static struct clk_rcg2 ne_gcc_qupv3_wrap2_s0_clk_src = { 330 .cmd_rcgr = 0x3816c, 331 .mnd_width = 16, 332 .hid_width = 5, 333 .parent_map = ne_gcc_parent_map_0, 334 .freq_tbl = ftbl_ne_gcc_qupv3_wrap2_s0_clk_src, 335 .hw_clk_ctrl = true, 336 .clkr.hw.init = &ne_gcc_qupv3_wrap2_s0_clk_src_init, 337 }; 338 339 static struct clk_init_data ne_gcc_qupv3_wrap2_s1_clk_src_init = { 340 .name = "ne_gcc_qupv3_wrap2_s1_clk_src", 341 .parent_data = ne_gcc_parent_data_0, 342 .num_parents = ARRAY_SIZE(ne_gcc_parent_data_0), 343 .flags = CLK_SET_RATE_PARENT, 344 .ops = &clk_rcg2_shared_no_init_park_ops, 345 }; 346 347 static struct clk_rcg2 ne_gcc_qupv3_wrap2_s1_clk_src = { 348 .cmd_rcgr = 0x382a8, 349 .mnd_width = 16, 350 .hid_width = 5, 351 .parent_map = ne_gcc_parent_map_0, 352 .freq_tbl = ftbl_ne_gcc_qupv3_wrap2_s0_clk_src, 353 .hw_clk_ctrl = true, 354 .clkr.hw.init = &ne_gcc_qupv3_wrap2_s1_clk_src_init, 355 }; 356 357 static const struct freq_tbl ftbl_ne_gcc_qupv3_wrap2_s2_clk_src[] = { 358 F(7372800, P_NE_GCC_GPLL0_OUT_MAIN, 1, 192, 15625), 359 F(14745600, P_NE_GCC_GPLL0_OUT_MAIN, 1, 384, 15625), 360 F(19200000, P_BI_TCXO, 1, 0, 0), 361 F(29491200, P_NE_GCC_GPLL0_OUT_MAIN, 1, 768, 15625), 362 F(32000000, P_NE_GCC_GPLL0_OUT_MAIN, 1, 4, 75), 363 F(48000000, P_NE_GCC_GPLL0_OUT_MAIN, 1, 2, 25), 364 F(51200000, P_NE_GCC_GPLL0_OUT_MAIN, 1, 32, 375), 365 F(64000000, P_NE_GCC_GPLL0_OUT_MAIN, 1, 8, 75), 366 F(66666667, P_NE_GCC_GPLL0_OUT_MAIN, 9, 0, 0), 367 F(75000000, P_NE_GCC_GPLL0_OUT_MAIN, 8, 0, 0), 368 F(80000000, P_NE_GCC_GPLL0_OUT_MAIN, 1, 2, 15), 369 F(96000000, P_NE_GCC_GPLL0_OUT_MAIN, 1, 4, 25), 370 F(100000000, P_NE_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 371 { } 372 }; 373 374 static struct clk_init_data ne_gcc_qupv3_wrap2_s2_clk_src_init = { 375 .name = "ne_gcc_qupv3_wrap2_s2_clk_src", 376 .parent_data = ne_gcc_parent_data_0, 377 .num_parents = ARRAY_SIZE(ne_gcc_parent_data_0), 378 .flags = CLK_SET_RATE_PARENT, 379 .ops = &clk_rcg2_shared_no_init_park_ops, 380 }; 381 382 static struct clk_rcg2 ne_gcc_qupv3_wrap2_s2_clk_src = { 383 .cmd_rcgr = 0x383e4, 384 .mnd_width = 16, 385 .hid_width = 5, 386 .parent_map = ne_gcc_parent_map_0, 387 .freq_tbl = ftbl_ne_gcc_qupv3_wrap2_s2_clk_src, 388 .hw_clk_ctrl = true, 389 .clkr.hw.init = &ne_gcc_qupv3_wrap2_s2_clk_src_init, 390 }; 391 392 static struct clk_init_data ne_gcc_qupv3_wrap2_s3_clk_src_init = { 393 .name = "ne_gcc_qupv3_wrap2_s3_clk_src", 394 .parent_data = ne_gcc_parent_data_0, 395 .num_parents = ARRAY_SIZE(ne_gcc_parent_data_0), 396 .flags = CLK_SET_RATE_PARENT, 397 .ops = &clk_rcg2_shared_no_init_park_ops, 398 }; 399 400 static struct clk_rcg2 ne_gcc_qupv3_wrap2_s3_clk_src = { 401 .cmd_rcgr = 0x38520, 402 .mnd_width = 16, 403 .hid_width = 5, 404 .parent_map = ne_gcc_parent_map_0, 405 .freq_tbl = ftbl_ne_gcc_qupv3_wrap2_s2_clk_src, 406 .hw_clk_ctrl = true, 407 .clkr.hw.init = &ne_gcc_qupv3_wrap2_s3_clk_src_init, 408 }; 409 410 static struct clk_init_data ne_gcc_qupv3_wrap2_s4_clk_src_init = { 411 .name = "ne_gcc_qupv3_wrap2_s4_clk_src", 412 .parent_data = ne_gcc_parent_data_0, 413 .num_parents = ARRAY_SIZE(ne_gcc_parent_data_0), 414 .flags = CLK_SET_RATE_PARENT, 415 .ops = &clk_rcg2_shared_no_init_park_ops, 416 }; 417 418 static struct clk_rcg2 ne_gcc_qupv3_wrap2_s4_clk_src = { 419 .cmd_rcgr = 0x3865c, 420 .mnd_width = 16, 421 .hid_width = 5, 422 .parent_map = ne_gcc_parent_map_0, 423 .freq_tbl = ftbl_ne_gcc_qupv3_wrap2_s2_clk_src, 424 .hw_clk_ctrl = true, 425 .clkr.hw.init = &ne_gcc_qupv3_wrap2_s4_clk_src_init, 426 }; 427 428 static struct clk_init_data ne_gcc_qupv3_wrap2_s5_clk_src_init = { 429 .name = "ne_gcc_qupv3_wrap2_s5_clk_src", 430 .parent_data = ne_gcc_parent_data_0, 431 .num_parents = ARRAY_SIZE(ne_gcc_parent_data_0), 432 .flags = CLK_SET_RATE_PARENT, 433 .ops = &clk_rcg2_shared_no_init_park_ops, 434 }; 435 436 static struct clk_rcg2 ne_gcc_qupv3_wrap2_s5_clk_src = { 437 .cmd_rcgr = 0x38798, 438 .mnd_width = 16, 439 .hid_width = 5, 440 .parent_map = ne_gcc_parent_map_0, 441 .freq_tbl = ftbl_ne_gcc_qupv3_wrap2_s2_clk_src, 442 .hw_clk_ctrl = true, 443 .clkr.hw.init = &ne_gcc_qupv3_wrap2_s5_clk_src_init, 444 }; 445 446 static struct clk_init_data ne_gcc_qupv3_wrap2_s6_clk_src_init = { 447 .name = "ne_gcc_qupv3_wrap2_s6_clk_src", 448 .parent_data = ne_gcc_parent_data_0, 449 .num_parents = ARRAY_SIZE(ne_gcc_parent_data_0), 450 .flags = CLK_SET_RATE_PARENT, 451 .ops = &clk_rcg2_shared_no_init_park_ops, 452 }; 453 454 static struct clk_rcg2 ne_gcc_qupv3_wrap2_s6_clk_src = { 455 .cmd_rcgr = 0x388d4, 456 .mnd_width = 16, 457 .hid_width = 5, 458 .parent_map = ne_gcc_parent_map_0, 459 .freq_tbl = ftbl_ne_gcc_qupv3_wrap2_s2_clk_src, 460 .hw_clk_ctrl = true, 461 .clkr.hw.init = &ne_gcc_qupv3_wrap2_s6_clk_src_init, 462 }; 463 464 static const struct freq_tbl ftbl_ne_gcc_sdcc4_apps_clk_src[] = { 465 F(37500000, P_NE_GCC_GPLL0_OUT_MAIN, 16, 0, 0), 466 F(50000000, P_NE_GCC_GPLL0_OUT_MAIN, 12, 0, 0), 467 F(100000000, P_NE_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 468 { } 469 }; 470 471 static struct clk_rcg2 ne_gcc_sdcc4_apps_clk_src = { 472 .cmd_rcgr = 0x1801c, 473 .mnd_width = 8, 474 .hid_width = 5, 475 .parent_map = ne_gcc_parent_map_0, 476 .freq_tbl = ftbl_ne_gcc_sdcc4_apps_clk_src, 477 .hw_clk_ctrl = true, 478 .clkr.hw.init = &(const struct clk_init_data) { 479 .name = "ne_gcc_sdcc4_apps_clk_src", 480 .parent_data = ne_gcc_parent_data_0, 481 .num_parents = ARRAY_SIZE(ne_gcc_parent_data_0), 482 .flags = CLK_SET_RATE_PARENT, 483 .ops = &clk_rcg2_shared_floor_ops, 484 }, 485 }; 486 487 static const struct freq_tbl ftbl_ne_gcc_ufs_phy_axi_clk_src[] = { 488 F(120000000, P_NE_GCC_GPLL0_OUT_MAIN, 5, 0, 0), 489 F(201500000, P_NE_GCC_GPLL2_OUT_MAIN, 4, 0, 0), 490 F(300000000, P_NE_GCC_GPLL0_OUT_MAIN, 2, 0, 0), 491 F(403000000, P_NE_GCC_GPLL2_OUT_MAIN, 2, 0, 0), 492 { } 493 }; 494 495 static struct clk_rcg2 ne_gcc_ufs_phy_axi_clk_src = { 496 .cmd_rcgr = 0x33034, 497 .mnd_width = 8, 498 .hid_width = 5, 499 .parent_map = ne_gcc_parent_map_2, 500 .freq_tbl = ftbl_ne_gcc_ufs_phy_axi_clk_src, 501 .hw_clk_ctrl = true, 502 .clkr.hw.init = &(const struct clk_init_data) { 503 .name = "ne_gcc_ufs_phy_axi_clk_src", 504 .parent_data = ne_gcc_parent_data_2, 505 .num_parents = ARRAY_SIZE(ne_gcc_parent_data_2), 506 .flags = CLK_SET_RATE_PARENT, 507 .ops = &clk_rcg2_shared_ops, 508 }, 509 }; 510 511 static struct clk_rcg2 ne_gcc_ufs_phy_ice_core_clk_src = { 512 .cmd_rcgr = 0x3308c, 513 .mnd_width = 0, 514 .hid_width = 5, 515 .parent_map = ne_gcc_parent_map_2, 516 .freq_tbl = ftbl_ne_gcc_ufs_phy_axi_clk_src, 517 .hw_clk_ctrl = true, 518 .clkr.hw.init = &(const struct clk_init_data) { 519 .name = "ne_gcc_ufs_phy_ice_core_clk_src", 520 .parent_data = ne_gcc_parent_data_2, 521 .num_parents = ARRAY_SIZE(ne_gcc_parent_data_2), 522 .flags = CLK_SET_RATE_PARENT, 523 .ops = &clk_rcg2_shared_ops, 524 }, 525 }; 526 527 static const struct freq_tbl ftbl_ne_gcc_ufs_phy_phy_aux_clk_src[] = { 528 F(19200000, P_BI_TCXO, 1, 0, 0), 529 { } 530 }; 531 532 static struct clk_rcg2 ne_gcc_ufs_phy_phy_aux_clk_src = { 533 .cmd_rcgr = 0x330c0, 534 .mnd_width = 0, 535 .hid_width = 5, 536 .parent_map = ne_gcc_parent_map_5, 537 .freq_tbl = ftbl_ne_gcc_ufs_phy_phy_aux_clk_src, 538 .hw_clk_ctrl = true, 539 .clkr.hw.init = &(const struct clk_init_data) { 540 .name = "ne_gcc_ufs_phy_phy_aux_clk_src", 541 .parent_data = ne_gcc_parent_data_5, 542 .num_parents = ARRAY_SIZE(ne_gcc_parent_data_5), 543 .flags = CLK_SET_RATE_PARENT, 544 .ops = &clk_rcg2_shared_ops, 545 }, 546 }; 547 548 static struct clk_rcg2 ne_gcc_ufs_phy_unipro_core_clk_src = { 549 .cmd_rcgr = 0x330a4, 550 .mnd_width = 0, 551 .hid_width = 5, 552 .parent_map = ne_gcc_parent_map_2, 553 .freq_tbl = ftbl_ne_gcc_ufs_phy_axi_clk_src, 554 .hw_clk_ctrl = true, 555 .clkr.hw.init = &(const struct clk_init_data) { 556 .name = "ne_gcc_ufs_phy_unipro_core_clk_src", 557 .parent_data = ne_gcc_parent_data_2, 558 .num_parents = ARRAY_SIZE(ne_gcc_parent_data_2), 559 .flags = CLK_SET_RATE_PARENT, 560 .ops = &clk_rcg2_shared_ops, 561 }, 562 }; 563 564 static const struct freq_tbl ftbl_ne_gcc_usb20_master_clk_src[] = { 565 F(75000000, P_NE_GCC_GPLL0_OUT_MAIN, 8, 0, 0), 566 F(120000000, P_NE_GCC_GPLL0_OUT_MAIN, 5, 0, 0), 567 { } 568 }; 569 570 static struct clk_rcg2 ne_gcc_usb20_master_clk_src = { 571 .cmd_rcgr = 0x31030, 572 .mnd_width = 8, 573 .hid_width = 5, 574 .parent_map = ne_gcc_parent_map_0, 575 .freq_tbl = ftbl_ne_gcc_usb20_master_clk_src, 576 .hw_clk_ctrl = true, 577 .clkr.hw.init = &(const struct clk_init_data) { 578 .name = "ne_gcc_usb20_master_clk_src", 579 .parent_data = ne_gcc_parent_data_0, 580 .num_parents = ARRAY_SIZE(ne_gcc_parent_data_0), 581 .flags = CLK_SET_RATE_PARENT, 582 .ops = &clk_rcg2_shared_ops, 583 }, 584 }; 585 586 static struct clk_rcg2 ne_gcc_usb20_mock_utmi_clk_src = { 587 .cmd_rcgr = 0x31048, 588 .mnd_width = 0, 589 .hid_width = 5, 590 .parent_map = ne_gcc_parent_map_0, 591 .freq_tbl = ftbl_ne_gcc_ufs_phy_phy_aux_clk_src, 592 .hw_clk_ctrl = true, 593 .clkr.hw.init = &(const struct clk_init_data) { 594 .name = "ne_gcc_usb20_mock_utmi_clk_src", 595 .parent_data = ne_gcc_parent_data_0, 596 .num_parents = ARRAY_SIZE(ne_gcc_parent_data_0), 597 .flags = CLK_SET_RATE_PARENT, 598 .ops = &clk_rcg2_shared_ops, 599 }, 600 }; 601 602 static const struct freq_tbl ftbl_ne_gcc_usb31_prim_master_clk_src[] = { 603 F(85714286, P_NE_GCC_GPLL0_OUT_MAIN, 7, 0, 0), 604 F(133333333, P_NE_GCC_GPLL0_OUT_MAIN, 4.5, 0, 0), 605 F(200000000, P_NE_GCC_GPLL0_OUT_MAIN, 3, 0, 0), 606 F(240000000, P_NE_GCC_GPLL0_OUT_MAIN, 2.5, 0, 0), 607 { } 608 }; 609 610 static struct clk_rcg2 ne_gcc_usb31_prim_master_clk_src = { 611 .cmd_rcgr = 0x2a038, 612 .mnd_width = 8, 613 .hid_width = 5, 614 .parent_map = ne_gcc_parent_map_1, 615 .freq_tbl = ftbl_ne_gcc_usb31_prim_master_clk_src, 616 .hw_clk_ctrl = true, 617 .clkr.hw.init = &(const struct clk_init_data) { 618 .name = "ne_gcc_usb31_prim_master_clk_src", 619 .parent_data = ne_gcc_parent_data_1, 620 .num_parents = ARRAY_SIZE(ne_gcc_parent_data_1), 621 .flags = CLK_SET_RATE_PARENT, 622 .ops = &clk_rcg2_shared_ops, 623 }, 624 }; 625 626 static struct clk_rcg2 ne_gcc_usb31_prim_mock_utmi_clk_src = { 627 .cmd_rcgr = 0x2a050, 628 .mnd_width = 0, 629 .hid_width = 5, 630 .parent_map = ne_gcc_parent_map_0, 631 .freq_tbl = ftbl_ne_gcc_ufs_phy_phy_aux_clk_src, 632 .hw_clk_ctrl = true, 633 .clkr.hw.init = &(const struct clk_init_data) { 634 .name = "ne_gcc_usb31_prim_mock_utmi_clk_src", 635 .parent_data = ne_gcc_parent_data_0, 636 .num_parents = ARRAY_SIZE(ne_gcc_parent_data_0), 637 .flags = CLK_SET_RATE_PARENT, 638 .ops = &clk_rcg2_shared_ops, 639 }, 640 }; 641 642 static struct clk_rcg2 ne_gcc_usb31_sec_master_clk_src = { 643 .cmd_rcgr = 0x2c038, 644 .mnd_width = 8, 645 .hid_width = 5, 646 .parent_map = ne_gcc_parent_map_0, 647 .freq_tbl = ftbl_ne_gcc_usb31_prim_master_clk_src, 648 .hw_clk_ctrl = true, 649 .clkr.hw.init = &(const struct clk_init_data) { 650 .name = "ne_gcc_usb31_sec_master_clk_src", 651 .parent_data = ne_gcc_parent_data_0, 652 .num_parents = ARRAY_SIZE(ne_gcc_parent_data_0), 653 .flags = CLK_SET_RATE_PARENT, 654 .ops = &clk_rcg2_shared_ops, 655 }, 656 }; 657 658 static struct clk_rcg2 ne_gcc_usb31_sec_mock_utmi_clk_src = { 659 .cmd_rcgr = 0x2c050, 660 .mnd_width = 0, 661 .hid_width = 5, 662 .parent_map = ne_gcc_parent_map_0, 663 .freq_tbl = ftbl_ne_gcc_ufs_phy_phy_aux_clk_src, 664 .hw_clk_ctrl = true, 665 .clkr.hw.init = &(const struct clk_init_data) { 666 .name = "ne_gcc_usb31_sec_mock_utmi_clk_src", 667 .parent_data = ne_gcc_parent_data_0, 668 .num_parents = ARRAY_SIZE(ne_gcc_parent_data_0), 669 .flags = CLK_SET_RATE_PARENT, 670 .ops = &clk_rcg2_shared_ops, 671 }, 672 }; 673 674 static struct clk_rcg2 ne_gcc_usb3_prim_phy_aux_clk_src = { 675 .cmd_rcgr = 0x2a07c, 676 .mnd_width = 0, 677 .hid_width = 5, 678 .parent_map = ne_gcc_parent_map_3, 679 .freq_tbl = ftbl_ne_gcc_ufs_phy_phy_aux_clk_src, 680 .hw_clk_ctrl = true, 681 .clkr.hw.init = &(const struct clk_init_data) { 682 .name = "ne_gcc_usb3_prim_phy_aux_clk_src", 683 .parent_data = ne_gcc_parent_data_3, 684 .num_parents = ARRAY_SIZE(ne_gcc_parent_data_3), 685 .flags = CLK_SET_RATE_PARENT, 686 .ops = &clk_rcg2_shared_ops, 687 }, 688 }; 689 690 static struct clk_rcg2 ne_gcc_usb3_sec_phy_aux_clk_src = { 691 .cmd_rcgr = 0x2c07c, 692 .mnd_width = 0, 693 .hid_width = 5, 694 .parent_map = ne_gcc_parent_map_3, 695 .freq_tbl = ftbl_ne_gcc_ufs_phy_phy_aux_clk_src, 696 .hw_clk_ctrl = true, 697 .clkr.hw.init = &(const struct clk_init_data) { 698 .name = "ne_gcc_usb3_sec_phy_aux_clk_src", 699 .parent_data = ne_gcc_parent_data_3, 700 .num_parents = ARRAY_SIZE(ne_gcc_parent_data_3), 701 .flags = CLK_SET_RATE_PARENT, 702 .ops = &clk_rcg2_shared_ops, 703 }, 704 }; 705 706 static struct clk_regmap_div ne_gcc_usb20_mock_utmi_postdiv_clk_src = { 707 .reg = 0x31060, 708 .shift = 0, 709 .width = 4, 710 .clkr.hw.init = &(const struct clk_init_data) { 711 .name = "ne_gcc_usb20_mock_utmi_postdiv_clk_src", 712 .parent_hws = (const struct clk_hw*[]) { 713 &ne_gcc_usb20_mock_utmi_clk_src.clkr.hw, 714 }, 715 .num_parents = 1, 716 .flags = CLK_SET_RATE_PARENT, 717 .ops = &clk_regmap_div_ro_ops, 718 }, 719 }; 720 721 static struct clk_regmap_div ne_gcc_usb31_prim_mock_utmi_postdiv_clk_src = { 722 .reg = 0x2a068, 723 .shift = 0, 724 .width = 4, 725 .clkr.hw.init = &(const struct clk_init_data) { 726 .name = "ne_gcc_usb31_prim_mock_utmi_postdiv_clk_src", 727 .parent_hws = (const struct clk_hw*[]) { 728 &ne_gcc_usb31_prim_mock_utmi_clk_src.clkr.hw, 729 }, 730 .num_parents = 1, 731 .flags = CLK_SET_RATE_PARENT, 732 .ops = &clk_regmap_div_ro_ops, 733 }, 734 }; 735 736 static struct clk_regmap_div ne_gcc_usb31_sec_mock_utmi_postdiv_clk_src = { 737 .reg = 0x2c068, 738 .shift = 0, 739 .width = 4, 740 .clkr.hw.init = &(const struct clk_init_data) { 741 .name = "ne_gcc_usb31_sec_mock_utmi_postdiv_clk_src", 742 .parent_hws = (const struct clk_hw*[]) { 743 &ne_gcc_usb31_sec_mock_utmi_clk_src.clkr.hw, 744 }, 745 .num_parents = 1, 746 .flags = CLK_SET_RATE_PARENT, 747 .ops = &clk_regmap_div_ro_ops, 748 }, 749 }; 750 751 static struct clk_branch ne_gcc_aggre_noc_ufs_phy_axi_clk = { 752 .halt_reg = 0x330f4, 753 .halt_check = BRANCH_HALT_VOTED, 754 .hwcg_reg = 0x330f4, 755 .hwcg_bit = 1, 756 .clkr = { 757 .enable_reg = 0x330f4, 758 .enable_mask = BIT(0), 759 .hw.init = &(const struct clk_init_data) { 760 .name = "ne_gcc_aggre_noc_ufs_phy_axi_clk", 761 .parent_hws = (const struct clk_hw*[]) { 762 &ne_gcc_ufs_phy_axi_clk_src.clkr.hw, 763 }, 764 .num_parents = 1, 765 .flags = CLK_SET_RATE_PARENT, 766 .ops = &clk_branch2_ops, 767 }, 768 }, 769 }; 770 771 static struct clk_branch ne_gcc_aggre_noc_usb2_axi_clk = { 772 .halt_reg = 0x31068, 773 .halt_check = BRANCH_HALT_VOTED, 774 .hwcg_reg = 0x31068, 775 .hwcg_bit = 1, 776 .clkr = { 777 .enable_reg = 0x31068, 778 .enable_mask = BIT(0), 779 .hw.init = &(const struct clk_init_data) { 780 .name = "ne_gcc_aggre_noc_usb2_axi_clk", 781 .parent_hws = (const struct clk_hw*[]) { 782 &ne_gcc_usb20_master_clk_src.clkr.hw, 783 }, 784 .num_parents = 1, 785 .flags = CLK_SET_RATE_PARENT, 786 .ops = &clk_branch2_ops, 787 }, 788 }, 789 }; 790 791 static struct clk_branch ne_gcc_aggre_noc_usb3_prim_axi_clk = { 792 .halt_reg = 0x2a098, 793 .halt_check = BRANCH_HALT_VOTED, 794 .hwcg_reg = 0x2a098, 795 .hwcg_bit = 1, 796 .clkr = { 797 .enable_reg = 0x2a098, 798 .enable_mask = BIT(0), 799 .hw.init = &(const struct clk_init_data) { 800 .name = "ne_gcc_aggre_noc_usb3_prim_axi_clk", 801 .parent_hws = (const struct clk_hw*[]) { 802 &ne_gcc_usb31_prim_master_clk_src.clkr.hw, 803 }, 804 .num_parents = 1, 805 .flags = CLK_SET_RATE_PARENT, 806 .ops = &clk_branch2_ops, 807 }, 808 }, 809 }; 810 811 static struct clk_branch ne_gcc_aggre_noc_usb3_sec_axi_clk = { 812 .halt_reg = 0x2c098, 813 .halt_check = BRANCH_HALT_VOTED, 814 .hwcg_reg = 0x2c098, 815 .hwcg_bit = 1, 816 .clkr = { 817 .enable_reg = 0x2c098, 818 .enable_mask = BIT(0), 819 .hw.init = &(const struct clk_init_data) { 820 .name = "ne_gcc_aggre_noc_usb3_sec_axi_clk", 821 .parent_hws = (const struct clk_hw*[]) { 822 &ne_gcc_usb31_sec_master_clk_src.clkr.hw, 823 }, 824 .num_parents = 1, 825 .flags = CLK_SET_RATE_PARENT, 826 .ops = &clk_branch2_ops, 827 }, 828 }, 829 }; 830 831 static struct clk_branch ne_gcc_ahb2phy_clk = { 832 .halt_reg = 0x30004, 833 .halt_check = BRANCH_HALT_VOTED, 834 .hwcg_reg = 0x30004, 835 .hwcg_bit = 1, 836 .clkr = { 837 .enable_reg = 0x30004, 838 .enable_mask = BIT(0), 839 .hw.init = &(const struct clk_init_data) { 840 .name = "ne_gcc_ahb2phy_clk", 841 .ops = &clk_branch2_ops, 842 }, 843 }, 844 }; 845 846 static struct clk_branch ne_gcc_cnoc_usb2_axi_clk = { 847 .halt_reg = 0x31064, 848 .halt_check = BRANCH_HALT_VOTED, 849 .hwcg_reg = 0x31064, 850 .hwcg_bit = 1, 851 .clkr = { 852 .enable_reg = 0x31064, 853 .enable_mask = BIT(0), 854 .hw.init = &(const struct clk_init_data) { 855 .name = "ne_gcc_cnoc_usb2_axi_clk", 856 .parent_hws = (const struct clk_hw*[]) { 857 &ne_gcc_usb20_master_clk_src.clkr.hw, 858 }, 859 .num_parents = 1, 860 .flags = CLK_SET_RATE_PARENT, 861 .ops = &clk_branch2_ops, 862 }, 863 }, 864 }; 865 866 static struct clk_branch ne_gcc_cnoc_usb3_prim_axi_clk = { 867 .halt_reg = 0x2a094, 868 .halt_check = BRANCH_HALT_VOTED, 869 .hwcg_reg = 0x2a094, 870 .hwcg_bit = 1, 871 .clkr = { 872 .enable_reg = 0x2a094, 873 .enable_mask = BIT(0), 874 .hw.init = &(const struct clk_init_data) { 875 .name = "ne_gcc_cnoc_usb3_prim_axi_clk", 876 .parent_hws = (const struct clk_hw*[]) { 877 &ne_gcc_usb31_prim_master_clk_src.clkr.hw, 878 }, 879 .num_parents = 1, 880 .flags = CLK_SET_RATE_PARENT, 881 .ops = &clk_branch2_ops, 882 }, 883 }, 884 }; 885 886 static struct clk_branch ne_gcc_cnoc_usb3_sec_axi_clk = { 887 .halt_reg = 0x2c094, 888 .halt_check = BRANCH_HALT_VOTED, 889 .hwcg_reg = 0x2c094, 890 .hwcg_bit = 1, 891 .clkr = { 892 .enable_reg = 0x2c094, 893 .enable_mask = BIT(0), 894 .hw.init = &(const struct clk_init_data) { 895 .name = "ne_gcc_cnoc_usb3_sec_axi_clk", 896 .parent_hws = (const struct clk_hw*[]) { 897 &ne_gcc_usb31_sec_master_clk_src.clkr.hw, 898 }, 899 .num_parents = 1, 900 .flags = CLK_SET_RATE_PARENT, 901 .ops = &clk_branch2_ops, 902 }, 903 }, 904 }; 905 906 static struct clk_branch ne_gcc_frq_measure_ref_clk = { 907 .halt_reg = 0x20008, 908 .halt_check = BRANCH_HALT, 909 .clkr = { 910 .enable_reg = 0x20008, 911 .enable_mask = BIT(0), 912 .hw.init = &(const struct clk_init_data) { 913 .name = "ne_gcc_frq_measure_ref_clk", 914 .ops = &clk_branch2_ops, 915 }, 916 }, 917 }; 918 919 static struct clk_branch ne_gcc_gp1_clk = { 920 .halt_reg = 0x21000, 921 .halt_check = BRANCH_HALT, 922 .clkr = { 923 .enable_reg = 0x21000, 924 .enable_mask = BIT(0), 925 .hw.init = &(const struct clk_init_data) { 926 .name = "ne_gcc_gp1_clk", 927 .parent_hws = (const struct clk_hw*[]) { 928 &ne_gcc_gp1_clk_src.clkr.hw, 929 }, 930 .num_parents = 1, 931 .flags = CLK_SET_RATE_PARENT, 932 .ops = &clk_branch2_ops, 933 }, 934 }, 935 }; 936 937 static struct clk_branch ne_gcc_gp2_clk = { 938 .halt_reg = 0x22000, 939 .halt_check = BRANCH_HALT, 940 .clkr = { 941 .enable_reg = 0x22000, 942 .enable_mask = BIT(0), 943 .hw.init = &(const struct clk_init_data) { 944 .name = "ne_gcc_gp2_clk", 945 .parent_hws = (const struct clk_hw*[]) { 946 &ne_gcc_gp2_clk_src.clkr.hw, 947 }, 948 .num_parents = 1, 949 .flags = CLK_SET_RATE_PARENT, 950 .ops = &clk_branch2_ops, 951 }, 952 }, 953 }; 954 955 static struct clk_branch ne_gcc_gpu_2_cfg_clk = { 956 .halt_reg = 0x34004, 957 .halt_check = BRANCH_HALT_VOTED, 958 .hwcg_reg = 0x34004, 959 .hwcg_bit = 1, 960 .clkr = { 961 .enable_reg = 0x34004, 962 .enable_mask = BIT(0), 963 .hw.init = &(const struct clk_init_data) { 964 .name = "ne_gcc_gpu_2_cfg_clk", 965 .ops = &clk_branch2_ops, 966 }, 967 }, 968 }; 969 970 static struct clk_branch ne_gcc_gpu_2_gpll0_clk_src = { 971 .halt_check = BRANCH_HALT_DELAY, 972 .clkr = { 973 .enable_reg = 0x57000, 974 .enable_mask = BIT(19), 975 .hw.init = &(const struct clk_init_data) { 976 .name = "ne_gcc_gpu_2_gpll0_clk_src", 977 .parent_hws = (const struct clk_hw*[]) { 978 &ne_gcc_gpll0.clkr.hw, 979 }, 980 .num_parents = 1, 981 .flags = CLK_SET_RATE_PARENT, 982 .ops = &clk_branch2_ops, 983 }, 984 }, 985 }; 986 987 static struct clk_branch ne_gcc_gpu_2_gpll0_div_clk_src = { 988 .halt_check = BRANCH_HALT_DELAY, 989 .clkr = { 990 .enable_reg = 0x57000, 991 .enable_mask = BIT(20), 992 .hw.init = &(const struct clk_init_data) { 993 .name = "ne_gcc_gpu_2_gpll0_div_clk_src", 994 .parent_hws = (const struct clk_hw*[]) { 995 &ne_gcc_gpll0_out_even.clkr.hw, 996 }, 997 .num_parents = 1, 998 .flags = CLK_SET_RATE_PARENT, 999 .ops = &clk_branch2_ops, 1000 }, 1001 }, 1002 }; 1003 1004 static struct clk_branch ne_gcc_gpu_2_hscnoc_gfx_clk = { 1005 .halt_reg = 0x34014, 1006 .halt_check = BRANCH_HALT_VOTED, 1007 .hwcg_reg = 0x34014, 1008 .hwcg_bit = 1, 1009 .clkr = { 1010 .enable_reg = 0x34014, 1011 .enable_mask = BIT(0), 1012 .hw.init = &(const struct clk_init_data) { 1013 .name = "ne_gcc_gpu_2_hscnoc_gfx_clk", 1014 .ops = &clk_branch2_ops, 1015 }, 1016 }, 1017 }; 1018 1019 static struct clk_branch ne_gcc_gpu_2_smmu_vote_clk = { 1020 .halt_reg = 0x57028, 1021 .halt_check = BRANCH_HALT_VOTED, 1022 .clkr = { 1023 .enable_reg = 0x57028, 1024 .enable_mask = BIT(0), 1025 .hw.init = &(const struct clk_init_data) { 1026 .name = "ne_gcc_gpu_2_smmu_vote_clk", 1027 .ops = &clk_branch2_ops, 1028 }, 1029 }, 1030 }; 1031 1032 static struct clk_branch ne_gcc_qupv3_wrap2_core_2x_clk = { 1033 .halt_reg = 0x38020, 1034 .halt_check = BRANCH_HALT_VOTED, 1035 .clkr = { 1036 .enable_reg = 0x57008, 1037 .enable_mask = BIT(1), 1038 .hw.init = &(const struct clk_init_data) { 1039 .name = "ne_gcc_qupv3_wrap2_core_2x_clk", 1040 .ops = &clk_branch2_ops, 1041 }, 1042 }, 1043 }; 1044 1045 static struct clk_branch ne_gcc_qupv3_wrap2_core_clk = { 1046 .halt_reg = 0x3800c, 1047 .halt_check = BRANCH_HALT_VOTED, 1048 .clkr = { 1049 .enable_reg = 0x57008, 1050 .enable_mask = BIT(0), 1051 .hw.init = &(const struct clk_init_data) { 1052 .name = "ne_gcc_qupv3_wrap2_core_clk", 1053 .ops = &clk_branch2_ops, 1054 }, 1055 }, 1056 }; 1057 1058 static struct clk_branch ne_gcc_qupv3_wrap2_m_ahb_clk = { 1059 .halt_reg = 0x38004, 1060 .halt_check = BRANCH_HALT_VOTED, 1061 .hwcg_reg = 0x38004, 1062 .hwcg_bit = 1, 1063 .clkr = { 1064 .enable_reg = 0x57000, 1065 .enable_mask = BIT(30), 1066 .hw.init = &(const struct clk_init_data) { 1067 .name = "ne_gcc_qupv3_wrap2_m_ahb_clk", 1068 .ops = &clk_branch2_ops, 1069 }, 1070 }, 1071 }; 1072 1073 static struct clk_branch ne_gcc_qupv3_wrap2_s0_clk = { 1074 .halt_reg = 0x3815c, 1075 .halt_check = BRANCH_HALT_VOTED, 1076 .clkr = { 1077 .enable_reg = 0x57008, 1078 .enable_mask = BIT(2), 1079 .hw.init = &(const struct clk_init_data) { 1080 .name = "ne_gcc_qupv3_wrap2_s0_clk", 1081 .parent_hws = (const struct clk_hw*[]) { 1082 &ne_gcc_qupv3_wrap2_s0_clk_src.clkr.hw, 1083 }, 1084 .num_parents = 1, 1085 .flags = CLK_SET_RATE_PARENT, 1086 .ops = &clk_branch2_ops, 1087 }, 1088 }, 1089 }; 1090 1091 static struct clk_branch ne_gcc_qupv3_wrap2_s1_clk = { 1092 .halt_reg = 0x38298, 1093 .halt_check = BRANCH_HALT_VOTED, 1094 .clkr = { 1095 .enable_reg = 0x57008, 1096 .enable_mask = BIT(3), 1097 .hw.init = &(const struct clk_init_data) { 1098 .name = "ne_gcc_qupv3_wrap2_s1_clk", 1099 .parent_hws = (const struct clk_hw*[]) { 1100 &ne_gcc_qupv3_wrap2_s1_clk_src.clkr.hw, 1101 }, 1102 .num_parents = 1, 1103 .flags = CLK_SET_RATE_PARENT, 1104 .ops = &clk_branch2_ops, 1105 }, 1106 }, 1107 }; 1108 1109 static struct clk_branch ne_gcc_qupv3_wrap2_s2_clk = { 1110 .halt_reg = 0x383d4, 1111 .halt_check = BRANCH_HALT_VOTED, 1112 .clkr = { 1113 .enable_reg = 0x57008, 1114 .enable_mask = BIT(4), 1115 .hw.init = &(const struct clk_init_data) { 1116 .name = "ne_gcc_qupv3_wrap2_s2_clk", 1117 .parent_hws = (const struct clk_hw*[]) { 1118 &ne_gcc_qupv3_wrap2_s2_clk_src.clkr.hw, 1119 }, 1120 .num_parents = 1, 1121 .flags = CLK_SET_RATE_PARENT, 1122 .ops = &clk_branch2_ops, 1123 }, 1124 }, 1125 }; 1126 1127 static struct clk_branch ne_gcc_qupv3_wrap2_s3_clk = { 1128 .halt_reg = 0x38510, 1129 .halt_check = BRANCH_HALT_VOTED, 1130 .clkr = { 1131 .enable_reg = 0x57008, 1132 .enable_mask = BIT(5), 1133 .hw.init = &(const struct clk_init_data) { 1134 .name = "ne_gcc_qupv3_wrap2_s3_clk", 1135 .parent_hws = (const struct clk_hw*[]) { 1136 &ne_gcc_qupv3_wrap2_s3_clk_src.clkr.hw, 1137 }, 1138 .num_parents = 1, 1139 .flags = CLK_SET_RATE_PARENT, 1140 .ops = &clk_branch2_ops, 1141 }, 1142 }, 1143 }; 1144 1145 static struct clk_branch ne_gcc_qupv3_wrap2_s4_clk = { 1146 .halt_reg = 0x3864c, 1147 .halt_check = BRANCH_HALT_VOTED, 1148 .clkr = { 1149 .enable_reg = 0x57008, 1150 .enable_mask = BIT(6), 1151 .hw.init = &(const struct clk_init_data) { 1152 .name = "ne_gcc_qupv3_wrap2_s4_clk", 1153 .parent_hws = (const struct clk_hw*[]) { 1154 &ne_gcc_qupv3_wrap2_s4_clk_src.clkr.hw, 1155 }, 1156 .num_parents = 1, 1157 .flags = CLK_SET_RATE_PARENT, 1158 .ops = &clk_branch2_ops, 1159 }, 1160 }, 1161 }; 1162 1163 static struct clk_branch ne_gcc_qupv3_wrap2_s5_clk = { 1164 .halt_reg = 0x38788, 1165 .halt_check = BRANCH_HALT_VOTED, 1166 .clkr = { 1167 .enable_reg = 0x57008, 1168 .enable_mask = BIT(7), 1169 .hw.init = &(const struct clk_init_data) { 1170 .name = "ne_gcc_qupv3_wrap2_s5_clk", 1171 .parent_hws = (const struct clk_hw*[]) { 1172 &ne_gcc_qupv3_wrap2_s5_clk_src.clkr.hw, 1173 }, 1174 .num_parents = 1, 1175 .flags = CLK_SET_RATE_PARENT, 1176 .ops = &clk_branch2_ops, 1177 }, 1178 }, 1179 }; 1180 1181 static struct clk_branch ne_gcc_qupv3_wrap2_s6_clk = { 1182 .halt_reg = 0x388c4, 1183 .halt_check = BRANCH_HALT_VOTED, 1184 .clkr = { 1185 .enable_reg = 0x57008, 1186 .enable_mask = BIT(8), 1187 .hw.init = &(const struct clk_init_data) { 1188 .name = "ne_gcc_qupv3_wrap2_s6_clk", 1189 .parent_hws = (const struct clk_hw*[]) { 1190 &ne_gcc_qupv3_wrap2_s6_clk_src.clkr.hw, 1191 }, 1192 .num_parents = 1, 1193 .flags = CLK_SET_RATE_PARENT, 1194 .ops = &clk_branch2_ops, 1195 }, 1196 }, 1197 }; 1198 1199 static struct clk_branch ne_gcc_qupv3_wrap2_s_ahb_clk = { 1200 .halt_reg = 0x38008, 1201 .halt_check = BRANCH_HALT_VOTED, 1202 .hwcg_reg = 0x38008, 1203 .hwcg_bit = 1, 1204 .clkr = { 1205 .enable_reg = 0x57000, 1206 .enable_mask = BIT(31), 1207 .hw.init = &(const struct clk_init_data) { 1208 .name = "ne_gcc_qupv3_wrap2_s_ahb_clk", 1209 .ops = &clk_branch2_ops, 1210 }, 1211 }, 1212 }; 1213 1214 static struct clk_branch ne_gcc_sdcc4_apps_clk = { 1215 .halt_reg = 0x18004, 1216 .halt_check = BRANCH_HALT, 1217 .clkr = { 1218 .enable_reg = 0x18004, 1219 .enable_mask = BIT(0), 1220 .hw.init = &(const struct clk_init_data) { 1221 .name = "ne_gcc_sdcc4_apps_clk", 1222 .parent_hws = (const struct clk_hw*[]) { 1223 &ne_gcc_sdcc4_apps_clk_src.clkr.hw, 1224 }, 1225 .num_parents = 1, 1226 .flags = CLK_SET_RATE_PARENT, 1227 .ops = &clk_branch2_ops, 1228 }, 1229 }, 1230 }; 1231 1232 static struct clk_branch ne_gcc_sdcc4_axi_clk = { 1233 .halt_reg = 0x18014, 1234 .halt_check = BRANCH_HALT, 1235 .clkr = { 1236 .enable_reg = 0x18014, 1237 .enable_mask = BIT(0), 1238 .hw.init = &(const struct clk_init_data) { 1239 .name = "ne_gcc_sdcc4_axi_clk", 1240 .ops = &clk_branch2_ops, 1241 }, 1242 }, 1243 }; 1244 1245 static struct clk_branch ne_gcc_ufs_phy_ahb_clk = { 1246 .halt_reg = 0x33028, 1247 .halt_check = BRANCH_HALT_VOTED, 1248 .hwcg_reg = 0x33028, 1249 .hwcg_bit = 1, 1250 .clkr = { 1251 .enable_reg = 0x33028, 1252 .enable_mask = BIT(0), 1253 .hw.init = &(const struct clk_init_data) { 1254 .name = "ne_gcc_ufs_phy_ahb_clk", 1255 .ops = &clk_branch2_ops, 1256 }, 1257 }, 1258 }; 1259 1260 static struct clk_branch ne_gcc_ufs_phy_axi_clk = { 1261 .halt_reg = 0x33018, 1262 .halt_check = BRANCH_HALT_VOTED, 1263 .hwcg_reg = 0x33018, 1264 .hwcg_bit = 1, 1265 .clkr = { 1266 .enable_reg = 0x33018, 1267 .enable_mask = BIT(0), 1268 .hw.init = &(const struct clk_init_data) { 1269 .name = "ne_gcc_ufs_phy_axi_clk", 1270 .parent_hws = (const struct clk_hw*[]) { 1271 &ne_gcc_ufs_phy_axi_clk_src.clkr.hw, 1272 }, 1273 .num_parents = 1, 1274 .flags = CLK_SET_RATE_PARENT, 1275 .ops = &clk_branch2_ops, 1276 }, 1277 }, 1278 }; 1279 1280 static struct clk_branch ne_gcc_ufs_phy_ice_core_clk = { 1281 .halt_reg = 0x3307c, 1282 .halt_check = BRANCH_HALT_VOTED, 1283 .hwcg_reg = 0x3307c, 1284 .hwcg_bit = 1, 1285 .clkr = { 1286 .enable_reg = 0x3307c, 1287 .enable_mask = BIT(0), 1288 .hw.init = &(const struct clk_init_data) { 1289 .name = "ne_gcc_ufs_phy_ice_core_clk", 1290 .parent_hws = (const struct clk_hw*[]) { 1291 &ne_gcc_ufs_phy_ice_core_clk_src.clkr.hw, 1292 }, 1293 .num_parents = 1, 1294 .flags = CLK_SET_RATE_PARENT, 1295 .ops = &clk_branch2_ops, 1296 }, 1297 }, 1298 }; 1299 1300 static struct clk_branch ne_gcc_ufs_phy_phy_aux_clk = { 1301 .halt_reg = 0x330bc, 1302 .halt_check = BRANCH_HALT_VOTED, 1303 .hwcg_reg = 0x330bc, 1304 .hwcg_bit = 1, 1305 .clkr = { 1306 .enable_reg = 0x330bc, 1307 .enable_mask = BIT(0), 1308 .hw.init = &(const struct clk_init_data) { 1309 .name = "ne_gcc_ufs_phy_phy_aux_clk", 1310 .parent_hws = (const struct clk_hw*[]) { 1311 &ne_gcc_ufs_phy_phy_aux_clk_src.clkr.hw, 1312 }, 1313 .num_parents = 1, 1314 .flags = CLK_SET_RATE_PARENT, 1315 .ops = &clk_branch2_ops, 1316 }, 1317 }, 1318 }; 1319 1320 static struct clk_branch ne_gcc_ufs_phy_rx_symbol_0_clk = { 1321 .halt_reg = 0x33030, 1322 .halt_check = BRANCH_HALT_DELAY, 1323 .clkr = { 1324 .enable_reg = 0x33030, 1325 .enable_mask = BIT(0), 1326 .hw.init = &(const struct clk_init_data) { 1327 .name = "ne_gcc_ufs_phy_rx_symbol_0_clk", 1328 .parent_hws = (const struct clk_hw*[]) { 1329 &ne_gcc_ufs_phy_rx_symbol_0_clk_src.clkr.hw, 1330 }, 1331 .num_parents = 1, 1332 .flags = CLK_SET_RATE_PARENT, 1333 .ops = &clk_branch2_ops, 1334 }, 1335 }, 1336 }; 1337 1338 static struct clk_branch ne_gcc_ufs_phy_rx_symbol_1_clk = { 1339 .halt_reg = 0x330d8, 1340 .halt_check = BRANCH_HALT_DELAY, 1341 .clkr = { 1342 .enable_reg = 0x330d8, 1343 .enable_mask = BIT(0), 1344 .hw.init = &(const struct clk_init_data) { 1345 .name = "ne_gcc_ufs_phy_rx_symbol_1_clk", 1346 .parent_hws = (const struct clk_hw*[]) { 1347 &ne_gcc_ufs_phy_rx_symbol_1_clk_src.clkr.hw, 1348 }, 1349 .num_parents = 1, 1350 .flags = CLK_SET_RATE_PARENT, 1351 .ops = &clk_branch2_ops, 1352 }, 1353 }, 1354 }; 1355 1356 static struct clk_branch ne_gcc_ufs_phy_tx_symbol_0_clk = { 1357 .halt_reg = 0x3302c, 1358 .halt_check = BRANCH_HALT_DELAY, 1359 .clkr = { 1360 .enable_reg = 0x3302c, 1361 .enable_mask = BIT(0), 1362 .hw.init = &(const struct clk_init_data) { 1363 .name = "ne_gcc_ufs_phy_tx_symbol_0_clk", 1364 .parent_hws = (const struct clk_hw*[]) { 1365 &ne_gcc_ufs_phy_tx_symbol_0_clk_src.clkr.hw, 1366 }, 1367 .num_parents = 1, 1368 .flags = CLK_SET_RATE_PARENT, 1369 .ops = &clk_branch2_ops, 1370 }, 1371 }, 1372 }; 1373 1374 static struct clk_branch ne_gcc_ufs_phy_unipro_core_clk = { 1375 .halt_reg = 0x3306c, 1376 .halt_check = BRANCH_HALT_VOTED, 1377 .hwcg_reg = 0x3306c, 1378 .hwcg_bit = 1, 1379 .clkr = { 1380 .enable_reg = 0x3306c, 1381 .enable_mask = BIT(0), 1382 .hw.init = &(const struct clk_init_data) { 1383 .name = "ne_gcc_ufs_phy_unipro_core_clk", 1384 .parent_hws = (const struct clk_hw*[]) { 1385 &ne_gcc_ufs_phy_unipro_core_clk_src.clkr.hw, 1386 }, 1387 .num_parents = 1, 1388 .flags = CLK_SET_RATE_PARENT, 1389 .ops = &clk_branch2_ops, 1390 }, 1391 }, 1392 }; 1393 1394 static struct clk_branch ne_gcc_usb20_master_clk = { 1395 .halt_reg = 0x31018, 1396 .halt_check = BRANCH_HALT, 1397 .clkr = { 1398 .enable_reg = 0x31018, 1399 .enable_mask = BIT(0), 1400 .hw.init = &(const struct clk_init_data) { 1401 .name = "ne_gcc_usb20_master_clk", 1402 .parent_hws = (const struct clk_hw*[]) { 1403 &ne_gcc_usb20_master_clk_src.clkr.hw, 1404 }, 1405 .num_parents = 1, 1406 .flags = CLK_SET_RATE_PARENT, 1407 .ops = &clk_branch2_ops, 1408 }, 1409 }, 1410 }; 1411 1412 static struct clk_branch ne_gcc_usb20_mock_utmi_clk = { 1413 .halt_reg = 0x3102c, 1414 .halt_check = BRANCH_HALT, 1415 .clkr = { 1416 .enable_reg = 0x3102c, 1417 .enable_mask = BIT(0), 1418 .hw.init = &(const struct clk_init_data) { 1419 .name = "ne_gcc_usb20_mock_utmi_clk", 1420 .parent_hws = (const struct clk_hw*[]) { 1421 &ne_gcc_usb20_mock_utmi_postdiv_clk_src.clkr.hw, 1422 }, 1423 .num_parents = 1, 1424 .flags = CLK_SET_RATE_PARENT, 1425 .ops = &clk_branch2_ops, 1426 }, 1427 }, 1428 }; 1429 1430 static struct clk_branch ne_gcc_usb20_sleep_clk = { 1431 .halt_reg = 0x31028, 1432 .halt_check = BRANCH_HALT, 1433 .clkr = { 1434 .enable_reg = 0x31028, 1435 .enable_mask = BIT(0), 1436 .hw.init = &(const struct clk_init_data) { 1437 .name = "ne_gcc_usb20_sleep_clk", 1438 .ops = &clk_branch2_ops, 1439 }, 1440 }, 1441 }; 1442 1443 static struct clk_branch ne_gcc_usb31_prim_atb_clk = { 1444 .halt_reg = 0x2a018, 1445 .halt_check = BRANCH_HALT_VOTED, 1446 .clkr = { 1447 .enable_reg = 0x2a018, 1448 .enable_mask = BIT(0), 1449 .hw.init = &(const struct clk_init_data) { 1450 .name = "ne_gcc_usb31_prim_atb_clk", 1451 .parent_hws = (const struct clk_hw*[]) { 1452 &ne_gcc_usb31_prim_master_clk_src.clkr.hw, 1453 }, 1454 .num_parents = 1, 1455 .flags = CLK_SET_RATE_PARENT, 1456 .ops = &clk_branch2_ops, 1457 }, 1458 }, 1459 }; 1460 1461 static struct clk_branch ne_gcc_usb31_prim_eud_ahb_clk = { 1462 .halt_reg = 0x2a02c, 1463 .halt_check = BRANCH_HALT_VOTED, 1464 .hwcg_reg = 0x2a02c, 1465 .hwcg_bit = 1, 1466 .clkr = { 1467 .enable_reg = 0x2a02c, 1468 .enable_mask = BIT(0), 1469 .hw.init = &(const struct clk_init_data) { 1470 .name = "ne_gcc_usb31_prim_eud_ahb_clk", 1471 .ops = &clk_branch2_ops, 1472 }, 1473 }, 1474 }; 1475 1476 static struct clk_branch ne_gcc_usb31_prim_master_clk = { 1477 .halt_reg = 0x2a01c, 1478 .halt_check = BRANCH_HALT, 1479 .clkr = { 1480 .enable_reg = 0x2a01c, 1481 .enable_mask = BIT(0), 1482 .hw.init = &(const struct clk_init_data) { 1483 .name = "ne_gcc_usb31_prim_master_clk", 1484 .parent_hws = (const struct clk_hw*[]) { 1485 &ne_gcc_usb31_prim_master_clk_src.clkr.hw, 1486 }, 1487 .num_parents = 1, 1488 .flags = CLK_SET_RATE_PARENT, 1489 .ops = &clk_branch2_ops, 1490 }, 1491 }, 1492 }; 1493 1494 static struct clk_branch ne_gcc_usb31_prim_mock_utmi_clk = { 1495 .halt_reg = 0x2a034, 1496 .halt_check = BRANCH_HALT, 1497 .clkr = { 1498 .enable_reg = 0x2a034, 1499 .enable_mask = BIT(0), 1500 .hw.init = &(const struct clk_init_data) { 1501 .name = "ne_gcc_usb31_prim_mock_utmi_clk", 1502 .parent_hws = (const struct clk_hw*[]) { 1503 &ne_gcc_usb31_prim_mock_utmi_postdiv_clk_src.clkr.hw, 1504 }, 1505 .num_parents = 1, 1506 .flags = CLK_SET_RATE_PARENT, 1507 .ops = &clk_branch2_ops, 1508 }, 1509 }, 1510 }; 1511 1512 static struct clk_branch ne_gcc_usb31_prim_sleep_clk = { 1513 .halt_reg = 0x2a030, 1514 .halt_check = BRANCH_HALT, 1515 .clkr = { 1516 .enable_reg = 0x2a030, 1517 .enable_mask = BIT(0), 1518 .hw.init = &(const struct clk_init_data) { 1519 .name = "ne_gcc_usb31_prim_sleep_clk", 1520 .ops = &clk_branch2_ops, 1521 }, 1522 }, 1523 }; 1524 1525 static struct clk_branch ne_gcc_usb31_sec_atb_clk = { 1526 .halt_reg = 0x2c018, 1527 .halt_check = BRANCH_HALT_VOTED, 1528 .clkr = { 1529 .enable_reg = 0x2c018, 1530 .enable_mask = BIT(0), 1531 .hw.init = &(const struct clk_init_data) { 1532 .name = "ne_gcc_usb31_sec_atb_clk", 1533 .parent_hws = (const struct clk_hw*[]) { 1534 &ne_gcc_usb31_prim_master_clk_src.clkr.hw, 1535 }, 1536 .num_parents = 1, 1537 .flags = CLK_SET_RATE_PARENT, 1538 .ops = &clk_branch2_ops, 1539 }, 1540 }, 1541 }; 1542 1543 static struct clk_branch ne_gcc_usb31_sec_eud_ahb_clk = { 1544 .halt_reg = 0x2c02c, 1545 .halt_check = BRANCH_HALT_VOTED, 1546 .hwcg_reg = 0x2c02c, 1547 .hwcg_bit = 1, 1548 .clkr = { 1549 .enable_reg = 0x2c02c, 1550 .enable_mask = BIT(0), 1551 .hw.init = &(const struct clk_init_data) { 1552 .name = "ne_gcc_usb31_sec_eud_ahb_clk", 1553 .ops = &clk_branch2_ops, 1554 }, 1555 }, 1556 }; 1557 1558 static struct clk_branch ne_gcc_usb31_sec_master_clk = { 1559 .halt_reg = 0x2c01c, 1560 .halt_check = BRANCH_HALT, 1561 .clkr = { 1562 .enable_reg = 0x2c01c, 1563 .enable_mask = BIT(0), 1564 .hw.init = &(const struct clk_init_data) { 1565 .name = "ne_gcc_usb31_sec_master_clk", 1566 .parent_hws = (const struct clk_hw*[]) { 1567 &ne_gcc_usb31_sec_master_clk_src.clkr.hw, 1568 }, 1569 .num_parents = 1, 1570 .flags = CLK_SET_RATE_PARENT, 1571 .ops = &clk_branch2_ops, 1572 }, 1573 }, 1574 }; 1575 1576 static struct clk_branch ne_gcc_usb31_sec_mock_utmi_clk = { 1577 .halt_reg = 0x2c034, 1578 .halt_check = BRANCH_HALT, 1579 .clkr = { 1580 .enable_reg = 0x2c034, 1581 .enable_mask = BIT(0), 1582 .hw.init = &(const struct clk_init_data) { 1583 .name = "ne_gcc_usb31_sec_mock_utmi_clk", 1584 .parent_hws = (const struct clk_hw*[]) { 1585 &ne_gcc_usb31_sec_mock_utmi_postdiv_clk_src.clkr.hw, 1586 }, 1587 .num_parents = 1, 1588 .flags = CLK_SET_RATE_PARENT, 1589 .ops = &clk_branch2_ops, 1590 }, 1591 }, 1592 }; 1593 1594 static struct clk_branch ne_gcc_usb31_sec_sleep_clk = { 1595 .halt_reg = 0x2c030, 1596 .halt_check = BRANCH_HALT, 1597 .clkr = { 1598 .enable_reg = 0x2c030, 1599 .enable_mask = BIT(0), 1600 .hw.init = &(const struct clk_init_data) { 1601 .name = "ne_gcc_usb31_sec_sleep_clk", 1602 .ops = &clk_branch2_ops, 1603 }, 1604 }, 1605 }; 1606 1607 static struct clk_branch ne_gcc_usb3_prim_phy_aux_clk = { 1608 .halt_reg = 0x2a06c, 1609 .halt_check = BRANCH_HALT, 1610 .clkr = { 1611 .enable_reg = 0x2a06c, 1612 .enable_mask = BIT(0), 1613 .hw.init = &(const struct clk_init_data) { 1614 .name = "ne_gcc_usb3_prim_phy_aux_clk", 1615 .parent_hws = (const struct clk_hw*[]) { 1616 &ne_gcc_usb3_prim_phy_aux_clk_src.clkr.hw, 1617 }, 1618 .num_parents = 1, 1619 .flags = CLK_SET_RATE_PARENT, 1620 .ops = &clk_branch2_ops, 1621 }, 1622 }, 1623 }; 1624 1625 static struct clk_branch ne_gcc_usb3_prim_phy_com_aux_clk = { 1626 .halt_reg = 0x2a070, 1627 .halt_check = BRANCH_HALT, 1628 .clkr = { 1629 .enable_reg = 0x2a070, 1630 .enable_mask = BIT(0), 1631 .hw.init = &(const struct clk_init_data) { 1632 .name = "ne_gcc_usb3_prim_phy_com_aux_clk", 1633 .parent_hws = (const struct clk_hw*[]) { 1634 &ne_gcc_usb3_prim_phy_aux_clk_src.clkr.hw, 1635 }, 1636 .num_parents = 1, 1637 .flags = CLK_SET_RATE_PARENT, 1638 .ops = &clk_branch2_ops, 1639 }, 1640 }, 1641 }; 1642 1643 static struct clk_branch ne_gcc_usb3_prim_phy_pipe_clk = { 1644 .halt_reg = 0x2a074, 1645 .halt_check = BRANCH_HALT_VOTED, 1646 .hwcg_reg = 0x2a074, 1647 .hwcg_bit = 1, 1648 .clkr = { 1649 .enable_reg = 0x2a074, 1650 .enable_mask = BIT(0), 1651 .hw.init = &(const struct clk_init_data) { 1652 .name = "ne_gcc_usb3_prim_phy_pipe_clk", 1653 .parent_hws = (const struct clk_hw*[]) { 1654 &ne_gcc_usb3_prim_phy_pipe_clk_src.clkr.hw, 1655 }, 1656 .num_parents = 1, 1657 .flags = CLK_SET_RATE_PARENT, 1658 .ops = &clk_branch2_ops, 1659 }, 1660 }, 1661 }; 1662 1663 static struct clk_branch ne_gcc_usb3_sec_phy_aux_clk = { 1664 .halt_reg = 0x2c06c, 1665 .halt_check = BRANCH_HALT, 1666 .clkr = { 1667 .enable_reg = 0x2c06c, 1668 .enable_mask = BIT(0), 1669 .hw.init = &(const struct clk_init_data) { 1670 .name = "ne_gcc_usb3_sec_phy_aux_clk", 1671 .parent_hws = (const struct clk_hw*[]) { 1672 &ne_gcc_usb3_sec_phy_aux_clk_src.clkr.hw, 1673 }, 1674 .num_parents = 1, 1675 .flags = CLK_SET_RATE_PARENT, 1676 .ops = &clk_branch2_ops, 1677 }, 1678 }, 1679 }; 1680 1681 static struct clk_branch ne_gcc_usb3_sec_phy_com_aux_clk = { 1682 .halt_reg = 0x2c070, 1683 .halt_check = BRANCH_HALT, 1684 .clkr = { 1685 .enable_reg = 0x2c070, 1686 .enable_mask = BIT(0), 1687 .hw.init = &(const struct clk_init_data) { 1688 .name = "ne_gcc_usb3_sec_phy_com_aux_clk", 1689 .parent_hws = (const struct clk_hw*[]) { 1690 &ne_gcc_usb3_sec_phy_aux_clk_src.clkr.hw, 1691 }, 1692 .num_parents = 1, 1693 .flags = CLK_SET_RATE_PARENT, 1694 .ops = &clk_branch2_ops, 1695 }, 1696 }, 1697 }; 1698 1699 static struct clk_branch ne_gcc_usb3_sec_phy_pipe_clk = { 1700 .halt_reg = 0x2c074, 1701 .halt_check = BRANCH_HALT_VOTED, 1702 .hwcg_reg = 0x2c074, 1703 .hwcg_bit = 1, 1704 .clkr = { 1705 .enable_reg = 0x2c074, 1706 .enable_mask = BIT(0), 1707 .hw.init = &(const struct clk_init_data) { 1708 .name = "ne_gcc_usb3_sec_phy_pipe_clk", 1709 .parent_hws = (const struct clk_hw*[]) { 1710 &ne_gcc_usb3_sec_phy_pipe_clk_src.clkr.hw, 1711 }, 1712 .num_parents = 1, 1713 .flags = CLK_SET_RATE_PARENT, 1714 .ops = &clk_branch2_ops, 1715 }, 1716 }, 1717 }; 1718 1719 static struct gdsc ne_gcc_ufs_mem_phy_gdsc = { 1720 .gdscr = 0x32000, 1721 .en_rest_wait_val = 0x2, 1722 .en_few_wait_val = 0x2, 1723 .clk_dis_wait_val = 0x2, 1724 .pd = { 1725 .name = "ne_gcc_ufs_mem_phy_gdsc", 1726 }, 1727 .pwrsts = PWRSTS_OFF_ON, 1728 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 1729 }; 1730 1731 static struct gdsc ne_gcc_ufs_phy_gdsc = { 1732 .gdscr = 0x33004, 1733 .en_rest_wait_val = 0x2, 1734 .en_few_wait_val = 0x2, 1735 .clk_dis_wait_val = 0xf, 1736 .pd = { 1737 .name = "ne_gcc_ufs_phy_gdsc", 1738 }, 1739 .pwrsts = PWRSTS_OFF_ON, 1740 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 1741 }; 1742 1743 static struct gdsc ne_gcc_usb20_prim_gdsc = { 1744 .gdscr = 0x31004, 1745 .en_rest_wait_val = 0x2, 1746 .en_few_wait_val = 0x2, 1747 .clk_dis_wait_val = 0xf, 1748 .pd = { 1749 .name = "ne_gcc_usb20_prim_gdsc", 1750 }, 1751 .pwrsts = PWRSTS_OFF_ON, 1752 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 1753 }; 1754 1755 static struct gdsc ne_gcc_usb31_prim_gdsc = { 1756 .gdscr = 0x2a004, 1757 .en_rest_wait_val = 0x2, 1758 .en_few_wait_val = 0x2, 1759 .clk_dis_wait_val = 0xf, 1760 .pd = { 1761 .name = "ne_gcc_usb31_prim_gdsc", 1762 }, 1763 .pwrsts = PWRSTS_OFF_ON, 1764 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 1765 }; 1766 1767 static struct gdsc ne_gcc_usb31_sec_gdsc = { 1768 .gdscr = 0x2c004, 1769 .en_rest_wait_val = 0x2, 1770 .en_few_wait_val = 0x2, 1771 .clk_dis_wait_val = 0xf, 1772 .pd = { 1773 .name = "ne_gcc_usb31_sec_gdsc", 1774 }, 1775 .pwrsts = PWRSTS_OFF_ON, 1776 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 1777 }; 1778 1779 static struct gdsc ne_gcc_usb3_phy_gdsc = { 1780 .gdscr = 0x2b00c, 1781 .en_rest_wait_val = 0x2, 1782 .en_few_wait_val = 0x2, 1783 .clk_dis_wait_val = 0x2, 1784 .pd = { 1785 .name = "ne_gcc_usb3_phy_gdsc", 1786 }, 1787 .pwrsts = PWRSTS_OFF_ON, 1788 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 1789 }; 1790 1791 static struct gdsc ne_gcc_usb3_sec_phy_gdsc = { 1792 .gdscr = 0x2d00c, 1793 .en_rest_wait_val = 0x2, 1794 .en_few_wait_val = 0x2, 1795 .clk_dis_wait_val = 0x2, 1796 .pd = { 1797 .name = "ne_gcc_usb3_sec_phy_gdsc", 1798 }, 1799 .pwrsts = PWRSTS_OFF_ON, 1800 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 1801 }; 1802 1803 static struct clk_regmap *ne_gcc_nord_clocks[] = { 1804 [NE_GCC_AGGRE_NOC_UFS_PHY_AXI_CLK] = &ne_gcc_aggre_noc_ufs_phy_axi_clk.clkr, 1805 [NE_GCC_AGGRE_NOC_USB2_AXI_CLK] = &ne_gcc_aggre_noc_usb2_axi_clk.clkr, 1806 [NE_GCC_AGGRE_NOC_USB3_PRIM_AXI_CLK] = &ne_gcc_aggre_noc_usb3_prim_axi_clk.clkr, 1807 [NE_GCC_AGGRE_NOC_USB3_SEC_AXI_CLK] = &ne_gcc_aggre_noc_usb3_sec_axi_clk.clkr, 1808 [NE_GCC_AHB2PHY_CLK] = &ne_gcc_ahb2phy_clk.clkr, 1809 [NE_GCC_CNOC_USB2_AXI_CLK] = &ne_gcc_cnoc_usb2_axi_clk.clkr, 1810 [NE_GCC_CNOC_USB3_PRIM_AXI_CLK] = &ne_gcc_cnoc_usb3_prim_axi_clk.clkr, 1811 [NE_GCC_CNOC_USB3_SEC_AXI_CLK] = &ne_gcc_cnoc_usb3_sec_axi_clk.clkr, 1812 [NE_GCC_FRQ_MEASURE_REF_CLK] = &ne_gcc_frq_measure_ref_clk.clkr, 1813 [NE_GCC_GP1_CLK] = &ne_gcc_gp1_clk.clkr, 1814 [NE_GCC_GP1_CLK_SRC] = &ne_gcc_gp1_clk_src.clkr, 1815 [NE_GCC_GP2_CLK] = &ne_gcc_gp2_clk.clkr, 1816 [NE_GCC_GP2_CLK_SRC] = &ne_gcc_gp2_clk_src.clkr, 1817 [NE_GCC_GPLL0] = &ne_gcc_gpll0.clkr, 1818 [NE_GCC_GPLL0_OUT_EVEN] = &ne_gcc_gpll0_out_even.clkr, 1819 [NE_GCC_GPLL2] = &ne_gcc_gpll2.clkr, 1820 [NE_GCC_GPU_2_CFG_CLK] = &ne_gcc_gpu_2_cfg_clk.clkr, 1821 [NE_GCC_GPU_2_GPLL0_CLK_SRC] = &ne_gcc_gpu_2_gpll0_clk_src.clkr, 1822 [NE_GCC_GPU_2_GPLL0_DIV_CLK_SRC] = &ne_gcc_gpu_2_gpll0_div_clk_src.clkr, 1823 [NE_GCC_GPU_2_HSCNOC_GFX_CLK] = &ne_gcc_gpu_2_hscnoc_gfx_clk.clkr, 1824 [NE_GCC_GPU_2_SMMU_VOTE_CLK] = &ne_gcc_gpu_2_smmu_vote_clk.clkr, 1825 [NE_GCC_QUPV3_WRAP2_CORE_2X_CLK] = &ne_gcc_qupv3_wrap2_core_2x_clk.clkr, 1826 [NE_GCC_QUPV3_WRAP2_CORE_CLK] = &ne_gcc_qupv3_wrap2_core_clk.clkr, 1827 [NE_GCC_QUPV3_WRAP2_M_AHB_CLK] = &ne_gcc_qupv3_wrap2_m_ahb_clk.clkr, 1828 [NE_GCC_QUPV3_WRAP2_S0_CLK] = &ne_gcc_qupv3_wrap2_s0_clk.clkr, 1829 [NE_GCC_QUPV3_WRAP2_S0_CLK_SRC] = &ne_gcc_qupv3_wrap2_s0_clk_src.clkr, 1830 [NE_GCC_QUPV3_WRAP2_S1_CLK] = &ne_gcc_qupv3_wrap2_s1_clk.clkr, 1831 [NE_GCC_QUPV3_WRAP2_S1_CLK_SRC] = &ne_gcc_qupv3_wrap2_s1_clk_src.clkr, 1832 [NE_GCC_QUPV3_WRAP2_S2_CLK] = &ne_gcc_qupv3_wrap2_s2_clk.clkr, 1833 [NE_GCC_QUPV3_WRAP2_S2_CLK_SRC] = &ne_gcc_qupv3_wrap2_s2_clk_src.clkr, 1834 [NE_GCC_QUPV3_WRAP2_S3_CLK] = &ne_gcc_qupv3_wrap2_s3_clk.clkr, 1835 [NE_GCC_QUPV3_WRAP2_S3_CLK_SRC] = &ne_gcc_qupv3_wrap2_s3_clk_src.clkr, 1836 [NE_GCC_QUPV3_WRAP2_S4_CLK] = &ne_gcc_qupv3_wrap2_s4_clk.clkr, 1837 [NE_GCC_QUPV3_WRAP2_S4_CLK_SRC] = &ne_gcc_qupv3_wrap2_s4_clk_src.clkr, 1838 [NE_GCC_QUPV3_WRAP2_S5_CLK] = &ne_gcc_qupv3_wrap2_s5_clk.clkr, 1839 [NE_GCC_QUPV3_WRAP2_S5_CLK_SRC] = &ne_gcc_qupv3_wrap2_s5_clk_src.clkr, 1840 [NE_GCC_QUPV3_WRAP2_S6_CLK] = &ne_gcc_qupv3_wrap2_s6_clk.clkr, 1841 [NE_GCC_QUPV3_WRAP2_S6_CLK_SRC] = &ne_gcc_qupv3_wrap2_s6_clk_src.clkr, 1842 [NE_GCC_QUPV3_WRAP2_S_AHB_CLK] = &ne_gcc_qupv3_wrap2_s_ahb_clk.clkr, 1843 [NE_GCC_SDCC4_APPS_CLK] = &ne_gcc_sdcc4_apps_clk.clkr, 1844 [NE_GCC_SDCC4_APPS_CLK_SRC] = &ne_gcc_sdcc4_apps_clk_src.clkr, 1845 [NE_GCC_SDCC4_AXI_CLK] = &ne_gcc_sdcc4_axi_clk.clkr, 1846 [NE_GCC_UFS_PHY_AHB_CLK] = &ne_gcc_ufs_phy_ahb_clk.clkr, 1847 [NE_GCC_UFS_PHY_AXI_CLK] = &ne_gcc_ufs_phy_axi_clk.clkr, 1848 [NE_GCC_UFS_PHY_AXI_CLK_SRC] = &ne_gcc_ufs_phy_axi_clk_src.clkr, 1849 [NE_GCC_UFS_PHY_ICE_CORE_CLK] = &ne_gcc_ufs_phy_ice_core_clk.clkr, 1850 [NE_GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &ne_gcc_ufs_phy_ice_core_clk_src.clkr, 1851 [NE_GCC_UFS_PHY_PHY_AUX_CLK] = &ne_gcc_ufs_phy_phy_aux_clk.clkr, 1852 [NE_GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &ne_gcc_ufs_phy_phy_aux_clk_src.clkr, 1853 [NE_GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &ne_gcc_ufs_phy_rx_symbol_0_clk.clkr, 1854 [NE_GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC] = &ne_gcc_ufs_phy_rx_symbol_0_clk_src.clkr, 1855 [NE_GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &ne_gcc_ufs_phy_rx_symbol_1_clk.clkr, 1856 [NE_GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC] = &ne_gcc_ufs_phy_rx_symbol_1_clk_src.clkr, 1857 [NE_GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &ne_gcc_ufs_phy_tx_symbol_0_clk.clkr, 1858 [NE_GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC] = &ne_gcc_ufs_phy_tx_symbol_0_clk_src.clkr, 1859 [NE_GCC_UFS_PHY_UNIPRO_CORE_CLK] = &ne_gcc_ufs_phy_unipro_core_clk.clkr, 1860 [NE_GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] = &ne_gcc_ufs_phy_unipro_core_clk_src.clkr, 1861 [NE_GCC_USB20_MASTER_CLK] = &ne_gcc_usb20_master_clk.clkr, 1862 [NE_GCC_USB20_MASTER_CLK_SRC] = &ne_gcc_usb20_master_clk_src.clkr, 1863 [NE_GCC_USB20_MOCK_UTMI_CLK] = &ne_gcc_usb20_mock_utmi_clk.clkr, 1864 [NE_GCC_USB20_MOCK_UTMI_CLK_SRC] = &ne_gcc_usb20_mock_utmi_clk_src.clkr, 1865 [NE_GCC_USB20_MOCK_UTMI_POSTDIV_CLK_SRC] = &ne_gcc_usb20_mock_utmi_postdiv_clk_src.clkr, 1866 [NE_GCC_USB20_SLEEP_CLK] = &ne_gcc_usb20_sleep_clk.clkr, 1867 [NE_GCC_USB31_PRIM_ATB_CLK] = &ne_gcc_usb31_prim_atb_clk.clkr, 1868 [NE_GCC_USB31_PRIM_EUD_AHB_CLK] = &ne_gcc_usb31_prim_eud_ahb_clk.clkr, 1869 [NE_GCC_USB31_PRIM_MASTER_CLK] = &ne_gcc_usb31_prim_master_clk.clkr, 1870 [NE_GCC_USB31_PRIM_MASTER_CLK_SRC] = &ne_gcc_usb31_prim_master_clk_src.clkr, 1871 [NE_GCC_USB31_PRIM_MOCK_UTMI_CLK] = &ne_gcc_usb31_prim_mock_utmi_clk.clkr, 1872 [NE_GCC_USB31_PRIM_MOCK_UTMI_CLK_SRC] = &ne_gcc_usb31_prim_mock_utmi_clk_src.clkr, 1873 [NE_GCC_USB31_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC] = 1874 &ne_gcc_usb31_prim_mock_utmi_postdiv_clk_src.clkr, 1875 [NE_GCC_USB31_PRIM_SLEEP_CLK] = &ne_gcc_usb31_prim_sleep_clk.clkr, 1876 [NE_GCC_USB31_SEC_ATB_CLK] = &ne_gcc_usb31_sec_atb_clk.clkr, 1877 [NE_GCC_USB31_SEC_EUD_AHB_CLK] = &ne_gcc_usb31_sec_eud_ahb_clk.clkr, 1878 [NE_GCC_USB31_SEC_MASTER_CLK] = &ne_gcc_usb31_sec_master_clk.clkr, 1879 [NE_GCC_USB31_SEC_MASTER_CLK_SRC] = &ne_gcc_usb31_sec_master_clk_src.clkr, 1880 [NE_GCC_USB31_SEC_MOCK_UTMI_CLK] = &ne_gcc_usb31_sec_mock_utmi_clk.clkr, 1881 [NE_GCC_USB31_SEC_MOCK_UTMI_CLK_SRC] = &ne_gcc_usb31_sec_mock_utmi_clk_src.clkr, 1882 [NE_GCC_USB31_SEC_MOCK_UTMI_POSTDIV_CLK_SRC] = 1883 &ne_gcc_usb31_sec_mock_utmi_postdiv_clk_src.clkr, 1884 [NE_GCC_USB31_SEC_SLEEP_CLK] = &ne_gcc_usb31_sec_sleep_clk.clkr, 1885 [NE_GCC_USB3_PRIM_PHY_AUX_CLK] = &ne_gcc_usb3_prim_phy_aux_clk.clkr, 1886 [NE_GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &ne_gcc_usb3_prim_phy_aux_clk_src.clkr, 1887 [NE_GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &ne_gcc_usb3_prim_phy_com_aux_clk.clkr, 1888 [NE_GCC_USB3_PRIM_PHY_PIPE_CLK] = &ne_gcc_usb3_prim_phy_pipe_clk.clkr, 1889 [NE_GCC_USB3_PRIM_PHY_PIPE_CLK_SRC] = &ne_gcc_usb3_prim_phy_pipe_clk_src.clkr, 1890 [NE_GCC_USB3_SEC_PHY_AUX_CLK] = &ne_gcc_usb3_sec_phy_aux_clk.clkr, 1891 [NE_GCC_USB3_SEC_PHY_AUX_CLK_SRC] = &ne_gcc_usb3_sec_phy_aux_clk_src.clkr, 1892 [NE_GCC_USB3_SEC_PHY_COM_AUX_CLK] = &ne_gcc_usb3_sec_phy_com_aux_clk.clkr, 1893 [NE_GCC_USB3_SEC_PHY_PIPE_CLK] = &ne_gcc_usb3_sec_phy_pipe_clk.clkr, 1894 [NE_GCC_USB3_SEC_PHY_PIPE_CLK_SRC] = &ne_gcc_usb3_sec_phy_pipe_clk_src.clkr, 1895 }; 1896 1897 static struct gdsc *ne_gcc_nord_gdscs[] = { 1898 [NE_GCC_UFS_MEM_PHY_GDSC] = &ne_gcc_ufs_mem_phy_gdsc, 1899 [NE_GCC_UFS_PHY_GDSC] = &ne_gcc_ufs_phy_gdsc, 1900 [NE_GCC_USB20_PRIM_GDSC] = &ne_gcc_usb20_prim_gdsc, 1901 [NE_GCC_USB31_PRIM_GDSC] = &ne_gcc_usb31_prim_gdsc, 1902 [NE_GCC_USB31_SEC_GDSC] = &ne_gcc_usb31_sec_gdsc, 1903 [NE_GCC_USB3_PHY_GDSC] = &ne_gcc_usb3_phy_gdsc, 1904 [NE_GCC_USB3_SEC_PHY_GDSC] = &ne_gcc_usb3_sec_phy_gdsc, 1905 }; 1906 1907 static const struct qcom_reset_map ne_gcc_nord_resets[] = { 1908 [NE_GCC_GPU_2_BCR] = { 0x34000 }, 1909 [NE_GCC_QUPV3_WRAPPER_2_BCR] = { 0x38000 }, 1910 [NE_GCC_SDCC4_BCR] = { 0x18000 }, 1911 [NE_GCC_UFS_PHY_BCR] = { 0x33000 }, 1912 [NE_GCC_USB20_PRIM_BCR] = { 0x31000 }, 1913 [NE_GCC_USB31_PRIM_BCR] = { 0x2a000 }, 1914 [NE_GCC_USB31_SEC_BCR] = { 0x2c000 }, 1915 [NE_GCC_USB3_DP_PHY_PRIM_BCR] = { 0x2b008 }, 1916 [NE_GCC_USB3_DP_PHY_SEC_BCR] = { 0x2d008 }, 1917 [NE_GCC_USB3_PHY_PRIM_BCR] = { 0x2b000 }, 1918 [NE_GCC_USB3_PHY_SEC_BCR] = { 0x2d000 }, 1919 [NE_GCC_USB3PHY_PHY_PRIM_BCR] = { 0x2b004 }, 1920 [NE_GCC_USB3PHY_PHY_SEC_BCR] = { 0x2d004 }, 1921 }; 1922 1923 static const struct clk_rcg_dfs_data ne_gcc_nord_dfs_clocks[] = { 1924 DEFINE_RCG_DFS(ne_gcc_qupv3_wrap2_s0_clk_src), 1925 DEFINE_RCG_DFS(ne_gcc_qupv3_wrap2_s1_clk_src), 1926 DEFINE_RCG_DFS(ne_gcc_qupv3_wrap2_s2_clk_src), 1927 DEFINE_RCG_DFS(ne_gcc_qupv3_wrap2_s3_clk_src), 1928 DEFINE_RCG_DFS(ne_gcc_qupv3_wrap2_s4_clk_src), 1929 DEFINE_RCG_DFS(ne_gcc_qupv3_wrap2_s5_clk_src), 1930 DEFINE_RCG_DFS(ne_gcc_qupv3_wrap2_s6_clk_src), 1931 }; 1932 1933 static const struct regmap_config ne_gcc_nord_regmap_config = { 1934 .reg_bits = 32, 1935 .reg_stride = 4, 1936 .val_bits = 32, 1937 .max_register = 0xf41f0, 1938 .fast_io = true, 1939 }; 1940 1941 static void clk_nord_regs_configure(struct device *dev, struct regmap *regmap) 1942 { 1943 /* FORCE_MEM_CORE_ON for ne_gcc_ufs_phy_ice_core_clk and ne_gcc_ufs_phy_axi_clk */ 1944 qcom_branch_set_force_mem_core(regmap, ne_gcc_ufs_phy_ice_core_clk, true); 1945 qcom_branch_set_force_mem_core(regmap, ne_gcc_ufs_phy_axi_clk, true); 1946 } 1947 1948 static struct qcom_cc_driver_data ne_gcc_nord_driver_data = { 1949 .dfs_rcgs = ne_gcc_nord_dfs_clocks, 1950 .num_dfs_rcgs = ARRAY_SIZE(ne_gcc_nord_dfs_clocks), 1951 .clk_regs_configure = clk_nord_regs_configure, 1952 }; 1953 1954 static const struct qcom_cc_desc ne_gcc_nord_desc = { 1955 .config = &ne_gcc_nord_regmap_config, 1956 .clks = ne_gcc_nord_clocks, 1957 .num_clks = ARRAY_SIZE(ne_gcc_nord_clocks), 1958 .resets = ne_gcc_nord_resets, 1959 .num_resets = ARRAY_SIZE(ne_gcc_nord_resets), 1960 .gdscs = ne_gcc_nord_gdscs, 1961 .num_gdscs = ARRAY_SIZE(ne_gcc_nord_gdscs), 1962 .driver_data = &ne_gcc_nord_driver_data, 1963 }; 1964 1965 static const struct of_device_id ne_gcc_nord_match_table[] = { 1966 { .compatible = "qcom,nord-negcc" }, 1967 { } 1968 }; 1969 MODULE_DEVICE_TABLE(of, ne_gcc_nord_match_table); 1970 1971 static int ne_gcc_nord_probe(struct platform_device *pdev) 1972 { 1973 return qcom_cc_probe(pdev, &ne_gcc_nord_desc); 1974 } 1975 1976 static struct platform_driver ne_gcc_nord_driver = { 1977 .probe = ne_gcc_nord_probe, 1978 .driver = { 1979 .name = "negcc-nord", 1980 .of_match_table = ne_gcc_nord_match_table, 1981 }, 1982 }; 1983 1984 module_platform_driver(ne_gcc_nord_driver); 1985 1986 MODULE_DESCRIPTION("QTI NEGCC NORD Driver"); 1987 MODULE_LICENSE("GPL"); 1988