1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 4 */ 5 6 #include <linux/clk-provider.h> 7 #include <linux/module.h> 8 #include <linux/platform_device.h> 9 #include <linux/regmap.h> 10 11 #include <dt-bindings/clock/qcom,glymur-gpucc.h> 12 13 #include "clk-alpha-pll.h" 14 #include "clk-branch.h" 15 #include "clk-pll.h" 16 #include "clk-rcg.h" 17 #include "clk-regmap.h" 18 #include "clk-regmap-divider.h" 19 #include "clk-regmap-mux.h" 20 #include "common.h" 21 #include "gdsc.h" 22 #include "reset.h" 23 24 enum { 25 DT_BI_TCXO, 26 DT_GPLL0_OUT_MAIN, 27 DT_GPLL0_OUT_MAIN_DIV, 28 }; 29 30 enum { 31 P_BI_TCXO, 32 P_GPLL0_OUT_MAIN, 33 P_GPLL0_OUT_MAIN_DIV, 34 P_GPU_CC_PLL0_OUT_EVEN, 35 P_GPU_CC_PLL0_OUT_MAIN, 36 P_GPU_CC_PLL0_OUT_ODD, 37 }; 38 39 static const struct pll_vco taycan_eko_t_vco[] = { 40 { 249600000, 2500000000, 0 }, 41 }; 42 43 /* 1150.0 MHz Configuration */ 44 static const struct alpha_pll_config gpu_cc_pll0_config = { 45 .l = 0x3b, 46 .alpha = 0xe555, 47 .config_ctl_val = 0x25c400e7, 48 .config_ctl_hi_val = 0x0a8060e0, 49 .config_ctl_hi1_val = 0xf51dea20, 50 .user_ctl_val = 0x00000408, 51 .user_ctl_hi_val = 0x00000002, 52 }; 53 54 static struct clk_alpha_pll gpu_cc_pll0 = { 55 .offset = 0x0, 56 .config = &gpu_cc_pll0_config, 57 .vco_table = taycan_eko_t_vco, 58 .num_vco = ARRAY_SIZE(taycan_eko_t_vco), 59 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], 60 .clkr = { 61 .hw.init = &(const struct clk_init_data) { 62 .name = "gpu_cc_pll0", 63 .parent_data = &(const struct clk_parent_data) { 64 .index = DT_BI_TCXO, 65 }, 66 .num_parents = 1, 67 .ops = &clk_alpha_pll_taycan_eko_t_ops, 68 }, 69 }, 70 }; 71 72 static const struct clk_div_table post_div_table_gpu_cc_pll0_out_even[] = { 73 { 0x1, 2 }, 74 { } 75 }; 76 77 static struct clk_alpha_pll_postdiv gpu_cc_pll0_out_even = { 78 .offset = 0x0, 79 .post_div_shift = 10, 80 .post_div_table = post_div_table_gpu_cc_pll0_out_even, 81 .num_post_div = ARRAY_SIZE(post_div_table_gpu_cc_pll0_out_even), 82 .width = 4, 83 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], 84 .clkr.hw.init = &(const struct clk_init_data) { 85 .name = "gpu_cc_pll0_out_even", 86 .parent_hws = (const struct clk_hw*[]) { 87 &gpu_cc_pll0.clkr.hw, 88 }, 89 .num_parents = 1, 90 .flags = CLK_SET_RATE_PARENT, 91 .ops = &clk_alpha_pll_postdiv_taycan_eko_t_ops, 92 }, 93 }; 94 95 static const struct parent_map gpu_cc_parent_map_0[] = { 96 { P_BI_TCXO, 0 }, 97 { P_GPLL0_OUT_MAIN, 5 }, 98 { P_GPLL0_OUT_MAIN_DIV, 6 }, 99 }; 100 101 static const struct clk_parent_data gpu_cc_parent_data_0[] = { 102 { .index = DT_BI_TCXO }, 103 { .index = DT_GPLL0_OUT_MAIN }, 104 { .index = DT_GPLL0_OUT_MAIN_DIV }, 105 }; 106 107 static const struct parent_map gpu_cc_parent_map_1[] = { 108 { P_BI_TCXO, 0 }, 109 { P_GPU_CC_PLL0_OUT_MAIN, 1 }, 110 { P_GPU_CC_PLL0_OUT_EVEN, 2 }, 111 { P_GPU_CC_PLL0_OUT_ODD, 3 }, 112 { P_GPLL0_OUT_MAIN, 5 }, 113 { P_GPLL0_OUT_MAIN_DIV, 6 }, 114 }; 115 116 static const struct clk_parent_data gpu_cc_parent_data_1[] = { 117 { .index = DT_BI_TCXO }, 118 { .hw = &gpu_cc_pll0.clkr.hw }, 119 { .hw = &gpu_cc_pll0_out_even.clkr.hw }, 120 { .hw = &gpu_cc_pll0.clkr.hw }, 121 { .index = DT_GPLL0_OUT_MAIN }, 122 { .index = DT_GPLL0_OUT_MAIN_DIV }, 123 }; 124 125 static const struct freq_tbl ftbl_gpu_cc_ff_clk_src[] = { 126 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), 127 { } 128 }; 129 130 static struct clk_rcg2 gpu_cc_ff_clk_src = { 131 .cmd_rcgr = 0x9474, 132 .mnd_width = 0, 133 .hid_width = 5, 134 .parent_map = gpu_cc_parent_map_0, 135 .freq_tbl = ftbl_gpu_cc_ff_clk_src, 136 .clkr.hw.init = &(const struct clk_init_data) { 137 .name = "gpu_cc_ff_clk_src", 138 .parent_data = gpu_cc_parent_data_0, 139 .num_parents = ARRAY_SIZE(gpu_cc_parent_data_0), 140 .flags = CLK_SET_RATE_PARENT, 141 .ops = &clk_rcg2_shared_ops, 142 }, 143 }; 144 145 static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = { 146 F(19200000, P_BI_TCXO, 1, 0, 0), 147 F(575000000, P_GPU_CC_PLL0_OUT_EVEN, 1, 0, 0), 148 F(700000000, P_GPU_CC_PLL0_OUT_EVEN, 1, 0, 0), 149 F(725000000, P_GPU_CC_PLL0_OUT_EVEN, 1, 0, 0), 150 F(750000000, P_GPU_CC_PLL0_OUT_EVEN, 1, 0, 0), 151 { } 152 }; 153 154 static struct clk_rcg2 gpu_cc_gmu_clk_src = { 155 .cmd_rcgr = 0x9318, 156 .mnd_width = 0, 157 .hid_width = 5, 158 .parent_map = gpu_cc_parent_map_1, 159 .freq_tbl = ftbl_gpu_cc_gmu_clk_src, 160 .clkr.hw.init = &(const struct clk_init_data) { 161 .name = "gpu_cc_gmu_clk_src", 162 .parent_data = gpu_cc_parent_data_1, 163 .num_parents = ARRAY_SIZE(gpu_cc_parent_data_1), 164 .flags = CLK_SET_RATE_PARENT, 165 .ops = &clk_rcg2_shared_ops, 166 }, 167 }; 168 169 static const struct freq_tbl ftbl_gpu_cc_hub_clk_src[] = { 170 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), 171 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), 172 F(400000000, P_GPLL0_OUT_MAIN, 1.5, 0, 0), 173 { } 174 }; 175 176 static struct clk_rcg2 gpu_cc_hub_clk_src = { 177 .cmd_rcgr = 0x93f0, 178 .mnd_width = 0, 179 .hid_width = 5, 180 .parent_map = gpu_cc_parent_map_1, 181 .freq_tbl = ftbl_gpu_cc_hub_clk_src, 182 .clkr.hw.init = &(const struct clk_init_data) { 183 .name = "gpu_cc_hub_clk_src", 184 .parent_data = gpu_cc_parent_data_1, 185 .num_parents = ARRAY_SIZE(gpu_cc_parent_data_1), 186 .flags = CLK_SET_RATE_PARENT, 187 .ops = &clk_rcg2_shared_ops, 188 }, 189 }; 190 191 static struct clk_regmap_div gpu_cc_hub_div_clk_src = { 192 .reg = 0x9430, 193 .shift = 0, 194 .width = 4, 195 .clkr.hw.init = &(const struct clk_init_data) { 196 .name = "gpu_cc_hub_div_clk_src", 197 .parent_hws = (const struct clk_hw*[]) { 198 &gpu_cc_hub_clk_src.clkr.hw, 199 }, 200 .num_parents = 1, 201 .flags = CLK_SET_RATE_PARENT, 202 .ops = &clk_regmap_div_ro_ops, 203 }, 204 }; 205 206 static struct clk_branch gpu_cc_ahb_clk = { 207 .halt_reg = 0x90bc, 208 .halt_check = BRANCH_HALT_DELAY, 209 .clkr = { 210 .enable_reg = 0x90bc, 211 .enable_mask = BIT(0), 212 .hw.init = &(const struct clk_init_data) { 213 .name = "gpu_cc_ahb_clk", 214 .parent_hws = (const struct clk_hw*[]) { 215 &gpu_cc_hub_div_clk_src.clkr.hw, 216 }, 217 .num_parents = 1, 218 .flags = CLK_SET_RATE_PARENT, 219 .ops = &clk_branch2_ops, 220 }, 221 }, 222 }; 223 224 static struct clk_branch gpu_cc_cx_accu_shift_clk = { 225 .halt_reg = 0x9108, 226 .halt_check = BRANCH_HALT_VOTED, 227 .clkr = { 228 .enable_reg = 0x9108, 229 .enable_mask = BIT(0), 230 .hw.init = &(const struct clk_init_data) { 231 .name = "gpu_cc_cx_accu_shift_clk", 232 .ops = &clk_branch2_ops, 233 }, 234 }, 235 }; 236 237 static struct clk_branch gpu_cc_cx_ff_clk = { 238 .halt_reg = 0x90ec, 239 .halt_check = BRANCH_HALT, 240 .clkr = { 241 .enable_reg = 0x90ec, 242 .enable_mask = BIT(0), 243 .hw.init = &(const struct clk_init_data) { 244 .name = "gpu_cc_cx_ff_clk", 245 .parent_hws = (const struct clk_hw*[]) { 246 &gpu_cc_ff_clk_src.clkr.hw, 247 }, 248 .num_parents = 1, 249 .flags = CLK_SET_RATE_PARENT, 250 .ops = &clk_branch2_ops, 251 }, 252 }, 253 }; 254 255 static struct clk_branch gpu_cc_cx_gmu_clk = { 256 .halt_reg = 0x90d4, 257 .halt_check = BRANCH_HALT_VOTED, 258 .clkr = { 259 .enable_reg = 0x90d4, 260 .enable_mask = BIT(0), 261 .hw.init = &(const struct clk_init_data) { 262 .name = "gpu_cc_cx_gmu_clk", 263 .parent_hws = (const struct clk_hw*[]) { 264 &gpu_cc_gmu_clk_src.clkr.hw, 265 }, 266 .num_parents = 1, 267 .flags = CLK_SET_RATE_PARENT, 268 .ops = &clk_branch2_aon_ops, 269 }, 270 }, 271 }; 272 273 static struct clk_branch gpu_cc_cxo_clk = { 274 .halt_reg = 0x90e4, 275 .halt_check = BRANCH_HALT, 276 .clkr = { 277 .enable_reg = 0x90e4, 278 .enable_mask = BIT(0), 279 .hw.init = &(const struct clk_init_data) { 280 .name = "gpu_cc_cxo_clk", 281 .ops = &clk_branch2_ops, 282 }, 283 }, 284 }; 285 286 static struct clk_branch gpu_cc_demet_clk = { 287 .halt_reg = 0x9010, 288 .halt_check = BRANCH_HALT_VOTED, 289 .clkr = { 290 .enable_reg = 0x9010, 291 .enable_mask = BIT(0), 292 .hw.init = &(const struct clk_init_data) { 293 .name = "gpu_cc_demet_clk", 294 .ops = &clk_branch2_ops, 295 }, 296 }, 297 }; 298 299 static struct clk_branch gpu_cc_dpm_clk = { 300 .halt_reg = 0x910c, 301 .halt_check = BRANCH_HALT, 302 .clkr = { 303 .enable_reg = 0x910c, 304 .enable_mask = BIT(0), 305 .hw.init = &(const struct clk_init_data) { 306 .name = "gpu_cc_dpm_clk", 307 .ops = &clk_branch2_ops, 308 }, 309 }, 310 }; 311 312 static struct clk_branch gpu_cc_freq_measure_clk = { 313 .halt_reg = 0x900c, 314 .halt_check = BRANCH_HALT, 315 .clkr = { 316 .enable_reg = 0x900c, 317 .enable_mask = BIT(0), 318 .hw.init = &(const struct clk_init_data) { 319 .name = "gpu_cc_freq_measure_clk", 320 .ops = &clk_branch2_ops, 321 }, 322 }, 323 }; 324 325 static struct clk_branch gpu_cc_gpu_smmu_vote_clk = { 326 .halt_reg = 0x7000, 327 .halt_check = BRANCH_HALT_VOTED, 328 .clkr = { 329 .enable_reg = 0x7000, 330 .enable_mask = BIT(0), 331 .hw.init = &(const struct clk_init_data) { 332 .name = "gpu_cc_gpu_smmu_vote_clk", 333 .ops = &clk_branch2_ops, 334 }, 335 }, 336 }; 337 338 static struct clk_branch gpu_cc_gx_accu_shift_clk = { 339 .halt_reg = 0x9070, 340 .halt_check = BRANCH_HALT_VOTED, 341 .clkr = { 342 .enable_reg = 0x9070, 343 .enable_mask = BIT(0), 344 .hw.init = &(const struct clk_init_data) { 345 .name = "gpu_cc_gx_accu_shift_clk", 346 .ops = &clk_branch2_ops, 347 }, 348 }, 349 }; 350 351 static struct clk_branch gpu_cc_gx_acd_ahb_ff_clk = { 352 .halt_reg = 0x9068, 353 .halt_check = BRANCH_HALT, 354 .clkr = { 355 .enable_reg = 0x9068, 356 .enable_mask = BIT(0), 357 .hw.init = &(const struct clk_init_data) { 358 .name = "gpu_cc_gx_acd_ahb_ff_clk", 359 .parent_hws = (const struct clk_hw*[]) { 360 &gpu_cc_ff_clk_src.clkr.hw, 361 }, 362 .num_parents = 1, 363 .flags = CLK_SET_RATE_PARENT, 364 .ops = &clk_branch2_ops, 365 }, 366 }, 367 }; 368 369 static struct clk_branch gpu_cc_gx_ahb_ff_clk = { 370 .halt_reg = 0x9064, 371 .halt_check = BRANCH_HALT, 372 .clkr = { 373 .enable_reg = 0x9064, 374 .enable_mask = BIT(0), 375 .hw.init = &(const struct clk_init_data) { 376 .name = "gpu_cc_gx_ahb_ff_clk", 377 .parent_hws = (const struct clk_hw*[]) { 378 &gpu_cc_ff_clk_src.clkr.hw, 379 }, 380 .num_parents = 1, 381 .flags = CLK_SET_RATE_PARENT, 382 .ops = &clk_branch2_ops, 383 }, 384 }, 385 }; 386 387 static struct clk_branch gpu_cc_gx_gmu_clk = { 388 .halt_reg = 0x9060, 389 .halt_check = BRANCH_HALT, 390 .clkr = { 391 .enable_reg = 0x9060, 392 .enable_mask = BIT(0), 393 .hw.init = &(const struct clk_init_data) { 394 .name = "gpu_cc_gx_gmu_clk", 395 .parent_hws = (const struct clk_hw*[]) { 396 &gpu_cc_gmu_clk_src.clkr.hw, 397 }, 398 .num_parents = 1, 399 .flags = CLK_SET_RATE_PARENT, 400 .ops = &clk_branch2_ops, 401 }, 402 }, 403 }; 404 405 static struct clk_branch gpu_cc_gx_rcg_ahb_ff_clk = { 406 .halt_reg = 0x906c, 407 .halt_check = BRANCH_HALT_VOTED, 408 .clkr = { 409 .enable_reg = 0x906c, 410 .enable_mask = BIT(0), 411 .hw.init = &(const struct clk_init_data) { 412 .name = "gpu_cc_gx_rcg_ahb_ff_clk", 413 .parent_hws = (const struct clk_hw*[]) { 414 &gpu_cc_ff_clk_src.clkr.hw, 415 }, 416 .num_parents = 1, 417 .flags = CLK_SET_RATE_PARENT, 418 .ops = &clk_branch2_ops, 419 }, 420 }, 421 }; 422 423 static struct clk_branch gpu_cc_hub_aon_clk = { 424 .halt_reg = 0x93ec, 425 .halt_check = BRANCH_HALT_VOTED, 426 .clkr = { 427 .enable_reg = 0x93ec, 428 .enable_mask = BIT(0), 429 .hw.init = &(const struct clk_init_data) { 430 .name = "gpu_cc_hub_aon_clk", 431 .parent_hws = (const struct clk_hw*[]) { 432 &gpu_cc_hub_clk_src.clkr.hw, 433 }, 434 .num_parents = 1, 435 .flags = CLK_SET_RATE_PARENT, 436 .ops = &clk_branch2_aon_ops, 437 }, 438 }, 439 }; 440 441 static struct clk_branch gpu_cc_hub_cx_int_clk = { 442 .halt_reg = 0x90e8, 443 .halt_check = BRANCH_HALT_VOTED, 444 .clkr = { 445 .enable_reg = 0x90e8, 446 .enable_mask = BIT(0), 447 .hw.init = &(const struct clk_init_data) { 448 .name = "gpu_cc_hub_cx_int_clk", 449 .parent_hws = (const struct clk_hw*[]) { 450 &gpu_cc_hub_clk_src.clkr.hw, 451 }, 452 .num_parents = 1, 453 .flags = CLK_SET_RATE_PARENT, 454 .ops = &clk_branch2_aon_ops, 455 }, 456 }, 457 }; 458 459 static struct clk_branch gpu_cc_memnoc_gfx_clk = { 460 .halt_reg = 0x90f0, 461 .halt_check = BRANCH_HALT_VOTED, 462 .clkr = { 463 .enable_reg = 0x90f0, 464 .enable_mask = BIT(0), 465 .hw.init = &(const struct clk_init_data) { 466 .name = "gpu_cc_memnoc_gfx_clk", 467 .ops = &clk_branch2_ops, 468 }, 469 }, 470 }; 471 472 static struct clk_branch gpu_cc_rscc_hub_aon_clk = { 473 .halt_reg = 0x93e8, 474 .halt_check = BRANCH_HALT, 475 .clkr = { 476 .enable_reg = 0x93e8, 477 .enable_mask = BIT(0), 478 .hw.init = &(const struct clk_init_data) { 479 .name = "gpu_cc_rscc_hub_aon_clk", 480 .parent_hws = (const struct clk_hw*[]) { 481 &gpu_cc_hub_clk_src.clkr.hw, 482 }, 483 .num_parents = 1, 484 .flags = CLK_SET_RATE_PARENT, 485 .ops = &clk_branch2_ops, 486 }, 487 }, 488 }; 489 490 static struct clk_branch gpu_cc_sleep_clk = { 491 .halt_reg = 0x90cc, 492 .halt_check = BRANCH_HALT, 493 .clkr = { 494 .enable_reg = 0x90cc, 495 .enable_mask = BIT(0), 496 .hw.init = &(const struct clk_init_data) { 497 .name = "gpu_cc_sleep_clk", 498 .ops = &clk_branch2_ops, 499 }, 500 }, 501 }; 502 503 static struct gdsc gpu_cc_cx_gdsc = { 504 .gdscr = 0x9080, 505 .gds_hw_ctrl = 0x9094, 506 .en_rest_wait_val = 0x2, 507 .en_few_wait_val = 0x2, 508 .clk_dis_wait_val = 0xf, 509 .pd = { 510 .name = "gpu_cc_cx_gdsc", 511 }, 512 .pwrsts = PWRSTS_OFF_ON, 513 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 514 }; 515 516 static struct clk_regmap *gpu_cc_glymur_clocks[] = { 517 [GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr, 518 [GPU_CC_CX_ACCU_SHIFT_CLK] = &gpu_cc_cx_accu_shift_clk.clkr, 519 [GPU_CC_CX_FF_CLK] = &gpu_cc_cx_ff_clk.clkr, 520 [GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr, 521 [GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr, 522 [GPU_CC_DEMET_CLK] = &gpu_cc_demet_clk.clkr, 523 [GPU_CC_DPM_CLK] = &gpu_cc_dpm_clk.clkr, 524 [GPU_CC_FF_CLK_SRC] = &gpu_cc_ff_clk_src.clkr, 525 [GPU_CC_FREQ_MEASURE_CLK] = &gpu_cc_freq_measure_clk.clkr, 526 [GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr, 527 [GPU_CC_GPU_SMMU_VOTE_CLK] = &gpu_cc_gpu_smmu_vote_clk.clkr, 528 [GPU_CC_GX_ACCU_SHIFT_CLK] = &gpu_cc_gx_accu_shift_clk.clkr, 529 [GPU_CC_GX_ACD_AHB_FF_CLK] = &gpu_cc_gx_acd_ahb_ff_clk.clkr, 530 [GPU_CC_GX_AHB_FF_CLK] = &gpu_cc_gx_ahb_ff_clk.clkr, 531 [GPU_CC_GX_GMU_CLK] = &gpu_cc_gx_gmu_clk.clkr, 532 [GPU_CC_GX_RCG_AHB_FF_CLK] = &gpu_cc_gx_rcg_ahb_ff_clk.clkr, 533 [GPU_CC_HUB_AON_CLK] = &gpu_cc_hub_aon_clk.clkr, 534 [GPU_CC_HUB_CLK_SRC] = &gpu_cc_hub_clk_src.clkr, 535 [GPU_CC_HUB_CX_INT_CLK] = &gpu_cc_hub_cx_int_clk.clkr, 536 [GPU_CC_HUB_DIV_CLK_SRC] = &gpu_cc_hub_div_clk_src.clkr, 537 [GPU_CC_MEMNOC_GFX_CLK] = &gpu_cc_memnoc_gfx_clk.clkr, 538 [GPU_CC_PLL0] = &gpu_cc_pll0.clkr, 539 [GPU_CC_PLL0_OUT_EVEN] = &gpu_cc_pll0_out_even.clkr, 540 [GPU_CC_RSCC_HUB_AON_CLK] = &gpu_cc_rscc_hub_aon_clk.clkr, 541 [GPU_CC_SLEEP_CLK] = &gpu_cc_sleep_clk.clkr, 542 }; 543 544 static struct gdsc *gpu_cc_glymur_gdscs[] = { 545 [GPU_CC_CX_GDSC] = &gpu_cc_cx_gdsc, 546 }; 547 548 static const struct qcom_reset_map gpu_cc_glymur_resets[] = { 549 [GPU_CC_CB_BCR] = { 0x93a0 }, 550 [GPU_CC_CX_BCR] = { 0x907c }, 551 [GPU_CC_FAST_HUB_BCR] = { 0x93e4 }, 552 [GPU_CC_FF_BCR] = { 0x9470 }, 553 [GPU_CC_GMU_BCR] = { 0x9314 }, 554 [GPU_CC_GX_BCR] = { 0x905c }, 555 [GPU_CC_XO_BCR] = { 0x9000 }, 556 }; 557 558 static struct clk_alpha_pll *gpu_cc_glymur_plls[] = { 559 &gpu_cc_pll0, 560 }; 561 562 static const u32 gpu_cc_glymur_critical_cbcrs[] = { 563 0x93a4, /* GPU_CC_CB_CLK */ 564 0x9008, /* GPU_CC_CXO_AON_CLK */ 565 0x9004, /* GPU_CC_RSCC_XO_AON_CLK */ 566 }; 567 568 static const struct regmap_config gpu_cc_glymur_regmap_config = { 569 .reg_bits = 32, 570 .reg_stride = 4, 571 .val_bits = 32, 572 .max_register = 0x95e8, 573 .fast_io = true, 574 }; 575 576 static const struct qcom_cc_driver_data gpu_cc_glymur_driver_data = { 577 .alpha_plls = gpu_cc_glymur_plls, 578 .num_alpha_plls = ARRAY_SIZE(gpu_cc_glymur_plls), 579 .clk_cbcrs = gpu_cc_glymur_critical_cbcrs, 580 .num_clk_cbcrs = ARRAY_SIZE(gpu_cc_glymur_critical_cbcrs), 581 }; 582 583 static const struct qcom_cc_desc gpu_cc_glymur_desc = { 584 .config = &gpu_cc_glymur_regmap_config, 585 .clks = gpu_cc_glymur_clocks, 586 .num_clks = ARRAY_SIZE(gpu_cc_glymur_clocks), 587 .resets = gpu_cc_glymur_resets, 588 .num_resets = ARRAY_SIZE(gpu_cc_glymur_resets), 589 .gdscs = gpu_cc_glymur_gdscs, 590 .num_gdscs = ARRAY_SIZE(gpu_cc_glymur_gdscs), 591 .use_rpm = true, 592 .driver_data = &gpu_cc_glymur_driver_data, 593 }; 594 595 static const struct of_device_id gpu_cc_glymur_match_table[] = { 596 { .compatible = "qcom,glymur-gpucc" }, 597 { } 598 }; 599 MODULE_DEVICE_TABLE(of, gpu_cc_glymur_match_table); 600 601 static int gpu_cc_glymur_probe(struct platform_device *pdev) 602 { 603 return qcom_cc_probe(pdev, &gpu_cc_glymur_desc); 604 } 605 606 static struct platform_driver gpu_cc_glymur_driver = { 607 .probe = gpu_cc_glymur_probe, 608 .driver = { 609 .name = "gpucc-glymur", 610 .of_match_table = gpu_cc_glymur_match_table, 611 }, 612 }; 613 614 module_platform_driver(gpu_cc_glymur_driver); 615 616 MODULE_DESCRIPTION("QTI GPUCC Glymur Driver"); 617 MODULE_LICENSE("GPL"); 618