1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 4 */ 5 6 #include <linux/clk-provider.h> 7 #include <linux/mod_devicetable.h> 8 #include <linux/module.h> 9 #include <linux/platform_device.h> 10 #include <linux/regmap.h> 11 12 #include <dt-bindings/clock/qcom,glymur-gpucc.h> 13 14 #include "clk-alpha-pll.h" 15 #include "clk-branch.h" 16 #include "clk-pll.h" 17 #include "clk-rcg.h" 18 #include "clk-regmap.h" 19 #include "clk-regmap-divider.h" 20 #include "clk-regmap-mux.h" 21 #include "common.h" 22 #include "gdsc.h" 23 #include "reset.h" 24 25 enum { 26 DT_BI_TCXO, 27 DT_GPLL0_OUT_MAIN, 28 DT_GPLL0_OUT_MAIN_DIV, 29 }; 30 31 enum { 32 P_BI_TCXO, 33 P_GPLL0_OUT_MAIN, 34 P_GPLL0_OUT_MAIN_DIV, 35 P_GPU_CC_PLL0_OUT_EVEN, 36 P_GPU_CC_PLL0_OUT_MAIN, 37 P_GPU_CC_PLL0_OUT_ODD, 38 }; 39 40 static const struct pll_vco taycan_eko_t_vco[] = { 41 { 249600000, 2500000000, 0 }, 42 }; 43 44 /* 1150.0 MHz Configuration */ 45 static const struct alpha_pll_config gpu_cc_pll0_config = { 46 .l = 0x3b, 47 .alpha = 0xe555, 48 .config_ctl_val = 0x25c400e7, 49 .config_ctl_hi_val = 0x0a8060e0, 50 .config_ctl_hi1_val = 0xf51dea20, 51 .user_ctl_val = 0x00000408, 52 .user_ctl_hi_val = 0x00000002, 53 }; 54 55 static struct clk_alpha_pll gpu_cc_pll0 = { 56 .offset = 0x0, 57 .config = &gpu_cc_pll0_config, 58 .vco_table = taycan_eko_t_vco, 59 .num_vco = ARRAY_SIZE(taycan_eko_t_vco), 60 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], 61 .clkr = { 62 .hw.init = &(const struct clk_init_data) { 63 .name = "gpu_cc_pll0", 64 .parent_data = &(const struct clk_parent_data) { 65 .index = DT_BI_TCXO, 66 }, 67 .num_parents = 1, 68 .ops = &clk_alpha_pll_taycan_eko_t_ops, 69 }, 70 }, 71 }; 72 73 static const struct clk_div_table post_div_table_gpu_cc_pll0_out_even[] = { 74 { 0x1, 2 }, 75 { } 76 }; 77 78 static struct clk_alpha_pll_postdiv gpu_cc_pll0_out_even = { 79 .offset = 0x0, 80 .post_div_shift = 10, 81 .post_div_table = post_div_table_gpu_cc_pll0_out_even, 82 .num_post_div = ARRAY_SIZE(post_div_table_gpu_cc_pll0_out_even), 83 .width = 4, 84 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], 85 .clkr.hw.init = &(const struct clk_init_data) { 86 .name = "gpu_cc_pll0_out_even", 87 .parent_hws = (const struct clk_hw*[]) { 88 &gpu_cc_pll0.clkr.hw, 89 }, 90 .num_parents = 1, 91 .flags = CLK_SET_RATE_PARENT, 92 .ops = &clk_alpha_pll_postdiv_taycan_eko_t_ops, 93 }, 94 }; 95 96 static const struct parent_map gpu_cc_parent_map_0[] = { 97 { P_BI_TCXO, 0 }, 98 { P_GPLL0_OUT_MAIN, 5 }, 99 { P_GPLL0_OUT_MAIN_DIV, 6 }, 100 }; 101 102 static const struct clk_parent_data gpu_cc_parent_data_0[] = { 103 { .index = DT_BI_TCXO }, 104 { .index = DT_GPLL0_OUT_MAIN }, 105 { .index = DT_GPLL0_OUT_MAIN_DIV }, 106 }; 107 108 static const struct parent_map gpu_cc_parent_map_1[] = { 109 { P_BI_TCXO, 0 }, 110 { P_GPU_CC_PLL0_OUT_MAIN, 1 }, 111 { P_GPU_CC_PLL0_OUT_EVEN, 2 }, 112 { P_GPU_CC_PLL0_OUT_ODD, 3 }, 113 { P_GPLL0_OUT_MAIN, 5 }, 114 { P_GPLL0_OUT_MAIN_DIV, 6 }, 115 }; 116 117 static const struct clk_parent_data gpu_cc_parent_data_1[] = { 118 { .index = DT_BI_TCXO }, 119 { .hw = &gpu_cc_pll0.clkr.hw }, 120 { .hw = &gpu_cc_pll0_out_even.clkr.hw }, 121 { .hw = &gpu_cc_pll0.clkr.hw }, 122 { .index = DT_GPLL0_OUT_MAIN }, 123 { .index = DT_GPLL0_OUT_MAIN_DIV }, 124 }; 125 126 static const struct freq_tbl ftbl_gpu_cc_ff_clk_src[] = { 127 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), 128 { } 129 }; 130 131 static struct clk_rcg2 gpu_cc_ff_clk_src = { 132 .cmd_rcgr = 0x9474, 133 .mnd_width = 0, 134 .hid_width = 5, 135 .parent_map = gpu_cc_parent_map_0, 136 .freq_tbl = ftbl_gpu_cc_ff_clk_src, 137 .clkr.hw.init = &(const struct clk_init_data) { 138 .name = "gpu_cc_ff_clk_src", 139 .parent_data = gpu_cc_parent_data_0, 140 .num_parents = ARRAY_SIZE(gpu_cc_parent_data_0), 141 .flags = CLK_SET_RATE_PARENT, 142 .ops = &clk_rcg2_shared_ops, 143 }, 144 }; 145 146 static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = { 147 F(19200000, P_BI_TCXO, 1, 0, 0), 148 F(575000000, P_GPU_CC_PLL0_OUT_EVEN, 1, 0, 0), 149 F(700000000, P_GPU_CC_PLL0_OUT_EVEN, 1, 0, 0), 150 F(725000000, P_GPU_CC_PLL0_OUT_EVEN, 1, 0, 0), 151 F(750000000, P_GPU_CC_PLL0_OUT_EVEN, 1, 0, 0), 152 { } 153 }; 154 155 static struct clk_rcg2 gpu_cc_gmu_clk_src = { 156 .cmd_rcgr = 0x9318, 157 .mnd_width = 0, 158 .hid_width = 5, 159 .parent_map = gpu_cc_parent_map_1, 160 .freq_tbl = ftbl_gpu_cc_gmu_clk_src, 161 .clkr.hw.init = &(const struct clk_init_data) { 162 .name = "gpu_cc_gmu_clk_src", 163 .parent_data = gpu_cc_parent_data_1, 164 .num_parents = ARRAY_SIZE(gpu_cc_parent_data_1), 165 .flags = CLK_SET_RATE_PARENT, 166 .ops = &clk_rcg2_shared_ops, 167 }, 168 }; 169 170 static const struct freq_tbl ftbl_gpu_cc_hub_clk_src[] = { 171 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), 172 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), 173 F(400000000, P_GPLL0_OUT_MAIN, 1.5, 0, 0), 174 { } 175 }; 176 177 static struct clk_rcg2 gpu_cc_hub_clk_src = { 178 .cmd_rcgr = 0x93f0, 179 .mnd_width = 0, 180 .hid_width = 5, 181 .parent_map = gpu_cc_parent_map_1, 182 .freq_tbl = ftbl_gpu_cc_hub_clk_src, 183 .clkr.hw.init = &(const struct clk_init_data) { 184 .name = "gpu_cc_hub_clk_src", 185 .parent_data = gpu_cc_parent_data_1, 186 .num_parents = ARRAY_SIZE(gpu_cc_parent_data_1), 187 .flags = CLK_SET_RATE_PARENT, 188 .ops = &clk_rcg2_shared_ops, 189 }, 190 }; 191 192 static struct clk_regmap_div gpu_cc_hub_div_clk_src = { 193 .reg = 0x9430, 194 .shift = 0, 195 .width = 4, 196 .clkr.hw.init = &(const struct clk_init_data) { 197 .name = "gpu_cc_hub_div_clk_src", 198 .parent_hws = (const struct clk_hw*[]) { 199 &gpu_cc_hub_clk_src.clkr.hw, 200 }, 201 .num_parents = 1, 202 .flags = CLK_SET_RATE_PARENT, 203 .ops = &clk_regmap_div_ro_ops, 204 }, 205 }; 206 207 static struct clk_branch gpu_cc_ahb_clk = { 208 .halt_reg = 0x90bc, 209 .halt_check = BRANCH_HALT_DELAY, 210 .clkr = { 211 .enable_reg = 0x90bc, 212 .enable_mask = BIT(0), 213 .hw.init = &(const struct clk_init_data) { 214 .name = "gpu_cc_ahb_clk", 215 .parent_hws = (const struct clk_hw*[]) { 216 &gpu_cc_hub_div_clk_src.clkr.hw, 217 }, 218 .num_parents = 1, 219 .flags = CLK_SET_RATE_PARENT, 220 .ops = &clk_branch2_ops, 221 }, 222 }, 223 }; 224 225 static struct clk_branch gpu_cc_cx_accu_shift_clk = { 226 .halt_reg = 0x9108, 227 .halt_check = BRANCH_HALT_VOTED, 228 .clkr = { 229 .enable_reg = 0x9108, 230 .enable_mask = BIT(0), 231 .hw.init = &(const struct clk_init_data) { 232 .name = "gpu_cc_cx_accu_shift_clk", 233 .ops = &clk_branch2_ops, 234 }, 235 }, 236 }; 237 238 static struct clk_branch gpu_cc_cx_ff_clk = { 239 .halt_reg = 0x90ec, 240 .halt_check = BRANCH_HALT, 241 .clkr = { 242 .enable_reg = 0x90ec, 243 .enable_mask = BIT(0), 244 .hw.init = &(const struct clk_init_data) { 245 .name = "gpu_cc_cx_ff_clk", 246 .parent_hws = (const struct clk_hw*[]) { 247 &gpu_cc_ff_clk_src.clkr.hw, 248 }, 249 .num_parents = 1, 250 .flags = CLK_SET_RATE_PARENT, 251 .ops = &clk_branch2_ops, 252 }, 253 }, 254 }; 255 256 static struct clk_branch gpu_cc_cx_gmu_clk = { 257 .halt_reg = 0x90d4, 258 .halt_check = BRANCH_HALT_VOTED, 259 .clkr = { 260 .enable_reg = 0x90d4, 261 .enable_mask = BIT(0), 262 .hw.init = &(const struct clk_init_data) { 263 .name = "gpu_cc_cx_gmu_clk", 264 .parent_hws = (const struct clk_hw*[]) { 265 &gpu_cc_gmu_clk_src.clkr.hw, 266 }, 267 .num_parents = 1, 268 .flags = CLK_SET_RATE_PARENT, 269 .ops = &clk_branch2_aon_ops, 270 }, 271 }, 272 }; 273 274 static struct clk_branch gpu_cc_cxo_clk = { 275 .halt_reg = 0x90e4, 276 .halt_check = BRANCH_HALT, 277 .clkr = { 278 .enable_reg = 0x90e4, 279 .enable_mask = BIT(0), 280 .hw.init = &(const struct clk_init_data) { 281 .name = "gpu_cc_cxo_clk", 282 .ops = &clk_branch2_ops, 283 }, 284 }, 285 }; 286 287 static struct clk_branch gpu_cc_demet_clk = { 288 .halt_reg = 0x9010, 289 .halt_check = BRANCH_HALT_VOTED, 290 .clkr = { 291 .enable_reg = 0x9010, 292 .enable_mask = BIT(0), 293 .hw.init = &(const struct clk_init_data) { 294 .name = "gpu_cc_demet_clk", 295 .ops = &clk_branch2_ops, 296 }, 297 }, 298 }; 299 300 static struct clk_branch gpu_cc_dpm_clk = { 301 .halt_reg = 0x910c, 302 .halt_check = BRANCH_HALT, 303 .clkr = { 304 .enable_reg = 0x910c, 305 .enable_mask = BIT(0), 306 .hw.init = &(const struct clk_init_data) { 307 .name = "gpu_cc_dpm_clk", 308 .ops = &clk_branch2_ops, 309 }, 310 }, 311 }; 312 313 static struct clk_branch gpu_cc_freq_measure_clk = { 314 .halt_reg = 0x900c, 315 .halt_check = BRANCH_HALT, 316 .clkr = { 317 .enable_reg = 0x900c, 318 .enable_mask = BIT(0), 319 .hw.init = &(const struct clk_init_data) { 320 .name = "gpu_cc_freq_measure_clk", 321 .ops = &clk_branch2_ops, 322 }, 323 }, 324 }; 325 326 static struct clk_branch gpu_cc_gpu_smmu_vote_clk = { 327 .halt_reg = 0x7000, 328 .halt_check = BRANCH_HALT_VOTED, 329 .clkr = { 330 .enable_reg = 0x7000, 331 .enable_mask = BIT(0), 332 .hw.init = &(const struct clk_init_data) { 333 .name = "gpu_cc_gpu_smmu_vote_clk", 334 .ops = &clk_branch2_ops, 335 }, 336 }, 337 }; 338 339 static struct clk_branch gpu_cc_gx_accu_shift_clk = { 340 .halt_reg = 0x9070, 341 .halt_check = BRANCH_HALT_VOTED, 342 .clkr = { 343 .enable_reg = 0x9070, 344 .enable_mask = BIT(0), 345 .hw.init = &(const struct clk_init_data) { 346 .name = "gpu_cc_gx_accu_shift_clk", 347 .ops = &clk_branch2_ops, 348 }, 349 }, 350 }; 351 352 static struct clk_branch gpu_cc_gx_acd_ahb_ff_clk = { 353 .halt_reg = 0x9068, 354 .halt_check = BRANCH_HALT, 355 .clkr = { 356 .enable_reg = 0x9068, 357 .enable_mask = BIT(0), 358 .hw.init = &(const struct clk_init_data) { 359 .name = "gpu_cc_gx_acd_ahb_ff_clk", 360 .parent_hws = (const struct clk_hw*[]) { 361 &gpu_cc_ff_clk_src.clkr.hw, 362 }, 363 .num_parents = 1, 364 .flags = CLK_SET_RATE_PARENT, 365 .ops = &clk_branch2_ops, 366 }, 367 }, 368 }; 369 370 static struct clk_branch gpu_cc_gx_ahb_ff_clk = { 371 .halt_reg = 0x9064, 372 .halt_check = BRANCH_HALT, 373 .clkr = { 374 .enable_reg = 0x9064, 375 .enable_mask = BIT(0), 376 .hw.init = &(const struct clk_init_data) { 377 .name = "gpu_cc_gx_ahb_ff_clk", 378 .parent_hws = (const struct clk_hw*[]) { 379 &gpu_cc_ff_clk_src.clkr.hw, 380 }, 381 .num_parents = 1, 382 .flags = CLK_SET_RATE_PARENT, 383 .ops = &clk_branch2_ops, 384 }, 385 }, 386 }; 387 388 static struct clk_branch gpu_cc_gx_gmu_clk = { 389 .halt_reg = 0x9060, 390 .halt_check = BRANCH_HALT, 391 .clkr = { 392 .enable_reg = 0x9060, 393 .enable_mask = BIT(0), 394 .hw.init = &(const struct clk_init_data) { 395 .name = "gpu_cc_gx_gmu_clk", 396 .parent_hws = (const struct clk_hw*[]) { 397 &gpu_cc_gmu_clk_src.clkr.hw, 398 }, 399 .num_parents = 1, 400 .flags = CLK_SET_RATE_PARENT, 401 .ops = &clk_branch2_ops, 402 }, 403 }, 404 }; 405 406 static struct clk_branch gpu_cc_gx_rcg_ahb_ff_clk = { 407 .halt_reg = 0x906c, 408 .halt_check = BRANCH_HALT_VOTED, 409 .clkr = { 410 .enable_reg = 0x906c, 411 .enable_mask = BIT(0), 412 .hw.init = &(const struct clk_init_data) { 413 .name = "gpu_cc_gx_rcg_ahb_ff_clk", 414 .parent_hws = (const struct clk_hw*[]) { 415 &gpu_cc_ff_clk_src.clkr.hw, 416 }, 417 .num_parents = 1, 418 .flags = CLK_SET_RATE_PARENT, 419 .ops = &clk_branch2_ops, 420 }, 421 }, 422 }; 423 424 static struct clk_branch gpu_cc_hub_aon_clk = { 425 .halt_reg = 0x93ec, 426 .halt_check = BRANCH_HALT_VOTED, 427 .clkr = { 428 .enable_reg = 0x93ec, 429 .enable_mask = BIT(0), 430 .hw.init = &(const struct clk_init_data) { 431 .name = "gpu_cc_hub_aon_clk", 432 .parent_hws = (const struct clk_hw*[]) { 433 &gpu_cc_hub_clk_src.clkr.hw, 434 }, 435 .num_parents = 1, 436 .flags = CLK_SET_RATE_PARENT, 437 .ops = &clk_branch2_aon_ops, 438 }, 439 }, 440 }; 441 442 static struct clk_branch gpu_cc_hub_cx_int_clk = { 443 .halt_reg = 0x90e8, 444 .halt_check = BRANCH_HALT_VOTED, 445 .clkr = { 446 .enable_reg = 0x90e8, 447 .enable_mask = BIT(0), 448 .hw.init = &(const struct clk_init_data) { 449 .name = "gpu_cc_hub_cx_int_clk", 450 .parent_hws = (const struct clk_hw*[]) { 451 &gpu_cc_hub_clk_src.clkr.hw, 452 }, 453 .num_parents = 1, 454 .flags = CLK_SET_RATE_PARENT, 455 .ops = &clk_branch2_aon_ops, 456 }, 457 }, 458 }; 459 460 static struct clk_branch gpu_cc_memnoc_gfx_clk = { 461 .halt_reg = 0x90f0, 462 .halt_check = BRANCH_HALT_VOTED, 463 .clkr = { 464 .enable_reg = 0x90f0, 465 .enable_mask = BIT(0), 466 .hw.init = &(const struct clk_init_data) { 467 .name = "gpu_cc_memnoc_gfx_clk", 468 .ops = &clk_branch2_ops, 469 }, 470 }, 471 }; 472 473 static struct clk_branch gpu_cc_rscc_hub_aon_clk = { 474 .halt_reg = 0x93e8, 475 .halt_check = BRANCH_HALT, 476 .clkr = { 477 .enable_reg = 0x93e8, 478 .enable_mask = BIT(0), 479 .hw.init = &(const struct clk_init_data) { 480 .name = "gpu_cc_rscc_hub_aon_clk", 481 .parent_hws = (const struct clk_hw*[]) { 482 &gpu_cc_hub_clk_src.clkr.hw, 483 }, 484 .num_parents = 1, 485 .flags = CLK_SET_RATE_PARENT, 486 .ops = &clk_branch2_ops, 487 }, 488 }, 489 }; 490 491 static struct clk_branch gpu_cc_sleep_clk = { 492 .halt_reg = 0x90cc, 493 .halt_check = BRANCH_HALT, 494 .clkr = { 495 .enable_reg = 0x90cc, 496 .enable_mask = BIT(0), 497 .hw.init = &(const struct clk_init_data) { 498 .name = "gpu_cc_sleep_clk", 499 .ops = &clk_branch2_ops, 500 }, 501 }, 502 }; 503 504 static struct gdsc gpu_cc_cx_gdsc = { 505 .gdscr = 0x9080, 506 .gds_hw_ctrl = 0x9094, 507 .en_rest_wait_val = 0x2, 508 .en_few_wait_val = 0x2, 509 .clk_dis_wait_val = 0xf, 510 .pd = { 511 .name = "gpu_cc_cx_gdsc", 512 }, 513 .pwrsts = PWRSTS_OFF_ON, 514 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 515 }; 516 517 static struct clk_regmap *gpu_cc_glymur_clocks[] = { 518 [GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr, 519 [GPU_CC_CX_ACCU_SHIFT_CLK] = &gpu_cc_cx_accu_shift_clk.clkr, 520 [GPU_CC_CX_FF_CLK] = &gpu_cc_cx_ff_clk.clkr, 521 [GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr, 522 [GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr, 523 [GPU_CC_DEMET_CLK] = &gpu_cc_demet_clk.clkr, 524 [GPU_CC_DPM_CLK] = &gpu_cc_dpm_clk.clkr, 525 [GPU_CC_FF_CLK_SRC] = &gpu_cc_ff_clk_src.clkr, 526 [GPU_CC_FREQ_MEASURE_CLK] = &gpu_cc_freq_measure_clk.clkr, 527 [GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr, 528 [GPU_CC_GPU_SMMU_VOTE_CLK] = &gpu_cc_gpu_smmu_vote_clk.clkr, 529 [GPU_CC_GX_ACCU_SHIFT_CLK] = &gpu_cc_gx_accu_shift_clk.clkr, 530 [GPU_CC_GX_ACD_AHB_FF_CLK] = &gpu_cc_gx_acd_ahb_ff_clk.clkr, 531 [GPU_CC_GX_AHB_FF_CLK] = &gpu_cc_gx_ahb_ff_clk.clkr, 532 [GPU_CC_GX_GMU_CLK] = &gpu_cc_gx_gmu_clk.clkr, 533 [GPU_CC_GX_RCG_AHB_FF_CLK] = &gpu_cc_gx_rcg_ahb_ff_clk.clkr, 534 [GPU_CC_HUB_AON_CLK] = &gpu_cc_hub_aon_clk.clkr, 535 [GPU_CC_HUB_CLK_SRC] = &gpu_cc_hub_clk_src.clkr, 536 [GPU_CC_HUB_CX_INT_CLK] = &gpu_cc_hub_cx_int_clk.clkr, 537 [GPU_CC_HUB_DIV_CLK_SRC] = &gpu_cc_hub_div_clk_src.clkr, 538 [GPU_CC_MEMNOC_GFX_CLK] = &gpu_cc_memnoc_gfx_clk.clkr, 539 [GPU_CC_PLL0] = &gpu_cc_pll0.clkr, 540 [GPU_CC_PLL0_OUT_EVEN] = &gpu_cc_pll0_out_even.clkr, 541 [GPU_CC_RSCC_HUB_AON_CLK] = &gpu_cc_rscc_hub_aon_clk.clkr, 542 [GPU_CC_SLEEP_CLK] = &gpu_cc_sleep_clk.clkr, 543 }; 544 545 static struct gdsc *gpu_cc_glymur_gdscs[] = { 546 [GPU_CC_CX_GDSC] = &gpu_cc_cx_gdsc, 547 }; 548 549 static const struct qcom_reset_map gpu_cc_glymur_resets[] = { 550 [GPU_CC_CB_BCR] = { 0x93a0 }, 551 [GPU_CC_CX_BCR] = { 0x907c }, 552 [GPU_CC_FAST_HUB_BCR] = { 0x93e4 }, 553 [GPU_CC_FF_BCR] = { 0x9470 }, 554 [GPU_CC_GMU_BCR] = { 0x9314 }, 555 [GPU_CC_GX_BCR] = { 0x905c }, 556 [GPU_CC_XO_BCR] = { 0x9000 }, 557 }; 558 559 static struct clk_alpha_pll *gpu_cc_glymur_plls[] = { 560 &gpu_cc_pll0, 561 }; 562 563 static const u32 gpu_cc_glymur_critical_cbcrs[] = { 564 0x93a4, /* GPU_CC_CB_CLK */ 565 0x9008, /* GPU_CC_CXO_AON_CLK */ 566 0x9004, /* GPU_CC_RSCC_XO_AON_CLK */ 567 }; 568 569 static const struct regmap_config gpu_cc_glymur_regmap_config = { 570 .reg_bits = 32, 571 .reg_stride = 4, 572 .val_bits = 32, 573 .max_register = 0x95e8, 574 .fast_io = true, 575 }; 576 577 static const struct qcom_cc_driver_data gpu_cc_glymur_driver_data = { 578 .alpha_plls = gpu_cc_glymur_plls, 579 .num_alpha_plls = ARRAY_SIZE(gpu_cc_glymur_plls), 580 .clk_cbcrs = gpu_cc_glymur_critical_cbcrs, 581 .num_clk_cbcrs = ARRAY_SIZE(gpu_cc_glymur_critical_cbcrs), 582 }; 583 584 static const struct qcom_cc_desc gpu_cc_glymur_desc = { 585 .config = &gpu_cc_glymur_regmap_config, 586 .clks = gpu_cc_glymur_clocks, 587 .num_clks = ARRAY_SIZE(gpu_cc_glymur_clocks), 588 .resets = gpu_cc_glymur_resets, 589 .num_resets = ARRAY_SIZE(gpu_cc_glymur_resets), 590 .gdscs = gpu_cc_glymur_gdscs, 591 .num_gdscs = ARRAY_SIZE(gpu_cc_glymur_gdscs), 592 .use_rpm = true, 593 .driver_data = &gpu_cc_glymur_driver_data, 594 }; 595 596 static const struct of_device_id gpu_cc_glymur_match_table[] = { 597 { .compatible = "qcom,glymur-gpucc" }, 598 { } 599 }; 600 MODULE_DEVICE_TABLE(of, gpu_cc_glymur_match_table); 601 602 static int gpu_cc_glymur_probe(struct platform_device *pdev) 603 { 604 return qcom_cc_probe(pdev, &gpu_cc_glymur_desc); 605 } 606 607 static struct platform_driver gpu_cc_glymur_driver = { 608 .probe = gpu_cc_glymur_probe, 609 .driver = { 610 .name = "gpucc-glymur", 611 .of_match_table = gpu_cc_glymur_match_table, 612 }, 613 }; 614 615 module_platform_driver(gpu_cc_glymur_driver); 616 617 MODULE_DESCRIPTION("QTI GPUCC Glymur Driver"); 618 MODULE_LICENSE("GPL"); 619