1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2021, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 5 * Copyright (c) 2023, Linaro Limited 6 */ 7 8 #include <linux/clk-provider.h> 9 #include <linux/module.h> 10 #include <linux/platform_device.h> 11 #include <linux/regmap.h> 12 13 #include <dt-bindings/clock/qcom,sm8650-gcc.h> 14 15 #include "clk-alpha-pll.h" 16 #include "clk-branch.h" 17 #include "clk-rcg.h" 18 #include "clk-regmap.h" 19 #include "clk-regmap-divider.h" 20 #include "clk-regmap-mux.h" 21 #include "clk-regmap-phy-mux.h" 22 #include "gdsc.h" 23 #include "reset.h" 24 25 /* Need to match the order of clocks in DT binding */ 26 enum { 27 DT_BI_TCXO, 28 DT_BI_TCXO_AO, 29 DT_SLEEP_CLK, 30 31 DT_PCIE_0_PIPE, 32 DT_PCIE_1_PIPE, 33 DT_PCIE_1_PHY_AUX, 34 35 DT_UFS_PHY_RX_SYMBOL_0, 36 DT_UFS_PHY_RX_SYMBOL_1, 37 DT_UFS_PHY_TX_SYMBOL_0, 38 39 DT_USB3_PHY_WRAPPER_GCC_USB30_PIPE, 40 }; 41 42 enum { 43 P_BI_TCXO, 44 P_GCC_GPLL0_OUT_EVEN, 45 P_GCC_GPLL0_OUT_MAIN, 46 P_GCC_GPLL1_OUT_MAIN, 47 P_GCC_GPLL3_OUT_MAIN, 48 P_GCC_GPLL4_OUT_MAIN, 49 P_GCC_GPLL6_OUT_MAIN, 50 P_GCC_GPLL7_OUT_MAIN, 51 P_GCC_GPLL9_OUT_MAIN, 52 P_PCIE_0_PIPE_CLK, 53 P_PCIE_1_PHY_AUX_CLK, 54 P_PCIE_1_PIPE_CLK, 55 P_SLEEP_CLK, 56 P_UFS_PHY_RX_SYMBOL_0_CLK, 57 P_UFS_PHY_RX_SYMBOL_1_CLK, 58 P_UFS_PHY_TX_SYMBOL_0_CLK, 59 P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 60 }; 61 62 static struct clk_alpha_pll gcc_gpll0 = { 63 .offset = 0x0, 64 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 65 .clkr = { 66 .enable_reg = 0x52020, 67 .enable_mask = BIT(0), 68 .hw.init = &(const struct clk_init_data) { 69 .name = "gcc_gpll0", 70 .parent_data = &(const struct clk_parent_data) { 71 .index = DT_BI_TCXO, 72 }, 73 .num_parents = 1, 74 .ops = &clk_alpha_pll_fixed_lucid_ole_ops, 75 }, 76 }, 77 }; 78 79 static struct clk_alpha_pll gcc_gpll0_ao = { 80 .offset = 0x0, 81 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 82 .clkr = { 83 .enable_reg = 0x57020, 84 .enable_mask = BIT(0), 85 .hw.init = &(const struct clk_init_data) { 86 .name = "gcc_gpll0_ao", 87 .parent_data = &(const struct clk_parent_data) { 88 .index = DT_BI_TCXO_AO, 89 }, 90 .num_parents = 1, 91 .ops = &clk_alpha_pll_fixed_lucid_ole_ops, 92 }, 93 }, 94 }; 95 96 static const struct clk_div_table post_div_table_gcc_gpll0_out_even[] = { 97 { 0x1, 2 }, 98 { } 99 }; 100 101 static struct clk_alpha_pll_postdiv gcc_gpll0_out_even = { 102 .offset = 0x0, 103 .post_div_shift = 10, 104 .post_div_table = post_div_table_gcc_gpll0_out_even, 105 .num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_even), 106 .width = 4, 107 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 108 .clkr.hw.init = &(const struct clk_init_data) { 109 .name = "gcc_gpll0_out_even", 110 .parent_hws = (const struct clk_hw*[]) { 111 &gcc_gpll0.clkr.hw, 112 }, 113 .num_parents = 1, 114 .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, 115 }, 116 }; 117 118 static struct clk_alpha_pll_postdiv gcc_gpll0_out_even_ao = { 119 .offset = 0x0, 120 .post_div_shift = 10, 121 .post_div_table = post_div_table_gcc_gpll0_out_even, 122 .num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_even), 123 .width = 4, 124 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 125 .clkr.hw.init = &(const struct clk_init_data) { 126 .name = "gcc_gpll0_out_even_ao", 127 .parent_hws = (const struct clk_hw*[]) { 128 &gcc_gpll0_ao.clkr.hw, 129 }, 130 .num_parents = 1, 131 .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, 132 }, 133 }; 134 135 static struct clk_alpha_pll gcc_gpll1 = { 136 .offset = 0x4000, 137 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 138 .clkr = { 139 .enable_reg = 0x52020, 140 .enable_mask = BIT(1), 141 .hw.init = &(const struct clk_init_data) { 142 .name = "gcc_gpll1", 143 .parent_data = &(const struct clk_parent_data) { 144 .index = DT_BI_TCXO, 145 }, 146 .num_parents = 1, 147 .ops = &clk_alpha_pll_fixed_lucid_ole_ops, 148 }, 149 }, 150 }; 151 152 static struct clk_alpha_pll gcc_gpll1_ao = { 153 .offset = 0x1000, 154 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 155 .clkr = { 156 .enable_reg = 0x57020, 157 .enable_mask = BIT(1), 158 .hw.init = &(const struct clk_init_data) { 159 .name = "gcc_gpll1_ao", 160 .parent_data = &(const struct clk_parent_data) { 161 .index = DT_BI_TCXO_AO, 162 }, 163 .num_parents = 1, 164 .ops = &clk_alpha_pll_fixed_lucid_ole_ops, 165 }, 166 }, 167 }; 168 169 static struct clk_alpha_pll gcc_gpll3 = { 170 .offset = 0x3000, 171 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 172 .clkr = { 173 .enable_reg = 0x52020, 174 .enable_mask = BIT(3), 175 .hw.init = &(const struct clk_init_data) { 176 .name = "gcc_gpll3", 177 .parent_data = &(const struct clk_parent_data) { 178 .index = DT_BI_TCXO, 179 }, 180 .num_parents = 1, 181 .ops = &clk_alpha_pll_fixed_lucid_ole_ops, 182 }, 183 }, 184 }; 185 186 static struct clk_alpha_pll gcc_gpll3_ao = { 187 .offset = 0x3000, 188 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 189 .clkr = { 190 .enable_reg = 0x57020, 191 .enable_mask = BIT(3), 192 .hw.init = &(const struct clk_init_data) { 193 .name = "gcc_gpll3_ao", 194 .parent_data = &(const struct clk_parent_data) { 195 .index = DT_BI_TCXO_AO, 196 }, 197 .num_parents = 1, 198 .ops = &clk_alpha_pll_fixed_lucid_ole_ops, 199 }, 200 }, 201 }; 202 203 static struct clk_alpha_pll gcc_gpll4 = { 204 .offset = 0x4000, 205 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 206 .clkr = { 207 .enable_reg = 0x52020, 208 .enable_mask = BIT(4), 209 .hw.init = &(const struct clk_init_data) { 210 .name = "gcc_gpll4", 211 .parent_data = &(const struct clk_parent_data) { 212 .index = DT_BI_TCXO, 213 }, 214 .num_parents = 1, 215 .ops = &clk_alpha_pll_fixed_lucid_ole_ops, 216 }, 217 }, 218 }; 219 220 static struct clk_alpha_pll gcc_gpll4_ao = { 221 .offset = 0x4000, 222 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 223 .clkr = { 224 .enable_reg = 0x57020, 225 .enable_mask = BIT(4), 226 .hw.init = &(const struct clk_init_data) { 227 .name = "gcc_gpll4_ao", 228 .parent_data = &(const struct clk_parent_data) { 229 .index = DT_BI_TCXO_AO, 230 }, 231 .num_parents = 1, 232 .ops = &clk_alpha_pll_fixed_lucid_ole_ops, 233 }, 234 }, 235 }; 236 237 static struct clk_alpha_pll gcc_gpll6 = { 238 .offset = 0x6000, 239 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 240 .clkr = { 241 .enable_reg = 0x52020, 242 .enable_mask = BIT(6), 243 .hw.init = &(const struct clk_init_data) { 244 .name = "gcc_gpll6", 245 .parent_data = &(const struct clk_parent_data) { 246 .index = DT_BI_TCXO, 247 }, 248 .num_parents = 1, 249 .ops = &clk_alpha_pll_fixed_lucid_ole_ops, 250 }, 251 }, 252 }; 253 254 static struct clk_alpha_pll gcc_gpll6_ao = { 255 .offset = 0x6000, 256 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 257 .clkr = { 258 .enable_reg = 0x57020, 259 .enable_mask = BIT(6), 260 .hw.init = &(const struct clk_init_data) { 261 .name = "gcc_gpll6_ao", 262 .parent_data = &(const struct clk_parent_data) { 263 .index = DT_BI_TCXO_AO, 264 }, 265 .num_parents = 1, 266 .ops = &clk_alpha_pll_fixed_lucid_ole_ops, 267 }, 268 }, 269 }; 270 271 static struct clk_alpha_pll gcc_gpll7 = { 272 .offset = 0x7000, 273 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 274 .clkr = { 275 .enable_reg = 0x52020, 276 .enable_mask = BIT(7), 277 .hw.init = &(const struct clk_init_data) { 278 .name = "gcc_gpll7", 279 .parent_data = &(const struct clk_parent_data) { 280 .index = DT_BI_TCXO, 281 }, 282 .num_parents = 1, 283 .ops = &clk_alpha_pll_fixed_lucid_ole_ops, 284 }, 285 }, 286 }; 287 288 static struct clk_alpha_pll gcc_gpll9 = { 289 .offset = 0x9000, 290 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 291 .clkr = { 292 .enable_reg = 0x52020, 293 .enable_mask = BIT(9), 294 .hw.init = &(const struct clk_init_data) { 295 .name = "gcc_gpll9", 296 .parent_data = &(const struct clk_parent_data) { 297 .index = DT_BI_TCXO, 298 }, 299 .num_parents = 1, 300 .ops = &clk_alpha_pll_fixed_lucid_ole_ops, 301 }, 302 }, 303 }; 304 305 static const struct parent_map gcc_parent_map_0[] = { 306 { P_BI_TCXO, 0 }, 307 { P_GCC_GPLL0_OUT_MAIN, 1 }, 308 { P_GCC_GPLL0_OUT_EVEN, 6 }, 309 }; 310 311 static const struct clk_parent_data gcc_parent_data_0[] = { 312 { .index = DT_BI_TCXO }, 313 { .hw = &gcc_gpll0.clkr.hw }, 314 { .hw = &gcc_gpll0_out_even.clkr.hw }, 315 }; 316 317 static const struct parent_map gcc_parent_map_1[] = { 318 { P_BI_TCXO, 0 }, 319 { P_GCC_GPLL0_OUT_MAIN, 1 }, 320 { P_SLEEP_CLK, 5 }, 321 { P_GCC_GPLL0_OUT_EVEN, 6 }, 322 }; 323 324 static const struct clk_parent_data gcc_parent_data_1[] = { 325 { .index = DT_BI_TCXO }, 326 { .hw = &gcc_gpll0.clkr.hw }, 327 { .index = DT_SLEEP_CLK }, 328 { .hw = &gcc_gpll0_out_even.clkr.hw }, 329 }; 330 331 static const struct parent_map gcc_parent_map_2[] = { 332 { P_BI_TCXO, 0 }, 333 { P_GCC_GPLL0_OUT_MAIN, 1 }, 334 { P_GCC_GPLL1_OUT_MAIN, 4 }, 335 { P_GCC_GPLL4_OUT_MAIN, 5 }, 336 { P_GCC_GPLL0_OUT_EVEN, 6 }, 337 }; 338 339 static const struct clk_parent_data gcc_parent_data_2[] = { 340 { .index = DT_BI_TCXO }, 341 { .hw = &gcc_gpll0.clkr.hw }, 342 { .hw = &gcc_gpll1.clkr.hw }, 343 { .hw = &gcc_gpll4.clkr.hw }, 344 { .hw = &gcc_gpll0_out_even.clkr.hw }, 345 }; 346 347 static const struct parent_map gcc_parent_map_3[] = { 348 { P_BI_TCXO, 0 }, 349 { P_GCC_GPLL0_OUT_MAIN, 1 }, 350 { P_GCC_GPLL4_OUT_MAIN, 5 }, 351 { P_GCC_GPLL0_OUT_EVEN, 6 }, 352 }; 353 354 static const struct clk_parent_data gcc_parent_data_3[] = { 355 { .index = DT_BI_TCXO }, 356 { .hw = &gcc_gpll0.clkr.hw }, 357 { .hw = &gcc_gpll4.clkr.hw }, 358 { .hw = &gcc_gpll0_out_even.clkr.hw }, 359 }; 360 361 static const struct parent_map gcc_parent_map_4[] = { 362 { P_BI_TCXO, 0 }, 363 { P_SLEEP_CLK, 5 }, 364 }; 365 366 static const struct clk_parent_data gcc_parent_data_4[] = { 367 { .index = DT_BI_TCXO }, 368 { .index = DT_SLEEP_CLK }, 369 }; 370 371 static const struct parent_map gcc_parent_map_5[] = { 372 { P_BI_TCXO, 0 }, 373 }; 374 375 static const struct clk_parent_data gcc_parent_data_5[] = { 376 { .index = DT_BI_TCXO }, 377 }; 378 379 static const struct parent_map gcc_parent_map_8[] = { 380 { P_PCIE_1_PHY_AUX_CLK, 0 }, 381 { P_BI_TCXO, 2 }, 382 }; 383 384 static const struct clk_parent_data gcc_parent_data_8[] = { 385 { .index = DT_PCIE_1_PHY_AUX }, 386 { .index = DT_BI_TCXO }, 387 }; 388 389 static const struct parent_map gcc_parent_map_10[] = { 390 { P_BI_TCXO, 0 }, 391 { P_GCC_GPLL0_OUT_MAIN, 1 }, 392 { P_GCC_GPLL7_OUT_MAIN, 2 }, 393 { P_GCC_GPLL0_OUT_EVEN, 6 }, 394 }; 395 396 static const struct clk_parent_data gcc_parent_data_10[] = { 397 { .index = DT_BI_TCXO }, 398 { .hw = &gcc_gpll0.clkr.hw }, 399 { .hw = &gcc_gpll7.clkr.hw }, 400 { .hw = &gcc_gpll0_out_even.clkr.hw }, 401 }; 402 403 static const struct parent_map gcc_parent_map_11[] = { 404 { P_BI_TCXO, 0 }, 405 { P_GCC_GPLL0_OUT_MAIN, 1 }, 406 { P_GCC_GPLL9_OUT_MAIN, 2 }, 407 { P_GCC_GPLL4_OUT_MAIN, 5 }, 408 { P_GCC_GPLL0_OUT_EVEN, 6 }, 409 }; 410 411 static const struct clk_parent_data gcc_parent_data_11[] = { 412 { .index = DT_BI_TCXO }, 413 { .hw = &gcc_gpll0.clkr.hw }, 414 { .hw = &gcc_gpll9.clkr.hw }, 415 { .hw = &gcc_gpll4.clkr.hw }, 416 { .hw = &gcc_gpll0_out_even.clkr.hw }, 417 }; 418 419 static const struct parent_map gcc_parent_map_12[] = { 420 { P_UFS_PHY_RX_SYMBOL_0_CLK, 0 }, 421 { P_BI_TCXO, 2 }, 422 }; 423 424 static const struct clk_parent_data gcc_parent_data_12[] = { 425 { .index = DT_UFS_PHY_RX_SYMBOL_0 }, 426 { .index = DT_BI_TCXO }, 427 }; 428 429 static const struct parent_map gcc_parent_map_13[] = { 430 { P_UFS_PHY_RX_SYMBOL_1_CLK, 0 }, 431 { P_BI_TCXO, 2 }, 432 }; 433 434 static const struct clk_parent_data gcc_parent_data_13[] = { 435 { .index = DT_UFS_PHY_RX_SYMBOL_1 }, 436 { .index = DT_BI_TCXO }, 437 }; 438 439 static const struct parent_map gcc_parent_map_14[] = { 440 { P_UFS_PHY_TX_SYMBOL_0_CLK, 0 }, 441 { P_BI_TCXO, 2 }, 442 }; 443 444 static const struct clk_parent_data gcc_parent_data_14[] = { 445 { .index = DT_UFS_PHY_TX_SYMBOL_0 }, 446 { .index = DT_BI_TCXO }, 447 }; 448 449 static const struct parent_map gcc_parent_map_15[] = { 450 { P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 0 }, 451 { P_BI_TCXO, 2 }, 452 }; 453 454 static const struct clk_parent_data gcc_parent_data_15[] = { 455 { .index = DT_USB3_PHY_WRAPPER_GCC_USB30_PIPE }, 456 { .index = DT_BI_TCXO }, 457 }; 458 459 static struct clk_regmap_phy_mux gcc_pcie_0_pipe_clk_src = { 460 .reg = 0x6b070, 461 .clkr = { 462 .hw.init = &(const struct clk_init_data) { 463 .name = "gcc_pcie_0_pipe_clk_src", 464 .parent_data = &(const struct clk_parent_data){ 465 .index = DT_PCIE_0_PIPE, 466 }, 467 .num_parents = 1, 468 .ops = &clk_regmap_phy_mux_ops, 469 }, 470 }, 471 }; 472 473 static struct clk_regmap_mux gcc_pcie_1_phy_aux_clk_src = { 474 .reg = 0x8d094, 475 .shift = 0, 476 .width = 2, 477 .parent_map = gcc_parent_map_8, 478 .clkr = { 479 .hw.init = &(const struct clk_init_data) { 480 .name = "gcc_pcie_1_phy_aux_clk_src", 481 .parent_data = gcc_parent_data_8, 482 .num_parents = ARRAY_SIZE(gcc_parent_data_8), 483 .ops = &clk_regmap_mux_closest_ops, 484 }, 485 }, 486 }; 487 488 static struct clk_regmap_phy_mux gcc_pcie_1_pipe_clk_src = { 489 .reg = 0x8d078, 490 .clkr = { 491 .hw.init = &(const struct clk_init_data) { 492 .name = "gcc_pcie_1_pipe_clk_src", 493 .parent_data = &(const struct clk_parent_data){ 494 .index = DT_PCIE_1_PIPE, 495 }, 496 .num_parents = 1, 497 .ops = &clk_regmap_phy_mux_ops, 498 }, 499 }, 500 }; 501 502 static struct clk_regmap_mux gcc_ufs_phy_rx_symbol_0_clk_src = { 503 .reg = 0x77064, 504 .shift = 0, 505 .width = 2, 506 .parent_map = gcc_parent_map_12, 507 .clkr = { 508 .hw.init = &(const struct clk_init_data) { 509 .name = "gcc_ufs_phy_rx_symbol_0_clk_src", 510 .parent_data = gcc_parent_data_12, 511 .num_parents = ARRAY_SIZE(gcc_parent_data_12), 512 .ops = &clk_regmap_mux_closest_ops, 513 }, 514 }, 515 }; 516 517 static struct clk_regmap_mux gcc_ufs_phy_rx_symbol_1_clk_src = { 518 .reg = 0x770e0, 519 .shift = 0, 520 .width = 2, 521 .parent_map = gcc_parent_map_13, 522 .clkr = { 523 .hw.init = &(const struct clk_init_data) { 524 .name = "gcc_ufs_phy_rx_symbol_1_clk_src", 525 .parent_data = gcc_parent_data_13, 526 .num_parents = ARRAY_SIZE(gcc_parent_data_13), 527 .ops = &clk_regmap_mux_closest_ops, 528 }, 529 }, 530 }; 531 532 static struct clk_regmap_mux gcc_ufs_phy_tx_symbol_0_clk_src = { 533 .reg = 0x77054, 534 .shift = 0, 535 .width = 2, 536 .parent_map = gcc_parent_map_14, 537 .clkr = { 538 .hw.init = &(const struct clk_init_data) { 539 .name = "gcc_ufs_phy_tx_symbol_0_clk_src", 540 .parent_data = gcc_parent_data_14, 541 .num_parents = ARRAY_SIZE(gcc_parent_data_14), 542 .ops = &clk_regmap_mux_closest_ops, 543 }, 544 }, 545 }; 546 547 static struct clk_regmap_mux gcc_usb3_prim_phy_pipe_clk_src = { 548 .reg = 0x3906c, 549 .shift = 0, 550 .width = 2, 551 .parent_map = gcc_parent_map_15, 552 .clkr = { 553 .hw.init = &(const struct clk_init_data) { 554 .name = "gcc_usb3_prim_phy_pipe_clk_src", 555 .parent_data = gcc_parent_data_15, 556 .num_parents = ARRAY_SIZE(gcc_parent_data_15), 557 .ops = &clk_regmap_mux_closest_ops, 558 }, 559 }, 560 }; 561 562 static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = { 563 F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0), 564 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 565 F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0), 566 { } 567 }; 568 569 static struct clk_rcg2 gcc_gp1_clk_src = { 570 .cmd_rcgr = 0x64004, 571 .mnd_width = 16, 572 .hid_width = 5, 573 .parent_map = gcc_parent_map_1, 574 .freq_tbl = ftbl_gcc_gp1_clk_src, 575 .clkr.hw.init = &(const struct clk_init_data) { 576 .name = "gcc_gp1_clk_src", 577 .parent_data = gcc_parent_data_1, 578 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 579 .flags = CLK_SET_RATE_PARENT, 580 .ops = &clk_rcg2_shared_ops, 581 }, 582 }; 583 584 static struct clk_rcg2 gcc_gp2_clk_src = { 585 .cmd_rcgr = 0x65004, 586 .mnd_width = 16, 587 .hid_width = 5, 588 .parent_map = gcc_parent_map_1, 589 .freq_tbl = ftbl_gcc_gp1_clk_src, 590 .clkr.hw.init = &(const struct clk_init_data) { 591 .name = "gcc_gp2_clk_src", 592 .parent_data = gcc_parent_data_1, 593 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 594 .flags = CLK_SET_RATE_PARENT, 595 .ops = &clk_rcg2_shared_ops, 596 }, 597 }; 598 599 static struct clk_rcg2 gcc_gp3_clk_src = { 600 .cmd_rcgr = 0x66004, 601 .mnd_width = 16, 602 .hid_width = 5, 603 .parent_map = gcc_parent_map_1, 604 .freq_tbl = ftbl_gcc_gp1_clk_src, 605 .clkr.hw.init = &(const struct clk_init_data) { 606 .name = "gcc_gp3_clk_src", 607 .parent_data = gcc_parent_data_1, 608 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 609 .flags = CLK_SET_RATE_PARENT, 610 .ops = &clk_rcg2_shared_ops, 611 }, 612 }; 613 614 static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = { 615 F(19200000, P_BI_TCXO, 1, 0, 0), 616 { } 617 }; 618 619 static struct clk_rcg2 gcc_pcie_0_aux_clk_src = { 620 .cmd_rcgr = 0x6b074, 621 .mnd_width = 16, 622 .hid_width = 5, 623 .parent_map = gcc_parent_map_4, 624 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 625 .clkr.hw.init = &(const struct clk_init_data) { 626 .name = "gcc_pcie_0_aux_clk_src", 627 .parent_data = gcc_parent_data_4, 628 .num_parents = ARRAY_SIZE(gcc_parent_data_4), 629 .flags = CLK_SET_RATE_PARENT, 630 .ops = &clk_rcg2_shared_ops, 631 }, 632 }; 633 634 static const struct freq_tbl ftbl_gcc_pcie_0_phy_rchng_clk_src[] = { 635 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0), 636 { } 637 }; 638 639 static struct clk_rcg2 gcc_pcie_0_phy_rchng_clk_src = { 640 .cmd_rcgr = 0x6b058, 641 .mnd_width = 0, 642 .hid_width = 5, 643 .parent_map = gcc_parent_map_0, 644 .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src, 645 .clkr.hw.init = &(const struct clk_init_data) { 646 .name = "gcc_pcie_0_phy_rchng_clk_src", 647 .parent_data = gcc_parent_data_0, 648 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 649 .flags = CLK_SET_RATE_PARENT, 650 .ops = &clk_rcg2_shared_ops, 651 }, 652 }; 653 654 static struct clk_rcg2 gcc_pcie_1_aux_clk_src = { 655 .cmd_rcgr = 0x8d07c, 656 .mnd_width = 16, 657 .hid_width = 5, 658 .parent_map = gcc_parent_map_4, 659 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 660 .clkr.hw.init = &(const struct clk_init_data) { 661 .name = "gcc_pcie_1_aux_clk_src", 662 .parent_data = gcc_parent_data_4, 663 .num_parents = ARRAY_SIZE(gcc_parent_data_4), 664 .flags = CLK_SET_RATE_PARENT, 665 .ops = &clk_rcg2_shared_ops, 666 }, 667 }; 668 669 static struct clk_rcg2 gcc_pcie_1_phy_rchng_clk_src = { 670 .cmd_rcgr = 0x8d060, 671 .mnd_width = 0, 672 .hid_width = 5, 673 .parent_map = gcc_parent_map_0, 674 .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src, 675 .clkr.hw.init = &(const struct clk_init_data) { 676 .name = "gcc_pcie_1_phy_rchng_clk_src", 677 .parent_data = gcc_parent_data_0, 678 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 679 .flags = CLK_SET_RATE_PARENT, 680 .ops = &clk_rcg2_shared_ops, 681 }, 682 }; 683 684 static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = { 685 F(60000000, P_GCC_GPLL0_OUT_MAIN, 10, 0, 0), 686 { } 687 }; 688 689 static struct clk_rcg2 gcc_pdm2_clk_src = { 690 .cmd_rcgr = 0x33010, 691 .mnd_width = 0, 692 .hid_width = 5, 693 .parent_map = gcc_parent_map_0, 694 .freq_tbl = ftbl_gcc_pdm2_clk_src, 695 .clkr.hw.init = &(const struct clk_init_data) { 696 .name = "gcc_pdm2_clk_src", 697 .parent_data = gcc_parent_data_0, 698 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 699 .flags = CLK_SET_RATE_PARENT, 700 .ops = &clk_rcg2_shared_ops, 701 }, 702 }; 703 704 static struct clk_rcg2 gcc_qupv3_i2c_s0_clk_src = { 705 .cmd_rcgr = 0x17008, 706 .mnd_width = 0, 707 .hid_width = 5, 708 .parent_map = gcc_parent_map_0, 709 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 710 .clkr.hw.init = &(const struct clk_init_data) { 711 .name = "gcc_qupv3_i2c_s0_clk_src", 712 .parent_data = gcc_parent_data_0, 713 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 714 .flags = CLK_SET_RATE_PARENT, 715 .ops = &clk_rcg2_ops, 716 }, 717 }; 718 719 static struct clk_rcg2 gcc_qupv3_i2c_s1_clk_src = { 720 .cmd_rcgr = 0x17024, 721 .mnd_width = 0, 722 .hid_width = 5, 723 .parent_map = gcc_parent_map_0, 724 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 725 .clkr.hw.init = &(const struct clk_init_data) { 726 .name = "gcc_qupv3_i2c_s1_clk_src", 727 .parent_data = gcc_parent_data_0, 728 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 729 .flags = CLK_SET_RATE_PARENT, 730 .ops = &clk_rcg2_ops, 731 }, 732 }; 733 734 static struct clk_rcg2 gcc_qupv3_i2c_s2_clk_src = { 735 .cmd_rcgr = 0x17040, 736 .mnd_width = 0, 737 .hid_width = 5, 738 .parent_map = gcc_parent_map_0, 739 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 740 .clkr.hw.init = &(const struct clk_init_data) { 741 .name = "gcc_qupv3_i2c_s2_clk_src", 742 .parent_data = gcc_parent_data_0, 743 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 744 .flags = CLK_SET_RATE_PARENT, 745 .ops = &clk_rcg2_ops, 746 }, 747 }; 748 749 static struct clk_rcg2 gcc_qupv3_i2c_s3_clk_src = { 750 .cmd_rcgr = 0x1705c, 751 .mnd_width = 0, 752 .hid_width = 5, 753 .parent_map = gcc_parent_map_0, 754 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 755 .clkr.hw.init = &(const struct clk_init_data) { 756 .name = "gcc_qupv3_i2c_s3_clk_src", 757 .parent_data = gcc_parent_data_0, 758 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 759 .flags = CLK_SET_RATE_PARENT, 760 .ops = &clk_rcg2_ops, 761 }, 762 }; 763 764 static struct clk_rcg2 gcc_qupv3_i2c_s4_clk_src = { 765 .cmd_rcgr = 0x17078, 766 .mnd_width = 0, 767 .hid_width = 5, 768 .parent_map = gcc_parent_map_0, 769 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 770 .clkr.hw.init = &(const struct clk_init_data) { 771 .name = "gcc_qupv3_i2c_s4_clk_src", 772 .parent_data = gcc_parent_data_0, 773 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 774 .flags = CLK_SET_RATE_PARENT, 775 .ops = &clk_rcg2_ops, 776 }, 777 }; 778 779 static struct clk_rcg2 gcc_qupv3_i2c_s5_clk_src = { 780 .cmd_rcgr = 0x17094, 781 .mnd_width = 0, 782 .hid_width = 5, 783 .parent_map = gcc_parent_map_0, 784 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 785 .clkr.hw.init = &(const struct clk_init_data) { 786 .name = "gcc_qupv3_i2c_s5_clk_src", 787 .parent_data = gcc_parent_data_0, 788 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 789 .flags = CLK_SET_RATE_PARENT, 790 .ops = &clk_rcg2_ops, 791 }, 792 }; 793 794 static struct clk_rcg2 gcc_qupv3_i2c_s6_clk_src = { 795 .cmd_rcgr = 0x170b0, 796 .mnd_width = 0, 797 .hid_width = 5, 798 .parent_map = gcc_parent_map_0, 799 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 800 .clkr.hw.init = &(const struct clk_init_data) { 801 .name = "gcc_qupv3_i2c_s6_clk_src", 802 .parent_data = gcc_parent_data_0, 803 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 804 .flags = CLK_SET_RATE_PARENT, 805 .ops = &clk_rcg2_ops, 806 }, 807 }; 808 809 static struct clk_rcg2 gcc_qupv3_i2c_s7_clk_src = { 810 .cmd_rcgr = 0x170cc, 811 .mnd_width = 0, 812 .hid_width = 5, 813 .parent_map = gcc_parent_map_0, 814 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 815 .clkr.hw.init = &(const struct clk_init_data) { 816 .name = "gcc_qupv3_i2c_s7_clk_src", 817 .parent_data = gcc_parent_data_0, 818 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 819 .flags = CLK_SET_RATE_PARENT, 820 .ops = &clk_rcg2_ops, 821 }, 822 }; 823 824 static struct clk_rcg2 gcc_qupv3_i2c_s8_clk_src = { 825 .cmd_rcgr = 0x170e8, 826 .mnd_width = 0, 827 .hid_width = 5, 828 .parent_map = gcc_parent_map_0, 829 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 830 .clkr.hw.init = &(const struct clk_init_data) { 831 .name = "gcc_qupv3_i2c_s8_clk_src", 832 .parent_data = gcc_parent_data_0, 833 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 834 .flags = CLK_SET_RATE_PARENT, 835 .ops = &clk_rcg2_ops, 836 }, 837 }; 838 839 static struct clk_rcg2 gcc_qupv3_i2c_s9_clk_src = { 840 .cmd_rcgr = 0x17104, 841 .mnd_width = 0, 842 .hid_width = 5, 843 .parent_map = gcc_parent_map_0, 844 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 845 .clkr.hw.init = &(const struct clk_init_data) { 846 .name = "gcc_qupv3_i2c_s9_clk_src", 847 .parent_data = gcc_parent_data_0, 848 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 849 .flags = CLK_SET_RATE_PARENT, 850 .ops = &clk_rcg2_ops, 851 }, 852 }; 853 854 static const struct freq_tbl ftbl_gcc_qupv3_wrap1_qspi_ref_clk_src[] = { 855 F(150000000, P_GCC_GPLL0_OUT_EVEN, 2, 0, 0), 856 F(240000000, P_GCC_GPLL0_OUT_MAIN, 2.5, 0, 0), 857 { } 858 }; 859 860 static struct clk_init_data gcc_qupv3_wrap1_qspi_ref_clk_src_init = { 861 .name = "gcc_qupv3_wrap1_qspi_ref_clk_src", 862 .parent_data = gcc_parent_data_0, 863 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 864 .flags = CLK_SET_RATE_PARENT, 865 .ops = &clk_rcg2_ops, 866 }; 867 868 static struct clk_rcg2 gcc_qupv3_wrap1_qspi_ref_clk_src = { 869 .cmd_rcgr = 0x188a0, 870 .mnd_width = 16, 871 .hid_width = 5, 872 .parent_map = gcc_parent_map_0, 873 .freq_tbl = ftbl_gcc_qupv3_wrap1_qspi_ref_clk_src, 874 .clkr.hw.init = &gcc_qupv3_wrap1_qspi_ref_clk_src_init, 875 }; 876 877 static const struct freq_tbl ftbl_gcc_qupv3_wrap1_s0_clk_src[] = { 878 F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625), 879 F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625), 880 F(19200000, P_BI_TCXO, 1, 0, 0), 881 F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625), 882 F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75), 883 F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25), 884 F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75), 885 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), 886 F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15), 887 F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25), 888 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 889 F(102400000, P_GCC_GPLL0_OUT_EVEN, 1, 128, 375), 890 F(112000000, P_GCC_GPLL0_OUT_EVEN, 1, 28, 75), 891 F(117964800, P_GCC_GPLL0_OUT_EVEN, 1, 6144, 15625), 892 F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0), 893 { } 894 }; 895 896 static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = { 897 .name = "gcc_qupv3_wrap1_s0_clk_src", 898 .parent_data = gcc_parent_data_0, 899 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 900 .flags = CLK_SET_RATE_PARENT, 901 .ops = &clk_rcg2_ops, 902 }; 903 904 static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = { 905 .cmd_rcgr = 0x18010, 906 .mnd_width = 16, 907 .hid_width = 5, 908 .parent_map = gcc_parent_map_0, 909 .freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src, 910 .clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init, 911 }; 912 913 static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = { 914 .name = "gcc_qupv3_wrap1_s1_clk_src", 915 .parent_data = gcc_parent_data_0, 916 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 917 .flags = CLK_SET_RATE_PARENT, 918 .ops = &clk_rcg2_ops, 919 }; 920 921 static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = { 922 .cmd_rcgr = 0x18148, 923 .mnd_width = 16, 924 .hid_width = 5, 925 .parent_map = gcc_parent_map_0, 926 .freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src, 927 .clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init, 928 }; 929 930 static const struct freq_tbl ftbl_gcc_qupv3_wrap1_s3_clk_src[] = { 931 F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625), 932 F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625), 933 F(19200000, P_BI_TCXO, 1, 0, 0), 934 F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625), 935 F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75), 936 F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25), 937 F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75), 938 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), 939 F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15), 940 F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25), 941 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 942 { } 943 }; 944 945 static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = { 946 .name = "gcc_qupv3_wrap1_s3_clk_src", 947 .parent_data = gcc_parent_data_0, 948 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 949 .flags = CLK_SET_RATE_PARENT, 950 .ops = &clk_rcg2_ops, 951 }; 952 953 static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = { 954 .cmd_rcgr = 0x18290, 955 .mnd_width = 16, 956 .hid_width = 5, 957 .parent_map = gcc_parent_map_0, 958 .freq_tbl = ftbl_gcc_qupv3_wrap1_s3_clk_src, 959 .clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init, 960 }; 961 962 static const struct freq_tbl ftbl_gcc_qupv3_wrap1_s4_clk_src[] = { 963 F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625), 964 F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625), 965 F(19200000, P_BI_TCXO, 1, 0, 0), 966 F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625), 967 F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75), 968 F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25), 969 F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75), 970 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), 971 F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15), 972 F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25), 973 F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0), 974 { } 975 }; 976 977 static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = { 978 .name = "gcc_qupv3_wrap1_s4_clk_src", 979 .parent_data = gcc_parent_data_0, 980 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 981 .flags = CLK_SET_RATE_PARENT, 982 .ops = &clk_rcg2_ops, 983 }; 984 985 static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = { 986 .cmd_rcgr = 0x183c8, 987 .mnd_width = 16, 988 .hid_width = 5, 989 .parent_map = gcc_parent_map_0, 990 .freq_tbl = ftbl_gcc_qupv3_wrap1_s4_clk_src, 991 .clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init, 992 }; 993 994 static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = { 995 .name = "gcc_qupv3_wrap1_s5_clk_src", 996 .parent_data = gcc_parent_data_0, 997 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 998 .flags = CLK_SET_RATE_PARENT, 999 .ops = &clk_rcg2_ops, 1000 }; 1001 1002 static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = { 1003 .cmd_rcgr = 0x18500, 1004 .mnd_width = 16, 1005 .hid_width = 5, 1006 .parent_map = gcc_parent_map_0, 1007 .freq_tbl = ftbl_gcc_qupv3_wrap1_s3_clk_src, 1008 .clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init, 1009 }; 1010 1011 static struct clk_init_data gcc_qupv3_wrap1_s6_clk_src_init = { 1012 .name = "gcc_qupv3_wrap1_s6_clk_src", 1013 .parent_data = gcc_parent_data_0, 1014 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1015 .flags = CLK_SET_RATE_PARENT, 1016 .ops = &clk_rcg2_ops, 1017 }; 1018 1019 static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = { 1020 .cmd_rcgr = 0x18638, 1021 .mnd_width = 16, 1022 .hid_width = 5, 1023 .parent_map = gcc_parent_map_0, 1024 .freq_tbl = ftbl_gcc_qupv3_wrap1_s4_clk_src, 1025 .clkr.hw.init = &gcc_qupv3_wrap1_s6_clk_src_init, 1026 }; 1027 1028 static struct clk_init_data gcc_qupv3_wrap1_s7_clk_src_init = { 1029 .name = "gcc_qupv3_wrap1_s7_clk_src", 1030 .parent_data = gcc_parent_data_0, 1031 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1032 .flags = CLK_SET_RATE_PARENT, 1033 .ops = &clk_rcg2_ops, 1034 }; 1035 1036 static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src = { 1037 .cmd_rcgr = 0x18770, 1038 .mnd_width = 16, 1039 .hid_width = 5, 1040 .parent_map = gcc_parent_map_0, 1041 .freq_tbl = ftbl_gcc_qupv3_wrap1_s3_clk_src, 1042 .clkr.hw.init = &gcc_qupv3_wrap1_s7_clk_src_init, 1043 }; 1044 1045 static const struct freq_tbl ftbl_gcc_qupv3_wrap2_ibi_ctrl_0_clk_src[] = { 1046 F(37500000, P_GCC_GPLL0_OUT_EVEN, 8, 0, 0), 1047 { } 1048 }; 1049 1050 static struct clk_rcg2 gcc_qupv3_wrap2_ibi_ctrl_0_clk_src = { 1051 .cmd_rcgr = 0x1e9d4, 1052 .mnd_width = 0, 1053 .hid_width = 5, 1054 .parent_map = gcc_parent_map_2, 1055 .freq_tbl = ftbl_gcc_qupv3_wrap2_ibi_ctrl_0_clk_src, 1056 .clkr.hw.init = &(const struct clk_init_data) { 1057 .name = "gcc_qupv3_wrap2_ibi_ctrl_0_clk_src", 1058 .parent_data = gcc_parent_data_2, 1059 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 1060 .flags = CLK_SET_RATE_PARENT, 1061 .ops = &clk_rcg2_ops, 1062 }, 1063 }; 1064 1065 static struct clk_init_data gcc_qupv3_wrap2_s0_clk_src_init = { 1066 .name = "gcc_qupv3_wrap2_s0_clk_src", 1067 .parent_data = gcc_parent_data_0, 1068 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1069 .flags = CLK_SET_RATE_PARENT, 1070 .ops = &clk_rcg2_ops, 1071 }; 1072 1073 static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = { 1074 .cmd_rcgr = 0x1e010, 1075 .mnd_width = 16, 1076 .hid_width = 5, 1077 .parent_map = gcc_parent_map_0, 1078 .freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src, 1079 .clkr.hw.init = &gcc_qupv3_wrap2_s0_clk_src_init, 1080 }; 1081 1082 static struct clk_init_data gcc_qupv3_wrap2_s1_clk_src_init = { 1083 .name = "gcc_qupv3_wrap2_s1_clk_src", 1084 .parent_data = gcc_parent_data_0, 1085 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1086 .flags = CLK_SET_RATE_PARENT, 1087 .ops = &clk_rcg2_ops, 1088 }; 1089 1090 static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = { 1091 .cmd_rcgr = 0x1e148, 1092 .mnd_width = 16, 1093 .hid_width = 5, 1094 .parent_map = gcc_parent_map_0, 1095 .freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src, 1096 .clkr.hw.init = &gcc_qupv3_wrap2_s1_clk_src_init, 1097 }; 1098 1099 static struct clk_init_data gcc_qupv3_wrap2_s2_clk_src_init = { 1100 .name = "gcc_qupv3_wrap2_s2_clk_src", 1101 .parent_data = gcc_parent_data_0, 1102 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1103 .flags = CLK_SET_RATE_PARENT, 1104 .ops = &clk_rcg2_ops, 1105 }; 1106 1107 static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = { 1108 .cmd_rcgr = 0x1e280, 1109 .mnd_width = 16, 1110 .hid_width = 5, 1111 .parent_map = gcc_parent_map_0, 1112 .freq_tbl = ftbl_gcc_qupv3_wrap1_s4_clk_src, 1113 .clkr.hw.init = &gcc_qupv3_wrap2_s2_clk_src_init, 1114 }; 1115 1116 static struct clk_init_data gcc_qupv3_wrap2_s3_clk_src_init = { 1117 .name = "gcc_qupv3_wrap2_s3_clk_src", 1118 .parent_data = gcc_parent_data_0, 1119 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1120 .flags = CLK_SET_RATE_PARENT, 1121 .ops = &clk_rcg2_ops, 1122 }; 1123 1124 static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = { 1125 .cmd_rcgr = 0x1e3b8, 1126 .mnd_width = 16, 1127 .hid_width = 5, 1128 .parent_map = gcc_parent_map_0, 1129 .freq_tbl = ftbl_gcc_qupv3_wrap1_s4_clk_src, 1130 .clkr.hw.init = &gcc_qupv3_wrap2_s3_clk_src_init, 1131 }; 1132 1133 static struct clk_init_data gcc_qupv3_wrap2_s4_clk_src_init = { 1134 .name = "gcc_qupv3_wrap2_s4_clk_src", 1135 .parent_data = gcc_parent_data_0, 1136 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1137 .flags = CLK_SET_RATE_PARENT, 1138 .ops = &clk_rcg2_ops, 1139 }; 1140 1141 static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = { 1142 .cmd_rcgr = 0x1e4f0, 1143 .mnd_width = 16, 1144 .hid_width = 5, 1145 .parent_map = gcc_parent_map_0, 1146 .freq_tbl = ftbl_gcc_qupv3_wrap1_s3_clk_src, 1147 .clkr.hw.init = &gcc_qupv3_wrap2_s4_clk_src_init, 1148 }; 1149 1150 static struct clk_init_data gcc_qupv3_wrap2_s5_clk_src_init = { 1151 .name = "gcc_qupv3_wrap2_s5_clk_src", 1152 .parent_data = gcc_parent_data_0, 1153 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1154 .flags = CLK_SET_RATE_PARENT, 1155 .ops = &clk_rcg2_ops, 1156 }; 1157 1158 static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = { 1159 .cmd_rcgr = 0x1e628, 1160 .mnd_width = 16, 1161 .hid_width = 5, 1162 .parent_map = gcc_parent_map_0, 1163 .freq_tbl = ftbl_gcc_qupv3_wrap1_s3_clk_src, 1164 .clkr.hw.init = &gcc_qupv3_wrap2_s5_clk_src_init, 1165 }; 1166 1167 static const struct freq_tbl ftbl_gcc_qupv3_wrap2_s6_clk_src[] = { 1168 F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625), 1169 F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625), 1170 F(19200000, P_BI_TCXO, 1, 0, 0), 1171 F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625), 1172 F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75), 1173 F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25), 1174 F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75), 1175 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), 1176 F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15), 1177 F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25), 1178 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 1179 F(128000000, P_GCC_GPLL0_OUT_MAIN, 1, 16, 75), 1180 { } 1181 }; 1182 1183 static struct clk_init_data gcc_qupv3_wrap2_s6_clk_src_init = { 1184 .name = "gcc_qupv3_wrap2_s6_clk_src", 1185 .parent_data = gcc_parent_data_10, 1186 .num_parents = ARRAY_SIZE(gcc_parent_data_10), 1187 .flags = CLK_SET_RATE_PARENT, 1188 .ops = &clk_rcg2_ops, 1189 }; 1190 1191 static struct clk_rcg2 gcc_qupv3_wrap2_s6_clk_src = { 1192 .cmd_rcgr = 0x1e760, 1193 .mnd_width = 16, 1194 .hid_width = 5, 1195 .parent_map = gcc_parent_map_10, 1196 .freq_tbl = ftbl_gcc_qupv3_wrap2_s6_clk_src, 1197 .clkr.hw.init = &gcc_qupv3_wrap2_s6_clk_src_init, 1198 }; 1199 1200 static struct clk_init_data gcc_qupv3_wrap2_s7_clk_src_init = { 1201 .name = "gcc_qupv3_wrap2_s7_clk_src", 1202 .parent_data = gcc_parent_data_0, 1203 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1204 .flags = CLK_SET_RATE_PARENT, 1205 .ops = &clk_rcg2_ops, 1206 }; 1207 1208 static struct clk_rcg2 gcc_qupv3_wrap2_s7_clk_src = { 1209 .cmd_rcgr = 0x1e898, 1210 .mnd_width = 16, 1211 .hid_width = 5, 1212 .parent_map = gcc_parent_map_0, 1213 .freq_tbl = ftbl_gcc_qupv3_wrap1_s3_clk_src, 1214 .clkr.hw.init = &gcc_qupv3_wrap2_s7_clk_src_init, 1215 }; 1216 1217 static const struct freq_tbl ftbl_gcc_qupv3_wrap3_qspi_ref_clk_src[] = { 1218 F(300000000, P_GCC_GPLL0_OUT_EVEN, 1, 0, 0), 1219 F(400000000, P_GCC_GPLL0_OUT_MAIN, 1.5, 0, 0), 1220 { } 1221 }; 1222 1223 static struct clk_init_data gcc_qupv3_wrap3_qspi_ref_clk_src_init = { 1224 .name = "gcc_qupv3_wrap3_qspi_ref_clk_src", 1225 .parent_data = gcc_parent_data_0, 1226 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1227 .flags = CLK_SET_RATE_PARENT, 1228 .ops = &clk_rcg2_ops, 1229 }; 1230 1231 static struct clk_rcg2 gcc_qupv3_wrap3_qspi_ref_clk_src = { 1232 .cmd_rcgr = 0x19018, 1233 .mnd_width = 16, 1234 .hid_width = 5, 1235 .parent_map = gcc_parent_map_0, 1236 .freq_tbl = ftbl_gcc_qupv3_wrap3_qspi_ref_clk_src, 1237 .clkr.hw.init = &gcc_qupv3_wrap3_qspi_ref_clk_src_init, 1238 }; 1239 1240 static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = { 1241 F(400000, P_BI_TCXO, 12, 1, 4), 1242 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0), 1243 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0), 1244 F(202000000, P_GCC_GPLL9_OUT_MAIN, 4, 0, 0), 1245 { } 1246 }; 1247 1248 static struct clk_rcg2 gcc_sdcc2_apps_clk_src = { 1249 .cmd_rcgr = 0x14018, 1250 .mnd_width = 8, 1251 .hid_width = 5, 1252 .parent_map = gcc_parent_map_11, 1253 .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src, 1254 .clkr.hw.init = &(const struct clk_init_data) { 1255 .name = "gcc_sdcc2_apps_clk_src", 1256 .parent_data = gcc_parent_data_11, 1257 .num_parents = ARRAY_SIZE(gcc_parent_data_11), 1258 .flags = CLK_SET_RATE_PARENT, 1259 .ops = &clk_rcg2_shared_floor_ops, 1260 }, 1261 }; 1262 1263 static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_src[] = { 1264 F(400000, P_BI_TCXO, 12, 1, 4), 1265 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0), 1266 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), 1267 { } 1268 }; 1269 1270 static struct clk_rcg2 gcc_sdcc4_apps_clk_src = { 1271 .cmd_rcgr = 0x16018, 1272 .mnd_width = 8, 1273 .hid_width = 5, 1274 .parent_map = gcc_parent_map_0, 1275 .freq_tbl = ftbl_gcc_sdcc4_apps_clk_src, 1276 .clkr.hw.init = &(const struct clk_init_data) { 1277 .name = "gcc_sdcc4_apps_clk_src", 1278 .parent_data = gcc_parent_data_0, 1279 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1280 .flags = CLK_SET_RATE_PARENT, 1281 .ops = &clk_rcg2_shared_floor_ops, 1282 }, 1283 }; 1284 1285 static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = { 1286 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0), 1287 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0), 1288 F(201500000, P_GCC_GPLL4_OUT_MAIN, 4, 0, 0), 1289 F(403000000, P_GCC_GPLL4_OUT_MAIN, 2, 0, 0), 1290 { } 1291 }; 1292 1293 static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = { 1294 .cmd_rcgr = 0x77030, 1295 .mnd_width = 8, 1296 .hid_width = 5, 1297 .parent_map = gcc_parent_map_3, 1298 .freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src, 1299 .clkr.hw.init = &(const struct clk_init_data) { 1300 .name = "gcc_ufs_phy_axi_clk_src", 1301 .parent_data = gcc_parent_data_3, 1302 .num_parents = ARRAY_SIZE(gcc_parent_data_3), 1303 .flags = CLK_SET_RATE_PARENT, 1304 .ops = &clk_rcg2_shared_ops, 1305 }, 1306 }; 1307 1308 static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = { 1309 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0), 1310 F(201500000, P_GCC_GPLL4_OUT_MAIN, 4, 0, 0), 1311 F(403000000, P_GCC_GPLL4_OUT_MAIN, 2, 0, 0), 1312 { } 1313 }; 1314 1315 static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = { 1316 .cmd_rcgr = 0x77080, 1317 .mnd_width = 0, 1318 .hid_width = 5, 1319 .parent_map = gcc_parent_map_3, 1320 .freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src, 1321 .clkr.hw.init = &(const struct clk_init_data) { 1322 .name = "gcc_ufs_phy_ice_core_clk_src", 1323 .parent_data = gcc_parent_data_3, 1324 .num_parents = ARRAY_SIZE(gcc_parent_data_3), 1325 .flags = CLK_SET_RATE_PARENT, 1326 .ops = &clk_rcg2_shared_ops, 1327 }, 1328 }; 1329 1330 static const struct freq_tbl ftbl_gcc_ufs_phy_phy_aux_clk_src[] = { 1331 F(9600000, P_BI_TCXO, 2, 0, 0), 1332 F(19200000, P_BI_TCXO, 1, 0, 0), 1333 { } 1334 }; 1335 1336 static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = { 1337 .cmd_rcgr = 0x770b4, 1338 .mnd_width = 0, 1339 .hid_width = 5, 1340 .parent_map = gcc_parent_map_5, 1341 .freq_tbl = ftbl_gcc_ufs_phy_phy_aux_clk_src, 1342 .clkr.hw.init = &(const struct clk_init_data) { 1343 .name = "gcc_ufs_phy_phy_aux_clk_src", 1344 .parent_data = gcc_parent_data_5, 1345 .num_parents = ARRAY_SIZE(gcc_parent_data_5), 1346 .flags = CLK_SET_RATE_PARENT, 1347 .ops = &clk_rcg2_shared_ops, 1348 }, 1349 }; 1350 1351 static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = { 1352 .cmd_rcgr = 0x77098, 1353 .mnd_width = 0, 1354 .hid_width = 5, 1355 .parent_map = gcc_parent_map_3, 1356 .freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src, 1357 .clkr.hw.init = &(const struct clk_init_data) { 1358 .name = "gcc_ufs_phy_unipro_core_clk_src", 1359 .parent_data = gcc_parent_data_3, 1360 .num_parents = ARRAY_SIZE(gcc_parent_data_3), 1361 .flags = CLK_SET_RATE_PARENT, 1362 .ops = &clk_rcg2_shared_ops, 1363 }, 1364 }; 1365 1366 static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = { 1367 F(66666667, P_GCC_GPLL0_OUT_EVEN, 4.5, 0, 0), 1368 F(133333333, P_GCC_GPLL0_OUT_MAIN, 4.5, 0, 0), 1369 F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0), 1370 F(240000000, P_GCC_GPLL0_OUT_MAIN, 2.5, 0, 0), 1371 { } 1372 }; 1373 1374 static struct clk_rcg2 gcc_usb30_prim_master_clk_src = { 1375 .cmd_rcgr = 0x3902c, 1376 .mnd_width = 8, 1377 .hid_width = 5, 1378 .parent_map = gcc_parent_map_0, 1379 .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src, 1380 .clkr.hw.init = &(const struct clk_init_data) { 1381 .name = "gcc_usb30_prim_master_clk_src", 1382 .parent_data = gcc_parent_data_0, 1383 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1384 .flags = CLK_SET_RATE_PARENT, 1385 .ops = &clk_rcg2_shared_ops, 1386 }, 1387 }; 1388 1389 static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = { 1390 .cmd_rcgr = 0x39044, 1391 .mnd_width = 0, 1392 .hid_width = 5, 1393 .parent_map = gcc_parent_map_0, 1394 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 1395 .clkr.hw.init = &(const struct clk_init_data) { 1396 .name = "gcc_usb30_prim_mock_utmi_clk_src", 1397 .parent_data = gcc_parent_data_0, 1398 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1399 .flags = CLK_SET_RATE_PARENT, 1400 .ops = &clk_rcg2_shared_ops, 1401 }, 1402 }; 1403 1404 static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = { 1405 .cmd_rcgr = 0x39070, 1406 .mnd_width = 0, 1407 .hid_width = 5, 1408 .parent_map = gcc_parent_map_4, 1409 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 1410 .clkr.hw.init = &(const struct clk_init_data) { 1411 .name = "gcc_usb3_prim_phy_aux_clk_src", 1412 .parent_data = gcc_parent_data_4, 1413 .num_parents = ARRAY_SIZE(gcc_parent_data_4), 1414 .flags = CLK_SET_RATE_PARENT, 1415 .ops = &clk_rcg2_shared_ops, 1416 }, 1417 }; 1418 1419 static struct clk_regmap_div gcc_qupv3_wrap1_s2_clk_src = { 1420 .reg = 0x18280, 1421 .shift = 0, 1422 .width = 4, 1423 .clkr.hw.init = &(const struct clk_init_data) { 1424 .name = "gcc_qupv3_wrap1_s2_clk_src", 1425 .parent_hws = (const struct clk_hw*[]) { 1426 &gcc_qupv3_wrap1_qspi_ref_clk_src.clkr.hw, 1427 }, 1428 .num_parents = 1, 1429 .flags = CLK_SET_RATE_PARENT, 1430 .ops = &clk_regmap_div_ro_ops, 1431 }, 1432 }; 1433 1434 static struct clk_regmap_div gcc_qupv3_wrap3_s0_clk_src = { 1435 .reg = 0x19010, 1436 .shift = 0, 1437 .width = 4, 1438 .clkr.hw.init = &(const struct clk_init_data) { 1439 .name = "gcc_qupv3_wrap3_s0_clk_src", 1440 .parent_hws = (const struct clk_hw*[]) { 1441 &gcc_qupv3_wrap3_qspi_ref_clk_src.clkr.hw, 1442 }, 1443 .num_parents = 1, 1444 .flags = CLK_SET_RATE_PARENT, 1445 .ops = &clk_regmap_div_ro_ops, 1446 }, 1447 }; 1448 1449 static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv_clk_src = { 1450 .reg = 0x3905c, 1451 .shift = 0, 1452 .width = 4, 1453 .clkr.hw.init = &(const struct clk_init_data) { 1454 .name = "gcc_usb30_prim_mock_utmi_postdiv_clk_src", 1455 .parent_hws = (const struct clk_hw*[]) { 1456 &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw, 1457 }, 1458 .num_parents = 1, 1459 .flags = CLK_SET_RATE_PARENT, 1460 .ops = &clk_regmap_div_ro_ops, 1461 }, 1462 }; 1463 1464 static struct clk_branch gcc_aggre_noc_pcie_axi_clk = { 1465 .halt_reg = 0x10064, 1466 .halt_check = BRANCH_HALT_SKIP, 1467 .hwcg_reg = 0x10064, 1468 .hwcg_bit = 1, 1469 .clkr = { 1470 .enable_reg = 0x52000, 1471 .enable_mask = BIT(12), 1472 .hw.init = &(const struct clk_init_data) { 1473 .name = "gcc_aggre_noc_pcie_axi_clk", 1474 .ops = &clk_branch2_ops, 1475 }, 1476 }, 1477 }; 1478 1479 static struct clk_branch gcc_aggre_ufs_phy_axi_clk = { 1480 .halt_reg = 0x770e4, 1481 .halt_check = BRANCH_HALT_VOTED, 1482 .hwcg_reg = 0x770e4, 1483 .hwcg_bit = 1, 1484 .clkr = { 1485 .enable_reg = 0x770e4, 1486 .enable_mask = BIT(0), 1487 .hw.init = &(const struct clk_init_data) { 1488 .name = "gcc_aggre_ufs_phy_axi_clk", 1489 .parent_hws = (const struct clk_hw*[]) { 1490 &gcc_ufs_phy_axi_clk_src.clkr.hw, 1491 }, 1492 .num_parents = 1, 1493 .flags = CLK_SET_RATE_PARENT, 1494 .ops = &clk_branch2_ops, 1495 }, 1496 }, 1497 }; 1498 1499 static struct clk_branch gcc_aggre_ufs_phy_axi_hw_ctl_clk = { 1500 .halt_reg = 0x770e4, 1501 .halt_check = BRANCH_HALT_VOTED, 1502 .hwcg_reg = 0x770e4, 1503 .hwcg_bit = 1, 1504 .clkr = { 1505 .enable_reg = 0x770e4, 1506 .enable_mask = BIT(1), 1507 .hw.init = &(const struct clk_init_data) { 1508 .name = "gcc_aggre_ufs_phy_axi_hw_ctl_clk", 1509 .parent_hws = (const struct clk_hw*[]) { 1510 &gcc_ufs_phy_axi_clk_src.clkr.hw, 1511 }, 1512 .num_parents = 1, 1513 .flags = CLK_SET_RATE_PARENT, 1514 .ops = &clk_branch2_ops, 1515 }, 1516 }, 1517 }; 1518 1519 static struct clk_branch gcc_aggre_usb3_prim_axi_clk = { 1520 .halt_reg = 0x3908c, 1521 .halt_check = BRANCH_HALT_VOTED, 1522 .hwcg_reg = 0x3908c, 1523 .hwcg_bit = 1, 1524 .clkr = { 1525 .enable_reg = 0x3908c, 1526 .enable_mask = BIT(0), 1527 .hw.init = &(const struct clk_init_data) { 1528 .name = "gcc_aggre_usb3_prim_axi_clk", 1529 .parent_hws = (const struct clk_hw*[]) { 1530 &gcc_usb30_prim_master_clk_src.clkr.hw, 1531 }, 1532 .num_parents = 1, 1533 .flags = CLK_SET_RATE_PARENT, 1534 .ops = &clk_branch2_ops, 1535 }, 1536 }, 1537 }; 1538 1539 static struct clk_branch gcc_boot_rom_ahb_clk = { 1540 .halt_reg = 0x38004, 1541 .halt_check = BRANCH_HALT_VOTED, 1542 .hwcg_reg = 0x38004, 1543 .hwcg_bit = 1, 1544 .clkr = { 1545 .enable_reg = 0x52000, 1546 .enable_mask = BIT(10), 1547 .hw.init = &(const struct clk_init_data) { 1548 .name = "gcc_boot_rom_ahb_clk", 1549 .ops = &clk_branch2_ops, 1550 }, 1551 }, 1552 }; 1553 1554 static struct clk_branch gcc_camera_hf_axi_clk = { 1555 .halt_reg = 0x26010, 1556 .halt_check = BRANCH_HALT_SKIP, 1557 .hwcg_reg = 0x26010, 1558 .hwcg_bit = 1, 1559 .clkr = { 1560 .enable_reg = 0x26010, 1561 .enable_mask = BIT(0), 1562 .hw.init = &(const struct clk_init_data) { 1563 .name = "gcc_camera_hf_axi_clk", 1564 .ops = &clk_branch2_ops, 1565 }, 1566 }, 1567 }; 1568 1569 static struct clk_branch gcc_camera_sf_axi_clk = { 1570 .halt_reg = 0x2601c, 1571 .halt_check = BRANCH_HALT_SKIP, 1572 .hwcg_reg = 0x2601c, 1573 .hwcg_bit = 1, 1574 .clkr = { 1575 .enable_reg = 0x2601c, 1576 .enable_mask = BIT(0), 1577 .hw.init = &(const struct clk_init_data) { 1578 .name = "gcc_camera_sf_axi_clk", 1579 .ops = &clk_branch2_ops, 1580 }, 1581 }, 1582 }; 1583 1584 static struct clk_branch gcc_cfg_noc_pcie_anoc_ahb_clk = { 1585 .halt_reg = 0x10050, 1586 .halt_check = BRANCH_HALT_SKIP, 1587 .hwcg_reg = 0x10050, 1588 .hwcg_bit = 1, 1589 .clkr = { 1590 .enable_reg = 0x52000, 1591 .enable_mask = BIT(20), 1592 .hw.init = &(const struct clk_init_data) { 1593 .name = "gcc_cfg_noc_pcie_anoc_ahb_clk", 1594 .ops = &clk_branch2_ops, 1595 }, 1596 }, 1597 }; 1598 1599 static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = { 1600 .halt_reg = 0x39088, 1601 .halt_check = BRANCH_HALT_VOTED, 1602 .hwcg_reg = 0x39088, 1603 .hwcg_bit = 1, 1604 .clkr = { 1605 .enable_reg = 0x39088, 1606 .enable_mask = BIT(0), 1607 .hw.init = &(const struct clk_init_data) { 1608 .name = "gcc_cfg_noc_usb3_prim_axi_clk", 1609 .parent_hws = (const struct clk_hw*[]) { 1610 &gcc_usb30_prim_master_clk_src.clkr.hw, 1611 }, 1612 .num_parents = 1, 1613 .flags = CLK_SET_RATE_PARENT, 1614 .ops = &clk_branch2_ops, 1615 }, 1616 }, 1617 }; 1618 1619 static struct clk_branch gcc_cnoc_pcie_sf_axi_clk = { 1620 .halt_reg = 0x10058, 1621 .halt_check = BRANCH_HALT_VOTED, 1622 .hwcg_reg = 0x10058, 1623 .hwcg_bit = 1, 1624 .clkr = { 1625 .enable_reg = 0x52008, 1626 .enable_mask = BIT(6), 1627 .hw.init = &(const struct clk_init_data) { 1628 .name = "gcc_cnoc_pcie_sf_axi_clk", 1629 .ops = &clk_branch2_ops, 1630 }, 1631 }, 1632 }; 1633 1634 static struct clk_branch gcc_ddrss_gpu_axi_clk = { 1635 .halt_reg = 0x71154, 1636 .halt_check = BRANCH_HALT_SKIP, 1637 .hwcg_reg = 0x71154, 1638 .hwcg_bit = 1, 1639 .clkr = { 1640 .enable_reg = 0x71154, 1641 .enable_mask = BIT(0), 1642 .hw.init = &(const struct clk_init_data) { 1643 .name = "gcc_ddrss_gpu_axi_clk", 1644 .ops = &clk_branch2_aon_ops, 1645 }, 1646 }, 1647 }; 1648 1649 static struct clk_branch gcc_ddrss_pcie_sf_qtb_clk = { 1650 .halt_reg = 0x10074, 1651 .halt_check = BRANCH_HALT_SKIP, 1652 .hwcg_reg = 0x10074, 1653 .hwcg_bit = 1, 1654 .clkr = { 1655 .enable_reg = 0x52000, 1656 .enable_mask = BIT(19), 1657 .hw.init = &(const struct clk_init_data) { 1658 .name = "gcc_ddrss_pcie_sf_qtb_clk", 1659 .ops = &clk_branch2_ops, 1660 }, 1661 }, 1662 }; 1663 1664 static struct clk_branch gcc_disp_hf_axi_clk = { 1665 .halt_reg = 0x2700c, 1666 .halt_check = BRANCH_HALT_SKIP, 1667 .hwcg_reg = 0x2700c, 1668 .hwcg_bit = 1, 1669 .clkr = { 1670 .enable_reg = 0x2700c, 1671 .enable_mask = BIT(0), 1672 .hw.init = &(const struct clk_init_data) { 1673 .name = "gcc_disp_hf_axi_clk", 1674 .ops = &clk_branch2_ops, 1675 }, 1676 }, 1677 }; 1678 1679 static struct clk_branch gcc_gp1_clk = { 1680 .halt_reg = 0x64000, 1681 .halt_check = BRANCH_HALT, 1682 .clkr = { 1683 .enable_reg = 0x64000, 1684 .enable_mask = BIT(0), 1685 .hw.init = &(const struct clk_init_data) { 1686 .name = "gcc_gp1_clk", 1687 .parent_hws = (const struct clk_hw*[]) { 1688 &gcc_gp1_clk_src.clkr.hw, 1689 }, 1690 .num_parents = 1, 1691 .flags = CLK_SET_RATE_PARENT, 1692 .ops = &clk_branch2_ops, 1693 }, 1694 }, 1695 }; 1696 1697 static struct clk_branch gcc_gp2_clk = { 1698 .halt_reg = 0x65000, 1699 .halt_check = BRANCH_HALT, 1700 .clkr = { 1701 .enable_reg = 0x65000, 1702 .enable_mask = BIT(0), 1703 .hw.init = &(const struct clk_init_data) { 1704 .name = "gcc_gp2_clk", 1705 .parent_hws = (const struct clk_hw*[]) { 1706 &gcc_gp2_clk_src.clkr.hw, 1707 }, 1708 .num_parents = 1, 1709 .flags = CLK_SET_RATE_PARENT, 1710 .ops = &clk_branch2_ops, 1711 }, 1712 }, 1713 }; 1714 1715 static struct clk_branch gcc_gp3_clk = { 1716 .halt_reg = 0x66000, 1717 .halt_check = BRANCH_HALT, 1718 .clkr = { 1719 .enable_reg = 0x66000, 1720 .enable_mask = BIT(0), 1721 .hw.init = &(const struct clk_init_data) { 1722 .name = "gcc_gp3_clk", 1723 .parent_hws = (const struct clk_hw*[]) { 1724 &gcc_gp3_clk_src.clkr.hw, 1725 }, 1726 .num_parents = 1, 1727 .flags = CLK_SET_RATE_PARENT, 1728 .ops = &clk_branch2_ops, 1729 }, 1730 }, 1731 }; 1732 1733 static struct clk_branch gcc_gpu_gpll0_clk_src = { 1734 .halt_check = BRANCH_HALT_DELAY, 1735 .clkr = { 1736 .enable_reg = 0x52000, 1737 .enable_mask = BIT(15), 1738 .hw.init = &(const struct clk_init_data) { 1739 .name = "gcc_gpu_gpll0_clk_src", 1740 .parent_hws = (const struct clk_hw*[]) { 1741 &gcc_gpll0.clkr.hw, 1742 }, 1743 .num_parents = 1, 1744 .flags = CLK_SET_RATE_PARENT, 1745 .ops = &clk_branch2_ops, 1746 }, 1747 }, 1748 }; 1749 1750 static struct clk_branch gcc_gpu_gpll0_div_clk_src = { 1751 .halt_check = BRANCH_HALT_DELAY, 1752 .clkr = { 1753 .enable_reg = 0x52000, 1754 .enable_mask = BIT(16), 1755 .hw.init = &(const struct clk_init_data) { 1756 .name = "gcc_gpu_gpll0_div_clk_src", 1757 .parent_hws = (const struct clk_hw*[]) { 1758 &gcc_gpll0_out_even.clkr.hw, 1759 }, 1760 .num_parents = 1, 1761 .flags = CLK_SET_RATE_PARENT, 1762 .ops = &clk_branch2_ops, 1763 }, 1764 }, 1765 }; 1766 1767 static struct clk_branch gcc_gpu_memnoc_gfx_clk = { 1768 .halt_reg = 0x71010, 1769 .halt_check = BRANCH_HALT_VOTED, 1770 .hwcg_reg = 0x71010, 1771 .hwcg_bit = 1, 1772 .clkr = { 1773 .enable_reg = 0x71010, 1774 .enable_mask = BIT(0), 1775 .hw.init = &(const struct clk_init_data) { 1776 .name = "gcc_gpu_memnoc_gfx_clk", 1777 .ops = &clk_branch2_ops, 1778 }, 1779 }, 1780 }; 1781 1782 static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = { 1783 .halt_reg = 0x71018, 1784 .halt_check = BRANCH_HALT_DELAY, 1785 .clkr = { 1786 .enable_reg = 0x71018, 1787 .enable_mask = BIT(0), 1788 .hw.init = &(const struct clk_init_data) { 1789 .name = "gcc_gpu_snoc_dvm_gfx_clk", 1790 .ops = &clk_branch2_ops, 1791 }, 1792 }, 1793 }; 1794 1795 static struct clk_branch gcc_pcie_0_aux_clk = { 1796 .halt_reg = 0x6b03c, 1797 .halt_check = BRANCH_HALT_VOTED, 1798 .clkr = { 1799 .enable_reg = 0x52008, 1800 .enable_mask = BIT(3), 1801 .hw.init = &(const struct clk_init_data) { 1802 .name = "gcc_pcie_0_aux_clk", 1803 .parent_hws = (const struct clk_hw*[]) { 1804 &gcc_pcie_0_aux_clk_src.clkr.hw, 1805 }, 1806 .num_parents = 1, 1807 .flags = CLK_SET_RATE_PARENT, 1808 .ops = &clk_branch2_ops, 1809 }, 1810 }, 1811 }; 1812 1813 static struct clk_branch gcc_pcie_0_cfg_ahb_clk = { 1814 .halt_reg = 0x6b038, 1815 .halt_check = BRANCH_HALT_VOTED, 1816 .hwcg_reg = 0x6b038, 1817 .hwcg_bit = 1, 1818 .clkr = { 1819 .enable_reg = 0x52008, 1820 .enable_mask = BIT(2), 1821 .hw.init = &(const struct clk_init_data) { 1822 .name = "gcc_pcie_0_cfg_ahb_clk", 1823 .ops = &clk_branch2_ops, 1824 }, 1825 }, 1826 }; 1827 1828 static struct clk_branch gcc_pcie_0_mstr_axi_clk = { 1829 .halt_reg = 0x6b02c, 1830 .halt_check = BRANCH_HALT_SKIP, 1831 .hwcg_reg = 0x6b02c, 1832 .hwcg_bit = 1, 1833 .clkr = { 1834 .enable_reg = 0x52008, 1835 .enable_mask = BIT(1), 1836 .hw.init = &(const struct clk_init_data) { 1837 .name = "gcc_pcie_0_mstr_axi_clk", 1838 .ops = &clk_branch2_ops, 1839 }, 1840 }, 1841 }; 1842 1843 static struct clk_branch gcc_pcie_0_phy_rchng_clk = { 1844 .halt_reg = 0x6b054, 1845 .halt_check = BRANCH_HALT_VOTED, 1846 .clkr = { 1847 .enable_reg = 0x52000, 1848 .enable_mask = BIT(22), 1849 .hw.init = &(const struct clk_init_data) { 1850 .name = "gcc_pcie_0_phy_rchng_clk", 1851 .parent_hws = (const struct clk_hw*[]) { 1852 &gcc_pcie_0_phy_rchng_clk_src.clkr.hw, 1853 }, 1854 .num_parents = 1, 1855 .flags = CLK_SET_RATE_PARENT, 1856 .ops = &clk_branch2_ops, 1857 }, 1858 }, 1859 }; 1860 1861 static struct clk_branch gcc_pcie_0_pipe_clk = { 1862 .halt_reg = 0x6b048, 1863 .halt_check = BRANCH_HALT_SKIP, 1864 .clkr = { 1865 .enable_reg = 0x52008, 1866 .enable_mask = BIT(4), 1867 .hw.init = &(const struct clk_init_data) { 1868 .name = "gcc_pcie_0_pipe_clk", 1869 .parent_hws = (const struct clk_hw*[]) { 1870 &gcc_pcie_0_pipe_clk_src.clkr.hw, 1871 }, 1872 .num_parents = 1, 1873 .flags = CLK_SET_RATE_PARENT, 1874 .ops = &clk_branch2_ops, 1875 }, 1876 }, 1877 }; 1878 1879 static struct clk_branch gcc_pcie_0_slv_axi_clk = { 1880 .halt_reg = 0x6b020, 1881 .halt_check = BRANCH_HALT_VOTED, 1882 .hwcg_reg = 0x6b020, 1883 .hwcg_bit = 1, 1884 .clkr = { 1885 .enable_reg = 0x52008, 1886 .enable_mask = BIT(0), 1887 .hw.init = &(const struct clk_init_data) { 1888 .name = "gcc_pcie_0_slv_axi_clk", 1889 .ops = &clk_branch2_ops, 1890 }, 1891 }, 1892 }; 1893 1894 static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = { 1895 .halt_reg = 0x6b01c, 1896 .halt_check = BRANCH_HALT_VOTED, 1897 .clkr = { 1898 .enable_reg = 0x52008, 1899 .enable_mask = BIT(5), 1900 .hw.init = &(const struct clk_init_data) { 1901 .name = "gcc_pcie_0_slv_q2a_axi_clk", 1902 .ops = &clk_branch2_ops, 1903 }, 1904 }, 1905 }; 1906 1907 static struct clk_branch gcc_pcie_1_aux_clk = { 1908 .halt_reg = 0x8d038, 1909 .halt_check = BRANCH_HALT_VOTED, 1910 .clkr = { 1911 .enable_reg = 0x52000, 1912 .enable_mask = BIT(29), 1913 .hw.init = &(const struct clk_init_data) { 1914 .name = "gcc_pcie_1_aux_clk", 1915 .parent_hws = (const struct clk_hw*[]) { 1916 &gcc_pcie_1_aux_clk_src.clkr.hw, 1917 }, 1918 .num_parents = 1, 1919 .flags = CLK_SET_RATE_PARENT, 1920 .ops = &clk_branch2_ops, 1921 }, 1922 }, 1923 }; 1924 1925 static struct clk_branch gcc_pcie_1_cfg_ahb_clk = { 1926 .halt_reg = 0x8d034, 1927 .halt_check = BRANCH_HALT_VOTED, 1928 .hwcg_reg = 0x8d034, 1929 .hwcg_bit = 1, 1930 .clkr = { 1931 .enable_reg = 0x52000, 1932 .enable_mask = BIT(28), 1933 .hw.init = &(const struct clk_init_data) { 1934 .name = "gcc_pcie_1_cfg_ahb_clk", 1935 .ops = &clk_branch2_ops, 1936 }, 1937 }, 1938 }; 1939 1940 static struct clk_branch gcc_pcie_1_mstr_axi_clk = { 1941 .halt_reg = 0x8d028, 1942 .halt_check = BRANCH_HALT_SKIP, 1943 .hwcg_reg = 0x8d028, 1944 .hwcg_bit = 1, 1945 .clkr = { 1946 .enable_reg = 0x52000, 1947 .enable_mask = BIT(27), 1948 .hw.init = &(const struct clk_init_data) { 1949 .name = "gcc_pcie_1_mstr_axi_clk", 1950 .ops = &clk_branch2_ops, 1951 }, 1952 }, 1953 }; 1954 1955 static struct clk_branch gcc_pcie_1_phy_aux_clk = { 1956 .halt_reg = 0x8d044, 1957 .halt_check = BRANCH_HALT_VOTED, 1958 .clkr = { 1959 .enable_reg = 0x52000, 1960 .enable_mask = BIT(24), 1961 .hw.init = &(const struct clk_init_data) { 1962 .name = "gcc_pcie_1_phy_aux_clk", 1963 .parent_hws = (const struct clk_hw*[]) { 1964 &gcc_pcie_1_phy_aux_clk_src.clkr.hw, 1965 }, 1966 .num_parents = 1, 1967 .flags = CLK_SET_RATE_PARENT, 1968 .ops = &clk_branch2_ops, 1969 }, 1970 }, 1971 }; 1972 1973 static struct clk_branch gcc_pcie_1_phy_rchng_clk = { 1974 .halt_reg = 0x8d05c, 1975 .halt_check = BRANCH_HALT_VOTED, 1976 .clkr = { 1977 .enable_reg = 0x52000, 1978 .enable_mask = BIT(23), 1979 .hw.init = &(const struct clk_init_data) { 1980 .name = "gcc_pcie_1_phy_rchng_clk", 1981 .parent_hws = (const struct clk_hw*[]) { 1982 &gcc_pcie_1_phy_rchng_clk_src.clkr.hw, 1983 }, 1984 .num_parents = 1, 1985 .flags = CLK_SET_RATE_PARENT, 1986 .ops = &clk_branch2_ops, 1987 }, 1988 }, 1989 }; 1990 1991 static struct clk_branch gcc_pcie_1_pipe_clk = { 1992 .halt_reg = 0x8d050, 1993 .halt_check = BRANCH_HALT_SKIP, 1994 .clkr = { 1995 .enable_reg = 0x52000, 1996 .enable_mask = BIT(30), 1997 .hw.init = &(const struct clk_init_data) { 1998 .name = "gcc_pcie_1_pipe_clk", 1999 .parent_hws = (const struct clk_hw*[]) { 2000 &gcc_pcie_1_pipe_clk_src.clkr.hw, 2001 }, 2002 .num_parents = 1, 2003 .flags = CLK_SET_RATE_PARENT, 2004 .ops = &clk_branch2_ops, 2005 }, 2006 }, 2007 }; 2008 2009 static struct clk_branch gcc_pcie_1_slv_axi_clk = { 2010 .halt_reg = 0x8d01c, 2011 .halt_check = BRANCH_HALT_VOTED, 2012 .hwcg_reg = 0x8d01c, 2013 .hwcg_bit = 1, 2014 .clkr = { 2015 .enable_reg = 0x52000, 2016 .enable_mask = BIT(26), 2017 .hw.init = &(const struct clk_init_data) { 2018 .name = "gcc_pcie_1_slv_axi_clk", 2019 .ops = &clk_branch2_ops, 2020 }, 2021 }, 2022 }; 2023 2024 static struct clk_branch gcc_pcie_1_slv_q2a_axi_clk = { 2025 .halt_reg = 0x8d018, 2026 .halt_check = BRANCH_HALT_VOTED, 2027 .clkr = { 2028 .enable_reg = 0x52000, 2029 .enable_mask = BIT(25), 2030 .hw.init = &(const struct clk_init_data) { 2031 .name = "gcc_pcie_1_slv_q2a_axi_clk", 2032 .ops = &clk_branch2_ops, 2033 }, 2034 }, 2035 }; 2036 2037 static struct clk_branch gcc_pdm2_clk = { 2038 .halt_reg = 0x3300c, 2039 .halt_check = BRANCH_HALT, 2040 .clkr = { 2041 .enable_reg = 0x3300c, 2042 .enable_mask = BIT(0), 2043 .hw.init = &(const struct clk_init_data) { 2044 .name = "gcc_pdm2_clk", 2045 .parent_hws = (const struct clk_hw*[]) { 2046 &gcc_pdm2_clk_src.clkr.hw, 2047 }, 2048 .num_parents = 1, 2049 .flags = CLK_SET_RATE_PARENT, 2050 .ops = &clk_branch2_ops, 2051 }, 2052 }, 2053 }; 2054 2055 static struct clk_branch gcc_pdm_ahb_clk = { 2056 .halt_reg = 0x33004, 2057 .halt_check = BRANCH_HALT_VOTED, 2058 .hwcg_reg = 0x33004, 2059 .hwcg_bit = 1, 2060 .clkr = { 2061 .enable_reg = 0x33004, 2062 .enable_mask = BIT(0), 2063 .hw.init = &(const struct clk_init_data) { 2064 .name = "gcc_pdm_ahb_clk", 2065 .ops = &clk_branch2_ops, 2066 }, 2067 }, 2068 }; 2069 2070 static struct clk_branch gcc_pdm_xo4_clk = { 2071 .halt_reg = 0x33008, 2072 .halt_check = BRANCH_HALT, 2073 .clkr = { 2074 .enable_reg = 0x33008, 2075 .enable_mask = BIT(0), 2076 .hw.init = &(const struct clk_init_data) { 2077 .name = "gcc_pdm_xo4_clk", 2078 .ops = &clk_branch2_ops, 2079 }, 2080 }, 2081 }; 2082 2083 static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = { 2084 .halt_reg = 0x26008, 2085 .halt_check = BRANCH_HALT_VOTED, 2086 .hwcg_reg = 0x26008, 2087 .hwcg_bit = 1, 2088 .clkr = { 2089 .enable_reg = 0x26008, 2090 .enable_mask = BIT(0), 2091 .hw.init = &(const struct clk_init_data) { 2092 .name = "gcc_qmip_camera_nrt_ahb_clk", 2093 .ops = &clk_branch2_ops, 2094 }, 2095 }, 2096 }; 2097 2098 static struct clk_branch gcc_qmip_camera_rt_ahb_clk = { 2099 .halt_reg = 0x2600c, 2100 .halt_check = BRANCH_HALT_VOTED, 2101 .hwcg_reg = 0x2600c, 2102 .hwcg_bit = 1, 2103 .clkr = { 2104 .enable_reg = 0x2600c, 2105 .enable_mask = BIT(0), 2106 .hw.init = &(const struct clk_init_data) { 2107 .name = "gcc_qmip_camera_rt_ahb_clk", 2108 .ops = &clk_branch2_ops, 2109 }, 2110 }, 2111 }; 2112 2113 static struct clk_branch gcc_qmip_disp_ahb_clk = { 2114 .halt_reg = 0x27008, 2115 .halt_check = BRANCH_HALT_VOTED, 2116 .hwcg_reg = 0x27008, 2117 .hwcg_bit = 1, 2118 .clkr = { 2119 .enable_reg = 0x27008, 2120 .enable_mask = BIT(0), 2121 .hw.init = &(const struct clk_init_data) { 2122 .name = "gcc_qmip_disp_ahb_clk", 2123 .ops = &clk_branch2_ops, 2124 }, 2125 }, 2126 }; 2127 2128 static struct clk_branch gcc_qmip_gpu_ahb_clk = { 2129 .halt_reg = 0x71008, 2130 .halt_check = BRANCH_HALT_VOTED, 2131 .hwcg_reg = 0x71008, 2132 .hwcg_bit = 1, 2133 .clkr = { 2134 .enable_reg = 0x71008, 2135 .enable_mask = BIT(0), 2136 .hw.init = &(const struct clk_init_data) { 2137 .name = "gcc_qmip_gpu_ahb_clk", 2138 .ops = &clk_branch2_ops, 2139 }, 2140 }, 2141 }; 2142 2143 static struct clk_branch gcc_qmip_pcie_ahb_clk = { 2144 .halt_reg = 0x6b018, 2145 .halt_check = BRANCH_HALT_VOTED, 2146 .hwcg_reg = 0x6b018, 2147 .hwcg_bit = 1, 2148 .clkr = { 2149 .enable_reg = 0x52000, 2150 .enable_mask = BIT(11), 2151 .hw.init = &(const struct clk_init_data) { 2152 .name = "gcc_qmip_pcie_ahb_clk", 2153 .ops = &clk_branch2_ops, 2154 }, 2155 }, 2156 }; 2157 2158 static struct clk_branch gcc_qmip_video_cv_cpu_ahb_clk = { 2159 .halt_reg = 0x32014, 2160 .halt_check = BRANCH_HALT_VOTED, 2161 .hwcg_reg = 0x32014, 2162 .hwcg_bit = 1, 2163 .clkr = { 2164 .enable_reg = 0x32014, 2165 .enable_mask = BIT(0), 2166 .hw.init = &(const struct clk_init_data) { 2167 .name = "gcc_qmip_video_cv_cpu_ahb_clk", 2168 .ops = &clk_branch2_ops, 2169 }, 2170 }, 2171 }; 2172 2173 static struct clk_branch gcc_qmip_video_cvp_ahb_clk = { 2174 .halt_reg = 0x32008, 2175 .halt_check = BRANCH_HALT_VOTED, 2176 .hwcg_reg = 0x32008, 2177 .hwcg_bit = 1, 2178 .clkr = { 2179 .enable_reg = 0x32008, 2180 .enable_mask = BIT(0), 2181 .hw.init = &(const struct clk_init_data) { 2182 .name = "gcc_qmip_video_cvp_ahb_clk", 2183 .ops = &clk_branch2_ops, 2184 }, 2185 }, 2186 }; 2187 2188 static struct clk_branch gcc_qmip_video_v_cpu_ahb_clk = { 2189 .halt_reg = 0x32010, 2190 .halt_check = BRANCH_HALT_VOTED, 2191 .hwcg_reg = 0x32010, 2192 .hwcg_bit = 1, 2193 .clkr = { 2194 .enable_reg = 0x32010, 2195 .enable_mask = BIT(0), 2196 .hw.init = &(const struct clk_init_data) { 2197 .name = "gcc_qmip_video_v_cpu_ahb_clk", 2198 .ops = &clk_branch2_ops, 2199 }, 2200 }, 2201 }; 2202 2203 static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = { 2204 .halt_reg = 0x3200c, 2205 .halt_check = BRANCH_HALT_VOTED, 2206 .hwcg_reg = 0x3200c, 2207 .hwcg_bit = 1, 2208 .clkr = { 2209 .enable_reg = 0x3200c, 2210 .enable_mask = BIT(0), 2211 .hw.init = &(const struct clk_init_data) { 2212 .name = "gcc_qmip_video_vcodec_ahb_clk", 2213 .ops = &clk_branch2_ops, 2214 }, 2215 }, 2216 }; 2217 2218 static struct clk_branch gcc_qupv3_i2c_core_clk = { 2219 .halt_reg = 0x23004, 2220 .halt_check = BRANCH_HALT_VOTED, 2221 .clkr = { 2222 .enable_reg = 0x52008, 2223 .enable_mask = BIT(8), 2224 .hw.init = &(const struct clk_init_data) { 2225 .name = "gcc_qupv3_i2c_core_clk", 2226 .ops = &clk_branch2_ops, 2227 }, 2228 }, 2229 }; 2230 2231 static struct clk_branch gcc_qupv3_i2c_s0_clk = { 2232 .halt_reg = 0x17004, 2233 .halt_check = BRANCH_HALT_VOTED, 2234 .clkr = { 2235 .enable_reg = 0x52008, 2236 .enable_mask = BIT(10), 2237 .hw.init = &(const struct clk_init_data) { 2238 .name = "gcc_qupv3_i2c_s0_clk", 2239 .parent_hws = (const struct clk_hw*[]) { 2240 &gcc_qupv3_i2c_s0_clk_src.clkr.hw, 2241 }, 2242 .num_parents = 1, 2243 .flags = CLK_SET_RATE_PARENT, 2244 .ops = &clk_branch2_ops, 2245 }, 2246 }, 2247 }; 2248 2249 static struct clk_branch gcc_qupv3_i2c_s1_clk = { 2250 .halt_reg = 0x17020, 2251 .halt_check = BRANCH_HALT_VOTED, 2252 .clkr = { 2253 .enable_reg = 0x52008, 2254 .enable_mask = BIT(11), 2255 .hw.init = &(const struct clk_init_data) { 2256 .name = "gcc_qupv3_i2c_s1_clk", 2257 .parent_hws = (const struct clk_hw*[]) { 2258 &gcc_qupv3_i2c_s1_clk_src.clkr.hw, 2259 }, 2260 .num_parents = 1, 2261 .flags = CLK_SET_RATE_PARENT, 2262 .ops = &clk_branch2_ops, 2263 }, 2264 }, 2265 }; 2266 2267 static struct clk_branch gcc_qupv3_i2c_s2_clk = { 2268 .halt_reg = 0x1703c, 2269 .halt_check = BRANCH_HALT_VOTED, 2270 .clkr = { 2271 .enable_reg = 0x52008, 2272 .enable_mask = BIT(12), 2273 .hw.init = &(const struct clk_init_data) { 2274 .name = "gcc_qupv3_i2c_s2_clk", 2275 .parent_hws = (const struct clk_hw*[]) { 2276 &gcc_qupv3_i2c_s2_clk_src.clkr.hw, 2277 }, 2278 .num_parents = 1, 2279 .flags = CLK_SET_RATE_PARENT, 2280 .ops = &clk_branch2_ops, 2281 }, 2282 }, 2283 }; 2284 2285 static struct clk_branch gcc_qupv3_i2c_s3_clk = { 2286 .halt_reg = 0x17058, 2287 .halt_check = BRANCH_HALT_VOTED, 2288 .clkr = { 2289 .enable_reg = 0x52008, 2290 .enable_mask = BIT(13), 2291 .hw.init = &(const struct clk_init_data) { 2292 .name = "gcc_qupv3_i2c_s3_clk", 2293 .parent_hws = (const struct clk_hw*[]) { 2294 &gcc_qupv3_i2c_s3_clk_src.clkr.hw, 2295 }, 2296 .num_parents = 1, 2297 .flags = CLK_SET_RATE_PARENT, 2298 .ops = &clk_branch2_ops, 2299 }, 2300 }, 2301 }; 2302 2303 static struct clk_branch gcc_qupv3_i2c_s4_clk = { 2304 .halt_reg = 0x17074, 2305 .halt_check = BRANCH_HALT_VOTED, 2306 .clkr = { 2307 .enable_reg = 0x52008, 2308 .enable_mask = BIT(14), 2309 .hw.init = &(const struct clk_init_data) { 2310 .name = "gcc_qupv3_i2c_s4_clk", 2311 .parent_hws = (const struct clk_hw*[]) { 2312 &gcc_qupv3_i2c_s4_clk_src.clkr.hw, 2313 }, 2314 .num_parents = 1, 2315 .flags = CLK_SET_RATE_PARENT, 2316 .ops = &clk_branch2_ops, 2317 }, 2318 }, 2319 }; 2320 2321 static struct clk_branch gcc_qupv3_i2c_s5_clk = { 2322 .halt_reg = 0x17090, 2323 .halt_check = BRANCH_HALT_VOTED, 2324 .clkr = { 2325 .enable_reg = 0x52008, 2326 .enable_mask = BIT(15), 2327 .hw.init = &(const struct clk_init_data) { 2328 .name = "gcc_qupv3_i2c_s5_clk", 2329 .parent_hws = (const struct clk_hw*[]) { 2330 &gcc_qupv3_i2c_s5_clk_src.clkr.hw, 2331 }, 2332 .num_parents = 1, 2333 .flags = CLK_SET_RATE_PARENT, 2334 .ops = &clk_branch2_ops, 2335 }, 2336 }, 2337 }; 2338 2339 static struct clk_branch gcc_qupv3_i2c_s6_clk = { 2340 .halt_reg = 0x170ac, 2341 .halt_check = BRANCH_HALT_VOTED, 2342 .clkr = { 2343 .enable_reg = 0x52008, 2344 .enable_mask = BIT(16), 2345 .hw.init = &(const struct clk_init_data) { 2346 .name = "gcc_qupv3_i2c_s6_clk", 2347 .parent_hws = (const struct clk_hw*[]) { 2348 &gcc_qupv3_i2c_s6_clk_src.clkr.hw, 2349 }, 2350 .num_parents = 1, 2351 .flags = CLK_SET_RATE_PARENT, 2352 .ops = &clk_branch2_ops, 2353 }, 2354 }, 2355 }; 2356 2357 static struct clk_branch gcc_qupv3_i2c_s7_clk = { 2358 .halt_reg = 0x170c8, 2359 .halt_check = BRANCH_HALT_VOTED, 2360 .clkr = { 2361 .enable_reg = 0x52008, 2362 .enable_mask = BIT(17), 2363 .hw.init = &(const struct clk_init_data) { 2364 .name = "gcc_qupv3_i2c_s7_clk", 2365 .parent_hws = (const struct clk_hw*[]) { 2366 &gcc_qupv3_i2c_s7_clk_src.clkr.hw, 2367 }, 2368 .num_parents = 1, 2369 .flags = CLK_SET_RATE_PARENT, 2370 .ops = &clk_branch2_ops, 2371 }, 2372 }, 2373 }; 2374 2375 static struct clk_branch gcc_qupv3_i2c_s8_clk = { 2376 .halt_reg = 0x170e4, 2377 .halt_check = BRANCH_HALT_VOTED, 2378 .clkr = { 2379 .enable_reg = 0x52010, 2380 .enable_mask = BIT(14), 2381 .hw.init = &(const struct clk_init_data) { 2382 .name = "gcc_qupv3_i2c_s8_clk", 2383 .parent_hws = (const struct clk_hw*[]) { 2384 &gcc_qupv3_i2c_s8_clk_src.clkr.hw, 2385 }, 2386 .num_parents = 1, 2387 .flags = CLK_SET_RATE_PARENT, 2388 .ops = &clk_branch2_ops, 2389 }, 2390 }, 2391 }; 2392 2393 static struct clk_branch gcc_qupv3_i2c_s9_clk = { 2394 .halt_reg = 0x17100, 2395 .halt_check = BRANCH_HALT_VOTED, 2396 .clkr = { 2397 .enable_reg = 0x52010, 2398 .enable_mask = BIT(15), 2399 .hw.init = &(const struct clk_init_data) { 2400 .name = "gcc_qupv3_i2c_s9_clk", 2401 .parent_hws = (const struct clk_hw*[]) { 2402 &gcc_qupv3_i2c_s9_clk_src.clkr.hw, 2403 }, 2404 .num_parents = 1, 2405 .flags = CLK_SET_RATE_PARENT, 2406 .ops = &clk_branch2_ops, 2407 }, 2408 }, 2409 }; 2410 2411 static struct clk_branch gcc_qupv3_i2c_s_ahb_clk = { 2412 .halt_reg = 0x23000, 2413 .halt_check = BRANCH_HALT_VOTED, 2414 .hwcg_reg = 0x23000, 2415 .hwcg_bit = 1, 2416 .clkr = { 2417 .enable_reg = 0x52008, 2418 .enable_mask = BIT(7), 2419 .hw.init = &(const struct clk_init_data) { 2420 .name = "gcc_qupv3_i2c_s_ahb_clk", 2421 .ops = &clk_branch2_ops, 2422 }, 2423 }, 2424 }; 2425 2426 static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = { 2427 .halt_reg = 0x23154, 2428 .halt_check = BRANCH_HALT_VOTED, 2429 .clkr = { 2430 .enable_reg = 0x52008, 2431 .enable_mask = BIT(18), 2432 .hw.init = &(const struct clk_init_data) { 2433 .name = "gcc_qupv3_wrap1_core_2x_clk", 2434 .ops = &clk_branch2_ops, 2435 }, 2436 }, 2437 }; 2438 2439 static struct clk_branch gcc_qupv3_wrap1_core_clk = { 2440 .halt_reg = 0x23144, 2441 .halt_check = BRANCH_HALT_VOTED, 2442 .clkr = { 2443 .enable_reg = 0x52008, 2444 .enable_mask = BIT(19), 2445 .hw.init = &(const struct clk_init_data) { 2446 .name = "gcc_qupv3_wrap1_core_clk", 2447 .ops = &clk_branch2_ops, 2448 }, 2449 }, 2450 }; 2451 2452 static struct clk_branch gcc_qupv3_wrap1_qspi_ref_clk = { 2453 .halt_reg = 0x1889c, 2454 .halt_check = BRANCH_HALT_VOTED, 2455 .clkr = { 2456 .enable_reg = 0x52010, 2457 .enable_mask = BIT(29), 2458 .hw.init = &(const struct clk_init_data) { 2459 .name = "gcc_qupv3_wrap1_qspi_ref_clk", 2460 .parent_hws = (const struct clk_hw*[]) { 2461 &gcc_qupv3_wrap1_qspi_ref_clk_src.clkr.hw, 2462 }, 2463 .num_parents = 1, 2464 .flags = CLK_SET_RATE_PARENT, 2465 .ops = &clk_branch2_ops, 2466 }, 2467 }, 2468 }; 2469 2470 static struct clk_branch gcc_qupv3_wrap1_s0_clk = { 2471 .halt_reg = 0x18004, 2472 .halt_check = BRANCH_HALT_VOTED, 2473 .clkr = { 2474 .enable_reg = 0x52008, 2475 .enable_mask = BIT(22), 2476 .hw.init = &(const struct clk_init_data) { 2477 .name = "gcc_qupv3_wrap1_s0_clk", 2478 .parent_hws = (const struct clk_hw*[]) { 2479 &gcc_qupv3_wrap1_s0_clk_src.clkr.hw, 2480 }, 2481 .num_parents = 1, 2482 .flags = CLK_SET_RATE_PARENT, 2483 .ops = &clk_branch2_ops, 2484 }, 2485 }, 2486 }; 2487 2488 static struct clk_branch gcc_qupv3_wrap1_s1_clk = { 2489 .halt_reg = 0x1813c, 2490 .halt_check = BRANCH_HALT_VOTED, 2491 .clkr = { 2492 .enable_reg = 0x52008, 2493 .enable_mask = BIT(23), 2494 .hw.init = &(const struct clk_init_data) { 2495 .name = "gcc_qupv3_wrap1_s1_clk", 2496 .parent_hws = (const struct clk_hw*[]) { 2497 &gcc_qupv3_wrap1_s1_clk_src.clkr.hw, 2498 }, 2499 .num_parents = 1, 2500 .flags = CLK_SET_RATE_PARENT, 2501 .ops = &clk_branch2_ops, 2502 }, 2503 }, 2504 }; 2505 2506 static struct clk_branch gcc_qupv3_wrap1_s2_clk = { 2507 .halt_reg = 0x18274, 2508 .halt_check = BRANCH_HALT_VOTED, 2509 .clkr = { 2510 .enable_reg = 0x52008, 2511 .enable_mask = BIT(24), 2512 .hw.init = &(const struct clk_init_data) { 2513 .name = "gcc_qupv3_wrap1_s2_clk", 2514 .parent_hws = (const struct clk_hw*[]) { 2515 &gcc_qupv3_wrap1_s2_clk_src.clkr.hw, 2516 }, 2517 .num_parents = 1, 2518 .flags = CLK_SET_RATE_PARENT, 2519 .ops = &clk_branch2_ops, 2520 }, 2521 }, 2522 }; 2523 2524 static struct clk_branch gcc_qupv3_wrap1_s3_clk = { 2525 .halt_reg = 0x18284, 2526 .halt_check = BRANCH_HALT_VOTED, 2527 .clkr = { 2528 .enable_reg = 0x52008, 2529 .enable_mask = BIT(25), 2530 .hw.init = &(const struct clk_init_data) { 2531 .name = "gcc_qupv3_wrap1_s3_clk", 2532 .parent_hws = (const struct clk_hw*[]) { 2533 &gcc_qupv3_wrap1_s3_clk_src.clkr.hw, 2534 }, 2535 .num_parents = 1, 2536 .flags = CLK_SET_RATE_PARENT, 2537 .ops = &clk_branch2_ops, 2538 }, 2539 }, 2540 }; 2541 2542 static struct clk_branch gcc_qupv3_wrap1_s4_clk = { 2543 .halt_reg = 0x183bc, 2544 .halt_check = BRANCH_HALT_VOTED, 2545 .clkr = { 2546 .enable_reg = 0x52008, 2547 .enable_mask = BIT(26), 2548 .hw.init = &(const struct clk_init_data) { 2549 .name = "gcc_qupv3_wrap1_s4_clk", 2550 .parent_hws = (const struct clk_hw*[]) { 2551 &gcc_qupv3_wrap1_s4_clk_src.clkr.hw, 2552 }, 2553 .num_parents = 1, 2554 .flags = CLK_SET_RATE_PARENT, 2555 .ops = &clk_branch2_ops, 2556 }, 2557 }, 2558 }; 2559 2560 static struct clk_branch gcc_qupv3_wrap1_s5_clk = { 2561 .halt_reg = 0x184f4, 2562 .halt_check = BRANCH_HALT_VOTED, 2563 .clkr = { 2564 .enable_reg = 0x52008, 2565 .enable_mask = BIT(27), 2566 .hw.init = &(const struct clk_init_data) { 2567 .name = "gcc_qupv3_wrap1_s5_clk", 2568 .parent_hws = (const struct clk_hw*[]) { 2569 &gcc_qupv3_wrap1_s5_clk_src.clkr.hw, 2570 }, 2571 .num_parents = 1, 2572 .flags = CLK_SET_RATE_PARENT, 2573 .ops = &clk_branch2_ops, 2574 }, 2575 }, 2576 }; 2577 2578 static struct clk_branch gcc_qupv3_wrap1_s6_clk = { 2579 .halt_reg = 0x1862c, 2580 .halt_check = BRANCH_HALT_VOTED, 2581 .clkr = { 2582 .enable_reg = 0x52008, 2583 .enable_mask = BIT(28), 2584 .hw.init = &(const struct clk_init_data) { 2585 .name = "gcc_qupv3_wrap1_s6_clk", 2586 .parent_hws = (const struct clk_hw*[]) { 2587 &gcc_qupv3_wrap1_s6_clk_src.clkr.hw, 2588 }, 2589 .num_parents = 1, 2590 .flags = CLK_SET_RATE_PARENT, 2591 .ops = &clk_branch2_ops, 2592 }, 2593 }, 2594 }; 2595 2596 static struct clk_branch gcc_qupv3_wrap1_s7_clk = { 2597 .halt_reg = 0x18764, 2598 .halt_check = BRANCH_HALT_VOTED, 2599 .clkr = { 2600 .enable_reg = 0x52010, 2601 .enable_mask = BIT(16), 2602 .hw.init = &(const struct clk_init_data) { 2603 .name = "gcc_qupv3_wrap1_s7_clk", 2604 .parent_hws = (const struct clk_hw*[]) { 2605 &gcc_qupv3_wrap1_s7_clk_src.clkr.hw, 2606 }, 2607 .num_parents = 1, 2608 .flags = CLK_SET_RATE_PARENT, 2609 .ops = &clk_branch2_ops, 2610 }, 2611 }, 2612 }; 2613 2614 static struct clk_branch gcc_qupv3_wrap2_core_2x_clk = { 2615 .halt_reg = 0x232a4, 2616 .halt_check = BRANCH_HALT_VOTED, 2617 .clkr = { 2618 .enable_reg = 0x52010, 2619 .enable_mask = BIT(3), 2620 .hw.init = &(const struct clk_init_data) { 2621 .name = "gcc_qupv3_wrap2_core_2x_clk", 2622 .ops = &clk_branch2_ops, 2623 }, 2624 }, 2625 }; 2626 2627 static struct clk_branch gcc_qupv3_wrap2_core_clk = { 2628 .halt_reg = 0x23294, 2629 .halt_check = BRANCH_HALT_VOTED, 2630 .clkr = { 2631 .enable_reg = 0x52010, 2632 .enable_mask = BIT(0), 2633 .hw.init = &(const struct clk_init_data) { 2634 .name = "gcc_qupv3_wrap2_core_clk", 2635 .ops = &clk_branch2_ops, 2636 }, 2637 }, 2638 }; 2639 2640 static struct clk_branch gcc_qupv3_wrap2_ibi_ctrl_2_clk = { 2641 .halt_reg = 0x1e9cc, 2642 .halt_check = BRANCH_HALT_VOTED, 2643 .hwcg_reg = 0x1e9cc, 2644 .hwcg_bit = 1, 2645 .clkr = { 2646 .enable_reg = 0x52010, 2647 .enable_mask = BIT(27), 2648 .hw.init = &(const struct clk_init_data) { 2649 .name = "gcc_qupv3_wrap2_ibi_ctrl_2_clk", 2650 .parent_hws = (const struct clk_hw*[]) { 2651 &gcc_qupv3_wrap2_ibi_ctrl_0_clk_src.clkr.hw, 2652 }, 2653 .num_parents = 1, 2654 .flags = CLK_SET_RATE_PARENT, 2655 .ops = &clk_branch2_ops, 2656 }, 2657 }, 2658 }; 2659 2660 static struct clk_branch gcc_qupv3_wrap2_ibi_ctrl_3_clk = { 2661 .halt_reg = 0x1e9d0, 2662 .halt_check = BRANCH_HALT_VOTED, 2663 .hwcg_reg = 0x1e9d0, 2664 .hwcg_bit = 1, 2665 .clkr = { 2666 .enable_reg = 0x52010, 2667 .enable_mask = BIT(28), 2668 .hw.init = &(const struct clk_init_data) { 2669 .name = "gcc_qupv3_wrap2_ibi_ctrl_3_clk", 2670 .parent_hws = (const struct clk_hw*[]) { 2671 &gcc_qupv3_wrap2_ibi_ctrl_0_clk_src.clkr.hw, 2672 }, 2673 .num_parents = 1, 2674 .flags = CLK_SET_RATE_PARENT, 2675 .ops = &clk_branch2_ops, 2676 }, 2677 }, 2678 }; 2679 2680 static struct clk_branch gcc_qupv3_wrap2_s0_clk = { 2681 .halt_reg = 0x1e004, 2682 .halt_check = BRANCH_HALT_VOTED, 2683 .clkr = { 2684 .enable_reg = 0x52010, 2685 .enable_mask = BIT(4), 2686 .hw.init = &(const struct clk_init_data) { 2687 .name = "gcc_qupv3_wrap2_s0_clk", 2688 .parent_hws = (const struct clk_hw*[]) { 2689 &gcc_qupv3_wrap2_s0_clk_src.clkr.hw, 2690 }, 2691 .num_parents = 1, 2692 .flags = CLK_SET_RATE_PARENT, 2693 .ops = &clk_branch2_ops, 2694 }, 2695 }, 2696 }; 2697 2698 static struct clk_branch gcc_qupv3_wrap2_s1_clk = { 2699 .halt_reg = 0x1e13c, 2700 .halt_check = BRANCH_HALT_VOTED, 2701 .clkr = { 2702 .enable_reg = 0x52010, 2703 .enable_mask = BIT(5), 2704 .hw.init = &(const struct clk_init_data) { 2705 .name = "gcc_qupv3_wrap2_s1_clk", 2706 .parent_hws = (const struct clk_hw*[]) { 2707 &gcc_qupv3_wrap2_s1_clk_src.clkr.hw, 2708 }, 2709 .num_parents = 1, 2710 .flags = CLK_SET_RATE_PARENT, 2711 .ops = &clk_branch2_ops, 2712 }, 2713 }, 2714 }; 2715 2716 static struct clk_branch gcc_qupv3_wrap2_s2_clk = { 2717 .halt_reg = 0x1e274, 2718 .halt_check = BRANCH_HALT_VOTED, 2719 .clkr = { 2720 .enable_reg = 0x52010, 2721 .enable_mask = BIT(6), 2722 .hw.init = &(const struct clk_init_data) { 2723 .name = "gcc_qupv3_wrap2_s2_clk", 2724 .parent_hws = (const struct clk_hw*[]) { 2725 &gcc_qupv3_wrap2_s2_clk_src.clkr.hw, 2726 }, 2727 .num_parents = 1, 2728 .flags = CLK_SET_RATE_PARENT, 2729 .ops = &clk_branch2_ops, 2730 }, 2731 }, 2732 }; 2733 2734 static struct clk_branch gcc_qupv3_wrap2_s3_clk = { 2735 .halt_reg = 0x1e3ac, 2736 .halt_check = BRANCH_HALT_VOTED, 2737 .clkr = { 2738 .enable_reg = 0x52010, 2739 .enable_mask = BIT(7), 2740 .hw.init = &(const struct clk_init_data) { 2741 .name = "gcc_qupv3_wrap2_s3_clk", 2742 .parent_hws = (const struct clk_hw*[]) { 2743 &gcc_qupv3_wrap2_s3_clk_src.clkr.hw, 2744 }, 2745 .num_parents = 1, 2746 .flags = CLK_SET_RATE_PARENT, 2747 .ops = &clk_branch2_ops, 2748 }, 2749 }, 2750 }; 2751 2752 static struct clk_branch gcc_qupv3_wrap2_s4_clk = { 2753 .halt_reg = 0x1e4e4, 2754 .halt_check = BRANCH_HALT_VOTED, 2755 .clkr = { 2756 .enable_reg = 0x52010, 2757 .enable_mask = BIT(8), 2758 .hw.init = &(const struct clk_init_data) { 2759 .name = "gcc_qupv3_wrap2_s4_clk", 2760 .parent_hws = (const struct clk_hw*[]) { 2761 &gcc_qupv3_wrap2_s4_clk_src.clkr.hw, 2762 }, 2763 .num_parents = 1, 2764 .flags = CLK_SET_RATE_PARENT, 2765 .ops = &clk_branch2_ops, 2766 }, 2767 }, 2768 }; 2769 2770 static struct clk_branch gcc_qupv3_wrap2_s5_clk = { 2771 .halt_reg = 0x1e61c, 2772 .halt_check = BRANCH_HALT_VOTED, 2773 .clkr = { 2774 .enable_reg = 0x52010, 2775 .enable_mask = BIT(9), 2776 .hw.init = &(const struct clk_init_data) { 2777 .name = "gcc_qupv3_wrap2_s5_clk", 2778 .parent_hws = (const struct clk_hw*[]) { 2779 &gcc_qupv3_wrap2_s5_clk_src.clkr.hw, 2780 }, 2781 .num_parents = 1, 2782 .flags = CLK_SET_RATE_PARENT, 2783 .ops = &clk_branch2_ops, 2784 }, 2785 }, 2786 }; 2787 2788 static struct clk_branch gcc_qupv3_wrap2_s6_clk = { 2789 .halt_reg = 0x1e754, 2790 .halt_check = BRANCH_HALT_VOTED, 2791 .clkr = { 2792 .enable_reg = 0x52010, 2793 .enable_mask = BIT(10), 2794 .hw.init = &(const struct clk_init_data) { 2795 .name = "gcc_qupv3_wrap2_s6_clk", 2796 .parent_hws = (const struct clk_hw*[]) { 2797 &gcc_qupv3_wrap2_s6_clk_src.clkr.hw, 2798 }, 2799 .num_parents = 1, 2800 .flags = CLK_SET_RATE_PARENT, 2801 .ops = &clk_branch2_ops, 2802 }, 2803 }, 2804 }; 2805 2806 static struct clk_branch gcc_qupv3_wrap2_s7_clk = { 2807 .halt_reg = 0x1e88c, 2808 .halt_check = BRANCH_HALT_VOTED, 2809 .clkr = { 2810 .enable_reg = 0x52010, 2811 .enable_mask = BIT(17), 2812 .hw.init = &(const struct clk_init_data) { 2813 .name = "gcc_qupv3_wrap2_s7_clk", 2814 .parent_hws = (const struct clk_hw*[]) { 2815 &gcc_qupv3_wrap2_s7_clk_src.clkr.hw, 2816 }, 2817 .num_parents = 1, 2818 .flags = CLK_SET_RATE_PARENT, 2819 .ops = &clk_branch2_ops, 2820 }, 2821 }, 2822 }; 2823 2824 static struct clk_branch gcc_qupv3_wrap3_core_2x_clk = { 2825 .halt_reg = 0x233f4, 2826 .halt_check = BRANCH_HALT_VOTED, 2827 .clkr = { 2828 .enable_reg = 0x52018, 2829 .enable_mask = BIT(1), 2830 .hw.init = &(const struct clk_init_data) { 2831 .name = "gcc_qupv3_wrap3_core_2x_clk", 2832 .ops = &clk_branch2_ops, 2833 }, 2834 }, 2835 }; 2836 2837 static struct clk_branch gcc_qupv3_wrap3_core_clk = { 2838 .halt_reg = 0x233e4, 2839 .halt_check = BRANCH_HALT_VOTED, 2840 .clkr = { 2841 .enable_reg = 0x52018, 2842 .enable_mask = BIT(0), 2843 .hw.init = &(const struct clk_init_data) { 2844 .name = "gcc_qupv3_wrap3_core_clk", 2845 .ops = &clk_branch2_ops, 2846 }, 2847 }, 2848 }; 2849 2850 static struct clk_branch gcc_qupv3_wrap3_qspi_ref_clk = { 2851 .halt_reg = 0x19014, 2852 .halt_check = BRANCH_HALT_VOTED, 2853 .clkr = { 2854 .enable_reg = 0x52018, 2855 .enable_mask = BIT(3), 2856 .hw.init = &(const struct clk_init_data) { 2857 .name = "gcc_qupv3_wrap3_qspi_ref_clk", 2858 .parent_hws = (const struct clk_hw*[]) { 2859 &gcc_qupv3_wrap3_qspi_ref_clk_src.clkr.hw, 2860 }, 2861 .num_parents = 1, 2862 .flags = CLK_SET_RATE_PARENT, 2863 .ops = &clk_branch2_ops, 2864 }, 2865 }, 2866 }; 2867 2868 static struct clk_branch gcc_qupv3_wrap3_s0_clk = { 2869 .halt_reg = 0x19004, 2870 .halt_check = BRANCH_HALT_VOTED, 2871 .clkr = { 2872 .enable_reg = 0x52018, 2873 .enable_mask = BIT(2), 2874 .hw.init = &(const struct clk_init_data) { 2875 .name = "gcc_qupv3_wrap3_s0_clk", 2876 .parent_hws = (const struct clk_hw*[]) { 2877 &gcc_qupv3_wrap3_s0_clk_src.clkr.hw, 2878 }, 2879 .num_parents = 1, 2880 .flags = CLK_SET_RATE_PARENT, 2881 .ops = &clk_branch2_ops, 2882 }, 2883 }, 2884 }; 2885 2886 static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = { 2887 .halt_reg = 0x2313c, 2888 .halt_check = BRANCH_HALT_VOTED, 2889 .hwcg_reg = 0x2313c, 2890 .hwcg_bit = 1, 2891 .clkr = { 2892 .enable_reg = 0x52008, 2893 .enable_mask = BIT(20), 2894 .hw.init = &(const struct clk_init_data) { 2895 .name = "gcc_qupv3_wrap_1_m_ahb_clk", 2896 .ops = &clk_branch2_ops, 2897 }, 2898 }, 2899 }; 2900 2901 static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = { 2902 .halt_reg = 0x23140, 2903 .halt_check = BRANCH_HALT_VOTED, 2904 .hwcg_reg = 0x23140, 2905 .hwcg_bit = 1, 2906 .clkr = { 2907 .enable_reg = 0x52008, 2908 .enable_mask = BIT(21), 2909 .hw.init = &(const struct clk_init_data) { 2910 .name = "gcc_qupv3_wrap_1_s_ahb_clk", 2911 .ops = &clk_branch2_ops, 2912 }, 2913 }, 2914 }; 2915 2916 static struct clk_branch gcc_qupv3_wrap_2_ibi_2_ahb_clk = { 2917 .halt_reg = 0x1e9c4, 2918 .halt_check = BRANCH_HALT_VOTED, 2919 .hwcg_reg = 0x1e9c4, 2920 .hwcg_bit = 1, 2921 .clkr = { 2922 .enable_reg = 0x52010, 2923 .enable_mask = BIT(25), 2924 .hw.init = &(const struct clk_init_data) { 2925 .name = "gcc_qupv3_wrap_2_ibi_2_ahb_clk", 2926 .ops = &clk_branch2_ops, 2927 }, 2928 }, 2929 }; 2930 2931 static struct clk_branch gcc_qupv3_wrap_2_ibi_3_ahb_clk = { 2932 .halt_reg = 0x1e9c8, 2933 .halt_check = BRANCH_HALT_VOTED, 2934 .hwcg_reg = 0x1e9c8, 2935 .hwcg_bit = 1, 2936 .clkr = { 2937 .enable_reg = 0x52010, 2938 .enable_mask = BIT(26), 2939 .hw.init = &(const struct clk_init_data) { 2940 .name = "gcc_qupv3_wrap_2_ibi_3_ahb_clk", 2941 .ops = &clk_branch2_ops, 2942 }, 2943 }, 2944 }; 2945 2946 static struct clk_branch gcc_qupv3_wrap_2_m_ahb_clk = { 2947 .halt_reg = 0x2328c, 2948 .halt_check = BRANCH_HALT_VOTED, 2949 .hwcg_reg = 0x2328c, 2950 .hwcg_bit = 1, 2951 .clkr = { 2952 .enable_reg = 0x52010, 2953 .enable_mask = BIT(2), 2954 .hw.init = &(const struct clk_init_data) { 2955 .name = "gcc_qupv3_wrap_2_m_ahb_clk", 2956 .ops = &clk_branch2_ops, 2957 }, 2958 }, 2959 }; 2960 2961 static struct clk_branch gcc_qupv3_wrap_2_s_ahb_clk = { 2962 .halt_reg = 0x23290, 2963 .halt_check = BRANCH_HALT_VOTED, 2964 .hwcg_reg = 0x23290, 2965 .hwcg_bit = 1, 2966 .clkr = { 2967 .enable_reg = 0x52010, 2968 .enable_mask = BIT(1), 2969 .hw.init = &(const struct clk_init_data) { 2970 .name = "gcc_qupv3_wrap_2_s_ahb_clk", 2971 .ops = &clk_branch2_ops, 2972 }, 2973 }, 2974 }; 2975 2976 static struct clk_branch gcc_qupv3_wrap_3_m_ahb_clk = { 2977 .halt_reg = 0x233dc, 2978 .halt_check = BRANCH_HALT_VOTED, 2979 .hwcg_reg = 0x233dc, 2980 .hwcg_bit = 1, 2981 .clkr = { 2982 .enable_reg = 0x52010, 2983 .enable_mask = BIT(30), 2984 .hw.init = &(const struct clk_init_data) { 2985 .name = "gcc_qupv3_wrap_3_m_ahb_clk", 2986 .ops = &clk_branch2_ops, 2987 }, 2988 }, 2989 }; 2990 2991 static struct clk_branch gcc_qupv3_wrap_3_s_ahb_clk = { 2992 .halt_reg = 0x233e0, 2993 .halt_check = BRANCH_HALT_VOTED, 2994 .hwcg_reg = 0x233e0, 2995 .hwcg_bit = 1, 2996 .clkr = { 2997 .enable_reg = 0x52010, 2998 .enable_mask = BIT(31), 2999 .hw.init = &(const struct clk_init_data) { 3000 .name = "gcc_qupv3_wrap_3_s_ahb_clk", 3001 .ops = &clk_branch2_ops, 3002 }, 3003 }, 3004 }; 3005 3006 static struct clk_branch gcc_sdcc2_ahb_clk = { 3007 .halt_reg = 0x14010, 3008 .halt_check = BRANCH_HALT, 3009 .clkr = { 3010 .enable_reg = 0x14010, 3011 .enable_mask = BIT(0), 3012 .hw.init = &(const struct clk_init_data) { 3013 .name = "gcc_sdcc2_ahb_clk", 3014 .ops = &clk_branch2_ops, 3015 }, 3016 }, 3017 }; 3018 3019 static struct clk_branch gcc_sdcc2_apps_clk = { 3020 .halt_reg = 0x14004, 3021 .halt_check = BRANCH_HALT, 3022 .clkr = { 3023 .enable_reg = 0x14004, 3024 .enable_mask = BIT(0), 3025 .hw.init = &(const struct clk_init_data) { 3026 .name = "gcc_sdcc2_apps_clk", 3027 .parent_hws = (const struct clk_hw*[]) { 3028 &gcc_sdcc2_apps_clk_src.clkr.hw, 3029 }, 3030 .num_parents = 1, 3031 .flags = CLK_SET_RATE_PARENT, 3032 .ops = &clk_branch2_ops, 3033 }, 3034 }, 3035 }; 3036 3037 static struct clk_branch gcc_sdcc4_ahb_clk = { 3038 .halt_reg = 0x16010, 3039 .halt_check = BRANCH_HALT, 3040 .clkr = { 3041 .enable_reg = 0x16010, 3042 .enable_mask = BIT(0), 3043 .hw.init = &(const struct clk_init_data) { 3044 .name = "gcc_sdcc4_ahb_clk", 3045 .ops = &clk_branch2_ops, 3046 }, 3047 }, 3048 }; 3049 3050 static struct clk_branch gcc_sdcc4_apps_clk = { 3051 .halt_reg = 0x16004, 3052 .halt_check = BRANCH_HALT, 3053 .clkr = { 3054 .enable_reg = 0x16004, 3055 .enable_mask = BIT(0), 3056 .hw.init = &(const struct clk_init_data) { 3057 .name = "gcc_sdcc4_apps_clk", 3058 .parent_hws = (const struct clk_hw*[]) { 3059 &gcc_sdcc4_apps_clk_src.clkr.hw, 3060 }, 3061 .num_parents = 1, 3062 .flags = CLK_SET_RATE_PARENT, 3063 .ops = &clk_branch2_ops, 3064 }, 3065 }, 3066 }; 3067 3068 static struct clk_branch gcc_ufs_phy_ahb_clk = { 3069 .halt_reg = 0x77024, 3070 .halt_check = BRANCH_HALT_VOTED, 3071 .hwcg_reg = 0x77024, 3072 .hwcg_bit = 1, 3073 .clkr = { 3074 .enable_reg = 0x77024, 3075 .enable_mask = BIT(0), 3076 .hw.init = &(const struct clk_init_data) { 3077 .name = "gcc_ufs_phy_ahb_clk", 3078 .ops = &clk_branch2_ops, 3079 }, 3080 }, 3081 }; 3082 3083 static struct clk_branch gcc_ufs_phy_axi_clk = { 3084 .halt_reg = 0x77018, 3085 .halt_check = BRANCH_HALT_VOTED, 3086 .hwcg_reg = 0x77018, 3087 .hwcg_bit = 1, 3088 .clkr = { 3089 .enable_reg = 0x77018, 3090 .enable_mask = BIT(0), 3091 .hw.init = &(const struct clk_init_data) { 3092 .name = "gcc_ufs_phy_axi_clk", 3093 .parent_hws = (const struct clk_hw*[]) { 3094 &gcc_ufs_phy_axi_clk_src.clkr.hw, 3095 }, 3096 .num_parents = 1, 3097 .flags = CLK_SET_RATE_PARENT, 3098 .ops = &clk_branch2_ops, 3099 }, 3100 }, 3101 }; 3102 3103 static struct clk_branch gcc_ufs_phy_axi_hw_ctl_clk = { 3104 .halt_reg = 0x77018, 3105 .halt_check = BRANCH_HALT_VOTED, 3106 .hwcg_reg = 0x77018, 3107 .hwcg_bit = 1, 3108 .clkr = { 3109 .enable_reg = 0x77018, 3110 .enable_mask = BIT(1), 3111 .hw.init = &(const struct clk_init_data) { 3112 .name = "gcc_ufs_phy_axi_hw_ctl_clk", 3113 .parent_hws = (const struct clk_hw*[]) { 3114 &gcc_ufs_phy_axi_clk_src.clkr.hw, 3115 }, 3116 .num_parents = 1, 3117 .flags = CLK_SET_RATE_PARENT, 3118 .ops = &clk_branch2_ops, 3119 }, 3120 }, 3121 }; 3122 3123 static struct clk_branch gcc_ufs_phy_ice_core_clk = { 3124 .halt_reg = 0x77074, 3125 .halt_check = BRANCH_HALT_VOTED, 3126 .hwcg_reg = 0x77074, 3127 .hwcg_bit = 1, 3128 .clkr = { 3129 .enable_reg = 0x77074, 3130 .enable_mask = BIT(0), 3131 .hw.init = &(const struct clk_init_data) { 3132 .name = "gcc_ufs_phy_ice_core_clk", 3133 .parent_hws = (const struct clk_hw*[]) { 3134 &gcc_ufs_phy_ice_core_clk_src.clkr.hw, 3135 }, 3136 .num_parents = 1, 3137 .flags = CLK_SET_RATE_PARENT, 3138 .ops = &clk_branch2_ops, 3139 }, 3140 }, 3141 }; 3142 3143 static struct clk_branch gcc_ufs_phy_ice_core_hw_ctl_clk = { 3144 .halt_reg = 0x77074, 3145 .halt_check = BRANCH_HALT_VOTED, 3146 .hwcg_reg = 0x77074, 3147 .hwcg_bit = 1, 3148 .clkr = { 3149 .enable_reg = 0x77074, 3150 .enable_mask = BIT(1), 3151 .hw.init = &(const struct clk_init_data) { 3152 .name = "gcc_ufs_phy_ice_core_hw_ctl_clk", 3153 .parent_hws = (const struct clk_hw*[]) { 3154 &gcc_ufs_phy_ice_core_clk_src.clkr.hw, 3155 }, 3156 .num_parents = 1, 3157 .flags = CLK_SET_RATE_PARENT, 3158 .ops = &clk_branch2_ops, 3159 }, 3160 }, 3161 }; 3162 3163 static struct clk_branch gcc_ufs_phy_phy_aux_clk = { 3164 .halt_reg = 0x770b0, 3165 .halt_check = BRANCH_HALT_VOTED, 3166 .hwcg_reg = 0x770b0, 3167 .hwcg_bit = 1, 3168 .clkr = { 3169 .enable_reg = 0x770b0, 3170 .enable_mask = BIT(0), 3171 .hw.init = &(const struct clk_init_data) { 3172 .name = "gcc_ufs_phy_phy_aux_clk", 3173 .parent_hws = (const struct clk_hw*[]) { 3174 &gcc_ufs_phy_phy_aux_clk_src.clkr.hw, 3175 }, 3176 .num_parents = 1, 3177 .flags = CLK_SET_RATE_PARENT, 3178 .ops = &clk_branch2_ops, 3179 }, 3180 }, 3181 }; 3182 3183 static struct clk_branch gcc_ufs_phy_phy_aux_hw_ctl_clk = { 3184 .halt_reg = 0x770b0, 3185 .halt_check = BRANCH_HALT_VOTED, 3186 .hwcg_reg = 0x770b0, 3187 .hwcg_bit = 1, 3188 .clkr = { 3189 .enable_reg = 0x770b0, 3190 .enable_mask = BIT(1), 3191 .hw.init = &(const struct clk_init_data) { 3192 .name = "gcc_ufs_phy_phy_aux_hw_ctl_clk", 3193 .parent_hws = (const struct clk_hw*[]) { 3194 &gcc_ufs_phy_phy_aux_clk_src.clkr.hw, 3195 }, 3196 .num_parents = 1, 3197 .flags = CLK_SET_RATE_PARENT, 3198 .ops = &clk_branch2_ops, 3199 }, 3200 }, 3201 }; 3202 3203 static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = { 3204 .halt_reg = 0x7702c, 3205 .halt_check = BRANCH_HALT_DELAY, 3206 .clkr = { 3207 .enable_reg = 0x7702c, 3208 .enable_mask = BIT(0), 3209 .hw.init = &(const struct clk_init_data) { 3210 .name = "gcc_ufs_phy_rx_symbol_0_clk", 3211 .parent_hws = (const struct clk_hw*[]) { 3212 &gcc_ufs_phy_rx_symbol_0_clk_src.clkr.hw, 3213 }, 3214 .num_parents = 1, 3215 .flags = CLK_SET_RATE_PARENT, 3216 .ops = &clk_branch2_ops, 3217 }, 3218 }, 3219 }; 3220 3221 static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = { 3222 .halt_reg = 0x770cc, 3223 .halt_check = BRANCH_HALT_DELAY, 3224 .clkr = { 3225 .enable_reg = 0x770cc, 3226 .enable_mask = BIT(0), 3227 .hw.init = &(const struct clk_init_data) { 3228 .name = "gcc_ufs_phy_rx_symbol_1_clk", 3229 .parent_hws = (const struct clk_hw*[]) { 3230 &gcc_ufs_phy_rx_symbol_1_clk_src.clkr.hw, 3231 }, 3232 .num_parents = 1, 3233 .flags = CLK_SET_RATE_PARENT, 3234 .ops = &clk_branch2_ops, 3235 }, 3236 }, 3237 }; 3238 3239 static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = { 3240 .halt_reg = 0x77028, 3241 .halt_check = BRANCH_HALT_DELAY, 3242 .clkr = { 3243 .enable_reg = 0x77028, 3244 .enable_mask = BIT(0), 3245 .hw.init = &(const struct clk_init_data) { 3246 .name = "gcc_ufs_phy_tx_symbol_0_clk", 3247 .parent_hws = (const struct clk_hw*[]) { 3248 &gcc_ufs_phy_tx_symbol_0_clk_src.clkr.hw, 3249 }, 3250 .num_parents = 1, 3251 .flags = CLK_SET_RATE_PARENT, 3252 .ops = &clk_branch2_ops, 3253 }, 3254 }, 3255 }; 3256 3257 static struct clk_branch gcc_ufs_phy_unipro_core_clk = { 3258 .halt_reg = 0x77068, 3259 .halt_check = BRANCH_HALT_VOTED, 3260 .hwcg_reg = 0x77068, 3261 .hwcg_bit = 1, 3262 .clkr = { 3263 .enable_reg = 0x77068, 3264 .enable_mask = BIT(0), 3265 .hw.init = &(const struct clk_init_data) { 3266 .name = "gcc_ufs_phy_unipro_core_clk", 3267 .parent_hws = (const struct clk_hw*[]) { 3268 &gcc_ufs_phy_unipro_core_clk_src.clkr.hw, 3269 }, 3270 .num_parents = 1, 3271 .flags = CLK_SET_RATE_PARENT, 3272 .ops = &clk_branch2_ops, 3273 }, 3274 }, 3275 }; 3276 3277 static struct clk_branch gcc_ufs_phy_unipro_core_hw_ctl_clk = { 3278 .halt_reg = 0x77068, 3279 .halt_check = BRANCH_HALT_VOTED, 3280 .hwcg_reg = 0x77068, 3281 .hwcg_bit = 1, 3282 .clkr = { 3283 .enable_reg = 0x77068, 3284 .enable_mask = BIT(1), 3285 .hw.init = &(const struct clk_init_data) { 3286 .name = "gcc_ufs_phy_unipro_core_hw_ctl_clk", 3287 .parent_hws = (const struct clk_hw*[]) { 3288 &gcc_ufs_phy_unipro_core_clk_src.clkr.hw, 3289 }, 3290 .num_parents = 1, 3291 .flags = CLK_SET_RATE_PARENT, 3292 .ops = &clk_branch2_ops, 3293 }, 3294 }, 3295 }; 3296 3297 static struct clk_branch gcc_usb30_prim_master_clk = { 3298 .halt_reg = 0x39018, 3299 .halt_check = BRANCH_HALT, 3300 .clkr = { 3301 .enable_reg = 0x39018, 3302 .enable_mask = BIT(0), 3303 .hw.init = &(const struct clk_init_data) { 3304 .name = "gcc_usb30_prim_master_clk", 3305 .parent_hws = (const struct clk_hw*[]) { 3306 &gcc_usb30_prim_master_clk_src.clkr.hw, 3307 }, 3308 .num_parents = 1, 3309 .flags = CLK_SET_RATE_PARENT, 3310 .ops = &clk_branch2_ops, 3311 }, 3312 }, 3313 }; 3314 3315 static struct clk_branch gcc_usb30_prim_mock_utmi_clk = { 3316 .halt_reg = 0x39028, 3317 .halt_check = BRANCH_HALT, 3318 .clkr = { 3319 .enable_reg = 0x39028, 3320 .enable_mask = BIT(0), 3321 .hw.init = &(const struct clk_init_data) { 3322 .name = "gcc_usb30_prim_mock_utmi_clk", 3323 .parent_hws = (const struct clk_hw*[]) { 3324 &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr.hw, 3325 }, 3326 .num_parents = 1, 3327 .flags = CLK_SET_RATE_PARENT, 3328 .ops = &clk_branch2_ops, 3329 }, 3330 }, 3331 }; 3332 3333 static struct clk_branch gcc_usb30_prim_sleep_clk = { 3334 .halt_reg = 0x39024, 3335 .halt_check = BRANCH_HALT, 3336 .clkr = { 3337 .enable_reg = 0x39024, 3338 .enable_mask = BIT(0), 3339 .hw.init = &(const struct clk_init_data) { 3340 .name = "gcc_usb30_prim_sleep_clk", 3341 .ops = &clk_branch2_ops, 3342 }, 3343 }, 3344 }; 3345 3346 static struct clk_branch gcc_usb3_prim_phy_aux_clk = { 3347 .halt_reg = 0x39060, 3348 .halt_check = BRANCH_HALT, 3349 .clkr = { 3350 .enable_reg = 0x39060, 3351 .enable_mask = BIT(0), 3352 .hw.init = &(const struct clk_init_data) { 3353 .name = "gcc_usb3_prim_phy_aux_clk", 3354 .parent_hws = (const struct clk_hw*[]) { 3355 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, 3356 }, 3357 .num_parents = 1, 3358 .flags = CLK_SET_RATE_PARENT, 3359 .ops = &clk_branch2_ops, 3360 }, 3361 }, 3362 }; 3363 3364 static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = { 3365 .halt_reg = 0x39064, 3366 .halt_check = BRANCH_HALT, 3367 .clkr = { 3368 .enable_reg = 0x39064, 3369 .enable_mask = BIT(0), 3370 .hw.init = &(const struct clk_init_data) { 3371 .name = "gcc_usb3_prim_phy_com_aux_clk", 3372 .parent_hws = (const struct clk_hw*[]) { 3373 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, 3374 }, 3375 .num_parents = 1, 3376 .flags = CLK_SET_RATE_PARENT, 3377 .ops = &clk_branch2_ops, 3378 }, 3379 }, 3380 }; 3381 3382 static struct clk_branch gcc_usb3_prim_phy_pipe_clk = { 3383 .halt_reg = 0x39068, 3384 .halt_check = BRANCH_HALT_DELAY, 3385 .hwcg_reg = 0x39068, 3386 .hwcg_bit = 1, 3387 .clkr = { 3388 .enable_reg = 0x39068, 3389 .enable_mask = BIT(0), 3390 .hw.init = &(const struct clk_init_data) { 3391 .name = "gcc_usb3_prim_phy_pipe_clk", 3392 .parent_hws = (const struct clk_hw*[]) { 3393 &gcc_usb3_prim_phy_pipe_clk_src.clkr.hw, 3394 }, 3395 .num_parents = 1, 3396 .flags = CLK_SET_RATE_PARENT, 3397 .ops = &clk_branch2_ops, 3398 }, 3399 }, 3400 }; 3401 3402 static struct clk_branch gcc_video_axi0_clk = { 3403 .halt_reg = 0x32018, 3404 .halt_check = BRANCH_HALT_SKIP, 3405 .hwcg_reg = 0x32018, 3406 .hwcg_bit = 1, 3407 .clkr = { 3408 .enable_reg = 0x32018, 3409 .enable_mask = BIT(0), 3410 .hw.init = &(const struct clk_init_data) { 3411 .name = "gcc_video_axi0_clk", 3412 .ops = &clk_branch2_ops, 3413 }, 3414 }, 3415 }; 3416 3417 static struct clk_branch gcc_video_axi1_clk = { 3418 .halt_reg = 0x32024, 3419 .halt_check = BRANCH_HALT_SKIP, 3420 .hwcg_reg = 0x32024, 3421 .hwcg_bit = 1, 3422 .clkr = { 3423 .enable_reg = 0x32024, 3424 .enable_mask = BIT(0), 3425 .hw.init = &(const struct clk_init_data) { 3426 .name = "gcc_video_axi1_clk", 3427 .ops = &clk_branch2_ops, 3428 }, 3429 }, 3430 }; 3431 3432 static struct gdsc pcie_0_gdsc = { 3433 .gdscr = 0x6b004, 3434 .collapse_ctrl = 0x5214c, 3435 .collapse_mask = BIT(0), 3436 .pd = { 3437 .name = "pcie_0_gdsc", 3438 }, 3439 .pwrsts = PWRSTS_RET_ON, 3440 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, 3441 }; 3442 3443 static struct gdsc pcie_0_phy_gdsc = { 3444 .gdscr = 0x6c000, 3445 .collapse_ctrl = 0x5214c, 3446 .collapse_mask = BIT(3), 3447 .pd = { 3448 .name = "pcie_0_phy_gdsc", 3449 }, 3450 .pwrsts = PWRSTS_RET_ON, 3451 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, 3452 }; 3453 3454 static struct gdsc pcie_1_gdsc = { 3455 .gdscr = 0x8d004, 3456 .collapse_ctrl = 0x5214c, 3457 .collapse_mask = BIT(1), 3458 .pd = { 3459 .name = "pcie_1_gdsc", 3460 }, 3461 .pwrsts = PWRSTS_RET_ON, 3462 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, 3463 }; 3464 3465 static struct gdsc pcie_1_phy_gdsc = { 3466 .gdscr = 0x8e000, 3467 .collapse_ctrl = 0x5214c, 3468 .collapse_mask = BIT(4), 3469 .pd = { 3470 .name = "pcie_1_phy_gdsc", 3471 }, 3472 .pwrsts = PWRSTS_RET_ON, 3473 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, 3474 }; 3475 3476 static struct gdsc ufs_phy_gdsc = { 3477 .gdscr = 0x77004, 3478 .pd = { 3479 .name = "ufs_phy_gdsc", 3480 }, 3481 .pwrsts = PWRSTS_OFF_ON, 3482 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 3483 }; 3484 3485 static struct gdsc ufs_mem_phy_gdsc = { 3486 .gdscr = 0x9e000, 3487 .pd = { 3488 .name = "ufs_mem_phy_gdsc", 3489 }, 3490 .pwrsts = PWRSTS_OFF_ON, 3491 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 3492 }; 3493 3494 static struct gdsc usb30_prim_gdsc = { 3495 .gdscr = 0x39004, 3496 .pd = { 3497 .name = "usb30_prim_gdsc", 3498 }, 3499 .pwrsts = PWRSTS_RET_ON, 3500 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 3501 }; 3502 3503 static struct gdsc usb3_phy_gdsc = { 3504 .gdscr = 0x50018, 3505 .pd = { 3506 .name = "usb3_phy_gdsc", 3507 }, 3508 .pwrsts = PWRSTS_RET_ON, 3509 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 3510 }; 3511 3512 static struct clk_regmap *gcc_sm8650_clocks[] = { 3513 [GCC_AGGRE_NOC_PCIE_AXI_CLK] = &gcc_aggre_noc_pcie_axi_clk.clkr, 3514 [GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr, 3515 [GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK] = &gcc_aggre_ufs_phy_axi_hw_ctl_clk.clkr, 3516 [GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr, 3517 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, 3518 [GCC_CAMERA_HF_AXI_CLK] = &gcc_camera_hf_axi_clk.clkr, 3519 [GCC_CAMERA_SF_AXI_CLK] = &gcc_camera_sf_axi_clk.clkr, 3520 [GCC_CFG_NOC_PCIE_ANOC_AHB_CLK] = &gcc_cfg_noc_pcie_anoc_ahb_clk.clkr, 3521 [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr, 3522 [GCC_CNOC_PCIE_SF_AXI_CLK] = &gcc_cnoc_pcie_sf_axi_clk.clkr, 3523 [GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr, 3524 [GCC_DDRSS_PCIE_SF_QTB_CLK] = &gcc_ddrss_pcie_sf_qtb_clk.clkr, 3525 [GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr, 3526 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, 3527 [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr, 3528 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, 3529 [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr, 3530 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, 3531 [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr, 3532 [GCC_GPLL0] = &gcc_gpll0.clkr, 3533 [GCC_GPLL0_OUT_EVEN] = &gcc_gpll0_out_even.clkr, 3534 [GCC_GPLL1] = &gcc_gpll1.clkr, 3535 [GCC_GPLL3] = &gcc_gpll3.clkr, 3536 [GCC_GPLL4] = &gcc_gpll4.clkr, 3537 [GCC_GPLL6] = &gcc_gpll6.clkr, 3538 [GCC_GPLL7] = &gcc_gpll7.clkr, 3539 [GCC_GPLL9] = &gcc_gpll9.clkr, 3540 [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr, 3541 [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr, 3542 [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr, 3543 [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr, 3544 [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr, 3545 [GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr, 3546 [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr, 3547 [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr, 3548 [GCC_PCIE_0_PHY_RCHNG_CLK] = &gcc_pcie_0_phy_rchng_clk.clkr, 3549 [GCC_PCIE_0_PHY_RCHNG_CLK_SRC] = &gcc_pcie_0_phy_rchng_clk_src.clkr, 3550 [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr, 3551 [GCC_PCIE_0_PIPE_CLK_SRC] = &gcc_pcie_0_pipe_clk_src.clkr, 3552 [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr, 3553 [GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr, 3554 [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr, 3555 [GCC_PCIE_1_AUX_CLK_SRC] = &gcc_pcie_1_aux_clk_src.clkr, 3556 [GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr, 3557 [GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr, 3558 [GCC_PCIE_1_PHY_AUX_CLK] = &gcc_pcie_1_phy_aux_clk.clkr, 3559 [GCC_PCIE_1_PHY_AUX_CLK_SRC] = &gcc_pcie_1_phy_aux_clk_src.clkr, 3560 [GCC_PCIE_1_PHY_RCHNG_CLK] = &gcc_pcie_1_phy_rchng_clk.clkr, 3561 [GCC_PCIE_1_PHY_RCHNG_CLK_SRC] = &gcc_pcie_1_phy_rchng_clk_src.clkr, 3562 [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr, 3563 [GCC_PCIE_1_PIPE_CLK_SRC] = &gcc_pcie_1_pipe_clk_src.clkr, 3564 [GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr, 3565 [GCC_PCIE_1_SLV_Q2A_AXI_CLK] = &gcc_pcie_1_slv_q2a_axi_clk.clkr, 3566 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, 3567 [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr, 3568 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, 3569 [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr, 3570 [GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr, 3571 [GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr, 3572 [GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr, 3573 [GCC_QMIP_GPU_AHB_CLK] = &gcc_qmip_gpu_ahb_clk.clkr, 3574 [GCC_QMIP_PCIE_AHB_CLK] = &gcc_qmip_pcie_ahb_clk.clkr, 3575 [GCC_QMIP_VIDEO_CV_CPU_AHB_CLK] = &gcc_qmip_video_cv_cpu_ahb_clk.clkr, 3576 [GCC_QMIP_VIDEO_CVP_AHB_CLK] = &gcc_qmip_video_cvp_ahb_clk.clkr, 3577 [GCC_QMIP_VIDEO_V_CPU_AHB_CLK] = &gcc_qmip_video_v_cpu_ahb_clk.clkr, 3578 [GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr, 3579 [GCC_QUPV3_I2C_CORE_CLK] = &gcc_qupv3_i2c_core_clk.clkr, 3580 [GCC_QUPV3_I2C_S0_CLK] = &gcc_qupv3_i2c_s0_clk.clkr, 3581 [GCC_QUPV3_I2C_S0_CLK_SRC] = &gcc_qupv3_i2c_s0_clk_src.clkr, 3582 [GCC_QUPV3_I2C_S1_CLK] = &gcc_qupv3_i2c_s1_clk.clkr, 3583 [GCC_QUPV3_I2C_S1_CLK_SRC] = &gcc_qupv3_i2c_s1_clk_src.clkr, 3584 [GCC_QUPV3_I2C_S2_CLK] = &gcc_qupv3_i2c_s2_clk.clkr, 3585 [GCC_QUPV3_I2C_S2_CLK_SRC] = &gcc_qupv3_i2c_s2_clk_src.clkr, 3586 [GCC_QUPV3_I2C_S3_CLK] = &gcc_qupv3_i2c_s3_clk.clkr, 3587 [GCC_QUPV3_I2C_S3_CLK_SRC] = &gcc_qupv3_i2c_s3_clk_src.clkr, 3588 [GCC_QUPV3_I2C_S4_CLK] = &gcc_qupv3_i2c_s4_clk.clkr, 3589 [GCC_QUPV3_I2C_S4_CLK_SRC] = &gcc_qupv3_i2c_s4_clk_src.clkr, 3590 [GCC_QUPV3_I2C_S5_CLK] = &gcc_qupv3_i2c_s5_clk.clkr, 3591 [GCC_QUPV3_I2C_S5_CLK_SRC] = &gcc_qupv3_i2c_s5_clk_src.clkr, 3592 [GCC_QUPV3_I2C_S6_CLK] = &gcc_qupv3_i2c_s6_clk.clkr, 3593 [GCC_QUPV3_I2C_S6_CLK_SRC] = &gcc_qupv3_i2c_s6_clk_src.clkr, 3594 [GCC_QUPV3_I2C_S7_CLK] = &gcc_qupv3_i2c_s7_clk.clkr, 3595 [GCC_QUPV3_I2C_S7_CLK_SRC] = &gcc_qupv3_i2c_s7_clk_src.clkr, 3596 [GCC_QUPV3_I2C_S8_CLK] = &gcc_qupv3_i2c_s8_clk.clkr, 3597 [GCC_QUPV3_I2C_S8_CLK_SRC] = &gcc_qupv3_i2c_s8_clk_src.clkr, 3598 [GCC_QUPV3_I2C_S9_CLK] = &gcc_qupv3_i2c_s9_clk.clkr, 3599 [GCC_QUPV3_I2C_S9_CLK_SRC] = &gcc_qupv3_i2c_s9_clk_src.clkr, 3600 [GCC_QUPV3_I2C_S_AHB_CLK] = &gcc_qupv3_i2c_s_ahb_clk.clkr, 3601 [GCC_QUPV3_WRAP1_CORE_2X_CLK] = &gcc_qupv3_wrap1_core_2x_clk.clkr, 3602 [GCC_QUPV3_WRAP1_CORE_CLK] = &gcc_qupv3_wrap1_core_clk.clkr, 3603 [GCC_QUPV3_WRAP1_QSPI_REF_CLK] = &gcc_qupv3_wrap1_qspi_ref_clk.clkr, 3604 [GCC_QUPV3_WRAP1_QSPI_REF_CLK_SRC] = &gcc_qupv3_wrap1_qspi_ref_clk_src.clkr, 3605 [GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr, 3606 [GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr, 3607 [GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr, 3608 [GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr, 3609 [GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr, 3610 [GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr, 3611 [GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr, 3612 [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr, 3613 [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr, 3614 [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr, 3615 [GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr, 3616 [GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr, 3617 [GCC_QUPV3_WRAP1_S6_CLK] = &gcc_qupv3_wrap1_s6_clk.clkr, 3618 [GCC_QUPV3_WRAP1_S6_CLK_SRC] = &gcc_qupv3_wrap1_s6_clk_src.clkr, 3619 [GCC_QUPV3_WRAP1_S7_CLK] = &gcc_qupv3_wrap1_s7_clk.clkr, 3620 [GCC_QUPV3_WRAP1_S7_CLK_SRC] = &gcc_qupv3_wrap1_s7_clk_src.clkr, 3621 [GCC_QUPV3_WRAP2_CORE_2X_CLK] = &gcc_qupv3_wrap2_core_2x_clk.clkr, 3622 [GCC_QUPV3_WRAP2_CORE_CLK] = &gcc_qupv3_wrap2_core_clk.clkr, 3623 [GCC_QUPV3_WRAP2_IBI_CTRL_0_CLK_SRC] = &gcc_qupv3_wrap2_ibi_ctrl_0_clk_src.clkr, 3624 [GCC_QUPV3_WRAP2_IBI_CTRL_2_CLK] = &gcc_qupv3_wrap2_ibi_ctrl_2_clk.clkr, 3625 [GCC_QUPV3_WRAP2_IBI_CTRL_3_CLK] = &gcc_qupv3_wrap2_ibi_ctrl_3_clk.clkr, 3626 [GCC_QUPV3_WRAP2_S0_CLK] = &gcc_qupv3_wrap2_s0_clk.clkr, 3627 [GCC_QUPV3_WRAP2_S0_CLK_SRC] = &gcc_qupv3_wrap2_s0_clk_src.clkr, 3628 [GCC_QUPV3_WRAP2_S1_CLK] = &gcc_qupv3_wrap2_s1_clk.clkr, 3629 [GCC_QUPV3_WRAP2_S1_CLK_SRC] = &gcc_qupv3_wrap2_s1_clk_src.clkr, 3630 [GCC_QUPV3_WRAP2_S2_CLK] = &gcc_qupv3_wrap2_s2_clk.clkr, 3631 [GCC_QUPV3_WRAP2_S2_CLK_SRC] = &gcc_qupv3_wrap2_s2_clk_src.clkr, 3632 [GCC_QUPV3_WRAP2_S3_CLK] = &gcc_qupv3_wrap2_s3_clk.clkr, 3633 [GCC_QUPV3_WRAP2_S3_CLK_SRC] = &gcc_qupv3_wrap2_s3_clk_src.clkr, 3634 [GCC_QUPV3_WRAP2_S4_CLK] = &gcc_qupv3_wrap2_s4_clk.clkr, 3635 [GCC_QUPV3_WRAP2_S4_CLK_SRC] = &gcc_qupv3_wrap2_s4_clk_src.clkr, 3636 [GCC_QUPV3_WRAP2_S5_CLK] = &gcc_qupv3_wrap2_s5_clk.clkr, 3637 [GCC_QUPV3_WRAP2_S5_CLK_SRC] = &gcc_qupv3_wrap2_s5_clk_src.clkr, 3638 [GCC_QUPV3_WRAP2_S6_CLK] = &gcc_qupv3_wrap2_s6_clk.clkr, 3639 [GCC_QUPV3_WRAP2_S6_CLK_SRC] = &gcc_qupv3_wrap2_s6_clk_src.clkr, 3640 [GCC_QUPV3_WRAP2_S7_CLK] = &gcc_qupv3_wrap2_s7_clk.clkr, 3641 [GCC_QUPV3_WRAP2_S7_CLK_SRC] = &gcc_qupv3_wrap2_s7_clk_src.clkr, 3642 [GCC_QUPV3_WRAP3_CORE_2X_CLK] = &gcc_qupv3_wrap3_core_2x_clk.clkr, 3643 [GCC_QUPV3_WRAP3_CORE_CLK] = &gcc_qupv3_wrap3_core_clk.clkr, 3644 [GCC_QUPV3_WRAP3_QSPI_REF_CLK] = &gcc_qupv3_wrap3_qspi_ref_clk.clkr, 3645 [GCC_QUPV3_WRAP3_QSPI_REF_CLK_SRC] = &gcc_qupv3_wrap3_qspi_ref_clk_src.clkr, 3646 [GCC_QUPV3_WRAP3_S0_CLK] = &gcc_qupv3_wrap3_s0_clk.clkr, 3647 [GCC_QUPV3_WRAP3_S0_CLK_SRC] = &gcc_qupv3_wrap3_s0_clk_src.clkr, 3648 [GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr, 3649 [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr, 3650 [GCC_QUPV3_WRAP_2_IBI_2_AHB_CLK] = &gcc_qupv3_wrap_2_ibi_2_ahb_clk.clkr, 3651 [GCC_QUPV3_WRAP_2_IBI_3_AHB_CLK] = &gcc_qupv3_wrap_2_ibi_3_ahb_clk.clkr, 3652 [GCC_QUPV3_WRAP_2_M_AHB_CLK] = &gcc_qupv3_wrap_2_m_ahb_clk.clkr, 3653 [GCC_QUPV3_WRAP_2_S_AHB_CLK] = &gcc_qupv3_wrap_2_s_ahb_clk.clkr, 3654 [GCC_QUPV3_WRAP_3_M_AHB_CLK] = &gcc_qupv3_wrap_3_m_ahb_clk.clkr, 3655 [GCC_QUPV3_WRAP_3_S_AHB_CLK] = &gcc_qupv3_wrap_3_s_ahb_clk.clkr, 3656 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, 3657 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, 3658 [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr, 3659 [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr, 3660 [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr, 3661 [GCC_SDCC4_APPS_CLK_SRC] = &gcc_sdcc4_apps_clk_src.clkr, 3662 [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr, 3663 [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr, 3664 [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr, 3665 [GCC_UFS_PHY_AXI_HW_CTL_CLK] = &gcc_ufs_phy_axi_hw_ctl_clk.clkr, 3666 [GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr, 3667 [GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr, 3668 [GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK] = &gcc_ufs_phy_ice_core_hw_ctl_clk.clkr, 3669 [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr, 3670 [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr, 3671 [GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK] = &gcc_ufs_phy_phy_aux_hw_ctl_clk.clkr, 3672 [GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr, 3673 [GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC] = &gcc_ufs_phy_rx_symbol_0_clk_src.clkr, 3674 [GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &gcc_ufs_phy_rx_symbol_1_clk.clkr, 3675 [GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC] = &gcc_ufs_phy_rx_symbol_1_clk_src.clkr, 3676 [GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr, 3677 [GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC] = &gcc_ufs_phy_tx_symbol_0_clk_src.clkr, 3678 [GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr, 3679 [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] = &gcc_ufs_phy_unipro_core_clk_src.clkr, 3680 [GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK] = &gcc_ufs_phy_unipro_core_hw_ctl_clk.clkr, 3681 [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr, 3682 [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr, 3683 [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr, 3684 [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = &gcc_usb30_prim_mock_utmi_clk_src.clkr, 3685 [GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr, 3686 [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr, 3687 [GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr, 3688 [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr, 3689 [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr, 3690 [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr, 3691 [GCC_USB3_PRIM_PHY_PIPE_CLK_SRC] = &gcc_usb3_prim_phy_pipe_clk_src.clkr, 3692 [GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr, 3693 [GCC_VIDEO_AXI1_CLK] = &gcc_video_axi1_clk.clkr, 3694 [GCC_GPLL0_AO] = &gcc_gpll0_ao.clkr, 3695 [GCC_GPLL0_OUT_EVEN_AO] = &gcc_gpll0_out_even_ao.clkr, 3696 [GCC_GPLL1_AO] = &gcc_gpll1_ao.clkr, 3697 [GCC_GPLL3_AO] = &gcc_gpll3_ao.clkr, 3698 [GCC_GPLL4_AO] = &gcc_gpll4_ao.clkr, 3699 [GCC_GPLL6_AO] = &gcc_gpll6_ao.clkr, 3700 }; 3701 3702 static const struct qcom_reset_map gcc_sm8650_resets[] = { 3703 [GCC_CAMERA_BCR] = { 0x26000 }, 3704 [GCC_DISPLAY_BCR] = { 0x27000 }, 3705 [GCC_GPU_BCR] = { 0x71000 }, 3706 [GCC_PCIE_0_BCR] = { 0x6b000 }, 3707 [GCC_PCIE_0_LINK_DOWN_BCR] = { 0x6c014 }, 3708 [GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0x6c020 }, 3709 [GCC_PCIE_0_PHY_BCR] = { 0x6c01c }, 3710 [GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR] = { 0x6c028 }, 3711 [GCC_PCIE_1_BCR] = { 0x8d000 }, 3712 [GCC_PCIE_1_LINK_DOWN_BCR] = { 0x8e014 }, 3713 [GCC_PCIE_1_NOCSR_COM_PHY_BCR] = { 0x8e020 }, 3714 [GCC_PCIE_1_PHY_BCR] = { 0x8e01c }, 3715 [GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR] = { 0x8e024 }, 3716 [GCC_PCIE_PHY_BCR] = { 0x6f000 }, 3717 [GCC_PCIE_PHY_CFG_AHB_BCR] = { 0x6f00c }, 3718 [GCC_PCIE_PHY_COM_BCR] = { 0x6f010 }, 3719 [GCC_PDM_BCR] = { 0x33000 }, 3720 [GCC_QUPV3_WRAPPER_1_BCR] = { 0x18000 }, 3721 [GCC_QUPV3_WRAPPER_2_BCR] = { 0x1e000 }, 3722 [GCC_QUPV3_WRAPPER_3_BCR] = { 0x19000 }, 3723 [GCC_QUPV3_WRAPPER_I2C_BCR] = { 0x17000 }, 3724 [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 }, 3725 [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 }, 3726 [GCC_SDCC2_BCR] = { 0x14000 }, 3727 [GCC_SDCC4_BCR] = { 0x16000 }, 3728 [GCC_UFS_PHY_BCR] = { 0x77000 }, 3729 [GCC_USB30_PRIM_BCR] = { 0x39000 }, 3730 [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 }, 3731 [GCC_USB3_DP_PHY_SEC_BCR] = { 0x50014 }, 3732 [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 }, 3733 [GCC_USB3_PHY_SEC_BCR] = { 0x5000c }, 3734 [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 }, 3735 [GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 }, 3736 [GCC_VIDEO_AXI0_CLK_ARES] = { .reg = 0x32018, .bit = 2, .udelay = 1000 }, 3737 [GCC_VIDEO_AXI1_CLK_ARES] = { .reg = 0x32024, .bit = 2, .udelay = 1000 }, 3738 [GCC_VIDEO_BCR] = { 0x32000 }, 3739 }; 3740 3741 static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = { 3742 DEFINE_RCG_DFS(gcc_qupv3_wrap1_qspi_ref_clk_src), 3743 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src), 3744 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src), 3745 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src), 3746 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src), 3747 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src), 3748 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s6_clk_src), 3749 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s7_clk_src), 3750 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s0_clk_src), 3751 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s1_clk_src), 3752 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s2_clk_src), 3753 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s3_clk_src), 3754 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s4_clk_src), 3755 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s5_clk_src), 3756 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s6_clk_src), 3757 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s7_clk_src), 3758 DEFINE_RCG_DFS(gcc_qupv3_wrap3_qspi_ref_clk_src), 3759 }; 3760 3761 static struct gdsc *gcc_sm8650_gdscs[] = { 3762 [PCIE_0_GDSC] = &pcie_0_gdsc, 3763 [PCIE_0_PHY_GDSC] = &pcie_0_phy_gdsc, 3764 [PCIE_1_GDSC] = &pcie_1_gdsc, 3765 [PCIE_1_PHY_GDSC] = &pcie_1_phy_gdsc, 3766 [UFS_PHY_GDSC] = &ufs_phy_gdsc, 3767 [UFS_MEM_PHY_GDSC] = &ufs_mem_phy_gdsc, 3768 [USB30_PRIM_GDSC] = &usb30_prim_gdsc, 3769 [USB3_PHY_GDSC] = &usb3_phy_gdsc, 3770 }; 3771 3772 static const struct regmap_config gcc_sm8650_regmap_config = { 3773 .reg_bits = 32, 3774 .reg_stride = 4, 3775 .val_bits = 32, 3776 .max_register = 0x1f41f0, 3777 .fast_io = true, 3778 }; 3779 3780 static const struct qcom_cc_desc gcc_sm8650_desc = { 3781 .config = &gcc_sm8650_regmap_config, 3782 .clks = gcc_sm8650_clocks, 3783 .num_clks = ARRAY_SIZE(gcc_sm8650_clocks), 3784 .resets = gcc_sm8650_resets, 3785 .num_resets = ARRAY_SIZE(gcc_sm8650_resets), 3786 .gdscs = gcc_sm8650_gdscs, 3787 .num_gdscs = ARRAY_SIZE(gcc_sm8650_gdscs), 3788 }; 3789 3790 static const struct of_device_id gcc_sm8650_match_table[] = { 3791 { .compatible = "qcom,sm8650-gcc" }, 3792 { } 3793 }; 3794 MODULE_DEVICE_TABLE(of, gcc_sm8650_match_table); 3795 3796 static int gcc_sm8650_probe(struct platform_device *pdev) 3797 { 3798 struct regmap *regmap; 3799 int ret; 3800 3801 regmap = qcom_cc_map(pdev, &gcc_sm8650_desc); 3802 if (IS_ERR(regmap)) 3803 return PTR_ERR(regmap); 3804 3805 ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, 3806 ARRAY_SIZE(gcc_dfs_clocks)); 3807 if (ret) 3808 return ret; 3809 3810 /* Keep some clocks always-on */ 3811 qcom_branch_set_clk_en(regmap, 0x26004); /* GCC_CAMERA_AHB_CLK */ 3812 qcom_branch_set_clk_en(regmap, 0x26028); /* GCC_CAMERA_XO_CLK */ 3813 qcom_branch_set_clk_en(regmap, 0x27004); /* GCC_DISP_AHB_CLK */ 3814 qcom_branch_set_clk_en(regmap, 0x27018); /* GCC_DISP_XO_CLK */ 3815 qcom_branch_set_clk_en(regmap, 0x71004); /* GCC_GPU_CFG_AHB_CLK */ 3816 qcom_branch_set_clk_en(regmap, 0x32004); /* GCC_VIDEO_AHB_CLK */ 3817 qcom_branch_set_clk_en(regmap, 0x32030); /* GCC_VIDEO_XO_CLK */ 3818 3819 /* FORCE_MEM_CORE_ON for ufs phy ice core and gcc ufs phy axi clocks */ 3820 qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_ice_core_clk, true); 3821 qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_axi_clk, true); 3822 3823 /* Clear GDSC_SLEEP_ENA_VOTE to stop votes being auto-removed in sleep. */ 3824 regmap_write(regmap, 0x52150, 0x0); 3825 3826 return qcom_cc_really_probe(&pdev->dev, &gcc_sm8650_desc, regmap); 3827 } 3828 3829 static struct platform_driver gcc_sm8650_driver = { 3830 .probe = gcc_sm8650_probe, 3831 .driver = { 3832 .name = "gcc-sm8650", 3833 .of_match_table = gcc_sm8650_match_table, 3834 }, 3835 }; 3836 3837 static int __init gcc_sm8650_init(void) 3838 { 3839 return platform_driver_register(&gcc_sm8650_driver); 3840 } 3841 subsys_initcall(gcc_sm8650_init); 3842 3843 static void __exit gcc_sm8650_exit(void) 3844 { 3845 platform_driver_unregister(&gcc_sm8650_driver); 3846 } 3847 module_exit(gcc_sm8650_exit); 3848 3849 MODULE_DESCRIPTION("QTI GCC SM8650 Driver"); 3850 MODULE_LICENSE("GPL"); 3851