1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 4 */ 5 6 #include <linux/clk-provider.h> 7 #include <linux/module.h> 8 #include <linux/platform_device.h> 9 #include <linux/regmap.h> 10 11 #include <dt-bindings/clock/qcom,nord-gcc.h> 12 13 #include "clk-alpha-pll.h" 14 #include "clk-branch.h" 15 #include "clk-pll.h" 16 #include "clk-rcg.h" 17 #include "clk-regmap.h" 18 #include "clk-regmap-divider.h" 19 #include "clk-regmap-mux.h" 20 #include "clk-regmap-phy-mux.h" 21 #include "common.h" 22 #include "gdsc.h" 23 #include "reset.h" 24 25 enum { 26 DT_BI_TCXO, 27 DT_SLEEP_CLK, 28 DT_PCIE_A_PIPE_CLK, 29 DT_PCIE_B_PIPE_CLK, 30 DT_PCIE_C_PIPE_CLK, 31 DT_PCIE_D_PIPE_CLK, 32 }; 33 34 enum { 35 P_BI_TCXO, 36 P_GCC_GPLL0_OUT_EVEN, 37 P_GCC_GPLL0_OUT_MAIN, 38 P_PCIE_A_PIPE_CLK, 39 P_PCIE_B_PIPE_CLK, 40 P_PCIE_C_PIPE_CLK, 41 P_PCIE_D_PIPE_CLK, 42 P_SLEEP_CLK, 43 }; 44 45 static struct clk_alpha_pll gcc_gpll0 = { 46 .offset = 0x0, 47 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 48 .clkr = { 49 .enable_reg = 0x9d020, 50 .enable_mask = BIT(0), 51 .hw.init = &(const struct clk_init_data) { 52 .name = "gcc_gpll0", 53 .parent_data = &(const struct clk_parent_data) { 54 .index = DT_BI_TCXO, 55 }, 56 .num_parents = 1, 57 .ops = &clk_alpha_pll_fixed_lucid_ole_ops, 58 }, 59 }, 60 }; 61 62 static const struct clk_div_table post_div_table_gcc_gpll0_out_even[] = { 63 { 0x1, 2 }, 64 { } 65 }; 66 67 static struct clk_alpha_pll_postdiv gcc_gpll0_out_even = { 68 .offset = 0x0, 69 .post_div_shift = 10, 70 .post_div_table = post_div_table_gcc_gpll0_out_even, 71 .num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_even), 72 .width = 4, 73 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 74 .clkr.hw.init = &(const struct clk_init_data) { 75 .name = "gcc_gpll0_out_even", 76 .parent_hws = (const struct clk_hw*[]) { 77 &gcc_gpll0.clkr.hw, 78 }, 79 .num_parents = 1, 80 .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, 81 }, 82 }; 83 84 static const struct parent_map gcc_parent_map_0[] = { 85 { P_BI_TCXO, 0 }, 86 { P_GCC_GPLL0_OUT_MAIN, 1 }, 87 { P_GCC_GPLL0_OUT_EVEN, 6 }, 88 }; 89 90 static const struct clk_parent_data gcc_parent_data_0[] = { 91 { .index = DT_BI_TCXO }, 92 { .hw = &gcc_gpll0.clkr.hw }, 93 { .hw = &gcc_gpll0_out_even.clkr.hw }, 94 }; 95 96 static const struct parent_map gcc_parent_map_1[] = { 97 { P_BI_TCXO, 0 }, 98 { P_SLEEP_CLK, 5 }, 99 }; 100 101 static const struct clk_parent_data gcc_parent_data_1[] = { 102 { .index = DT_BI_TCXO }, 103 { .index = DT_SLEEP_CLK }, 104 }; 105 106 static const struct parent_map gcc_parent_map_2[] = { 107 { P_BI_TCXO, 0 }, 108 { P_GCC_GPLL0_OUT_MAIN, 1 }, 109 { P_SLEEP_CLK, 5 }, 110 { P_GCC_GPLL0_OUT_EVEN, 6 }, 111 }; 112 113 static const struct clk_parent_data gcc_parent_data_2[] = { 114 { .index = DT_BI_TCXO }, 115 { .hw = &gcc_gpll0.clkr.hw }, 116 { .index = DT_SLEEP_CLK }, 117 { .hw = &gcc_gpll0_out_even.clkr.hw }, 118 }; 119 120 static const struct parent_map gcc_parent_map_3[] = { 121 { P_BI_TCXO, 0 }, 122 { P_GCC_GPLL0_OUT_MAIN, 1 }, 123 }; 124 125 static const struct clk_parent_data gcc_parent_data_3[] = { 126 { .index = DT_BI_TCXO }, 127 { .hw = &gcc_gpll0.clkr.hw }, 128 }; 129 130 static struct clk_regmap_phy_mux gcc_pcie_a_pipe_clk_src = { 131 .reg = 0x49094, 132 .clkr = { 133 .hw.init = &(const struct clk_init_data) { 134 .name = "gcc_pcie_a_pipe_clk_src", 135 .parent_data = &(const struct clk_parent_data){ 136 .index = DT_PCIE_A_PIPE_CLK, 137 }, 138 .num_parents = 1, 139 .ops = &clk_regmap_phy_mux_ops, 140 }, 141 }, 142 }; 143 144 static struct clk_regmap_phy_mux gcc_pcie_b_pipe_clk_src = { 145 .reg = 0x4a094, 146 .clkr = { 147 .hw.init = &(const struct clk_init_data) { 148 .name = "gcc_pcie_b_pipe_clk_src", 149 .parent_data = &(const struct clk_parent_data){ 150 .index = DT_PCIE_B_PIPE_CLK, 151 }, 152 .num_parents = 1, 153 .ops = &clk_regmap_phy_mux_ops, 154 }, 155 }, 156 }; 157 158 static struct clk_regmap_phy_mux gcc_pcie_c_pipe_clk_src = { 159 .reg = 0x4b094, 160 .clkr = { 161 .hw.init = &(const struct clk_init_data) { 162 .name = "gcc_pcie_c_pipe_clk_src", 163 .parent_data = &(const struct clk_parent_data){ 164 .index = DT_PCIE_C_PIPE_CLK, 165 }, 166 .num_parents = 1, 167 .ops = &clk_regmap_phy_mux_ops, 168 }, 169 }, 170 }; 171 172 static struct clk_regmap_phy_mux gcc_pcie_d_pipe_clk_src = { 173 .reg = 0x4c094, 174 .clkr = { 175 .hw.init = &(const struct clk_init_data) { 176 .name = "gcc_pcie_d_pipe_clk_src", 177 .parent_data = &(const struct clk_parent_data){ 178 .index = DT_PCIE_D_PIPE_CLK, 179 }, 180 .num_parents = 1, 181 .ops = &clk_regmap_phy_mux_ops, 182 }, 183 }, 184 }; 185 186 static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = { 187 F(66666667, P_GCC_GPLL0_OUT_MAIN, 9, 0, 0), 188 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 189 F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0), 190 { } 191 }; 192 193 static struct clk_rcg2 gcc_gp1_clk_src = { 194 .cmd_rcgr = 0x30004, 195 .mnd_width = 16, 196 .hid_width = 5, 197 .parent_map = gcc_parent_map_2, 198 .freq_tbl = ftbl_gcc_gp1_clk_src, 199 .hw_clk_ctrl = true, 200 .clkr.hw.init = &(const struct clk_init_data) { 201 .name = "gcc_gp1_clk_src", 202 .parent_data = gcc_parent_data_2, 203 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 204 .flags = CLK_SET_RATE_PARENT, 205 .ops = &clk_rcg2_shared_ops, 206 }, 207 }; 208 209 static struct clk_rcg2 gcc_gp2_clk_src = { 210 .cmd_rcgr = 0x31004, 211 .mnd_width = 16, 212 .hid_width = 5, 213 .parent_map = gcc_parent_map_2, 214 .freq_tbl = ftbl_gcc_gp1_clk_src, 215 .hw_clk_ctrl = true, 216 .clkr.hw.init = &(const struct clk_init_data) { 217 .name = "gcc_gp2_clk_src", 218 .parent_data = gcc_parent_data_2, 219 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 220 .flags = CLK_SET_RATE_PARENT, 221 .ops = &clk_rcg2_shared_ops, 222 }, 223 }; 224 225 static const struct freq_tbl ftbl_gcc_pcie_a_aux_clk_src[] = { 226 F(19200000, P_BI_TCXO, 1, 0, 0), 227 { } 228 }; 229 230 static struct clk_rcg2 gcc_pcie_a_aux_clk_src = { 231 .cmd_rcgr = 0x49098, 232 .mnd_width = 16, 233 .hid_width = 5, 234 .parent_map = gcc_parent_map_1, 235 .freq_tbl = ftbl_gcc_pcie_a_aux_clk_src, 236 .hw_clk_ctrl = true, 237 .clkr.hw.init = &(const struct clk_init_data) { 238 .name = "gcc_pcie_a_aux_clk_src", 239 .parent_data = gcc_parent_data_1, 240 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 241 .flags = CLK_SET_RATE_PARENT, 242 .ops = &clk_rcg2_shared_ops, 243 }, 244 }; 245 246 static struct clk_rcg2 gcc_pcie_a_phy_aux_clk_src = { 247 .cmd_rcgr = 0x4d020, 248 .mnd_width = 16, 249 .hid_width = 5, 250 .parent_map = gcc_parent_map_1, 251 .freq_tbl = ftbl_gcc_pcie_a_aux_clk_src, 252 .hw_clk_ctrl = true, 253 .clkr.hw.init = &(const struct clk_init_data) { 254 .name = "gcc_pcie_a_phy_aux_clk_src", 255 .parent_data = gcc_parent_data_1, 256 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 257 .flags = CLK_SET_RATE_PARENT, 258 .ops = &clk_rcg2_shared_ops, 259 }, 260 }; 261 262 static const struct freq_tbl ftbl_gcc_pcie_a_phy_rchng_clk_src[] = { 263 F(66666667, P_GCC_GPLL0_OUT_MAIN, 9, 0, 0), 264 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 265 { } 266 }; 267 268 static struct clk_rcg2 gcc_pcie_a_phy_rchng_clk_src = { 269 .cmd_rcgr = 0x4907c, 270 .mnd_width = 0, 271 .hid_width = 5, 272 .parent_map = gcc_parent_map_0, 273 .freq_tbl = ftbl_gcc_pcie_a_phy_rchng_clk_src, 274 .hw_clk_ctrl = true, 275 .clkr.hw.init = &(const struct clk_init_data) { 276 .name = "gcc_pcie_a_phy_rchng_clk_src", 277 .parent_data = gcc_parent_data_0, 278 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 279 .flags = CLK_SET_RATE_PARENT, 280 .ops = &clk_rcg2_shared_ops, 281 }, 282 }; 283 284 static struct clk_rcg2 gcc_pcie_b_aux_clk_src = { 285 .cmd_rcgr = 0x4a098, 286 .mnd_width = 16, 287 .hid_width = 5, 288 .parent_map = gcc_parent_map_1, 289 .freq_tbl = ftbl_gcc_pcie_a_aux_clk_src, 290 .hw_clk_ctrl = true, 291 .clkr.hw.init = &(const struct clk_init_data) { 292 .name = "gcc_pcie_b_aux_clk_src", 293 .parent_data = gcc_parent_data_1, 294 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 295 .flags = CLK_SET_RATE_PARENT, 296 .ops = &clk_rcg2_shared_ops, 297 }, 298 }; 299 300 static struct clk_rcg2 gcc_pcie_b_phy_aux_clk_src = { 301 .cmd_rcgr = 0x4e020, 302 .mnd_width = 16, 303 .hid_width = 5, 304 .parent_map = gcc_parent_map_1, 305 .freq_tbl = ftbl_gcc_pcie_a_aux_clk_src, 306 .hw_clk_ctrl = true, 307 .clkr.hw.init = &(const struct clk_init_data) { 308 .name = "gcc_pcie_b_phy_aux_clk_src", 309 .parent_data = gcc_parent_data_1, 310 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 311 .flags = CLK_SET_RATE_PARENT, 312 .ops = &clk_rcg2_shared_ops, 313 }, 314 }; 315 316 static struct clk_rcg2 gcc_pcie_b_phy_rchng_clk_src = { 317 .cmd_rcgr = 0x4a07c, 318 .mnd_width = 0, 319 .hid_width = 5, 320 .parent_map = gcc_parent_map_0, 321 .freq_tbl = ftbl_gcc_pcie_a_phy_rchng_clk_src, 322 .hw_clk_ctrl = true, 323 .clkr.hw.init = &(const struct clk_init_data) { 324 .name = "gcc_pcie_b_phy_rchng_clk_src", 325 .parent_data = gcc_parent_data_0, 326 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 327 .flags = CLK_SET_RATE_PARENT, 328 .ops = &clk_rcg2_shared_ops, 329 }, 330 }; 331 332 static struct clk_rcg2 gcc_pcie_c_aux_clk_src = { 333 .cmd_rcgr = 0x4b098, 334 .mnd_width = 16, 335 .hid_width = 5, 336 .parent_map = gcc_parent_map_1, 337 .freq_tbl = ftbl_gcc_pcie_a_aux_clk_src, 338 .hw_clk_ctrl = true, 339 .clkr.hw.init = &(const struct clk_init_data) { 340 .name = "gcc_pcie_c_aux_clk_src", 341 .parent_data = gcc_parent_data_1, 342 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 343 .flags = CLK_SET_RATE_PARENT, 344 .ops = &clk_rcg2_shared_ops, 345 }, 346 }; 347 348 static struct clk_rcg2 gcc_pcie_c_phy_aux_clk_src = { 349 .cmd_rcgr = 0x4f020, 350 .mnd_width = 16, 351 .hid_width = 5, 352 .parent_map = gcc_parent_map_1, 353 .freq_tbl = ftbl_gcc_pcie_a_aux_clk_src, 354 .hw_clk_ctrl = true, 355 .clkr.hw.init = &(const struct clk_init_data) { 356 .name = "gcc_pcie_c_phy_aux_clk_src", 357 .parent_data = gcc_parent_data_1, 358 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 359 .flags = CLK_SET_RATE_PARENT, 360 .ops = &clk_rcg2_shared_ops, 361 }, 362 }; 363 364 static struct clk_rcg2 gcc_pcie_c_phy_rchng_clk_src = { 365 .cmd_rcgr = 0x4b07c, 366 .mnd_width = 0, 367 .hid_width = 5, 368 .parent_map = gcc_parent_map_3, 369 .freq_tbl = ftbl_gcc_pcie_a_phy_rchng_clk_src, 370 .hw_clk_ctrl = true, 371 .clkr.hw.init = &(const struct clk_init_data) { 372 .name = "gcc_pcie_c_phy_rchng_clk_src", 373 .parent_data = gcc_parent_data_3, 374 .num_parents = ARRAY_SIZE(gcc_parent_data_3), 375 .flags = CLK_SET_RATE_PARENT, 376 .ops = &clk_rcg2_shared_ops, 377 }, 378 }; 379 380 static struct clk_rcg2 gcc_pcie_d_aux_clk_src = { 381 .cmd_rcgr = 0x4c098, 382 .mnd_width = 16, 383 .hid_width = 5, 384 .parent_map = gcc_parent_map_1, 385 .freq_tbl = ftbl_gcc_pcie_a_aux_clk_src, 386 .hw_clk_ctrl = true, 387 .clkr.hw.init = &(const struct clk_init_data) { 388 .name = "gcc_pcie_d_aux_clk_src", 389 .parent_data = gcc_parent_data_1, 390 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 391 .flags = CLK_SET_RATE_PARENT, 392 .ops = &clk_rcg2_shared_ops, 393 }, 394 }; 395 396 static struct clk_rcg2 gcc_pcie_d_phy_aux_clk_src = { 397 .cmd_rcgr = 0x50020, 398 .mnd_width = 16, 399 .hid_width = 5, 400 .parent_map = gcc_parent_map_1, 401 .freq_tbl = ftbl_gcc_pcie_a_aux_clk_src, 402 .hw_clk_ctrl = true, 403 .clkr.hw.init = &(const struct clk_init_data) { 404 .name = "gcc_pcie_d_phy_aux_clk_src", 405 .parent_data = gcc_parent_data_1, 406 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 407 .flags = CLK_SET_RATE_PARENT, 408 .ops = &clk_rcg2_shared_ops, 409 }, 410 }; 411 412 static struct clk_rcg2 gcc_pcie_d_phy_rchng_clk_src = { 413 .cmd_rcgr = 0x4c07c, 414 .mnd_width = 0, 415 .hid_width = 5, 416 .parent_map = gcc_parent_map_3, 417 .freq_tbl = ftbl_gcc_pcie_a_phy_rchng_clk_src, 418 .hw_clk_ctrl = true, 419 .clkr.hw.init = &(const struct clk_init_data) { 420 .name = "gcc_pcie_d_phy_rchng_clk_src", 421 .parent_data = gcc_parent_data_3, 422 .num_parents = ARRAY_SIZE(gcc_parent_data_3), 423 .flags = CLK_SET_RATE_PARENT, 424 .ops = &clk_rcg2_shared_ops, 425 }, 426 }; 427 428 static struct clk_rcg2 gcc_pcie_noc_refgen_clk_src = { 429 .cmd_rcgr = 0x52094, 430 .mnd_width = 0, 431 .hid_width = 5, 432 .parent_map = gcc_parent_map_0, 433 .freq_tbl = ftbl_gcc_pcie_a_aux_clk_src, 434 .hw_clk_ctrl = true, 435 .clkr.hw.init = &(const struct clk_init_data) { 436 .name = "gcc_pcie_noc_refgen_clk_src", 437 .parent_data = gcc_parent_data_0, 438 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 439 .flags = CLK_SET_RATE_PARENT, 440 .ops = &clk_rcg2_shared_ops, 441 }, 442 }; 443 444 static struct clk_rcg2 gcc_pcie_noc_safety_clk_src = { 445 .cmd_rcgr = 0x520ac, 446 .mnd_width = 0, 447 .hid_width = 5, 448 .parent_map = gcc_parent_map_0, 449 .freq_tbl = ftbl_gcc_pcie_a_aux_clk_src, 450 .hw_clk_ctrl = true, 451 .clkr.hw.init = &(const struct clk_init_data) { 452 .name = "gcc_pcie_noc_safety_clk_src", 453 .parent_data = gcc_parent_data_0, 454 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 455 .flags = CLK_SET_RATE_PARENT, 456 .ops = &clk_rcg2_shared_ops, 457 }, 458 }; 459 460 static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = { 461 F(40000000, P_GCC_GPLL0_OUT_MAIN, 15, 0, 0), 462 F(60000000, P_GCC_GPLL0_OUT_MAIN, 10, 0, 0), 463 { } 464 }; 465 466 static struct clk_rcg2 gcc_pdm2_clk_src = { 467 .cmd_rcgr = 0x1a010, 468 .mnd_width = 0, 469 .hid_width = 5, 470 .parent_map = gcc_parent_map_0, 471 .freq_tbl = ftbl_gcc_pdm2_clk_src, 472 .hw_clk_ctrl = true, 473 .clkr.hw.init = &(const struct clk_init_data) { 474 .name = "gcc_pdm2_clk_src", 475 .parent_data = gcc_parent_data_0, 476 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 477 .flags = CLK_SET_RATE_PARENT, 478 .ops = &clk_rcg2_shared_ops, 479 }, 480 }; 481 482 static const struct freq_tbl ftbl_gcc_qupv3_wrap3_qspi_ref_clk_src[] = { 483 F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625), 484 F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625), 485 F(19200000, P_BI_TCXO, 1, 0, 0), 486 F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625), 487 F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75), 488 F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25), 489 F(51200000, P_GCC_GPLL0_OUT_EVEN, 1, 64, 375), 490 F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75), 491 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), 492 F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15), 493 F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25), 494 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 495 F(102400000, P_GCC_GPLL0_OUT_EVEN, 1, 128, 375), 496 F(112000000, P_GCC_GPLL0_OUT_EVEN, 1, 28, 75), 497 F(117964800, P_GCC_GPLL0_OUT_EVEN, 1, 6144, 15625), 498 F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0), 499 F(150000000, P_GCC_GPLL0_OUT_EVEN, 2, 0, 0), 500 F(240000000, P_GCC_GPLL0_OUT_MAIN, 2.5, 0, 0), 501 { } 502 }; 503 504 static struct clk_init_data gcc_qupv3_wrap3_qspi_ref_clk_src_init = { 505 .name = "gcc_qupv3_wrap3_qspi_ref_clk_src", 506 .parent_data = gcc_parent_data_0, 507 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 508 .flags = CLK_SET_RATE_PARENT, 509 .ops = &clk_rcg2_shared_no_init_park_ops, 510 }; 511 512 static struct clk_rcg2 gcc_qupv3_wrap3_qspi_ref_clk_src = { 513 .cmd_rcgr = 0x23174, 514 .mnd_width = 16, 515 .hid_width = 5, 516 .parent_map = gcc_parent_map_0, 517 .freq_tbl = ftbl_gcc_qupv3_wrap3_qspi_ref_clk_src, 518 .hw_clk_ctrl = true, 519 .clkr.hw.init = &gcc_qupv3_wrap3_qspi_ref_clk_src_init, 520 }; 521 522 static struct clk_regmap_div gcc_qupv3_wrap3_s0_clk_src = { 523 .reg = 0x2316c, 524 .shift = 0, 525 .width = 4, 526 .clkr.hw.init = &(const struct clk_init_data) { 527 .name = "gcc_qupv3_wrap3_s0_clk_src", 528 .parent_hws = (const struct clk_hw*[]) { 529 &gcc_qupv3_wrap3_qspi_ref_clk_src.clkr.hw, 530 }, 531 .num_parents = 1, 532 .flags = CLK_SET_RATE_PARENT, 533 .ops = &clk_regmap_div_ro_ops, 534 }, 535 }; 536 537 static struct clk_branch gcc_boot_rom_ahb_clk = { 538 .halt_reg = 0x1f004, 539 .halt_check = BRANCH_HALT, 540 .clkr = { 541 .enable_reg = 0x1f004, 542 .enable_mask = BIT(0), 543 .hw.init = &(const struct clk_init_data) { 544 .name = "gcc_boot_rom_ahb_clk", 545 .ops = &clk_branch2_ops, 546 }, 547 }, 548 }; 549 550 static struct clk_branch gcc_gp1_clk = { 551 .halt_reg = 0x30000, 552 .halt_check = BRANCH_HALT, 553 .clkr = { 554 .enable_reg = 0x30000, 555 .enable_mask = BIT(0), 556 .hw.init = &(const struct clk_init_data) { 557 .name = "gcc_gp1_clk", 558 .parent_hws = (const struct clk_hw*[]) { 559 &gcc_gp1_clk_src.clkr.hw, 560 }, 561 .num_parents = 1, 562 .flags = CLK_SET_RATE_PARENT, 563 .ops = &clk_branch2_ops, 564 }, 565 }, 566 }; 567 568 static struct clk_branch gcc_gp2_clk = { 569 .halt_reg = 0x31000, 570 .halt_check = BRANCH_HALT, 571 .clkr = { 572 .enable_reg = 0x31000, 573 .enable_mask = BIT(0), 574 .hw.init = &(const struct clk_init_data) { 575 .name = "gcc_gp2_clk", 576 .parent_hws = (const struct clk_hw*[]) { 577 &gcc_gp2_clk_src.clkr.hw, 578 }, 579 .num_parents = 1, 580 .flags = CLK_SET_RATE_PARENT, 581 .ops = &clk_branch2_ops, 582 }, 583 }, 584 }; 585 586 static struct clk_branch gcc_mmu_0_tcu_vote_clk = { 587 .halt_reg = 0x7d094, 588 .halt_check = BRANCH_HALT_VOTED, 589 .clkr = { 590 .enable_reg = 0x7d094, 591 .enable_mask = BIT(0), 592 .hw.init = &(const struct clk_init_data) { 593 .name = "gcc_mmu_0_tcu_vote_clk", 594 .ops = &clk_branch2_ops, 595 }, 596 }, 597 }; 598 599 static struct clk_branch gcc_pcie_a_aux_clk = { 600 .halt_reg = 0x49058, 601 .halt_check = BRANCH_HALT_VOTED, 602 .hwcg_reg = 0x49058, 603 .hwcg_bit = 1, 604 .clkr = { 605 .enable_reg = 0x9d008, 606 .enable_mask = BIT(14), 607 .hw.init = &(const struct clk_init_data) { 608 .name = "gcc_pcie_a_aux_clk", 609 .parent_hws = (const struct clk_hw*[]) { 610 &gcc_pcie_a_aux_clk_src.clkr.hw, 611 }, 612 .num_parents = 1, 613 .flags = CLK_SET_RATE_PARENT, 614 .ops = &clk_branch2_ops, 615 }, 616 }, 617 }; 618 619 static struct clk_branch gcc_pcie_a_cfg_ahb_clk = { 620 .halt_reg = 0x49054, 621 .halt_check = BRANCH_HALT_VOTED, 622 .hwcg_reg = 0x49054, 623 .hwcg_bit = 1, 624 .clkr = { 625 .enable_reg = 0x9d008, 626 .enable_mask = BIT(13), 627 .hw.init = &(const struct clk_init_data) { 628 .name = "gcc_pcie_a_cfg_ahb_clk", 629 .ops = &clk_branch2_ops, 630 }, 631 }, 632 }; 633 634 static struct clk_branch gcc_pcie_a_dti_qtc_clk = { 635 .halt_reg = 0x49018, 636 .halt_check = BRANCH_HALT_SKIP, 637 .hwcg_reg = 0x49018, 638 .hwcg_bit = 1, 639 .clkr = { 640 .enable_reg = 0x9d008, 641 .enable_mask = BIT(8), 642 .hw.init = &(const struct clk_init_data) { 643 .name = "gcc_pcie_a_dti_qtc_clk", 644 .ops = &clk_branch2_ops, 645 }, 646 }, 647 }; 648 649 static struct clk_branch gcc_pcie_a_mstr_axi_clk = { 650 .halt_reg = 0x49040, 651 .halt_check = BRANCH_HALT_SKIP, 652 .hwcg_reg = 0x49040, 653 .hwcg_bit = 1, 654 .clkr = { 655 .enable_reg = 0x9d008, 656 .enable_mask = BIT(12), 657 .hw.init = &(const struct clk_init_data) { 658 .name = "gcc_pcie_a_mstr_axi_clk", 659 .ops = &clk_branch2_ops, 660 }, 661 }, 662 }; 663 664 static struct clk_branch gcc_pcie_a_phy_aux_clk = { 665 .halt_reg = 0x4d01c, 666 .halt_check = BRANCH_HALT_VOTED, 667 .clkr = { 668 .enable_reg = 0x9d010, 669 .enable_mask = BIT(12), 670 .hw.init = &(const struct clk_init_data) { 671 .name = "gcc_pcie_a_phy_aux_clk", 672 .parent_hws = (const struct clk_hw*[]) { 673 &gcc_pcie_a_phy_aux_clk_src.clkr.hw, 674 }, 675 .num_parents = 1, 676 .flags = CLK_SET_RATE_PARENT, 677 .ops = &clk_branch2_ops, 678 }, 679 }, 680 }; 681 682 static struct clk_branch gcc_pcie_a_phy_rchng_clk = { 683 .halt_reg = 0x49078, 684 .halt_check = BRANCH_HALT_VOTED, 685 .hwcg_reg = 0x49078, 686 .hwcg_bit = 1, 687 .clkr = { 688 .enable_reg = 0x9d008, 689 .enable_mask = BIT(16), 690 .hw.init = &(const struct clk_init_data) { 691 .name = "gcc_pcie_a_phy_rchng_clk", 692 .parent_hws = (const struct clk_hw*[]) { 693 &gcc_pcie_a_phy_rchng_clk_src.clkr.hw, 694 }, 695 .num_parents = 1, 696 .flags = CLK_SET_RATE_PARENT, 697 .ops = &clk_branch2_ops, 698 }, 699 }, 700 }; 701 702 static struct clk_branch gcc_pcie_a_pipe_clk = { 703 .halt_reg = 0x49068, 704 .halt_check = BRANCH_HALT_SKIP, 705 .hwcg_reg = 0x49068, 706 .hwcg_bit = 1, 707 .clkr = { 708 .enable_reg = 0x9d008, 709 .enable_mask = BIT(15), 710 .hw.init = &(const struct clk_init_data) { 711 .name = "gcc_pcie_a_pipe_clk", 712 .parent_hws = (const struct clk_hw*[]) { 713 &gcc_pcie_a_pipe_clk_src.clkr.hw, 714 }, 715 .num_parents = 1, 716 .flags = CLK_SET_RATE_PARENT, 717 .ops = &clk_branch2_ops, 718 }, 719 }, 720 }; 721 722 static struct clk_branch gcc_pcie_a_slv_axi_clk = { 723 .halt_reg = 0x4902c, 724 .halt_check = BRANCH_HALT_VOTED, 725 .hwcg_reg = 0x4902c, 726 .hwcg_bit = 1, 727 .clkr = { 728 .enable_reg = 0x9d008, 729 .enable_mask = BIT(11), 730 .hw.init = &(const struct clk_init_data) { 731 .name = "gcc_pcie_a_slv_axi_clk", 732 .ops = &clk_branch2_ops, 733 }, 734 }, 735 }; 736 737 static struct clk_branch gcc_pcie_a_slv_q2a_axi_clk = { 738 .halt_reg = 0x49024, 739 .halt_check = BRANCH_HALT_VOTED, 740 .hwcg_reg = 0x49024, 741 .hwcg_bit = 1, 742 .clkr = { 743 .enable_reg = 0x9d008, 744 .enable_mask = BIT(10), 745 .hw.init = &(const struct clk_init_data) { 746 .name = "gcc_pcie_a_slv_q2a_axi_clk", 747 .ops = &clk_branch2_ops, 748 }, 749 }, 750 }; 751 752 static struct clk_branch gcc_pcie_b_aux_clk = { 753 .halt_reg = 0x4a058, 754 .halt_check = BRANCH_HALT_VOTED, 755 .clkr = { 756 .enable_reg = 0x9d008, 757 .enable_mask = BIT(23), 758 .hw.init = &(const struct clk_init_data) { 759 .name = "gcc_pcie_b_aux_clk", 760 .parent_hws = (const struct clk_hw*[]) { 761 &gcc_pcie_b_aux_clk_src.clkr.hw, 762 }, 763 .num_parents = 1, 764 .flags = CLK_SET_RATE_PARENT, 765 .ops = &clk_branch2_ops, 766 }, 767 }, 768 }; 769 770 static struct clk_branch gcc_pcie_b_cfg_ahb_clk = { 771 .halt_reg = 0x4a054, 772 .halt_check = BRANCH_HALT_VOTED, 773 .hwcg_reg = 0x4a054, 774 .hwcg_bit = 1, 775 .clkr = { 776 .enable_reg = 0x9d008, 777 .enable_mask = BIT(22), 778 .hw.init = &(const struct clk_init_data) { 779 .name = "gcc_pcie_b_cfg_ahb_clk", 780 .ops = &clk_branch2_ops, 781 }, 782 }, 783 }; 784 785 static struct clk_branch gcc_pcie_b_dti_qtc_clk = { 786 .halt_reg = 0x4a018, 787 .halt_check = BRANCH_HALT_SKIP, 788 .hwcg_reg = 0x4a018, 789 .hwcg_bit = 1, 790 .clkr = { 791 .enable_reg = 0x9d008, 792 .enable_mask = BIT(17), 793 .hw.init = &(const struct clk_init_data) { 794 .name = "gcc_pcie_b_dti_qtc_clk", 795 .ops = &clk_branch2_ops, 796 }, 797 }, 798 }; 799 800 static struct clk_branch gcc_pcie_b_mstr_axi_clk = { 801 .halt_reg = 0x4a040, 802 .halt_check = BRANCH_HALT_SKIP, 803 .hwcg_reg = 0x4a040, 804 .hwcg_bit = 1, 805 .clkr = { 806 .enable_reg = 0x9d008, 807 .enable_mask = BIT(21), 808 .hw.init = &(const struct clk_init_data) { 809 .name = "gcc_pcie_b_mstr_axi_clk", 810 .ops = &clk_branch2_ops, 811 }, 812 }, 813 }; 814 815 static struct clk_branch gcc_pcie_b_phy_aux_clk = { 816 .halt_reg = 0x4e01c, 817 .halt_check = BRANCH_HALT_VOTED, 818 .clkr = { 819 .enable_reg = 0x9d010, 820 .enable_mask = BIT(13), 821 .hw.init = &(const struct clk_init_data) { 822 .name = "gcc_pcie_b_phy_aux_clk", 823 .parent_hws = (const struct clk_hw*[]) { 824 &gcc_pcie_b_phy_aux_clk_src.clkr.hw, 825 }, 826 .num_parents = 1, 827 .flags = CLK_SET_RATE_PARENT, 828 .ops = &clk_branch2_ops, 829 }, 830 }, 831 }; 832 833 static struct clk_branch gcc_pcie_b_phy_rchng_clk = { 834 .halt_reg = 0x4a078, 835 .halt_check = BRANCH_HALT_VOTED, 836 .clkr = { 837 .enable_reg = 0x9d008, 838 .enable_mask = BIT(25), 839 .hw.init = &(const struct clk_init_data) { 840 .name = "gcc_pcie_b_phy_rchng_clk", 841 .parent_hws = (const struct clk_hw*[]) { 842 &gcc_pcie_b_phy_rchng_clk_src.clkr.hw, 843 }, 844 .num_parents = 1, 845 .flags = CLK_SET_RATE_PARENT, 846 .ops = &clk_branch2_ops, 847 }, 848 }, 849 }; 850 851 static struct clk_branch gcc_pcie_b_pipe_clk = { 852 .halt_reg = 0x4a068, 853 .halt_check = BRANCH_HALT_SKIP, 854 .clkr = { 855 .enable_reg = 0x9d008, 856 .enable_mask = BIT(24), 857 .hw.init = &(const struct clk_init_data) { 858 .name = "gcc_pcie_b_pipe_clk", 859 .parent_hws = (const struct clk_hw*[]) { 860 &gcc_pcie_b_pipe_clk_src.clkr.hw, 861 }, 862 .num_parents = 1, 863 .flags = CLK_SET_RATE_PARENT, 864 .ops = &clk_branch2_ops, 865 }, 866 }, 867 }; 868 869 static struct clk_branch gcc_pcie_b_slv_axi_clk = { 870 .halt_reg = 0x4a02c, 871 .halt_check = BRANCH_HALT_VOTED, 872 .hwcg_reg = 0x4a02c, 873 .hwcg_bit = 1, 874 .clkr = { 875 .enable_reg = 0x9d008, 876 .enable_mask = BIT(20), 877 .hw.init = &(const struct clk_init_data) { 878 .name = "gcc_pcie_b_slv_axi_clk", 879 .ops = &clk_branch2_ops, 880 }, 881 }, 882 }; 883 884 static struct clk_branch gcc_pcie_b_slv_q2a_axi_clk = { 885 .halt_reg = 0x4a024, 886 .halt_check = BRANCH_HALT_VOTED, 887 .clkr = { 888 .enable_reg = 0x9d008, 889 .enable_mask = BIT(19), 890 .hw.init = &(const struct clk_init_data) { 891 .name = "gcc_pcie_b_slv_q2a_axi_clk", 892 .ops = &clk_branch2_ops, 893 }, 894 }, 895 }; 896 897 static struct clk_branch gcc_pcie_c_aux_clk = { 898 .halt_reg = 0x4b058, 899 .halt_check = BRANCH_HALT_VOTED, 900 .clkr = { 901 .enable_reg = 0x9d010, 902 .enable_mask = BIT(0), 903 .hw.init = &(const struct clk_init_data) { 904 .name = "gcc_pcie_c_aux_clk", 905 .parent_hws = (const struct clk_hw*[]) { 906 &gcc_pcie_c_aux_clk_src.clkr.hw, 907 }, 908 .num_parents = 1, 909 .flags = CLK_SET_RATE_PARENT, 910 .ops = &clk_branch2_ops, 911 }, 912 }, 913 }; 914 915 static struct clk_branch gcc_pcie_c_cfg_ahb_clk = { 916 .halt_reg = 0x4b054, 917 .halt_check = BRANCH_HALT_VOTED, 918 .hwcg_reg = 0x4b054, 919 .hwcg_bit = 1, 920 .clkr = { 921 .enable_reg = 0x9d008, 922 .enable_mask = BIT(31), 923 .hw.init = &(const struct clk_init_data) { 924 .name = "gcc_pcie_c_cfg_ahb_clk", 925 .ops = &clk_branch2_ops, 926 }, 927 }, 928 }; 929 930 static struct clk_branch gcc_pcie_c_dti_qtc_clk = { 931 .halt_reg = 0x4b018, 932 .halt_check = BRANCH_HALT_SKIP, 933 .hwcg_reg = 0x4b018, 934 .hwcg_bit = 1, 935 .clkr = { 936 .enable_reg = 0x9d008, 937 .enable_mask = BIT(26), 938 .hw.init = &(const struct clk_init_data) { 939 .name = "gcc_pcie_c_dti_qtc_clk", 940 .ops = &clk_branch2_ops, 941 }, 942 }, 943 }; 944 945 static struct clk_branch gcc_pcie_c_mstr_axi_clk = { 946 .halt_reg = 0x4b040, 947 .halt_check = BRANCH_HALT_SKIP, 948 .hwcg_reg = 0x4b040, 949 .hwcg_bit = 1, 950 .clkr = { 951 .enable_reg = 0x9d008, 952 .enable_mask = BIT(30), 953 .hw.init = &(const struct clk_init_data) { 954 .name = "gcc_pcie_c_mstr_axi_clk", 955 .ops = &clk_branch2_ops, 956 }, 957 }, 958 }; 959 960 static struct clk_branch gcc_pcie_c_phy_aux_clk = { 961 .halt_reg = 0x4f01c, 962 .halt_check = BRANCH_HALT_VOTED, 963 .clkr = { 964 .enable_reg = 0x9d010, 965 .enable_mask = BIT(14), 966 .hw.init = &(const struct clk_init_data) { 967 .name = "gcc_pcie_c_phy_aux_clk", 968 .parent_hws = (const struct clk_hw*[]) { 969 &gcc_pcie_c_phy_aux_clk_src.clkr.hw, 970 }, 971 .num_parents = 1, 972 .flags = CLK_SET_RATE_PARENT, 973 .ops = &clk_branch2_ops, 974 }, 975 }, 976 }; 977 978 static struct clk_branch gcc_pcie_c_phy_rchng_clk = { 979 .halt_reg = 0x4b078, 980 .halt_check = BRANCH_HALT_VOTED, 981 .clkr = { 982 .enable_reg = 0x9d010, 983 .enable_mask = BIT(2), 984 .hw.init = &(const struct clk_init_data) { 985 .name = "gcc_pcie_c_phy_rchng_clk", 986 .parent_hws = (const struct clk_hw*[]) { 987 &gcc_pcie_c_phy_rchng_clk_src.clkr.hw, 988 }, 989 .num_parents = 1, 990 .flags = CLK_SET_RATE_PARENT, 991 .ops = &clk_branch2_ops, 992 }, 993 }, 994 }; 995 996 static struct clk_branch gcc_pcie_c_pipe_clk = { 997 .halt_reg = 0x4b068, 998 .halt_check = BRANCH_HALT_SKIP, 999 .clkr = { 1000 .enable_reg = 0x9d010, 1001 .enable_mask = BIT(1), 1002 .hw.init = &(const struct clk_init_data) { 1003 .name = "gcc_pcie_c_pipe_clk", 1004 .parent_hws = (const struct clk_hw*[]) { 1005 &gcc_pcie_c_pipe_clk_src.clkr.hw, 1006 }, 1007 .num_parents = 1, 1008 .flags = CLK_SET_RATE_PARENT, 1009 .ops = &clk_branch2_ops, 1010 }, 1011 }, 1012 }; 1013 1014 static struct clk_branch gcc_pcie_c_slv_axi_clk = { 1015 .halt_reg = 0x4b02c, 1016 .halt_check = BRANCH_HALT_VOTED, 1017 .hwcg_reg = 0x4b02c, 1018 .hwcg_bit = 1, 1019 .clkr = { 1020 .enable_reg = 0x9d008, 1021 .enable_mask = BIT(29), 1022 .hw.init = &(const struct clk_init_data) { 1023 .name = "gcc_pcie_c_slv_axi_clk", 1024 .ops = &clk_branch2_ops, 1025 }, 1026 }, 1027 }; 1028 1029 static struct clk_branch gcc_pcie_c_slv_q2a_axi_clk = { 1030 .halt_reg = 0x4b024, 1031 .halt_check = BRANCH_HALT_VOTED, 1032 .clkr = { 1033 .enable_reg = 0x9d008, 1034 .enable_mask = BIT(28), 1035 .hw.init = &(const struct clk_init_data) { 1036 .name = "gcc_pcie_c_slv_q2a_axi_clk", 1037 .ops = &clk_branch2_ops, 1038 }, 1039 }, 1040 }; 1041 1042 static struct clk_branch gcc_pcie_d_aux_clk = { 1043 .halt_reg = 0x4c058, 1044 .halt_check = BRANCH_HALT_VOTED, 1045 .clkr = { 1046 .enable_reg = 0x9d010, 1047 .enable_mask = BIT(9), 1048 .hw.init = &(const struct clk_init_data) { 1049 .name = "gcc_pcie_d_aux_clk", 1050 .parent_hws = (const struct clk_hw*[]) { 1051 &gcc_pcie_d_aux_clk_src.clkr.hw, 1052 }, 1053 .num_parents = 1, 1054 .flags = CLK_SET_RATE_PARENT, 1055 .ops = &clk_branch2_ops, 1056 }, 1057 }, 1058 }; 1059 1060 static struct clk_branch gcc_pcie_d_cfg_ahb_clk = { 1061 .halt_reg = 0x4c054, 1062 .halt_check = BRANCH_HALT_VOTED, 1063 .hwcg_reg = 0x4c054, 1064 .hwcg_bit = 1, 1065 .clkr = { 1066 .enable_reg = 0x9d010, 1067 .enable_mask = BIT(8), 1068 .hw.init = &(const struct clk_init_data) { 1069 .name = "gcc_pcie_d_cfg_ahb_clk", 1070 .ops = &clk_branch2_ops, 1071 }, 1072 }, 1073 }; 1074 1075 static struct clk_branch gcc_pcie_d_dti_qtc_clk = { 1076 .halt_reg = 0x4c018, 1077 .halt_check = BRANCH_HALT_SKIP, 1078 .hwcg_reg = 0x4c018, 1079 .hwcg_bit = 1, 1080 .clkr = { 1081 .enable_reg = 0x9d010, 1082 .enable_mask = BIT(3), 1083 .hw.init = &(const struct clk_init_data) { 1084 .name = "gcc_pcie_d_dti_qtc_clk", 1085 .ops = &clk_branch2_ops, 1086 }, 1087 }, 1088 }; 1089 1090 static struct clk_branch gcc_pcie_d_mstr_axi_clk = { 1091 .halt_reg = 0x4c040, 1092 .halt_check = BRANCH_HALT_SKIP, 1093 .hwcg_reg = 0x4c040, 1094 .hwcg_bit = 1, 1095 .clkr = { 1096 .enable_reg = 0x9d010, 1097 .enable_mask = BIT(7), 1098 .hw.init = &(const struct clk_init_data) { 1099 .name = "gcc_pcie_d_mstr_axi_clk", 1100 .ops = &clk_branch2_ops, 1101 }, 1102 }, 1103 }; 1104 1105 static struct clk_branch gcc_pcie_d_phy_aux_clk = { 1106 .halt_reg = 0x5001c, 1107 .halt_check = BRANCH_HALT_VOTED, 1108 .clkr = { 1109 .enable_reg = 0x9d010, 1110 .enable_mask = BIT(16), 1111 .hw.init = &(const struct clk_init_data) { 1112 .name = "gcc_pcie_d_phy_aux_clk", 1113 .parent_hws = (const struct clk_hw*[]) { 1114 &gcc_pcie_d_phy_aux_clk_src.clkr.hw, 1115 }, 1116 .num_parents = 1, 1117 .flags = CLK_SET_RATE_PARENT, 1118 .ops = &clk_branch2_ops, 1119 }, 1120 }, 1121 }; 1122 1123 static struct clk_branch gcc_pcie_d_phy_rchng_clk = { 1124 .halt_reg = 0x4c078, 1125 .halt_check = BRANCH_HALT_VOTED, 1126 .clkr = { 1127 .enable_reg = 0x9d010, 1128 .enable_mask = BIT(11), 1129 .hw.init = &(const struct clk_init_data) { 1130 .name = "gcc_pcie_d_phy_rchng_clk", 1131 .parent_hws = (const struct clk_hw*[]) { 1132 &gcc_pcie_d_phy_rchng_clk_src.clkr.hw, 1133 }, 1134 .num_parents = 1, 1135 .flags = CLK_SET_RATE_PARENT, 1136 .ops = &clk_branch2_ops, 1137 }, 1138 }, 1139 }; 1140 1141 static struct clk_branch gcc_pcie_d_pipe_clk = { 1142 .halt_reg = 0x4c068, 1143 .halt_check = BRANCH_HALT_SKIP, 1144 .clkr = { 1145 .enable_reg = 0x9d010, 1146 .enable_mask = BIT(10), 1147 .hw.init = &(const struct clk_init_data) { 1148 .name = "gcc_pcie_d_pipe_clk", 1149 .parent_hws = (const struct clk_hw*[]) { 1150 &gcc_pcie_d_pipe_clk_src.clkr.hw, 1151 }, 1152 .num_parents = 1, 1153 .flags = CLK_SET_RATE_PARENT, 1154 .ops = &clk_branch2_ops, 1155 }, 1156 }, 1157 }; 1158 1159 static struct clk_branch gcc_pcie_d_slv_axi_clk = { 1160 .halt_reg = 0x4c02c, 1161 .halt_check = BRANCH_HALT_VOTED, 1162 .hwcg_reg = 0x4c02c, 1163 .hwcg_bit = 1, 1164 .clkr = { 1165 .enable_reg = 0x9d010, 1166 .enable_mask = BIT(6), 1167 .hw.init = &(const struct clk_init_data) { 1168 .name = "gcc_pcie_d_slv_axi_clk", 1169 .ops = &clk_branch2_ops, 1170 }, 1171 }, 1172 }; 1173 1174 static struct clk_branch gcc_pcie_d_slv_q2a_axi_clk = { 1175 .halt_reg = 0x4c024, 1176 .halt_check = BRANCH_HALT_VOTED, 1177 .clkr = { 1178 .enable_reg = 0x9d010, 1179 .enable_mask = BIT(5), 1180 .hw.init = &(const struct clk_init_data) { 1181 .name = "gcc_pcie_d_slv_q2a_axi_clk", 1182 .ops = &clk_branch2_ops, 1183 }, 1184 }, 1185 }; 1186 1187 static struct clk_branch gcc_pcie_noc_async_bridge_clk = { 1188 .halt_reg = 0x52048, 1189 .halt_check = BRANCH_HALT_SKIP, 1190 .hwcg_reg = 0x52048, 1191 .hwcg_bit = 1, 1192 .clkr = { 1193 .enable_reg = 0x9d018, 1194 .enable_mask = BIT(18), 1195 .hw.init = &(const struct clk_init_data) { 1196 .name = "gcc_pcie_noc_async_bridge_clk", 1197 .ops = &clk_branch2_ops, 1198 }, 1199 }, 1200 }; 1201 1202 static struct clk_branch gcc_pcie_noc_cnoc_sf_qx_clk = { 1203 .halt_reg = 0x52040, 1204 .halt_check = BRANCH_HALT_VOTED, 1205 .hwcg_reg = 0x52040, 1206 .hwcg_bit = 1, 1207 .clkr = { 1208 .enable_reg = 0x9d010, 1209 .enable_mask = BIT(24), 1210 .hw.init = &(const struct clk_init_data) { 1211 .name = "gcc_pcie_noc_cnoc_sf_qx_clk", 1212 .ops = &clk_branch2_ops, 1213 }, 1214 }, 1215 }; 1216 1217 static struct clk_branch gcc_pcie_noc_m_cfg_clk = { 1218 .halt_reg = 0x52060, 1219 .halt_check = BRANCH_HALT_VOTED, 1220 .hwcg_reg = 0x52060, 1221 .hwcg_bit = 1, 1222 .clkr = { 1223 .enable_reg = 0x9d018, 1224 .enable_mask = BIT(4), 1225 .hw.init = &(const struct clk_init_data) { 1226 .name = "gcc_pcie_noc_m_cfg_clk", 1227 .ops = &clk_branch2_ops, 1228 }, 1229 }, 1230 }; 1231 1232 static struct clk_branch gcc_pcie_noc_m_pdb_clk = { 1233 .halt_reg = 0x52084, 1234 .halt_check = BRANCH_HALT_VOTED, 1235 .hwcg_reg = 0x52084, 1236 .hwcg_bit = 1, 1237 .clkr = { 1238 .enable_reg = 0x9d018, 1239 .enable_mask = BIT(8), 1240 .hw.init = &(const struct clk_init_data) { 1241 .name = "gcc_pcie_noc_m_pdb_clk", 1242 .ops = &clk_branch2_ops, 1243 }, 1244 }, 1245 }; 1246 1247 static struct clk_branch gcc_pcie_noc_mstr_axi_clk = { 1248 .halt_reg = 0x52050, 1249 .halt_check = BRANCH_HALT_SKIP, 1250 .hwcg_reg = 0x52050, 1251 .hwcg_bit = 1, 1252 .clkr = { 1253 .enable_reg = 0x9d010, 1254 .enable_mask = BIT(25), 1255 .hw.init = &(const struct clk_init_data) { 1256 .name = "gcc_pcie_noc_mstr_axi_clk", 1257 .ops = &clk_branch2_ops, 1258 }, 1259 }, 1260 }; 1261 1262 static struct clk_branch gcc_pcie_noc_pwrctl_clk = { 1263 .halt_reg = 0x52080, 1264 .halt_check = BRANCH_HALT_VOTED, 1265 .clkr = { 1266 .enable_reg = 0x9d018, 1267 .enable_mask = BIT(7), 1268 .hw.init = &(const struct clk_init_data) { 1269 .name = "gcc_pcie_noc_pwrctl_clk", 1270 .ops = &clk_branch2_ops, 1271 }, 1272 }, 1273 }; 1274 1275 static struct clk_branch gcc_pcie_noc_qosgen_extref_clk = { 1276 .halt_reg = 0x52074, 1277 .halt_check = BRANCH_HALT_VOTED, 1278 .clkr = { 1279 .enable_reg = 0x9d010, 1280 .enable_mask = BIT(19), 1281 .hw.init = &(const struct clk_init_data) { 1282 .name = "gcc_pcie_noc_qosgen_extref_clk", 1283 .ops = &clk_branch2_ops, 1284 }, 1285 }, 1286 }; 1287 1288 static struct clk_branch gcc_pcie_noc_refgen_clk = { 1289 .halt_reg = 0x52078, 1290 .halt_check = BRANCH_HALT, 1291 .clkr = { 1292 .enable_reg = 0x52078, 1293 .enable_mask = BIT(0), 1294 .hw.init = &(const struct clk_init_data) { 1295 .name = "gcc_pcie_noc_refgen_clk", 1296 .parent_hws = (const struct clk_hw*[]) { 1297 &gcc_pcie_noc_refgen_clk_src.clkr.hw, 1298 }, 1299 .num_parents = 1, 1300 .flags = CLK_SET_RATE_PARENT, 1301 .ops = &clk_branch2_ops, 1302 }, 1303 }, 1304 }; 1305 1306 static struct clk_branch gcc_pcie_noc_s_cfg_clk = { 1307 .halt_reg = 0x52064, 1308 .halt_check = BRANCH_HALT_VOTED, 1309 .clkr = { 1310 .enable_reg = 0x9d018, 1311 .enable_mask = BIT(5), 1312 .hw.init = &(const struct clk_init_data) { 1313 .name = "gcc_pcie_noc_s_cfg_clk", 1314 .ops = &clk_branch2_ops, 1315 }, 1316 }, 1317 }; 1318 1319 static struct clk_branch gcc_pcie_noc_s_pdb_clk = { 1320 .halt_reg = 0x5208c, 1321 .halt_check = BRANCH_HALT_VOTED, 1322 .hwcg_reg = 0x5208c, 1323 .hwcg_bit = 1, 1324 .clkr = { 1325 .enable_reg = 0x9d018, 1326 .enable_mask = BIT(9), 1327 .hw.init = &(const struct clk_init_data) { 1328 .name = "gcc_pcie_noc_s_pdb_clk", 1329 .ops = &clk_branch2_ops, 1330 }, 1331 }, 1332 }; 1333 1334 static struct clk_branch gcc_pcie_noc_safety_clk = { 1335 .halt_reg = 0x5207c, 1336 .halt_check = BRANCH_HALT, 1337 .clkr = { 1338 .enable_reg = 0x5207c, 1339 .enable_mask = BIT(0), 1340 .hw.init = &(const struct clk_init_data) { 1341 .name = "gcc_pcie_noc_safety_clk", 1342 .parent_hws = (const struct clk_hw*[]) { 1343 &gcc_pcie_noc_safety_clk_src.clkr.hw, 1344 }, 1345 .num_parents = 1, 1346 .flags = CLK_SET_RATE_PARENT, 1347 .ops = &clk_branch2_ops, 1348 }, 1349 }, 1350 }; 1351 1352 static struct clk_branch gcc_pcie_noc_slave_axi_clk = { 1353 .halt_reg = 0x52058, 1354 .halt_check = BRANCH_HALT_VOTED, 1355 .hwcg_reg = 0x52058, 1356 .hwcg_bit = 1, 1357 .clkr = { 1358 .enable_reg = 0x9d010, 1359 .enable_mask = BIT(26), 1360 .hw.init = &(const struct clk_init_data) { 1361 .name = "gcc_pcie_noc_slave_axi_clk", 1362 .ops = &clk_branch2_ops, 1363 }, 1364 }, 1365 }; 1366 1367 static struct clk_branch gcc_pcie_noc_tsctr_clk = { 1368 .halt_reg = 0x52070, 1369 .halt_check = BRANCH_HALT_VOTED, 1370 .clkr = { 1371 .enable_reg = 0x9d010, 1372 .enable_mask = BIT(18), 1373 .hw.init = &(const struct clk_init_data) { 1374 .name = "gcc_pcie_noc_tsctr_clk", 1375 .ops = &clk_branch2_ops, 1376 }, 1377 }, 1378 }; 1379 1380 static struct clk_branch gcc_pcie_noc_xo_clk = { 1381 .halt_reg = 0x52068, 1382 .halt_check = BRANCH_HALT_VOTED, 1383 .clkr = { 1384 .enable_reg = 0x9d018, 1385 .enable_mask = BIT(6), 1386 .hw.init = &(const struct clk_init_data) { 1387 .name = "gcc_pcie_noc_xo_clk", 1388 .ops = &clk_branch2_ops, 1389 }, 1390 }, 1391 }; 1392 1393 static struct clk_branch gcc_pdm2_clk = { 1394 .halt_reg = 0x1a00c, 1395 .halt_check = BRANCH_HALT, 1396 .clkr = { 1397 .enable_reg = 0x1a00c, 1398 .enable_mask = BIT(0), 1399 .hw.init = &(const struct clk_init_data) { 1400 .name = "gcc_pdm2_clk", 1401 .parent_hws = (const struct clk_hw*[]) { 1402 &gcc_pdm2_clk_src.clkr.hw, 1403 }, 1404 .num_parents = 1, 1405 .flags = CLK_SET_RATE_PARENT, 1406 .ops = &clk_branch2_ops, 1407 }, 1408 }, 1409 }; 1410 1411 static struct clk_branch gcc_pdm_ahb_clk = { 1412 .halt_reg = 0x1a004, 1413 .halt_check = BRANCH_HALT_VOTED, 1414 .hwcg_reg = 0x1a004, 1415 .hwcg_bit = 1, 1416 .clkr = { 1417 .enable_reg = 0x1a004, 1418 .enable_mask = BIT(0), 1419 .hw.init = &(const struct clk_init_data) { 1420 .name = "gcc_pdm_ahb_clk", 1421 .ops = &clk_branch2_ops, 1422 }, 1423 }, 1424 }; 1425 1426 static struct clk_branch gcc_pdm_xo4_clk = { 1427 .halt_reg = 0x1a008, 1428 .halt_check = BRANCH_HALT, 1429 .clkr = { 1430 .enable_reg = 0x1a008, 1431 .enable_mask = BIT(0), 1432 .hw.init = &(const struct clk_init_data) { 1433 .name = "gcc_pdm_xo4_clk", 1434 .ops = &clk_branch2_ops, 1435 }, 1436 }, 1437 }; 1438 1439 static struct clk_branch gcc_qupv3_wrap3_core_2x_clk = { 1440 .halt_reg = 0x23020, 1441 .halt_check = BRANCH_HALT_VOTED, 1442 .clkr = { 1443 .enable_reg = 0x9d000, 1444 .enable_mask = BIT(24), 1445 .hw.init = &(const struct clk_init_data) { 1446 .name = "gcc_qupv3_wrap3_core_2x_clk", 1447 .ops = &clk_branch2_ops, 1448 }, 1449 }, 1450 }; 1451 1452 static struct clk_branch gcc_qupv3_wrap3_core_clk = { 1453 .halt_reg = 0x2300c, 1454 .halt_check = BRANCH_HALT_VOTED, 1455 .clkr = { 1456 .enable_reg = 0x9d000, 1457 .enable_mask = BIT(23), 1458 .hw.init = &(const struct clk_init_data) { 1459 .name = "gcc_qupv3_wrap3_core_clk", 1460 .ops = &clk_branch2_ops, 1461 }, 1462 }, 1463 }; 1464 1465 static struct clk_branch gcc_qupv3_wrap3_m_clk = { 1466 .halt_reg = 0x23004, 1467 .halt_check = BRANCH_HALT_VOTED, 1468 .hwcg_reg = 0x23004, 1469 .hwcg_bit = 1, 1470 .clkr = { 1471 .enable_reg = 0x9d000, 1472 .enable_mask = BIT(22), 1473 .hw.init = &(const struct clk_init_data) { 1474 .name = "gcc_qupv3_wrap3_m_clk", 1475 .ops = &clk_branch2_ops, 1476 }, 1477 }, 1478 }; 1479 1480 static struct clk_branch gcc_qupv3_wrap3_qspi_ref_clk = { 1481 .halt_reg = 0x23170, 1482 .halt_check = BRANCH_HALT_VOTED, 1483 .clkr = { 1484 .enable_reg = 0x9d000, 1485 .enable_mask = BIT(26), 1486 .hw.init = &(const struct clk_init_data) { 1487 .name = "gcc_qupv3_wrap3_qspi_ref_clk", 1488 .parent_hws = (const struct clk_hw*[]) { 1489 &gcc_qupv3_wrap3_qspi_ref_clk_src.clkr.hw, 1490 }, 1491 .num_parents = 1, 1492 .flags = CLK_SET_RATE_PARENT, 1493 .ops = &clk_branch2_ops, 1494 }, 1495 }, 1496 }; 1497 1498 static struct clk_branch gcc_qupv3_wrap3_s0_clk = { 1499 .halt_reg = 0x2315c, 1500 .halt_check = BRANCH_HALT_VOTED, 1501 .clkr = { 1502 .enable_reg = 0x9d000, 1503 .enable_mask = BIT(25), 1504 .hw.init = &(const struct clk_init_data) { 1505 .name = "gcc_qupv3_wrap3_s0_clk", 1506 .parent_hws = (const struct clk_hw*[]) { 1507 &gcc_qupv3_wrap3_s0_clk_src.clkr.hw, 1508 }, 1509 .num_parents = 1, 1510 .flags = CLK_SET_RATE_PARENT, 1511 .ops = &clk_branch2_ops, 1512 }, 1513 }, 1514 }; 1515 1516 static struct clk_branch gcc_qupv3_wrap3_s_ahb_clk = { 1517 .halt_reg = 0x23008, 1518 .halt_check = BRANCH_HALT_VOTED, 1519 .hwcg_reg = 0x23008, 1520 .hwcg_bit = 1, 1521 .clkr = { 1522 .enable_reg = 0x9d010, 1523 .enable_mask = BIT(15), 1524 .hw.init = &(const struct clk_init_data) { 1525 .name = "gcc_qupv3_wrap3_s_ahb_clk", 1526 .ops = &clk_branch2_ops, 1527 }, 1528 }, 1529 }; 1530 1531 static struct clk_branch gcc_smmu_pcie_qtc_vote_clk = { 1532 .halt_reg = 0x7d0b8, 1533 .halt_check = BRANCH_HALT_VOTED, 1534 .clkr = { 1535 .enable_reg = 0x7d0b8, 1536 .enable_mask = BIT(0), 1537 .hw.init = &(const struct clk_init_data) { 1538 .name = "gcc_smmu_pcie_qtc_vote_clk", 1539 .ops = &clk_branch2_ops, 1540 }, 1541 }, 1542 }; 1543 1544 static struct gdsc gcc_pcie_a_gdsc = { 1545 .gdscr = 0x49004, 1546 .en_rest_wait_val = 0x2, 1547 .en_few_wait_val = 0x2, 1548 .clk_dis_wait_val = 0xf, 1549 .collapse_ctrl = 0x8d02c, 1550 .collapse_mask = BIT(1), 1551 .pd = { 1552 .name = "gcc_pcie_a_gdsc", 1553 }, 1554 .pwrsts = PWRSTS_OFF_ON, 1555 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, 1556 }; 1557 1558 static struct gdsc gcc_pcie_a_phy_gdsc = { 1559 .gdscr = 0x4d004, 1560 .en_rest_wait_val = 0x2, 1561 .en_few_wait_val = 0x2, 1562 .clk_dis_wait_val = 0x2, 1563 .collapse_ctrl = 0x8d02c, 1564 .collapse_mask = BIT(5), 1565 .pd = { 1566 .name = "gcc_pcie_a_phy_gdsc", 1567 }, 1568 .pwrsts = PWRSTS_OFF_ON, 1569 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, 1570 }; 1571 1572 static struct gdsc gcc_pcie_b_gdsc = { 1573 .gdscr = 0x4a004, 1574 .en_rest_wait_val = 0x2, 1575 .en_few_wait_val = 0x2, 1576 .clk_dis_wait_val = 0xf, 1577 .collapse_ctrl = 0x8d02c, 1578 .collapse_mask = BIT(2), 1579 .pd = { 1580 .name = "gcc_pcie_b_gdsc", 1581 }, 1582 .pwrsts = PWRSTS_OFF_ON, 1583 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, 1584 }; 1585 1586 static struct gdsc gcc_pcie_b_phy_gdsc = { 1587 .gdscr = 0x4e004, 1588 .en_rest_wait_val = 0x2, 1589 .en_few_wait_val = 0x2, 1590 .clk_dis_wait_val = 0x2, 1591 .collapse_ctrl = 0x8d02c, 1592 .collapse_mask = BIT(6), 1593 .pd = { 1594 .name = "gcc_pcie_b_phy_gdsc", 1595 }, 1596 .pwrsts = PWRSTS_OFF_ON, 1597 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, 1598 }; 1599 1600 static struct gdsc gcc_pcie_c_gdsc = { 1601 .gdscr = 0x4b004, 1602 .en_rest_wait_val = 0x2, 1603 .en_few_wait_val = 0x2, 1604 .clk_dis_wait_val = 0xf, 1605 .collapse_ctrl = 0x8d02c, 1606 .collapse_mask = BIT(3), 1607 .pd = { 1608 .name = "gcc_pcie_c_gdsc", 1609 }, 1610 .pwrsts = PWRSTS_OFF_ON, 1611 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, 1612 }; 1613 1614 static struct gdsc gcc_pcie_c_phy_gdsc = { 1615 .gdscr = 0x4f004, 1616 .en_rest_wait_val = 0x2, 1617 .en_few_wait_val = 0x2, 1618 .clk_dis_wait_val = 0x2, 1619 .collapse_ctrl = 0x8d02c, 1620 .collapse_mask = BIT(7), 1621 .pd = { 1622 .name = "gcc_pcie_c_phy_gdsc", 1623 }, 1624 .pwrsts = PWRSTS_OFF_ON, 1625 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, 1626 }; 1627 1628 static struct gdsc gcc_pcie_d_gdsc = { 1629 .gdscr = 0x4c004, 1630 .en_rest_wait_val = 0x2, 1631 .en_few_wait_val = 0x2, 1632 .clk_dis_wait_val = 0xf, 1633 .collapse_ctrl = 0x8d02c, 1634 .collapse_mask = BIT(4), 1635 .pd = { 1636 .name = "gcc_pcie_d_gdsc", 1637 }, 1638 .pwrsts = PWRSTS_OFF_ON, 1639 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, 1640 }; 1641 1642 static struct gdsc gcc_pcie_d_phy_gdsc = { 1643 .gdscr = 0x50004, 1644 .en_rest_wait_val = 0x2, 1645 .en_few_wait_val = 0x2, 1646 .clk_dis_wait_val = 0x2, 1647 .collapse_ctrl = 0x8d02c, 1648 .collapse_mask = BIT(8), 1649 .pd = { 1650 .name = "gcc_pcie_d_phy_gdsc", 1651 }, 1652 .pwrsts = PWRSTS_OFF_ON, 1653 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, 1654 }; 1655 1656 static struct gdsc gcc_pcie_noc_gdsc = { 1657 .gdscr = 0x52004, 1658 .gds_hw_ctrl = 0x52018, 1659 .en_rest_wait_val = 0x2, 1660 .en_few_wait_val = 0x2, 1661 .clk_dis_wait_val = 0xf, 1662 .collapse_ctrl = 0x8d02c, 1663 .collapse_mask = BIT(0), 1664 .pd = { 1665 .name = "gcc_pcie_noc_gdsc", 1666 }, 1667 .pwrsts = PWRSTS_OFF_ON, 1668 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, 1669 }; 1670 1671 static struct clk_regmap *gcc_nord_clocks[] = { 1672 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, 1673 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, 1674 [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr, 1675 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, 1676 [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr, 1677 [GCC_GPLL0] = &gcc_gpll0.clkr, 1678 [GCC_GPLL0_OUT_EVEN] = &gcc_gpll0_out_even.clkr, 1679 [GCC_MMU_0_TCU_VOTE_CLK] = &gcc_mmu_0_tcu_vote_clk.clkr, 1680 [GCC_PCIE_A_AUX_CLK] = &gcc_pcie_a_aux_clk.clkr, 1681 [GCC_PCIE_A_AUX_CLK_SRC] = &gcc_pcie_a_aux_clk_src.clkr, 1682 [GCC_PCIE_A_CFG_AHB_CLK] = &gcc_pcie_a_cfg_ahb_clk.clkr, 1683 [GCC_PCIE_A_DTI_QTC_CLK] = &gcc_pcie_a_dti_qtc_clk.clkr, 1684 [GCC_PCIE_A_MSTR_AXI_CLK] = &gcc_pcie_a_mstr_axi_clk.clkr, 1685 [GCC_PCIE_A_PHY_AUX_CLK] = &gcc_pcie_a_phy_aux_clk.clkr, 1686 [GCC_PCIE_A_PHY_AUX_CLK_SRC] = &gcc_pcie_a_phy_aux_clk_src.clkr, 1687 [GCC_PCIE_A_PHY_RCHNG_CLK] = &gcc_pcie_a_phy_rchng_clk.clkr, 1688 [GCC_PCIE_A_PHY_RCHNG_CLK_SRC] = &gcc_pcie_a_phy_rchng_clk_src.clkr, 1689 [GCC_PCIE_A_PIPE_CLK] = &gcc_pcie_a_pipe_clk.clkr, 1690 [GCC_PCIE_A_PIPE_CLK_SRC] = &gcc_pcie_a_pipe_clk_src.clkr, 1691 [GCC_PCIE_A_SLV_AXI_CLK] = &gcc_pcie_a_slv_axi_clk.clkr, 1692 [GCC_PCIE_A_SLV_Q2A_AXI_CLK] = &gcc_pcie_a_slv_q2a_axi_clk.clkr, 1693 [GCC_PCIE_B_AUX_CLK] = &gcc_pcie_b_aux_clk.clkr, 1694 [GCC_PCIE_B_AUX_CLK_SRC] = &gcc_pcie_b_aux_clk_src.clkr, 1695 [GCC_PCIE_B_CFG_AHB_CLK] = &gcc_pcie_b_cfg_ahb_clk.clkr, 1696 [GCC_PCIE_B_DTI_QTC_CLK] = &gcc_pcie_b_dti_qtc_clk.clkr, 1697 [GCC_PCIE_B_MSTR_AXI_CLK] = &gcc_pcie_b_mstr_axi_clk.clkr, 1698 [GCC_PCIE_B_PHY_AUX_CLK] = &gcc_pcie_b_phy_aux_clk.clkr, 1699 [GCC_PCIE_B_PHY_AUX_CLK_SRC] = &gcc_pcie_b_phy_aux_clk_src.clkr, 1700 [GCC_PCIE_B_PHY_RCHNG_CLK] = &gcc_pcie_b_phy_rchng_clk.clkr, 1701 [GCC_PCIE_B_PHY_RCHNG_CLK_SRC] = &gcc_pcie_b_phy_rchng_clk_src.clkr, 1702 [GCC_PCIE_B_PIPE_CLK] = &gcc_pcie_b_pipe_clk.clkr, 1703 [GCC_PCIE_B_PIPE_CLK_SRC] = &gcc_pcie_b_pipe_clk_src.clkr, 1704 [GCC_PCIE_B_SLV_AXI_CLK] = &gcc_pcie_b_slv_axi_clk.clkr, 1705 [GCC_PCIE_B_SLV_Q2A_AXI_CLK] = &gcc_pcie_b_slv_q2a_axi_clk.clkr, 1706 [GCC_PCIE_C_AUX_CLK] = &gcc_pcie_c_aux_clk.clkr, 1707 [GCC_PCIE_C_AUX_CLK_SRC] = &gcc_pcie_c_aux_clk_src.clkr, 1708 [GCC_PCIE_C_CFG_AHB_CLK] = &gcc_pcie_c_cfg_ahb_clk.clkr, 1709 [GCC_PCIE_C_DTI_QTC_CLK] = &gcc_pcie_c_dti_qtc_clk.clkr, 1710 [GCC_PCIE_C_MSTR_AXI_CLK] = &gcc_pcie_c_mstr_axi_clk.clkr, 1711 [GCC_PCIE_C_PHY_AUX_CLK] = &gcc_pcie_c_phy_aux_clk.clkr, 1712 [GCC_PCIE_C_PHY_AUX_CLK_SRC] = &gcc_pcie_c_phy_aux_clk_src.clkr, 1713 [GCC_PCIE_C_PHY_RCHNG_CLK] = &gcc_pcie_c_phy_rchng_clk.clkr, 1714 [GCC_PCIE_C_PHY_RCHNG_CLK_SRC] = &gcc_pcie_c_phy_rchng_clk_src.clkr, 1715 [GCC_PCIE_C_PIPE_CLK] = &gcc_pcie_c_pipe_clk.clkr, 1716 [GCC_PCIE_C_PIPE_CLK_SRC] = &gcc_pcie_c_pipe_clk_src.clkr, 1717 [GCC_PCIE_C_SLV_AXI_CLK] = &gcc_pcie_c_slv_axi_clk.clkr, 1718 [GCC_PCIE_C_SLV_Q2A_AXI_CLK] = &gcc_pcie_c_slv_q2a_axi_clk.clkr, 1719 [GCC_PCIE_D_AUX_CLK] = &gcc_pcie_d_aux_clk.clkr, 1720 [GCC_PCIE_D_AUX_CLK_SRC] = &gcc_pcie_d_aux_clk_src.clkr, 1721 [GCC_PCIE_D_CFG_AHB_CLK] = &gcc_pcie_d_cfg_ahb_clk.clkr, 1722 [GCC_PCIE_D_DTI_QTC_CLK] = &gcc_pcie_d_dti_qtc_clk.clkr, 1723 [GCC_PCIE_D_MSTR_AXI_CLK] = &gcc_pcie_d_mstr_axi_clk.clkr, 1724 [GCC_PCIE_D_PHY_AUX_CLK] = &gcc_pcie_d_phy_aux_clk.clkr, 1725 [GCC_PCIE_D_PHY_AUX_CLK_SRC] = &gcc_pcie_d_phy_aux_clk_src.clkr, 1726 [GCC_PCIE_D_PHY_RCHNG_CLK] = &gcc_pcie_d_phy_rchng_clk.clkr, 1727 [GCC_PCIE_D_PHY_RCHNG_CLK_SRC] = &gcc_pcie_d_phy_rchng_clk_src.clkr, 1728 [GCC_PCIE_D_PIPE_CLK] = &gcc_pcie_d_pipe_clk.clkr, 1729 [GCC_PCIE_D_PIPE_CLK_SRC] = &gcc_pcie_d_pipe_clk_src.clkr, 1730 [GCC_PCIE_D_SLV_AXI_CLK] = &gcc_pcie_d_slv_axi_clk.clkr, 1731 [GCC_PCIE_D_SLV_Q2A_AXI_CLK] = &gcc_pcie_d_slv_q2a_axi_clk.clkr, 1732 [GCC_PCIE_NOC_ASYNC_BRIDGE_CLK] = &gcc_pcie_noc_async_bridge_clk.clkr, 1733 [GCC_PCIE_NOC_CNOC_SF_QX_CLK] = &gcc_pcie_noc_cnoc_sf_qx_clk.clkr, 1734 [GCC_PCIE_NOC_M_CFG_CLK] = &gcc_pcie_noc_m_cfg_clk.clkr, 1735 [GCC_PCIE_NOC_M_PDB_CLK] = &gcc_pcie_noc_m_pdb_clk.clkr, 1736 [GCC_PCIE_NOC_MSTR_AXI_CLK] = &gcc_pcie_noc_mstr_axi_clk.clkr, 1737 [GCC_PCIE_NOC_PWRCTL_CLK] = &gcc_pcie_noc_pwrctl_clk.clkr, 1738 [GCC_PCIE_NOC_QOSGEN_EXTREF_CLK] = &gcc_pcie_noc_qosgen_extref_clk.clkr, 1739 [GCC_PCIE_NOC_REFGEN_CLK] = &gcc_pcie_noc_refgen_clk.clkr, 1740 [GCC_PCIE_NOC_REFGEN_CLK_SRC] = &gcc_pcie_noc_refgen_clk_src.clkr, 1741 [GCC_PCIE_NOC_S_CFG_CLK] = &gcc_pcie_noc_s_cfg_clk.clkr, 1742 [GCC_PCIE_NOC_S_PDB_CLK] = &gcc_pcie_noc_s_pdb_clk.clkr, 1743 [GCC_PCIE_NOC_SAFETY_CLK] = &gcc_pcie_noc_safety_clk.clkr, 1744 [GCC_PCIE_NOC_SAFETY_CLK_SRC] = &gcc_pcie_noc_safety_clk_src.clkr, 1745 [GCC_PCIE_NOC_SLAVE_AXI_CLK] = &gcc_pcie_noc_slave_axi_clk.clkr, 1746 [GCC_PCIE_NOC_TSCTR_CLK] = &gcc_pcie_noc_tsctr_clk.clkr, 1747 [GCC_PCIE_NOC_XO_CLK] = &gcc_pcie_noc_xo_clk.clkr, 1748 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, 1749 [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr, 1750 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, 1751 [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr, 1752 [GCC_QUPV3_WRAP3_CORE_2X_CLK] = &gcc_qupv3_wrap3_core_2x_clk.clkr, 1753 [GCC_QUPV3_WRAP3_CORE_CLK] = &gcc_qupv3_wrap3_core_clk.clkr, 1754 [GCC_QUPV3_WRAP3_M_CLK] = &gcc_qupv3_wrap3_m_clk.clkr, 1755 [GCC_QUPV3_WRAP3_QSPI_REF_CLK] = &gcc_qupv3_wrap3_qspi_ref_clk.clkr, 1756 [GCC_QUPV3_WRAP3_QSPI_REF_CLK_SRC] = &gcc_qupv3_wrap3_qspi_ref_clk_src.clkr, 1757 [GCC_QUPV3_WRAP3_S0_CLK] = &gcc_qupv3_wrap3_s0_clk.clkr, 1758 [GCC_QUPV3_WRAP3_S0_CLK_SRC] = &gcc_qupv3_wrap3_s0_clk_src.clkr, 1759 [GCC_QUPV3_WRAP3_S_AHB_CLK] = &gcc_qupv3_wrap3_s_ahb_clk.clkr, 1760 [GCC_SMMU_PCIE_QTC_VOTE_CLK] = &gcc_smmu_pcie_qtc_vote_clk.clkr, 1761 }; 1762 1763 static struct gdsc *gcc_nord_gdscs[] = { 1764 [GCC_PCIE_A_GDSC] = &gcc_pcie_a_gdsc, 1765 [GCC_PCIE_A_PHY_GDSC] = &gcc_pcie_a_phy_gdsc, 1766 [GCC_PCIE_B_GDSC] = &gcc_pcie_b_gdsc, 1767 [GCC_PCIE_B_PHY_GDSC] = &gcc_pcie_b_phy_gdsc, 1768 [GCC_PCIE_C_GDSC] = &gcc_pcie_c_gdsc, 1769 [GCC_PCIE_C_PHY_GDSC] = &gcc_pcie_c_phy_gdsc, 1770 [GCC_PCIE_D_GDSC] = &gcc_pcie_d_gdsc, 1771 [GCC_PCIE_D_PHY_GDSC] = &gcc_pcie_d_phy_gdsc, 1772 [GCC_PCIE_NOC_GDSC] = &gcc_pcie_noc_gdsc, 1773 }; 1774 1775 static const struct qcom_reset_map gcc_nord_resets[] = { 1776 [GCC_PCIE_A_BCR] = { 0x49000 }, 1777 [GCC_PCIE_A_LINK_DOWN_BCR] = { 0xb9000 }, 1778 [GCC_PCIE_A_NOCSR_COM_PHY_BCR] = { 0xb900c }, 1779 [GCC_PCIE_A_PHY_BCR] = { 0x4d000 }, 1780 [GCC_PCIE_A_PHY_CFG_AHB_BCR] = { 0xb9014 }, 1781 [GCC_PCIE_A_PHY_COM_BCR] = { 0xb9018 }, 1782 [GCC_PCIE_A_PHY_NOCSR_COM_PHY_BCR] = { 0xb9010 }, 1783 [GCC_PCIE_B_BCR] = { 0x4a000 }, 1784 [GCC_PCIE_B_LINK_DOWN_BCR] = { 0xba000 }, 1785 [GCC_PCIE_B_NOCSR_COM_PHY_BCR] = { 0xba008 }, 1786 [GCC_PCIE_B_PHY_BCR] = { 0x4e000 }, 1787 [GCC_PCIE_B_PHY_CFG_AHB_BCR] = { 0xba010 }, 1788 [GCC_PCIE_B_PHY_COM_BCR] = { 0xba014 }, 1789 [GCC_PCIE_B_PHY_NOCSR_COM_PHY_BCR] = { 0xba00c }, 1790 [GCC_PCIE_C_BCR] = { 0x4b000 }, 1791 [GCC_PCIE_C_LINK_DOWN_BCR] = { 0xbb07c }, 1792 [GCC_PCIE_C_NOCSR_COM_PHY_BCR] = { 0xbb084 }, 1793 [GCC_PCIE_C_PHY_BCR] = { 0x4f000 }, 1794 [GCC_PCIE_C_PHY_CFG_AHB_BCR] = { 0xbb08c }, 1795 [GCC_PCIE_C_PHY_COM_BCR] = { 0xbb090 }, 1796 [GCC_PCIE_C_PHY_NOCSR_COM_PHY_BCR] = { 0xbb088 }, 1797 [GCC_PCIE_D_BCR] = { 0x4c000 }, 1798 [GCC_PCIE_D_LINK_DOWN_BCR] = { 0xbc000 }, 1799 [GCC_PCIE_D_NOCSR_COM_PHY_BCR] = { 0xbc008 }, 1800 [GCC_PCIE_D_PHY_BCR] = { 0x50000 }, 1801 [GCC_PCIE_D_PHY_CFG_AHB_BCR] = { 0xbc010 }, 1802 [GCC_PCIE_D_PHY_COM_BCR] = { 0xbc014 }, 1803 [GCC_PCIE_D_PHY_NOCSR_COM_PHY_BCR] = { 0xbc00c }, 1804 [GCC_PCIE_NOC_BCR] = { 0x52000 }, 1805 [GCC_PDM_BCR] = { 0x1a000 }, 1806 [GCC_QUPV3_WRAPPER_3_BCR] = { 0x23000 }, 1807 [GCC_TCSR_PCIE_BCR] = { 0xb901c }, 1808 }; 1809 1810 static const struct clk_rcg_dfs_data gcc_nord_dfs_clocks[] = { 1811 DEFINE_RCG_DFS(gcc_qupv3_wrap3_qspi_ref_clk_src), 1812 }; 1813 1814 static const struct regmap_config gcc_nord_regmap_config = { 1815 .reg_bits = 32, 1816 .reg_stride = 4, 1817 .val_bits = 32, 1818 .max_register = 0x1f41f0, 1819 .fast_io = true, 1820 }; 1821 1822 static const u32 gcc_nord_critical_cbcrs[] = { 1823 0x52464, /* GCC_PCIE_LINK_AHB_CLK */ 1824 0x52468, /* GCC_PCIE_LINK_XO_CLK */ 1825 }; 1826 1827 static const struct qcom_cc_driver_data gcc_nord_driver_data = { 1828 .dfs_rcgs = gcc_nord_dfs_clocks, 1829 .num_dfs_rcgs = ARRAY_SIZE(gcc_nord_dfs_clocks), 1830 .clk_cbcrs = gcc_nord_critical_cbcrs, 1831 .num_clk_cbcrs = ARRAY_SIZE(gcc_nord_critical_cbcrs), 1832 }; 1833 1834 static const struct qcom_cc_desc gcc_nord_desc = { 1835 .config = &gcc_nord_regmap_config, 1836 .clks = gcc_nord_clocks, 1837 .num_clks = ARRAY_SIZE(gcc_nord_clocks), 1838 .resets = gcc_nord_resets, 1839 .num_resets = ARRAY_SIZE(gcc_nord_resets), 1840 .gdscs = gcc_nord_gdscs, 1841 .num_gdscs = ARRAY_SIZE(gcc_nord_gdscs), 1842 .use_rpm = true, 1843 .driver_data = &gcc_nord_driver_data, 1844 }; 1845 1846 static const struct of_device_id gcc_nord_match_table[] = { 1847 { .compatible = "qcom,nord-gcc" }, 1848 { } 1849 }; 1850 MODULE_DEVICE_TABLE(of, gcc_nord_match_table); 1851 1852 static int gcc_nord_probe(struct platform_device *pdev) 1853 { 1854 return qcom_cc_probe(pdev, &gcc_nord_desc); 1855 } 1856 1857 static struct platform_driver gcc_nord_driver = { 1858 .probe = gcc_nord_probe, 1859 .driver = { 1860 .name = "gcc-nord", 1861 .of_match_table = gcc_nord_match_table, 1862 }, 1863 }; 1864 1865 static int __init gcc_nord_init(void) 1866 { 1867 return platform_driver_register(&gcc_nord_driver); 1868 } 1869 subsys_initcall(gcc_nord_init); 1870 1871 static void __exit gcc_nord_exit(void) 1872 { 1873 platform_driver_unregister(&gcc_nord_driver); 1874 } 1875 module_exit(gcc_nord_exit); 1876 1877 MODULE_DESCRIPTION("QTI GCC NORD Driver"); 1878 MODULE_LICENSE("GPL"); 1879