1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 4 */ 5 6 #include <linux/clk-provider.h> 7 #include <linux/mod_devicetable.h> 8 #include <linux/module.h> 9 #include <linux/platform_device.h> 10 #include <linux/regmap.h> 11 12 #include <dt-bindings/clock/qcom,kaanapali-gcc.h> 13 14 #include "clk-alpha-pll.h" 15 #include "clk-branch.h" 16 #include "clk-pll.h" 17 #include "clk-rcg.h" 18 #include "clk-regmap.h" 19 #include "clk-regmap-divider.h" 20 #include "clk-regmap-mux.h" 21 #include "clk-regmap-phy-mux.h" 22 #include "common.h" 23 #include "gdsc.h" 24 #include "reset.h" 25 26 enum { 27 DT_BI_TCXO, 28 DT_BI_TCXO_AO, 29 DT_SLEEP_CLK, 30 DT_PCIE_0_PIPE_CLK, 31 DT_UFS_PHY_RX_SYMBOL_0_CLK, 32 DT_UFS_PHY_RX_SYMBOL_1_CLK, 33 DT_UFS_PHY_TX_SYMBOL_0_CLK, 34 DT_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 35 }; 36 37 enum { 38 P_BI_TCXO, 39 P_GCC_GPLL0_OUT_EVEN, 40 P_GCC_GPLL0_OUT_MAIN, 41 P_GCC_GPLL1_OUT_MAIN, 42 P_GCC_GPLL4_OUT_MAIN, 43 P_GCC_GPLL7_OUT_MAIN, 44 P_GCC_GPLL9_OUT_MAIN, 45 P_PCIE_0_PIPE_CLK, 46 P_SLEEP_CLK, 47 P_UFS_PHY_RX_SYMBOL_0_CLK, 48 P_UFS_PHY_RX_SYMBOL_1_CLK, 49 P_UFS_PHY_TX_SYMBOL_0_CLK, 50 P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 51 }; 52 53 static struct clk_alpha_pll gcc_gpll0 = { 54 .offset = 0x0, 55 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], 56 .clkr = { 57 .enable_reg = 0x52020, 58 .enable_mask = BIT(0), 59 .hw.init = &(const struct clk_init_data) { 60 .name = "gcc_gpll0", 61 .parent_data = &(const struct clk_parent_data) { 62 .index = DT_BI_TCXO, 63 }, 64 .num_parents = 1, 65 .ops = &clk_alpha_pll_fixed_taycan_eko_t_ops, 66 }, 67 }, 68 }; 69 70 static const struct clk_div_table post_div_table_gcc_gpll0_out_even[] = { 71 { 0x1, 2 }, 72 { } 73 }; 74 75 static struct clk_alpha_pll_postdiv gcc_gpll0_out_even = { 76 .offset = 0x0, 77 .post_div_shift = 10, 78 .post_div_table = post_div_table_gcc_gpll0_out_even, 79 .num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_even), 80 .width = 4, 81 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], 82 .clkr.hw.init = &(const struct clk_init_data) { 83 .name = "gcc_gpll0_out_even", 84 .parent_hws = (const struct clk_hw*[]) { 85 &gcc_gpll0.clkr.hw, 86 }, 87 .num_parents = 1, 88 .ops = &clk_alpha_pll_postdiv_taycan_eko_t_ops, 89 }, 90 }; 91 92 static struct clk_alpha_pll gcc_gpll1 = { 93 .offset = 0x1000, 94 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], 95 .clkr = { 96 .enable_reg = 0x52020, 97 .enable_mask = BIT(1), 98 .hw.init = &(const struct clk_init_data) { 99 .name = "gcc_gpll1", 100 .parent_data = &(const struct clk_parent_data) { 101 .index = DT_BI_TCXO, 102 }, 103 .num_parents = 1, 104 .ops = &clk_alpha_pll_fixed_taycan_eko_t_ops, 105 }, 106 }, 107 }; 108 109 static struct clk_alpha_pll gcc_gpll4 = { 110 .offset = 0x4000, 111 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], 112 .clkr = { 113 .enable_reg = 0x52020, 114 .enable_mask = BIT(4), 115 .hw.init = &(const struct clk_init_data) { 116 .name = "gcc_gpll4", 117 .parent_data = &(const struct clk_parent_data) { 118 .index = DT_BI_TCXO, 119 }, 120 .num_parents = 1, 121 .ops = &clk_alpha_pll_fixed_taycan_eko_t_ops, 122 }, 123 }, 124 }; 125 126 static struct clk_alpha_pll gcc_gpll7 = { 127 .offset = 0x7000, 128 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], 129 .clkr = { 130 .enable_reg = 0x52020, 131 .enable_mask = BIT(7), 132 .hw.init = &(const struct clk_init_data) { 133 .name = "gcc_gpll7", 134 .parent_data = &(const struct clk_parent_data) { 135 .index = DT_BI_TCXO, 136 }, 137 .num_parents = 1, 138 .ops = &clk_alpha_pll_fixed_taycan_eko_t_ops, 139 }, 140 }, 141 }; 142 143 static struct clk_alpha_pll gcc_gpll9 = { 144 .offset = 0x9000, 145 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], 146 .clkr = { 147 .enable_reg = 0x52020, 148 .enable_mask = BIT(9), 149 .hw.init = &(const struct clk_init_data) { 150 .name = "gcc_gpll9", 151 .parent_data = &(const struct clk_parent_data) { 152 .index = DT_BI_TCXO, 153 }, 154 .num_parents = 1, 155 .ops = &clk_alpha_pll_fixed_taycan_eko_t_ops, 156 }, 157 }, 158 }; 159 160 static const struct parent_map gcc_parent_map_0[] = { 161 { P_BI_TCXO, 0 }, 162 { P_GCC_GPLL0_OUT_MAIN, 1 }, 163 { P_GCC_GPLL0_OUT_EVEN, 6 }, 164 }; 165 166 static const struct clk_parent_data gcc_parent_data_0[] = { 167 { .index = DT_BI_TCXO }, 168 { .hw = &gcc_gpll0.clkr.hw }, 169 { .hw = &gcc_gpll0_out_even.clkr.hw }, 170 }; 171 172 static const struct parent_map gcc_parent_map_1[] = { 173 { P_BI_TCXO, 0 }, 174 { P_GCC_GPLL0_OUT_MAIN, 1 }, 175 { P_GCC_GPLL1_OUT_MAIN, 4 }, 176 { P_GCC_GPLL4_OUT_MAIN, 5 }, 177 { P_GCC_GPLL0_OUT_EVEN, 6 }, 178 }; 179 180 static const struct clk_parent_data gcc_parent_data_1[] = { 181 { .index = DT_BI_TCXO }, 182 { .hw = &gcc_gpll0.clkr.hw }, 183 { .hw = &gcc_gpll1.clkr.hw }, 184 { .hw = &gcc_gpll4.clkr.hw }, 185 { .hw = &gcc_gpll0_out_even.clkr.hw }, 186 }; 187 188 static const struct parent_map gcc_parent_map_2[] = { 189 { P_BI_TCXO, 0 }, 190 { P_GCC_GPLL0_OUT_MAIN, 1 }, 191 { P_SLEEP_CLK, 5 }, 192 { P_GCC_GPLL0_OUT_EVEN, 6 }, 193 }; 194 195 static const struct clk_parent_data gcc_parent_data_2[] = { 196 { .index = DT_BI_TCXO }, 197 { .hw = &gcc_gpll0.clkr.hw }, 198 { .index = DT_SLEEP_CLK }, 199 { .hw = &gcc_gpll0_out_even.clkr.hw }, 200 }; 201 202 static const struct parent_map gcc_parent_map_3[] = { 203 { P_BI_TCXO, 0 }, 204 { P_GCC_GPLL0_OUT_MAIN, 1 }, 205 { P_GCC_GPLL4_OUT_MAIN, 5 }, 206 { P_GCC_GPLL0_OUT_EVEN, 6 }, 207 }; 208 209 static const struct clk_parent_data gcc_parent_data_3[] = { 210 { .index = DT_BI_TCXO }, 211 { .hw = &gcc_gpll0.clkr.hw }, 212 { .hw = &gcc_gpll4.clkr.hw }, 213 { .hw = &gcc_gpll0_out_even.clkr.hw }, 214 }; 215 216 static const struct parent_map gcc_parent_map_4[] = { 217 { P_BI_TCXO, 0 }, 218 }; 219 220 static const struct clk_parent_data gcc_parent_data_4[] = { 221 { .index = DT_BI_TCXO }, 222 }; 223 224 static const struct parent_map gcc_parent_map_5[] = { 225 { P_BI_TCXO, 0 }, 226 { P_GCC_GPLL0_OUT_MAIN, 1 }, 227 { P_GCC_GPLL7_OUT_MAIN, 2 }, 228 { P_GCC_GPLL0_OUT_EVEN, 6 }, 229 }; 230 231 static const struct clk_parent_data gcc_parent_data_5[] = { 232 { .index = DT_BI_TCXO }, 233 { .hw = &gcc_gpll0.clkr.hw }, 234 { .hw = &gcc_gpll7.clkr.hw }, 235 { .hw = &gcc_gpll0_out_even.clkr.hw }, 236 }; 237 238 static const struct parent_map gcc_parent_map_6[] = { 239 { P_BI_TCXO, 0 }, 240 { P_SLEEP_CLK, 5 }, 241 }; 242 243 static const struct clk_parent_data gcc_parent_data_6[] = { 244 { .index = DT_BI_TCXO }, 245 { .index = DT_SLEEP_CLK }, 246 }; 247 248 static const struct parent_map gcc_parent_map_8[] = { 249 { P_BI_TCXO, 0 }, 250 { P_GCC_GPLL0_OUT_MAIN, 1 }, 251 { P_GCC_GPLL9_OUT_MAIN, 2 }, 252 { P_GCC_GPLL4_OUT_MAIN, 5 }, 253 { P_GCC_GPLL0_OUT_EVEN, 6 }, 254 }; 255 256 static const struct clk_parent_data gcc_parent_data_8[] = { 257 { .index = DT_BI_TCXO }, 258 { .hw = &gcc_gpll0.clkr.hw }, 259 { .hw = &gcc_gpll9.clkr.hw }, 260 { .hw = &gcc_gpll4.clkr.hw }, 261 { .hw = &gcc_gpll0_out_even.clkr.hw }, 262 }; 263 264 static const struct parent_map gcc_parent_map_12[] = { 265 { P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 0 }, 266 { P_BI_TCXO, 2 }, 267 }; 268 269 static const struct clk_parent_data gcc_parent_data_12[] = { 270 { .index = DT_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK }, 271 { .index = DT_BI_TCXO }, 272 }; 273 274 static struct clk_regmap_phy_mux gcc_pcie_0_pipe_clk_src = { 275 .reg = 0x6b090, 276 .clkr = { 277 .hw.init = &(const struct clk_init_data) { 278 .name = "gcc_pcie_0_pipe_clk_src", 279 .parent_data = &(const struct clk_parent_data){ 280 .index = DT_PCIE_0_PIPE_CLK, 281 }, 282 .num_parents = 1, 283 .ops = &clk_regmap_phy_mux_ops, 284 }, 285 }, 286 }; 287 288 static struct clk_regmap_phy_mux gcc_ufs_phy_rx_symbol_0_clk_src = { 289 .reg = 0x77068, 290 .clkr = { 291 .hw.init = &(const struct clk_init_data) { 292 .name = "gcc_ufs_phy_rx_symbol_0_clk_src", 293 .parent_data = &(const struct clk_parent_data){ 294 .index = DT_UFS_PHY_RX_SYMBOL_0_CLK, 295 }, 296 .num_parents = 1, 297 .ops = &clk_regmap_phy_mux_ops, 298 }, 299 }, 300 }; 301 302 static struct clk_regmap_phy_mux gcc_ufs_phy_rx_symbol_1_clk_src = { 303 .reg = 0x770ec, 304 .clkr = { 305 .hw.init = &(const struct clk_init_data) { 306 .name = "gcc_ufs_phy_rx_symbol_1_clk_src", 307 .parent_data = &(const struct clk_parent_data){ 308 .index = DT_UFS_PHY_RX_SYMBOL_1_CLK, 309 }, 310 .num_parents = 1, 311 .ops = &clk_regmap_phy_mux_ops, 312 }, 313 }, 314 }; 315 316 static struct clk_regmap_phy_mux gcc_ufs_phy_tx_symbol_0_clk_src = { 317 .reg = 0x77058, 318 .clkr = { 319 .hw.init = &(const struct clk_init_data) { 320 .name = "gcc_ufs_phy_tx_symbol_0_clk_src", 321 .parent_data = &(const struct clk_parent_data){ 322 .index = DT_UFS_PHY_TX_SYMBOL_0_CLK, 323 }, 324 .num_parents = 1, 325 .ops = &clk_regmap_phy_mux_ops, 326 }, 327 }, 328 }; 329 330 static struct clk_regmap_mux gcc_usb3_prim_phy_pipe_clk_src = { 331 .reg = 0x39074, 332 .shift = 0, 333 .width = 2, 334 .parent_map = gcc_parent_map_12, 335 .clkr = { 336 .hw.init = &(const struct clk_init_data) { 337 .name = "gcc_usb3_prim_phy_pipe_clk_src", 338 .parent_data = gcc_parent_data_12, 339 .num_parents = ARRAY_SIZE(gcc_parent_data_12), 340 .ops = &clk_regmap_mux_closest_ops, 341 }, 342 }, 343 }; 344 345 static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = { 346 F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0), 347 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 348 F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0), 349 { } 350 }; 351 352 static struct clk_rcg2 gcc_gp1_clk_src = { 353 .cmd_rcgr = 0x64004, 354 .mnd_width = 16, 355 .hid_width = 5, 356 .parent_map = gcc_parent_map_2, 357 .freq_tbl = ftbl_gcc_gp1_clk_src, 358 .clkr.hw.init = &(const struct clk_init_data) { 359 .name = "gcc_gp1_clk_src", 360 .parent_data = gcc_parent_data_2, 361 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 362 .flags = CLK_SET_RATE_PARENT, 363 .ops = &clk_rcg2_ops, 364 }, 365 }; 366 367 static struct clk_rcg2 gcc_gp2_clk_src = { 368 .cmd_rcgr = 0x65004, 369 .mnd_width = 16, 370 .hid_width = 5, 371 .parent_map = gcc_parent_map_2, 372 .freq_tbl = ftbl_gcc_gp1_clk_src, 373 .clkr.hw.init = &(const struct clk_init_data) { 374 .name = "gcc_gp2_clk_src", 375 .parent_data = gcc_parent_data_2, 376 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 377 .flags = CLK_SET_RATE_PARENT, 378 .ops = &clk_rcg2_ops, 379 }, 380 }; 381 382 static struct clk_rcg2 gcc_gp3_clk_src = { 383 .cmd_rcgr = 0x66004, 384 .mnd_width = 16, 385 .hid_width = 5, 386 .parent_map = gcc_parent_map_2, 387 .freq_tbl = ftbl_gcc_gp1_clk_src, 388 .clkr.hw.init = &(const struct clk_init_data) { 389 .name = "gcc_gp3_clk_src", 390 .parent_data = gcc_parent_data_2, 391 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 392 .flags = CLK_SET_RATE_PARENT, 393 .ops = &clk_rcg2_ops, 394 }, 395 }; 396 397 static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = { 398 F(19200000, P_BI_TCXO, 1, 0, 0), 399 { } 400 }; 401 402 static struct clk_rcg2 gcc_pcie_0_aux_clk_src = { 403 .cmd_rcgr = 0x6b094, 404 .mnd_width = 16, 405 .hid_width = 5, 406 .parent_map = gcc_parent_map_6, 407 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 408 .clkr.hw.init = &(const struct clk_init_data) { 409 .name = "gcc_pcie_0_aux_clk_src", 410 .parent_data = gcc_parent_data_6, 411 .num_parents = ARRAY_SIZE(gcc_parent_data_6), 412 .flags = CLK_SET_RATE_PARENT, 413 .ops = &clk_rcg2_shared_no_init_park_ops, 414 }, 415 }; 416 417 static struct clk_rcg2 gcc_pcie_0_phy_aux_clk_src = { 418 .cmd_rcgr = 0x6b0ac, 419 .mnd_width = 0, 420 .hid_width = 5, 421 .parent_map = gcc_parent_map_0, 422 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 423 .clkr.hw.init = &(const struct clk_init_data) { 424 .name = "gcc_pcie_0_phy_aux_clk_src", 425 .parent_data = gcc_parent_data_0, 426 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 427 .flags = CLK_SET_RATE_PARENT, 428 .ops = &clk_rcg2_shared_no_init_park_ops, 429 }, 430 }; 431 432 static const struct freq_tbl ftbl_gcc_pcie_0_phy_rchng_clk_src[] = { 433 F(19200000, P_BI_TCXO, 1, 0, 0), 434 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0), 435 { } 436 }; 437 438 static struct clk_rcg2 gcc_pcie_0_phy_rchng_clk_src = { 439 .cmd_rcgr = 0x6b078, 440 .mnd_width = 0, 441 .hid_width = 5, 442 .parent_map = gcc_parent_map_0, 443 .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src, 444 .clkr.hw.init = &(const struct clk_init_data) { 445 .name = "gcc_pcie_0_phy_rchng_clk_src", 446 .parent_data = gcc_parent_data_0, 447 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 448 .flags = CLK_SET_RATE_PARENT, 449 .ops = &clk_rcg2_shared_no_init_park_ops, 450 }, 451 }; 452 453 static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = { 454 F(60000000, P_GCC_GPLL0_OUT_MAIN, 10, 0, 0), 455 { } 456 }; 457 458 static struct clk_rcg2 gcc_pdm2_clk_src = { 459 .cmd_rcgr = 0x33010, 460 .mnd_width = 0, 461 .hid_width = 5, 462 .parent_map = gcc_parent_map_0, 463 .freq_tbl = ftbl_gcc_pdm2_clk_src, 464 .clkr.hw.init = &(const struct clk_init_data) { 465 .name = "gcc_pdm2_clk_src", 466 .parent_data = gcc_parent_data_0, 467 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 468 .flags = CLK_SET_RATE_PARENT, 469 .ops = &clk_rcg2_shared_no_init_park_ops, 470 }, 471 }; 472 473 static struct clk_rcg2 gcc_qupv3_i2c_s0_clk_src = { 474 .cmd_rcgr = 0x17008, 475 .mnd_width = 0, 476 .hid_width = 5, 477 .parent_map = gcc_parent_map_0, 478 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 479 .clkr.hw.init = &(const struct clk_init_data) { 480 .name = "gcc_qupv3_i2c_s0_clk_src", 481 .parent_data = gcc_parent_data_0, 482 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 483 .flags = CLK_SET_RATE_PARENT, 484 .ops = &clk_rcg2_shared_no_init_park_ops, 485 }, 486 }; 487 488 static struct clk_rcg2 gcc_qupv3_i2c_s1_clk_src = { 489 .cmd_rcgr = 0x17024, 490 .mnd_width = 0, 491 .hid_width = 5, 492 .parent_map = gcc_parent_map_0, 493 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 494 .clkr.hw.init = &(const struct clk_init_data) { 495 .name = "gcc_qupv3_i2c_s1_clk_src", 496 .parent_data = gcc_parent_data_0, 497 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 498 .flags = CLK_SET_RATE_PARENT, 499 .ops = &clk_rcg2_shared_no_init_park_ops, 500 }, 501 }; 502 503 static struct clk_rcg2 gcc_qupv3_i2c_s2_clk_src = { 504 .cmd_rcgr = 0x17040, 505 .mnd_width = 0, 506 .hid_width = 5, 507 .parent_map = gcc_parent_map_0, 508 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 509 .clkr.hw.init = &(const struct clk_init_data) { 510 .name = "gcc_qupv3_i2c_s2_clk_src", 511 .parent_data = gcc_parent_data_0, 512 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 513 .flags = CLK_SET_RATE_PARENT, 514 .ops = &clk_rcg2_shared_no_init_park_ops, 515 }, 516 }; 517 518 static struct clk_rcg2 gcc_qupv3_i2c_s3_clk_src = { 519 .cmd_rcgr = 0x1705c, 520 .mnd_width = 0, 521 .hid_width = 5, 522 .parent_map = gcc_parent_map_0, 523 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 524 .clkr.hw.init = &(const struct clk_init_data) { 525 .name = "gcc_qupv3_i2c_s3_clk_src", 526 .parent_data = gcc_parent_data_0, 527 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 528 .flags = CLK_SET_RATE_PARENT, 529 .ops = &clk_rcg2_shared_no_init_park_ops, 530 }, 531 }; 532 533 static struct clk_rcg2 gcc_qupv3_i2c_s4_clk_src = { 534 .cmd_rcgr = 0x17078, 535 .mnd_width = 0, 536 .hid_width = 5, 537 .parent_map = gcc_parent_map_0, 538 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 539 .clkr.hw.init = &(const struct clk_init_data) { 540 .name = "gcc_qupv3_i2c_s4_clk_src", 541 .parent_data = gcc_parent_data_0, 542 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 543 .flags = CLK_SET_RATE_PARENT, 544 .ops = &clk_rcg2_shared_no_init_park_ops, 545 }, 546 }; 547 548 static const struct freq_tbl ftbl_gcc_qupv3_wrap1_qspi_ref_clk_src[] = { 549 F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625), 550 F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625), 551 F(19200000, P_BI_TCXO, 1, 0, 0), 552 F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625), 553 F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75), 554 F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25), 555 F(51200000, P_GCC_GPLL0_OUT_EVEN, 1, 64, 375), 556 F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75), 557 F(66666667, P_GCC_GPLL0_OUT_MAIN, 9, 0, 0), 558 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), 559 F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15), 560 F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25), 561 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 562 F(102400000, P_GCC_GPLL0_OUT_EVEN, 1, 128, 375), 563 F(112000000, P_GCC_GPLL0_OUT_EVEN, 1, 28, 75), 564 F(117964800, P_GCC_GPLL0_OUT_EVEN, 1, 6144, 15625), 565 F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0), 566 F(150000000, P_GCC_GPLL0_OUT_EVEN, 2, 0, 0), 567 F(250000000, P_GCC_GPLL7_OUT_MAIN, 2, 0, 0), 568 { } 569 }; 570 571 static struct clk_init_data gcc_qupv3_wrap1_qspi_ref_clk_src_init = { 572 .name = "gcc_qupv3_wrap1_qspi_ref_clk_src", 573 .parent_data = gcc_parent_data_5, 574 .num_parents = ARRAY_SIZE(gcc_parent_data_5), 575 .flags = CLK_SET_RATE_PARENT, 576 .ops = &clk_rcg2_shared_no_init_park_ops, 577 }; 578 579 static struct clk_rcg2 gcc_qupv3_wrap1_qspi_ref_clk_src = { 580 .cmd_rcgr = 0x188c0, 581 .mnd_width = 16, 582 .hid_width = 5, 583 .parent_map = gcc_parent_map_5, 584 .freq_tbl = ftbl_gcc_qupv3_wrap1_qspi_ref_clk_src, 585 .clkr.hw.init = &gcc_qupv3_wrap1_qspi_ref_clk_src_init, 586 }; 587 588 static const struct freq_tbl ftbl_gcc_qupv3_wrap1_s0_clk_src[] = { 589 F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625), 590 F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625), 591 F(19200000, P_BI_TCXO, 1, 0, 0), 592 F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625), 593 F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75), 594 F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25), 595 F(51200000, P_GCC_GPLL0_OUT_EVEN, 1, 64, 375), 596 F(60000000, P_GCC_GPLL0_OUT_EVEN, 5, 0, 0), 597 F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75), 598 F(66666667, P_GCC_GPLL0_OUT_MAIN, 9, 0, 0), 599 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), 600 F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15), 601 F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25), 602 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 603 { } 604 }; 605 606 static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = { 607 .name = "gcc_qupv3_wrap1_s0_clk_src", 608 .parent_data = gcc_parent_data_0, 609 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 610 .flags = CLK_SET_RATE_PARENT, 611 .ops = &clk_rcg2_shared_no_init_park_ops, 612 }; 613 614 static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = { 615 .cmd_rcgr = 0x18014, 616 .mnd_width = 16, 617 .hid_width = 5, 618 .parent_map = gcc_parent_map_0, 619 .freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src, 620 .clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init, 621 }; 622 623 static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = { 624 .name = "gcc_qupv3_wrap1_s1_clk_src", 625 .parent_data = gcc_parent_data_0, 626 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 627 .flags = CLK_SET_RATE_PARENT, 628 .ops = &clk_rcg2_shared_no_init_park_ops, 629 }; 630 631 static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = { 632 .cmd_rcgr = 0x18150, 633 .mnd_width = 16, 634 .hid_width = 5, 635 .parent_map = gcc_parent_map_0, 636 .freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src, 637 .clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init, 638 }; 639 640 static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = { 641 .name = "gcc_qupv3_wrap1_s3_clk_src", 642 .parent_data = gcc_parent_data_0, 643 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 644 .flags = CLK_SET_RATE_PARENT, 645 .ops = &clk_rcg2_shared_no_init_park_ops, 646 }; 647 648 static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = { 649 .cmd_rcgr = 0x182a0, 650 .mnd_width = 16, 651 .hid_width = 5, 652 .parent_map = gcc_parent_map_0, 653 .freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src, 654 .clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init, 655 }; 656 657 static const struct freq_tbl ftbl_gcc_qupv3_wrap1_s4_clk_src[] = { 658 F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625), 659 F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625), 660 F(19200000, P_BI_TCXO, 1, 0, 0), 661 F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625), 662 F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75), 663 F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25), 664 F(51200000, P_GCC_GPLL0_OUT_EVEN, 1, 64, 375), 665 F(60000000, P_GCC_GPLL0_OUT_EVEN, 5, 0, 0), 666 F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75), 667 F(66666667, P_GCC_GPLL0_OUT_MAIN, 9, 0, 0), 668 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), 669 F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15), 670 F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25), 671 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 672 F(102400000, P_GCC_GPLL0_OUT_EVEN, 1, 128, 375), 673 F(112000000, P_GCC_GPLL0_OUT_EVEN, 1, 28, 75), 674 F(117964800, P_GCC_GPLL0_OUT_EVEN, 1, 6144, 15625), 675 F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0), 676 { } 677 }; 678 679 static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = { 680 .name = "gcc_qupv3_wrap1_s4_clk_src", 681 .parent_data = gcc_parent_data_0, 682 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 683 .flags = CLK_SET_RATE_PARENT, 684 .ops = &clk_rcg2_shared_no_init_park_ops, 685 }; 686 687 static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = { 688 .cmd_rcgr = 0x183dc, 689 .mnd_width = 16, 690 .hid_width = 5, 691 .parent_map = gcc_parent_map_0, 692 .freq_tbl = ftbl_gcc_qupv3_wrap1_s4_clk_src, 693 .clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init, 694 }; 695 696 static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = { 697 .name = "gcc_qupv3_wrap1_s5_clk_src", 698 .parent_data = gcc_parent_data_0, 699 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 700 .flags = CLK_SET_RATE_PARENT, 701 .ops = &clk_rcg2_shared_no_init_park_ops, 702 }; 703 704 static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = { 705 .cmd_rcgr = 0x18518, 706 .mnd_width = 16, 707 .hid_width = 5, 708 .parent_map = gcc_parent_map_0, 709 .freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src, 710 .clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init, 711 }; 712 713 static struct clk_init_data gcc_qupv3_wrap1_s6_clk_src_init = { 714 .name = "gcc_qupv3_wrap1_s6_clk_src", 715 .parent_data = gcc_parent_data_0, 716 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 717 .flags = CLK_SET_RATE_PARENT, 718 .ops = &clk_rcg2_shared_no_init_park_ops, 719 }; 720 721 static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = { 722 .cmd_rcgr = 0x18654, 723 .mnd_width = 16, 724 .hid_width = 5, 725 .parent_map = gcc_parent_map_0, 726 .freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src, 727 .clkr.hw.init = &gcc_qupv3_wrap1_s6_clk_src_init, 728 }; 729 730 static struct clk_init_data gcc_qupv3_wrap1_s7_clk_src_init = { 731 .name = "gcc_qupv3_wrap1_s7_clk_src", 732 .parent_data = gcc_parent_data_0, 733 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 734 .flags = CLK_SET_RATE_PARENT, 735 .ops = &clk_rcg2_shared_no_init_park_ops, 736 }; 737 738 static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src = { 739 .cmd_rcgr = 0x18790, 740 .mnd_width = 16, 741 .hid_width = 5, 742 .parent_map = gcc_parent_map_0, 743 .freq_tbl = ftbl_gcc_qupv3_wrap1_s4_clk_src, 744 .clkr.hw.init = &gcc_qupv3_wrap1_s7_clk_src_init, 745 }; 746 747 static struct clk_init_data gcc_qupv3_wrap2_s0_clk_src_init = { 748 .name = "gcc_qupv3_wrap2_s0_clk_src", 749 .parent_data = gcc_parent_data_0, 750 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 751 .flags = CLK_SET_RATE_PARENT, 752 .ops = &clk_rcg2_shared_no_init_park_ops, 753 }; 754 755 static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = { 756 .cmd_rcgr = 0x1e014, 757 .mnd_width = 16, 758 .hid_width = 5, 759 .parent_map = gcc_parent_map_0, 760 .freq_tbl = ftbl_gcc_qupv3_wrap1_s4_clk_src, 761 .clkr.hw.init = &gcc_qupv3_wrap2_s0_clk_src_init, 762 }; 763 764 static struct clk_init_data gcc_qupv3_wrap2_s1_clk_src_init = { 765 .name = "gcc_qupv3_wrap2_s1_clk_src", 766 .parent_data = gcc_parent_data_0, 767 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 768 .flags = CLK_SET_RATE_PARENT, 769 .ops = &clk_rcg2_shared_no_init_park_ops, 770 }; 771 772 static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = { 773 .cmd_rcgr = 0x1e150, 774 .mnd_width = 16, 775 .hid_width = 5, 776 .parent_map = gcc_parent_map_0, 777 .freq_tbl = ftbl_gcc_qupv3_wrap1_s4_clk_src, 778 .clkr.hw.init = &gcc_qupv3_wrap2_s1_clk_src_init, 779 }; 780 781 static struct clk_init_data gcc_qupv3_wrap2_s2_clk_src_init = { 782 .name = "gcc_qupv3_wrap2_s2_clk_src", 783 .parent_data = gcc_parent_data_0, 784 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 785 .flags = CLK_SET_RATE_PARENT, 786 .ops = &clk_rcg2_shared_no_init_park_ops, 787 }; 788 789 static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = { 790 .cmd_rcgr = 0x1e28c, 791 .mnd_width = 16, 792 .hid_width = 5, 793 .parent_map = gcc_parent_map_0, 794 .freq_tbl = ftbl_gcc_qupv3_wrap1_s4_clk_src, 795 .clkr.hw.init = &gcc_qupv3_wrap2_s2_clk_src_init, 796 }; 797 798 static struct clk_init_data gcc_qupv3_wrap2_s3_clk_src_init = { 799 .name = "gcc_qupv3_wrap2_s3_clk_src", 800 .parent_data = gcc_parent_data_0, 801 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 802 .flags = CLK_SET_RATE_PARENT, 803 .ops = &clk_rcg2_shared_no_init_park_ops, 804 }; 805 806 static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = { 807 .cmd_rcgr = 0x1e3c8, 808 .mnd_width = 16, 809 .hid_width = 5, 810 .parent_map = gcc_parent_map_0, 811 .freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src, 812 .clkr.hw.init = &gcc_qupv3_wrap2_s3_clk_src_init, 813 }; 814 815 static struct clk_init_data gcc_qupv3_wrap2_s4_clk_src_init = { 816 .name = "gcc_qupv3_wrap2_s4_clk_src", 817 .parent_data = gcc_parent_data_0, 818 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 819 .flags = CLK_SET_RATE_PARENT, 820 .ops = &clk_rcg2_shared_no_init_park_ops, 821 }; 822 823 static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = { 824 .cmd_rcgr = 0x1e504, 825 .mnd_width = 16, 826 .hid_width = 5, 827 .parent_map = gcc_parent_map_0, 828 .freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src, 829 .clkr.hw.init = &gcc_qupv3_wrap2_s4_clk_src_init, 830 }; 831 832 static const struct freq_tbl ftbl_gcc_qupv3_wrap3_ibi_ctrl_0_clk_src[] = { 833 F(37500000, P_GCC_GPLL0_OUT_EVEN, 8, 0, 0), 834 { } 835 }; 836 837 static struct clk_rcg2 gcc_qupv3_wrap3_ibi_ctrl_0_clk_src = { 838 .cmd_rcgr = 0xa877c, 839 .mnd_width = 0, 840 .hid_width = 5, 841 .parent_map = gcc_parent_map_1, 842 .freq_tbl = ftbl_gcc_qupv3_wrap3_ibi_ctrl_0_clk_src, 843 .clkr.hw.init = &(const struct clk_init_data) { 844 .name = "gcc_qupv3_wrap3_ibi_ctrl_0_clk_src", 845 .parent_data = gcc_parent_data_1, 846 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 847 .flags = CLK_SET_RATE_PARENT, 848 .ops = &clk_rcg2_shared_no_init_park_ops, 849 }, 850 }; 851 852 static struct clk_init_data gcc_qupv3_wrap3_s0_clk_src_init = { 853 .name = "gcc_qupv3_wrap3_s0_clk_src", 854 .parent_data = gcc_parent_data_0, 855 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 856 .flags = CLK_SET_RATE_PARENT, 857 .ops = &clk_rcg2_shared_no_init_park_ops, 858 }; 859 860 static struct clk_rcg2 gcc_qupv3_wrap3_s0_clk_src = { 861 .cmd_rcgr = 0xa8014, 862 .mnd_width = 16, 863 .hid_width = 5, 864 .parent_map = gcc_parent_map_0, 865 .freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src, 866 .clkr.hw.init = &gcc_qupv3_wrap3_s0_clk_src_init, 867 }; 868 869 static struct clk_init_data gcc_qupv3_wrap3_s1_clk_src_init = { 870 .name = "gcc_qupv3_wrap3_s1_clk_src", 871 .parent_data = gcc_parent_data_0, 872 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 873 .flags = CLK_SET_RATE_PARENT, 874 .ops = &clk_rcg2_shared_no_init_park_ops, 875 }; 876 877 static struct clk_rcg2 gcc_qupv3_wrap3_s1_clk_src = { 878 .cmd_rcgr = 0xa8150, 879 .mnd_width = 16, 880 .hid_width = 5, 881 .parent_map = gcc_parent_map_0, 882 .freq_tbl = ftbl_gcc_qupv3_wrap1_s4_clk_src, 883 .clkr.hw.init = &gcc_qupv3_wrap3_s1_clk_src_init, 884 }; 885 886 static struct clk_init_data gcc_qupv3_wrap3_s2_clk_src_init = { 887 .name = "gcc_qupv3_wrap3_s2_clk_src", 888 .parent_data = gcc_parent_data_0, 889 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 890 .flags = CLK_SET_RATE_PARENT, 891 .ops = &clk_rcg2_shared_no_init_park_ops, 892 }; 893 894 static struct clk_rcg2 gcc_qupv3_wrap3_s2_clk_src = { 895 .cmd_rcgr = 0xa828c, 896 .mnd_width = 16, 897 .hid_width = 5, 898 .parent_map = gcc_parent_map_0, 899 .freq_tbl = ftbl_gcc_qupv3_wrap1_s4_clk_src, 900 .clkr.hw.init = &gcc_qupv3_wrap3_s2_clk_src_init, 901 }; 902 903 static struct clk_init_data gcc_qupv3_wrap3_s3_clk_src_init = { 904 .name = "gcc_qupv3_wrap3_s3_clk_src", 905 .parent_data = gcc_parent_data_0, 906 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 907 .flags = CLK_SET_RATE_PARENT, 908 .ops = &clk_rcg2_shared_no_init_park_ops, 909 }; 910 911 static struct clk_rcg2 gcc_qupv3_wrap3_s3_clk_src = { 912 .cmd_rcgr = 0xa83c8, 913 .mnd_width = 16, 914 .hid_width = 5, 915 .parent_map = gcc_parent_map_0, 916 .freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src, 917 .clkr.hw.init = &gcc_qupv3_wrap3_s3_clk_src_init, 918 }; 919 920 static struct clk_init_data gcc_qupv3_wrap3_s4_clk_src_init = { 921 .name = "gcc_qupv3_wrap3_s4_clk_src", 922 .parent_data = gcc_parent_data_0, 923 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 924 .flags = CLK_SET_RATE_PARENT, 925 .ops = &clk_rcg2_shared_no_init_park_ops, 926 }; 927 928 static struct clk_rcg2 gcc_qupv3_wrap3_s4_clk_src = { 929 .cmd_rcgr = 0xa8504, 930 .mnd_width = 16, 931 .hid_width = 5, 932 .parent_map = gcc_parent_map_0, 933 .freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src, 934 .clkr.hw.init = &gcc_qupv3_wrap3_s4_clk_src_init, 935 }; 936 937 static const struct freq_tbl ftbl_gcc_qupv3_wrap3_s5_clk_src[] = { 938 F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625), 939 F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625), 940 F(19200000, P_BI_TCXO, 1, 0, 0), 941 F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625), 942 F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75), 943 F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25), 944 F(51200000, P_GCC_GPLL0_OUT_EVEN, 1, 64, 375), 945 F(60000000, P_GCC_GPLL0_OUT_EVEN, 5, 0, 0), 946 F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75), 947 F(66666667, P_GCC_GPLL0_OUT_MAIN, 9, 0, 0), 948 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), 949 F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15), 950 F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25), 951 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 952 F(102400000, P_GCC_GPLL0_OUT_EVEN, 1, 128, 375), 953 F(112000000, P_GCC_GPLL0_OUT_EVEN, 1, 28, 75), 954 F(117964800, P_GCC_GPLL0_OUT_EVEN, 1, 6144, 15625), 955 F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0), 956 F(128000000, P_GCC_GPLL0_OUT_MAIN, 1, 16, 75), 957 { } 958 }; 959 960 static struct clk_init_data gcc_qupv3_wrap3_s5_clk_src_init = { 961 .name = "gcc_qupv3_wrap3_s5_clk_src", 962 .parent_data = gcc_parent_data_0, 963 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 964 .flags = CLK_SET_RATE_PARENT, 965 .ops = &clk_rcg2_shared_no_init_park_ops, 966 }; 967 968 static struct clk_rcg2 gcc_qupv3_wrap3_s5_clk_src = { 969 .cmd_rcgr = 0xa8640, 970 .mnd_width = 16, 971 .hid_width = 5, 972 .parent_map = gcc_parent_map_0, 973 .freq_tbl = ftbl_gcc_qupv3_wrap3_s5_clk_src, 974 .clkr.hw.init = &gcc_qupv3_wrap3_s5_clk_src_init, 975 }; 976 977 static struct clk_init_data gcc_qupv3_wrap4_s0_clk_src_init = { 978 .name = "gcc_qupv3_wrap4_s0_clk_src", 979 .parent_data = gcc_parent_data_0, 980 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 981 .flags = CLK_SET_RATE_PARENT, 982 .ops = &clk_rcg2_shared_no_init_park_ops, 983 }; 984 985 static struct clk_rcg2 gcc_qupv3_wrap4_s0_clk_src = { 986 .cmd_rcgr = 0xa9014, 987 .mnd_width = 16, 988 .hid_width = 5, 989 .parent_map = gcc_parent_map_0, 990 .freq_tbl = ftbl_gcc_qupv3_wrap1_s4_clk_src, 991 .clkr.hw.init = &gcc_qupv3_wrap4_s0_clk_src_init, 992 }; 993 994 static struct clk_init_data gcc_qupv3_wrap4_s1_clk_src_init = { 995 .name = "gcc_qupv3_wrap4_s1_clk_src", 996 .parent_data = gcc_parent_data_0, 997 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 998 .flags = CLK_SET_RATE_PARENT, 999 .ops = &clk_rcg2_shared_no_init_park_ops, 1000 }; 1001 1002 static struct clk_rcg2 gcc_qupv3_wrap4_s1_clk_src = { 1003 .cmd_rcgr = 0xa9150, 1004 .mnd_width = 16, 1005 .hid_width = 5, 1006 .parent_map = gcc_parent_map_0, 1007 .freq_tbl = ftbl_gcc_qupv3_wrap1_s4_clk_src, 1008 .clkr.hw.init = &gcc_qupv3_wrap4_s1_clk_src_init, 1009 }; 1010 1011 static struct clk_init_data gcc_qupv3_wrap4_s2_clk_src_init = { 1012 .name = "gcc_qupv3_wrap4_s2_clk_src", 1013 .parent_data = gcc_parent_data_0, 1014 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1015 .flags = CLK_SET_RATE_PARENT, 1016 .ops = &clk_rcg2_shared_no_init_park_ops, 1017 }; 1018 1019 static struct clk_rcg2 gcc_qupv3_wrap4_s2_clk_src = { 1020 .cmd_rcgr = 0xa928c, 1021 .mnd_width = 16, 1022 .hid_width = 5, 1023 .parent_map = gcc_parent_map_0, 1024 .freq_tbl = ftbl_gcc_qupv3_wrap1_s4_clk_src, 1025 .clkr.hw.init = &gcc_qupv3_wrap4_s2_clk_src_init, 1026 }; 1027 1028 static struct clk_init_data gcc_qupv3_wrap4_s3_clk_src_init = { 1029 .name = "gcc_qupv3_wrap4_s3_clk_src", 1030 .parent_data = gcc_parent_data_0, 1031 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1032 .flags = CLK_SET_RATE_PARENT, 1033 .ops = &clk_rcg2_shared_no_init_park_ops, 1034 }; 1035 1036 static struct clk_rcg2 gcc_qupv3_wrap4_s3_clk_src = { 1037 .cmd_rcgr = 0xa93c8, 1038 .mnd_width = 16, 1039 .hid_width = 5, 1040 .parent_map = gcc_parent_map_0, 1041 .freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src, 1042 .clkr.hw.init = &gcc_qupv3_wrap4_s3_clk_src_init, 1043 }; 1044 1045 static struct clk_init_data gcc_qupv3_wrap4_s4_clk_src_init = { 1046 .name = "gcc_qupv3_wrap4_s4_clk_src", 1047 .parent_data = gcc_parent_data_0, 1048 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1049 .flags = CLK_SET_RATE_PARENT, 1050 .ops = &clk_rcg2_shared_no_init_park_ops, 1051 }; 1052 1053 static struct clk_rcg2 gcc_qupv3_wrap4_s4_clk_src = { 1054 .cmd_rcgr = 0xa9504, 1055 .mnd_width = 16, 1056 .hid_width = 5, 1057 .parent_map = gcc_parent_map_0, 1058 .freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src, 1059 .clkr.hw.init = &gcc_qupv3_wrap4_s4_clk_src_init, 1060 }; 1061 1062 static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = { 1063 F(400000, P_BI_TCXO, 12, 1, 4), 1064 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0), 1065 F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0), 1066 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), 1067 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0), 1068 F(202000000, P_GCC_GPLL9_OUT_MAIN, 4, 0, 0), 1069 { } 1070 }; 1071 1072 static struct clk_rcg2 gcc_sdcc2_apps_clk_src = { 1073 .cmd_rcgr = 0x1401c, 1074 .mnd_width = 8, 1075 .hid_width = 5, 1076 .parent_map = gcc_parent_map_8, 1077 .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src, 1078 .clkr.hw.init = &(const struct clk_init_data) { 1079 .name = "gcc_sdcc2_apps_clk_src", 1080 .parent_data = gcc_parent_data_8, 1081 .num_parents = ARRAY_SIZE(gcc_parent_data_8), 1082 .flags = CLK_SET_RATE_PARENT, 1083 .ops = &clk_rcg2_shared_floor_ops, 1084 }, 1085 }; 1086 1087 static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_src[] = { 1088 F(400000, P_BI_TCXO, 12, 1, 4), 1089 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0), 1090 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), 1091 { } 1092 }; 1093 1094 static struct clk_rcg2 gcc_sdcc4_apps_clk_src = { 1095 .cmd_rcgr = 0x1601c, 1096 .mnd_width = 8, 1097 .hid_width = 5, 1098 .parent_map = gcc_parent_map_0, 1099 .freq_tbl = ftbl_gcc_sdcc4_apps_clk_src, 1100 .clkr.hw.init = &(const struct clk_init_data) { 1101 .name = "gcc_sdcc4_apps_clk_src", 1102 .parent_data = gcc_parent_data_0, 1103 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1104 .flags = CLK_SET_RATE_PARENT, 1105 .ops = &clk_rcg2_shared_floor_ops, 1106 }, 1107 }; 1108 1109 static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = { 1110 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0), 1111 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), 1112 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0), 1113 F(201500000, P_GCC_GPLL4_OUT_MAIN, 4, 0, 0), 1114 F(403000000, P_GCC_GPLL4_OUT_MAIN, 2, 0, 0), 1115 { } 1116 }; 1117 1118 static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = { 1119 .cmd_rcgr = 0x77034, 1120 .mnd_width = 8, 1121 .hid_width = 5, 1122 .parent_map = gcc_parent_map_3, 1123 .freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src, 1124 .clkr.hw.init = &(const struct clk_init_data) { 1125 .name = "gcc_ufs_phy_axi_clk_src", 1126 .parent_data = gcc_parent_data_3, 1127 .num_parents = ARRAY_SIZE(gcc_parent_data_3), 1128 .flags = CLK_SET_RATE_PARENT, 1129 .ops = &clk_rcg2_shared_no_init_park_ops, 1130 }, 1131 }; 1132 1133 static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = { 1134 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), 1135 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0), 1136 F(201500000, P_GCC_GPLL4_OUT_MAIN, 4, 0, 0), 1137 F(403000000, P_GCC_GPLL4_OUT_MAIN, 2, 0, 0), 1138 { } 1139 }; 1140 1141 static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = { 1142 .cmd_rcgr = 0x7708c, 1143 .mnd_width = 0, 1144 .hid_width = 5, 1145 .parent_map = gcc_parent_map_3, 1146 .freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src, 1147 .clkr.hw.init = &(const struct clk_init_data) { 1148 .name = "gcc_ufs_phy_ice_core_clk_src", 1149 .parent_data = gcc_parent_data_3, 1150 .num_parents = ARRAY_SIZE(gcc_parent_data_3), 1151 .flags = CLK_SET_RATE_PARENT, 1152 .ops = &clk_rcg2_shared_no_init_park_ops, 1153 }, 1154 }; 1155 1156 static const struct freq_tbl ftbl_gcc_ufs_phy_phy_aux_clk_src[] = { 1157 F(9600000, P_BI_TCXO, 2, 0, 0), 1158 F(19200000, P_BI_TCXO, 1, 0, 0), 1159 { } 1160 }; 1161 1162 static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = { 1163 .cmd_rcgr = 0x770c0, 1164 .mnd_width = 0, 1165 .hid_width = 5, 1166 .parent_map = gcc_parent_map_4, 1167 .freq_tbl = ftbl_gcc_ufs_phy_phy_aux_clk_src, 1168 .clkr.hw.init = &(const struct clk_init_data) { 1169 .name = "gcc_ufs_phy_phy_aux_clk_src", 1170 .parent_data = gcc_parent_data_4, 1171 .num_parents = ARRAY_SIZE(gcc_parent_data_4), 1172 .flags = CLK_SET_RATE_PARENT, 1173 .ops = &clk_rcg2_shared_no_init_park_ops, 1174 }, 1175 }; 1176 1177 static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = { 1178 .cmd_rcgr = 0x770a4, 1179 .mnd_width = 0, 1180 .hid_width = 5, 1181 .parent_map = gcc_parent_map_3, 1182 .freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src, 1183 .clkr.hw.init = &(const struct clk_init_data) { 1184 .name = "gcc_ufs_phy_unipro_core_clk_src", 1185 .parent_data = gcc_parent_data_3, 1186 .num_parents = ARRAY_SIZE(gcc_parent_data_3), 1187 .flags = CLK_SET_RATE_PARENT, 1188 .ops = &clk_rcg2_shared_no_init_park_ops, 1189 }, 1190 }; 1191 1192 static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = { 1193 F(66666667, P_GCC_GPLL0_OUT_EVEN, 4.5, 0, 0), 1194 F(133333333, P_GCC_GPLL0_OUT_MAIN, 4.5, 0, 0), 1195 F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0), 1196 F(240000000, P_GCC_GPLL0_OUT_MAIN, 2.5, 0, 0), 1197 { } 1198 }; 1199 1200 static struct clk_rcg2 gcc_usb30_prim_master_clk_src = { 1201 .cmd_rcgr = 0x39034, 1202 .mnd_width = 8, 1203 .hid_width = 5, 1204 .parent_map = gcc_parent_map_0, 1205 .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src, 1206 .clkr.hw.init = &(const struct clk_init_data) { 1207 .name = "gcc_usb30_prim_master_clk_src", 1208 .parent_data = gcc_parent_data_0, 1209 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1210 .flags = CLK_SET_RATE_PARENT, 1211 .ops = &clk_rcg2_shared_no_init_park_ops, 1212 }, 1213 }; 1214 1215 static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = { 1216 .cmd_rcgr = 0x3904c, 1217 .mnd_width = 0, 1218 .hid_width = 5, 1219 .parent_map = gcc_parent_map_0, 1220 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 1221 .clkr.hw.init = &(const struct clk_init_data) { 1222 .name = "gcc_usb30_prim_mock_utmi_clk_src", 1223 .parent_data = gcc_parent_data_0, 1224 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1225 .flags = CLK_SET_RATE_PARENT, 1226 .ops = &clk_rcg2_shared_no_init_park_ops, 1227 }, 1228 }; 1229 1230 static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = { 1231 .cmd_rcgr = 0x39078, 1232 .mnd_width = 0, 1233 .hid_width = 5, 1234 .parent_map = gcc_parent_map_6, 1235 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 1236 .clkr.hw.init = &(const struct clk_init_data) { 1237 .name = "gcc_usb3_prim_phy_aux_clk_src", 1238 .parent_data = gcc_parent_data_6, 1239 .num_parents = ARRAY_SIZE(gcc_parent_data_6), 1240 .flags = CLK_SET_RATE_PARENT, 1241 .ops = &clk_rcg2_shared_no_init_park_ops, 1242 }, 1243 }; 1244 1245 static struct clk_regmap_div gcc_qupv3_wrap1_s2_clk_src = { 1246 .reg = 0x1828c, 1247 .shift = 0, 1248 .width = 4, 1249 .clkr.hw.init = &(const struct clk_init_data) { 1250 .name = "gcc_qupv3_wrap1_s2_clk_src", 1251 .parent_hws = (const struct clk_hw*[]) { 1252 &gcc_qupv3_wrap1_qspi_ref_clk_src.clkr.hw, 1253 }, 1254 .num_parents = 1, 1255 .flags = CLK_SET_RATE_PARENT, 1256 .ops = &clk_regmap_div_ro_ops, 1257 }, 1258 }; 1259 1260 static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv_clk_src = { 1261 .reg = 0x39064, 1262 .shift = 0, 1263 .width = 4, 1264 .clkr.hw.init = &(const struct clk_init_data) { 1265 .name = "gcc_usb30_prim_mock_utmi_postdiv_clk_src", 1266 .parent_hws = (const struct clk_hw*[]) { 1267 &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw, 1268 }, 1269 .num_parents = 1, 1270 .flags = CLK_SET_RATE_PARENT, 1271 .ops = &clk_regmap_div_ro_ops, 1272 }, 1273 }; 1274 1275 static struct clk_branch gcc_aggre_noc_pcie_axi_clk = { 1276 .halt_reg = 0x10068, 1277 .halt_check = BRANCH_HALT_SKIP, 1278 .hwcg_reg = 0x10068, 1279 .hwcg_bit = 1, 1280 .clkr = { 1281 .enable_reg = 0x52000, 1282 .enable_mask = BIT(12), 1283 .hw.init = &(const struct clk_init_data) { 1284 .name = "gcc_aggre_noc_pcie_axi_clk", 1285 .ops = &clk_branch2_ops, 1286 }, 1287 }, 1288 }; 1289 1290 static struct clk_branch gcc_aggre_ufs_phy_axi_clk = { 1291 .halt_reg = 0x770f0, 1292 .halt_check = BRANCH_HALT_VOTED, 1293 .hwcg_reg = 0x770f0, 1294 .hwcg_bit = 1, 1295 .clkr = { 1296 .enable_reg = 0x770f0, 1297 .enable_mask = BIT(0), 1298 .hw.init = &(const struct clk_init_data) { 1299 .name = "gcc_aggre_ufs_phy_axi_clk", 1300 .parent_hws = (const struct clk_hw*[]) { 1301 &gcc_ufs_phy_axi_clk_src.clkr.hw, 1302 }, 1303 .num_parents = 1, 1304 .flags = CLK_SET_RATE_PARENT, 1305 .ops = &clk_branch2_ops, 1306 }, 1307 }, 1308 }; 1309 1310 static struct clk_branch gcc_aggre_usb3_prim_axi_clk = { 1311 .halt_reg = 0x39094, 1312 .halt_check = BRANCH_HALT_VOTED, 1313 .hwcg_reg = 0x39094, 1314 .hwcg_bit = 1, 1315 .clkr = { 1316 .enable_reg = 0x39094, 1317 .enable_mask = BIT(0), 1318 .hw.init = &(const struct clk_init_data) { 1319 .name = "gcc_aggre_usb3_prim_axi_clk", 1320 .parent_hws = (const struct clk_hw*[]) { 1321 &gcc_usb30_prim_master_clk_src.clkr.hw, 1322 }, 1323 .num_parents = 1, 1324 .flags = CLK_SET_RATE_PARENT, 1325 .ops = &clk_branch2_ops, 1326 }, 1327 }, 1328 }; 1329 1330 static struct clk_branch gcc_boot_rom_ahb_clk = { 1331 .halt_reg = 0x38004, 1332 .halt_check = BRANCH_HALT_VOTED, 1333 .hwcg_reg = 0x38004, 1334 .hwcg_bit = 1, 1335 .clkr = { 1336 .enable_reg = 0x52010, 1337 .enable_mask = BIT(18), 1338 .hw.init = &(const struct clk_init_data) { 1339 .name = "gcc_boot_rom_ahb_clk", 1340 .ops = &clk_branch2_ops, 1341 }, 1342 }, 1343 }; 1344 1345 static struct clk_branch gcc_camera_hf_axi_clk = { 1346 .halt_reg = 0x26014, 1347 .halt_check = BRANCH_HALT_SKIP, 1348 .hwcg_reg = 0x26014, 1349 .hwcg_bit = 1, 1350 .clkr = { 1351 .enable_reg = 0x26014, 1352 .enable_mask = BIT(0), 1353 .hw.init = &(const struct clk_init_data) { 1354 .name = "gcc_camera_hf_axi_clk", 1355 .ops = &clk_branch2_ops, 1356 }, 1357 }, 1358 }; 1359 1360 static struct clk_branch gcc_camera_sf_axi_clk = { 1361 .halt_reg = 0x26028, 1362 .halt_check = BRANCH_HALT_SKIP, 1363 .hwcg_reg = 0x26028, 1364 .hwcg_bit = 1, 1365 .clkr = { 1366 .enable_reg = 0x26028, 1367 .enable_mask = BIT(0), 1368 .hw.init = &(const struct clk_init_data) { 1369 .name = "gcc_camera_sf_axi_clk", 1370 .ops = &clk_branch2_ops, 1371 }, 1372 }, 1373 }; 1374 1375 static struct clk_branch gcc_cfg_noc_pcie_anoc_ahb_clk = { 1376 .halt_reg = 0x10050, 1377 .halt_check = BRANCH_HALT_SKIP, 1378 .hwcg_reg = 0x10050, 1379 .hwcg_bit = 1, 1380 .clkr = { 1381 .enable_reg = 0x52000, 1382 .enable_mask = BIT(20), 1383 .hw.init = &(const struct clk_init_data) { 1384 .name = "gcc_cfg_noc_pcie_anoc_ahb_clk", 1385 .ops = &clk_branch2_ops, 1386 }, 1387 }, 1388 }; 1389 1390 static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = { 1391 .halt_reg = 0x39090, 1392 .halt_check = BRANCH_HALT_VOTED, 1393 .hwcg_reg = 0x39090, 1394 .hwcg_bit = 1, 1395 .clkr = { 1396 .enable_reg = 0x39090, 1397 .enable_mask = BIT(0), 1398 .hw.init = &(const struct clk_init_data) { 1399 .name = "gcc_cfg_noc_usb3_prim_axi_clk", 1400 .parent_hws = (const struct clk_hw*[]) { 1401 &gcc_usb30_prim_master_clk_src.clkr.hw, 1402 }, 1403 .num_parents = 1, 1404 .flags = CLK_SET_RATE_PARENT, 1405 .ops = &clk_branch2_ops, 1406 }, 1407 }, 1408 }; 1409 1410 static struct clk_branch gcc_cnoc_pcie_sf_axi_clk = { 1411 .halt_reg = 0x10058, 1412 .halt_check = BRANCH_HALT_VOTED, 1413 .clkr = { 1414 .enable_reg = 0x52008, 1415 .enable_mask = BIT(6), 1416 .hw.init = &(const struct clk_init_data) { 1417 .name = "gcc_cnoc_pcie_sf_axi_clk", 1418 .ops = &clk_branch2_ops, 1419 }, 1420 }, 1421 }; 1422 1423 static struct clk_branch gcc_ddrss_pcie_sf_qtb_clk = { 1424 .halt_reg = 0x1007c, 1425 .halt_check = BRANCH_HALT_SKIP, 1426 .hwcg_reg = 0x1007c, 1427 .hwcg_bit = 1, 1428 .clkr = { 1429 .enable_reg = 0x52000, 1430 .enable_mask = BIT(19), 1431 .hw.init = &(const struct clk_init_data) { 1432 .name = "gcc_ddrss_pcie_sf_qtb_clk", 1433 .ops = &clk_branch2_ops, 1434 }, 1435 }, 1436 }; 1437 1438 static struct clk_branch gcc_disp_hf_axi_clk = { 1439 .halt_reg = 0x2701c, 1440 .halt_check = BRANCH_HALT_SKIP, 1441 .clkr = { 1442 .enable_reg = 0x2701c, 1443 .enable_mask = BIT(0), 1444 .hw.init = &(const struct clk_init_data) { 1445 .name = "gcc_disp_hf_axi_clk", 1446 .ops = &clk_branch2_ops, 1447 }, 1448 }, 1449 }; 1450 1451 static struct clk_branch gcc_disp_sf_axi_clk = { 1452 .halt_reg = 0x27008, 1453 .halt_check = BRANCH_HALT_SKIP, 1454 .hwcg_reg = 0x27008, 1455 .hwcg_bit = 1, 1456 .clkr = { 1457 .enable_reg = 0x27008, 1458 .enable_mask = BIT(0), 1459 .hw.init = &(const struct clk_init_data) { 1460 .name = "gcc_disp_sf_axi_clk", 1461 .ops = &clk_branch2_aon_ops, 1462 }, 1463 }, 1464 }; 1465 1466 static struct clk_branch gcc_eva_axi0_clk = { 1467 .halt_reg = 0x9f008, 1468 .halt_check = BRANCH_HALT_SKIP, 1469 .hwcg_reg = 0x9f008, 1470 .hwcg_bit = 1, 1471 .clkr = { 1472 .enable_reg = 0x9f008, 1473 .enable_mask = BIT(0), 1474 .hw.init = &(const struct clk_init_data) { 1475 .name = "gcc_eva_axi0_clk", 1476 .ops = &clk_branch2_ops, 1477 }, 1478 }, 1479 }; 1480 1481 static struct clk_branch gcc_eva_axi0c_clk = { 1482 .halt_reg = 0x9f01c, 1483 .halt_check = BRANCH_HALT_SKIP, 1484 .hwcg_reg = 0x9f01c, 1485 .hwcg_bit = 1, 1486 .clkr = { 1487 .enable_reg = 0x9f01c, 1488 .enable_mask = BIT(0), 1489 .hw.init = &(const struct clk_init_data) { 1490 .name = "gcc_eva_axi0c_clk", 1491 .ops = &clk_branch2_ops, 1492 }, 1493 }, 1494 }; 1495 1496 static struct clk_branch gcc_gp1_clk = { 1497 .halt_reg = 0x64000, 1498 .halt_check = BRANCH_HALT, 1499 .clkr = { 1500 .enable_reg = 0x64000, 1501 .enable_mask = BIT(0), 1502 .hw.init = &(const struct clk_init_data) { 1503 .name = "gcc_gp1_clk", 1504 .parent_hws = (const struct clk_hw*[]) { 1505 &gcc_gp1_clk_src.clkr.hw, 1506 }, 1507 .num_parents = 1, 1508 .flags = CLK_SET_RATE_PARENT, 1509 .ops = &clk_branch2_ops, 1510 }, 1511 }, 1512 }; 1513 1514 static struct clk_branch gcc_gp2_clk = { 1515 .halt_reg = 0x65000, 1516 .halt_check = BRANCH_HALT, 1517 .clkr = { 1518 .enable_reg = 0x65000, 1519 .enable_mask = BIT(0), 1520 .hw.init = &(const struct clk_init_data) { 1521 .name = "gcc_gp2_clk", 1522 .parent_hws = (const struct clk_hw*[]) { 1523 &gcc_gp2_clk_src.clkr.hw, 1524 }, 1525 .num_parents = 1, 1526 .flags = CLK_SET_RATE_PARENT, 1527 .ops = &clk_branch2_ops, 1528 }, 1529 }, 1530 }; 1531 1532 static struct clk_branch gcc_gp3_clk = { 1533 .halt_reg = 0x66000, 1534 .halt_check = BRANCH_HALT, 1535 .clkr = { 1536 .enable_reg = 0x66000, 1537 .enable_mask = BIT(0), 1538 .hw.init = &(const struct clk_init_data) { 1539 .name = "gcc_gp3_clk", 1540 .parent_hws = (const struct clk_hw*[]) { 1541 &gcc_gp3_clk_src.clkr.hw, 1542 }, 1543 .num_parents = 1, 1544 .flags = CLK_SET_RATE_PARENT, 1545 .ops = &clk_branch2_ops, 1546 }, 1547 }, 1548 }; 1549 1550 static struct clk_branch gcc_gpu_gemnoc_gfx_clk = { 1551 .halt_reg = 0x71010, 1552 .halt_check = BRANCH_HALT_VOTED, 1553 .hwcg_reg = 0x71010, 1554 .hwcg_bit = 1, 1555 .clkr = { 1556 .enable_reg = 0x71010, 1557 .enable_mask = BIT(0), 1558 .hw.init = &(const struct clk_init_data) { 1559 .name = "gcc_gpu_gemnoc_gfx_clk", 1560 .ops = &clk_branch2_ops, 1561 }, 1562 }, 1563 }; 1564 1565 static struct clk_branch gcc_gpu_gpll0_clk_src = { 1566 .halt_check = BRANCH_HALT_DELAY, 1567 .clkr = { 1568 .enable_reg = 0x52000, 1569 .enable_mask = BIT(15), 1570 .hw.init = &(const struct clk_init_data) { 1571 .name = "gcc_gpu_gpll0_clk_src", 1572 .parent_hws = (const struct clk_hw*[]) { 1573 &gcc_gpll0.clkr.hw, 1574 }, 1575 .num_parents = 1, 1576 .flags = CLK_SET_RATE_PARENT, 1577 .ops = &clk_branch2_ops, 1578 }, 1579 }, 1580 }; 1581 1582 static struct clk_branch gcc_gpu_gpll0_div_clk_src = { 1583 .halt_check = BRANCH_HALT_DELAY, 1584 .clkr = { 1585 .enable_reg = 0x52000, 1586 .enable_mask = BIT(16), 1587 .hw.init = &(const struct clk_init_data) { 1588 .name = "gcc_gpu_gpll0_div_clk_src", 1589 .parent_hws = (const struct clk_hw*[]) { 1590 &gcc_gpll0_out_even.clkr.hw, 1591 }, 1592 .num_parents = 1, 1593 .flags = CLK_SET_RATE_PARENT, 1594 .ops = &clk_branch2_ops, 1595 }, 1596 }, 1597 }; 1598 1599 static struct clk_branch gcc_pcie_0_aux_clk = { 1600 .halt_reg = 0x6b044, 1601 .halt_check = BRANCH_HALT_VOTED, 1602 .clkr = { 1603 .enable_reg = 0x52008, 1604 .enable_mask = BIT(3), 1605 .hw.init = &(const struct clk_init_data) { 1606 .name = "gcc_pcie_0_aux_clk", 1607 .parent_hws = (const struct clk_hw*[]) { 1608 &gcc_pcie_0_aux_clk_src.clkr.hw, 1609 }, 1610 .num_parents = 1, 1611 .flags = CLK_SET_RATE_PARENT, 1612 .ops = &clk_branch2_ops, 1613 }, 1614 }, 1615 }; 1616 1617 static struct clk_branch gcc_pcie_0_cfg_ahb_clk = { 1618 .halt_reg = 0x6b040, 1619 .halt_check = BRANCH_HALT_VOTED, 1620 .hwcg_reg = 0x6b040, 1621 .hwcg_bit = 1, 1622 .clkr = { 1623 .enable_reg = 0x52008, 1624 .enable_mask = BIT(2), 1625 .hw.init = &(const struct clk_init_data) { 1626 .name = "gcc_pcie_0_cfg_ahb_clk", 1627 .ops = &clk_branch2_ops, 1628 }, 1629 }, 1630 }; 1631 1632 static struct clk_branch gcc_pcie_0_mstr_axi_clk = { 1633 .halt_reg = 0x6b030, 1634 .halt_check = BRANCH_HALT_SKIP, 1635 .hwcg_reg = 0x6b030, 1636 .hwcg_bit = 1, 1637 .clkr = { 1638 .enable_reg = 0x52008, 1639 .enable_mask = BIT(1), 1640 .hw.init = &(const struct clk_init_data) { 1641 .name = "gcc_pcie_0_mstr_axi_clk", 1642 .ops = &clk_branch2_ops, 1643 }, 1644 }, 1645 }; 1646 1647 static struct clk_branch gcc_pcie_0_phy_aux_clk = { 1648 .halt_reg = 0x6b054, 1649 .halt_check = BRANCH_HALT_VOTED, 1650 .clkr = { 1651 .enable_reg = 0x52018, 1652 .enable_mask = BIT(31), 1653 .hw.init = &(const struct clk_init_data) { 1654 .name = "gcc_pcie_0_phy_aux_clk", 1655 .parent_hws = (const struct clk_hw*[]) { 1656 &gcc_pcie_0_phy_aux_clk_src.clkr.hw, 1657 }, 1658 .num_parents = 1, 1659 .flags = CLK_SET_RATE_PARENT, 1660 .ops = &clk_branch2_ops, 1661 }, 1662 }, 1663 }; 1664 1665 static struct clk_branch gcc_pcie_0_phy_rchng_clk = { 1666 .halt_reg = 0x6b074, 1667 .halt_check = BRANCH_HALT_VOTED, 1668 .clkr = { 1669 .enable_reg = 0x52000, 1670 .enable_mask = BIT(22), 1671 .hw.init = &(const struct clk_init_data) { 1672 .name = "gcc_pcie_0_phy_rchng_clk", 1673 .parent_hws = (const struct clk_hw*[]) { 1674 &gcc_pcie_0_phy_rchng_clk_src.clkr.hw, 1675 }, 1676 .num_parents = 1, 1677 .flags = CLK_SET_RATE_PARENT, 1678 .ops = &clk_branch2_ops, 1679 }, 1680 }, 1681 }; 1682 1683 static struct clk_branch gcc_pcie_0_pipe_clk = { 1684 .halt_reg = 0x6b064, 1685 .halt_check = BRANCH_HALT_SKIP, 1686 .clkr = { 1687 .enable_reg = 0x52008, 1688 .enable_mask = BIT(4), 1689 .hw.init = &(const struct clk_init_data) { 1690 .name = "gcc_pcie_0_pipe_clk", 1691 .parent_hws = (const struct clk_hw*[]) { 1692 &gcc_pcie_0_pipe_clk_src.clkr.hw, 1693 }, 1694 .num_parents = 1, 1695 .flags = CLK_SET_RATE_PARENT, 1696 .ops = &clk_branch2_ops, 1697 }, 1698 }, 1699 }; 1700 1701 static struct clk_branch gcc_pcie_0_slv_axi_clk = { 1702 .halt_reg = 0x6b020, 1703 .halt_check = BRANCH_HALT_VOTED, 1704 .hwcg_reg = 0x6b020, 1705 .hwcg_bit = 1, 1706 .clkr = { 1707 .enable_reg = 0x52008, 1708 .enable_mask = BIT(0), 1709 .hw.init = &(const struct clk_init_data) { 1710 .name = "gcc_pcie_0_slv_axi_clk", 1711 .ops = &clk_branch2_ops, 1712 }, 1713 }, 1714 }; 1715 1716 static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = { 1717 .halt_reg = 0x6b01c, 1718 .halt_check = BRANCH_HALT_VOTED, 1719 .clkr = { 1720 .enable_reg = 0x52008, 1721 .enable_mask = BIT(5), 1722 .hw.init = &(const struct clk_init_data) { 1723 .name = "gcc_pcie_0_slv_q2a_axi_clk", 1724 .ops = &clk_branch2_ops, 1725 }, 1726 }, 1727 }; 1728 1729 static struct clk_branch gcc_pdm2_clk = { 1730 .halt_reg = 0x3300c, 1731 .halt_check = BRANCH_HALT, 1732 .clkr = { 1733 .enable_reg = 0x3300c, 1734 .enable_mask = BIT(0), 1735 .hw.init = &(const struct clk_init_data) { 1736 .name = "gcc_pdm2_clk", 1737 .parent_hws = (const struct clk_hw*[]) { 1738 &gcc_pdm2_clk_src.clkr.hw, 1739 }, 1740 .num_parents = 1, 1741 .flags = CLK_SET_RATE_PARENT, 1742 .ops = &clk_branch2_ops, 1743 }, 1744 }, 1745 }; 1746 1747 static struct clk_branch gcc_pdm_ahb_clk = { 1748 .halt_reg = 0x33004, 1749 .halt_check = BRANCH_HALT_VOTED, 1750 .hwcg_reg = 0x33004, 1751 .hwcg_bit = 1, 1752 .clkr = { 1753 .enable_reg = 0x33004, 1754 .enable_mask = BIT(0), 1755 .hw.init = &(const struct clk_init_data) { 1756 .name = "gcc_pdm_ahb_clk", 1757 .ops = &clk_branch2_ops, 1758 }, 1759 }, 1760 }; 1761 1762 static struct clk_branch gcc_pdm_xo4_clk = { 1763 .halt_reg = 0x33008, 1764 .halt_check = BRANCH_HALT, 1765 .clkr = { 1766 .enable_reg = 0x33008, 1767 .enable_mask = BIT(0), 1768 .hw.init = &(const struct clk_init_data) { 1769 .name = "gcc_pdm_xo4_clk", 1770 .ops = &clk_branch2_ops, 1771 }, 1772 }, 1773 }; 1774 1775 static struct clk_branch gcc_qmip_camera_cmd_ahb_clk = { 1776 .halt_reg = 0x26010, 1777 .halt_check = BRANCH_HALT_VOTED, 1778 .hwcg_reg = 0x26010, 1779 .hwcg_bit = 1, 1780 .clkr = { 1781 .enable_reg = 0x26010, 1782 .enable_mask = BIT(0), 1783 .hw.init = &(const struct clk_init_data) { 1784 .name = "gcc_qmip_camera_cmd_ahb_clk", 1785 .ops = &clk_branch2_ops, 1786 }, 1787 }, 1788 }; 1789 1790 static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = { 1791 .halt_reg = 0x26008, 1792 .halt_check = BRANCH_HALT_VOTED, 1793 .hwcg_reg = 0x26008, 1794 .hwcg_bit = 1, 1795 .clkr = { 1796 .enable_reg = 0x26008, 1797 .enable_mask = BIT(0), 1798 .hw.init = &(const struct clk_init_data) { 1799 .name = "gcc_qmip_camera_nrt_ahb_clk", 1800 .ops = &clk_branch2_ops, 1801 }, 1802 }, 1803 }; 1804 1805 static struct clk_branch gcc_qmip_camera_rt_ahb_clk = { 1806 .halt_reg = 0x2600c, 1807 .halt_check = BRANCH_HALT_VOTED, 1808 .hwcg_reg = 0x2600c, 1809 .hwcg_bit = 1, 1810 .clkr = { 1811 .enable_reg = 0x2600c, 1812 .enable_mask = BIT(0), 1813 .hw.init = &(const struct clk_init_data) { 1814 .name = "gcc_qmip_camera_rt_ahb_clk", 1815 .ops = &clk_branch2_ops, 1816 }, 1817 }, 1818 }; 1819 1820 static struct clk_branch gcc_qmip_disp_dcp_sf_ahb_clk = { 1821 .halt_reg = 0x27030, 1822 .halt_check = BRANCH_HALT_VOTED, 1823 .hwcg_reg = 0x27030, 1824 .hwcg_bit = 1, 1825 .clkr = { 1826 .enable_reg = 0x27030, 1827 .enable_mask = BIT(0), 1828 .hw.init = &(const struct clk_init_data) { 1829 .name = "gcc_qmip_disp_dcp_sf_ahb_clk", 1830 .ops = &clk_branch2_ops, 1831 }, 1832 }, 1833 }; 1834 1835 static struct clk_branch gcc_qmip_gpu_ahb_clk = { 1836 .halt_reg = 0x71008, 1837 .halt_check = BRANCH_HALT_VOTED, 1838 .hwcg_reg = 0x71008, 1839 .hwcg_bit = 1, 1840 .clkr = { 1841 .enable_reg = 0x71008, 1842 .enable_mask = BIT(0), 1843 .hw.init = &(const struct clk_init_data) { 1844 .name = "gcc_qmip_gpu_ahb_clk", 1845 .ops = &clk_branch2_ops, 1846 }, 1847 }, 1848 }; 1849 1850 static struct clk_branch gcc_qmip_pcie_ahb_clk = { 1851 .halt_reg = 0x6b018, 1852 .halt_check = BRANCH_HALT_VOTED, 1853 .hwcg_reg = 0x6b018, 1854 .hwcg_bit = 1, 1855 .clkr = { 1856 .enable_reg = 0x52010, 1857 .enable_mask = BIT(19), 1858 .hw.init = &(const struct clk_init_data) { 1859 .name = "gcc_qmip_pcie_ahb_clk", 1860 .ops = &clk_branch2_ops, 1861 }, 1862 }, 1863 }; 1864 1865 static struct clk_branch gcc_qmip_video_cv_cpu_ahb_clk = { 1866 .halt_reg = 0x32014, 1867 .halt_check = BRANCH_HALT_VOTED, 1868 .hwcg_reg = 0x32014, 1869 .hwcg_bit = 1, 1870 .clkr = { 1871 .enable_reg = 0x32014, 1872 .enable_mask = BIT(0), 1873 .hw.init = &(const struct clk_init_data) { 1874 .name = "gcc_qmip_video_cv_cpu_ahb_clk", 1875 .ops = &clk_branch2_ops, 1876 }, 1877 }, 1878 }; 1879 1880 static struct clk_branch gcc_qmip_video_cvp_ahb_clk = { 1881 .halt_reg = 0x32008, 1882 .halt_check = BRANCH_HALT_VOTED, 1883 .hwcg_reg = 0x32008, 1884 .hwcg_bit = 1, 1885 .clkr = { 1886 .enable_reg = 0x32008, 1887 .enable_mask = BIT(0), 1888 .hw.init = &(const struct clk_init_data) { 1889 .name = "gcc_qmip_video_cvp_ahb_clk", 1890 .ops = &clk_branch2_ops, 1891 }, 1892 }, 1893 }; 1894 1895 static struct clk_branch gcc_qmip_video_v_cpu_ahb_clk = { 1896 .halt_reg = 0x32010, 1897 .halt_check = BRANCH_HALT_VOTED, 1898 .hwcg_reg = 0x32010, 1899 .hwcg_bit = 1, 1900 .clkr = { 1901 .enable_reg = 0x32010, 1902 .enable_mask = BIT(0), 1903 .hw.init = &(const struct clk_init_data) { 1904 .name = "gcc_qmip_video_v_cpu_ahb_clk", 1905 .ops = &clk_branch2_ops, 1906 }, 1907 }, 1908 }; 1909 1910 static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = { 1911 .halt_reg = 0x3200c, 1912 .halt_check = BRANCH_HALT_VOTED, 1913 .hwcg_reg = 0x3200c, 1914 .hwcg_bit = 1, 1915 .clkr = { 1916 .enable_reg = 0x3200c, 1917 .enable_mask = BIT(0), 1918 .hw.init = &(const struct clk_init_data) { 1919 .name = "gcc_qmip_video_vcodec_ahb_clk", 1920 .ops = &clk_branch2_ops, 1921 }, 1922 }, 1923 }; 1924 1925 static struct clk_branch gcc_qupv3_i2c_core_clk = { 1926 .halt_reg = 0x23004, 1927 .halt_check = BRANCH_HALT_VOTED, 1928 .clkr = { 1929 .enable_reg = 0x52008, 1930 .enable_mask = BIT(8), 1931 .hw.init = &(const struct clk_init_data) { 1932 .name = "gcc_qupv3_i2c_core_clk", 1933 .ops = &clk_branch2_ops, 1934 }, 1935 }, 1936 }; 1937 1938 static struct clk_branch gcc_qupv3_i2c_s0_clk = { 1939 .halt_reg = 0x17004, 1940 .halt_check = BRANCH_HALT_VOTED, 1941 .clkr = { 1942 .enable_reg = 0x52008, 1943 .enable_mask = BIT(10), 1944 .hw.init = &(const struct clk_init_data) { 1945 .name = "gcc_qupv3_i2c_s0_clk", 1946 .parent_hws = (const struct clk_hw*[]) { 1947 &gcc_qupv3_i2c_s0_clk_src.clkr.hw, 1948 }, 1949 .num_parents = 1, 1950 .flags = CLK_SET_RATE_PARENT, 1951 .ops = &clk_branch2_ops, 1952 }, 1953 }, 1954 }; 1955 1956 static struct clk_branch gcc_qupv3_i2c_s1_clk = { 1957 .halt_reg = 0x17020, 1958 .halt_check = BRANCH_HALT_VOTED, 1959 .clkr = { 1960 .enable_reg = 0x52008, 1961 .enable_mask = BIT(11), 1962 .hw.init = &(const struct clk_init_data) { 1963 .name = "gcc_qupv3_i2c_s1_clk", 1964 .parent_hws = (const struct clk_hw*[]) { 1965 &gcc_qupv3_i2c_s1_clk_src.clkr.hw, 1966 }, 1967 .num_parents = 1, 1968 .flags = CLK_SET_RATE_PARENT, 1969 .ops = &clk_branch2_ops, 1970 }, 1971 }, 1972 }; 1973 1974 static struct clk_branch gcc_qupv3_i2c_s2_clk = { 1975 .halt_reg = 0x1703c, 1976 .halt_check = BRANCH_HALT_VOTED, 1977 .clkr = { 1978 .enable_reg = 0x52008, 1979 .enable_mask = BIT(12), 1980 .hw.init = &(const struct clk_init_data) { 1981 .name = "gcc_qupv3_i2c_s2_clk", 1982 .parent_hws = (const struct clk_hw*[]) { 1983 &gcc_qupv3_i2c_s2_clk_src.clkr.hw, 1984 }, 1985 .num_parents = 1, 1986 .flags = CLK_SET_RATE_PARENT, 1987 .ops = &clk_branch2_ops, 1988 }, 1989 }, 1990 }; 1991 1992 static struct clk_branch gcc_qupv3_i2c_s3_clk = { 1993 .halt_reg = 0x17058, 1994 .halt_check = BRANCH_HALT_VOTED, 1995 .clkr = { 1996 .enable_reg = 0x52008, 1997 .enable_mask = BIT(13), 1998 .hw.init = &(const struct clk_init_data) { 1999 .name = "gcc_qupv3_i2c_s3_clk", 2000 .parent_hws = (const struct clk_hw*[]) { 2001 &gcc_qupv3_i2c_s3_clk_src.clkr.hw, 2002 }, 2003 .num_parents = 1, 2004 .flags = CLK_SET_RATE_PARENT, 2005 .ops = &clk_branch2_ops, 2006 }, 2007 }, 2008 }; 2009 2010 static struct clk_branch gcc_qupv3_i2c_s4_clk = { 2011 .halt_reg = 0x17074, 2012 .halt_check = BRANCH_HALT_VOTED, 2013 .clkr = { 2014 .enable_reg = 0x52008, 2015 .enable_mask = BIT(14), 2016 .hw.init = &(const struct clk_init_data) { 2017 .name = "gcc_qupv3_i2c_s4_clk", 2018 .parent_hws = (const struct clk_hw*[]) { 2019 &gcc_qupv3_i2c_s4_clk_src.clkr.hw, 2020 }, 2021 .num_parents = 1, 2022 .flags = CLK_SET_RATE_PARENT, 2023 .ops = &clk_branch2_ops, 2024 }, 2025 }, 2026 }; 2027 2028 static struct clk_branch gcc_qupv3_i2c_s_ahb_clk = { 2029 .halt_reg = 0x23000, 2030 .halt_check = BRANCH_HALT_VOTED, 2031 .hwcg_reg = 0x23000, 2032 .hwcg_bit = 1, 2033 .clkr = { 2034 .enable_reg = 0x52008, 2035 .enable_mask = BIT(7), 2036 .hw.init = &(const struct clk_init_data) { 2037 .name = "gcc_qupv3_i2c_s_ahb_clk", 2038 .ops = &clk_branch2_ops, 2039 }, 2040 }, 2041 }; 2042 2043 static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = { 2044 .halt_reg = 0x2315c, 2045 .halt_check = BRANCH_HALT_VOTED, 2046 .clkr = { 2047 .enable_reg = 0x52008, 2048 .enable_mask = BIT(18), 2049 .hw.init = &(const struct clk_init_data) { 2050 .name = "gcc_qupv3_wrap1_core_2x_clk", 2051 .ops = &clk_branch2_ops, 2052 }, 2053 }, 2054 }; 2055 2056 static struct clk_branch gcc_qupv3_wrap1_core_clk = { 2057 .halt_reg = 0x23148, 2058 .halt_check = BRANCH_HALT_VOTED, 2059 .clkr = { 2060 .enable_reg = 0x52008, 2061 .enable_mask = BIT(19), 2062 .hw.init = &(const struct clk_init_data) { 2063 .name = "gcc_qupv3_wrap1_core_clk", 2064 .ops = &clk_branch2_ops, 2065 }, 2066 }, 2067 }; 2068 2069 static struct clk_branch gcc_qupv3_wrap1_qspi_ref_clk = { 2070 .halt_reg = 0x188bc, 2071 .halt_check = BRANCH_HALT_VOTED, 2072 .clkr = { 2073 .enable_reg = 0x52010, 2074 .enable_mask = BIT(29), 2075 .hw.init = &(const struct clk_init_data) { 2076 .name = "gcc_qupv3_wrap1_qspi_ref_clk", 2077 .parent_hws = (const struct clk_hw*[]) { 2078 &gcc_qupv3_wrap1_qspi_ref_clk_src.clkr.hw, 2079 }, 2080 .num_parents = 1, 2081 .flags = CLK_SET_RATE_PARENT, 2082 .ops = &clk_branch2_ops, 2083 }, 2084 }, 2085 }; 2086 2087 static struct clk_branch gcc_qupv3_wrap1_s0_clk = { 2088 .halt_reg = 0x18004, 2089 .halt_check = BRANCH_HALT_VOTED, 2090 .clkr = { 2091 .enable_reg = 0x52008, 2092 .enable_mask = BIT(22), 2093 .hw.init = &(const struct clk_init_data) { 2094 .name = "gcc_qupv3_wrap1_s0_clk", 2095 .parent_hws = (const struct clk_hw*[]) { 2096 &gcc_qupv3_wrap1_s0_clk_src.clkr.hw, 2097 }, 2098 .num_parents = 1, 2099 .flags = CLK_SET_RATE_PARENT, 2100 .ops = &clk_branch2_ops, 2101 }, 2102 }, 2103 }; 2104 2105 static struct clk_branch gcc_qupv3_wrap1_s1_clk = { 2106 .halt_reg = 0x18140, 2107 .halt_check = BRANCH_HALT_VOTED, 2108 .clkr = { 2109 .enable_reg = 0x52008, 2110 .enable_mask = BIT(23), 2111 .hw.init = &(const struct clk_init_data) { 2112 .name = "gcc_qupv3_wrap1_s1_clk", 2113 .parent_hws = (const struct clk_hw*[]) { 2114 &gcc_qupv3_wrap1_s1_clk_src.clkr.hw, 2115 }, 2116 .num_parents = 1, 2117 .flags = CLK_SET_RATE_PARENT, 2118 .ops = &clk_branch2_ops, 2119 }, 2120 }, 2121 }; 2122 2123 static struct clk_branch gcc_qupv3_wrap1_s2_clk = { 2124 .halt_reg = 0x1827c, 2125 .halt_check = BRANCH_HALT_VOTED, 2126 .clkr = { 2127 .enable_reg = 0x52008, 2128 .enable_mask = BIT(24), 2129 .hw.init = &(const struct clk_init_data) { 2130 .name = "gcc_qupv3_wrap1_s2_clk", 2131 .parent_hws = (const struct clk_hw*[]) { 2132 &gcc_qupv3_wrap1_s2_clk_src.clkr.hw, 2133 }, 2134 .num_parents = 1, 2135 .flags = CLK_SET_RATE_PARENT, 2136 .ops = &clk_branch2_ops, 2137 }, 2138 }, 2139 }; 2140 2141 static struct clk_branch gcc_qupv3_wrap1_s3_clk = { 2142 .halt_reg = 0x18290, 2143 .halt_check = BRANCH_HALT_VOTED, 2144 .clkr = { 2145 .enable_reg = 0x52008, 2146 .enable_mask = BIT(25), 2147 .hw.init = &(const struct clk_init_data) { 2148 .name = "gcc_qupv3_wrap1_s3_clk", 2149 .parent_hws = (const struct clk_hw*[]) { 2150 &gcc_qupv3_wrap1_s3_clk_src.clkr.hw, 2151 }, 2152 .num_parents = 1, 2153 .flags = CLK_SET_RATE_PARENT, 2154 .ops = &clk_branch2_ops, 2155 }, 2156 }, 2157 }; 2158 2159 static struct clk_branch gcc_qupv3_wrap1_s4_clk = { 2160 .halt_reg = 0x183cc, 2161 .halt_check = BRANCH_HALT_VOTED, 2162 .clkr = { 2163 .enable_reg = 0x52008, 2164 .enable_mask = BIT(26), 2165 .hw.init = &(const struct clk_init_data) { 2166 .name = "gcc_qupv3_wrap1_s4_clk", 2167 .parent_hws = (const struct clk_hw*[]) { 2168 &gcc_qupv3_wrap1_s4_clk_src.clkr.hw, 2169 }, 2170 .num_parents = 1, 2171 .flags = CLK_SET_RATE_PARENT, 2172 .ops = &clk_branch2_ops, 2173 }, 2174 }, 2175 }; 2176 2177 static struct clk_branch gcc_qupv3_wrap1_s5_clk = { 2178 .halt_reg = 0x18508, 2179 .halt_check = BRANCH_HALT_VOTED, 2180 .clkr = { 2181 .enable_reg = 0x52008, 2182 .enable_mask = BIT(27), 2183 .hw.init = &(const struct clk_init_data) { 2184 .name = "gcc_qupv3_wrap1_s5_clk", 2185 .parent_hws = (const struct clk_hw*[]) { 2186 &gcc_qupv3_wrap1_s5_clk_src.clkr.hw, 2187 }, 2188 .num_parents = 1, 2189 .flags = CLK_SET_RATE_PARENT, 2190 .ops = &clk_branch2_ops, 2191 }, 2192 }, 2193 }; 2194 2195 static struct clk_branch gcc_qupv3_wrap1_s6_clk = { 2196 .halt_reg = 0x18644, 2197 .halt_check = BRANCH_HALT_VOTED, 2198 .clkr = { 2199 .enable_reg = 0x52008, 2200 .enable_mask = BIT(28), 2201 .hw.init = &(const struct clk_init_data) { 2202 .name = "gcc_qupv3_wrap1_s6_clk", 2203 .parent_hws = (const struct clk_hw*[]) { 2204 &gcc_qupv3_wrap1_s6_clk_src.clkr.hw, 2205 }, 2206 .num_parents = 1, 2207 .flags = CLK_SET_RATE_PARENT, 2208 .ops = &clk_branch2_ops, 2209 }, 2210 }, 2211 }; 2212 2213 static struct clk_branch gcc_qupv3_wrap1_s7_clk = { 2214 .halt_reg = 0x18780, 2215 .halt_check = BRANCH_HALT_VOTED, 2216 .clkr = { 2217 .enable_reg = 0x52010, 2218 .enable_mask = BIT(16), 2219 .hw.init = &(const struct clk_init_data) { 2220 .name = "gcc_qupv3_wrap1_s7_clk", 2221 .parent_hws = (const struct clk_hw*[]) { 2222 &gcc_qupv3_wrap1_s7_clk_src.clkr.hw, 2223 }, 2224 .num_parents = 1, 2225 .flags = CLK_SET_RATE_PARENT, 2226 .ops = &clk_branch2_ops, 2227 }, 2228 }, 2229 }; 2230 2231 static struct clk_branch gcc_qupv3_wrap2_core_2x_clk = { 2232 .halt_reg = 0x232b4, 2233 .halt_check = BRANCH_HALT_VOTED, 2234 .clkr = { 2235 .enable_reg = 0x52010, 2236 .enable_mask = BIT(3), 2237 .hw.init = &(const struct clk_init_data) { 2238 .name = "gcc_qupv3_wrap2_core_2x_clk", 2239 .ops = &clk_branch2_ops, 2240 }, 2241 }, 2242 }; 2243 2244 static struct clk_branch gcc_qupv3_wrap2_core_clk = { 2245 .halt_reg = 0x232a0, 2246 .halt_check = BRANCH_HALT_VOTED, 2247 .clkr = { 2248 .enable_reg = 0x52010, 2249 .enable_mask = BIT(0), 2250 .hw.init = &(const struct clk_init_data) { 2251 .name = "gcc_qupv3_wrap2_core_clk", 2252 .ops = &clk_branch2_ops, 2253 }, 2254 }, 2255 }; 2256 2257 static struct clk_branch gcc_qupv3_wrap2_s0_clk = { 2258 .halt_reg = 0x1e004, 2259 .halt_check = BRANCH_HALT_VOTED, 2260 .clkr = { 2261 .enable_reg = 0x52010, 2262 .enable_mask = BIT(4), 2263 .hw.init = &(const struct clk_init_data) { 2264 .name = "gcc_qupv3_wrap2_s0_clk", 2265 .parent_hws = (const struct clk_hw*[]) { 2266 &gcc_qupv3_wrap2_s0_clk_src.clkr.hw, 2267 }, 2268 .num_parents = 1, 2269 .flags = CLK_SET_RATE_PARENT, 2270 .ops = &clk_branch2_ops, 2271 }, 2272 }, 2273 }; 2274 2275 static struct clk_branch gcc_qupv3_wrap2_s1_clk = { 2276 .halt_reg = 0x1e140, 2277 .halt_check = BRANCH_HALT_VOTED, 2278 .clkr = { 2279 .enable_reg = 0x52010, 2280 .enable_mask = BIT(5), 2281 .hw.init = &(const struct clk_init_data) { 2282 .name = "gcc_qupv3_wrap2_s1_clk", 2283 .parent_hws = (const struct clk_hw*[]) { 2284 &gcc_qupv3_wrap2_s1_clk_src.clkr.hw, 2285 }, 2286 .num_parents = 1, 2287 .flags = CLK_SET_RATE_PARENT, 2288 .ops = &clk_branch2_ops, 2289 }, 2290 }, 2291 }; 2292 2293 static struct clk_branch gcc_qupv3_wrap2_s2_clk = { 2294 .halt_reg = 0x1e27c, 2295 .halt_check = BRANCH_HALT_VOTED, 2296 .clkr = { 2297 .enable_reg = 0x52010, 2298 .enable_mask = BIT(6), 2299 .hw.init = &(const struct clk_init_data) { 2300 .name = "gcc_qupv3_wrap2_s2_clk", 2301 .parent_hws = (const struct clk_hw*[]) { 2302 &gcc_qupv3_wrap2_s2_clk_src.clkr.hw, 2303 }, 2304 .num_parents = 1, 2305 .flags = CLK_SET_RATE_PARENT, 2306 .ops = &clk_branch2_ops, 2307 }, 2308 }, 2309 }; 2310 2311 static struct clk_branch gcc_qupv3_wrap2_s3_clk = { 2312 .halt_reg = 0x1e3b8, 2313 .halt_check = BRANCH_HALT_VOTED, 2314 .clkr = { 2315 .enable_reg = 0x52010, 2316 .enable_mask = BIT(7), 2317 .hw.init = &(const struct clk_init_data) { 2318 .name = "gcc_qupv3_wrap2_s3_clk", 2319 .parent_hws = (const struct clk_hw*[]) { 2320 &gcc_qupv3_wrap2_s3_clk_src.clkr.hw, 2321 }, 2322 .num_parents = 1, 2323 .flags = CLK_SET_RATE_PARENT, 2324 .ops = &clk_branch2_ops, 2325 }, 2326 }, 2327 }; 2328 2329 static struct clk_branch gcc_qupv3_wrap2_s4_clk = { 2330 .halt_reg = 0x1e4f4, 2331 .halt_check = BRANCH_HALT_VOTED, 2332 .clkr = { 2333 .enable_reg = 0x52010, 2334 .enable_mask = BIT(8), 2335 .hw.init = &(const struct clk_init_data) { 2336 .name = "gcc_qupv3_wrap2_s4_clk", 2337 .parent_hws = (const struct clk_hw*[]) { 2338 &gcc_qupv3_wrap2_s4_clk_src.clkr.hw, 2339 }, 2340 .num_parents = 1, 2341 .flags = CLK_SET_RATE_PARENT, 2342 .ops = &clk_branch2_ops, 2343 }, 2344 }, 2345 }; 2346 2347 static struct clk_branch gcc_qupv3_wrap3_core_2x_clk = { 2348 .halt_reg = 0x2340c, 2349 .halt_check = BRANCH_HALT_VOTED, 2350 .clkr = { 2351 .enable_reg = 0x52018, 2352 .enable_mask = BIT(11), 2353 .hw.init = &(const struct clk_init_data) { 2354 .name = "gcc_qupv3_wrap3_core_2x_clk", 2355 .ops = &clk_branch2_ops, 2356 }, 2357 }, 2358 }; 2359 2360 static struct clk_branch gcc_qupv3_wrap3_core_clk = { 2361 .halt_reg = 0x233f8, 2362 .halt_check = BRANCH_HALT_VOTED, 2363 .clkr = { 2364 .enable_reg = 0x52018, 2365 .enable_mask = BIT(10), 2366 .hw.init = &(const struct clk_init_data) { 2367 .name = "gcc_qupv3_wrap3_core_clk", 2368 .ops = &clk_branch2_ops, 2369 }, 2370 }, 2371 }; 2372 2373 static struct clk_branch gcc_qupv3_wrap3_ibi_ctrl_1_clk = { 2374 .halt_reg = 0xa8774, 2375 .halt_check = BRANCH_HALT_VOTED, 2376 .hwcg_reg = 0xa8774, 2377 .hwcg_bit = 1, 2378 .clkr = { 2379 .enable_reg = 0x52018, 2380 .enable_mask = BIT(20), 2381 .hw.init = &(const struct clk_init_data) { 2382 .name = "gcc_qupv3_wrap3_ibi_ctrl_1_clk", 2383 .parent_hws = (const struct clk_hw*[]) { 2384 &gcc_qupv3_wrap3_ibi_ctrl_0_clk_src.clkr.hw, 2385 }, 2386 .num_parents = 1, 2387 .flags = CLK_SET_RATE_PARENT, 2388 .ops = &clk_branch2_ops, 2389 }, 2390 }, 2391 }; 2392 2393 static struct clk_branch gcc_qupv3_wrap3_ibi_ctrl_2_clk = { 2394 .halt_reg = 0xa8778, 2395 .halt_check = BRANCH_HALT_VOTED, 2396 .hwcg_reg = 0xa8778, 2397 .hwcg_bit = 1, 2398 .clkr = { 2399 .enable_reg = 0x52018, 2400 .enable_mask = BIT(21), 2401 .hw.init = &(const struct clk_init_data) { 2402 .name = "gcc_qupv3_wrap3_ibi_ctrl_2_clk", 2403 .parent_hws = (const struct clk_hw*[]) { 2404 &gcc_qupv3_wrap3_ibi_ctrl_0_clk_src.clkr.hw, 2405 }, 2406 .num_parents = 1, 2407 .flags = CLK_SET_RATE_PARENT, 2408 .ops = &clk_branch2_ops, 2409 }, 2410 }, 2411 }; 2412 2413 static struct clk_branch gcc_qupv3_wrap3_s0_clk = { 2414 .halt_reg = 0xa8004, 2415 .halt_check = BRANCH_HALT_VOTED, 2416 .clkr = { 2417 .enable_reg = 0x52018, 2418 .enable_mask = BIT(12), 2419 .hw.init = &(const struct clk_init_data) { 2420 .name = "gcc_qupv3_wrap3_s0_clk", 2421 .parent_hws = (const struct clk_hw*[]) { 2422 &gcc_qupv3_wrap3_s0_clk_src.clkr.hw, 2423 }, 2424 .num_parents = 1, 2425 .flags = CLK_SET_RATE_PARENT, 2426 .ops = &clk_branch2_ops, 2427 }, 2428 }, 2429 }; 2430 2431 static struct clk_branch gcc_qupv3_wrap3_s1_clk = { 2432 .halt_reg = 0xa8140, 2433 .halt_check = BRANCH_HALT_VOTED, 2434 .clkr = { 2435 .enable_reg = 0x52018, 2436 .enable_mask = BIT(13), 2437 .hw.init = &(const struct clk_init_data) { 2438 .name = "gcc_qupv3_wrap3_s1_clk", 2439 .parent_hws = (const struct clk_hw*[]) { 2440 &gcc_qupv3_wrap3_s1_clk_src.clkr.hw, 2441 }, 2442 .num_parents = 1, 2443 .flags = CLK_SET_RATE_PARENT, 2444 .ops = &clk_branch2_ops, 2445 }, 2446 }, 2447 }; 2448 2449 static struct clk_branch gcc_qupv3_wrap3_s2_clk = { 2450 .halt_reg = 0xa827c, 2451 .halt_check = BRANCH_HALT_VOTED, 2452 .clkr = { 2453 .enable_reg = 0x52018, 2454 .enable_mask = BIT(14), 2455 .hw.init = &(const struct clk_init_data) { 2456 .name = "gcc_qupv3_wrap3_s2_clk", 2457 .parent_hws = (const struct clk_hw*[]) { 2458 &gcc_qupv3_wrap3_s2_clk_src.clkr.hw, 2459 }, 2460 .num_parents = 1, 2461 .flags = CLK_SET_RATE_PARENT, 2462 .ops = &clk_branch2_ops, 2463 }, 2464 }, 2465 }; 2466 2467 static struct clk_branch gcc_qupv3_wrap3_s3_clk = { 2468 .halt_reg = 0xa83b8, 2469 .halt_check = BRANCH_HALT_VOTED, 2470 .clkr = { 2471 .enable_reg = 0x52018, 2472 .enable_mask = BIT(15), 2473 .hw.init = &(const struct clk_init_data) { 2474 .name = "gcc_qupv3_wrap3_s3_clk", 2475 .parent_hws = (const struct clk_hw*[]) { 2476 &gcc_qupv3_wrap3_s3_clk_src.clkr.hw, 2477 }, 2478 .num_parents = 1, 2479 .flags = CLK_SET_RATE_PARENT, 2480 .ops = &clk_branch2_ops, 2481 }, 2482 }, 2483 }; 2484 2485 static struct clk_branch gcc_qupv3_wrap3_s4_clk = { 2486 .halt_reg = 0xa84f4, 2487 .halt_check = BRANCH_HALT_VOTED, 2488 .clkr = { 2489 .enable_reg = 0x52018, 2490 .enable_mask = BIT(16), 2491 .hw.init = &(const struct clk_init_data) { 2492 .name = "gcc_qupv3_wrap3_s4_clk", 2493 .parent_hws = (const struct clk_hw*[]) { 2494 &gcc_qupv3_wrap3_s4_clk_src.clkr.hw, 2495 }, 2496 .num_parents = 1, 2497 .flags = CLK_SET_RATE_PARENT, 2498 .ops = &clk_branch2_ops, 2499 }, 2500 }, 2501 }; 2502 2503 static struct clk_branch gcc_qupv3_wrap3_s5_clk = { 2504 .halt_reg = 0xa8630, 2505 .halt_check = BRANCH_HALT_VOTED, 2506 .clkr = { 2507 .enable_reg = 0x52018, 2508 .enable_mask = BIT(17), 2509 .hw.init = &(const struct clk_init_data) { 2510 .name = "gcc_qupv3_wrap3_s5_clk", 2511 .parent_hws = (const struct clk_hw*[]) { 2512 &gcc_qupv3_wrap3_s5_clk_src.clkr.hw, 2513 }, 2514 .num_parents = 1, 2515 .flags = CLK_SET_RATE_PARENT, 2516 .ops = &clk_branch2_ops, 2517 }, 2518 }, 2519 }; 2520 2521 static struct clk_branch gcc_qupv3_wrap4_core_2x_clk = { 2522 .halt_reg = 0x23564, 2523 .halt_check = BRANCH_HALT_VOTED, 2524 .clkr = { 2525 .enable_reg = 0x52018, 2526 .enable_mask = BIT(25), 2527 .hw.init = &(const struct clk_init_data) { 2528 .name = "gcc_qupv3_wrap4_core_2x_clk", 2529 .ops = &clk_branch2_ops, 2530 }, 2531 }, 2532 }; 2533 2534 static struct clk_branch gcc_qupv3_wrap4_core_clk = { 2535 .halt_reg = 0x23550, 2536 .halt_check = BRANCH_HALT_VOTED, 2537 .clkr = { 2538 .enable_reg = 0x52018, 2539 .enable_mask = BIT(24), 2540 .hw.init = &(const struct clk_init_data) { 2541 .name = "gcc_qupv3_wrap4_core_clk", 2542 .ops = &clk_branch2_ops, 2543 }, 2544 }, 2545 }; 2546 2547 static struct clk_branch gcc_qupv3_wrap4_s0_clk = { 2548 .halt_reg = 0xa9004, 2549 .halt_check = BRANCH_HALT_VOTED, 2550 .clkr = { 2551 .enable_reg = 0x52018, 2552 .enable_mask = BIT(26), 2553 .hw.init = &(const struct clk_init_data) { 2554 .name = "gcc_qupv3_wrap4_s0_clk", 2555 .parent_hws = (const struct clk_hw*[]) { 2556 &gcc_qupv3_wrap4_s0_clk_src.clkr.hw, 2557 }, 2558 .num_parents = 1, 2559 .flags = CLK_SET_RATE_PARENT, 2560 .ops = &clk_branch2_ops, 2561 }, 2562 }, 2563 }; 2564 2565 static struct clk_branch gcc_qupv3_wrap4_s1_clk = { 2566 .halt_reg = 0xa9140, 2567 .halt_check = BRANCH_HALT_VOTED, 2568 .clkr = { 2569 .enable_reg = 0x52018, 2570 .enable_mask = BIT(27), 2571 .hw.init = &(const struct clk_init_data) { 2572 .name = "gcc_qupv3_wrap4_s1_clk", 2573 .parent_hws = (const struct clk_hw*[]) { 2574 &gcc_qupv3_wrap4_s1_clk_src.clkr.hw, 2575 }, 2576 .num_parents = 1, 2577 .flags = CLK_SET_RATE_PARENT, 2578 .ops = &clk_branch2_ops, 2579 }, 2580 }, 2581 }; 2582 2583 static struct clk_branch gcc_qupv3_wrap4_s2_clk = { 2584 .halt_reg = 0xa927c, 2585 .halt_check = BRANCH_HALT_VOTED, 2586 .clkr = { 2587 .enable_reg = 0x52018, 2588 .enable_mask = BIT(28), 2589 .hw.init = &(const struct clk_init_data) { 2590 .name = "gcc_qupv3_wrap4_s2_clk", 2591 .parent_hws = (const struct clk_hw*[]) { 2592 &gcc_qupv3_wrap4_s2_clk_src.clkr.hw, 2593 }, 2594 .num_parents = 1, 2595 .flags = CLK_SET_RATE_PARENT, 2596 .ops = &clk_branch2_ops, 2597 }, 2598 }, 2599 }; 2600 2601 static struct clk_branch gcc_qupv3_wrap4_s3_clk = { 2602 .halt_reg = 0xa93b8, 2603 .halt_check = BRANCH_HALT_VOTED, 2604 .clkr = { 2605 .enable_reg = 0x52018, 2606 .enable_mask = BIT(29), 2607 .hw.init = &(const struct clk_init_data) { 2608 .name = "gcc_qupv3_wrap4_s3_clk", 2609 .parent_hws = (const struct clk_hw*[]) { 2610 &gcc_qupv3_wrap4_s3_clk_src.clkr.hw, 2611 }, 2612 .num_parents = 1, 2613 .flags = CLK_SET_RATE_PARENT, 2614 .ops = &clk_branch2_ops, 2615 }, 2616 }, 2617 }; 2618 2619 static struct clk_branch gcc_qupv3_wrap4_s4_clk = { 2620 .halt_reg = 0xa94f4, 2621 .halt_check = BRANCH_HALT_VOTED, 2622 .clkr = { 2623 .enable_reg = 0x52018, 2624 .enable_mask = BIT(30), 2625 .hw.init = &(const struct clk_init_data) { 2626 .name = "gcc_qupv3_wrap4_s4_clk", 2627 .parent_hws = (const struct clk_hw*[]) { 2628 &gcc_qupv3_wrap4_s4_clk_src.clkr.hw, 2629 }, 2630 .num_parents = 1, 2631 .flags = CLK_SET_RATE_PARENT, 2632 .ops = &clk_branch2_ops, 2633 }, 2634 }, 2635 }; 2636 2637 static struct clk_branch gcc_qupv3_wrap_1_m_axi_clk = { 2638 .halt_reg = 0x23140, 2639 .halt_check = BRANCH_HALT_VOTED, 2640 .hwcg_reg = 0x23140, 2641 .hwcg_bit = 1, 2642 .clkr = { 2643 .enable_reg = 0x52008, 2644 .enable_mask = BIT(20), 2645 .hw.init = &(const struct clk_init_data) { 2646 .name = "gcc_qupv3_wrap_1_m_axi_clk", 2647 .ops = &clk_branch2_ops, 2648 }, 2649 }, 2650 }; 2651 2652 static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = { 2653 .halt_reg = 0x23144, 2654 .halt_check = BRANCH_HALT_VOTED, 2655 .hwcg_reg = 0x23144, 2656 .hwcg_bit = 1, 2657 .clkr = { 2658 .enable_reg = 0x52008, 2659 .enable_mask = BIT(21), 2660 .hw.init = &(const struct clk_init_data) { 2661 .name = "gcc_qupv3_wrap_1_s_ahb_clk", 2662 .ops = &clk_branch2_ops, 2663 }, 2664 }, 2665 }; 2666 2667 static struct clk_branch gcc_qupv3_wrap_2_m_ahb_clk = { 2668 .halt_reg = 0x23298, 2669 .halt_check = BRANCH_HALT_VOTED, 2670 .hwcg_reg = 0x23298, 2671 .hwcg_bit = 1, 2672 .clkr = { 2673 .enable_reg = 0x52010, 2674 .enable_mask = BIT(2), 2675 .hw.init = &(const struct clk_init_data) { 2676 .name = "gcc_qupv3_wrap_2_m_ahb_clk", 2677 .ops = &clk_branch2_ops, 2678 }, 2679 }, 2680 }; 2681 2682 static struct clk_branch gcc_qupv3_wrap_2_s_ahb_clk = { 2683 .halt_reg = 0x2329c, 2684 .halt_check = BRANCH_HALT_VOTED, 2685 .hwcg_reg = 0x2329c, 2686 .hwcg_bit = 1, 2687 .clkr = { 2688 .enable_reg = 0x52010, 2689 .enable_mask = BIT(1), 2690 .hw.init = &(const struct clk_init_data) { 2691 .name = "gcc_qupv3_wrap_2_s_ahb_clk", 2692 .ops = &clk_branch2_ops, 2693 }, 2694 }, 2695 }; 2696 2697 static struct clk_branch gcc_qupv3_wrap_3_ibi_1_ahb_clk = { 2698 .halt_reg = 0xa876c, 2699 .halt_check = BRANCH_HALT_VOTED, 2700 .hwcg_reg = 0xa876c, 2701 .hwcg_bit = 1, 2702 .clkr = { 2703 .enable_reg = 0x52018, 2704 .enable_mask = BIT(18), 2705 .hw.init = &(const struct clk_init_data) { 2706 .name = "gcc_qupv3_wrap_3_ibi_1_ahb_clk", 2707 .ops = &clk_branch2_ops, 2708 }, 2709 }, 2710 }; 2711 2712 static struct clk_branch gcc_qupv3_wrap_3_ibi_2_ahb_clk = { 2713 .halt_reg = 0xa8770, 2714 .halt_check = BRANCH_HALT_VOTED, 2715 .hwcg_reg = 0xa8770, 2716 .hwcg_bit = 1, 2717 .clkr = { 2718 .enable_reg = 0x52018, 2719 .enable_mask = BIT(19), 2720 .hw.init = &(const struct clk_init_data) { 2721 .name = "gcc_qupv3_wrap_3_ibi_2_ahb_clk", 2722 .ops = &clk_branch2_ops, 2723 }, 2724 }, 2725 }; 2726 2727 static struct clk_branch gcc_qupv3_wrap_3_m_ahb_clk = { 2728 .halt_reg = 0x233f0, 2729 .halt_check = BRANCH_HALT_VOTED, 2730 .hwcg_reg = 0x233f0, 2731 .hwcg_bit = 1, 2732 .clkr = { 2733 .enable_reg = 0x52018, 2734 .enable_mask = BIT(8), 2735 .hw.init = &(const struct clk_init_data) { 2736 .name = "gcc_qupv3_wrap_3_m_ahb_clk", 2737 .ops = &clk_branch2_ops, 2738 }, 2739 }, 2740 }; 2741 2742 static struct clk_branch gcc_qupv3_wrap_3_s_ahb_clk = { 2743 .halt_reg = 0x233f4, 2744 .halt_check = BRANCH_HALT_VOTED, 2745 .hwcg_reg = 0x233f4, 2746 .hwcg_bit = 1, 2747 .clkr = { 2748 .enable_reg = 0x52018, 2749 .enable_mask = BIT(9), 2750 .hw.init = &(const struct clk_init_data) { 2751 .name = "gcc_qupv3_wrap_3_s_ahb_clk", 2752 .ops = &clk_branch2_ops, 2753 }, 2754 }, 2755 }; 2756 2757 static struct clk_branch gcc_qupv3_wrap_4_m_ahb_clk = { 2758 .halt_reg = 0x23548, 2759 .halt_check = BRANCH_HALT_VOTED, 2760 .hwcg_reg = 0x23548, 2761 .hwcg_bit = 1, 2762 .clkr = { 2763 .enable_reg = 0x52018, 2764 .enable_mask = BIT(22), 2765 .hw.init = &(const struct clk_init_data) { 2766 .name = "gcc_qupv3_wrap_4_m_ahb_clk", 2767 .ops = &clk_branch2_ops, 2768 }, 2769 }, 2770 }; 2771 2772 static struct clk_branch gcc_qupv3_wrap_4_s_ahb_clk = { 2773 .halt_reg = 0x2354c, 2774 .halt_check = BRANCH_HALT_VOTED, 2775 .hwcg_reg = 0x2354c, 2776 .hwcg_bit = 1, 2777 .clkr = { 2778 .enable_reg = 0x52018, 2779 .enable_mask = BIT(23), 2780 .hw.init = &(const struct clk_init_data) { 2781 .name = "gcc_qupv3_wrap_4_s_ahb_clk", 2782 .ops = &clk_branch2_ops, 2783 }, 2784 }, 2785 }; 2786 2787 static struct clk_branch gcc_sdcc2_ahb_clk = { 2788 .halt_reg = 0x14014, 2789 .halt_check = BRANCH_HALT, 2790 .clkr = { 2791 .enable_reg = 0x14014, 2792 .enable_mask = BIT(0), 2793 .hw.init = &(const struct clk_init_data) { 2794 .name = "gcc_sdcc2_ahb_clk", 2795 .ops = &clk_branch2_ops, 2796 }, 2797 }, 2798 }; 2799 2800 static struct clk_branch gcc_sdcc2_apps_clk = { 2801 .halt_reg = 0x14004, 2802 .halt_check = BRANCH_HALT, 2803 .clkr = { 2804 .enable_reg = 0x14004, 2805 .enable_mask = BIT(0), 2806 .hw.init = &(const struct clk_init_data) { 2807 .name = "gcc_sdcc2_apps_clk", 2808 .parent_hws = (const struct clk_hw*[]) { 2809 &gcc_sdcc2_apps_clk_src.clkr.hw, 2810 }, 2811 .num_parents = 1, 2812 .flags = CLK_SET_RATE_PARENT, 2813 .ops = &clk_branch2_ops, 2814 }, 2815 }, 2816 }; 2817 2818 static struct clk_branch gcc_sdcc4_ahb_clk = { 2819 .halt_reg = 0x16014, 2820 .halt_check = BRANCH_HALT, 2821 .clkr = { 2822 .enable_reg = 0x16014, 2823 .enable_mask = BIT(0), 2824 .hw.init = &(const struct clk_init_data) { 2825 .name = "gcc_sdcc4_ahb_clk", 2826 .ops = &clk_branch2_ops, 2827 }, 2828 }, 2829 }; 2830 2831 static struct clk_branch gcc_sdcc4_apps_clk = { 2832 .halt_reg = 0x16004, 2833 .halt_check = BRANCH_HALT, 2834 .clkr = { 2835 .enable_reg = 0x16004, 2836 .enable_mask = BIT(0), 2837 .hw.init = &(const struct clk_init_data) { 2838 .name = "gcc_sdcc4_apps_clk", 2839 .parent_hws = (const struct clk_hw*[]) { 2840 &gcc_sdcc4_apps_clk_src.clkr.hw, 2841 }, 2842 .num_parents = 1, 2843 .flags = CLK_SET_RATE_PARENT, 2844 .ops = &clk_branch2_ops, 2845 }, 2846 }, 2847 }; 2848 2849 static struct clk_branch gcc_ufs_phy_ahb_clk = { 2850 .halt_reg = 0x77028, 2851 .halt_check = BRANCH_HALT_VOTED, 2852 .hwcg_reg = 0x77028, 2853 .hwcg_bit = 1, 2854 .clkr = { 2855 .enable_reg = 0x77028, 2856 .enable_mask = BIT(0), 2857 .hw.init = &(const struct clk_init_data) { 2858 .name = "gcc_ufs_phy_ahb_clk", 2859 .ops = &clk_branch2_ops, 2860 }, 2861 }, 2862 }; 2863 2864 static struct clk_branch gcc_ufs_phy_axi_clk = { 2865 .halt_reg = 0x77018, 2866 .halt_check = BRANCH_HALT_VOTED, 2867 .hwcg_reg = 0x77018, 2868 .hwcg_bit = 1, 2869 .clkr = { 2870 .enable_reg = 0x77018, 2871 .enable_mask = BIT(0), 2872 .hw.init = &(const struct clk_init_data) { 2873 .name = "gcc_ufs_phy_axi_clk", 2874 .parent_hws = (const struct clk_hw*[]) { 2875 &gcc_ufs_phy_axi_clk_src.clkr.hw, 2876 }, 2877 .num_parents = 1, 2878 .flags = CLK_SET_RATE_PARENT, 2879 .ops = &clk_branch2_ops, 2880 }, 2881 }, 2882 }; 2883 2884 static struct clk_branch gcc_ufs_phy_ice_core_clk = { 2885 .halt_reg = 0x7707c, 2886 .halt_check = BRANCH_HALT_VOTED, 2887 .hwcg_reg = 0x7707c, 2888 .hwcg_bit = 1, 2889 .clkr = { 2890 .enable_reg = 0x7707c, 2891 .enable_mask = BIT(0), 2892 .hw.init = &(const struct clk_init_data) { 2893 .name = "gcc_ufs_phy_ice_core_clk", 2894 .parent_hws = (const struct clk_hw*[]) { 2895 &gcc_ufs_phy_ice_core_clk_src.clkr.hw, 2896 }, 2897 .num_parents = 1, 2898 .flags = CLK_SET_RATE_PARENT, 2899 .ops = &clk_branch2_ops, 2900 }, 2901 }, 2902 }; 2903 2904 static struct clk_branch gcc_ufs_phy_phy_aux_clk = { 2905 .halt_reg = 0x770bc, 2906 .halt_check = BRANCH_HALT_VOTED, 2907 .hwcg_reg = 0x770bc, 2908 .hwcg_bit = 1, 2909 .clkr = { 2910 .enable_reg = 0x770bc, 2911 .enable_mask = BIT(0), 2912 .hw.init = &(const struct clk_init_data) { 2913 .name = "gcc_ufs_phy_phy_aux_clk", 2914 .parent_hws = (const struct clk_hw*[]) { 2915 &gcc_ufs_phy_phy_aux_clk_src.clkr.hw, 2916 }, 2917 .num_parents = 1, 2918 .flags = CLK_SET_RATE_PARENT, 2919 .ops = &clk_branch2_ops, 2920 }, 2921 }, 2922 }; 2923 2924 static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = { 2925 .halt_reg = 0x77030, 2926 .halt_check = BRANCH_HALT_DELAY, 2927 .clkr = { 2928 .enable_reg = 0x77030, 2929 .enable_mask = BIT(0), 2930 .hw.init = &(const struct clk_init_data) { 2931 .name = "gcc_ufs_phy_rx_symbol_0_clk", 2932 .parent_hws = (const struct clk_hw*[]) { 2933 &gcc_ufs_phy_rx_symbol_0_clk_src.clkr.hw, 2934 }, 2935 .num_parents = 1, 2936 .flags = CLK_SET_RATE_PARENT, 2937 .ops = &clk_branch2_ops, 2938 }, 2939 }, 2940 }; 2941 2942 static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = { 2943 .halt_reg = 0x770d8, 2944 .halt_check = BRANCH_HALT_DELAY, 2945 .clkr = { 2946 .enable_reg = 0x770d8, 2947 .enable_mask = BIT(0), 2948 .hw.init = &(const struct clk_init_data) { 2949 .name = "gcc_ufs_phy_rx_symbol_1_clk", 2950 .parent_hws = (const struct clk_hw*[]) { 2951 &gcc_ufs_phy_rx_symbol_1_clk_src.clkr.hw, 2952 }, 2953 .num_parents = 1, 2954 .flags = CLK_SET_RATE_PARENT, 2955 .ops = &clk_branch2_ops, 2956 }, 2957 }, 2958 }; 2959 2960 static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = { 2961 .halt_reg = 0x7702c, 2962 .halt_check = BRANCH_HALT_DELAY, 2963 .clkr = { 2964 .enable_reg = 0x7702c, 2965 .enable_mask = BIT(0), 2966 .hw.init = &(const struct clk_init_data) { 2967 .name = "gcc_ufs_phy_tx_symbol_0_clk", 2968 .parent_hws = (const struct clk_hw*[]) { 2969 &gcc_ufs_phy_tx_symbol_0_clk_src.clkr.hw, 2970 }, 2971 .num_parents = 1, 2972 .flags = CLK_SET_RATE_PARENT, 2973 .ops = &clk_branch2_ops, 2974 }, 2975 }, 2976 }; 2977 2978 static struct clk_branch gcc_ufs_phy_unipro_core_clk = { 2979 .halt_reg = 0x7706c, 2980 .halt_check = BRANCH_HALT_VOTED, 2981 .hwcg_reg = 0x7706c, 2982 .hwcg_bit = 1, 2983 .clkr = { 2984 .enable_reg = 0x7706c, 2985 .enable_mask = BIT(0), 2986 .hw.init = &(const struct clk_init_data) { 2987 .name = "gcc_ufs_phy_unipro_core_clk", 2988 .parent_hws = (const struct clk_hw*[]) { 2989 &gcc_ufs_phy_unipro_core_clk_src.clkr.hw, 2990 }, 2991 .num_parents = 1, 2992 .flags = CLK_SET_RATE_PARENT, 2993 .ops = &clk_branch2_ops, 2994 }, 2995 }, 2996 }; 2997 2998 static struct clk_branch gcc_usb30_prim_master_clk = { 2999 .halt_reg = 0x39018, 3000 .halt_check = BRANCH_HALT, 3001 .clkr = { 3002 .enable_reg = 0x39018, 3003 .enable_mask = BIT(0), 3004 .hw.init = &(const struct clk_init_data) { 3005 .name = "gcc_usb30_prim_master_clk", 3006 .parent_hws = (const struct clk_hw*[]) { 3007 &gcc_usb30_prim_master_clk_src.clkr.hw, 3008 }, 3009 .num_parents = 1, 3010 .flags = CLK_SET_RATE_PARENT, 3011 .ops = &clk_branch2_ops, 3012 }, 3013 }, 3014 }; 3015 3016 static struct clk_branch gcc_usb30_prim_mock_utmi_clk = { 3017 .halt_reg = 0x3902c, 3018 .halt_check = BRANCH_HALT, 3019 .clkr = { 3020 .enable_reg = 0x3902c, 3021 .enable_mask = BIT(0), 3022 .hw.init = &(const struct clk_init_data) { 3023 .name = "gcc_usb30_prim_mock_utmi_clk", 3024 .parent_hws = (const struct clk_hw*[]) { 3025 &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr.hw, 3026 }, 3027 .num_parents = 1, 3028 .flags = CLK_SET_RATE_PARENT, 3029 .ops = &clk_branch2_ops, 3030 }, 3031 }, 3032 }; 3033 3034 static struct clk_branch gcc_usb30_prim_sleep_clk = { 3035 .halt_reg = 0x39028, 3036 .halt_check = BRANCH_HALT, 3037 .clkr = { 3038 .enable_reg = 0x39028, 3039 .enable_mask = BIT(0), 3040 .hw.init = &(const struct clk_init_data) { 3041 .name = "gcc_usb30_prim_sleep_clk", 3042 .ops = &clk_branch2_ops, 3043 }, 3044 }, 3045 }; 3046 3047 static struct clk_branch gcc_usb3_prim_phy_aux_clk = { 3048 .halt_reg = 0x39068, 3049 .halt_check = BRANCH_HALT, 3050 .clkr = { 3051 .enable_reg = 0x39068, 3052 .enable_mask = BIT(0), 3053 .hw.init = &(const struct clk_init_data) { 3054 .name = "gcc_usb3_prim_phy_aux_clk", 3055 .parent_hws = (const struct clk_hw*[]) { 3056 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, 3057 }, 3058 .num_parents = 1, 3059 .flags = CLK_SET_RATE_PARENT, 3060 .ops = &clk_branch2_ops, 3061 }, 3062 }, 3063 }; 3064 3065 static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = { 3066 .halt_reg = 0x3906c, 3067 .halt_check = BRANCH_HALT, 3068 .clkr = { 3069 .enable_reg = 0x3906c, 3070 .enable_mask = BIT(0), 3071 .hw.init = &(const struct clk_init_data) { 3072 .name = "gcc_usb3_prim_phy_com_aux_clk", 3073 .parent_hws = (const struct clk_hw*[]) { 3074 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, 3075 }, 3076 .num_parents = 1, 3077 .flags = CLK_SET_RATE_PARENT, 3078 .ops = &clk_branch2_ops, 3079 }, 3080 }, 3081 }; 3082 3083 static struct clk_branch gcc_usb3_prim_phy_pipe_clk = { 3084 .halt_reg = 0x39070, 3085 .halt_check = BRANCH_HALT_DELAY, 3086 .hwcg_reg = 0x39070, 3087 .hwcg_bit = 1, 3088 .clkr = { 3089 .enable_reg = 0x39070, 3090 .enable_mask = BIT(0), 3091 .hw.init = &(const struct clk_init_data) { 3092 .name = "gcc_usb3_prim_phy_pipe_clk", 3093 .parent_hws = (const struct clk_hw*[]) { 3094 &gcc_usb3_prim_phy_pipe_clk_src.clkr.hw, 3095 }, 3096 .num_parents = 1, 3097 .flags = CLK_SET_RATE_PARENT, 3098 .ops = &clk_branch2_ops, 3099 }, 3100 }, 3101 }; 3102 3103 static struct clk_branch gcc_video_axi0_clk = { 3104 .halt_reg = 0x32018, 3105 .halt_check = BRANCH_HALT_SKIP, 3106 .hwcg_reg = 0x32018, 3107 .hwcg_bit = 1, 3108 .clkr = { 3109 .enable_reg = 0x32018, 3110 .enable_mask = BIT(0), 3111 .hw.init = &(const struct clk_init_data) { 3112 .name = "gcc_video_axi0_clk", 3113 .ops = &clk_branch2_ops, 3114 }, 3115 }, 3116 }; 3117 3118 static struct clk_branch gcc_video_axi1_clk = { 3119 .halt_reg = 0x3202c, 3120 .halt_check = BRANCH_HALT_SKIP, 3121 .hwcg_reg = 0x3202c, 3122 .hwcg_bit = 1, 3123 .clkr = { 3124 .enable_reg = 0x3202c, 3125 .enable_mask = BIT(0), 3126 .hw.init = &(const struct clk_init_data) { 3127 .name = "gcc_video_axi1_clk", 3128 .ops = &clk_branch2_ops, 3129 }, 3130 }, 3131 }; 3132 3133 static struct gdsc gcc_pcie_0_gdsc = { 3134 .gdscr = 0x6b004, 3135 .en_rest_wait_val = 0x2, 3136 .en_few_wait_val = 0x2, 3137 .clk_dis_wait_val = 0xf, 3138 .collapse_ctrl = 0x5214c, 3139 .collapse_mask = BIT(0), 3140 .pd = { 3141 .name = "gcc_pcie_0_gdsc", 3142 }, 3143 .pwrsts = PWRSTS_OFF_ON, 3144 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, 3145 }; 3146 3147 static struct gdsc gcc_pcie_0_phy_gdsc = { 3148 .gdscr = 0x6c000, 3149 .en_rest_wait_val = 0x2, 3150 .en_few_wait_val = 0x2, 3151 .clk_dis_wait_val = 0x2, 3152 .collapse_ctrl = 0x5214c, 3153 .collapse_mask = BIT(2), 3154 .pd = { 3155 .name = "gcc_pcie_0_phy_gdsc", 3156 }, 3157 .pwrsts = PWRSTS_OFF_ON, 3158 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, 3159 }; 3160 3161 static struct gdsc gcc_ufs_mem_phy_gdsc = { 3162 .gdscr = 0x9e000, 3163 .en_rest_wait_val = 0x2, 3164 .en_few_wait_val = 0x2, 3165 .clk_dis_wait_val = 0x2, 3166 .pd = { 3167 .name = "gcc_ufs_mem_phy_gdsc", 3168 }, 3169 .pwrsts = PWRSTS_OFF_ON, 3170 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 3171 }; 3172 3173 static struct gdsc gcc_ufs_phy_gdsc = { 3174 .gdscr = 0x77004, 3175 .en_rest_wait_val = 0x2, 3176 .en_few_wait_val = 0x2, 3177 .clk_dis_wait_val = 0xf, 3178 .pd = { 3179 .name = "gcc_ufs_phy_gdsc", 3180 }, 3181 .pwrsts = PWRSTS_OFF_ON, 3182 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 3183 }; 3184 3185 static struct gdsc gcc_usb30_prim_gdsc = { 3186 .gdscr = 0x39004, 3187 .en_rest_wait_val = 0x2, 3188 .en_few_wait_val = 0x2, 3189 .clk_dis_wait_val = 0xf, 3190 .pd = { 3191 .name = "gcc_usb30_prim_gdsc", 3192 }, 3193 .pwrsts = PWRSTS_OFF_ON, 3194 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 3195 }; 3196 3197 static struct gdsc gcc_usb3_phy_gdsc = { 3198 .gdscr = 0x50018, 3199 .en_rest_wait_val = 0x2, 3200 .en_few_wait_val = 0x2, 3201 .clk_dis_wait_val = 0x2, 3202 .pd = { 3203 .name = "gcc_usb3_phy_gdsc", 3204 }, 3205 .pwrsts = PWRSTS_OFF_ON, 3206 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 3207 }; 3208 3209 static struct clk_regmap *gcc_kaanapali_clocks[] = { 3210 [GCC_AGGRE_NOC_PCIE_AXI_CLK] = &gcc_aggre_noc_pcie_axi_clk.clkr, 3211 [GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr, 3212 [GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr, 3213 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, 3214 [GCC_CAMERA_HF_AXI_CLK] = &gcc_camera_hf_axi_clk.clkr, 3215 [GCC_CAMERA_SF_AXI_CLK] = &gcc_camera_sf_axi_clk.clkr, 3216 [GCC_CFG_NOC_PCIE_ANOC_AHB_CLK] = &gcc_cfg_noc_pcie_anoc_ahb_clk.clkr, 3217 [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr, 3218 [GCC_CNOC_PCIE_SF_AXI_CLK] = &gcc_cnoc_pcie_sf_axi_clk.clkr, 3219 [GCC_DDRSS_PCIE_SF_QTB_CLK] = &gcc_ddrss_pcie_sf_qtb_clk.clkr, 3220 [GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr, 3221 [GCC_DISP_SF_AXI_CLK] = &gcc_disp_sf_axi_clk.clkr, 3222 [GCC_EVA_AXI0_CLK] = &gcc_eva_axi0_clk.clkr, 3223 [GCC_EVA_AXI0C_CLK] = &gcc_eva_axi0c_clk.clkr, 3224 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, 3225 [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr, 3226 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, 3227 [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr, 3228 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, 3229 [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr, 3230 [GCC_GPLL0] = &gcc_gpll0.clkr, 3231 [GCC_GPLL0_OUT_EVEN] = &gcc_gpll0_out_even.clkr, 3232 [GCC_GPLL1] = &gcc_gpll1.clkr, 3233 [GCC_GPLL4] = &gcc_gpll4.clkr, 3234 [GCC_GPLL7] = &gcc_gpll7.clkr, 3235 [GCC_GPLL9] = &gcc_gpll9.clkr, 3236 [GCC_GPU_GEMNOC_GFX_CLK] = &gcc_gpu_gemnoc_gfx_clk.clkr, 3237 [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr, 3238 [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr, 3239 [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr, 3240 [GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr, 3241 [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr, 3242 [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr, 3243 [GCC_PCIE_0_PHY_AUX_CLK] = &gcc_pcie_0_phy_aux_clk.clkr, 3244 [GCC_PCIE_0_PHY_AUX_CLK_SRC] = &gcc_pcie_0_phy_aux_clk_src.clkr, 3245 [GCC_PCIE_0_PHY_RCHNG_CLK] = &gcc_pcie_0_phy_rchng_clk.clkr, 3246 [GCC_PCIE_0_PHY_RCHNG_CLK_SRC] = &gcc_pcie_0_phy_rchng_clk_src.clkr, 3247 [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr, 3248 [GCC_PCIE_0_PIPE_CLK_SRC] = &gcc_pcie_0_pipe_clk_src.clkr, 3249 [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr, 3250 [GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr, 3251 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, 3252 [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr, 3253 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, 3254 [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr, 3255 [GCC_QUPV3_I2C_CORE_CLK] = &gcc_qupv3_i2c_core_clk.clkr, 3256 [GCC_QUPV3_I2C_S0_CLK] = &gcc_qupv3_i2c_s0_clk.clkr, 3257 [GCC_QUPV3_I2C_S0_CLK_SRC] = &gcc_qupv3_i2c_s0_clk_src.clkr, 3258 [GCC_QUPV3_I2C_S1_CLK] = &gcc_qupv3_i2c_s1_clk.clkr, 3259 [GCC_QUPV3_I2C_S1_CLK_SRC] = &gcc_qupv3_i2c_s1_clk_src.clkr, 3260 [GCC_QUPV3_I2C_S2_CLK] = &gcc_qupv3_i2c_s2_clk.clkr, 3261 [GCC_QUPV3_I2C_S2_CLK_SRC] = &gcc_qupv3_i2c_s2_clk_src.clkr, 3262 [GCC_QUPV3_I2C_S3_CLK] = &gcc_qupv3_i2c_s3_clk.clkr, 3263 [GCC_QUPV3_I2C_S3_CLK_SRC] = &gcc_qupv3_i2c_s3_clk_src.clkr, 3264 [GCC_QUPV3_I2C_S4_CLK] = &gcc_qupv3_i2c_s4_clk.clkr, 3265 [GCC_QUPV3_I2C_S4_CLK_SRC] = &gcc_qupv3_i2c_s4_clk_src.clkr, 3266 [GCC_QUPV3_I2C_S_AHB_CLK] = &gcc_qupv3_i2c_s_ahb_clk.clkr, 3267 [GCC_QUPV3_WRAP1_CORE_2X_CLK] = &gcc_qupv3_wrap1_core_2x_clk.clkr, 3268 [GCC_QUPV3_WRAP1_CORE_CLK] = &gcc_qupv3_wrap1_core_clk.clkr, 3269 [GCC_QUPV3_WRAP1_QSPI_REF_CLK] = &gcc_qupv3_wrap1_qspi_ref_clk.clkr, 3270 [GCC_QUPV3_WRAP1_QSPI_REF_CLK_SRC] = &gcc_qupv3_wrap1_qspi_ref_clk_src.clkr, 3271 [GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr, 3272 [GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr, 3273 [GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr, 3274 [GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr, 3275 [GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr, 3276 [GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr, 3277 [GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr, 3278 [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr, 3279 [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr, 3280 [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr, 3281 [GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr, 3282 [GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr, 3283 [GCC_QUPV3_WRAP1_S6_CLK] = &gcc_qupv3_wrap1_s6_clk.clkr, 3284 [GCC_QUPV3_WRAP1_S6_CLK_SRC] = &gcc_qupv3_wrap1_s6_clk_src.clkr, 3285 [GCC_QUPV3_WRAP1_S7_CLK] = &gcc_qupv3_wrap1_s7_clk.clkr, 3286 [GCC_QUPV3_WRAP1_S7_CLK_SRC] = &gcc_qupv3_wrap1_s7_clk_src.clkr, 3287 [GCC_QUPV3_WRAP2_CORE_2X_CLK] = &gcc_qupv3_wrap2_core_2x_clk.clkr, 3288 [GCC_QUPV3_WRAP2_CORE_CLK] = &gcc_qupv3_wrap2_core_clk.clkr, 3289 [GCC_QUPV3_WRAP2_S0_CLK] = &gcc_qupv3_wrap2_s0_clk.clkr, 3290 [GCC_QUPV3_WRAP2_S0_CLK_SRC] = &gcc_qupv3_wrap2_s0_clk_src.clkr, 3291 [GCC_QUPV3_WRAP2_S1_CLK] = &gcc_qupv3_wrap2_s1_clk.clkr, 3292 [GCC_QUPV3_WRAP2_S1_CLK_SRC] = &gcc_qupv3_wrap2_s1_clk_src.clkr, 3293 [GCC_QUPV3_WRAP2_S2_CLK] = &gcc_qupv3_wrap2_s2_clk.clkr, 3294 [GCC_QUPV3_WRAP2_S2_CLK_SRC] = &gcc_qupv3_wrap2_s2_clk_src.clkr, 3295 [GCC_QUPV3_WRAP2_S3_CLK] = &gcc_qupv3_wrap2_s3_clk.clkr, 3296 [GCC_QUPV3_WRAP2_S3_CLK_SRC] = &gcc_qupv3_wrap2_s3_clk_src.clkr, 3297 [GCC_QUPV3_WRAP2_S4_CLK] = &gcc_qupv3_wrap2_s4_clk.clkr, 3298 [GCC_QUPV3_WRAP2_S4_CLK_SRC] = &gcc_qupv3_wrap2_s4_clk_src.clkr, 3299 [GCC_QUPV3_WRAP3_CORE_2X_CLK] = &gcc_qupv3_wrap3_core_2x_clk.clkr, 3300 [GCC_QUPV3_WRAP3_CORE_CLK] = &gcc_qupv3_wrap3_core_clk.clkr, 3301 [GCC_QUPV3_WRAP3_IBI_CTRL_0_CLK_SRC] = &gcc_qupv3_wrap3_ibi_ctrl_0_clk_src.clkr, 3302 [GCC_QUPV3_WRAP3_IBI_CTRL_1_CLK] = &gcc_qupv3_wrap3_ibi_ctrl_1_clk.clkr, 3303 [GCC_QUPV3_WRAP3_IBI_CTRL_2_CLK] = &gcc_qupv3_wrap3_ibi_ctrl_2_clk.clkr, 3304 [GCC_QUPV3_WRAP3_S0_CLK] = &gcc_qupv3_wrap3_s0_clk.clkr, 3305 [GCC_QUPV3_WRAP3_S0_CLK_SRC] = &gcc_qupv3_wrap3_s0_clk_src.clkr, 3306 [GCC_QUPV3_WRAP3_S1_CLK] = &gcc_qupv3_wrap3_s1_clk.clkr, 3307 [GCC_QUPV3_WRAP3_S1_CLK_SRC] = &gcc_qupv3_wrap3_s1_clk_src.clkr, 3308 [GCC_QUPV3_WRAP3_S2_CLK] = &gcc_qupv3_wrap3_s2_clk.clkr, 3309 [GCC_QUPV3_WRAP3_S2_CLK_SRC] = &gcc_qupv3_wrap3_s2_clk_src.clkr, 3310 [GCC_QUPV3_WRAP3_S3_CLK] = &gcc_qupv3_wrap3_s3_clk.clkr, 3311 [GCC_QUPV3_WRAP3_S3_CLK_SRC] = &gcc_qupv3_wrap3_s3_clk_src.clkr, 3312 [GCC_QUPV3_WRAP3_S4_CLK] = &gcc_qupv3_wrap3_s4_clk.clkr, 3313 [GCC_QUPV3_WRAP3_S4_CLK_SRC] = &gcc_qupv3_wrap3_s4_clk_src.clkr, 3314 [GCC_QUPV3_WRAP3_S5_CLK] = &gcc_qupv3_wrap3_s5_clk.clkr, 3315 [GCC_QUPV3_WRAP3_S5_CLK_SRC] = &gcc_qupv3_wrap3_s5_clk_src.clkr, 3316 [GCC_QUPV3_WRAP4_CORE_2X_CLK] = &gcc_qupv3_wrap4_core_2x_clk.clkr, 3317 [GCC_QUPV3_WRAP4_CORE_CLK] = &gcc_qupv3_wrap4_core_clk.clkr, 3318 [GCC_QUPV3_WRAP4_S0_CLK] = &gcc_qupv3_wrap4_s0_clk.clkr, 3319 [GCC_QUPV3_WRAP4_S0_CLK_SRC] = &gcc_qupv3_wrap4_s0_clk_src.clkr, 3320 [GCC_QUPV3_WRAP4_S1_CLK] = &gcc_qupv3_wrap4_s1_clk.clkr, 3321 [GCC_QUPV3_WRAP4_S1_CLK_SRC] = &gcc_qupv3_wrap4_s1_clk_src.clkr, 3322 [GCC_QUPV3_WRAP4_S2_CLK] = &gcc_qupv3_wrap4_s2_clk.clkr, 3323 [GCC_QUPV3_WRAP4_S2_CLK_SRC] = &gcc_qupv3_wrap4_s2_clk_src.clkr, 3324 [GCC_QUPV3_WRAP4_S3_CLK] = &gcc_qupv3_wrap4_s3_clk.clkr, 3325 [GCC_QUPV3_WRAP4_S3_CLK_SRC] = &gcc_qupv3_wrap4_s3_clk_src.clkr, 3326 [GCC_QUPV3_WRAP4_S4_CLK] = &gcc_qupv3_wrap4_s4_clk.clkr, 3327 [GCC_QUPV3_WRAP4_S4_CLK_SRC] = &gcc_qupv3_wrap4_s4_clk_src.clkr, 3328 [GCC_QUPV3_WRAP_1_M_AXI_CLK] = &gcc_qupv3_wrap_1_m_axi_clk.clkr, 3329 [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr, 3330 [GCC_QUPV3_WRAP_2_M_AHB_CLK] = &gcc_qupv3_wrap_2_m_ahb_clk.clkr, 3331 [GCC_QUPV3_WRAP_2_S_AHB_CLK] = &gcc_qupv3_wrap_2_s_ahb_clk.clkr, 3332 [GCC_QUPV3_WRAP_3_IBI_1_AHB_CLK] = &gcc_qupv3_wrap_3_ibi_1_ahb_clk.clkr, 3333 [GCC_QUPV3_WRAP_3_IBI_2_AHB_CLK] = &gcc_qupv3_wrap_3_ibi_2_ahb_clk.clkr, 3334 [GCC_QUPV3_WRAP_3_M_AHB_CLK] = &gcc_qupv3_wrap_3_m_ahb_clk.clkr, 3335 [GCC_QUPV3_WRAP_3_S_AHB_CLK] = &gcc_qupv3_wrap_3_s_ahb_clk.clkr, 3336 [GCC_QUPV3_WRAP_4_M_AHB_CLK] = &gcc_qupv3_wrap_4_m_ahb_clk.clkr, 3337 [GCC_QUPV3_WRAP_4_S_AHB_CLK] = &gcc_qupv3_wrap_4_s_ahb_clk.clkr, 3338 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, 3339 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, 3340 [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr, 3341 [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr, 3342 [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr, 3343 [GCC_SDCC4_APPS_CLK_SRC] = &gcc_sdcc4_apps_clk_src.clkr, 3344 [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr, 3345 [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr, 3346 [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr, 3347 [GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr, 3348 [GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr, 3349 [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr, 3350 [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr, 3351 [GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr, 3352 [GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC] = &gcc_ufs_phy_rx_symbol_0_clk_src.clkr, 3353 [GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &gcc_ufs_phy_rx_symbol_1_clk.clkr, 3354 [GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC] = &gcc_ufs_phy_rx_symbol_1_clk_src.clkr, 3355 [GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr, 3356 [GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC] = &gcc_ufs_phy_tx_symbol_0_clk_src.clkr, 3357 [GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr, 3358 [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] = &gcc_ufs_phy_unipro_core_clk_src.clkr, 3359 [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr, 3360 [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr, 3361 [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr, 3362 [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = &gcc_usb30_prim_mock_utmi_clk_src.clkr, 3363 [GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr, 3364 [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr, 3365 [GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr, 3366 [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr, 3367 [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr, 3368 [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr, 3369 [GCC_USB3_PRIM_PHY_PIPE_CLK_SRC] = &gcc_usb3_prim_phy_pipe_clk_src.clkr, 3370 [GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr, 3371 [GCC_VIDEO_AXI1_CLK] = &gcc_video_axi1_clk.clkr, 3372 [GCC_QMIP_CAMERA_CMD_AHB_CLK] = &gcc_qmip_camera_cmd_ahb_clk.clkr, 3373 [GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr, 3374 [GCC_QMIP_GPU_AHB_CLK] = &gcc_qmip_gpu_ahb_clk.clkr, 3375 [GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr, 3376 [GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr, 3377 [GCC_QMIP_DISP_DCP_SF_AHB_CLK] = &gcc_qmip_disp_dcp_sf_ahb_clk.clkr, 3378 [GCC_QMIP_PCIE_AHB_CLK] = &gcc_qmip_pcie_ahb_clk.clkr, 3379 [GCC_QMIP_VIDEO_CV_CPU_AHB_CLK] = &gcc_qmip_video_cv_cpu_ahb_clk.clkr, 3380 [GCC_QMIP_VIDEO_CVP_AHB_CLK] = &gcc_qmip_video_cvp_ahb_clk.clkr, 3381 [GCC_QMIP_VIDEO_V_CPU_AHB_CLK] = &gcc_qmip_video_v_cpu_ahb_clk.clkr, 3382 }; 3383 3384 static struct gdsc *gcc_kaanapali_gdscs[] = { 3385 [GCC_PCIE_0_GDSC] = &gcc_pcie_0_gdsc, 3386 [GCC_PCIE_0_PHY_GDSC] = &gcc_pcie_0_phy_gdsc, 3387 [GCC_UFS_MEM_PHY_GDSC] = &gcc_ufs_mem_phy_gdsc, 3388 [GCC_UFS_PHY_GDSC] = &gcc_ufs_phy_gdsc, 3389 [GCC_USB30_PRIM_GDSC] = &gcc_usb30_prim_gdsc, 3390 [GCC_USB3_PHY_GDSC] = &gcc_usb3_phy_gdsc, 3391 }; 3392 3393 static const struct qcom_reset_map gcc_kaanapali_resets[] = { 3394 [GCC_CAMERA_BCR] = { 0x26000 }, 3395 [GCC_DISPLAY_BCR] = { 0x27000 }, 3396 [GCC_EVA_AXI0_CLK_ARES] = { 0x9f008, 2 }, 3397 [GCC_EVA_AXI0C_CLK_ARES] = { 0x9f01c, 2 }, 3398 [GCC_EVA_BCR] = { 0x9f000 }, 3399 [GCC_GPU_BCR] = { 0x71000 }, 3400 [GCC_PCIE_0_BCR] = { 0x6b000 }, 3401 [GCC_PCIE_0_LINK_DOWN_BCR] = { 0x6c014 }, 3402 [GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0x6c020 }, 3403 [GCC_PCIE_0_PHY_BCR] = { 0x6c01c }, 3404 [GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR] = { 0x6c028 }, 3405 [GCC_PCIE_PHY_BCR] = { 0x6f000 }, 3406 [GCC_PCIE_PHY_CFG_AHB_BCR] = { 0x6f00c }, 3407 [GCC_PCIE_PHY_COM_BCR] = { 0x6f010 }, 3408 [GCC_PCIE_RSCC_BCR] = { 0x11000 }, 3409 [GCC_PDM_BCR] = { 0x33000 }, 3410 [GCC_QUPV3_WRAPPER_1_BCR] = { 0x18000 }, 3411 [GCC_QUPV3_WRAPPER_2_BCR] = { 0x1e000 }, 3412 [GCC_QUPV3_WRAPPER_3_BCR] = { 0xa8000 }, 3413 [GCC_QUPV3_WRAPPER_4_BCR] = { 0xa9000 }, 3414 [GCC_QUPV3_WRAPPER_I2C_BCR] = { 0x17000 }, 3415 [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 }, 3416 [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 }, 3417 [GCC_SDCC2_BCR] = { 0x14000 }, 3418 [GCC_SDCC4_BCR] = { 0x16000 }, 3419 [GCC_UFS_PHY_BCR] = { 0x77000 }, 3420 [GCC_USB30_PRIM_BCR] = { 0x39000 }, 3421 [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 }, 3422 [GCC_USB3_DP_PHY_SEC_BCR] = { 0x50014 }, 3423 [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 }, 3424 [GCC_USB3_PHY_SEC_BCR] = { 0x5000c }, 3425 [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 }, 3426 [GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 }, 3427 [GCC_VIDEO_AXI0_CLK_ARES] = { 0x32018, 2 }, 3428 [GCC_VIDEO_AXI1_CLK_ARES] = { 0x3202c, 2 }, 3429 [GCC_VIDEO_BCR] = { 0x32000 }, 3430 [GCC_VIDEO_XO_CLK_ARES] = { 0x32040, 2 }, 3431 }; 3432 3433 static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = { 3434 DEFINE_RCG_DFS(gcc_qupv3_wrap1_qspi_ref_clk_src), 3435 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src), 3436 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src), 3437 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src), 3438 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src), 3439 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src), 3440 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s6_clk_src), 3441 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s7_clk_src), 3442 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s0_clk_src), 3443 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s1_clk_src), 3444 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s2_clk_src), 3445 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s3_clk_src), 3446 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s4_clk_src), 3447 DEFINE_RCG_DFS(gcc_qupv3_wrap3_s0_clk_src), 3448 DEFINE_RCG_DFS(gcc_qupv3_wrap3_s1_clk_src), 3449 DEFINE_RCG_DFS(gcc_qupv3_wrap3_s2_clk_src), 3450 DEFINE_RCG_DFS(gcc_qupv3_wrap3_s3_clk_src), 3451 DEFINE_RCG_DFS(gcc_qupv3_wrap3_s4_clk_src), 3452 DEFINE_RCG_DFS(gcc_qupv3_wrap3_s5_clk_src), 3453 DEFINE_RCG_DFS(gcc_qupv3_wrap4_s0_clk_src), 3454 DEFINE_RCG_DFS(gcc_qupv3_wrap4_s1_clk_src), 3455 DEFINE_RCG_DFS(gcc_qupv3_wrap4_s2_clk_src), 3456 DEFINE_RCG_DFS(gcc_qupv3_wrap4_s3_clk_src), 3457 DEFINE_RCG_DFS(gcc_qupv3_wrap4_s4_clk_src), 3458 }; 3459 3460 static const u32 gcc_kaanapali_critical_cbcrs[] = { 3461 0xa0004, /* GCC_CAM_BIST_MCLK_AHB_CLK */ 3462 0x26004, /* GCC_CAMERA_AHB_CLK */ 3463 0x2603c, /* GCC_CAMERA_XO_CLK */ 3464 0x27004, /* GCC_DISP_AHB_CLK */ 3465 0x9f004, /* GCC_EVA_AHB_CLK */ 3466 0x9f024, /* GCC_EVA_XO_CLK */ 3467 0x71004, /* GCC_GPU_CFG_AHB_CLK */ 3468 0x52010, /* GCC_PCIE_RSCC_CFG_AHB_CLK */ 3469 0x52010, /* GCC_PCIE_RSCC_XO_CLK */ 3470 0x32004, /* GCC_VIDEO_AHB_CLK */ 3471 0x32040, /* GCC_VIDEO_XO_CLK */ 3472 }; 3473 3474 static const struct regmap_config gcc_kaanapali_regmap_config = { 3475 .reg_bits = 32, 3476 .reg_stride = 4, 3477 .val_bits = 32, 3478 .max_register = 0x1f41f0, 3479 .fast_io = true, 3480 }; 3481 3482 static void clk_kaanapali_regs_configure(struct device *dev, struct regmap *regmap) 3483 { 3484 /* FORCE_MEM_CORE_ON for ufs phy ice core clocks */ 3485 qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_ice_core_clk, true); 3486 } 3487 3488 static const struct qcom_cc_driver_data gcc_kaanapali_driver_data = { 3489 .clk_cbcrs = gcc_kaanapali_critical_cbcrs, 3490 .num_clk_cbcrs = ARRAY_SIZE(gcc_kaanapali_critical_cbcrs), 3491 .dfs_rcgs = gcc_dfs_clocks, 3492 .num_dfs_rcgs = ARRAY_SIZE(gcc_dfs_clocks), 3493 .clk_regs_configure = clk_kaanapali_regs_configure, 3494 }; 3495 3496 static const struct qcom_cc_desc gcc_kaanapali_desc = { 3497 .config = &gcc_kaanapali_regmap_config, 3498 .clks = gcc_kaanapali_clocks, 3499 .num_clks = ARRAY_SIZE(gcc_kaanapali_clocks), 3500 .resets = gcc_kaanapali_resets, 3501 .num_resets = ARRAY_SIZE(gcc_kaanapali_resets), 3502 .gdscs = gcc_kaanapali_gdscs, 3503 .num_gdscs = ARRAY_SIZE(gcc_kaanapali_gdscs), 3504 .driver_data = &gcc_kaanapali_driver_data, 3505 }; 3506 3507 static const struct of_device_id gcc_kaanapali_match_table[] = { 3508 { .compatible = "qcom,kaanapali-gcc" }, 3509 { } 3510 }; 3511 MODULE_DEVICE_TABLE(of, gcc_kaanapali_match_table); 3512 3513 static int gcc_kaanapali_probe(struct platform_device *pdev) 3514 { 3515 return qcom_cc_probe(pdev, &gcc_kaanapali_desc); 3516 } 3517 3518 static struct platform_driver gcc_kaanapali_driver = { 3519 .probe = gcc_kaanapali_probe, 3520 .driver = { 3521 .name = "gcc-kaanapali", 3522 .of_match_table = gcc_kaanapali_match_table, 3523 }, 3524 }; 3525 3526 static int __init gcc_kaanapali_init(void) 3527 { 3528 return platform_driver_register(&gcc_kaanapali_driver); 3529 } 3530 subsys_initcall(gcc_kaanapali_init); 3531 3532 static void __exit gcc_kaanapali_exit(void) 3533 { 3534 platform_driver_unregister(&gcc_kaanapali_driver); 3535 } 3536 module_exit(gcc_kaanapali_exit); 3537 3538 MODULE_DESCRIPTION("QTI GCC Kaanapali Driver"); 3539 MODULE_LICENSE("GPL"); 3540