1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 4 */ 5 6 #include <linux/clk-provider.h> 7 #include <linux/module.h> 8 #include <linux/platform_device.h> 9 #include <linux/regmap.h> 10 11 #include <dt-bindings/clock/qcom,ipq9650-gcc.h> 12 #include <dt-bindings/reset/qcom,ipq9650-gcc.h> 13 14 #include "clk-alpha-pll.h" 15 #include "clk-branch.h" 16 #include "clk-rcg.h" 17 #include "clk-regmap.h" 18 #include "clk-regmap-divider.h" 19 #include "clk-regmap-mux.h" 20 #include "clk-regmap-phy-mux.h" 21 #include "reset.h" 22 23 enum { 24 DT_XO, 25 DT_SLEEP_CLK, 26 DT_PCIE30_PHY0_PIPE_CLK, 27 DT_PCIE30_PHY1_PIPE_CLK, 28 DT_PCIE30_PHY2_PIPE_CLK, 29 DT_PCIE30_PHY3_PIPE_CLK, 30 DT_PCIE30_PHY4_PIPE_CLK, 31 DT_USB3_PHY0_CC_PIPE_CLK, 32 DT_NSS_CMN_CLK, 33 }; 34 35 enum { 36 P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 37 P_GPLL0_OUT_MAIN, 38 P_GPLL0_OUT_ODD, 39 P_GPLL2_OUT_AUX, 40 P_GPLL2_OUT_MAIN, 41 P_GPLL4_OUT_MAIN, 42 P_GPLL4_OUT_ODD, 43 P_NSS_CMN_CLK, 44 P_SLEEP_CLK, 45 P_XO, 46 }; 47 48 static const struct clk_parent_data gcc_parent_data_xo = { .index = DT_XO }; 49 50 static struct clk_alpha_pll gpll0_main = { 51 .offset = 0x20000, 52 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 53 .clkr = { 54 .enable_reg = 0xb000, 55 .enable_mask = BIT(0), 56 .hw.init = &(const struct clk_init_data) { 57 .name = "gpll0_main", 58 .parent_data = &gcc_parent_data_xo, 59 .num_parents = 1, 60 .ops = &clk_alpha_pll_fixed_lucid_ops, 61 }, 62 }, 63 }; 64 65 static struct clk_fixed_factor gpll0_div2 = { 66 .mult = 1, 67 .div = 2, 68 .hw.init = &(const struct clk_init_data) { 69 .name = "gpll0_div2", 70 .parent_hws = (const struct clk_hw *[]) { 71 &gpll0_main.clkr.hw 72 }, 73 .num_parents = 1, 74 .ops = &clk_fixed_factor_ops, 75 }, 76 }; 77 78 static struct clk_alpha_pll_postdiv gpll0 = { 79 .offset = 0x20000, 80 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 81 .width = 4, 82 .clkr.hw.init = &(const struct clk_init_data) { 83 .name = "gpll0", 84 .parent_hws = (const struct clk_hw *[]) { 85 &gpll0_main.clkr.hw }, 86 .num_parents = 1, 87 .ops = &clk_alpha_pll_postdiv_ro_ops, 88 }, 89 }; 90 91 static struct clk_alpha_pll gpll2 = { 92 .offset = 0x21000, 93 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_ZONDA], 94 .clkr = { 95 .enable_reg = 0xb000, 96 .enable_mask = BIT(1), 97 .hw.init = &(const struct clk_init_data) { 98 .name = "gpll2", 99 .parent_data = &gcc_parent_data_xo, 100 .num_parents = 1, 101 .ops = &clk_alpha_pll_zonda_ops, 102 }, 103 }, 104 }; 105 106 static const struct clk_div_table post_div_table_gpll2_out_main[] = { 107 { 0x1, 2 }, 108 { } 109 }; 110 111 static struct clk_alpha_pll_postdiv gpll2_out_main = { 112 .offset = 0x21000, 113 .post_div_shift = 8, 114 .post_div_table = post_div_table_gpll2_out_main, 115 .num_post_div = ARRAY_SIZE(post_div_table_gpll2_out_main), 116 .width = 2, 117 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_ZONDA], 118 .clkr.hw.init = &(const struct clk_init_data) { 119 .name = "gpll2_out_main", 120 .parent_hws = (const struct clk_hw*[]) { 121 &gpll2.clkr.hw, 122 }, 123 .num_parents = 1, 124 .ops = &clk_alpha_pll_postdiv_zonda_ops, 125 }, 126 }; 127 128 static struct clk_alpha_pll gpll4 = { 129 .offset = 0x22000, 130 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 131 .clkr = { 132 .enable_reg = 0xb000, 133 .enable_mask = BIT(2), 134 .hw.init = &(const struct clk_init_data) { 135 .name = "gpll4", 136 .parent_data = &gcc_parent_data_xo, 137 .num_parents = 1, 138 /* 139 * There are no consumers for this GPLL in kernel yet, 140 * (will be added soon), so the clock framework 141 * disables this source. But some of the clocks 142 * initialized by boot loaders uses this source. So we 143 * need to keep this clock ON. Add the 144 * CLK_IGNORE_UNUSED flag so the clock will not be 145 * disabled. Once the consumer in kernel is added, we 146 * can get rid of this flag. 147 */ 148 .flags = CLK_IS_CRITICAL, 149 .ops = &clk_alpha_pll_fixed_lucid_ops, 150 }, 151 }, 152 }; 153 154 static const struct parent_map gcc_parent_map_xo[] = { 155 { P_XO, 0 }, 156 }; 157 158 static const struct parent_map gcc_parent_map_0[] = { 159 { P_XO, 0 }, 160 { P_GPLL0_OUT_MAIN, 1 }, 161 { P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 4 }, 162 }; 163 164 static const struct clk_parent_data gcc_parent_data_0[] = { 165 { .index = DT_XO }, 166 { .hw = &gpll0.clkr.hw }, 167 { .hw = &gpll0_div2.hw }, 168 }; 169 170 static const struct parent_map gcc_parent_map_1[] = { 171 { P_XO, 0 }, 172 { P_GPLL0_OUT_MAIN, 1 }, 173 { P_GPLL4_OUT_MAIN, 2 }, 174 }; 175 176 static const struct clk_parent_data gcc_parent_data_1[] = { 177 { .index = DT_XO }, 178 { .hw = &gpll0.clkr.hw }, 179 { .hw = &gpll4.clkr.hw }, 180 }; 181 182 static const struct parent_map gcc_parent_map_2[] = { 183 { P_XO, 0 }, 184 { P_GPLL0_OUT_MAIN, 1 }, 185 }; 186 187 static const struct clk_parent_data gcc_parent_data_2[] = { 188 { .index = DT_XO }, 189 { .hw = &gpll0.clkr.hw }, 190 }; 191 192 static const struct parent_map gcc_parent_map_3[] = { 193 { P_XO, 0 }, 194 }; 195 196 static const struct clk_parent_data gcc_parent_data_3[] = { 197 { .index = DT_XO }, 198 }; 199 200 static const struct parent_map gcc_parent_map_4[] = { 201 { P_XO, 0 }, 202 { P_GPLL4_OUT_MAIN, 1 }, 203 { P_GPLL0_OUT_ODD, 2 }, 204 { P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 4 }, 205 }; 206 207 static const struct clk_parent_data gcc_parent_data_4[] = { 208 { .index = DT_XO }, 209 { .hw = &gpll4.clkr.hw }, 210 { .hw = &gpll0.clkr.hw }, 211 { .hw = &gpll0_div2.hw }, 212 }; 213 214 static const struct parent_map gcc_parent_map_5[] = { 215 { P_XO, 0 }, 216 { P_GPLL0_OUT_MAIN, 1 }, 217 { P_GPLL2_OUT_AUX, 2 }, 218 }; 219 220 static const struct clk_parent_data gcc_parent_data_5[] = { 221 { .index = DT_XO }, 222 { .hw = &gpll0.clkr.hw }, 223 { .hw = &gpll2.clkr.hw }, 224 }; 225 226 static const struct parent_map gcc_parent_map_6[] = { 227 { P_XO, 0 }, 228 { P_GPLL4_OUT_ODD, 1 }, 229 { P_GPLL0_OUT_MAIN, 3 }, 230 { P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 4 }, 231 }; 232 233 static const struct clk_parent_data gcc_parent_data_6[] = { 234 { .index = DT_XO }, 235 { .hw = &gpll4.clkr.hw }, 236 { .hw = &gpll0.clkr.hw }, 237 { .hw = &gpll0_div2.hw }, 238 }; 239 240 static const struct parent_map gcc_parent_map_7[] = { 241 { P_XO, 0 }, 242 { P_NSS_CMN_CLK, 1 }, 243 { P_GPLL0_OUT_ODD, 2 }, 244 { P_GPLL2_OUT_AUX, 3 }, 245 }; 246 247 static const struct clk_parent_data gcc_parent_data_7[] = { 248 { .index = DT_XO }, 249 { .index = DT_NSS_CMN_CLK }, 250 { .hw = &gpll0.clkr.hw }, 251 { .hw = &gpll2.clkr.hw }, 252 }; 253 254 static const struct parent_map gcc_parent_map_8[] = { 255 { P_XO, 0 }, 256 { P_GPLL0_OUT_MAIN, 1 }, 257 { P_GPLL0_OUT_ODD, 2 }, 258 { P_SLEEP_CLK, 6 }, 259 }; 260 261 static const struct clk_parent_data gcc_parent_data_8[] = { 262 { .index = DT_XO }, 263 { .hw = &gpll0.clkr.hw }, 264 { .hw = &gpll0.clkr.hw }, 265 { .index = DT_SLEEP_CLK }, 266 }; 267 268 static const struct parent_map gcc_parent_map_9[] = { 269 { P_XO, 0 }, 270 { P_GPLL0_OUT_MAIN, 1 }, 271 { P_GPLL2_OUT_MAIN, 2 }, 272 { P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 4 }, 273 }; 274 275 static const struct clk_parent_data gcc_parent_data_9[] = { 276 { .index = DT_XO }, 277 { .hw = &gpll0.clkr.hw }, 278 { .hw = &gpll2_out_main.clkr.hw }, 279 { .hw = &gpll0_div2.hw }, 280 }; 281 282 static const struct parent_map gcc_parent_map_10[] = { 283 { P_XO, 0 }, 284 { P_GPLL0_OUT_MAIN, 1 }, 285 { P_GPLL4_OUT_MAIN, 2 }, 286 { P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 4 }, 287 }; 288 289 static const struct clk_parent_data gcc_parent_data_10[] = { 290 { .index = DT_XO }, 291 { .hw = &gpll0.clkr.hw }, 292 { .hw = &gpll4.clkr.hw }, 293 { .hw = &gpll0_div2.hw }, 294 }; 295 296 static const struct parent_map gcc_parent_map_11[] = { 297 { P_XO, 0 }, 298 { P_GPLL0_OUT_ODD, 2 }, 299 { P_SLEEP_CLK, 6 }, 300 }; 301 302 static const struct clk_parent_data gcc_parent_data_11[] = { 303 { .index = DT_XO }, 304 { .hw = &gpll0.clkr.hw }, 305 { .index = DT_SLEEP_CLK }, 306 }; 307 308 static const struct parent_map gcc_parent_map_12[] = { 309 { P_SLEEP_CLK, 6 }, 310 }; 311 312 static const struct clk_parent_data gcc_parent_data_12[] = { 313 { .index = DT_SLEEP_CLK }, 314 }; 315 316 static const struct parent_map gcc_parent_map_13[] = { 317 { P_XO, 0 }, 318 { P_GPLL0_OUT_MAIN, 1 }, 319 { P_GPLL4_OUT_MAIN, 2 }, 320 { P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 3 }, 321 }; 322 323 static const struct clk_parent_data gcc_parent_data_13[] = { 324 { .index = DT_XO }, 325 { .hw = &gpll0.clkr.hw }, 326 { .hw = &gpll4.clkr.hw }, 327 { .hw = &gpll0_div2.hw }, 328 }; 329 330 static const struct freq_tbl ftbl_gcc_adss_pwm_clk_src[] = { 331 F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0), 332 { } 333 }; 334 335 static struct clk_rcg2 gcc_adss_pwm_clk_src = { 336 .cmd_rcgr = 0x1c004, 337 .mnd_width = 0, 338 .hid_width = 5, 339 .parent_map = gcc_parent_map_2, 340 .freq_tbl = ftbl_gcc_adss_pwm_clk_src, 341 .clkr.hw.init = &(const struct clk_init_data) { 342 .name = "gcc_adss_pwm_clk_src", 343 .parent_data = gcc_parent_data_2, 344 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 345 .ops = &clk_rcg2_ops, 346 }, 347 }; 348 349 static const struct freq_tbl ftbl_gcc_gemnoc_anoc_pcie_clk_src[] = { 350 F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0), 351 { } 352 }; 353 354 static const struct freq_tbl ftbl_gcc_nss_ts_clk_src[] = { 355 F(24000000, P_XO, 1, 0, 0), 356 { } 357 }; 358 359 static struct clk_rcg2 gcc_xo_clk_src = { 360 .cmd_rcgr = 0x34004, 361 .mnd_width = 0, 362 .hid_width = 5, 363 .parent_map = gcc_parent_map_xo, 364 .freq_tbl = ftbl_gcc_nss_ts_clk_src, 365 .clkr.hw.init = &(const struct clk_init_data) { 366 .name = "gcc_xo_clk_src", 367 .parent_data = &gcc_parent_data_xo, 368 .num_parents = 1, 369 .ops = &clk_rcg2_ops, 370 }, 371 }; 372 373 static struct clk_fixed_factor gcc_xo_div4_clk_src = { 374 .mult = 1, 375 .div = 4, 376 .hw.init = &(const struct clk_init_data) { 377 .name = "gcc_xo_div4_clk_src", 378 .parent_hws = (const struct clk_hw *[]) { 379 &gcc_xo_clk_src.clkr.hw 380 }, 381 .num_parents = 1, 382 .flags = CLK_SET_RATE_PARENT, 383 .ops = &clk_fixed_factor_ops, 384 }, 385 }; 386 387 static struct clk_rcg2 gcc_nss_ts_clk_src = { 388 .cmd_rcgr = 0x17088, 389 .mnd_width = 0, 390 .hid_width = 5, 391 .parent_map = gcc_parent_map_3, 392 .freq_tbl = ftbl_gcc_nss_ts_clk_src, 393 .clkr.hw.init = &(const struct clk_init_data) { 394 .name = "gcc_nss_ts_clk_src", 395 .parent_data = gcc_parent_data_3, 396 .num_parents = ARRAY_SIZE(gcc_parent_data_3), 397 .ops = &clk_rcg2_ops, 398 }, 399 }; 400 401 static const struct freq_tbl ftbl_gcc_nssnoc_memnoc_bfdcd_clk_src[] = { 402 F(462000000, P_NSS_CMN_CLK, 1, 0, 0), 403 { } 404 }; 405 406 static struct clk_rcg2 gcc_nssnoc_memnoc_bfdcd_clk_src = { 407 .cmd_rcgr = 0x17004, 408 .mnd_width = 0, 409 .hid_width = 5, 410 .parent_map = gcc_parent_map_7, 411 .freq_tbl = ftbl_gcc_nssnoc_memnoc_bfdcd_clk_src, 412 .clkr.hw.init = &(const struct clk_init_data) { 413 .name = "gcc_nssnoc_memnoc_bfdcd_clk_src", 414 .parent_data = gcc_parent_data_7, 415 .num_parents = ARRAY_SIZE(gcc_parent_data_7), 416 .ops = &clk_rcg2_ops, 417 }, 418 }; 419 420 static const struct freq_tbl ftbl_gcc_system_noc_bfdcd_clk_src[] = { 421 F(24000000, P_XO, 1, 0, 0), 422 F(133333333, P_GPLL0_OUT_MAIN, 6, 0, 0), 423 F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0), 424 F(266666667, P_GPLL4_OUT_MAIN, 4.5, 0, 0), 425 { } 426 }; 427 428 static struct clk_rcg2 gcc_system_noc_bfdcd_clk_src = { 429 .cmd_rcgr = 0x2e004, 430 .freq_tbl = ftbl_gcc_system_noc_bfdcd_clk_src, 431 .hid_width = 5, 432 .parent_map = gcc_parent_map_13, 433 .clkr.hw.init = &(const struct clk_init_data) { 434 .name = "gcc_system_noc_bfdcd_clk_src", 435 .parent_data = gcc_parent_data_13, 436 .num_parents = ARRAY_SIZE(gcc_parent_data_13), 437 .ops = &clk_rcg2_ops, 438 }, 439 }; 440 441 static const struct freq_tbl ftbl_gcc_pcnoc_bfdcd_clk_src[] = { 442 F(24000000, P_XO, 1, 0, 0), 443 F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0), 444 F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0), 445 { } 446 }; 447 448 static struct clk_rcg2 gcc_pcnoc_bfdcd_clk_src = { 449 .cmd_rcgr = 0x31004, 450 .mnd_width = 0, 451 .hid_width = 5, 452 .parent_map = gcc_parent_map_0, 453 .freq_tbl = ftbl_gcc_pcnoc_bfdcd_clk_src, 454 .clkr.hw.init = &(const struct clk_init_data) { 455 .name = "gcc_pcnoc_bfdcd_clk_src", 456 .parent_data = gcc_parent_data_0, 457 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 458 /* 459 * There are no consumers for this source in kernel yet, 460 * (will be added soon), so the clock framework 461 * disables this source. But some of the clocks 462 * initialized by boot loaders uses this source. So we 463 * need to keep this clock ON. Add the 464 * CLK_IGNORE_UNUSED flag so the clock will not be 465 * disabled. Once the consumer in kernel is added, we 466 * can get rid of this flag. 467 */ 468 .flags = CLK_IS_CRITICAL, 469 .ops = &clk_rcg2_ops, 470 }, 471 }; 472 static const struct freq_tbl ftbl_gcc_pcie0_axi_m_clk_src[] = { 473 F(200000000, P_GPLL4_OUT_MAIN, 6, 0, 0), 474 { } 475 }; 476 477 static struct clk_rcg2 gcc_pcie0_axi_m_clk_src = { 478 .cmd_rcgr = 0x28018, 479 .mnd_width = 0, 480 .hid_width = 5, 481 .parent_map = gcc_parent_map_1, 482 .freq_tbl = ftbl_gcc_pcie0_axi_m_clk_src, 483 .clkr.hw.init = &(const struct clk_init_data) { 484 .name = "gcc_pcie0_axi_m_clk_src", 485 .parent_data = gcc_parent_data_1, 486 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 487 .ops = &clk_rcg2_ops, 488 }, 489 }; 490 491 static struct clk_rcg2 gcc_pcie0_axi_s_clk_src = { 492 .cmd_rcgr = 0x28020, 493 .mnd_width = 0, 494 .hid_width = 5, 495 .parent_map = gcc_parent_map_1, 496 .freq_tbl = ftbl_gcc_pcie0_axi_m_clk_src, 497 .clkr.hw.init = &(const struct clk_init_data) { 498 .name = "gcc_pcie0_axi_s_clk_src", 499 .parent_data = gcc_parent_data_1, 500 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 501 .ops = &clk_rcg2_ops, 502 }, 503 }; 504 505 static struct clk_rcg2 gcc_pcie0_rchng_clk_src = { 506 .cmd_rcgr = 0x28028, 507 .mnd_width = 0, 508 .hid_width = 5, 509 .parent_map = gcc_parent_map_2, 510 .freq_tbl = ftbl_gcc_adss_pwm_clk_src, 511 .clkr.hw.init = &(const struct clk_init_data) { 512 .name = "gcc_pcie0_rchng_clk_src", 513 .parent_data = gcc_parent_data_2, 514 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 515 .ops = &clk_rcg2_ops, 516 }, 517 }; 518 519 static const struct freq_tbl ftbl_gcc_pcie1_axi_m_clk_src[] = { 520 F(266666667, P_GPLL4_OUT_MAIN, 4.5, 0, 0), 521 { } 522 }; 523 524 static struct clk_rcg2 gcc_pcie1_axi_m_clk_src = { 525 .cmd_rcgr = 0x29018, 526 .mnd_width = 0, 527 .hid_width = 5, 528 .parent_map = gcc_parent_map_1, 529 .freq_tbl = ftbl_gcc_pcie1_axi_m_clk_src, 530 .clkr.hw.init = &(const struct clk_init_data) { 531 .name = "gcc_pcie1_axi_m_clk_src", 532 .parent_data = gcc_parent_data_1, 533 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 534 .ops = &clk_rcg2_ops, 535 }, 536 }; 537 538 static struct clk_rcg2 gcc_pcie1_axi_s_clk_src = { 539 .cmd_rcgr = 0x29020, 540 .mnd_width = 0, 541 .hid_width = 5, 542 .parent_map = gcc_parent_map_1, 543 .freq_tbl = ftbl_gcc_pcie0_axi_m_clk_src, 544 .clkr.hw.init = &(const struct clk_init_data) { 545 .name = "gcc_pcie1_axi_s_clk_src", 546 .parent_data = gcc_parent_data_1, 547 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 548 .ops = &clk_rcg2_ops, 549 }, 550 }; 551 552 static struct clk_rcg2 gcc_pcie1_rchng_clk_src = { 553 .cmd_rcgr = 0x29028, 554 .mnd_width = 0, 555 .hid_width = 5, 556 .parent_map = gcc_parent_map_2, 557 .freq_tbl = ftbl_gcc_adss_pwm_clk_src, 558 .clkr.hw.init = &(const struct clk_init_data) { 559 .name = "gcc_pcie1_rchng_clk_src", 560 .parent_data = gcc_parent_data_2, 561 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 562 .ops = &clk_rcg2_ops, 563 }, 564 }; 565 566 static struct clk_rcg2 gcc_pcie2_axi_m_clk_src = { 567 .cmd_rcgr = 0x2a018, 568 .mnd_width = 0, 569 .hid_width = 5, 570 .parent_map = gcc_parent_map_1, 571 .freq_tbl = ftbl_gcc_pcie1_axi_m_clk_src, 572 .clkr.hw.init = &(const struct clk_init_data) { 573 .name = "gcc_pcie2_axi_m_clk_src", 574 .parent_data = gcc_parent_data_1, 575 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 576 .ops = &clk_rcg2_ops, 577 }, 578 }; 579 580 static struct clk_rcg2 gcc_pcie2_axi_s_clk_src = { 581 .cmd_rcgr = 0x2a020, 582 .mnd_width = 0, 583 .hid_width = 5, 584 .parent_map = gcc_parent_map_1, 585 .freq_tbl = ftbl_gcc_pcie0_axi_m_clk_src, 586 .clkr.hw.init = &(const struct clk_init_data) { 587 .name = "gcc_pcie2_axi_s_clk_src", 588 .parent_data = gcc_parent_data_1, 589 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 590 .ops = &clk_rcg2_ops, 591 }, 592 }; 593 594 static struct clk_rcg2 gcc_pcie2_rchng_clk_src = { 595 .cmd_rcgr = 0x2a028, 596 .mnd_width = 0, 597 .hid_width = 5, 598 .parent_map = gcc_parent_map_2, 599 .freq_tbl = ftbl_gcc_adss_pwm_clk_src, 600 .clkr.hw.init = &(const struct clk_init_data) { 601 .name = "gcc_pcie2_rchng_clk_src", 602 .parent_data = gcc_parent_data_2, 603 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 604 .ops = &clk_rcg2_ops, 605 }, 606 }; 607 608 static struct clk_rcg2 gcc_pcie3_axi_m_clk_src = { 609 .cmd_rcgr = 0x2b018, 610 .mnd_width = 0, 611 .hid_width = 5, 612 .parent_map = gcc_parent_map_1, 613 .freq_tbl = ftbl_gcc_pcie1_axi_m_clk_src, 614 .clkr.hw.init = &(const struct clk_init_data) { 615 .name = "gcc_pcie3_axi_m_clk_src", 616 .parent_data = gcc_parent_data_1, 617 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 618 .ops = &clk_rcg2_ops, 619 }, 620 }; 621 622 static struct clk_rcg2 gcc_pcie3_axi_s_clk_src = { 623 .cmd_rcgr = 0x2b020, 624 .mnd_width = 0, 625 .hid_width = 5, 626 .parent_map = gcc_parent_map_1, 627 .freq_tbl = ftbl_gcc_pcie0_axi_m_clk_src, 628 .clkr.hw.init = &(const struct clk_init_data) { 629 .name = "gcc_pcie3_axi_s_clk_src", 630 .parent_data = gcc_parent_data_1, 631 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 632 .ops = &clk_rcg2_ops, 633 }, 634 }; 635 636 static struct clk_rcg2 gcc_pcie3_rchng_clk_src = { 637 .cmd_rcgr = 0x2b028, 638 .mnd_width = 0, 639 .hid_width = 5, 640 .parent_map = gcc_parent_map_2, 641 .freq_tbl = ftbl_gcc_adss_pwm_clk_src, 642 .clkr.hw.init = &(const struct clk_init_data) { 643 .name = "gcc_pcie3_rchng_clk_src", 644 .parent_data = gcc_parent_data_2, 645 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 646 .ops = &clk_rcg2_ops, 647 }, 648 }; 649 650 static struct clk_rcg2 gcc_pcie4_axi_m_clk_src = { 651 .cmd_rcgr = 0x25004, 652 .mnd_width = 0, 653 .hid_width = 5, 654 .parent_map = gcc_parent_map_1, 655 .freq_tbl = ftbl_gcc_pcie0_axi_m_clk_src, 656 .clkr.hw.init = &(const struct clk_init_data) { 657 .name = "gcc_pcie4_axi_m_clk_src", 658 .parent_data = gcc_parent_data_1, 659 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 660 .ops = &clk_rcg2_ops, 661 }, 662 }; 663 664 static struct clk_rcg2 gcc_pcie4_axi_s_clk_src = { 665 .cmd_rcgr = 0x2500c, 666 .mnd_width = 0, 667 .hid_width = 5, 668 .parent_map = gcc_parent_map_1, 669 .freq_tbl = ftbl_gcc_pcie0_axi_m_clk_src, 670 .clkr.hw.init = &(const struct clk_init_data) { 671 .name = "gcc_pcie4_axi_s_clk_src", 672 .parent_data = gcc_parent_data_1, 673 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 674 .ops = &clk_rcg2_ops, 675 }, 676 }; 677 678 static struct clk_rcg2 gcc_pcie4_rchng_clk_src = { 679 .cmd_rcgr = 0x25014, 680 .mnd_width = 0, 681 .hid_width = 5, 682 .parent_map = gcc_parent_map_2, 683 .freq_tbl = ftbl_gcc_adss_pwm_clk_src, 684 .clkr.hw.init = &(const struct clk_init_data) { 685 .name = "gcc_pcie4_rchng_clk_src", 686 .parent_data = gcc_parent_data_2, 687 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 688 .ops = &clk_rcg2_ops, 689 }, 690 }; 691 692 static const struct freq_tbl ftbl_gcc_pcie_aux_clk_src[] = { 693 F(20000000, P_GPLL0_OUT_MAIN, 10, 1, 4), 694 { } 695 }; 696 697 static struct clk_rcg2 gcc_pcie_aux_clk_src = { 698 .cmd_rcgr = 0x28004, 699 .mnd_width = 16, 700 .hid_width = 5, 701 .parent_map = gcc_parent_map_8, 702 .freq_tbl = ftbl_gcc_pcie_aux_clk_src, 703 .clkr.hw.init = &(const struct clk_init_data) { 704 .name = "gcc_pcie_aux_clk_src", 705 .parent_data = gcc_parent_data_8, 706 .num_parents = ARRAY_SIZE(gcc_parent_data_8), 707 .ops = &clk_rcg2_ops, 708 }, 709 }; 710 711 static const struct freq_tbl ftbl_gcc_qdss_at_clk_src[] = { 712 F(240000000, P_GPLL4_OUT_MAIN, 5, 0, 0), 713 { } 714 }; 715 716 static struct clk_rcg2 gcc_qdss_at_clk_src = { 717 .cmd_rcgr = 0x2d004, 718 .mnd_width = 0, 719 .hid_width = 5, 720 .parent_map = gcc_parent_map_4, 721 .freq_tbl = ftbl_gcc_qdss_at_clk_src, 722 .clkr.hw.init = &(const struct clk_init_data) { 723 .name = "gcc_qdss_at_clk_src", 724 .parent_data = gcc_parent_data_4, 725 .num_parents = ARRAY_SIZE(gcc_parent_data_4), 726 .ops = &clk_rcg2_ops, 727 }, 728 }; 729 730 static struct clk_fixed_factor gcc_eud_at_div_clk_src = { 731 .mult = 1, 732 .div = 6, 733 .hw.init = &(const struct clk_init_data) { 734 .name = "gcc_eud_at_div_clk_src", 735 .parent_hws = (const struct clk_hw *[]) { 736 &gcc_qdss_at_clk_src.clkr.hw }, 737 .num_parents = 1, 738 .flags = CLK_SET_RATE_PARENT, 739 .ops = &clk_fixed_factor_ops, 740 }, 741 }; 742 743 static const struct freq_tbl ftbl_gcc_qdss_tsctr_clk_src[] = { 744 F(600000000, P_GPLL4_OUT_MAIN, 2, 0, 0), 745 { } 746 }; 747 748 static struct clk_rcg2 gcc_qdss_tsctr_clk_src = { 749 .cmd_rcgr = 0x2d01c, 750 .mnd_width = 0, 751 .hid_width = 5, 752 .parent_map = gcc_parent_map_4, 753 .freq_tbl = ftbl_gcc_qdss_tsctr_clk_src, 754 .clkr.hw.init = &(const struct clk_init_data) { 755 .name = "gcc_qdss_tsctr_clk_src", 756 .parent_data = gcc_parent_data_4, 757 .num_parents = ARRAY_SIZE(gcc_parent_data_4), 758 .ops = &clk_rcg2_ops, 759 }, 760 }; 761 762 static struct clk_fixed_factor gcc_qdss_dap_sync_clk_src = { 763 .mult = 1, 764 .div = 4, 765 .hw.init = &(const struct clk_init_data) { 766 .name = "gcc_qdss_dap_sync_clk_src", 767 .parent_hws = (const struct clk_hw *[]) { 768 &gcc_qdss_tsctr_clk_src.clkr.hw 769 }, 770 .num_parents = 1, 771 .ops = &clk_fixed_factor_ops, 772 }, 773 }; 774 775 static const struct freq_tbl ftbl_gcc_sleep_clk_src[] = { 776 F(32000, P_SLEEP_CLK, 1, 0, 0), 777 { } 778 }; 779 780 static struct clk_rcg2 gcc_sleep_clk_src = { 781 .cmd_rcgr = 0x3400c, 782 .mnd_width = 0, 783 .hid_width = 5, 784 .parent_map = gcc_parent_map_12, 785 .freq_tbl = ftbl_gcc_sleep_clk_src, 786 .clkr.hw.init = &(const struct clk_init_data) { 787 .name = "gcc_sleep_clk_src", 788 .parent_data = gcc_parent_data_12, 789 .num_parents = ARRAY_SIZE(gcc_parent_data_12), 790 .ops = &clk_rcg2_ops, 791 }, 792 }; 793 794 static const struct freq_tbl ftbl_gcc_qpic_io_macro_clk_src[] = { 795 F(24000000, P_XO, 1, 0, 0), 796 F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0), 797 F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0), 798 F(320000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), 799 F(400000000, P_GPLL0_OUT_MAIN, 2, 0, 0), 800 { } 801 }; 802 803 static struct clk_rcg2 gcc_qpic_clk_src = { 804 .cmd_rcgr = 0x32020, 805 .mnd_width = 0, 806 .hid_width = 5, 807 .parent_map = gcc_parent_map_5, 808 .freq_tbl = ftbl_gcc_qpic_io_macro_clk_src, 809 .clkr.hw.init = &(const struct clk_init_data) { 810 .name = "gcc_qpic_clk_src", 811 .parent_data = gcc_parent_data_5, 812 .num_parents = ARRAY_SIZE(gcc_parent_data_5), 813 .ops = &clk_rcg2_ops, 814 }, 815 }; 816 817 static struct clk_rcg2 gcc_qpic_io_macro_clk_src = { 818 .cmd_rcgr = 0x32004, 819 .mnd_width = 0, 820 .hid_width = 5, 821 .parent_map = gcc_parent_map_5, 822 .freq_tbl = ftbl_gcc_qpic_io_macro_clk_src, 823 .clkr.hw.init = &(const struct clk_init_data) { 824 .name = "gcc_qpic_io_macro_clk_src", 825 .parent_data = gcc_parent_data_5, 826 .num_parents = ARRAY_SIZE(gcc_parent_data_5), 827 .ops = &clk_rcg2_ops, 828 }, 829 }; 830 831 static struct clk_rcg2 gcc_qupv3_2x_core_clk_src = { 832 .cmd_rcgr = 0x100c, 833 .mnd_width = 0, 834 .hid_width = 5, 835 .parent_map = gcc_parent_map_0, 836 .freq_tbl = ftbl_gcc_gemnoc_anoc_pcie_clk_src, 837 .clkr.hw.init = &(const struct clk_init_data) { 838 .name = "gcc_qupv3_2x_core_clk_src", 839 .parent_data = gcc_parent_data_0, 840 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 841 .ops = &clk_rcg2_ops, 842 }, 843 }; 844 845 static const struct freq_tbl ftbl_gcc_qupv3_wrap_se0_clk_src[] = { 846 F(960000, P_XO, 10, 2, 5), 847 F(3686636, P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 1, 2, 217), 848 F(4800000, P_XO, 5, 0, 0), 849 F(7373272, P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 1, 4, 217), 850 F(9600000, P_XO, 2.5, 0, 0), 851 F(14746544, P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 1, 8, 217), 852 F(16000000, P_GPLL0_OUT_MAIN, 10, 1, 5), 853 F(24000000, P_XO, 1, 0, 0), 854 F(25000000, P_GPLL0_OUT_MAIN, 16, 1, 2), 855 F(32000000, P_GPLL0_OUT_MAIN, 1, 1, 25), 856 F(40000000, P_GPLL0_OUT_MAIN, 1, 1, 20), 857 F(46400000, P_GPLL0_OUT_MAIN, 2, 29, 250), 858 F(48000000, P_GPLL0_OUT_MAIN, 1, 3, 50), 859 F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0), 860 F(51200000, P_GPLL0_OUT_MAIN, 1, 8, 125), 861 F(56000000, P_GPLL0_OUT_MAIN, 1, 7, 100), 862 F(58986175, P_GPLL0_OUT_MAIN, 1, 16, 217), 863 F(60000000, P_GPLL0_OUT_MAIN, 1, 3, 40), 864 F(64000000, P_GPLL0_OUT_MAIN, 12.5, 0, 0), 865 { } 866 }; 867 868 static struct clk_rcg2 gcc_qupv3_wrap_se0_clk_src = { 869 .cmd_rcgr = 0x2018, 870 .mnd_width = 8, 871 .hid_width = 5, 872 .parent_map = gcc_parent_map_0, 873 .freq_tbl = ftbl_gcc_qupv3_wrap_se0_clk_src, 874 .clkr.hw.init = &(const struct clk_init_data) { 875 .name = "gcc_qupv3_wrap_se0_clk_src", 876 .parent_data = gcc_parent_data_0, 877 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 878 .ops = &clk_rcg2_ops, 879 }, 880 }; 881 882 static struct clk_rcg2 gcc_qupv3_wrap_se1_clk_src = { 883 .cmd_rcgr = 0x3018, 884 .mnd_width = 8, 885 .hid_width = 5, 886 .parent_map = gcc_parent_map_0, 887 .freq_tbl = ftbl_gcc_qupv3_wrap_se0_clk_src, 888 .clkr.hw.init = &(const struct clk_init_data) { 889 .name = "gcc_qupv3_wrap_se1_clk_src", 890 .parent_data = gcc_parent_data_0, 891 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 892 .ops = &clk_rcg2_ops, 893 }, 894 }; 895 896 static struct clk_rcg2 gcc_qupv3_wrap_se2_clk_src = { 897 .cmd_rcgr = 0x3034, 898 .mnd_width = 8, 899 .hid_width = 5, 900 .parent_map = gcc_parent_map_0, 901 .freq_tbl = ftbl_gcc_qupv3_wrap_se0_clk_src, 902 .clkr.hw.init = &(const struct clk_init_data) { 903 .name = "gcc_qupv3_wrap_se2_clk_src", 904 .parent_data = gcc_parent_data_0, 905 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 906 .ops = &clk_rcg2_ops, 907 }, 908 }; 909 910 static struct clk_rcg2 gcc_qupv3_wrap_se3_clk_src = { 911 .cmd_rcgr = 0x3050, 912 .mnd_width = 8, 913 .hid_width = 5, 914 .parent_map = gcc_parent_map_0, 915 .freq_tbl = ftbl_gcc_qupv3_wrap_se0_clk_src, 916 .clkr.hw.init = &(const struct clk_init_data) { 917 .name = "gcc_qupv3_wrap_se3_clk_src", 918 .parent_data = gcc_parent_data_0, 919 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 920 .ops = &clk_rcg2_ops, 921 }, 922 }; 923 924 static const struct freq_tbl ftbl_gcc_qupv3_wrap_se4_clk_src[] = { 925 F(960000, P_XO, 10, 2, 5), 926 F(3686636, P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 1, 2, 217), 927 F(4800000, P_XO, 5, 0, 0), 928 F(7373272, P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 1, 4, 217), 929 F(9600000, P_XO, 2.5, 0, 0), 930 F(14746544, P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 1, 8, 217), 931 F(16000000, P_GPLL0_OUT_MAIN, 10, 1, 5), 932 F(24000000, P_XO, 1, 0, 0), 933 F(25000000, P_GPLL0_OUT_MAIN, 16, 1, 2), 934 F(32000000, P_GPLL0_OUT_MAIN, 1, 1, 25), 935 F(40000000, P_GPLL0_OUT_MAIN, 1, 1, 20), 936 F(46400000, P_GPLL0_OUT_MAIN, 2, 29, 250), 937 F(48000000, P_GPLL0_OUT_MAIN, 1, 3, 50), 938 F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0), 939 F(51200000, P_GPLL0_OUT_MAIN, 1, 8, 125), 940 F(56000000, P_GPLL0_OUT_MAIN, 1, 7, 100), 941 F(58986175, P_GPLL0_OUT_MAIN, 1, 16, 217), 942 F(60000000, P_GPLL0_OUT_MAIN, 1, 3, 40), 943 F(64000000, P_GPLL0_OUT_MAIN, 12.5, 0, 0), 944 F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0), 945 { } 946 }; 947 948 static struct clk_rcg2 gcc_qupv3_wrap_se4_clk_src = { 949 .cmd_rcgr = 0x306c, 950 .mnd_width = 8, 951 .hid_width = 5, 952 .parent_map = gcc_parent_map_0, 953 .freq_tbl = ftbl_gcc_qupv3_wrap_se4_clk_src, 954 .clkr.hw.init = &(const struct clk_init_data) { 955 .name = "gcc_qupv3_wrap_se4_clk_src", 956 .parent_data = gcc_parent_data_0, 957 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 958 .ops = &clk_rcg2_ops, 959 }, 960 }; 961 962 static struct clk_rcg2 gcc_qupv3_wrap_se5_clk_src = { 963 .cmd_rcgr = 0x3090, 964 .mnd_width = 8, 965 .hid_width = 5, 966 .parent_map = gcc_parent_map_0, 967 .freq_tbl = ftbl_gcc_qupv3_wrap_se4_clk_src, 968 .clkr.hw.init = &(const struct clk_init_data) { 969 .name = "gcc_qupv3_wrap_se5_clk_src", 970 .parent_data = gcc_parent_data_0, 971 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 972 .ops = &clk_rcg2_ops, 973 }, 974 }; 975 976 static struct clk_rcg2 gcc_qupv3_wrap_se6_clk_src = { 977 .cmd_rcgr = 0x4004, 978 .mnd_width = 8, 979 .hid_width = 5, 980 .parent_map = gcc_parent_map_0, 981 .freq_tbl = ftbl_gcc_qupv3_wrap_se0_clk_src, 982 .clkr.hw.init = &(const struct clk_init_data) { 983 .name = "gcc_qupv3_wrap_se6_clk_src", 984 .parent_data = gcc_parent_data_0, 985 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 986 .ops = &clk_rcg2_ops, 987 }, 988 }; 989 990 static struct clk_rcg2 gcc_qupv3_wrap_se7_clk_src = { 991 .cmd_rcgr = 0x4020, 992 .mnd_width = 8, 993 .hid_width = 5, 994 .parent_map = gcc_parent_map_0, 995 .freq_tbl = ftbl_gcc_qupv3_wrap_se0_clk_src, 996 .clkr.hw.init = &(const struct clk_init_data) { 997 .name = "gcc_qupv3_wrap_se7_clk_src", 998 .parent_data = gcc_parent_data_0, 999 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1000 .ops = &clk_rcg2_ops, 1001 }, 1002 }; 1003 1004 static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = { 1005 F(144000, P_XO, 16, 12, 125), 1006 F(400000, P_XO, 12, 1, 5), 1007 F(24000000, P_GPLL2_OUT_MAIN, 12, 1, 2), 1008 F(48000000, P_GPLL2_OUT_MAIN, 12, 0, 0), 1009 F(96000000, P_GPLL2_OUT_MAIN, 6, 0, 0), 1010 F(177777778, P_GPLL0_OUT_MAIN, 4.5, 0, 0), 1011 F(192000000, P_GPLL2_OUT_MAIN, 3, 0, 0), 1012 F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0), 1013 { } 1014 }; 1015 1016 static struct clk_rcg2 gcc_sdcc1_apps_clk_src = { 1017 .cmd_rcgr = 0x33004, 1018 .mnd_width = 8, 1019 .hid_width = 5, 1020 .parent_map = gcc_parent_map_9, 1021 .freq_tbl = ftbl_gcc_sdcc1_apps_clk_src, 1022 .clkr.hw.init = &(const struct clk_init_data) { 1023 .name = "gcc_sdcc1_apps_clk_src", 1024 .parent_data = gcc_parent_data_9, 1025 .num_parents = ARRAY_SIZE(gcc_parent_data_9), 1026 .ops = &clk_rcg2_floor_ops, 1027 }, 1028 }; 1029 1030 static const struct freq_tbl ftbl_gcc_sdcc1_ice_core_clk_src[] = { 1031 F(300000000, P_GPLL4_OUT_MAIN, 4, 0, 0), 1032 { } 1033 }; 1034 1035 static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src = { 1036 .cmd_rcgr = 0x33018, 1037 .mnd_width = 8, 1038 .hid_width = 5, 1039 .parent_map = gcc_parent_map_10, 1040 .freq_tbl = ftbl_gcc_sdcc1_ice_core_clk_src, 1041 .clkr.hw.init = &(const struct clk_init_data) { 1042 .name = "gcc_sdcc1_ice_core_clk_src", 1043 .parent_data = gcc_parent_data_10, 1044 .num_parents = ARRAY_SIZE(gcc_parent_data_10), 1045 .ops = &clk_rcg2_floor_ops, 1046 }, 1047 }; 1048 1049 static struct clk_rcg2 gcc_uniphy_sys_clk_src = { 1050 .cmd_rcgr = 0x17090, 1051 .mnd_width = 0, 1052 .hid_width = 5, 1053 .parent_map = gcc_parent_map_3, 1054 .freq_tbl = ftbl_gcc_nss_ts_clk_src, 1055 .clkr.hw.init = &(const struct clk_init_data) { 1056 .name = "gcc_uniphy_sys_clk_src", 1057 .parent_data = gcc_parent_data_3, 1058 .num_parents = ARRAY_SIZE(gcc_parent_data_3), 1059 .ops = &clk_rcg2_ops, 1060 }, 1061 }; 1062 1063 static struct clk_rcg2 gcc_usb0_aux_clk_src = { 1064 .cmd_rcgr = 0x2c018, 1065 .mnd_width = 16, 1066 .hid_width = 5, 1067 .parent_map = gcc_parent_map_11, 1068 .freq_tbl = ftbl_gcc_nss_ts_clk_src, 1069 .clkr.hw.init = &(const struct clk_init_data) { 1070 .name = "gcc_usb0_aux_clk_src", 1071 .parent_data = gcc_parent_data_11, 1072 .num_parents = ARRAY_SIZE(gcc_parent_data_11), 1073 .ops = &clk_rcg2_ops, 1074 }, 1075 }; 1076 1077 static struct clk_rcg2 gcc_usb0_master_clk_src = { 1078 .cmd_rcgr = 0x2c004, 1079 .mnd_width = 8, 1080 .hid_width = 5, 1081 .parent_map = gcc_parent_map_0, 1082 .freq_tbl = ftbl_gcc_gemnoc_anoc_pcie_clk_src, 1083 .clkr.hw.init = &(const struct clk_init_data) { 1084 .name = "gcc_usb0_master_clk_src", 1085 .parent_data = gcc_parent_data_0, 1086 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1087 .ops = &clk_rcg2_ops, 1088 }, 1089 }; 1090 1091 static const struct freq_tbl ftbl_gcc_usb0_mock_utmi_clk_src[] = { 1092 F(24000000, P_XO, 1, 0, 0), 1093 F(60000000, P_GPLL4_OUT_ODD, 10, 1, 2), 1094 { } 1095 }; 1096 1097 static struct clk_rcg2 gcc_usb0_mock_utmi_clk_src = { 1098 .cmd_rcgr = 0x2c02c, 1099 .mnd_width = 8, 1100 .hid_width = 5, 1101 .parent_map = gcc_parent_map_6, 1102 .freq_tbl = ftbl_gcc_usb0_mock_utmi_clk_src, 1103 .clkr.hw.init = &(const struct clk_init_data) { 1104 .name = "gcc_usb0_mock_utmi_clk_src", 1105 .parent_data = gcc_parent_data_6, 1106 .num_parents = ARRAY_SIZE(gcc_parent_data_6), 1107 .ops = &clk_rcg2_ops, 1108 }, 1109 }; 1110 1111 static struct clk_rcg2 gcc_usb1_mock_utmi_clk_src = { 1112 .cmd_rcgr = 0x3c004, 1113 .mnd_width = 8, 1114 .hid_width = 5, 1115 .parent_map = gcc_parent_map_6, 1116 .freq_tbl = ftbl_gcc_usb0_mock_utmi_clk_src, 1117 .clkr.hw.init = &(const struct clk_init_data) { 1118 .name = "gcc_usb1_mock_utmi_clk_src", 1119 .parent_data = gcc_parent_data_6, 1120 .num_parents = ARRAY_SIZE(gcc_parent_data_6), 1121 .ops = &clk_rcg2_ops, 1122 }, 1123 }; 1124 1125 static struct clk_regmap_div gcc_nssnoc_memnoc_div_clk_src = { 1126 .reg = 0x1700c, 1127 .shift = 0, 1128 .width = 4, 1129 .clkr.hw.init = &(const struct clk_init_data) { 1130 .name = "gcc_nssnoc_memnoc_div_clk_src", 1131 .parent_hws = (const struct clk_hw*[]) { 1132 &gcc_nssnoc_memnoc_bfdcd_clk_src.clkr.hw, 1133 }, 1134 .num_parents = 1, 1135 .flags = CLK_SET_RATE_PARENT, 1136 .ops = &clk_regmap_div_ro_ops, 1137 }, 1138 }; 1139 1140 static struct clk_regmap_div gcc_usb0_mock_utmi_div_clk_src = { 1141 .reg = 0x2c040, 1142 .shift = 0, 1143 .width = 2, 1144 .clkr.hw.init = &(const struct clk_init_data) { 1145 .name = "gcc_usb0_mock_utmi_div_clk_src", 1146 .parent_hws = (const struct clk_hw*[]) { 1147 &gcc_usb0_mock_utmi_clk_src.clkr.hw, 1148 }, 1149 .num_parents = 1, 1150 .flags = CLK_SET_RATE_PARENT, 1151 .ops = &clk_regmap_div_ro_ops, 1152 }, 1153 }; 1154 1155 static struct clk_regmap_div gcc_usb1_mock_utmi_div_clk_src = { 1156 .reg = 0x3c018, 1157 .shift = 0, 1158 .width = 2, 1159 .clkr.hw.init = &(const struct clk_init_data) { 1160 .name = "gcc_usb1_mock_utmi_div_clk_src", 1161 .parent_hws = (const struct clk_hw*[]) { 1162 &gcc_usb1_mock_utmi_clk_src.clkr.hw, 1163 }, 1164 .num_parents = 1, 1165 .flags = CLK_SET_RATE_PARENT, 1166 .ops = &clk_regmap_div_ro_ops, 1167 }, 1168 }; 1169 1170 static struct clk_branch gcc_adss_pwm_clk = { 1171 .halt_reg = 0x1c00c, 1172 .halt_check = BRANCH_HALT, 1173 .clkr = { 1174 .enable_reg = 0x1c00c, 1175 .enable_mask = BIT(0), 1176 .hw.init = &(const struct clk_init_data) { 1177 .name = "gcc_adss_pwm_clk", 1178 .parent_hws = (const struct clk_hw*[]) { 1179 &gcc_adss_pwm_clk_src.clkr.hw, 1180 }, 1181 .num_parents = 1, 1182 .flags = CLK_SET_RATE_PARENT, 1183 .ops = &clk_branch2_ops, 1184 }, 1185 }, 1186 }; 1187 1188 static struct clk_branch gcc_anoc_pcie0_1lane_m_clk = { 1189 .halt_reg = 0x2e07c, 1190 .halt_check = BRANCH_HALT, 1191 .clkr = { 1192 .enable_reg = 0x2e07c, 1193 .enable_mask = BIT(0), 1194 .hw.init = &(const struct clk_init_data) { 1195 .name = "gcc_anoc_pcie0_1lane_m_clk", 1196 .parent_hws = (const struct clk_hw*[]) { 1197 &gcc_pcie0_axi_m_clk_src.clkr.hw, 1198 }, 1199 .num_parents = 1, 1200 .flags = CLK_SET_RATE_PARENT, 1201 .ops = &clk_branch2_ops, 1202 }, 1203 }, 1204 }; 1205 1206 static struct clk_branch gcc_anoc_pcie0_1lane_s_clk = { 1207 .halt_reg = 0x2e0cc, 1208 .halt_check = BRANCH_HALT, 1209 .clkr = { 1210 .enable_reg = 0x2e0cc, 1211 .enable_mask = BIT(0), 1212 .hw.init = &(const struct clk_init_data) { 1213 .name = "gcc_anoc_pcie0_1lane_s_clk", 1214 .parent_hws = (const struct clk_hw*[]) { 1215 &gcc_pcie0_axi_s_clk_src.clkr.hw, 1216 }, 1217 .num_parents = 1, 1218 .flags = CLK_SET_RATE_PARENT, 1219 .ops = &clk_branch2_ops, 1220 }, 1221 }, 1222 }; 1223 1224 static struct clk_branch gcc_anoc_pcie1_2lane_m_clk = { 1225 .halt_reg = 0x2e084, 1226 .halt_check = BRANCH_HALT, 1227 .clkr = { 1228 .enable_reg = 0x2e084, 1229 .enable_mask = BIT(0), 1230 .hw.init = &(const struct clk_init_data) { 1231 .name = "gcc_anoc_pcie1_2lane_m_clk", 1232 .parent_hws = (const struct clk_hw*[]) { 1233 &gcc_pcie1_axi_m_clk_src.clkr.hw, 1234 }, 1235 .num_parents = 1, 1236 .flags = CLK_SET_RATE_PARENT, 1237 .ops = &clk_branch2_ops, 1238 }, 1239 }, 1240 }; 1241 1242 static struct clk_branch gcc_anoc_pcie1_2lane_s_clk = { 1243 .halt_reg = 0x2e0d0, 1244 .halt_check = BRANCH_HALT, 1245 .clkr = { 1246 .enable_reg = 0x2e0d0, 1247 .enable_mask = BIT(0), 1248 .hw.init = &(const struct clk_init_data) { 1249 .name = "gcc_anoc_pcie1_2lane_s_clk", 1250 .parent_hws = (const struct clk_hw*[]) { 1251 &gcc_pcie1_axi_s_clk_src.clkr.hw, 1252 }, 1253 .num_parents = 1, 1254 .flags = CLK_SET_RATE_PARENT, 1255 .ops = &clk_branch2_ops, 1256 }, 1257 }, 1258 }; 1259 1260 static struct clk_branch gcc_anoc_pcie2_2lane_m_clk = { 1261 .halt_reg = 0x2e080, 1262 .halt_check = BRANCH_HALT, 1263 .clkr = { 1264 .enable_reg = 0x2e080, 1265 .enable_mask = BIT(0), 1266 .hw.init = &(const struct clk_init_data) { 1267 .name = "gcc_anoc_pcie2_2lane_m_clk", 1268 .parent_hws = (const struct clk_hw*[]) { 1269 &gcc_pcie2_axi_m_clk_src.clkr.hw, 1270 }, 1271 .num_parents = 1, 1272 .flags = CLK_SET_RATE_PARENT, 1273 .ops = &clk_branch2_ops, 1274 }, 1275 }, 1276 }; 1277 1278 static struct clk_branch gcc_anoc_pcie2_2lane_s_clk = { 1279 .halt_reg = 0x2e0d4, 1280 .halt_check = BRANCH_HALT, 1281 .clkr = { 1282 .enable_reg = 0x2e0d4, 1283 .enable_mask = BIT(0), 1284 .hw.init = &(const struct clk_init_data) { 1285 .name = "gcc_anoc_pcie2_2lane_s_clk", 1286 .parent_hws = (const struct clk_hw*[]) { 1287 &gcc_pcie2_axi_s_clk_src.clkr.hw, 1288 }, 1289 .num_parents = 1, 1290 .flags = CLK_SET_RATE_PARENT, 1291 .ops = &clk_branch2_ops, 1292 }, 1293 }, 1294 }; 1295 1296 static struct clk_branch gcc_anoc_pcie3_2lane_m_clk = { 1297 .halt_reg = 0x2e0bc, 1298 .halt_check = BRANCH_HALT, 1299 .clkr = { 1300 .enable_reg = 0x2e0bc, 1301 .enable_mask = BIT(0), 1302 .hw.init = &(const struct clk_init_data) { 1303 .name = "gcc_anoc_pcie3_2lane_m_clk", 1304 .parent_hws = (const struct clk_hw*[]) { 1305 &gcc_pcie3_axi_m_clk_src.clkr.hw, 1306 }, 1307 .num_parents = 1, 1308 .flags = CLK_SET_RATE_PARENT, 1309 .ops = &clk_branch2_ops, 1310 }, 1311 }, 1312 }; 1313 1314 static struct clk_branch gcc_anoc_pcie3_2lane_s_clk = { 1315 .halt_reg = 0x2e0d8, 1316 .halt_check = BRANCH_HALT, 1317 .clkr = { 1318 .enable_reg = 0x2e0d8, 1319 .enable_mask = BIT(0), 1320 .hw.init = &(const struct clk_init_data) { 1321 .name = "gcc_anoc_pcie3_2lane_s_clk", 1322 .parent_hws = (const struct clk_hw*[]) { 1323 &gcc_pcie3_axi_s_clk_src.clkr.hw, 1324 }, 1325 .num_parents = 1, 1326 .flags = CLK_SET_RATE_PARENT, 1327 .ops = &clk_branch2_ops, 1328 }, 1329 }, 1330 }; 1331 1332 static struct clk_branch gcc_anoc_pcie4_1lane_m_clk = { 1333 .halt_reg = 0x2e0c0, 1334 .halt_check = BRANCH_HALT, 1335 .clkr = { 1336 .enable_reg = 0x2e0c0, 1337 .enable_mask = BIT(0), 1338 .hw.init = &(const struct clk_init_data) { 1339 .name = "gcc_anoc_pcie4_1lane_m_clk", 1340 .parent_hws = (const struct clk_hw*[]) { 1341 &gcc_pcie4_axi_m_clk_src.clkr.hw, 1342 }, 1343 .num_parents = 1, 1344 .flags = CLK_SET_RATE_PARENT, 1345 .ops = &clk_branch2_ops, 1346 }, 1347 }, 1348 }; 1349 1350 static struct clk_branch gcc_anoc_pcie4_1lane_s_clk = { 1351 .halt_reg = 0x2e0dc, 1352 .halt_check = BRANCH_HALT, 1353 .clkr = { 1354 .enable_reg = 0x2e0dc, 1355 .enable_mask = BIT(0), 1356 .hw.init = &(const struct clk_init_data) { 1357 .name = "gcc_anoc_pcie4_1lane_s_clk", 1358 .parent_hws = (const struct clk_hw*[]) { 1359 &gcc_pcie4_axi_s_clk_src.clkr.hw, 1360 }, 1361 .num_parents = 1, 1362 .flags = CLK_SET_RATE_PARENT, 1363 .ops = &clk_branch2_ops, 1364 }, 1365 }, 1366 }; 1367 1368 static struct clk_branch gcc_cmn_12gpll_ahb_clk = { 1369 .halt_reg = 0x3a004, 1370 .halt_check = BRANCH_HALT, 1371 .clkr = { 1372 .enable_reg = 0x3a004, 1373 .enable_mask = BIT(0), 1374 .hw.init = &(const struct clk_init_data) { 1375 .name = "gcc_cmn_12gpll_ahb_clk", 1376 .parent_hws = (const struct clk_hw*[]) { 1377 &gcc_pcnoc_bfdcd_clk_src.clkr.hw, 1378 }, 1379 .num_parents = 1, 1380 .flags = CLK_SET_RATE_PARENT, 1381 .ops = &clk_branch2_ops, 1382 }, 1383 }, 1384 }; 1385 1386 static struct clk_branch gcc_cmn_12gpll_sys_clk = { 1387 .halt_reg = 0x3a008, 1388 .halt_check = BRANCH_HALT_VOTED, 1389 .clkr = { 1390 .enable_reg = 0x3a008, 1391 .enable_mask = BIT(0), 1392 .hw.init = &(const struct clk_init_data) { 1393 .name = "gcc_cmn_12gpll_sys_clk", 1394 .parent_hws = (const struct clk_hw*[]) { 1395 &gcc_uniphy_sys_clk_src.clkr.hw, 1396 }, 1397 .num_parents = 1, 1398 .flags = CLK_SET_RATE_PARENT, 1399 .ops = &clk_branch2_ops, 1400 }, 1401 }, 1402 }; 1403 1404 static struct clk_branch gcc_mdio_ahb_clk = { 1405 .halt_reg = 0x17040, 1406 .halt_check = BRANCH_HALT, 1407 .clkr = { 1408 .enable_reg = 0x17040, 1409 .enable_mask = BIT(0), 1410 .hw.init = &(const struct clk_init_data) { 1411 .name = "gcc_mdio_ahb_clk", 1412 .parent_hws = (const struct clk_hw*[]) { 1413 &gcc_pcnoc_bfdcd_clk_src.clkr.hw, 1414 }, 1415 .num_parents = 1, 1416 .flags = CLK_SET_RATE_PARENT, 1417 .ops = &clk_branch2_ops, 1418 }, 1419 }, 1420 }; 1421 1422 static struct clk_branch gcc_nss_ts_clk = { 1423 .halt_reg = 0x17018, 1424 .halt_check = BRANCH_HALT_VOTED, 1425 .clkr = { 1426 .enable_reg = 0x17018, 1427 .enable_mask = BIT(0), 1428 .hw.init = &(const struct clk_init_data) { 1429 .name = "gcc_nss_ts_clk", 1430 .parent_hws = (const struct clk_hw*[]) { 1431 &gcc_nss_ts_clk_src.clkr.hw, 1432 }, 1433 .num_parents = 1, 1434 .flags = CLK_SET_RATE_PARENT, 1435 .ops = &clk_branch2_ops, 1436 }, 1437 }, 1438 }; 1439 1440 static struct clk_branch gcc_nsscc_clk = { 1441 .halt_reg = 0x17034, 1442 .halt_check = BRANCH_HALT, 1443 .clkr = { 1444 .enable_reg = 0x17034, 1445 .enable_mask = BIT(0), 1446 .hw.init = &(const struct clk_init_data) { 1447 .name = "gcc_nsscc_clk", 1448 .parent_hws = (const struct clk_hw*[]) { 1449 &gcc_pcnoc_bfdcd_clk_src.clkr.hw, 1450 }, 1451 .num_parents = 1, 1452 .flags = CLK_SET_RATE_PARENT, 1453 .ops = &clk_branch2_ops, 1454 }, 1455 }, 1456 }; 1457 1458 static struct clk_branch gcc_nsscfg_clk = { 1459 .halt_reg = 0x1702c, 1460 .halt_check = BRANCH_HALT, 1461 .clkr = { 1462 .enable_reg = 0x1702c, 1463 .enable_mask = BIT(0), 1464 .hw.init = &(const struct clk_init_data) { 1465 .name = "gcc_nsscfg_clk", 1466 .parent_hws = (const struct clk_hw*[]) { 1467 &gcc_pcnoc_bfdcd_clk_src.clkr.hw, 1468 }, 1469 .num_parents = 1, 1470 .flags = CLK_SET_RATE_PARENT, 1471 .ops = &clk_branch2_ops, 1472 }, 1473 }, 1474 }; 1475 1476 static struct clk_branch gcc_nssnoc_atb_clk = { 1477 .halt_reg = 0x17014, 1478 .halt_check = BRANCH_HALT_VOTED, 1479 .clkr = { 1480 .enable_reg = 0x17014, 1481 .enable_mask = BIT(0), 1482 .hw.init = &(const struct clk_init_data) { 1483 .name = "gcc_nssnoc_atb_clk", 1484 .parent_hws = (const struct clk_hw*[]) { 1485 &gcc_qdss_at_clk_src.clkr.hw, 1486 }, 1487 .num_parents = 1, 1488 .flags = CLK_SET_RATE_PARENT, 1489 .ops = &clk_branch2_ops, 1490 }, 1491 }, 1492 }; 1493 1494 static struct clk_branch gcc_nssnoc_memnoc_1_clk = { 1495 .halt_reg = 0x17084, 1496 .halt_check = BRANCH_HALT, 1497 .clkr = { 1498 .enable_reg = 0x17084, 1499 .enable_mask = BIT(0), 1500 .hw.init = &(const struct clk_init_data) { 1501 .name = "gcc_nssnoc_memnoc_1_clk", 1502 .parent_hws = (const struct clk_hw*[]) { 1503 &gcc_nssnoc_memnoc_div_clk_src.clkr.hw, 1504 }, 1505 .num_parents = 1, 1506 .flags = CLK_SET_RATE_PARENT, 1507 .ops = &clk_branch2_ops, 1508 }, 1509 }, 1510 }; 1511 1512 static struct clk_branch gcc_nssnoc_memnoc_clk = { 1513 .halt_reg = 0x17024, 1514 .halt_check = BRANCH_HALT, 1515 .clkr = { 1516 .enable_reg = 0x17024, 1517 .enable_mask = BIT(0), 1518 .hw.init = &(const struct clk_init_data) { 1519 .name = "gcc_nssnoc_memnoc_clk", 1520 .parent_hws = (const struct clk_hw*[]) { 1521 &gcc_nssnoc_memnoc_div_clk_src.clkr.hw, 1522 }, 1523 .num_parents = 1, 1524 .flags = CLK_SET_RATE_PARENT, 1525 .ops = &clk_branch2_ops, 1526 }, 1527 }, 1528 }; 1529 1530 static struct clk_branch gcc_nssnoc_nsscc_clk = { 1531 .halt_reg = 0x17030, 1532 .halt_check = BRANCH_HALT, 1533 .clkr = { 1534 .enable_reg = 0x17030, 1535 .enable_mask = BIT(0), 1536 .hw.init = &(const struct clk_init_data) { 1537 .name = "gcc_nssnoc_nsscc_clk", 1538 .parent_hws = (const struct clk_hw*[]) { 1539 &gcc_pcnoc_bfdcd_clk_src.clkr.hw, 1540 }, 1541 .num_parents = 1, 1542 .flags = CLK_SET_RATE_PARENT, 1543 .ops = &clk_branch2_ops, 1544 }, 1545 }, 1546 }; 1547 1548 static struct clk_branch gcc_nssnoc_pcnoc_1_clk = { 1549 .halt_reg = 0x17080, 1550 .halt_check = BRANCH_HALT, 1551 .clkr = { 1552 .enable_reg = 0x17080, 1553 .enable_mask = BIT(0), 1554 .hw.init = &(const struct clk_init_data) { 1555 .name = "gcc_nssnoc_pcnoc_1_clk", 1556 .parent_hws = (const struct clk_hw*[]) { 1557 &gcc_pcnoc_bfdcd_clk_src.clkr.hw, 1558 }, 1559 .num_parents = 1, 1560 .flags = CLK_SET_RATE_PARENT, 1561 .ops = &clk_branch2_ops, 1562 }, 1563 }, 1564 }; 1565 1566 static struct clk_branch gcc_nssnoc_qosgen_ref_clk = { 1567 .halt_reg = 0x1701c, 1568 .halt_check = BRANCH_HALT, 1569 .clkr = { 1570 .enable_reg = 0x1701c, 1571 .enable_mask = BIT(0), 1572 .hw.init = &(const struct clk_init_data) { 1573 .name = "gcc_nssnoc_qosgen_ref_clk", 1574 .parent_hws = (const struct clk_hw *[]) { 1575 &gcc_xo_div4_clk_src.hw 1576 }, 1577 .num_parents = 1, 1578 .flags = CLK_SET_RATE_PARENT, 1579 .ops = &clk_branch2_ops, 1580 }, 1581 }, 1582 }; 1583 1584 static struct clk_branch gcc_nssnoc_snoc_1_clk = { 1585 .halt_reg = 0x1707c, 1586 .halt_check = BRANCH_HALT, 1587 .clkr = { 1588 .enable_reg = 0x1707c, 1589 .enable_mask = BIT(0), 1590 .hw.init = &(const struct clk_init_data) { 1591 .name = "gcc_nssnoc_snoc_1_clk", 1592 .parent_hws = (const struct clk_hw*[]) { 1593 &gcc_system_noc_bfdcd_clk_src.clkr.hw 1594 }, 1595 .num_parents = 1, 1596 .flags = CLK_SET_RATE_PARENT, 1597 .ops = &clk_branch2_ops, 1598 }, 1599 }, 1600 }; 1601 1602 static struct clk_branch gcc_nssnoc_snoc_clk = { 1603 .halt_reg = 0x17028, 1604 .halt_check = BRANCH_HALT, 1605 .clkr = { 1606 .enable_reg = 0x17028, 1607 .enable_mask = BIT(0), 1608 .hw.init = &(const struct clk_init_data) { 1609 .name = "gcc_nssnoc_snoc_clk", 1610 .parent_hws = (const struct clk_hw*[]) { 1611 &gcc_system_noc_bfdcd_clk_src.clkr.hw 1612 }, 1613 .num_parents = 1, 1614 .flags = CLK_SET_RATE_PARENT, 1615 .ops = &clk_branch2_ops, 1616 }, 1617 }, 1618 }; 1619 1620 static struct clk_branch gcc_nssnoc_timeout_ref_clk = { 1621 .halt_reg = 0x17020, 1622 .halt_check = BRANCH_HALT, 1623 .clkr = { 1624 .enable_reg = 0x17020, 1625 .enable_mask = BIT(0), 1626 .hw.init = &(const struct clk_init_data) { 1627 .name = "gcc_nssnoc_timeout_ref_clk", 1628 .parent_hws = (const struct clk_hw*[]) { 1629 &gcc_xo_div4_clk_src.hw, 1630 }, 1631 .num_parents = 1, 1632 .flags = CLK_SET_RATE_PARENT, 1633 .ops = &clk_branch2_ops, 1634 }, 1635 }, 1636 }; 1637 1638 static struct clk_branch gcc_nssnoc_xo_dcd_clk = { 1639 .halt_reg = 0x17074, 1640 .halt_check = BRANCH_HALT, 1641 .clkr = { 1642 .enable_reg = 0x17074, 1643 .enable_mask = BIT(0), 1644 .hw.init = &(const struct clk_init_data) { 1645 .name = "gcc_nssnoc_xo_dcd_clk", 1646 .parent_hws = (const struct clk_hw*[]) { 1647 &gcc_xo_clk_src.clkr.hw, 1648 }, 1649 .num_parents = 1, 1650 .flags = CLK_SET_RATE_PARENT, 1651 .ops = &clk_branch2_ops, 1652 }, 1653 }, 1654 }; 1655 1656 static struct clk_branch gcc_pcie0_ahb_clk = { 1657 .halt_reg = 0x28030, 1658 .halt_check = BRANCH_HALT, 1659 .clkr = { 1660 .enable_reg = 0x28030, 1661 .enable_mask = BIT(0), 1662 .hw.init = &(const struct clk_init_data) { 1663 .name = "gcc_pcie0_ahb_clk", 1664 .parent_hws = (const struct clk_hw*[]) { 1665 &gcc_pcnoc_bfdcd_clk_src.clkr.hw, 1666 }, 1667 .num_parents = 1, 1668 .flags = CLK_SET_RATE_PARENT, 1669 .ops = &clk_branch2_ops, 1670 }, 1671 }, 1672 }; 1673 1674 static struct clk_branch gcc_pcie0_aux_clk = { 1675 .halt_reg = 0x28070, 1676 .halt_check = BRANCH_HALT, 1677 .clkr = { 1678 .enable_reg = 0x28070, 1679 .enable_mask = BIT(0), 1680 .hw.init = &(const struct clk_init_data) { 1681 .name = "gcc_pcie0_aux_clk", 1682 .parent_hws = (const struct clk_hw*[]) { 1683 &gcc_pcie_aux_clk_src.clkr.hw, 1684 }, 1685 .num_parents = 1, 1686 .flags = CLK_SET_RATE_PARENT, 1687 .ops = &clk_branch2_ops, 1688 }, 1689 }, 1690 }; 1691 1692 static struct clk_branch gcc_pcie0_axi_m_clk = { 1693 .halt_reg = 0x28038, 1694 .halt_check = BRANCH_HALT, 1695 .clkr = { 1696 .enable_reg = 0x28038, 1697 .enable_mask = BIT(0), 1698 .hw.init = &(const struct clk_init_data) { 1699 .name = "gcc_pcie0_axi_m_clk", 1700 .parent_hws = (const struct clk_hw*[]) { 1701 &gcc_pcie0_axi_m_clk_src.clkr.hw, 1702 }, 1703 .num_parents = 1, 1704 .flags = CLK_SET_RATE_PARENT, 1705 .ops = &clk_branch2_ops, 1706 }, 1707 }, 1708 }; 1709 1710 static struct clk_branch gcc_pcie0_axi_s_bridge_clk = { 1711 .halt_reg = 0x28048, 1712 .halt_check = BRANCH_HALT, 1713 .clkr = { 1714 .enable_reg = 0x28048, 1715 .enable_mask = BIT(0), 1716 .hw.init = &(const struct clk_init_data) { 1717 .name = "gcc_pcie0_axi_s_bridge_clk", 1718 .parent_hws = (const struct clk_hw*[]) { 1719 &gcc_pcie0_axi_s_clk_src.clkr.hw, 1720 }, 1721 .num_parents = 1, 1722 .flags = CLK_SET_RATE_PARENT, 1723 .ops = &clk_branch2_ops, 1724 }, 1725 }, 1726 }; 1727 1728 static struct clk_branch gcc_pcie0_axi_s_clk = { 1729 .halt_reg = 0x28040, 1730 .halt_check = BRANCH_HALT, 1731 .clkr = { 1732 .enable_reg = 0x28040, 1733 .enable_mask = BIT(0), 1734 .hw.init = &(const struct clk_init_data) { 1735 .name = "gcc_pcie0_axi_s_clk", 1736 .parent_hws = (const struct clk_hw*[]) { 1737 &gcc_pcie0_axi_s_clk_src.clkr.hw, 1738 }, 1739 .num_parents = 1, 1740 .flags = CLK_SET_RATE_PARENT, 1741 .ops = &clk_branch2_ops, 1742 }, 1743 }, 1744 }; 1745 1746 static struct clk_regmap_phy_mux gcc_pcie0_pipe_clk_src = { 1747 .reg = 0x28064, 1748 .clkr = { 1749 .hw.init = &(const struct clk_init_data) { 1750 .name = "pcie0_pipe_clk_src", 1751 .parent_data = &(const struct clk_parent_data) { 1752 .index = DT_PCIE30_PHY0_PIPE_CLK, 1753 }, 1754 .num_parents = 1, 1755 .ops = &clk_regmap_phy_mux_ops, 1756 }, 1757 }, 1758 }; 1759 1760 static struct clk_branch gcc_pcie0_pipe_clk = { 1761 .halt_reg = 0x28068, 1762 .halt_check = BRANCH_HALT_DELAY, 1763 .clkr = { 1764 .enable_reg = 0x28068, 1765 .enable_mask = BIT(0), 1766 .hw.init = &(const struct clk_init_data) { 1767 .name = "gcc_pcie0_pipe_clk", 1768 .parent_hws = (const struct clk_hw *[]) { 1769 &gcc_pcie0_pipe_clk_src.clkr.hw 1770 }, 1771 .num_parents = 1, 1772 .flags = CLK_SET_RATE_PARENT, 1773 .ops = &clk_branch2_ops, 1774 }, 1775 }, 1776 }; 1777 1778 static struct clk_branch gcc_pcie1_ahb_clk = { 1779 .halt_reg = 0x29030, 1780 .halt_check = BRANCH_HALT, 1781 .clkr = { 1782 .enable_reg = 0x29030, 1783 .enable_mask = BIT(0), 1784 .hw.init = &(const struct clk_init_data) { 1785 .name = "gcc_pcie1_ahb_clk", 1786 .parent_hws = (const struct clk_hw*[]) { 1787 &gcc_pcnoc_bfdcd_clk_src.clkr.hw, 1788 }, 1789 .num_parents = 1, 1790 .flags = CLK_SET_RATE_PARENT, 1791 .ops = &clk_branch2_ops, 1792 }, 1793 }, 1794 }; 1795 1796 static struct clk_branch gcc_pcie1_aux_clk = { 1797 .halt_reg = 0x29074, 1798 .halt_check = BRANCH_HALT, 1799 .clkr = { 1800 .enable_reg = 0x29074, 1801 .enable_mask = BIT(0), 1802 .hw.init = &(const struct clk_init_data) { 1803 .name = "gcc_pcie1_aux_clk", 1804 .parent_hws = (const struct clk_hw*[]) { 1805 &gcc_pcie_aux_clk_src.clkr.hw, 1806 }, 1807 .num_parents = 1, 1808 .flags = CLK_SET_RATE_PARENT, 1809 .ops = &clk_branch2_ops, 1810 }, 1811 }, 1812 }; 1813 1814 static struct clk_branch gcc_pcie1_axi_m_clk = { 1815 .halt_reg = 0x29038, 1816 .halt_check = BRANCH_HALT, 1817 .clkr = { 1818 .enable_reg = 0x29038, 1819 .enable_mask = BIT(0), 1820 .hw.init = &(const struct clk_init_data) { 1821 .name = "gcc_pcie1_axi_m_clk", 1822 .parent_hws = (const struct clk_hw*[]) { 1823 &gcc_pcie1_axi_m_clk_src.clkr.hw, 1824 }, 1825 .num_parents = 1, 1826 .flags = CLK_SET_RATE_PARENT, 1827 .ops = &clk_branch2_ops, 1828 }, 1829 }, 1830 }; 1831 1832 static struct clk_branch gcc_pcie1_axi_s_bridge_clk = { 1833 .halt_reg = 0x29048, 1834 .halt_check = BRANCH_HALT, 1835 .clkr = { 1836 .enable_reg = 0x29048, 1837 .enable_mask = BIT(0), 1838 .hw.init = &(const struct clk_init_data) { 1839 .name = "gcc_pcie1_axi_s_bridge_clk", 1840 .parent_hws = (const struct clk_hw*[]) { 1841 &gcc_pcie1_axi_s_clk_src.clkr.hw, 1842 }, 1843 .num_parents = 1, 1844 .flags = CLK_SET_RATE_PARENT, 1845 .ops = &clk_branch2_ops, 1846 }, 1847 }, 1848 }; 1849 1850 static struct clk_branch gcc_pcie1_axi_s_clk = { 1851 .halt_reg = 0x29040, 1852 .halt_check = BRANCH_HALT, 1853 .clkr = { 1854 .enable_reg = 0x29040, 1855 .enable_mask = BIT(0), 1856 .hw.init = &(const struct clk_init_data) { 1857 .name = "gcc_pcie1_axi_s_clk", 1858 .parent_hws = (const struct clk_hw*[]) { 1859 &gcc_pcie1_axi_s_clk_src.clkr.hw, 1860 }, 1861 .num_parents = 1, 1862 .flags = CLK_SET_RATE_PARENT, 1863 .ops = &clk_branch2_ops, 1864 }, 1865 }, 1866 }; 1867 1868 static struct clk_regmap_phy_mux gcc_pcie1_pipe_clk_src = { 1869 .reg = 0x29064, 1870 .clkr = { 1871 .hw.init = &(const struct clk_init_data) { 1872 .name = "pcie1_pipe_clk_src", 1873 .parent_data = &(const struct clk_parent_data) { 1874 .index = DT_PCIE30_PHY1_PIPE_CLK, 1875 }, 1876 .num_parents = 1, 1877 .ops = &clk_regmap_phy_mux_ops, 1878 }, 1879 }, 1880 }; 1881 1882 static struct clk_branch gcc_pcie1_pipe_clk = { 1883 .halt_reg = 0x29068, 1884 .halt_check = BRANCH_HALT_DELAY, 1885 .clkr = { 1886 .enable_reg = 0x29068, 1887 .enable_mask = BIT(0), 1888 .hw.init = &(const struct clk_init_data) { 1889 .name = "gcc_pcie1_pipe_clk", 1890 .parent_hws = (const struct clk_hw *[]) { 1891 &gcc_pcie1_pipe_clk_src.clkr.hw 1892 }, 1893 .num_parents = 1, 1894 .flags = CLK_SET_RATE_PARENT, 1895 .ops = &clk_branch2_ops, 1896 }, 1897 }, 1898 }; 1899 1900 static struct clk_branch gcc_pcie2_ahb_clk = { 1901 .halt_reg = 0x2a030, 1902 .halt_check = BRANCH_HALT, 1903 .clkr = { 1904 .enable_reg = 0x2a030, 1905 .enable_mask = BIT(0), 1906 .hw.init = &(const struct clk_init_data) { 1907 .name = "gcc_pcie2_ahb_clk", 1908 .parent_hws = (const struct clk_hw*[]) { 1909 &gcc_pcnoc_bfdcd_clk_src.clkr.hw, 1910 }, 1911 .num_parents = 1, 1912 .flags = CLK_SET_RATE_PARENT, 1913 .ops = &clk_branch2_ops, 1914 }, 1915 }, 1916 }; 1917 1918 static struct clk_branch gcc_pcie2_aux_clk = { 1919 .halt_reg = 0x2a078, 1920 .halt_check = BRANCH_HALT, 1921 .clkr = { 1922 .enable_reg = 0x2a078, 1923 .enable_mask = BIT(0), 1924 .hw.init = &(const struct clk_init_data) { 1925 .name = "gcc_pcie2_aux_clk", 1926 .parent_hws = (const struct clk_hw*[]) { 1927 &gcc_pcie_aux_clk_src.clkr.hw, 1928 }, 1929 .num_parents = 1, 1930 .flags = CLK_SET_RATE_PARENT, 1931 .ops = &clk_branch2_ops, 1932 }, 1933 }, 1934 }; 1935 1936 static struct clk_branch gcc_pcie2_axi_m_clk = { 1937 .halt_reg = 0x2a038, 1938 .halt_check = BRANCH_HALT, 1939 .clkr = { 1940 .enable_reg = 0x2a038, 1941 .enable_mask = BIT(0), 1942 .hw.init = &(const struct clk_init_data) { 1943 .name = "gcc_pcie2_axi_m_clk", 1944 .parent_hws = (const struct clk_hw*[]) { 1945 &gcc_pcie2_axi_m_clk_src.clkr.hw, 1946 }, 1947 .num_parents = 1, 1948 .flags = CLK_SET_RATE_PARENT, 1949 .ops = &clk_branch2_ops, 1950 }, 1951 }, 1952 }; 1953 1954 static struct clk_branch gcc_pcie2_axi_s_bridge_clk = { 1955 .halt_reg = 0x2a048, 1956 .halt_check = BRANCH_HALT, 1957 .clkr = { 1958 .enable_reg = 0x2a048, 1959 .enable_mask = BIT(0), 1960 .hw.init = &(const struct clk_init_data) { 1961 .name = "gcc_pcie2_axi_s_bridge_clk", 1962 .parent_hws = (const struct clk_hw*[]) { 1963 &gcc_pcie2_axi_s_clk_src.clkr.hw, 1964 }, 1965 .num_parents = 1, 1966 .flags = CLK_SET_RATE_PARENT, 1967 .ops = &clk_branch2_ops, 1968 }, 1969 }, 1970 }; 1971 1972 static struct clk_branch gcc_pcie2_axi_s_clk = { 1973 .halt_reg = 0x2a040, 1974 .halt_check = BRANCH_HALT, 1975 .clkr = { 1976 .enable_reg = 0x2a040, 1977 .enable_mask = BIT(0), 1978 .hw.init = &(const struct clk_init_data) { 1979 .name = "gcc_pcie2_axi_s_clk", 1980 .parent_hws = (const struct clk_hw*[]) { 1981 &gcc_pcie2_axi_s_clk_src.clkr.hw, 1982 }, 1983 .num_parents = 1, 1984 .flags = CLK_SET_RATE_PARENT, 1985 .ops = &clk_branch2_ops, 1986 }, 1987 }, 1988 }; 1989 1990 static struct clk_regmap_phy_mux gcc_pcie2_pipe_clk_src = { 1991 .reg = 0x2a064, 1992 .clkr = { 1993 .hw.init = &(const struct clk_init_data) { 1994 .name = "pcie2_pipe_clk_src", 1995 .parent_data = &(const struct clk_parent_data) { 1996 .index = DT_PCIE30_PHY2_PIPE_CLK, 1997 }, 1998 .num_parents = 1, 1999 .ops = &clk_regmap_phy_mux_ops, 2000 }, 2001 }, 2002 }; 2003 2004 static struct clk_branch gcc_pcie2_pipe_clk = { 2005 .halt_reg = 0x2a068, 2006 .halt_check = BRANCH_HALT_DELAY, 2007 .clkr = { 2008 .enable_reg = 0x2a068, 2009 .enable_mask = BIT(0), 2010 .hw.init = &(const struct clk_init_data) { 2011 .name = "gcc_pcie2_pipe_clk", 2012 .parent_hws = (const struct clk_hw *[]) { 2013 &gcc_pcie2_pipe_clk_src.clkr.hw 2014 }, 2015 .num_parents = 1, 2016 .flags = CLK_SET_RATE_PARENT, 2017 .ops = &clk_branch2_ops, 2018 }, 2019 }, 2020 }; 2021 2022 static struct clk_branch gcc_pcie3_ahb_clk = { 2023 .halt_reg = 0x2b030, 2024 .halt_check = BRANCH_HALT, 2025 .clkr = { 2026 .enable_reg = 0x2b030, 2027 .enable_mask = BIT(0), 2028 .hw.init = &(const struct clk_init_data) { 2029 .name = "gcc_pcie3_ahb_clk", 2030 .parent_hws = (const struct clk_hw*[]) { 2031 &gcc_pcnoc_bfdcd_clk_src.clkr.hw, 2032 }, 2033 .num_parents = 1, 2034 .flags = CLK_SET_RATE_PARENT, 2035 .ops = &clk_branch2_ops, 2036 }, 2037 }, 2038 }; 2039 2040 static struct clk_branch gcc_pcie3_aux_clk = { 2041 .halt_reg = 0x2b07c, 2042 .halt_check = BRANCH_HALT, 2043 .clkr = { 2044 .enable_reg = 0x2b07c, 2045 .enable_mask = BIT(0), 2046 .hw.init = &(const struct clk_init_data) { 2047 .name = "gcc_pcie3_aux_clk", 2048 .parent_hws = (const struct clk_hw*[]) { 2049 &gcc_pcie_aux_clk_src.clkr.hw, 2050 }, 2051 .num_parents = 1, 2052 .flags = CLK_SET_RATE_PARENT, 2053 .ops = &clk_branch2_ops, 2054 }, 2055 }, 2056 }; 2057 2058 static struct clk_branch gcc_pcie3_axi_m_clk = { 2059 .halt_reg = 0x2b038, 2060 .halt_check = BRANCH_HALT, 2061 .clkr = { 2062 .enable_reg = 0x2b038, 2063 .enable_mask = BIT(0), 2064 .hw.init = &(const struct clk_init_data) { 2065 .name = "gcc_pcie3_axi_m_clk", 2066 .parent_hws = (const struct clk_hw*[]) { 2067 &gcc_pcie3_axi_m_clk_src.clkr.hw, 2068 }, 2069 .num_parents = 1, 2070 .flags = CLK_SET_RATE_PARENT, 2071 .ops = &clk_branch2_ops, 2072 }, 2073 }, 2074 }; 2075 2076 static struct clk_branch gcc_pcie3_axi_s_bridge_clk = { 2077 .halt_reg = 0x2b048, 2078 .halt_check = BRANCH_HALT, 2079 .clkr = { 2080 .enable_reg = 0x2b048, 2081 .enable_mask = BIT(0), 2082 .hw.init = &(const struct clk_init_data) { 2083 .name = "gcc_pcie3_axi_s_bridge_clk", 2084 .parent_hws = (const struct clk_hw*[]) { 2085 &gcc_pcie3_axi_s_clk_src.clkr.hw, 2086 }, 2087 .num_parents = 1, 2088 .flags = CLK_SET_RATE_PARENT, 2089 .ops = &clk_branch2_ops, 2090 }, 2091 }, 2092 }; 2093 2094 static struct clk_branch gcc_pcie3_axi_s_clk = { 2095 .halt_reg = 0x2b040, 2096 .halt_check = BRANCH_HALT, 2097 .clkr = { 2098 .enable_reg = 0x2b040, 2099 .enable_mask = BIT(0), 2100 .hw.init = &(const struct clk_init_data) { 2101 .name = "gcc_pcie3_axi_s_clk", 2102 .parent_hws = (const struct clk_hw*[]) { 2103 &gcc_pcie3_axi_s_clk_src.clkr.hw, 2104 }, 2105 .num_parents = 1, 2106 .flags = CLK_SET_RATE_PARENT, 2107 .ops = &clk_branch2_ops, 2108 }, 2109 }, 2110 }; 2111 2112 static struct clk_regmap_phy_mux gcc_pcie3_pipe_clk_src = { 2113 .reg = 0x2b064, 2114 .clkr = { 2115 .hw.init = &(const struct clk_init_data) { 2116 .name = "pcie3_pipe_clk_src", 2117 .parent_data = &(const struct clk_parent_data) { 2118 .index = DT_PCIE30_PHY3_PIPE_CLK, 2119 }, 2120 .num_parents = 1, 2121 .ops = &clk_regmap_phy_mux_ops, 2122 }, 2123 }, 2124 }; 2125 2126 static struct clk_branch gcc_pcie3_pipe_clk = { 2127 .halt_reg = 0x2b068, 2128 .halt_check = BRANCH_HALT_DELAY, 2129 .clkr = { 2130 .enable_reg = 0x2b068, 2131 .enable_mask = BIT(0), 2132 .hw.init = &(const struct clk_init_data) { 2133 .name = "gcc_pcie3_pipe_clk", 2134 .parent_hws = (const struct clk_hw *[]) { 2135 &gcc_pcie3_pipe_clk_src.clkr.hw 2136 }, 2137 .num_parents = 1, 2138 .flags = CLK_SET_RATE_PARENT, 2139 .ops = &clk_branch2_ops, 2140 }, 2141 }, 2142 }; 2143 2144 static struct clk_branch gcc_pcie4_ahb_clk = { 2145 .halt_reg = 0x2501c, 2146 .halt_check = BRANCH_HALT, 2147 .clkr = { 2148 .enable_reg = 0x2501c, 2149 .enable_mask = BIT(0), 2150 .hw.init = &(const struct clk_init_data) { 2151 .name = "gcc_pcie4_ahb_clk", 2152 .parent_hws = (const struct clk_hw*[]) { 2153 &gcc_pcnoc_bfdcd_clk_src.clkr.hw, 2154 }, 2155 .num_parents = 1, 2156 .flags = CLK_SET_RATE_PARENT, 2157 .ops = &clk_branch2_ops, 2158 }, 2159 }, 2160 }; 2161 2162 static struct clk_branch gcc_pcie4_aux_clk = { 2163 .halt_reg = 0x25020, 2164 .halt_check = BRANCH_HALT, 2165 .clkr = { 2166 .enable_reg = 0x25020, 2167 .enable_mask = BIT(0), 2168 .hw.init = &(const struct clk_init_data) { 2169 .name = "gcc_pcie4_aux_clk", 2170 .parent_hws = (const struct clk_hw*[]) { 2171 &gcc_pcie_aux_clk_src.clkr.hw, 2172 }, 2173 .num_parents = 1, 2174 .flags = CLK_SET_RATE_PARENT, 2175 .ops = &clk_branch2_ops, 2176 }, 2177 }, 2178 }; 2179 2180 static struct clk_branch gcc_pcie4_axi_m_clk = { 2181 .halt_reg = 0x25028, 2182 .halt_check = BRANCH_HALT, 2183 .clkr = { 2184 .enable_reg = 0x25028, 2185 .enable_mask = BIT(0), 2186 .hw.init = &(const struct clk_init_data) { 2187 .name = "gcc_pcie4_axi_m_clk", 2188 .parent_hws = (const struct clk_hw*[]) { 2189 &gcc_pcie4_axi_m_clk_src.clkr.hw, 2190 }, 2191 .num_parents = 1, 2192 .flags = CLK_SET_RATE_PARENT, 2193 .ops = &clk_branch2_ops, 2194 }, 2195 }, 2196 }; 2197 2198 static struct clk_branch gcc_pcie4_axi_s_bridge_clk = { 2199 .halt_reg = 0x25038, 2200 .halt_check = BRANCH_HALT, 2201 .clkr = { 2202 .enable_reg = 0x25038, 2203 .enable_mask = BIT(0), 2204 .hw.init = &(const struct clk_init_data) { 2205 .name = "gcc_pcie4_axi_s_bridge_clk", 2206 .parent_hws = (const struct clk_hw*[]) { 2207 &gcc_pcie4_axi_s_clk_src.clkr.hw, 2208 }, 2209 .num_parents = 1, 2210 .flags = CLK_SET_RATE_PARENT, 2211 .ops = &clk_branch2_ops, 2212 }, 2213 }, 2214 }; 2215 2216 static struct clk_branch gcc_pcie4_axi_s_clk = { 2217 .halt_reg = 0x25030, 2218 .halt_check = BRANCH_HALT, 2219 .clkr = { 2220 .enable_reg = 0x25030, 2221 .enable_mask = BIT(0), 2222 .hw.init = &(const struct clk_init_data) { 2223 .name = "gcc_pcie4_axi_s_clk", 2224 .parent_hws = (const struct clk_hw*[]) { 2225 &gcc_pcie4_axi_s_clk_src.clkr.hw, 2226 }, 2227 .num_parents = 1, 2228 .flags = CLK_SET_RATE_PARENT, 2229 .ops = &clk_branch2_ops, 2230 }, 2231 }, 2232 }; 2233 2234 static struct clk_regmap_phy_mux gcc_pcie4_pipe_clk_src = { 2235 .reg = 0x25058, 2236 .clkr = { 2237 .hw.init = &(const struct clk_init_data) { 2238 .name = "pcie4_pipe_clk_src", 2239 .parent_data = &(const struct clk_parent_data) { 2240 .index = DT_PCIE30_PHY4_PIPE_CLK, 2241 }, 2242 .num_parents = 1, 2243 .ops = &clk_regmap_phy_mux_ops, 2244 }, 2245 }, 2246 }; 2247 2248 static struct clk_branch gcc_pcie4_pipe_clk = { 2249 .halt_reg = 0x2503c, 2250 .halt_check = BRANCH_HALT_DELAY, 2251 .clkr = { 2252 .enable_reg = 0x2503c, 2253 .enable_mask = BIT(0), 2254 .hw.init = &(const struct clk_init_data) { 2255 .name = "gcc_pcie4_pipe_clk", 2256 .parent_hws = (const struct clk_hw *[]) { 2257 &gcc_pcie4_pipe_clk_src.clkr.hw 2258 }, 2259 .num_parents = 1, 2260 .flags = CLK_SET_RATE_PARENT, 2261 .ops = &clk_branch2_ops, 2262 }, 2263 }, 2264 }; 2265 2266 static struct clk_branch gcc_pcie0_rchng_clk = { 2267 .halt_reg = 0x28028, 2268 .clkr = { 2269 .enable_reg = 0x28028, 2270 .enable_mask = BIT(1), 2271 .hw.init = &(const struct clk_init_data) { 2272 .name = "gcc_pcie0_rchng_clk", 2273 .parent_hws = (const struct clk_hw *[]) { 2274 &gcc_pcie0_rchng_clk_src.clkr.hw 2275 }, 2276 .num_parents = 1, 2277 .flags = CLK_SET_RATE_PARENT, 2278 .ops = &clk_branch2_ops, 2279 }, 2280 }, 2281 }; 2282 2283 static struct clk_branch gcc_pcie1_rchng_clk = { 2284 .halt_reg = 0x29028, 2285 .clkr = { 2286 .enable_reg = 0x29028, 2287 .enable_mask = BIT(1), 2288 .hw.init = &(const struct clk_init_data) { 2289 .name = "gcc_pcie1_rchng_clk", 2290 .parent_hws = (const struct clk_hw *[]) { 2291 &gcc_pcie1_rchng_clk_src.clkr.hw 2292 }, 2293 .num_parents = 1, 2294 .flags = CLK_SET_RATE_PARENT, 2295 .ops = &clk_branch2_ops, 2296 }, 2297 }, 2298 }; 2299 2300 static struct clk_branch gcc_pcie2_rchng_clk = { 2301 .halt_reg = 0x2a028, 2302 .clkr = { 2303 .enable_reg = 0x2a028, 2304 .enable_mask = BIT(1), 2305 .hw.init = &(const struct clk_init_data) { 2306 .name = "gcc_pcie2_rchng_clk", 2307 .parent_hws = (const struct clk_hw *[]) { 2308 &gcc_pcie2_rchng_clk_src.clkr.hw 2309 }, 2310 .num_parents = 1, 2311 .flags = CLK_SET_RATE_PARENT, 2312 .ops = &clk_branch2_ops, 2313 }, 2314 }, 2315 }; 2316 2317 static struct clk_branch gcc_pcie3_rchng_clk = { 2318 .halt_reg = 0x2b028, 2319 .clkr = { 2320 .enable_reg = 0x2b028, 2321 .enable_mask = BIT(1), 2322 .hw.init = &(const struct clk_init_data) { 2323 .name = "gcc_pcie3_rchng_clk", 2324 .parent_hws = (const struct clk_hw *[]) { 2325 &gcc_pcie3_rchng_clk_src.clkr.hw 2326 }, 2327 .num_parents = 1, 2328 .flags = CLK_SET_RATE_PARENT, 2329 .ops = &clk_branch2_ops, 2330 }, 2331 }, 2332 }; 2333 2334 static struct clk_branch gcc_pcie4_rchng_clk = { 2335 .halt_reg = 0x25014, 2336 .clkr = { 2337 .enable_reg = 0x25014, 2338 .enable_mask = BIT(1), 2339 .hw.init = &(const struct clk_init_data) { 2340 .name = "gcc_pcie4_rchng_clk", 2341 .parent_hws = (const struct clk_hw *[]) { 2342 &gcc_pcie4_rchng_clk_src.clkr.hw 2343 }, 2344 .num_parents = 1, 2345 .flags = CLK_SET_RATE_PARENT, 2346 .ops = &clk_branch2_ops, 2347 }, 2348 }, 2349 }; 2350 2351 static struct clk_branch gcc_qdss_at_clk = { 2352 .halt_reg = 0x2d034, 2353 .halt_check = BRANCH_HALT_VOTED, 2354 .clkr = { 2355 .enable_reg = 0x2d034, 2356 .enable_mask = BIT(0), 2357 .hw.init = &(const struct clk_init_data) { 2358 .name = "gcc_qdss_at_clk", 2359 .parent_hws = (const struct clk_hw*[]) { 2360 &gcc_qdss_at_clk_src.clkr.hw, 2361 }, 2362 .num_parents = 1, 2363 .flags = CLK_SET_RATE_PARENT, 2364 .ops = &clk_branch2_ops, 2365 }, 2366 }, 2367 }; 2368 2369 static struct clk_branch gcc_qdss_dap_clk = { 2370 .halt_reg = 0x2d058, 2371 .halt_check = BRANCH_HALT_VOTED, 2372 .clkr = { 2373 .enable_reg = 0xb004, 2374 .enable_mask = BIT(2), 2375 .hw.init = &(const struct clk_init_data) { 2376 .name = "gcc_qdss_dap_clk", 2377 .parent_hws = (const struct clk_hw*[]) { 2378 &gcc_qdss_dap_sync_clk_src.hw 2379 }, 2380 .num_parents = 1, 2381 .flags = CLK_SET_RATE_PARENT, 2382 .ops = &clk_branch2_ops, 2383 }, 2384 }, 2385 }; 2386 2387 static struct clk_branch gcc_qpic_ahb_clk = { 2388 .halt_reg = 0x32010, 2389 .halt_check = BRANCH_HALT, 2390 .clkr = { 2391 .enable_reg = 0x32010, 2392 .enable_mask = BIT(0), 2393 .hw.init = &(const struct clk_init_data) { 2394 .name = "gcc_qpic_ahb_clk", 2395 .parent_hws = (const struct clk_hw*[]) { 2396 &gcc_pcnoc_bfdcd_clk_src.clkr.hw, 2397 }, 2398 .num_parents = 1, 2399 .flags = CLK_SET_RATE_PARENT, 2400 .ops = &clk_branch2_ops, 2401 }, 2402 }, 2403 }; 2404 2405 static struct clk_branch gcc_qpic_clk = { 2406 .halt_reg = 0x32028, 2407 .halt_check = BRANCH_HALT, 2408 .clkr = { 2409 .enable_reg = 0x32028, 2410 .enable_mask = BIT(0), 2411 .hw.init = &(const struct clk_init_data) { 2412 .name = "gcc_qpic_clk", 2413 .parent_hws = (const struct clk_hw*[]) { 2414 &gcc_qpic_clk_src.clkr.hw, 2415 }, 2416 .num_parents = 1, 2417 .flags = CLK_SET_RATE_PARENT, 2418 .ops = &clk_branch2_ops, 2419 }, 2420 }, 2421 }; 2422 2423 static struct clk_branch gcc_qpic_io_macro_clk = { 2424 .halt_reg = 0x3200c, 2425 .halt_check = BRANCH_HALT, 2426 .clkr = { 2427 .enable_reg = 0x3200c, 2428 .enable_mask = BIT(0), 2429 .hw.init = &(const struct clk_init_data) { 2430 .name = "gcc_qpic_io_macro_clk", 2431 .parent_hws = (const struct clk_hw*[]) { 2432 &gcc_qpic_io_macro_clk_src.clkr.hw, 2433 }, 2434 .num_parents = 1, 2435 .flags = CLK_SET_RATE_PARENT, 2436 .ops = &clk_branch2_ops, 2437 }, 2438 }, 2439 }; 2440 2441 static struct clk_branch gcc_qpic_sleep_clk = { 2442 .halt_reg = 0x32018, 2443 .halt_check = BRANCH_HALT, 2444 .clkr = { 2445 .enable_reg = 0x32018, 2446 .enable_mask = BIT(0), 2447 .hw.init = &(const struct clk_init_data) { 2448 .name = "gcc_qpic_sleep_clk", 2449 .ops = &clk_branch2_ops, 2450 }, 2451 }, 2452 }; 2453 2454 static struct clk_branch gcc_qupv3_ahb_mst_clk = { 2455 .halt_reg = 0x1014, 2456 .halt_check = BRANCH_HALT_VOTED, 2457 .clkr = { 2458 .enable_reg = 0xb004, 2459 .enable_mask = BIT(14), 2460 .hw.init = &(const struct clk_init_data) { 2461 .name = "gcc_qupv3_ahb_mst_clk", 2462 .parent_hws = (const struct clk_hw*[]) { 2463 &gcc_pcnoc_bfdcd_clk_src.clkr.hw, 2464 }, 2465 .num_parents = 1, 2466 .flags = CLK_SET_RATE_PARENT, 2467 .ops = &clk_branch2_ops, 2468 }, 2469 }, 2470 }; 2471 2472 static struct clk_branch gcc_qupv3_ahb_slv_clk = { 2473 .halt_reg = 0x102c, 2474 .halt_check = BRANCH_HALT_VOTED, 2475 .clkr = { 2476 .enable_reg = 0xb004, 2477 .enable_mask = BIT(4), 2478 .hw.init = &(const struct clk_init_data) { 2479 .name = "gcc_qupv3_ahb_slv_clk", 2480 .parent_hws = (const struct clk_hw*[]) { 2481 &gcc_pcnoc_bfdcd_clk_src.clkr.hw, 2482 }, 2483 .num_parents = 1, 2484 .flags = CLK_SET_RATE_PARENT, 2485 .ops = &clk_branch2_ops, 2486 }, 2487 }, 2488 }; 2489 2490 static struct clk_branch gcc_qupv3_wrap_se0_clk = { 2491 .halt_reg = 0x202c, 2492 .halt_check = BRANCH_HALT, 2493 .clkr = { 2494 .enable_reg = 0x202c, 2495 .enable_mask = BIT(0), 2496 .hw.init = &(const struct clk_init_data) { 2497 .name = "gcc_qupv3_wrap_se0_clk", 2498 .parent_hws = (const struct clk_hw*[]) { 2499 &gcc_qupv3_wrap_se0_clk_src.clkr.hw, 2500 }, 2501 .num_parents = 1, 2502 .flags = CLK_SET_RATE_PARENT, 2503 .ops = &clk_branch2_ops, 2504 }, 2505 }, 2506 }; 2507 2508 static struct clk_branch gcc_qupv3_wrap_se1_clk = { 2509 .halt_reg = 0x302c, 2510 .halt_check = BRANCH_HALT, 2511 .clkr = { 2512 .enable_reg = 0x302c, 2513 .enable_mask = BIT(0), 2514 .hw.init = &(const struct clk_init_data) { 2515 .name = "gcc_qupv3_wrap_se1_clk", 2516 .parent_hws = (const struct clk_hw*[]) { 2517 &gcc_qupv3_wrap_se1_clk_src.clkr.hw, 2518 }, 2519 .num_parents = 1, 2520 .flags = CLK_SET_RATE_PARENT, 2521 .ops = &clk_branch2_ops, 2522 }, 2523 }, 2524 }; 2525 2526 static struct clk_branch gcc_qupv3_wrap_se2_clk = { 2527 .halt_reg = 0x3048, 2528 .halt_check = BRANCH_HALT, 2529 .clkr = { 2530 .enable_reg = 0x3048, 2531 .enable_mask = BIT(0), 2532 .hw.init = &(const struct clk_init_data) { 2533 .name = "gcc_qupv3_wrap_se2_clk", 2534 .parent_hws = (const struct clk_hw*[]) { 2535 &gcc_qupv3_wrap_se2_clk_src.clkr.hw, 2536 }, 2537 .num_parents = 1, 2538 .flags = CLK_SET_RATE_PARENT, 2539 .ops = &clk_branch2_ops, 2540 }, 2541 }, 2542 }; 2543 2544 static struct clk_branch gcc_qupv3_wrap_se3_clk = { 2545 .halt_reg = 0x3064, 2546 .halt_check = BRANCH_HALT, 2547 .clkr = { 2548 .enable_reg = 0x3064, 2549 .enable_mask = BIT(0), 2550 .hw.init = &(const struct clk_init_data) { 2551 .name = "gcc_qupv3_wrap_se3_clk", 2552 .parent_hws = (const struct clk_hw*[]) { 2553 &gcc_qupv3_wrap_se3_clk_src.clkr.hw, 2554 }, 2555 .num_parents = 1, 2556 .flags = CLK_SET_RATE_PARENT, 2557 .ops = &clk_branch2_ops, 2558 }, 2559 }, 2560 }; 2561 2562 static struct clk_branch gcc_qupv3_wrap_se4_clk = { 2563 .halt_reg = 0x3080, 2564 .halt_check = BRANCH_HALT, 2565 .clkr = { 2566 .enable_reg = 0x3080, 2567 .enable_mask = BIT(0), 2568 .hw.init = &(const struct clk_init_data) { 2569 .name = "gcc_qupv3_wrap_se4_clk", 2570 .parent_hws = (const struct clk_hw*[]) { 2571 &gcc_qupv3_wrap_se4_clk_src.clkr.hw, 2572 }, 2573 .num_parents = 1, 2574 .flags = CLK_SET_RATE_PARENT, 2575 .ops = &clk_branch2_ops, 2576 }, 2577 }, 2578 }; 2579 2580 static struct clk_branch gcc_qupv3_wrap_se5_clk = { 2581 .halt_reg = 0x30a4, 2582 .halt_check = BRANCH_HALT, 2583 .clkr = { 2584 .enable_reg = 0x30a4, 2585 .enable_mask = BIT(0), 2586 .hw.init = &(const struct clk_init_data) { 2587 .name = "gcc_qupv3_wrap_se5_clk", 2588 .parent_hws = (const struct clk_hw*[]) { 2589 &gcc_qupv3_wrap_se5_clk_src.clkr.hw, 2590 }, 2591 .num_parents = 1, 2592 .flags = CLK_SET_RATE_PARENT, 2593 .ops = &clk_branch2_ops, 2594 }, 2595 }, 2596 }; 2597 2598 static struct clk_branch gcc_qupv3_wrap_se6_clk = { 2599 .halt_reg = 0x4018, 2600 .halt_check = BRANCH_HALT, 2601 .clkr = { 2602 .enable_reg = 0x4018, 2603 .enable_mask = BIT(0), 2604 .hw.init = &(const struct clk_init_data) { 2605 .name = "gcc_qupv3_wrap_se6_clk", 2606 .parent_hws = (const struct clk_hw*[]) { 2607 &gcc_qupv3_wrap_se6_clk_src.clkr.hw, 2608 }, 2609 .num_parents = 1, 2610 .flags = CLK_SET_RATE_PARENT, 2611 .ops = &clk_branch2_ops, 2612 }, 2613 }, 2614 }; 2615 2616 static struct clk_branch gcc_qupv3_wrap_se7_clk = { 2617 .halt_reg = 0x4034, 2618 .halt_check = BRANCH_HALT, 2619 .clkr = { 2620 .enable_reg = 0x4034, 2621 .enable_mask = BIT(0), 2622 .hw.init = &(const struct clk_init_data) { 2623 .name = "gcc_qupv3_wrap_se7_clk", 2624 .parent_hws = (const struct clk_hw*[]) { 2625 &gcc_qupv3_wrap_se7_clk_src.clkr.hw, 2626 }, 2627 .num_parents = 1, 2628 .flags = CLK_SET_RATE_PARENT, 2629 .ops = &clk_branch2_ops, 2630 }, 2631 }, 2632 }; 2633 2634 static struct clk_branch gcc_sdcc1_ahb_clk = { 2635 .halt_reg = 0x3303c, 2636 .halt_check = BRANCH_HALT, 2637 .clkr = { 2638 .enable_reg = 0x3303c, 2639 .enable_mask = BIT(0), 2640 .hw.init = &(const struct clk_init_data) { 2641 .name = "gcc_sdcc1_ahb_clk", 2642 .parent_hws = (const struct clk_hw*[]) { 2643 &gcc_pcnoc_bfdcd_clk_src.clkr.hw, 2644 }, 2645 .num_parents = 1, 2646 .flags = CLK_SET_RATE_PARENT, 2647 .ops = &clk_branch2_ops, 2648 }, 2649 }, 2650 }; 2651 2652 static struct clk_branch gcc_sdcc1_apps_clk = { 2653 .halt_reg = 0x3302c, 2654 .halt_check = BRANCH_HALT, 2655 .clkr = { 2656 .enable_reg = 0x3302c, 2657 .enable_mask = BIT(0), 2658 .hw.init = &(const struct clk_init_data) { 2659 .name = "gcc_sdcc1_apps_clk", 2660 .parent_hws = (const struct clk_hw*[]) { 2661 &gcc_sdcc1_apps_clk_src.clkr.hw, 2662 }, 2663 .num_parents = 1, 2664 .flags = CLK_SET_RATE_PARENT, 2665 .ops = &clk_branch2_ops, 2666 }, 2667 }, 2668 }; 2669 2670 static struct clk_branch gcc_sdcc1_ice_core_clk = { 2671 .halt_reg = 0x33034, 2672 .halt_check = BRANCH_HALT, 2673 .clkr = { 2674 .enable_reg = 0x33034, 2675 .enable_mask = BIT(0), 2676 .hw.init = &(const struct clk_init_data) { 2677 .name = "gcc_sdcc1_ice_core_clk", 2678 .parent_hws = (const struct clk_hw*[]) { 2679 &gcc_sdcc1_ice_core_clk_src.clkr.hw, 2680 }, 2681 .num_parents = 1, 2682 .flags = CLK_SET_RATE_PARENT, 2683 .ops = &clk_branch2_ops, 2684 }, 2685 }, 2686 }; 2687 2688 static struct clk_branch gcc_snoc_usb_clk = { 2689 .halt_reg = 0x2e0c4, 2690 .halt_check = BRANCH_HALT, 2691 .clkr = { 2692 .enable_reg = 0x2e0c4, 2693 .enable_mask = BIT(0), 2694 .hw.init = &(const struct clk_init_data) { 2695 .name = "gcc_snoc_usb_clk", 2696 .parent_hws = (const struct clk_hw*[]) { 2697 &gcc_usb0_master_clk_src.clkr.hw, 2698 }, 2699 .num_parents = 1, 2700 .flags = CLK_SET_RATE_PARENT, 2701 .ops = &clk_branch2_ops, 2702 }, 2703 }, 2704 }; 2705 2706 static struct clk_branch gcc_uniphy0_ahb_clk = { 2707 .halt_reg = 0x1704c, 2708 .halt_check = BRANCH_HALT, 2709 .clkr = { 2710 .enable_reg = 0x1704c, 2711 .enable_mask = BIT(0), 2712 .hw.init = &(const struct clk_init_data) { 2713 .name = "gcc_uniphy0_ahb_clk", 2714 .parent_hws = (const struct clk_hw*[]) { 2715 &gcc_pcnoc_bfdcd_clk_src.clkr.hw, 2716 }, 2717 .num_parents = 1, 2718 .flags = CLK_SET_RATE_PARENT, 2719 .ops = &clk_branch2_ops, 2720 }, 2721 }, 2722 }; 2723 2724 static struct clk_branch gcc_uniphy0_sys_clk = { 2725 .halt_reg = 0x17048, 2726 .halt_check = BRANCH_HALT_VOTED, 2727 .clkr = { 2728 .enable_reg = 0x17048, 2729 .enable_mask = BIT(0), 2730 .hw.init = &(const struct clk_init_data) { 2731 .name = "gcc_uniphy0_sys_clk", 2732 .parent_hws = (const struct clk_hw*[]) { 2733 &gcc_uniphy_sys_clk_src.clkr.hw, 2734 }, 2735 .num_parents = 1, 2736 .flags = CLK_SET_RATE_PARENT, 2737 .ops = &clk_branch2_ops, 2738 }, 2739 }, 2740 }; 2741 2742 static struct clk_branch gcc_uniphy1_ahb_clk = { 2743 .halt_reg = 0x1705c, 2744 .halt_check = BRANCH_HALT, 2745 .clkr = { 2746 .enable_reg = 0x1705c, 2747 .enable_mask = BIT(0), 2748 .hw.init = &(const struct clk_init_data) { 2749 .name = "gcc_uniphy1_ahb_clk", 2750 .parent_hws = (const struct clk_hw*[]) { 2751 &gcc_pcnoc_bfdcd_clk_src.clkr.hw, 2752 }, 2753 .num_parents = 1, 2754 .flags = CLK_SET_RATE_PARENT, 2755 .ops = &clk_branch2_ops, 2756 }, 2757 }, 2758 }; 2759 2760 static struct clk_branch gcc_uniphy1_sys_clk = { 2761 .halt_reg = 0x17058, 2762 .halt_check = BRANCH_HALT_VOTED, 2763 .clkr = { 2764 .enable_reg = 0x17058, 2765 .enable_mask = BIT(0), 2766 .hw.init = &(const struct clk_init_data) { 2767 .name = "gcc_uniphy1_sys_clk", 2768 .parent_hws = (const struct clk_hw*[]) { 2769 &gcc_uniphy_sys_clk_src.clkr.hw, 2770 }, 2771 .num_parents = 1, 2772 .flags = CLK_SET_RATE_PARENT, 2773 .ops = &clk_branch2_ops, 2774 }, 2775 }, 2776 }; 2777 2778 static struct clk_branch gcc_uniphy2_ahb_clk = { 2779 .halt_reg = 0x1706c, 2780 .halt_check = BRANCH_HALT, 2781 .clkr = { 2782 .enable_reg = 0x1706c, 2783 .enable_mask = BIT(0), 2784 .hw.init = &(const struct clk_init_data) { 2785 .name = "gcc_uniphy2_ahb_clk", 2786 .parent_hws = (const struct clk_hw*[]) { 2787 &gcc_pcnoc_bfdcd_clk_src.clkr.hw, 2788 }, 2789 .num_parents = 1, 2790 .flags = CLK_SET_RATE_PARENT, 2791 .ops = &clk_branch2_ops, 2792 }, 2793 }, 2794 }; 2795 2796 static struct clk_branch gcc_uniphy2_sys_clk = { 2797 .halt_reg = 0x17068, 2798 .halt_check = BRANCH_HALT_VOTED, 2799 .clkr = { 2800 .enable_reg = 0x17068, 2801 .enable_mask = BIT(0), 2802 .hw.init = &(const struct clk_init_data) { 2803 .name = "gcc_uniphy2_sys_clk", 2804 .parent_hws = (const struct clk_hw*[]) { 2805 &gcc_uniphy_sys_clk_src.clkr.hw, 2806 }, 2807 .num_parents = 1, 2808 .flags = CLK_SET_RATE_PARENT, 2809 .ops = &clk_branch2_ops, 2810 }, 2811 }, 2812 }; 2813 2814 static struct clk_branch gcc_usb0_aux_clk = { 2815 .halt_reg = 0x2c04c, 2816 .halt_check = BRANCH_HALT_VOTED, 2817 .clkr = { 2818 .enable_reg = 0x2c04c, 2819 .enable_mask = BIT(0), 2820 .hw.init = &(const struct clk_init_data) { 2821 .name = "gcc_usb0_aux_clk", 2822 .parent_hws = (const struct clk_hw*[]) { 2823 &gcc_usb0_aux_clk_src.clkr.hw, 2824 }, 2825 .num_parents = 1, 2826 .flags = CLK_SET_RATE_PARENT, 2827 .ops = &clk_branch2_ops, 2828 }, 2829 }, 2830 }; 2831 2832 static struct clk_branch gcc_usb0_eud_at_clk = { 2833 .halt_reg = 0x30004, 2834 .halt_check = BRANCH_HALT_VOTED, 2835 .clkr = { 2836 .enable_reg = 0x30004, 2837 .enable_mask = BIT(0), 2838 .hw.init = &(const struct clk_init_data) { 2839 .name = "gcc_usb0_eud_at_clk", 2840 .parent_hws = (const struct clk_hw*[]) { 2841 &gcc_eud_at_div_clk_src.hw, 2842 }, 2843 .num_parents = 1, 2844 .flags = CLK_SET_RATE_PARENT, 2845 .ops = &clk_branch2_ops, 2846 }, 2847 }, 2848 }; 2849 2850 static struct clk_branch gcc_usb0_master_clk = { 2851 .halt_reg = 0x2c044, 2852 .halt_check = BRANCH_HALT_VOTED, 2853 .clkr = { 2854 .enable_reg = 0x2c044, 2855 .enable_mask = BIT(0), 2856 .hw.init = &(const struct clk_init_data) { 2857 .name = "gcc_usb0_master_clk", 2858 .parent_hws = (const struct clk_hw*[]) { 2859 &gcc_usb0_master_clk_src.clkr.hw, 2860 }, 2861 .num_parents = 1, 2862 .flags = CLK_SET_RATE_PARENT, 2863 .ops = &clk_branch2_ops, 2864 }, 2865 }, 2866 }; 2867 2868 static struct clk_branch gcc_usb0_mock_utmi_clk = { 2869 .halt_reg = 0x2c050, 2870 .halt_check = BRANCH_HALT_VOTED, 2871 .clkr = { 2872 .enable_reg = 0x2c050, 2873 .enable_mask = BIT(0), 2874 .hw.init = &(const struct clk_init_data) { 2875 .name = "gcc_usb0_mock_utmi_clk", 2876 .parent_hws = (const struct clk_hw*[]) { 2877 &gcc_usb0_mock_utmi_div_clk_src.clkr.hw, 2878 }, 2879 .num_parents = 1, 2880 .flags = CLK_SET_RATE_PARENT, 2881 .ops = &clk_branch2_ops, 2882 }, 2883 }, 2884 }; 2885 2886 static struct clk_branch gcc_usb0_phy_cfg_ahb_clk = { 2887 .halt_reg = 0x2c05c, 2888 .halt_check = BRANCH_HALT_VOTED, 2889 .clkr = { 2890 .enable_reg = 0x2c05c, 2891 .enable_mask = BIT(0), 2892 .hw.init = &(const struct clk_init_data) { 2893 .name = "gcc_usb0_phy_cfg_ahb_clk", 2894 .parent_hws = (const struct clk_hw*[]) { 2895 &gcc_pcnoc_bfdcd_clk_src.clkr.hw, 2896 }, 2897 .num_parents = 1, 2898 .flags = CLK_SET_RATE_PARENT, 2899 .ops = &clk_branch2_ops, 2900 }, 2901 }, 2902 }; 2903 2904 static struct clk_regmap_phy_mux gcc_usb0_pipe_clk_src = { 2905 .reg = 0x2c074, 2906 .clkr = { 2907 .hw.init = &(const struct clk_init_data) { 2908 .name = "gcc_usb0_pipe_clk_src", 2909 .parent_data = &(const struct clk_parent_data) { 2910 .index = DT_USB3_PHY0_CC_PIPE_CLK, 2911 }, 2912 .num_parents = 1, 2913 .ops = &clk_regmap_phy_mux_ops, 2914 }, 2915 }, 2916 }; 2917 2918 static struct clk_branch gcc_usb0_pipe_clk = { 2919 .halt_reg = 0x2c054, 2920 .halt_check = BRANCH_HALT_DELAY, 2921 .clkr = { 2922 .enable_reg = 0x2c054, 2923 .enable_mask = BIT(0), 2924 .hw.init = &(const struct clk_init_data) { 2925 .name = "gcc_usb0_pipe_clk", 2926 .parent_hws = (const struct clk_hw *[]) { 2927 &gcc_usb0_pipe_clk_src.clkr.hw 2928 }, 2929 .num_parents = 1, 2930 .flags = CLK_SET_RATE_PARENT, 2931 .ops = &clk_branch2_ops, 2932 }, 2933 }, 2934 }; 2935 2936 static struct clk_branch gcc_usb0_sleep_clk = { 2937 .halt_reg = 0x2c058, 2938 .halt_check = BRANCH_HALT_VOTED, 2939 .clkr = { 2940 .enable_reg = 0x2c058, 2941 .enable_mask = BIT(0), 2942 .hw.init = &(const struct clk_init_data) { 2943 .name = "gcc_usb0_sleep_clk", 2944 .parent_hws = (const struct clk_hw*[]) { 2945 &gcc_sleep_clk_src.clkr.hw, 2946 }, 2947 .num_parents = 1, 2948 .flags = CLK_SET_RATE_PARENT, 2949 .ops = &clk_branch2_ops, 2950 }, 2951 }, 2952 }; 2953 2954 static struct clk_branch gcc_usb1_master_clk = { 2955 .halt_reg = 0x3c028, 2956 .halt_check = BRANCH_HALT, 2957 .clkr = { 2958 .enable_reg = 0x3c028, 2959 .enable_mask = BIT(0), 2960 .hw.init = &(const struct clk_init_data) { 2961 .name = "gcc_usb1_master_clk", 2962 .parent_hws = (const struct clk_hw*[]) { 2963 &gcc_pcnoc_bfdcd_clk_src.clkr.hw, 2964 }, 2965 .num_parents = 1, 2966 .flags = CLK_SET_RATE_PARENT, 2967 .ops = &clk_branch2_ops, 2968 }, 2969 }, 2970 }; 2971 2972 static struct clk_branch gcc_usb1_mock_utmi_clk = { 2973 .halt_reg = 0x3c024, 2974 .halt_check = BRANCH_HALT, 2975 .clkr = { 2976 .enable_reg = 0x3c024, 2977 .enable_mask = BIT(0), 2978 .hw.init = &(const struct clk_init_data) { 2979 .name = "gcc_usb1_mock_utmi_clk", 2980 .parent_hws = (const struct clk_hw*[]) { 2981 &gcc_usb1_mock_utmi_div_clk_src.clkr.hw, 2982 }, 2983 .num_parents = 1, 2984 .flags = CLK_SET_RATE_PARENT, 2985 .ops = &clk_branch2_ops, 2986 }, 2987 }, 2988 }; 2989 2990 static struct clk_branch gcc_usb1_phy_cfg_ahb_clk = { 2991 .halt_reg = 0x3c01c, 2992 .halt_check = BRANCH_HALT_VOTED, 2993 .clkr = { 2994 .enable_reg = 0x3c01c, 2995 .enable_mask = BIT(0), 2996 .hw.init = &(const struct clk_init_data) { 2997 .name = "gcc_usb1_phy_cfg_ahb_clk", 2998 .parent_hws = (const struct clk_hw*[]) { 2999 &gcc_pcnoc_bfdcd_clk_src.clkr.hw, 3000 }, 3001 .num_parents = 1, 3002 .flags = CLK_SET_RATE_PARENT, 3003 .ops = &clk_branch2_ops, 3004 }, 3005 }, 3006 }; 3007 3008 static struct clk_branch gcc_usb1_sleep_clk = { 3009 .halt_reg = 0x3c020, 3010 .halt_check = BRANCH_HALT, 3011 .clkr = { 3012 .enable_reg = 0x3c020, 3013 .enable_mask = BIT(0), 3014 .hw.init = &(const struct clk_init_data) { 3015 .name = "gcc_usb1_sleep_clk", 3016 .parent_hws = (const struct clk_hw*[]) { 3017 &gcc_sleep_clk_src.clkr.hw, 3018 }, 3019 .num_parents = 1, 3020 .ops = &clk_branch2_ops, 3021 }, 3022 }, 3023 }; 3024 3025 static struct clk_regmap *gcc_ipq9650_clocks[] = { 3026 [GCC_ADSS_PWM_CLK] = &gcc_adss_pwm_clk.clkr, 3027 [GCC_ADSS_PWM_CLK_SRC] = &gcc_adss_pwm_clk_src.clkr, 3028 [GCC_ANOC_PCIE0_1LANE_M_CLK] = &gcc_anoc_pcie0_1lane_m_clk.clkr, 3029 [GCC_ANOC_PCIE0_1LANE_S_CLK] = &gcc_anoc_pcie0_1lane_s_clk.clkr, 3030 [GCC_ANOC_PCIE1_2LANE_M_CLK] = &gcc_anoc_pcie1_2lane_m_clk.clkr, 3031 [GCC_ANOC_PCIE1_2LANE_S_CLK] = &gcc_anoc_pcie1_2lane_s_clk.clkr, 3032 [GCC_ANOC_PCIE2_2LANE_M_CLK] = &gcc_anoc_pcie2_2lane_m_clk.clkr, 3033 [GCC_ANOC_PCIE2_2LANE_S_CLK] = &gcc_anoc_pcie2_2lane_s_clk.clkr, 3034 [GCC_ANOC_PCIE3_2LANE_M_CLK] = &gcc_anoc_pcie3_2lane_m_clk.clkr, 3035 [GCC_ANOC_PCIE3_2LANE_S_CLK] = &gcc_anoc_pcie3_2lane_s_clk.clkr, 3036 [GCC_ANOC_PCIE4_1LANE_M_CLK] = &gcc_anoc_pcie4_1lane_m_clk.clkr, 3037 [GCC_ANOC_PCIE4_1LANE_S_CLK] = &gcc_anoc_pcie4_1lane_s_clk.clkr, 3038 [GCC_CMN_12GPLL_AHB_CLK] = &gcc_cmn_12gpll_ahb_clk.clkr, 3039 [GCC_CMN_12GPLL_SYS_CLK] = &gcc_cmn_12gpll_sys_clk.clkr, 3040 [GCC_MDIO_AHB_CLK] = &gcc_mdio_ahb_clk.clkr, 3041 [GCC_NSS_TS_CLK] = &gcc_nss_ts_clk.clkr, 3042 [GCC_NSS_TS_CLK_SRC] = &gcc_nss_ts_clk_src.clkr, 3043 [GCC_NSSCC_CLK] = &gcc_nsscc_clk.clkr, 3044 [GCC_NSSCFG_CLK] = &gcc_nsscfg_clk.clkr, 3045 [GCC_NSSNOC_ATB_CLK] = &gcc_nssnoc_atb_clk.clkr, 3046 [GCC_NSSNOC_MEMNOC_1_CLK] = &gcc_nssnoc_memnoc_1_clk.clkr, 3047 [GCC_NSSNOC_MEMNOC_BFDCD_CLK_SRC] = &gcc_nssnoc_memnoc_bfdcd_clk_src.clkr, 3048 [GCC_NSSNOC_MEMNOC_CLK] = &gcc_nssnoc_memnoc_clk.clkr, 3049 [GCC_NSSNOC_MEMNOC_DIV_CLK_SRC] = &gcc_nssnoc_memnoc_div_clk_src.clkr, 3050 [GCC_NSSNOC_NSSCC_CLK] = &gcc_nssnoc_nsscc_clk.clkr, 3051 [GCC_NSSNOC_PCNOC_1_CLK] = &gcc_nssnoc_pcnoc_1_clk.clkr, 3052 [GCC_NSSNOC_QOSGEN_REF_CLK] = &gcc_nssnoc_qosgen_ref_clk.clkr, 3053 [GCC_NSSNOC_SNOC_1_CLK] = &gcc_nssnoc_snoc_1_clk.clkr, 3054 [GCC_NSSNOC_SNOC_CLK] = &gcc_nssnoc_snoc_clk.clkr, 3055 [GCC_NSSNOC_TIMEOUT_REF_CLK] = &gcc_nssnoc_timeout_ref_clk.clkr, 3056 [GCC_NSSNOC_XO_DCD_CLK] = &gcc_nssnoc_xo_dcd_clk.clkr, 3057 [GCC_PCIE0_AHB_CLK] = &gcc_pcie0_ahb_clk.clkr, 3058 [GCC_PCIE0_AUX_CLK] = &gcc_pcie0_aux_clk.clkr, 3059 [GCC_PCIE0_AXI_M_CLK] = &gcc_pcie0_axi_m_clk.clkr, 3060 [GCC_PCIE0_AXI_M_CLK_SRC] = &gcc_pcie0_axi_m_clk_src.clkr, 3061 [GCC_PCIE0_AXI_S_BRIDGE_CLK] = &gcc_pcie0_axi_s_bridge_clk.clkr, 3062 [GCC_PCIE0_AXI_S_CLK] = &gcc_pcie0_axi_s_clk.clkr, 3063 [GCC_PCIE0_AXI_S_CLK_SRC] = &gcc_pcie0_axi_s_clk_src.clkr, 3064 [GCC_PCIE0_PIPE_CLK] = &gcc_pcie0_pipe_clk.clkr, 3065 [GCC_PCIE0_PIPE_CLK_SRC] = &gcc_pcie0_pipe_clk_src.clkr, 3066 [GCC_PCIE0_RCHNG_CLK_SRC] = &gcc_pcie0_rchng_clk_src.clkr, 3067 [GCC_PCIE0_RCHNG_CLK] = &gcc_pcie0_rchng_clk.clkr, 3068 [GCC_PCIE1_AHB_CLK] = &gcc_pcie1_ahb_clk.clkr, 3069 [GCC_PCIE1_AUX_CLK] = &gcc_pcie1_aux_clk.clkr, 3070 [GCC_PCIE1_AXI_M_CLK] = &gcc_pcie1_axi_m_clk.clkr, 3071 [GCC_PCIE1_AXI_M_CLK_SRC] = &gcc_pcie1_axi_m_clk_src.clkr, 3072 [GCC_PCIE1_AXI_S_BRIDGE_CLK] = &gcc_pcie1_axi_s_bridge_clk.clkr, 3073 [GCC_PCIE1_AXI_S_CLK] = &gcc_pcie1_axi_s_clk.clkr, 3074 [GCC_PCIE1_AXI_S_CLK_SRC] = &gcc_pcie1_axi_s_clk_src.clkr, 3075 [GCC_PCIE1_PIPE_CLK] = &gcc_pcie1_pipe_clk.clkr, 3076 [GCC_PCIE1_PIPE_CLK_SRC] = &gcc_pcie1_pipe_clk_src.clkr, 3077 [GCC_PCIE1_RCHNG_CLK_SRC] = &gcc_pcie1_rchng_clk_src.clkr, 3078 [GCC_PCIE1_RCHNG_CLK] = &gcc_pcie1_rchng_clk.clkr, 3079 [GCC_PCIE2_AHB_CLK] = &gcc_pcie2_ahb_clk.clkr, 3080 [GCC_PCIE2_AUX_CLK] = &gcc_pcie2_aux_clk.clkr, 3081 [GCC_PCIE2_AXI_M_CLK] = &gcc_pcie2_axi_m_clk.clkr, 3082 [GCC_PCIE2_AXI_M_CLK_SRC] = &gcc_pcie2_axi_m_clk_src.clkr, 3083 [GCC_PCIE2_AXI_S_BRIDGE_CLK] = &gcc_pcie2_axi_s_bridge_clk.clkr, 3084 [GCC_PCIE2_AXI_S_CLK] = &gcc_pcie2_axi_s_clk.clkr, 3085 [GCC_PCIE2_AXI_S_CLK_SRC] = &gcc_pcie2_axi_s_clk_src.clkr, 3086 [GCC_PCIE2_PIPE_CLK] = &gcc_pcie2_pipe_clk.clkr, 3087 [GCC_PCIE2_PIPE_CLK_SRC] = &gcc_pcie2_pipe_clk_src.clkr, 3088 [GCC_PCIE2_RCHNG_CLK_SRC] = &gcc_pcie2_rchng_clk_src.clkr, 3089 [GCC_PCIE2_RCHNG_CLK] = &gcc_pcie2_rchng_clk.clkr, 3090 [GCC_PCIE3_AHB_CLK] = &gcc_pcie3_ahb_clk.clkr, 3091 [GCC_PCIE3_AUX_CLK] = &gcc_pcie3_aux_clk.clkr, 3092 [GCC_PCIE3_AXI_M_CLK] = &gcc_pcie3_axi_m_clk.clkr, 3093 [GCC_PCIE3_AXI_M_CLK_SRC] = &gcc_pcie3_axi_m_clk_src.clkr, 3094 [GCC_PCIE3_AXI_S_BRIDGE_CLK] = &gcc_pcie3_axi_s_bridge_clk.clkr, 3095 [GCC_PCIE3_AXI_S_CLK] = &gcc_pcie3_axi_s_clk.clkr, 3096 [GCC_PCIE3_AXI_S_CLK_SRC] = &gcc_pcie3_axi_s_clk_src.clkr, 3097 [GCC_PCIE3_PIPE_CLK] = &gcc_pcie3_pipe_clk.clkr, 3098 [GCC_PCIE3_PIPE_CLK_SRC] = &gcc_pcie3_pipe_clk_src.clkr, 3099 [GCC_PCIE3_RCHNG_CLK_SRC] = &gcc_pcie3_rchng_clk_src.clkr, 3100 [GCC_PCIE3_RCHNG_CLK] = &gcc_pcie3_rchng_clk.clkr, 3101 [GCC_PCIE4_AHB_CLK] = &gcc_pcie4_ahb_clk.clkr, 3102 [GCC_PCIE4_AUX_CLK] = &gcc_pcie4_aux_clk.clkr, 3103 [GCC_PCIE4_AXI_M_CLK] = &gcc_pcie4_axi_m_clk.clkr, 3104 [GCC_PCIE4_AXI_M_CLK_SRC] = &gcc_pcie4_axi_m_clk_src.clkr, 3105 [GCC_PCIE4_AXI_S_BRIDGE_CLK] = &gcc_pcie4_axi_s_bridge_clk.clkr, 3106 [GCC_PCIE4_AXI_S_CLK] = &gcc_pcie4_axi_s_clk.clkr, 3107 [GCC_PCIE4_AXI_S_CLK_SRC] = &gcc_pcie4_axi_s_clk_src.clkr, 3108 [GCC_PCIE4_PIPE_CLK] = &gcc_pcie4_pipe_clk.clkr, 3109 [GCC_PCIE4_PIPE_CLK_SRC] = &gcc_pcie4_pipe_clk_src.clkr, 3110 [GCC_PCIE4_RCHNG_CLK_SRC] = &gcc_pcie4_rchng_clk_src.clkr, 3111 [GCC_PCIE4_RCHNG_CLK] = &gcc_pcie4_rchng_clk.clkr, 3112 [GCC_PCIE_AUX_CLK_SRC] = &gcc_pcie_aux_clk_src.clkr, 3113 [GCC_PCNOC_BFDCD_CLK_SRC] = &gcc_pcnoc_bfdcd_clk_src.clkr, 3114 [GCC_QDSS_AT_CLK] = &gcc_qdss_at_clk.clkr, 3115 [GCC_QDSS_AT_CLK_SRC] = &gcc_qdss_at_clk_src.clkr, 3116 [GCC_QDSS_DAP_CLK] = &gcc_qdss_dap_clk.clkr, 3117 [GCC_QDSS_TSCTR_CLK_SRC] = &gcc_qdss_tsctr_clk_src.clkr, 3118 [GCC_QPIC_AHB_CLK] = &gcc_qpic_ahb_clk.clkr, 3119 [GCC_QPIC_CLK] = &gcc_qpic_clk.clkr, 3120 [GCC_QPIC_CLK_SRC] = &gcc_qpic_clk_src.clkr, 3121 [GCC_QPIC_IO_MACRO_CLK] = &gcc_qpic_io_macro_clk.clkr, 3122 [GCC_QPIC_IO_MACRO_CLK_SRC] = &gcc_qpic_io_macro_clk_src.clkr, 3123 [GCC_QPIC_SLEEP_CLK] = &gcc_qpic_sleep_clk.clkr, 3124 [GCC_QUPV3_2X_CORE_CLK_SRC] = &gcc_qupv3_2x_core_clk_src.clkr, 3125 [GCC_QUPV3_AHB_MST_CLK] = &gcc_qupv3_ahb_mst_clk.clkr, 3126 [GCC_QUPV3_AHB_SLV_CLK] = &gcc_qupv3_ahb_slv_clk.clkr, 3127 [GCC_QUPV3_WRAP_SE0_CLK] = &gcc_qupv3_wrap_se0_clk.clkr, 3128 [GCC_QUPV3_WRAP_SE0_CLK_SRC] = &gcc_qupv3_wrap_se0_clk_src.clkr, 3129 [GCC_QUPV3_WRAP_SE1_CLK] = &gcc_qupv3_wrap_se1_clk.clkr, 3130 [GCC_QUPV3_WRAP_SE1_CLK_SRC] = &gcc_qupv3_wrap_se1_clk_src.clkr, 3131 [GCC_QUPV3_WRAP_SE2_CLK] = &gcc_qupv3_wrap_se2_clk.clkr, 3132 [GCC_QUPV3_WRAP_SE2_CLK_SRC] = &gcc_qupv3_wrap_se2_clk_src.clkr, 3133 [GCC_QUPV3_WRAP_SE3_CLK] = &gcc_qupv3_wrap_se3_clk.clkr, 3134 [GCC_QUPV3_WRAP_SE3_CLK_SRC] = &gcc_qupv3_wrap_se3_clk_src.clkr, 3135 [GCC_QUPV3_WRAP_SE4_CLK] = &gcc_qupv3_wrap_se4_clk.clkr, 3136 [GCC_QUPV3_WRAP_SE4_CLK_SRC] = &gcc_qupv3_wrap_se4_clk_src.clkr, 3137 [GCC_QUPV3_WRAP_SE5_CLK] = &gcc_qupv3_wrap_se5_clk.clkr, 3138 [GCC_QUPV3_WRAP_SE5_CLK_SRC] = &gcc_qupv3_wrap_se5_clk_src.clkr, 3139 [GCC_QUPV3_WRAP_SE6_CLK] = &gcc_qupv3_wrap_se6_clk.clkr, 3140 [GCC_QUPV3_WRAP_SE6_CLK_SRC] = &gcc_qupv3_wrap_se6_clk_src.clkr, 3141 [GCC_QUPV3_WRAP_SE7_CLK] = &gcc_qupv3_wrap_se7_clk.clkr, 3142 [GCC_QUPV3_WRAP_SE7_CLK_SRC] = &gcc_qupv3_wrap_se7_clk_src.clkr, 3143 [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr, 3144 [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr, 3145 [GCC_SDCC1_APPS_CLK_SRC] = &gcc_sdcc1_apps_clk_src.clkr, 3146 [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr, 3147 [GCC_SDCC1_ICE_CORE_CLK_SRC] = &gcc_sdcc1_ice_core_clk_src.clkr, 3148 [GCC_SLEEP_CLK_SRC] = &gcc_sleep_clk_src.clkr, 3149 [GCC_SNOC_USB_CLK] = &gcc_snoc_usb_clk.clkr, 3150 [GCC_SYSTEM_NOC_BFDCD_CLK_SRC] = &gcc_system_noc_bfdcd_clk_src.clkr, 3151 [GCC_UNIPHY0_AHB_CLK] = &gcc_uniphy0_ahb_clk.clkr, 3152 [GCC_UNIPHY0_SYS_CLK] = &gcc_uniphy0_sys_clk.clkr, 3153 [GCC_UNIPHY1_AHB_CLK] = &gcc_uniphy1_ahb_clk.clkr, 3154 [GCC_UNIPHY1_SYS_CLK] = &gcc_uniphy1_sys_clk.clkr, 3155 [GCC_UNIPHY2_AHB_CLK] = &gcc_uniphy2_ahb_clk.clkr, 3156 [GCC_UNIPHY2_SYS_CLK] = &gcc_uniphy2_sys_clk.clkr, 3157 [GCC_UNIPHY_SYS_CLK_SRC] = &gcc_uniphy_sys_clk_src.clkr, 3158 [GCC_USB0_AUX_CLK] = &gcc_usb0_aux_clk.clkr, 3159 [GCC_USB0_AUX_CLK_SRC] = &gcc_usb0_aux_clk_src.clkr, 3160 [GCC_USB0_EUD_AT_CLK] = &gcc_usb0_eud_at_clk.clkr, 3161 [GCC_USB0_MASTER_CLK] = &gcc_usb0_master_clk.clkr, 3162 [GCC_USB0_MASTER_CLK_SRC] = &gcc_usb0_master_clk_src.clkr, 3163 [GCC_USB0_MOCK_UTMI_CLK] = &gcc_usb0_mock_utmi_clk.clkr, 3164 [GCC_USB0_MOCK_UTMI_CLK_SRC] = &gcc_usb0_mock_utmi_clk_src.clkr, 3165 [GCC_USB0_MOCK_UTMI_DIV_CLK_SRC] = &gcc_usb0_mock_utmi_div_clk_src.clkr, 3166 [GCC_USB0_PHY_CFG_AHB_CLK] = &gcc_usb0_phy_cfg_ahb_clk.clkr, 3167 [GCC_USB0_PIPE_CLK] = &gcc_usb0_pipe_clk.clkr, 3168 [GCC_USB0_PIPE_CLK_SRC] = &gcc_usb0_pipe_clk_src.clkr, 3169 [GCC_USB0_SLEEP_CLK] = &gcc_usb0_sleep_clk.clkr, 3170 [GCC_USB1_MASTER_CLK] = &gcc_usb1_master_clk.clkr, 3171 [GCC_USB1_MOCK_UTMI_CLK] = &gcc_usb1_mock_utmi_clk.clkr, 3172 [GCC_USB1_MOCK_UTMI_CLK_SRC] = &gcc_usb1_mock_utmi_clk_src.clkr, 3173 [GCC_USB1_MOCK_UTMI_DIV_CLK_SRC] = &gcc_usb1_mock_utmi_div_clk_src.clkr, 3174 [GCC_USB1_PHY_CFG_AHB_CLK] = &gcc_usb1_phy_cfg_ahb_clk.clkr, 3175 [GCC_USB1_SLEEP_CLK] = &gcc_usb1_sleep_clk.clkr, 3176 [GCC_XO_CLK_SRC] = &gcc_xo_clk_src.clkr, 3177 [GPLL0_MAIN] = &gpll0_main.clkr, 3178 [GPLL0] = &gpll0.clkr, 3179 [GPLL2] = &gpll2.clkr, 3180 [GPLL2_OUT_MAIN] = &gpll2_out_main.clkr, 3181 [GPLL4] = &gpll4.clkr, 3182 }; 3183 3184 static const struct qcom_reset_map gcc_ipq9650_resets[] = { 3185 [GCC_ADSS_BCR] = { 0x1c000 }, 3186 [GCC_ADSS_PWM_CLK_ARES] = { 0x1c00c, 2 }, 3187 [GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR] = { 0x38000 }, 3188 [GCC_APC0_VOLTAGE_DROOP_DETECTOR_GPLL0_CLK_ARES] = { 0x3800c, 2 }, 3189 [GCC_APSS_AHB_CLK_ARES] = { 0x24014, 2 }, 3190 [GCC_APSS_ATB_CLK_ARES] = { 0x24034, 2 }, 3191 [GCC_APSS_AXI_CLK_ARES] = { 0x24018, 2 }, 3192 [GCC_APSS_TS_CLK_ARES] = { 0x24030, 2 }, 3193 [GCC_BOOT_ROM_AHB_CLK_ARES] = { 0x1302c, 2 }, 3194 [GCC_BOOT_ROM_BCR] = { 0x13028 }, 3195 [GCC_CPUSS_TRIG_CLK_ARES] = { 0x2401c, 2 }, 3196 [GCC_GP1_CLK_ARES] = { 0x8018, 2 }, 3197 [GCC_GP2_CLK_ARES] = { 0x8030, 2 }, 3198 [GCC_GP3_CLK_ARES] = { 0x8048, 2 }, 3199 [GCC_MDIO_AHB_CLK_ARES] = { 0x17040, 2 }, 3200 [GCC_MDIO_BCR] = { 0x1703c }, 3201 [GCC_NSS_BCR] = { 0x17000 }, 3202 [GCC_NSS_TS_CLK_ARES] = { 0x17018, 2 }, 3203 [GCC_NSSCC_CLK_ARES] = { 0x17034, 2 }, 3204 [GCC_NSSCFG_CLK_ARES] = { 0x1702c, 2 }, 3205 [GCC_NSSNOC_ATB_CLK_ARES] = { 0x17014, 2 }, 3206 [GCC_NSSNOC_MEMNOC_1_CLK_ARES] = { 0x17084, 2 }, 3207 [GCC_NSSNOC_MEMNOC_CLK_ARES] = { 0x17024, 2 }, 3208 [GCC_NSSNOC_NSSCC_CLK_ARES] = { 0x17030, 2 }, 3209 [GCC_NSSNOC_PCNOC_1_CLK_ARES] = { 0x17080, 2 }, 3210 [GCC_NSSNOC_QOSGEN_REF_CLK_ARES] = { 0x1701c, 2 }, 3211 [GCC_NSSNOC_SNOC_1_CLK_ARES] = { 0x1707c, 2 }, 3212 [GCC_NSSNOC_SNOC_CLK_ARES] = { 0x17028, 2 }, 3213 [GCC_NSSNOC_TIMEOUT_REF_CLK_ARES] = { 0x17020, 2 }, 3214 [GCC_NSSNOC_XO_DCD_CLK_ARES] = { 0x17074, 2 }, 3215 [GCC_PCIE0_AHB_CLK_ARES] = { 0x28030, 2 }, 3216 [GCC_PCIE0_AUX_CLK_ARES] = { 0x28070, 2 }, 3217 [GCC_PCIE0_AXI_M_CLK_ARES] = { 0x28038, 2 }, 3218 [GCC_PCIE0_AXI_S_BRIDGE_CLK_ARES] = { 0x28048, 2 }, 3219 [GCC_PCIE0_AXI_S_CLK_ARES] = { 0x28040, 2 }, 3220 [GCC_PCIE0_BCR] = { 0x28000 }, 3221 [GCC_PCIE0_LINK_DOWN_BCR] = { 0x28054 }, 3222 [GCC_PCIE0_PHY_BCR] = { 0x28060 }, 3223 [GCC_PCIE0_PIPE_CLK_ARES] = { 0x28068, 2 }, 3224 [GCC_PCIE0PHY_PHY_BCR] = { 0x2805c }, 3225 [GCC_PCIE0_PIPE_RESET] = { 0x28058, 0 }, 3226 [GCC_PCIE0_CORE_STICKY_RESET] = { 0x28058, 1 }, 3227 [GCC_PCIE0_AXI_S_STICKY_RESET] = { 0x28058, 2 }, 3228 [GCC_PCIE0_AXI_S_RESET] = { 0x28058, 3 }, 3229 [GCC_PCIE0_AXI_M_STICKY_RESET] = { 0x28058, 4 }, 3230 [GCC_PCIE0_AXI_M_RESET] = { 0x28058, 5 }, 3231 [GCC_PCIE0_AUX_RESET] = { 0x28058, 6 }, 3232 [GCC_PCIE0_AHB_RESET] = { 0x28058, 7 }, 3233 [GCC_PCIE1_AHB_CLK_ARES] = { 0x29030, 2 }, 3234 [GCC_PCIE1_AUX_CLK_ARES] = { 0x29074, 2 }, 3235 [GCC_PCIE1_AXI_M_CLK_ARES] = { 0x29038, 2 }, 3236 [GCC_PCIE1_AXI_S_BRIDGE_CLK_ARES] = { 0x29048, 2 }, 3237 [GCC_PCIE1_AXI_S_CLK_ARES] = { 0x29040, 2 }, 3238 [GCC_PCIE1_BCR] = { 0x29000 }, 3239 [GCC_PCIE1_LINK_DOWN_BCR] = { 0x29054 }, 3240 [GCC_PCIE1_PHY_BCR] = { 0x29060 }, 3241 [GCC_PCIE1_PIPE_CLK_ARES] = { 0x29068, 2 }, 3242 [GCC_PCIE1PHY_PHY_BCR] = { 0x2905c }, 3243 [GCC_PCIE1_PIPE_RESET] = { 0x29058, 0 }, 3244 [GCC_PCIE1_CORE_STICKY_RESET] = { 0x29058, 1 }, 3245 [GCC_PCIE1_AXI_S_STICKY_RESET] = { 0x29058, 2 }, 3246 [GCC_PCIE1_AXI_S_RESET] = { 0x29058, 3 }, 3247 [GCC_PCIE1_AXI_M_STICKY_RESET] = { 0x29058, 4 }, 3248 [GCC_PCIE1_AXI_M_RESET] = { 0x29058, 5 }, 3249 [GCC_PCIE1_AUX_RESET] = { 0x29058, 6 }, 3250 [GCC_PCIE1_AHB_RESET] = { 0x29058, 7 }, 3251 [GCC_PCIE2_AHB_CLK_ARES] = { 0x2a030, 2 }, 3252 [GCC_PCIE2_AUX_CLK_ARES] = { 0x2a078, 2 }, 3253 [GCC_PCIE2_AXI_M_CLK_ARES] = { 0x2a038, 2 }, 3254 [GCC_PCIE2_AXI_S_BRIDGE_CLK_ARES] = { 0x2a048, 2 }, 3255 [GCC_PCIE2_AXI_S_CLK_ARES] = { 0x2a040, 2 }, 3256 [GCC_PCIE2_BCR] = { 0x2a000 }, 3257 [GCC_PCIE2_LINK_DOWN_BCR] = { 0x2a054 }, 3258 [GCC_PCIE2_PHY_BCR] = { 0x2a060 }, 3259 [GCC_PCIE2_PIPE_CLK_ARES] = { 0x2a068, 2 }, 3260 [GCC_PCIE2PHY_PHY_BCR] = { 0x2a05c }, 3261 [GCC_PCIE2_PIPE_RESET] = { 0x2a058, 0 }, 3262 [GCC_PCIE2_CORE_STICKY_RESET] = { 0x2a058, 1 }, 3263 [GCC_PCIE2_AXI_S_STICKY_RESET] = { 0x2a058, 2 }, 3264 [GCC_PCIE2_AXI_S_RESET] = { 0x2a058, 3 }, 3265 [GCC_PCIE2_AXI_M_STICKY_RESET] = { 0x2a058, 4 }, 3266 [GCC_PCIE2_AXI_M_RESET] = { 0x2a058, 5 }, 3267 [GCC_PCIE2_AUX_RESET] = { 0x2a058, 6 }, 3268 [GCC_PCIE2_AHB_RESET] = { 0x2a058, 7 }, 3269 [GCC_PCIE3_AHB_CLK_ARES] = { 0x2b030, 2 }, 3270 [GCC_PCIE3_AUX_CLK_ARES] = { 0x2b07c, 2 }, 3271 [GCC_PCIE3_AXI_M_CLK_ARES] = { 0x2b038, 2 }, 3272 [GCC_PCIE3_AXI_S_BRIDGE_CLK_ARES] = { 0x2b048, 2 }, 3273 [GCC_PCIE3_AXI_S_CLK_ARES] = { 0x2b040, 2 }, 3274 [GCC_PCIE3_BCR] = { 0x2b000 }, 3275 [GCC_PCIE3_LINK_DOWN_BCR] = { 0x2b054 }, 3276 [GCC_PCIE3_PHY_BCR] = { 0x2b060 }, 3277 [GCC_PCIE3_PIPE_CLK_ARES] = { 0x2b068, 2 }, 3278 [GCC_PCIE3PHY_PHY_BCR] = { 0x2b05c }, 3279 [GCC_PCIE3_PIPE_RESET] = { 0x2b058, 0 }, 3280 [GCC_PCIE3_CORE_STICKY_RESET] = { 0x2b058, 1 }, 3281 [GCC_PCIE3_AXI_S_STICKY_RESET] = { 0x2b058, 2 }, 3282 [GCC_PCIE3_AXI_S_RESET] = { 0x2b058, 3 }, 3283 [GCC_PCIE3_AXI_M_STICKY_RESET] = { 0x2b058, 4 }, 3284 [GCC_PCIE3_AXI_M_RESET] = { 0x2b058, 5 }, 3285 [GCC_PCIE3_AUX_RESET] = { 0x2b058, 6 }, 3286 [GCC_PCIE3_AHB_RESET] = { 0x2b058, 7 }, 3287 [GCC_PCIE4_AHB_CLK_ARES] = { 0x2501c, 2 }, 3288 [GCC_PCIE4_AUX_CLK_ARES] = { 0x25020, 2 }, 3289 [GCC_PCIE4_AXI_M_CLK_ARES] = { 0x25028, 2 }, 3290 [GCC_PCIE4_AXI_S_BRIDGE_CLK_ARES] = { 0x25038, 2 }, 3291 [GCC_PCIE4_AXI_S_CLK_ARES] = { 0x25030, 2 }, 3292 [GCC_PCIE4_BCR] = { 0x25000 }, 3293 [GCC_PCIE4_LINK_DOWN_BCR] = { 0x25044 }, 3294 [GCC_PCIE4_PHY_BCR] = { 0x2504c }, 3295 [GCC_PCIE4_PIPE_CLK_ARES] = { 0x2503c, 2 }, 3296 [GCC_PCIE4_PIPE_RESET] = { 0x25054, 0 }, 3297 [GCC_PCIE4_CORE_STICKY_RESET] = { 0x25054, 1 }, 3298 [GCC_PCIE4_AXI_S_STICKY_RESET] = { 0x25054, 2 }, 3299 [GCC_PCIE4_AXI_S_RESET] = { 0x25054, 3 }, 3300 [GCC_PCIE4_AXI_M_STICKY_RESET] = { 0x25054, 4 }, 3301 [GCC_PCIE4_AXI_M_RESET] = { 0x25054, 5 }, 3302 [GCC_PCIE4_AUX_RESET] = { 0x25054, 6 }, 3303 [GCC_PCIE4_AHB_RESET] = { 0x25054, 7 }, 3304 [GCC_PCIE4PHY_PHY_BCR] = { 0x25048 }, 3305 [GCC_QDSS_APB2JTAG_CLK_ARES] = { 0x2d05c, 2 }, 3306 [GCC_QDSS_AT_CLK_ARES] = { 0x2d034, 2 }, 3307 [GCC_QDSS_BCR] = { 0x2d000 }, 3308 [GCC_QDSS_CFG_AHB_CLK_ARES] = { 0x2d068, 2 }, 3309 [GCC_QDSS_DAP_AHB_CLK_ARES] = { 0x2d064, 2 }, 3310 [GCC_QDSS_DAP_CLK_ARES] = { 0x2d058, 2 }, 3311 [GCC_QDSS_ETR_USB_CLK_ARES] = { 0x2d060, 2 }, 3312 [GCC_QDSS_EUD_AT_CLK_ARES] = { 0x2d06c, 2 }, 3313 [GCC_QDSS_STM_CLK_ARES] = { 0x2d03c, 2 }, 3314 [GCC_QDSS_TRACECLKIN_CLK_ARES] = { 0x2d040, 2 }, 3315 [GCC_QDSS_TS_CLK_ARES] = { 0x2d078, 2 }, 3316 [GCC_QDSS_TSCTR_DIV16_CLK_ARES] = { 0x2d054, 2 }, 3317 [GCC_QDSS_TSCTR_DIV2_CLK_ARES] = { 0x2d044, 2 }, 3318 [GCC_QDSS_TSCTR_DIV3_CLK_ARES] = { 0x2d048, 2 }, 3319 [GCC_QDSS_TSCTR_DIV4_CLK_ARES] = { 0x2d04c, 2 }, 3320 [GCC_QDSS_TSCTR_DIV8_CLK_ARES] = { 0x2d050, 2 }, 3321 [GCC_QPIC_AHB_CLK_ARES] = { 0x32010, 2 }, 3322 [GCC_QPIC_CLK_ARES] = { 0x32028, 2 }, 3323 [GCC_QPIC_BCR] = { 0x32000 }, 3324 [GCC_QPIC_IO_MACRO_CLK_ARES] = { 0x3200c, 2 }, 3325 [GCC_QPIC_SLEEP_CLK_ARES] = { 0x32018, 2 }, 3326 [GCC_QUPV3_2X_CORE_CLK_ARES] = { 0x1020, 2 }, 3327 [GCC_QUPV3_AHB_MST_CLK_ARES] = { 0x1014, 2 }, 3328 [GCC_QUPV3_AHB_SLV_CLK_ARES] = { 0x102c, 2 }, 3329 [GCC_QUPV3_BCR] = { 0x1000 }, 3330 [GCC_QUPV3_CORE_CLK_ARES] = { 0x1018, 2 }, 3331 [GCC_QUPV3_WRAP_SE0_CLK_ARES] = { 0x202c, 2 }, 3332 [GCC_QUPV3_WRAP_SE0_BCR] = { 0x2000 }, 3333 [GCC_QUPV3_WRAP_SE1_CLK_ARES] = { 0x302c, 2 }, 3334 [GCC_QUPV3_WRAP_SE1_BCR] = { 0x3000 }, 3335 [GCC_QUPV3_WRAP_SE2_CLK_ARES] = { 0x3048, 2 }, 3336 [GCC_QUPV3_WRAP_SE2_BCR] = { 0x3030 }, 3337 [GCC_QUPV3_WRAP_SE3_CLK_ARES] = { 0x3064, 2 }, 3338 [GCC_QUPV3_WRAP_SE3_BCR] = { 0x304c }, 3339 [GCC_QUPV3_WRAP_SE4_CLK_ARES] = { 0x3080, 2 }, 3340 [GCC_QUPV3_WRAP_SE4_BCR] = { 0x3068 }, 3341 [GCC_QUPV3_WRAP_SE5_CLK_ARES] = { 0x30a4, 2 }, 3342 [GCC_QUPV3_WRAP_SE5_BCR] = { 0x308c }, 3343 [GCC_QUPV3_WRAP_SE6_CLK_ARES] = { 0x4018, 2 }, 3344 [GCC_QUPV3_WRAP_SE6_BCR] = { 0x4000 }, 3345 [GCC_QUPV3_WRAP_SE7_CLK_ARES] = { 0x4034, 2 }, 3346 [GCC_QUPV3_WRAP_SE7_BCR] = { 0x401c }, 3347 [GCC_QUSB2_0_PHY_BCR] = { 0x2c068 }, 3348 [GCC_QUSB2_1_PHY_BCR] = { 0x3c030 }, 3349 [GCC_SDCC1_APPS_CLK_ARES] = { 0x3302c, 2 }, 3350 [GCC_SDCC1_ICE_CORE_CLK_ARES] = { 0x33034, 2 }, 3351 [GCC_SDCC_BCR] = { 0x33000 }, 3352 [GCC_TLMM_AHB_CLK_ARES] = { 0x3e004, 2 }, 3353 [GCC_TLMM_CLK_ARES] = { 0x3e008, 2 }, 3354 [GCC_TLMM_BCR] = { 0x3e000 }, 3355 [GCC_UNIPHY0_AHB_CLK_ARES] = { 0x1704c, 2 }, 3356 [GCC_UNIPHY0_BCR] = { 0x17044 }, 3357 [GCC_UNIPHY0_PMA_BCR] = { 0x17098 }, 3358 [GCC_UNIPHY0_SYS_CLK_ARES] = { 0x17048, 2 }, 3359 [GCC_UNIPHY1_AHB_CLK_ARES] = { 0x1705c, 2 }, 3360 [GCC_UNIPHY1_BCR] = { 0x17054 }, 3361 [GCC_UNIPHY1_PMA_BCR] = { 0x1709c }, 3362 [GCC_UNIPHY1_SYS_CLK_ARES] = { 0x17058, 2 }, 3363 [GCC_UNIPHY2_AHB_CLK_ARES] = { 0x1706c, 2 }, 3364 [GCC_UNIPHY2_BCR] = { 0x17064 }, 3365 [GCC_UNIPHY2_PMA_BCR] = { 0x170a0 }, 3366 [GCC_UNIPHY2_SYS_CLK_ARES] = { 0x17068, 2 }, 3367 [GCC_UNIPHY0_XPCS_ARES] = { 0x17050, 2 }, 3368 [GCC_UNIPHY1_XLGPCS_ARES] = { 0x17060, 1 }, 3369 [GCC_UNIPHY1_XPCS_ARES] = { 0x17060, 2 }, 3370 [GCC_UNIPHY2_XLGPCS_ARES] = { 0x17070, 1 }, 3371 [GCC_UNIPHY2_XPCS_ARES] = { 0x17070, 2 }, 3372 [GCC_USB0_AUX_CLK_ARES] = { 0x2c04c, 2 }, 3373 [GCC_USB0_MASTER_CLK_ARES] = { 0x2c044, 2 }, 3374 [GCC_USB0_MOCK_UTMI_CLK_ARES] = { 0x2c050, 2 }, 3375 [GCC_USB0_PHY_BCR] = { 0x2c06c }, 3376 [GCC_USB0_PHY_CFG_AHB_CLK_ARES] = { 0x2c05c, 2 }, 3377 [GCC_USB0_PIPE_CLK_ARES] = { 0x2c054, 2 }, 3378 [GCC_USB0_SLEEP_CLK_ARES] = { 0x2c058, 2 }, 3379 [GCC_USB1_BCR] = { 0x3c000 }, 3380 [GCC_USB1_MASTER_CLK_ARES] = { 0x3c028, 2 }, 3381 [GCC_USB1_MOCK_UTMI_CLK_ARES] = { 0x3c024, 2 }, 3382 [GCC_USB1_PHY_CFG_AHB_CLK_ARES] = { 0x3c01c, 2 }, 3383 [GCC_USB1_SLEEP_CLK_ARES] = { 0x3c020, 2 }, 3384 [GCC_USB3PHY_0_PHY_BCR] = { 0x2c070 }, 3385 [GCC_USB_BCR] = { 0x2c000 }, 3386 }; 3387 3388 static const struct of_device_id gcc_ipq9650_match_table[] = { 3389 { .compatible = "qcom,ipq9650-gcc" }, 3390 { } 3391 }; 3392 MODULE_DEVICE_TABLE(of, gcc_ipq9650_match_table); 3393 3394 static const struct regmap_config gcc_ipq9650_regmap_config = { 3395 .reg_bits = 32, 3396 .reg_stride = 4, 3397 .val_bits = 32, 3398 .max_register = 0x3f024, 3399 .fast_io = true, 3400 }; 3401 3402 static struct clk_hw *gcc_ipq9650_hws[] = { 3403 &gpll0_div2.hw, 3404 &gcc_xo_div4_clk_src.hw, 3405 &gcc_qdss_dap_sync_clk_src.hw, 3406 &gcc_eud_at_div_clk_src.hw, 3407 }; 3408 3409 static const struct qcom_cc_desc gcc_ipq9650_desc = { 3410 .config = &gcc_ipq9650_regmap_config, 3411 .clks = gcc_ipq9650_clocks, 3412 .num_clks = ARRAY_SIZE(gcc_ipq9650_clocks), 3413 .resets = gcc_ipq9650_resets, 3414 .num_resets = ARRAY_SIZE(gcc_ipq9650_resets), 3415 .clk_hws = gcc_ipq9650_hws, 3416 .num_clk_hws = ARRAY_SIZE(gcc_ipq9650_hws), 3417 }; 3418 3419 static int gcc_ipq9650_probe(struct platform_device *pdev) 3420 { 3421 return qcom_cc_probe(pdev, &gcc_ipq9650_desc); 3422 } 3423 3424 static struct platform_driver gcc_ipq9650_driver = { 3425 .probe = gcc_ipq9650_probe, 3426 .driver = { 3427 .name = "qcom,gcc-ipq9650", 3428 .of_match_table = gcc_ipq9650_match_table, 3429 }, 3430 }; 3431 3432 static int __init gcc_ipq9650_init(void) 3433 { 3434 return platform_driver_register(&gcc_ipq9650_driver); 3435 } 3436 core_initcall(gcc_ipq9650_init); 3437 3438 static void __exit gcc_ipq9650_exit(void) 3439 { 3440 platform_driver_unregister(&gcc_ipq9650_driver); 3441 } 3442 module_exit(gcc_ipq9650_exit); 3443 3444 MODULE_DESCRIPTION("QTI GCC IPQ9650 Driver"); 3445 MODULE_LICENSE("GPL"); 3446