1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 4 */ 5 6 #include <linux/clk-provider.h> 7 #include <linux/module.h> 8 #include <linux/platform_device.h> 9 #include <linux/regmap.h> 10 11 #include <dt-bindings/clock/qcom,ipq5210-gcc.h> 12 #include <dt-bindings/reset/qcom,ipq5210-gcc.h> 13 14 #include "clk-alpha-pll.h" 15 #include "clk-branch.h" 16 #include "clk-rcg.h" 17 #include "clk-regmap.h" 18 #include "clk-regmap-divider.h" 19 #include "clk-regmap-mux.h" 20 #include "clk-regmap-phy-mux.h" 21 #include "reset.h" 22 23 enum { 24 DT_XO, 25 DT_SLEEP_CLK, 26 DT_PCIE30_PHY0_PIPE_CLK, 27 DT_PCIE30_PHY1_PIPE_CLK, 28 DT_USB3_PHY0_CC_PIPE_CLK, 29 DT_NSS_CMN_CLK, 30 }; 31 32 enum { 33 P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 34 P_GPLL0_OUT_AUX, 35 P_GPLL0_OUT_MAIN, 36 P_GPLL2_OUT_AUX, 37 P_GPLL2_OUT_MAIN, 38 P_GPLL4_OUT_AUX, 39 P_GPLL4_OUT_MAIN, 40 P_NSS_CMN_CLK, 41 P_SLEEP_CLK, 42 P_USB3PHY_0_PIPE, 43 P_XO, 44 }; 45 46 static const struct clk_parent_data gcc_parent_data_xo = { .index = DT_XO }; 47 48 static struct clk_alpha_pll gpll0_main = { 49 .offset = 0x20000, 50 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], 51 .clkr = { 52 .enable_reg = 0xb000, 53 .enable_mask = BIT(0), 54 .hw.init = &(const struct clk_init_data) { 55 .name = "gpll0_main", 56 .parent_data = &gcc_parent_data_xo, 57 .num_parents = 1, 58 .ops = &clk_alpha_pll_ops, 59 }, 60 }, 61 }; 62 63 static struct clk_fixed_factor gpll0_div2 = { 64 .mult = 1, 65 .div = 2, 66 .hw.init = &(const struct clk_init_data) { 67 .name = "gpll0_div2", 68 .parent_hws = (const struct clk_hw *[]) { 69 &gpll0_main.clkr.hw 70 }, 71 .num_parents = 1, 72 .ops = &clk_fixed_factor_ops, 73 }, 74 }; 75 76 static struct clk_alpha_pll_postdiv gpll0 = { 77 .offset = 0x20000, 78 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], 79 .width = 4, 80 .clkr.hw.init = &(const struct clk_init_data) { 81 .name = "gpll0", 82 .parent_hws = (const struct clk_hw *[]) { 83 &gpll0_main.clkr.hw 84 }, 85 .num_parents = 1, 86 .ops = &clk_alpha_pll_postdiv_ro_ops, 87 }, 88 }; 89 90 static struct clk_alpha_pll gpll2_main = { 91 .offset = 0x21000, 92 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], 93 .clkr = { 94 .enable_reg = 0xb000, 95 .enable_mask = BIT(1), 96 .hw.init = &(const struct clk_init_data) { 97 .name = "gpll2_main", 98 .parent_data = &gcc_parent_data_xo, 99 .num_parents = 1, 100 .ops = &clk_alpha_pll_ops, 101 }, 102 }, 103 }; 104 105 static const struct clk_div_table post_div_table_gpll2[] = { 106 { 0x1, 2 }, 107 { } 108 }; 109 110 static struct clk_alpha_pll_postdiv gpll2 = { 111 .offset = 0x21000, 112 .post_div_table = post_div_table_gpll2, 113 .num_post_div = ARRAY_SIZE(post_div_table_gpll2), 114 .width = 4, 115 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], 116 .clkr.hw.init = &(const struct clk_init_data) { 117 .name = "gpll2", 118 .parent_hws = (const struct clk_hw*[]) { 119 &gpll2_main.clkr.hw, 120 }, 121 .num_parents = 1, 122 .ops = &clk_alpha_pll_postdiv_ro_ops, 123 }, 124 }; 125 126 static struct clk_alpha_pll gpll4_main = { 127 .offset = 0x22000, 128 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], 129 .clkr = { 130 .enable_reg = 0xb000, 131 .enable_mask = BIT(2), 132 .hw.init = &(const struct clk_init_data) { 133 .name = "gpll4_main", 134 .parent_data = &gcc_parent_data_xo, 135 .num_parents = 1, 136 .ops = &clk_alpha_pll_ops, 137 /* 138 * There are no consumers for this GPLL in kernel yet, 139 * (will be added soon), so the clock framework 140 * disables this source. But some of the clocks 141 * initialized by boot loaders uses this source. So we 142 * need to keep this clock ON. Add the 143 * CLK_IGNORE_UNUSED flag so the clock will not be 144 * disabled. Once the consumer in kernel is added, we 145 * can get rid of this flag. 146 */ 147 .flags = CLK_IS_CRITICAL, 148 }, 149 }, 150 }; 151 static const struct parent_map gcc_parent_map_xo[] = { 152 { P_XO, 0 }, 153 }; 154 155 static const struct parent_map gcc_parent_map_0[] = { 156 { P_XO, 0 }, 157 { P_GPLL0_OUT_MAIN, 1 }, 158 { P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 4 }, 159 }; 160 161 static const struct clk_parent_data gcc_parent_data_0[] = { 162 { .index = DT_XO }, 163 { .hw = &gpll0.clkr.hw }, 164 { .hw = &gpll0_div2.hw }, 165 }; 166 167 static const struct parent_map gcc_parent_map_1[] = { 168 { P_XO, 0 }, 169 { P_GPLL0_OUT_MAIN, 1 }, 170 }; 171 172 static const struct clk_parent_data gcc_parent_data_1[] = { 173 { .index = DT_XO }, 174 { .hw = &gpll0.clkr.hw }, 175 }; 176 177 static const struct parent_map gcc_parent_map_2[] = { 178 { P_XO, 0 }, 179 { P_GPLL0_OUT_MAIN, 1 }, 180 { P_GPLL4_OUT_MAIN, 2 }, 181 }; 182 183 static const struct clk_parent_data gcc_parent_data_2[] = { 184 { .index = DT_XO }, 185 { .hw = &gpll0.clkr.hw }, 186 { .hw = &gpll4_main.clkr.hw }, 187 }; 188 189 static const struct parent_map gcc_parent_map_3[] = { 190 { P_XO, 0 }, 191 }; 192 193 static const struct clk_parent_data gcc_parent_data_3[] = { 194 { .index = DT_XO }, 195 }; 196 197 static const struct parent_map gcc_parent_map_4[] = { 198 { P_XO, 0 }, 199 { P_NSS_CMN_CLK, 1 }, 200 { P_GPLL0_OUT_AUX, 2 }, 201 { P_GPLL2_OUT_AUX, 3 }, 202 }; 203 204 static const struct clk_parent_data gcc_parent_data_4[] = { 205 { .index = DT_XO }, 206 { .index = DT_NSS_CMN_CLK }, 207 { .hw = &gpll0.clkr.hw }, 208 { .hw = &gpll2_main.clkr.hw }, 209 }; 210 211 static const struct parent_map gcc_parent_map_5[] = { 212 { P_XO, 0 }, 213 { P_GPLL0_OUT_MAIN, 1 }, 214 { P_GPLL0_OUT_AUX, 2 }, 215 { P_SLEEP_CLK, 6 }, 216 }; 217 218 static const struct clk_parent_data gcc_parent_data_5[] = { 219 { .index = DT_XO }, 220 { .hw = &gpll0.clkr.hw }, 221 { .hw = &gpll0.clkr.hw }, 222 { .index = DT_SLEEP_CLK }, 223 }; 224 225 static const struct parent_map gcc_parent_map_6[] = { 226 { P_XO, 0 }, 227 { P_GPLL0_OUT_MAIN, 1 }, 228 { P_GPLL2_OUT_MAIN, 2 }, 229 { P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 4 }, 230 }; 231 232 static const struct clk_parent_data gcc_parent_data_6[] = { 233 { .index = DT_XO }, 234 { .hw = &gpll0.clkr.hw }, 235 { .hw = &gpll2.clkr.hw }, 236 { .hw = &gpll0_div2.hw }, 237 }; 238 239 static const struct parent_map gcc_parent_map_7[] = { 240 { P_XO, 0 }, 241 { P_GPLL0_OUT_MAIN, 1 }, 242 { P_GPLL4_OUT_MAIN, 2 }, 243 { P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 4 }, 244 }; 245 246 static const struct clk_parent_data gcc_parent_data_7[] = { 247 { .index = DT_XO }, 248 { .hw = &gpll0.clkr.hw }, 249 { .hw = &gpll4_main.clkr.hw }, 250 { .hw = &gpll0_div2.hw }, 251 }; 252 253 static const struct parent_map gcc_parent_map_8[] = { 254 { P_XO, 0 }, 255 { P_GPLL0_OUT_AUX, 2 }, 256 { P_SLEEP_CLK, 6 }, 257 }; 258 259 static const struct clk_parent_data gcc_parent_data_8[] = { 260 { .index = DT_XO }, 261 { .hw = &gpll0.clkr.hw }, 262 { .index = DT_SLEEP_CLK }, 263 }; 264 265 static const struct parent_map gcc_parent_map_9[] = { 266 { P_XO, 0 }, 267 { P_GPLL4_OUT_AUX, 1 }, 268 { P_GPLL0_OUT_MAIN, 3 }, 269 { P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 4 }, 270 }; 271 272 static const struct clk_parent_data gcc_parent_data_9[] = { 273 { .index = DT_XO }, 274 { .hw = &gpll4_main.clkr.hw }, 275 { .hw = &gpll0.clkr.hw }, 276 { .hw = &gpll0_div2.hw }, 277 }; 278 279 static const struct parent_map gcc_parent_map_10[] = { 280 { P_XO, 0 }, 281 { P_GPLL4_OUT_MAIN, 1 }, 282 { P_GPLL0_OUT_AUX, 2 }, 283 { P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 4 }, 284 }; 285 286 static const struct clk_parent_data gcc_parent_data_10[] = { 287 { .index = DT_XO }, 288 { .hw = &gpll4_main.clkr.hw }, 289 { .hw = &gpll0.clkr.hw }, 290 { .hw = &gpll0_div2.hw }, 291 }; 292 293 static const struct parent_map gcc_parent_map_11[] = { 294 { P_XO, 0 }, 295 { P_GPLL4_OUT_MAIN, 1 }, 296 { P_GPLL0_OUT_AUX, 2 }, 297 { P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 4 }, 298 }; 299 300 static const struct clk_parent_data gcc_parent_data_11[] = { 301 { .index = DT_XO }, 302 { .hw = &gpll4_main.clkr.hw }, 303 { .hw = &gpll0.clkr.hw }, 304 { .hw = &gpll0_div2.hw }, 305 }; 306 307 static const struct parent_map gcc_parent_map_12[] = { 308 { P_XO, 0 }, 309 { P_GPLL0_OUT_MAIN, 1 }, 310 { P_GPLL2_OUT_AUX, 2 }, 311 }; 312 313 static const struct clk_parent_data gcc_parent_data_12[] = { 314 { .index = DT_XO }, 315 { .hw = &gpll0.clkr.hw }, 316 { .hw = &gpll2_main.clkr.hw }, 317 }; 318 319 static const struct parent_map gcc_parent_map_13[] = { 320 { P_SLEEP_CLK, 6 }, 321 }; 322 323 static const struct clk_parent_data gcc_parent_data_13[] = { 324 { .index = DT_SLEEP_CLK }, 325 }; 326 327 static const struct freq_tbl ftbl_gcc_adss_pwm_clk_src[] = { 328 F(24000000, P_XO, 1, 0, 0), 329 F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0), 330 { } 331 }; 332 333 static struct clk_rcg2 gcc_adss_pwm_clk_src = { 334 .cmd_rcgr = 0x1c004, 335 .mnd_width = 0, 336 .hid_width = 5, 337 .parent_map = gcc_parent_map_1, 338 .freq_tbl = ftbl_gcc_adss_pwm_clk_src, 339 .clkr.hw.init = &(const struct clk_init_data) { 340 .name = "gcc_adss_pwm_clk_src", 341 .parent_data = gcc_parent_data_1, 342 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 343 .ops = &clk_rcg2_ops, 344 }, 345 }; 346 347 static const struct freq_tbl ftbl_gcc_nss_ts_clk_src[] = { 348 F(24000000, P_XO, 1, 0, 0), 349 { } 350 }; 351 352 static struct clk_rcg2 gcc_nss_ts_clk_src = { 353 .cmd_rcgr = 0x17088, 354 .mnd_width = 0, 355 .hid_width = 5, 356 .parent_map = gcc_parent_map_3, 357 .freq_tbl = ftbl_gcc_nss_ts_clk_src, 358 .clkr.hw.init = &(const struct clk_init_data) { 359 .name = "gcc_nss_ts_clk_src", 360 .parent_data = gcc_parent_data_3, 361 .num_parents = ARRAY_SIZE(gcc_parent_data_3), 362 .ops = &clk_rcg2_ops, 363 }, 364 }; 365 366 static const struct freq_tbl ftbl_gcc_system_noc_bfdcd_clk_src[] = { 367 F(24000000, P_XO, 1, 0, 0), 368 F(133333333, P_GPLL0_OUT_MAIN, 6, 0, 0), 369 F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0), 370 F(266666667, P_GPLL4_OUT_MAIN, 4.5, 0, 0), 371 { } 372 }; 373 374 static struct clk_rcg2 gcc_system_noc_bfdcd_clk_src = { 375 .cmd_rcgr = 0x2e004, 376 .freq_tbl = ftbl_gcc_system_noc_bfdcd_clk_src, 377 .hid_width = 5, 378 .parent_map = gcc_parent_map_7, 379 .clkr.hw.init = &(const struct clk_init_data) { 380 .name = "gcc_system_noc_bfdcd_clk_src", 381 .parent_data = gcc_parent_data_7, 382 .num_parents = ARRAY_SIZE(gcc_parent_data_7), 383 .ops = &clk_rcg2_ops, 384 }, 385 }; 386 387 static const struct freq_tbl ftbl_gcc_nssnoc_memnoc_bfdcd_clk_src[] = { 388 F(429000000, P_NSS_CMN_CLK, 1, 0, 0), 389 { } 390 }; 391 392 static struct clk_rcg2 gcc_nssnoc_memnoc_bfdcd_clk_src = { 393 .cmd_rcgr = 0x17004, 394 .mnd_width = 0, 395 .hid_width = 5, 396 .parent_map = gcc_parent_map_4, 397 .freq_tbl = ftbl_gcc_nssnoc_memnoc_bfdcd_clk_src, 398 .clkr.hw.init = &(const struct clk_init_data) { 399 .name = "gcc_nssnoc_memnoc_bfdcd_clk_src", 400 .parent_data = gcc_parent_data_4, 401 .num_parents = ARRAY_SIZE(gcc_parent_data_4), 402 .ops = &clk_rcg2_ops, 403 }, 404 }; 405 406 static const struct freq_tbl ftbl_gcc_pcie0_axi_m_clk_src[] = { 407 F(200000000, P_GPLL4_OUT_MAIN, 6, 0, 0), 408 { } 409 }; 410 411 static struct clk_rcg2 gcc_pcie0_axi_m_clk_src = { 412 .cmd_rcgr = 0x28018, 413 .mnd_width = 0, 414 .hid_width = 5, 415 .parent_map = gcc_parent_map_2, 416 .freq_tbl = ftbl_gcc_pcie0_axi_m_clk_src, 417 .clkr.hw.init = &(const struct clk_init_data) { 418 .name = "gcc_pcie0_axi_m_clk_src", 419 .parent_data = gcc_parent_data_2, 420 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 421 .ops = &clk_rcg2_ops, 422 }, 423 }; 424 425 static struct clk_rcg2 gcc_pcie0_axi_s_clk_src = { 426 .cmd_rcgr = 0x28020, 427 .mnd_width = 0, 428 .hid_width = 5, 429 .parent_map = gcc_parent_map_2, 430 .freq_tbl = ftbl_gcc_pcie0_axi_m_clk_src, 431 .clkr.hw.init = &(const struct clk_init_data) { 432 .name = "gcc_pcie0_axi_s_clk_src", 433 .parent_data = gcc_parent_data_2, 434 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 435 .ops = &clk_rcg2_ops, 436 }, 437 }; 438 439 static struct clk_rcg2 gcc_pcie0_rchng_clk_src = { 440 .cmd_rcgr = 0x28028, 441 .mnd_width = 0, 442 .hid_width = 5, 443 .parent_map = gcc_parent_map_1, 444 .freq_tbl = ftbl_gcc_adss_pwm_clk_src, 445 .clkr.hw.init = &(const struct clk_init_data) { 446 .name = "gcc_pcie0_rchng_clk_src", 447 .parent_data = gcc_parent_data_1, 448 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 449 .ops = &clk_rcg2_ops, 450 }, 451 }; 452 453 static const struct freq_tbl ftbl_gcc_pcie1_axi_m_clk_src[] = { 454 F(266666667, P_GPLL4_OUT_MAIN, 4.5, 0, 0), 455 { } 456 }; 457 458 static struct clk_rcg2 gcc_pcie1_axi_m_clk_src = { 459 .cmd_rcgr = 0x29018, 460 .mnd_width = 0, 461 .hid_width = 5, 462 .parent_map = gcc_parent_map_2, 463 .freq_tbl = ftbl_gcc_pcie1_axi_m_clk_src, 464 .clkr.hw.init = &(const struct clk_init_data) { 465 .name = "gcc_pcie1_axi_m_clk_src", 466 .parent_data = gcc_parent_data_2, 467 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 468 .ops = &clk_rcg2_ops, 469 }, 470 }; 471 472 static struct clk_rcg2 gcc_pcie1_axi_s_clk_src = { 473 .cmd_rcgr = 0x29020, 474 .mnd_width = 0, 475 .hid_width = 5, 476 .parent_map = gcc_parent_map_2, 477 .freq_tbl = ftbl_gcc_pcie0_axi_m_clk_src, 478 .clkr.hw.init = &(const struct clk_init_data) { 479 .name = "gcc_pcie1_axi_s_clk_src", 480 .parent_data = gcc_parent_data_2, 481 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 482 .ops = &clk_rcg2_ops, 483 }, 484 }; 485 486 static struct clk_rcg2 gcc_pcie1_rchng_clk_src = { 487 .cmd_rcgr = 0x29028, 488 .mnd_width = 0, 489 .hid_width = 5, 490 .parent_map = gcc_parent_map_1, 491 .freq_tbl = ftbl_gcc_adss_pwm_clk_src, 492 .clkr.hw.init = &(const struct clk_init_data) { 493 .name = "gcc_pcie1_rchng_clk_src", 494 .parent_data = gcc_parent_data_1, 495 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 496 .ops = &clk_rcg2_ops, 497 }, 498 }; 499 500 static const struct freq_tbl ftbl_gcc_pcie_aux_clk_src[] = { 501 F(20000000, P_GPLL0_OUT_MAIN, 10, 1, 4), 502 { } 503 }; 504 505 static struct clk_rcg2 gcc_pcie_aux_clk_src = { 506 .cmd_rcgr = 0x28004, 507 .mnd_width = 16, 508 .hid_width = 5, 509 .parent_map = gcc_parent_map_5, 510 .freq_tbl = ftbl_gcc_pcie_aux_clk_src, 511 .clkr.hw.init = &(const struct clk_init_data) { 512 .name = "gcc_pcie_aux_clk_src", 513 .parent_data = gcc_parent_data_5, 514 .num_parents = ARRAY_SIZE(gcc_parent_data_5), 515 .ops = &clk_rcg2_ops, 516 }, 517 }; 518 519 static const struct freq_tbl ftbl_gcc_qupv3_wrap_se0_clk_src[] = { 520 F(960000, P_XO, 10, 2, 5), 521 F(3686636, P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 1, 2, 217), 522 F(4800000, P_XO, 5, 0, 0), 523 F(7373272, P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 1, 4, 217), 524 F(9600000, P_XO, 2.5, 0, 0), 525 F(14746544, P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 1, 8, 217), 526 F(16000000, P_GPLL0_OUT_MAIN, 10, 1, 5), 527 F(24000000, P_XO, 1, 0, 0), 528 F(25000000, P_GPLL0_OUT_MAIN, 16, 1, 2), 529 F(32000000, P_GPLL0_OUT_MAIN, 1, 1, 25), 530 F(40000000, P_GPLL0_OUT_MAIN, 1, 1, 20), 531 F(46400000, P_GPLL0_OUT_MAIN, 2, 29, 250), 532 F(48000000, P_GPLL0_OUT_MAIN, 1, 3, 50), 533 F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0), 534 F(51200000, P_GPLL0_OUT_MAIN, 1, 8, 125), 535 F(56000000, P_GPLL0_OUT_MAIN, 1, 7, 100), 536 F(58986175, P_GPLL0_OUT_MAIN, 1, 16, 217), 537 F(60000000, P_GPLL0_OUT_MAIN, 1, 3, 40), 538 F(64000000, P_GPLL0_OUT_MAIN, 12.5, 0, 0), 539 { } 540 }; 541 542 static struct clk_rcg2 gcc_qupv3_wrap_se0_clk_src = { 543 .cmd_rcgr = 0x4004, 544 .mnd_width = 8, 545 .hid_width = 5, 546 .parent_map = gcc_parent_map_0, 547 .freq_tbl = ftbl_gcc_qupv3_wrap_se0_clk_src, 548 .clkr.hw.init = &(const struct clk_init_data) { 549 .name = "gcc_qupv3_wrap_se0_clk_src", 550 .parent_data = gcc_parent_data_0, 551 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 552 .ops = &clk_rcg2_ops, 553 }, 554 }; 555 556 static struct clk_rcg2 gcc_qupv3_wrap_se1_clk_src = { 557 .cmd_rcgr = 0x5004, 558 .mnd_width = 8, 559 .hid_width = 5, 560 .parent_map = gcc_parent_map_0, 561 .freq_tbl = ftbl_gcc_qupv3_wrap_se0_clk_src, 562 .clkr.hw.init = &(const struct clk_init_data) { 563 .name = "gcc_qupv3_wrap_se1_clk_src", 564 .parent_data = gcc_parent_data_0, 565 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 566 .ops = &clk_rcg2_ops, 567 }, 568 }; 569 570 static struct clk_rcg2 gcc_qupv3_wrap_se2_clk_src = { 571 .cmd_rcgr = 0x2018, 572 .mnd_width = 8, 573 .hid_width = 5, 574 .parent_map = gcc_parent_map_0, 575 .freq_tbl = ftbl_gcc_qupv3_wrap_se0_clk_src, 576 .clkr.hw.init = &(const struct clk_init_data) { 577 .name = "gcc_qupv3_wrap_se2_clk_src", 578 .parent_data = gcc_parent_data_0, 579 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 580 .ops = &clk_rcg2_ops, 581 }, 582 }; 583 584 static struct clk_rcg2 gcc_qupv3_wrap_se3_clk_src = { 585 .cmd_rcgr = 0x2034, 586 .mnd_width = 8, 587 .hid_width = 5, 588 .parent_map = gcc_parent_map_0, 589 .freq_tbl = ftbl_gcc_qupv3_wrap_se0_clk_src, 590 .clkr.hw.init = &(const struct clk_init_data) { 591 .name = "gcc_qupv3_wrap_se3_clk_src", 592 .parent_data = gcc_parent_data_0, 593 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 594 .ops = &clk_rcg2_ops, 595 }, 596 }; 597 598 static struct clk_rcg2 gcc_qupv3_wrap_se4_clk_src = { 599 .cmd_rcgr = 0x3018, 600 .mnd_width = 8, 601 .hid_width = 5, 602 .parent_map = gcc_parent_map_0, 603 .freq_tbl = ftbl_gcc_qupv3_wrap_se0_clk_src, 604 .clkr.hw.init = &(const struct clk_init_data) { 605 .name = "gcc_qupv3_wrap_se4_clk_src", 606 .parent_data = gcc_parent_data_0, 607 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 608 .ops = &clk_rcg2_ops, 609 }, 610 }; 611 612 static struct clk_rcg2 gcc_qupv3_wrap_se5_clk_src = { 613 .cmd_rcgr = 0x3034, 614 .mnd_width = 8, 615 .hid_width = 5, 616 .parent_map = gcc_parent_map_0, 617 .freq_tbl = ftbl_gcc_qupv3_wrap_se0_clk_src, 618 .clkr.hw.init = &(const struct clk_init_data) { 619 .name = "gcc_qupv3_wrap_se5_clk_src", 620 .parent_data = gcc_parent_data_0, 621 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 622 .ops = &clk_rcg2_ops, 623 }, 624 }; 625 626 static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = { 627 F(144000, P_XO, 16, 12, 125), 628 F(400000, P_XO, 12, 1, 5), 629 F(24000000, P_GPLL2_OUT_MAIN, 12, 1, 2), 630 F(48000000, P_GPLL2_OUT_MAIN, 12, 0, 0), 631 F(96000000, P_GPLL2_OUT_MAIN, 6, 0, 0), 632 F(177777778, P_GPLL0_OUT_MAIN, 4.5, 0, 0), 633 F(192000000, P_GPLL2_OUT_MAIN, 3, 0, 0), 634 F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0), 635 { } 636 }; 637 638 static struct clk_rcg2 gcc_sdcc1_apps_clk_src = { 639 .cmd_rcgr = 0x33004, 640 .mnd_width = 8, 641 .hid_width = 5, 642 .parent_map = gcc_parent_map_6, 643 .freq_tbl = ftbl_gcc_sdcc1_apps_clk_src, 644 .clkr.hw.init = &(const struct clk_init_data) { 645 .name = "gcc_sdcc1_apps_clk_src", 646 .parent_data = gcc_parent_data_6, 647 .num_parents = ARRAY_SIZE(gcc_parent_data_6), 648 .ops = &clk_rcg2_floor_ops, 649 }, 650 }; 651 652 static const struct freq_tbl ftbl_gcc_sdcc1_ice_core_clk_src[] = { 653 F(300000000, P_GPLL4_OUT_MAIN, 4, 0, 0), 654 { } 655 }; 656 657 static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src = { 658 .cmd_rcgr = 0x33018, 659 .mnd_width = 8, 660 .hid_width = 5, 661 .parent_map = gcc_parent_map_7, 662 .freq_tbl = ftbl_gcc_sdcc1_ice_core_clk_src, 663 .clkr.hw.init = &(const struct clk_init_data) { 664 .name = "gcc_sdcc1_ice_core_clk_src", 665 .parent_data = gcc_parent_data_7, 666 .num_parents = ARRAY_SIZE(gcc_parent_data_7), 667 .ops = &clk_rcg2_floor_ops, 668 }, 669 }; 670 671 static struct clk_rcg2 gcc_uniphy_sys_clk_src = { 672 .cmd_rcgr = 0x17090, 673 .mnd_width = 0, 674 .hid_width = 5, 675 .parent_map = gcc_parent_map_3, 676 .freq_tbl = ftbl_gcc_nss_ts_clk_src, 677 .clkr.hw.init = &(const struct clk_init_data) { 678 .name = "gcc_uniphy_sys_clk_src", 679 .parent_data = gcc_parent_data_3, 680 .num_parents = ARRAY_SIZE(gcc_parent_data_3), 681 .ops = &clk_rcg2_ops, 682 }, 683 }; 684 685 static struct clk_rcg2 gcc_usb0_aux_clk_src = { 686 .cmd_rcgr = 0x2c018, 687 .mnd_width = 16, 688 .hid_width = 5, 689 .parent_map = gcc_parent_map_8, 690 .freq_tbl = ftbl_gcc_nss_ts_clk_src, 691 .clkr.hw.init = &(const struct clk_init_data) { 692 .name = "gcc_usb0_aux_clk_src", 693 .parent_data = gcc_parent_data_8, 694 .num_parents = ARRAY_SIZE(gcc_parent_data_8), 695 .ops = &clk_rcg2_ops, 696 }, 697 }; 698 699 static const struct freq_tbl ftbl_gcc_usb0_master_clk_src[] = { 700 F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0), 701 { } 702 }; 703 704 static struct clk_rcg2 gcc_usb0_master_clk_src = { 705 .cmd_rcgr = 0x2c004, 706 .mnd_width = 8, 707 .hid_width = 5, 708 .parent_map = gcc_parent_map_0, 709 .freq_tbl = ftbl_gcc_usb0_master_clk_src, 710 .clkr.hw.init = &(const struct clk_init_data) { 711 .name = "gcc_usb0_master_clk_src", 712 .parent_data = gcc_parent_data_0, 713 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 714 .ops = &clk_rcg2_ops, 715 }, 716 }; 717 718 static const struct freq_tbl ftbl_gcc_usb0_mock_utmi_clk_src[] = { 719 F(60000000, P_GPLL4_OUT_AUX, 10, 1, 2), 720 { } 721 }; 722 723 static struct clk_rcg2 gcc_usb0_mock_utmi_clk_src = { 724 .cmd_rcgr = 0x2c02c, 725 .mnd_width = 8, 726 .hid_width = 5, 727 .parent_map = gcc_parent_map_9, 728 .freq_tbl = ftbl_gcc_usb0_mock_utmi_clk_src, 729 .clkr.hw.init = &(const struct clk_init_data) { 730 .name = "gcc_usb0_mock_utmi_clk_src", 731 .parent_data = gcc_parent_data_9, 732 .num_parents = ARRAY_SIZE(gcc_parent_data_9), 733 .ops = &clk_rcg2_ops, 734 }, 735 }; 736 737 static const struct freq_tbl ftbl_gcc_qdss_at_clk_src[] = { 738 F(240000000, P_GPLL4_OUT_MAIN, 5, 0, 0), 739 { } 740 }; 741 742 static struct clk_rcg2 gcc_qdss_at_clk_src = { 743 .cmd_rcgr = 0x2d004, 744 .mnd_width = 0, 745 .hid_width = 5, 746 .parent_map = gcc_parent_map_10, 747 .freq_tbl = ftbl_gcc_qdss_at_clk_src, 748 .clkr.hw.init = &(const struct clk_init_data) { 749 .name = "gcc_qdss_at_clk_src", 750 .parent_data = gcc_parent_data_10, 751 .num_parents = ARRAY_SIZE(gcc_parent_data_10), 752 .ops = &clk_rcg2_ops, 753 }, 754 }; 755 756 static const struct freq_tbl ftbl_gcc_qdss_tsctr_clk_src[] = { 757 F(600000000, P_GPLL4_OUT_MAIN, 2, 0, 0), 758 { } 759 }; 760 761 static struct clk_rcg2 gcc_qdss_tsctr_clk_src = { 762 .cmd_rcgr = 0x2d01c, 763 .mnd_width = 0, 764 .hid_width = 5, 765 .parent_map = gcc_parent_map_10, 766 .freq_tbl = ftbl_gcc_qdss_tsctr_clk_src, 767 .clkr.hw.init = &(const struct clk_init_data) { 768 .name = "gcc_qdss_tsctr_clk_src", 769 .parent_data = gcc_parent_data_10, 770 .num_parents = ARRAY_SIZE(gcc_parent_data_10), 771 .ops = &clk_rcg2_ops, 772 }, 773 }; 774 775 static const struct freq_tbl ftbl_gcc_pcnoc_bfdcd_clk_src[] = { 776 F(24000000, P_XO, 1, 0, 0), 777 F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0), 778 F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0), 779 { } 780 }; 781 782 static struct clk_rcg2 gcc_pcnoc_bfdcd_clk_src = { 783 .cmd_rcgr = 0x31004, 784 .mnd_width = 0, 785 .hid_width = 5, 786 .parent_map = gcc_parent_map_0, 787 .freq_tbl = ftbl_gcc_pcnoc_bfdcd_clk_src, 788 .clkr.hw.init = &(const struct clk_init_data) { 789 .name = "gcc_pcnoc_bfdcd_clk_src", 790 .parent_data = gcc_parent_data_0, 791 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 792 .ops = &clk_rcg2_ops, 793 /* 794 * There are no consumers for this source in kernel yet, 795 * (will be added soon), so the clock framework 796 * disables this source. But some of the clocks 797 * initialized by boot loaders uses this source. So we 798 * need to keep this clock ON. Add the 799 * CLK_IGNORE_UNUSED flag so the clock will not be 800 * disabled. Once the consumer in kernel is added, we 801 * can get rid of this flag. 802 */ 803 .flags = CLK_IS_CRITICAL, 804 }, 805 }; 806 807 static const struct freq_tbl ftbl_gcc_qpic_io_macro_clk_src[] = { 808 F(24000000, P_XO, 1, 0, 0), 809 F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0), 810 F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0), 811 F(320000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), 812 F(400000000, P_GPLL0_OUT_MAIN, 2, 0, 0), 813 { } 814 }; 815 816 static struct clk_rcg2 gcc_qpic_io_macro_clk_src = { 817 .cmd_rcgr = 0x32004, 818 .mnd_width = 0, 819 .hid_width = 5, 820 .parent_map = gcc_parent_map_12, 821 .freq_tbl = ftbl_gcc_qpic_io_macro_clk_src, 822 .clkr.hw.init = &(const struct clk_init_data) { 823 .name = "gcc_qpic_io_macro_clk_src", 824 .parent_data = gcc_parent_data_12, 825 .num_parents = ARRAY_SIZE(gcc_parent_data_12), 826 .ops = &clk_rcg2_ops, 827 }, 828 }; 829 830 static const struct freq_tbl ftbl_gcc_qpic_clk_src[] = { 831 F(24000000, P_XO, 1, 0, 0), 832 F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0), 833 F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0), 834 { } 835 }; 836 837 static struct clk_rcg2 gcc_qpic_clk_src = { 838 .cmd_rcgr = 0x32020, 839 .mnd_width = 0, 840 .hid_width = 5, 841 .parent_map = gcc_parent_map_12, 842 .freq_tbl = ftbl_gcc_qpic_clk_src, 843 .clkr.hw.init = &(const struct clk_init_data) { 844 .name = "gcc_qpic_clk_src", 845 .parent_data = gcc_parent_data_12, 846 .num_parents = ARRAY_SIZE(gcc_parent_data_12), 847 .ops = &clk_rcg2_ops, 848 }, 849 }; 850 851 static const struct freq_tbl ftbl_gcc_pon_tm2x_clk_src[] = { 852 F(342860000, P_GPLL4_OUT_MAIN, 3.5, 0, 0), 853 { } 854 }; 855 856 static struct clk_rcg2 gcc_pon_tm2x_clk_src = { 857 .cmd_rcgr = 0x3c004, 858 .mnd_width = 0, 859 .hid_width = 5, 860 .parent_map = gcc_parent_map_11, 861 .freq_tbl = ftbl_gcc_pon_tm2x_clk_src, 862 .clkr.hw.init = &(const struct clk_init_data) { 863 .name = "gcc_pon_tm2x_clk_src", 864 .parent_data = gcc_parent_data_11, 865 .num_parents = ARRAY_SIZE(gcc_parent_data_11), 866 .ops = &clk_rcg2_ops, 867 }, 868 }; 869 870 static const struct freq_tbl ftbl_gcc_sleep_clk_src[] = { 871 F(32000, P_SLEEP_CLK, 1, 0, 0), 872 { } 873 }; 874 875 static struct clk_rcg2 gcc_sleep_clk_src = { 876 .cmd_rcgr = 0x3400c, 877 .mnd_width = 0, 878 .hid_width = 5, 879 .parent_map = gcc_parent_map_13, 880 .freq_tbl = ftbl_gcc_sleep_clk_src, 881 .clkr.hw.init = &(const struct clk_init_data) { 882 .name = "gcc_sleep_clk_src", 883 .parent_data = gcc_parent_data_13, 884 .num_parents = ARRAY_SIZE(gcc_parent_data_13), 885 .ops = &clk_rcg2_ops, 886 }, 887 }; 888 889 static const struct freq_tbl ftbl_gcc_lpass_sway_clk_src[] = { 890 F(133333333, P_GPLL0_OUT_MAIN, 6, 0, 0), 891 { } 892 }; 893 894 static struct clk_rcg2 gcc_lpass_sway_clk_src = { 895 .cmd_rcgr = 0x27004, 896 .mnd_width = 0, 897 .hid_width = 5, 898 .parent_map = gcc_parent_map_1, 899 .freq_tbl = ftbl_gcc_lpass_sway_clk_src, 900 .clkr.hw.init = &(const struct clk_init_data) { 901 .name = "gcc_lpass_sway_clk_src", 902 .parent_data = gcc_parent_data_1, 903 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 904 .ops = &clk_rcg2_ops, 905 }, 906 }; 907 908 static struct clk_rcg2 gcc_lpass_axim_clk_src = { 909 .cmd_rcgr = 0x2700c, 910 .mnd_width = 0, 911 .hid_width = 5, 912 .parent_map = gcc_parent_map_1, 913 .freq_tbl = ftbl_gcc_lpass_sway_clk_src, 914 .clkr.hw.init = &(const struct clk_init_data) { 915 .name = "gcc_lpass_axim_clk_src", 916 .parent_data = gcc_parent_data_1, 917 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 918 .ops = &clk_rcg2_ops, 919 }, 920 }; 921 922 static struct clk_regmap_div gcc_nssnoc_memnoc_div_clk_src = { 923 .reg = 0x1700c, 924 .shift = 0, 925 .width = 4, 926 .clkr.hw.init = &(const struct clk_init_data) { 927 .name = "gcc_nssnoc_memnoc_div_clk_src", 928 .parent_hws = (const struct clk_hw*[]) { 929 &gcc_nssnoc_memnoc_bfdcd_clk_src.clkr.hw, 930 }, 931 .num_parents = 1, 932 .flags = CLK_SET_RATE_PARENT, 933 .ops = &clk_regmap_div_ro_ops, 934 }, 935 }; 936 937 static struct clk_regmap_div gcc_usb0_mock_utmi_div_clk_src = { 938 .reg = 0x2c040, 939 .shift = 0, 940 .width = 2, 941 .clkr.hw.init = &(const struct clk_init_data) { 942 .name = "gcc_usb0_mock_utmi_div_clk_src", 943 .parent_hws = (const struct clk_hw*[]) { 944 &gcc_usb0_mock_utmi_clk_src.clkr.hw, 945 }, 946 .num_parents = 1, 947 .flags = CLK_SET_RATE_PARENT, 948 .ops = &clk_regmap_div_ro_ops, 949 }, 950 }; 951 952 static struct clk_fixed_factor gcc_pon_tm_div_clk_src = { 953 .mult = 1, 954 .div = 2, 955 .hw.init = &(const struct clk_init_data) { 956 .name = "gcc_pon_tm_div_clk_src", 957 .parent_hws = (const struct clk_hw *[]) { 958 &gcc_pon_tm2x_clk_src.clkr.hw 959 }, 960 .num_parents = 1, 961 .flags = CLK_SET_RATE_PARENT, 962 .ops = &clk_fixed_factor_ops, 963 }, 964 }; 965 966 static struct clk_branch gcc_adss_pwm_clk = { 967 .halt_reg = 0x1c00c, 968 .halt_check = BRANCH_HALT, 969 .clkr = { 970 .enable_reg = 0x1c00c, 971 .enable_mask = BIT(0), 972 .hw.init = &(const struct clk_init_data) { 973 .name = "gcc_adss_pwm_clk", 974 .parent_hws = (const struct clk_hw*[]) { 975 &gcc_adss_pwm_clk_src.clkr.hw, 976 }, 977 .num_parents = 1, 978 .flags = CLK_SET_RATE_PARENT, 979 .ops = &clk_branch2_ops, 980 }, 981 }, 982 }; 983 984 static struct clk_branch gcc_cnoc_pcie0_1lane_s_clk = { 985 .halt_reg = 0x31088, 986 .halt_check = BRANCH_HALT, 987 .clkr = { 988 .enable_reg = 0x31088, 989 .enable_mask = BIT(0), 990 .hw.init = &(const struct clk_init_data) { 991 .name = "gcc_cnoc_pcie0_1lane_s_clk", 992 .parent_hws = (const struct clk_hw*[]) { 993 &gcc_pcie0_axi_s_clk_src.clkr.hw, 994 }, 995 .num_parents = 1, 996 .flags = CLK_SET_RATE_PARENT, 997 .ops = &clk_branch2_ops, 998 }, 999 }, 1000 }; 1001 1002 static struct clk_branch gcc_cnoc_pcie1_2lane_s_clk = { 1003 .halt_reg = 0x3108c, 1004 .halt_check = BRANCH_HALT, 1005 .clkr = { 1006 .enable_reg = 0x3108c, 1007 .enable_mask = BIT(0), 1008 .hw.init = &(const struct clk_init_data) { 1009 .name = "gcc_cnoc_pcie1_2lane_s_clk", 1010 .parent_hws = (const struct clk_hw*[]) { 1011 &gcc_pcie1_axi_s_clk_src.clkr.hw, 1012 }, 1013 .num_parents = 1, 1014 .flags = CLK_SET_RATE_PARENT, 1015 .ops = &clk_branch2_ops, 1016 }, 1017 }, 1018 }; 1019 1020 static struct clk_branch gcc_cnoc_usb_clk = { 1021 .halt_reg = 0x310a8, 1022 .halt_check = BRANCH_HALT, 1023 .clkr = { 1024 .enable_reg = 0x310a8, 1025 .enable_mask = BIT(0), 1026 .hw.init = &(const struct clk_init_data) { 1027 .name = "gcc_cnoc_usb_clk", 1028 .parent_hws = (const struct clk_hw*[]) { 1029 &gcc_usb0_master_clk_src.clkr.hw, 1030 }, 1031 .num_parents = 1, 1032 .flags = CLK_SET_RATE_PARENT, 1033 .ops = &clk_branch2_ops, 1034 }, 1035 }, 1036 }; 1037 1038 static struct clk_branch gcc_mdio_ahb_clk = { 1039 .halt_reg = 0x17040, 1040 .halt_check = BRANCH_HALT, 1041 .clkr = { 1042 .enable_reg = 0x17040, 1043 .enable_mask = BIT(0), 1044 .hw.init = &(const struct clk_init_data) { 1045 .name = "gcc_mdio_ahb_clk", 1046 .parent_hws = (const struct clk_hw*[]) { 1047 &gcc_pcnoc_bfdcd_clk_src.clkr.hw, 1048 }, 1049 .num_parents = 1, 1050 .flags = CLK_SET_RATE_PARENT, 1051 .ops = &clk_branch2_ops, 1052 }, 1053 }, 1054 }; 1055 1056 static struct clk_branch gcc_mdio_gephy_ahb_clk = { 1057 .halt_reg = 0x17098, 1058 .halt_check = BRANCH_HALT, 1059 .clkr = { 1060 .enable_reg = 0x17098, 1061 .enable_mask = BIT(0), 1062 .hw.init = &(const struct clk_init_data) { 1063 .name = "gcc_mdio_gephy_ahb_clk", 1064 .parent_hws = (const struct clk_hw*[]) { 1065 &gcc_pcnoc_bfdcd_clk_src.clkr.hw, 1066 }, 1067 .num_parents = 1, 1068 .flags = CLK_SET_RATE_PARENT, 1069 .ops = &clk_branch2_ops, 1070 }, 1071 }, 1072 }; 1073 1074 static struct clk_branch gcc_nss_ts_clk = { 1075 .halt_reg = 0x17018, 1076 .halt_check = BRANCH_HALT, 1077 .clkr = { 1078 .enable_reg = 0x17018, 1079 .enable_mask = BIT(0), 1080 .hw.init = &(const struct clk_init_data) { 1081 .name = "gcc_nss_ts_clk", 1082 .parent_hws = (const struct clk_hw*[]) { 1083 &gcc_nss_ts_clk_src.clkr.hw, 1084 }, 1085 .num_parents = 1, 1086 .flags = CLK_SET_RATE_PARENT, 1087 .ops = &clk_branch2_ops, 1088 }, 1089 }, 1090 }; 1091 1092 static struct clk_branch gcc_nsscc_clk = { 1093 .halt_reg = 0x17034, 1094 .halt_check = BRANCH_HALT, 1095 .clkr = { 1096 .enable_reg = 0x17034, 1097 .enable_mask = BIT(0), 1098 .hw.init = &(const struct clk_init_data) { 1099 .name = "gcc_nsscc_clk", 1100 .parent_hws = (const struct clk_hw*[]) { 1101 &gcc_pcnoc_bfdcd_clk_src.clkr.hw, 1102 }, 1103 .num_parents = 1, 1104 .flags = CLK_SET_RATE_PARENT, 1105 .ops = &clk_branch2_ops, 1106 }, 1107 }, 1108 }; 1109 1110 static struct clk_branch gcc_nsscfg_clk = { 1111 .halt_reg = 0x1702c, 1112 .halt_check = BRANCH_HALT, 1113 .clkr = { 1114 .enable_reg = 0x1702c, 1115 .enable_mask = BIT(0), 1116 .hw.init = &(const struct clk_init_data) { 1117 .name = "gcc_nsscfg_clk", 1118 .parent_hws = (const struct clk_hw*[]) { 1119 &gcc_pcnoc_bfdcd_clk_src.clkr.hw, 1120 }, 1121 .num_parents = 1, 1122 .flags = CLK_SET_RATE_PARENT, 1123 .ops = &clk_branch2_ops, 1124 }, 1125 }, 1126 }; 1127 1128 static struct clk_branch gcc_nssnoc_atb_clk = { 1129 .halt_reg = 0x17014, 1130 .halt_check = BRANCH_HALT, 1131 .clkr = { 1132 .enable_reg = 0x17014, 1133 .enable_mask = BIT(0), 1134 .hw.init = &(const struct clk_init_data) { 1135 .name = "gcc_nssnoc_atb_clk", 1136 .parent_hws = (const struct clk_hw*[]) { 1137 &gcc_qdss_at_clk_src.clkr.hw, 1138 }, 1139 .num_parents = 1, 1140 .flags = CLK_SET_RATE_PARENT, 1141 .ops = &clk_branch2_ops, 1142 }, 1143 }, 1144 }; 1145 1146 static struct clk_branch gcc_nssnoc_memnoc_1_clk = { 1147 .halt_reg = 0x17084, 1148 .halt_check = BRANCH_HALT, 1149 .clkr = { 1150 .enable_reg = 0x17084, 1151 .enable_mask = BIT(0), 1152 .hw.init = &(const struct clk_init_data) { 1153 .name = "gcc_nssnoc_memnoc_1_clk", 1154 .parent_hws = (const struct clk_hw*[]) { 1155 &gcc_nssnoc_memnoc_div_clk_src.clkr.hw, 1156 }, 1157 .num_parents = 1, 1158 .flags = CLK_SET_RATE_PARENT, 1159 .ops = &clk_branch2_ops, 1160 }, 1161 }, 1162 }; 1163 1164 static struct clk_branch gcc_nssnoc_memnoc_clk = { 1165 .halt_reg = 0x17024, 1166 .halt_check = BRANCH_HALT, 1167 .clkr = { 1168 .enable_reg = 0x17024, 1169 .enable_mask = BIT(0), 1170 .hw.init = &(const struct clk_init_data) { 1171 .name = "gcc_nssnoc_memnoc_clk", 1172 .parent_hws = (const struct clk_hw*[]) { 1173 &gcc_nssnoc_memnoc_div_clk_src.clkr.hw, 1174 }, 1175 .num_parents = 1, 1176 .flags = CLK_SET_RATE_PARENT, 1177 .ops = &clk_branch2_ops, 1178 }, 1179 }, 1180 }; 1181 1182 static struct clk_branch gcc_nssnoc_nsscc_clk = { 1183 .halt_reg = 0x17030, 1184 .halt_check = BRANCH_HALT, 1185 .clkr = { 1186 .enable_reg = 0x17030, 1187 .enable_mask = BIT(0), 1188 .hw.init = &(const struct clk_init_data) { 1189 .name = "gcc_nssnoc_nsscc_clk", 1190 .parent_hws = (const struct clk_hw*[]) { 1191 &gcc_pcnoc_bfdcd_clk_src.clkr.hw, 1192 }, 1193 .num_parents = 1, 1194 .flags = CLK_SET_RATE_PARENT, 1195 .ops = &clk_branch2_ops, 1196 }, 1197 }, 1198 }; 1199 1200 static struct clk_rcg2 gcc_xo_clk_src = { 1201 .cmd_rcgr = 0x34004, 1202 .mnd_width = 0, 1203 .hid_width = 5, 1204 .parent_map = gcc_parent_map_xo, 1205 .freq_tbl = ftbl_gcc_nss_ts_clk_src, 1206 .clkr.hw.init = &(const struct clk_init_data) { 1207 .name = "gcc_xo_clk_src", 1208 .parent_data = &gcc_parent_data_xo, 1209 .num_parents = 1, 1210 .ops = &clk_rcg2_ops, 1211 }, 1212 }; 1213 1214 static struct clk_fixed_factor gcc_xo_div4_clk_src = { 1215 .mult = 1, 1216 .div = 4, 1217 .hw.init = &(const struct clk_init_data) { 1218 .name = "gcc_xo_div4_clk_src", 1219 .parent_hws = (const struct clk_hw *[]) { 1220 &gcc_xo_clk_src.clkr.hw 1221 }, 1222 .num_parents = 1, 1223 .flags = CLK_SET_RATE_PARENT, 1224 .ops = &clk_fixed_factor_ops, 1225 }, 1226 }; 1227 1228 static struct clk_branch gcc_gephy_sys_clk = { 1229 .halt_reg = 0x2a004, 1230 .halt_check = BRANCH_HALT, 1231 .clkr = { 1232 .enable_reg = 0x2a004, 1233 .enable_mask = BIT(0), 1234 .hw.init = &(const struct clk_init_data) { 1235 .name = "gcc_gephy_sys_clk", 1236 .parent_hws = (const struct clk_hw*[]) { 1237 &gcc_xo_clk_src.clkr.hw, 1238 }, 1239 .num_parents = 1, 1240 .flags = CLK_SET_RATE_PARENT, 1241 .ops = &clk_branch2_ops, 1242 }, 1243 }, 1244 }; 1245 1246 static struct clk_branch gcc_nssnoc_pcnoc_1_clk = { 1247 .halt_reg = 0x17080, 1248 .halt_check = BRANCH_HALT, 1249 .clkr = { 1250 .enable_reg = 0x17080, 1251 .enable_mask = BIT(0), 1252 .hw.init = &(const struct clk_init_data) { 1253 .name = "gcc_nssnoc_pcnoc_1_clk", 1254 .parent_hws = (const struct clk_hw*[]) { 1255 &gcc_pcnoc_bfdcd_clk_src.clkr.hw 1256 }, 1257 .num_parents = 1, 1258 .flags = CLK_SET_RATE_PARENT, 1259 .ops = &clk_branch2_ops, 1260 }, 1261 }, 1262 }; 1263 1264 static struct clk_branch gcc_nssnoc_qosgen_ref_clk = { 1265 .halt_reg = 0x1701c, 1266 .halt_check = BRANCH_HALT, 1267 .clkr = { 1268 .enable_reg = 0x1701c, 1269 .enable_mask = BIT(0), 1270 .hw.init = &(const struct clk_init_data) { 1271 .name = "gcc_nssnoc_qosgen_ref_clk", 1272 .parent_hws = (const struct clk_hw *[]){ 1273 &gcc_xo_div4_clk_src.hw 1274 }, 1275 .num_parents = 1, 1276 .flags = CLK_SET_RATE_PARENT, 1277 .ops = &clk_branch2_ops, 1278 }, 1279 }, 1280 }; 1281 1282 static struct clk_branch gcc_nssnoc_snoc_1_clk = { 1283 .halt_reg = 0x1707c, 1284 .halt_check = BRANCH_HALT, 1285 .clkr = { 1286 .enable_reg = 0x1707c, 1287 .enable_mask = BIT(0), 1288 .hw.init = &(const struct clk_init_data) { 1289 .name = "gcc_nssnoc_snoc_1_clk", 1290 .parent_hws = (const struct clk_hw*[]) { 1291 &gcc_system_noc_bfdcd_clk_src.clkr.hw 1292 }, 1293 .num_parents = 1, 1294 .flags = CLK_SET_RATE_PARENT, 1295 .ops = &clk_branch2_ops, 1296 }, 1297 }, 1298 }; 1299 1300 static struct clk_branch gcc_nssnoc_snoc_clk = { 1301 .halt_reg = 0x17028, 1302 .halt_check = BRANCH_HALT, 1303 .clkr = { 1304 .enable_reg = 0x17028, 1305 .enable_mask = BIT(0), 1306 .hw.init = &(const struct clk_init_data) { 1307 .name = "gcc_nssnoc_snoc_clk", 1308 .parent_hws = (const struct clk_hw*[]) { 1309 &gcc_system_noc_bfdcd_clk_src.clkr.hw, 1310 }, 1311 .num_parents = 1, 1312 .flags = CLK_SET_RATE_PARENT, 1313 .ops = &clk_branch2_ops, 1314 }, 1315 }, 1316 }; 1317 1318 static struct clk_branch gcc_nssnoc_timeout_ref_clk = { 1319 .halt_reg = 0x17020, 1320 .halt_check = BRANCH_HALT, 1321 .clkr = { 1322 .enable_reg = 0x17020, 1323 .enable_mask = BIT(0), 1324 .hw.init = &(const struct clk_init_data) { 1325 .name = "gcc_nssnoc_timeout_ref_clk", 1326 .parent_hws = (const struct clk_hw*[]) { 1327 &gcc_xo_div4_clk_src.hw, 1328 }, 1329 .num_parents = 1, 1330 .flags = CLK_SET_RATE_PARENT, 1331 .ops = &clk_branch2_ops, 1332 }, 1333 }, 1334 }; 1335 1336 static struct clk_branch gcc_nssnoc_xo_dcd_clk = { 1337 .halt_reg = 0x17074, 1338 .halt_check = BRANCH_HALT, 1339 .clkr = { 1340 .enable_reg = 0x17074, 1341 .enable_mask = BIT(0), 1342 .hw.init = &(const struct clk_init_data) { 1343 .name = "gcc_nssnoc_xo_dcd_clk", 1344 .parent_hws = (const struct clk_hw*[]) { 1345 &gcc_xo_clk_src.clkr.hw, 1346 }, 1347 .num_parents = 1, 1348 .flags = CLK_SET_RATE_PARENT, 1349 .ops = &clk_branch2_ops, 1350 }, 1351 }, 1352 }; 1353 1354 static struct clk_branch gcc_pcie0_ahb_clk = { 1355 .halt_reg = 0x28030, 1356 .halt_check = BRANCH_HALT, 1357 .clkr = { 1358 .enable_reg = 0x28030, 1359 .enable_mask = BIT(0), 1360 .hw.init = &(const struct clk_init_data) { 1361 .name = "gcc_pcie0_ahb_clk", 1362 .parent_hws = (const struct clk_hw*[]) { 1363 &gcc_pcnoc_bfdcd_clk_src.clkr.hw, 1364 }, 1365 .num_parents = 1, 1366 .flags = CLK_SET_RATE_PARENT, 1367 .ops = &clk_branch2_ops, 1368 }, 1369 }, 1370 }; 1371 1372 static struct clk_branch gcc_pcie0_aux_clk = { 1373 .halt_reg = 0x28070, 1374 .halt_check = BRANCH_HALT, 1375 .clkr = { 1376 .enable_reg = 0x28070, 1377 .enable_mask = BIT(0), 1378 .hw.init = &(const struct clk_init_data) { 1379 .name = "gcc_pcie0_aux_clk", 1380 .parent_hws = (const struct clk_hw*[]) { 1381 &gcc_pcie_aux_clk_src.clkr.hw, 1382 }, 1383 .num_parents = 1, 1384 .flags = CLK_SET_RATE_PARENT, 1385 .ops = &clk_branch2_ops, 1386 }, 1387 }, 1388 }; 1389 1390 static struct clk_branch gcc_pcie0_axi_m_clk = { 1391 .halt_reg = 0x28038, 1392 .halt_check = BRANCH_HALT, 1393 .clkr = { 1394 .enable_reg = 0x28038, 1395 .enable_mask = BIT(0), 1396 .hw.init = &(const struct clk_init_data) { 1397 .name = "gcc_pcie0_axi_m_clk", 1398 .parent_hws = (const struct clk_hw*[]) { 1399 &gcc_pcie0_axi_m_clk_src.clkr.hw, 1400 }, 1401 .num_parents = 1, 1402 .flags = CLK_SET_RATE_PARENT, 1403 .ops = &clk_branch2_ops, 1404 }, 1405 }, 1406 }; 1407 1408 static struct clk_branch gcc_pcie0_axi_s_bridge_clk = { 1409 .halt_reg = 0x28048, 1410 .halt_check = BRANCH_HALT, 1411 .clkr = { 1412 .enable_reg = 0x28048, 1413 .enable_mask = BIT(0), 1414 .hw.init = &(const struct clk_init_data) { 1415 .name = "gcc_pcie0_axi_s_bridge_clk", 1416 .parent_hws = (const struct clk_hw*[]) { 1417 &gcc_pcie0_axi_s_clk_src.clkr.hw, 1418 }, 1419 .num_parents = 1, 1420 .flags = CLK_SET_RATE_PARENT, 1421 .ops = &clk_branch2_ops, 1422 }, 1423 }, 1424 }; 1425 1426 static struct clk_branch gcc_pcie0_axi_s_clk = { 1427 .halt_reg = 0x28040, 1428 .halt_check = BRANCH_HALT, 1429 .clkr = { 1430 .enable_reg = 0x28040, 1431 .enable_mask = BIT(0), 1432 .hw.init = &(const struct clk_init_data) { 1433 .name = "gcc_pcie0_axi_s_clk", 1434 .parent_hws = (const struct clk_hw*[]) { 1435 &gcc_pcie0_axi_s_clk_src.clkr.hw, 1436 }, 1437 .num_parents = 1, 1438 .flags = CLK_SET_RATE_PARENT, 1439 .ops = &clk_branch2_ops, 1440 }, 1441 }, 1442 }; 1443 1444 static struct clk_regmap_phy_mux gcc_pcie0_pipe_clk_src = { 1445 .reg = 0x28064, 1446 .clkr = { 1447 .hw.init = &(const struct clk_init_data) { 1448 .name = "pcie0_pipe_clk_src", 1449 .parent_data = &(const struct clk_parent_data) { 1450 .index = DT_PCIE30_PHY0_PIPE_CLK, 1451 }, 1452 .num_parents = 1, 1453 .ops = &clk_regmap_phy_mux_ops, 1454 }, 1455 }, 1456 }; 1457 1458 static struct clk_branch gcc_pcie0_pipe_clk = { 1459 .halt_reg = 0x28068, 1460 .halt_check = BRANCH_HALT_DELAY, 1461 .clkr = { 1462 .enable_reg = 0x28068, 1463 .enable_mask = BIT(0), 1464 .hw.init = &(const struct clk_init_data) { 1465 .name = "gcc_pcie0_pipe_clk", 1466 .parent_hws = (const struct clk_hw *[]) { 1467 &gcc_pcie0_pipe_clk_src.clkr.hw 1468 }, 1469 .num_parents = 1, 1470 .flags = CLK_SET_RATE_PARENT, 1471 .ops = &clk_branch2_ops, 1472 }, 1473 }, 1474 }; 1475 1476 static struct clk_branch gcc_pcie1_ahb_clk = { 1477 .halt_reg = 0x29030, 1478 .halt_check = BRANCH_HALT, 1479 .clkr = { 1480 .enable_reg = 0x29030, 1481 .enable_mask = BIT(0), 1482 .hw.init = &(const struct clk_init_data) { 1483 .name = "gcc_pcie1_ahb_clk", 1484 .parent_hws = (const struct clk_hw*[]) { 1485 &gcc_pcnoc_bfdcd_clk_src.clkr.hw, 1486 }, 1487 .num_parents = 1, 1488 .flags = CLK_SET_RATE_PARENT, 1489 .ops = &clk_branch2_ops, 1490 }, 1491 }, 1492 }; 1493 1494 static struct clk_branch gcc_pcie1_aux_clk = { 1495 .halt_reg = 0x29074, 1496 .halt_check = BRANCH_HALT, 1497 .clkr = { 1498 .enable_reg = 0x29074, 1499 .enable_mask = BIT(0), 1500 .hw.init = &(const struct clk_init_data) { 1501 .name = "gcc_pcie1_aux_clk", 1502 .parent_hws = (const struct clk_hw*[]) { 1503 &gcc_pcie_aux_clk_src.clkr.hw, 1504 }, 1505 .num_parents = 1, 1506 .flags = CLK_SET_RATE_PARENT, 1507 .ops = &clk_branch2_ops, 1508 }, 1509 }, 1510 }; 1511 1512 static struct clk_branch gcc_pcie1_axi_m_clk = { 1513 .halt_reg = 0x29038, 1514 .halt_check = BRANCH_HALT, 1515 .clkr = { 1516 .enable_reg = 0x29038, 1517 .enable_mask = BIT(0), 1518 .hw.init = &(const struct clk_init_data) { 1519 .name = "gcc_pcie1_axi_m_clk", 1520 .parent_hws = (const struct clk_hw*[]) { 1521 &gcc_pcie1_axi_m_clk_src.clkr.hw, 1522 }, 1523 .num_parents = 1, 1524 .flags = CLK_SET_RATE_PARENT, 1525 .ops = &clk_branch2_ops, 1526 }, 1527 }, 1528 }; 1529 1530 static struct clk_branch gcc_pcie1_axi_s_bridge_clk = { 1531 .halt_reg = 0x29048, 1532 .halt_check = BRANCH_HALT, 1533 .clkr = { 1534 .enable_reg = 0x29048, 1535 .enable_mask = BIT(0), 1536 .hw.init = &(const struct clk_init_data) { 1537 .name = "gcc_pcie1_axi_s_bridge_clk", 1538 .parent_hws = (const struct clk_hw*[]) { 1539 &gcc_pcie1_axi_s_clk_src.clkr.hw, 1540 }, 1541 .num_parents = 1, 1542 .flags = CLK_SET_RATE_PARENT, 1543 .ops = &clk_branch2_ops, 1544 }, 1545 }, 1546 }; 1547 1548 static struct clk_branch gcc_pcie1_axi_s_clk = { 1549 .halt_reg = 0x29040, 1550 .halt_check = BRANCH_HALT, 1551 .clkr = { 1552 .enable_reg = 0x29040, 1553 .enable_mask = BIT(0), 1554 .hw.init = &(const struct clk_init_data) { 1555 .name = "gcc_pcie1_axi_s_clk", 1556 .parent_hws = (const struct clk_hw*[]) { 1557 &gcc_pcie1_axi_s_clk_src.clkr.hw, 1558 }, 1559 .num_parents = 1, 1560 .flags = CLK_SET_RATE_PARENT, 1561 .ops = &clk_branch2_ops, 1562 }, 1563 }, 1564 }; 1565 1566 static struct clk_regmap_phy_mux gcc_pcie1_pipe_clk_src = { 1567 .reg = 0x29064, 1568 .clkr = { 1569 .hw.init = &(const struct clk_init_data) { 1570 .name = "pcie1_pipe_clk_src", 1571 .parent_data = &(const struct clk_parent_data) { 1572 .index = DT_PCIE30_PHY1_PIPE_CLK, 1573 }, 1574 .num_parents = 1, 1575 .ops = &clk_regmap_phy_mux_ops, 1576 }, 1577 }, 1578 }; 1579 1580 static struct clk_branch gcc_pcie1_pipe_clk = { 1581 .halt_reg = 0x29068, 1582 .halt_check = BRANCH_HALT_DELAY, 1583 .clkr = { 1584 .enable_reg = 0x29068, 1585 .enable_mask = BIT(0), 1586 .hw.init = &(const struct clk_init_data) { 1587 .name = "gcc_pcie1_pipe_clk", 1588 .parent_hws = (const struct clk_hw *[]) { 1589 &gcc_pcie1_pipe_clk_src.clkr.hw 1590 }, 1591 .num_parents = 1, 1592 .flags = CLK_SET_RATE_PARENT, 1593 .ops = &clk_branch2_ops, 1594 }, 1595 }, 1596 }; 1597 1598 static struct clk_branch gcc_qrng_ahb_clk = { 1599 .halt_reg = 0x13024, 1600 .halt_check = BRANCH_HALT_VOTED, 1601 .clkr = { 1602 .enable_reg = 0xb004, 1603 .enable_mask = BIT(10), 1604 .hw.init = &(const struct clk_init_data) { 1605 .name = "gcc_qrng_ahb_clk", 1606 .parent_hws = (const struct clk_hw*[]) { 1607 &gcc_pcnoc_bfdcd_clk_src.clkr.hw, 1608 }, 1609 .num_parents = 1, 1610 .flags = CLK_SET_RATE_PARENT, 1611 .ops = &clk_branch2_ops, 1612 }, 1613 }, 1614 }; 1615 1616 static struct clk_branch gcc_qupv3_ahb_mst_clk = { 1617 .halt_reg = 0x1014, 1618 .halt_check = BRANCH_HALT_VOTED, 1619 .clkr = { 1620 .enable_reg = 0xb004, 1621 .enable_mask = BIT(14), 1622 .hw.init = &(const struct clk_init_data) { 1623 .name = "gcc_qupv3_ahb_mst_clk", 1624 .parent_hws = (const struct clk_hw*[]) { 1625 &gcc_pcnoc_bfdcd_clk_src.clkr.hw, 1626 }, 1627 .num_parents = 1, 1628 .flags = CLK_SET_RATE_PARENT, 1629 .ops = &clk_branch2_ops, 1630 }, 1631 }, 1632 }; 1633 1634 static struct clk_branch gcc_qupv3_ahb_slv_clk = { 1635 .halt_reg = 0x102c, 1636 .halt_check = BRANCH_HALT_VOTED, 1637 .clkr = { 1638 .enable_reg = 0xb004, 1639 .enable_mask = BIT(4), 1640 .hw.init = &(const struct clk_init_data) { 1641 .name = "gcc_qupv3_ahb_slv_clk", 1642 .parent_hws = (const struct clk_hw*[]) { 1643 &gcc_pcnoc_bfdcd_clk_src.clkr.hw, 1644 }, 1645 .num_parents = 1, 1646 .flags = CLK_SET_RATE_PARENT, 1647 .ops = &clk_branch2_ops, 1648 }, 1649 }, 1650 }; 1651 1652 static struct clk_branch gcc_qupv3_wrap_se0_clk = { 1653 .halt_reg = 0x4020, 1654 .halt_check = BRANCH_HALT, 1655 .clkr = { 1656 .enable_reg = 0x4020, 1657 .enable_mask = BIT(0), 1658 .hw.init = &(const struct clk_init_data) { 1659 .name = "gcc_qupv3_wrap_se0_clk", 1660 .parent_hws = (const struct clk_hw*[]) { 1661 &gcc_qupv3_wrap_se0_clk_src.clkr.hw, 1662 }, 1663 .num_parents = 1, 1664 .flags = CLK_SET_RATE_PARENT, 1665 .ops = &clk_branch2_ops, 1666 }, 1667 }, 1668 }; 1669 1670 static struct clk_branch gcc_qupv3_wrap_se1_clk = { 1671 .halt_reg = 0x5020, 1672 .halt_check = BRANCH_HALT, 1673 .clkr = { 1674 .enable_reg = 0x5020, 1675 .enable_mask = BIT(0), 1676 .hw.init = &(const struct clk_init_data) { 1677 .name = "gcc_qupv3_wrap_se1_clk", 1678 .parent_hws = (const struct clk_hw*[]) { 1679 &gcc_qupv3_wrap_se1_clk_src.clkr.hw, 1680 }, 1681 .num_parents = 1, 1682 .flags = CLK_SET_RATE_PARENT, 1683 .ops = &clk_branch2_ops, 1684 }, 1685 }, 1686 }; 1687 1688 static struct clk_branch gcc_qupv3_wrap_se2_clk = { 1689 .halt_reg = 0x202c, 1690 .halt_check = BRANCH_HALT, 1691 .clkr = { 1692 .enable_reg = 0x202c, 1693 .enable_mask = BIT(0), 1694 .hw.init = &(const struct clk_init_data) { 1695 .name = "gcc_qupv3_wrap_se2_clk", 1696 .parent_hws = (const struct clk_hw*[]) { 1697 &gcc_qupv3_wrap_se2_clk_src.clkr.hw, 1698 }, 1699 .num_parents = 1, 1700 .flags = CLK_SET_RATE_PARENT, 1701 .ops = &clk_branch2_ops, 1702 }, 1703 }, 1704 }; 1705 1706 static struct clk_branch gcc_qupv3_wrap_se3_clk = { 1707 .halt_reg = 0x2048, 1708 .halt_check = BRANCH_HALT, 1709 .clkr = { 1710 .enable_reg = 0x2048, 1711 .enable_mask = BIT(0), 1712 .hw.init = &(const struct clk_init_data) { 1713 .name = "gcc_qupv3_wrap_se3_clk", 1714 .parent_hws = (const struct clk_hw*[]) { 1715 &gcc_qupv3_wrap_se3_clk_src.clkr.hw, 1716 }, 1717 .num_parents = 1, 1718 .flags = CLK_SET_RATE_PARENT, 1719 .ops = &clk_branch2_ops, 1720 }, 1721 }, 1722 }; 1723 1724 static struct clk_branch gcc_qupv3_wrap_se4_clk = { 1725 .halt_reg = 0x302c, 1726 .halt_check = BRANCH_HALT, 1727 .clkr = { 1728 .enable_reg = 0x302c, 1729 .enable_mask = BIT(0), 1730 .hw.init = &(const struct clk_init_data) { 1731 .name = "gcc_qupv3_wrap_se4_clk", 1732 .parent_hws = (const struct clk_hw*[]) { 1733 &gcc_qupv3_wrap_se4_clk_src.clkr.hw, 1734 }, 1735 .num_parents = 1, 1736 .flags = CLK_SET_RATE_PARENT, 1737 .ops = &clk_branch2_ops, 1738 }, 1739 }, 1740 }; 1741 1742 static struct clk_branch gcc_qupv3_wrap_se5_clk = { 1743 .halt_reg = 0x3048, 1744 .halt_check = BRANCH_HALT, 1745 .clkr = { 1746 .enable_reg = 0x3048, 1747 .enable_mask = BIT(0), 1748 .hw.init = &(const struct clk_init_data) { 1749 .name = "gcc_qupv3_wrap_se5_clk", 1750 .parent_hws = (const struct clk_hw*[]) { 1751 &gcc_qupv3_wrap_se5_clk_src.clkr.hw, 1752 }, 1753 .num_parents = 1, 1754 .flags = CLK_SET_RATE_PARENT, 1755 .ops = &clk_branch2_ops, 1756 }, 1757 }, 1758 }; 1759 1760 static struct clk_branch gcc_sdcc1_ahb_clk = { 1761 .halt_reg = 0x3303c, 1762 .halt_check = BRANCH_HALT, 1763 .clkr = { 1764 .enable_reg = 0x3303c, 1765 .enable_mask = BIT(0), 1766 .hw.init = &(const struct clk_init_data) { 1767 .name = "gcc_sdcc1_ahb_clk", 1768 .parent_hws = (const struct clk_hw*[]) { 1769 &gcc_pcnoc_bfdcd_clk_src.clkr.hw 1770 }, 1771 .num_parents = 1, 1772 .flags = CLK_SET_RATE_PARENT, 1773 .ops = &clk_branch2_ops, 1774 }, 1775 }, 1776 }; 1777 1778 static struct clk_branch gcc_sdcc1_apps_clk = { 1779 .halt_reg = 0x3302c, 1780 .halt_check = BRANCH_HALT, 1781 .clkr = { 1782 .enable_reg = 0x3302c, 1783 .enable_mask = BIT(0), 1784 .hw.init = &(const struct clk_init_data) { 1785 .name = "gcc_sdcc1_apps_clk", 1786 .parent_hws = (const struct clk_hw*[]) { 1787 &gcc_sdcc1_apps_clk_src.clkr.hw, 1788 }, 1789 .num_parents = 1, 1790 .flags = CLK_SET_RATE_PARENT, 1791 .ops = &clk_branch2_ops, 1792 }, 1793 }, 1794 }; 1795 1796 static struct clk_branch gcc_sdcc1_ice_core_clk = { 1797 .halt_reg = 0x33034, 1798 .halt_check = BRANCH_HALT, 1799 .clkr = { 1800 .enable_reg = 0x33034, 1801 .enable_mask = BIT(0), 1802 .hw.init = &(const struct clk_init_data) { 1803 .name = "gcc_sdcc1_ice_core_clk", 1804 .parent_hws = (const struct clk_hw*[]) { 1805 &gcc_sdcc1_ice_core_clk_src.clkr.hw, 1806 }, 1807 .num_parents = 1, 1808 .flags = CLK_SET_RATE_PARENT, 1809 .ops = &clk_branch2_ops, 1810 }, 1811 }, 1812 }; 1813 1814 static struct clk_branch gcc_snoc_pcie0_axi_m_clk = { 1815 .halt_reg = 0x2e04c, 1816 .halt_check = BRANCH_HALT, 1817 .clkr = { 1818 .enable_reg = 0x2e04c, 1819 .enable_mask = BIT(0), 1820 .hw.init = &(const struct clk_init_data) { 1821 .name = "gcc_snoc_pcie0_axi_m_clk", 1822 .parent_hws = (const struct clk_hw*[]) { 1823 &gcc_pcie0_axi_m_clk_src.clkr.hw, 1824 }, 1825 .num_parents = 1, 1826 .flags = CLK_SET_RATE_PARENT, 1827 .ops = &clk_branch2_ops, 1828 }, 1829 }, 1830 }; 1831 1832 static struct clk_branch gcc_snoc_pcie1_axi_m_clk = { 1833 .halt_reg = 0x2e050, 1834 .halt_check = BRANCH_HALT, 1835 .clkr = { 1836 .enable_reg = 0x2e050, 1837 .enable_mask = BIT(0), 1838 .hw.init = &(const struct clk_init_data) { 1839 .name = "gcc_snoc_pcie1_axi_m_clk", 1840 .parent_hws = (const struct clk_hw*[]) { 1841 &gcc_pcie1_axi_m_clk_src.clkr.hw, 1842 }, 1843 .num_parents = 1, 1844 .flags = CLK_SET_RATE_PARENT, 1845 .ops = &clk_branch2_ops, 1846 }, 1847 }, 1848 }; 1849 1850 static struct clk_branch gcc_uniphy0_ahb_clk = { 1851 .halt_reg = 0x1704c, 1852 .halt_check = BRANCH_HALT, 1853 .clkr = { 1854 .enable_reg = 0x1704c, 1855 .enable_mask = BIT(0), 1856 .hw.init = &(const struct clk_init_data) { 1857 .name = "gcc_uniphy0_ahb_clk", 1858 .parent_hws = (const struct clk_hw*[]) { 1859 &gcc_pcnoc_bfdcd_clk_src.clkr.hw, 1860 }, 1861 .num_parents = 1, 1862 .flags = CLK_SET_RATE_PARENT, 1863 .ops = &clk_branch2_ops, 1864 }, 1865 }, 1866 }; 1867 1868 static struct clk_branch gcc_uniphy0_sys_clk = { 1869 .halt_reg = 0x17048, 1870 .halt_check = BRANCH_HALT, 1871 .clkr = { 1872 .enable_reg = 0x17048, 1873 .enable_mask = BIT(0), 1874 .hw.init = &(const struct clk_init_data) { 1875 .name = "gcc_uniphy0_sys_clk", 1876 .parent_hws = (const struct clk_hw*[]) { 1877 &gcc_uniphy_sys_clk_src.clkr.hw, 1878 }, 1879 .num_parents = 1, 1880 .flags = CLK_SET_RATE_PARENT, 1881 .ops = &clk_branch2_ops, 1882 }, 1883 }, 1884 }; 1885 1886 static struct clk_branch gcc_uniphy1_ahb_clk = { 1887 .halt_reg = 0x1705c, 1888 .halt_check = BRANCH_HALT, 1889 .clkr = { 1890 .enable_reg = 0x1705c, 1891 .enable_mask = BIT(0), 1892 .hw.init = &(const struct clk_init_data) { 1893 .name = "gcc_uniphy1_ahb_clk", 1894 .parent_hws = (const struct clk_hw*[]) { 1895 &gcc_pcnoc_bfdcd_clk_src.clkr.hw, 1896 }, 1897 .num_parents = 1, 1898 .flags = CLK_SET_RATE_PARENT, 1899 .ops = &clk_branch2_ops, 1900 }, 1901 }, 1902 }; 1903 1904 static struct clk_branch gcc_uniphy1_sys_clk = { 1905 .halt_reg = 0x17058, 1906 .halt_check = BRANCH_HALT, 1907 .clkr = { 1908 .enable_reg = 0x17058, 1909 .enable_mask = BIT(0), 1910 .hw.init = &(const struct clk_init_data) { 1911 .name = "gcc_uniphy1_sys_clk", 1912 .parent_hws = (const struct clk_hw*[]) { 1913 &gcc_uniphy_sys_clk_src.clkr.hw, 1914 }, 1915 .num_parents = 1, 1916 .flags = CLK_SET_RATE_PARENT, 1917 .ops = &clk_branch2_ops, 1918 }, 1919 }, 1920 }; 1921 1922 static struct clk_branch gcc_uniphy2_ahb_clk = { 1923 .halt_reg = 0x1706c, 1924 .halt_check = BRANCH_HALT, 1925 .clkr = { 1926 .enable_reg = 0x1706c, 1927 .enable_mask = BIT(0), 1928 .hw.init = &(const struct clk_init_data) { 1929 .name = "gcc_uniphy2_ahb_clk", 1930 .parent_hws = (const struct clk_hw*[]) { 1931 &gcc_pcnoc_bfdcd_clk_src.clkr.hw, 1932 }, 1933 .num_parents = 1, 1934 .flags = CLK_SET_RATE_PARENT, 1935 .ops = &clk_branch2_ops, 1936 }, 1937 }, 1938 }; 1939 1940 static struct clk_branch gcc_uniphy2_sys_clk = { 1941 .halt_reg = 0x17068, 1942 .halt_check = BRANCH_HALT, 1943 .clkr = { 1944 .enable_reg = 0x17068, 1945 .enable_mask = BIT(0), 1946 .hw.init = &(const struct clk_init_data) { 1947 .name = "gcc_uniphy2_sys_clk", 1948 .parent_hws = (const struct clk_hw*[]) { 1949 &gcc_uniphy_sys_clk_src.clkr.hw, 1950 }, 1951 .num_parents = 1, 1952 .flags = CLK_SET_RATE_PARENT, 1953 .ops = &clk_branch2_ops, 1954 }, 1955 }, 1956 }; 1957 1958 static struct clk_branch gcc_usb0_aux_clk = { 1959 .halt_reg = 0x2c04c, 1960 .halt_check = BRANCH_HALT, 1961 .clkr = { 1962 .enable_reg = 0x2c04c, 1963 .enable_mask = BIT(0), 1964 .hw.init = &(const struct clk_init_data) { 1965 .name = "gcc_usb0_aux_clk", 1966 .parent_hws = (const struct clk_hw*[]) { 1967 &gcc_usb0_aux_clk_src.clkr.hw, 1968 }, 1969 .num_parents = 1, 1970 .flags = CLK_SET_RATE_PARENT, 1971 .ops = &clk_branch2_ops, 1972 }, 1973 }, 1974 }; 1975 1976 static struct clk_branch gcc_usb0_master_clk = { 1977 .halt_reg = 0x2c044, 1978 .halt_check = BRANCH_HALT, 1979 .clkr = { 1980 .enable_reg = 0x2c044, 1981 .enable_mask = BIT(0), 1982 .hw.init = &(const struct clk_init_data) { 1983 .name = "gcc_usb0_master_clk", 1984 .parent_hws = (const struct clk_hw*[]) { 1985 &gcc_usb0_master_clk_src.clkr.hw, 1986 }, 1987 .num_parents = 1, 1988 .flags = CLK_SET_RATE_PARENT, 1989 .ops = &clk_branch2_ops, 1990 }, 1991 }, 1992 }; 1993 1994 static struct clk_branch gcc_usb0_mock_utmi_clk = { 1995 .halt_reg = 0x2c050, 1996 .halt_check = BRANCH_HALT, 1997 .clkr = { 1998 .enable_reg = 0x2c050, 1999 .enable_mask = BIT(0), 2000 .hw.init = &(const struct clk_init_data) { 2001 .name = "gcc_usb0_mock_utmi_clk", 2002 .parent_hws = (const struct clk_hw*[]) { 2003 &gcc_usb0_mock_utmi_div_clk_src.clkr.hw, 2004 }, 2005 .num_parents = 1, 2006 .flags = CLK_SET_RATE_PARENT, 2007 .ops = &clk_branch2_ops, 2008 }, 2009 }, 2010 }; 2011 2012 static struct clk_branch gcc_usb0_phy_cfg_ahb_clk = { 2013 .halt_reg = 0x2c05c, 2014 .halt_check = BRANCH_HALT, 2015 .clkr = { 2016 .enable_reg = 0x2c05c, 2017 .enable_mask = BIT(0), 2018 .hw.init = &(const struct clk_init_data) { 2019 .name = "gcc_usb0_phy_cfg_ahb_clk", 2020 .parent_hws = (const struct clk_hw*[]) { 2021 &gcc_pcnoc_bfdcd_clk_src.clkr.hw, 2022 }, 2023 .num_parents = 1, 2024 .flags = CLK_SET_RATE_PARENT, 2025 .ops = &clk_branch2_ops, 2026 }, 2027 }, 2028 }; 2029 2030 static struct clk_regmap_phy_mux gcc_usb0_pipe_clk_src = { 2031 .reg = 0x2c074, 2032 .clkr = { 2033 .hw.init = &(const struct clk_init_data) { 2034 .name = "gcc_usb0_pipe_clk_src", 2035 .parent_data = &(const struct clk_parent_data) { 2036 .index = DT_USB3_PHY0_CC_PIPE_CLK, 2037 }, 2038 .num_parents = 1, 2039 .ops = &clk_regmap_phy_mux_ops, 2040 }, 2041 }, 2042 }; 2043 2044 static struct clk_branch gcc_usb0_pipe_clk = { 2045 .halt_reg = 0x2c054, 2046 .halt_check = BRANCH_HALT_DELAY, 2047 .clkr = { 2048 .enable_reg = 0x2c054, 2049 .enable_mask = BIT(0), 2050 .hw.init = &(const struct clk_init_data) { 2051 .name = "gcc_usb0_pipe_clk", 2052 .parent_hws = (const struct clk_hw *[]) { 2053 &gcc_usb0_pipe_clk_src.clkr.hw 2054 }, 2055 .num_parents = 1, 2056 .flags = CLK_SET_RATE_PARENT, 2057 .ops = &clk_branch2_ops, 2058 }, 2059 }, 2060 }; 2061 2062 static struct clk_branch gcc_usb0_sleep_clk = { 2063 .halt_reg = 0x2c058, 2064 .halt_check = BRANCH_HALT, 2065 .clkr = { 2066 .enable_reg = 0x2c058, 2067 .enable_mask = BIT(0), 2068 .hw.init = &(const struct clk_init_data) { 2069 .name = "gcc_usb0_sleep_clk", 2070 .parent_hws = (const struct clk_hw*[]) { 2071 &gcc_sleep_clk_src.clkr.hw, 2072 }, 2073 .num_parents = 1, 2074 .flags = CLK_SET_RATE_PARENT, 2075 .ops = &clk_branch2_ops, 2076 }, 2077 }, 2078 }; 2079 2080 static struct clk_branch gcc_pcie0_rchng_clk = { 2081 .halt_reg = 0x28028, 2082 .halt_check = BRANCH_HALT, 2083 .clkr = { 2084 .enable_reg = 0x28028, 2085 .enable_mask = BIT(1), 2086 .hw.init = &(const struct clk_init_data) { 2087 .name = "gcc_pcie0_rchng_clk", 2088 .parent_hws = (const struct clk_hw *[]) { 2089 &gcc_pcie0_rchng_clk_src.clkr.hw 2090 }, 2091 .num_parents = 1, 2092 .flags = CLK_SET_RATE_PARENT, 2093 .ops = &clk_branch2_ops, 2094 }, 2095 }, 2096 }; 2097 2098 static struct clk_branch gcc_pcie1_rchng_clk = { 2099 .halt_reg = 0x29028, 2100 .halt_check = BRANCH_HALT, 2101 .clkr = { 2102 .enable_reg = 0x29028, 2103 .enable_mask = BIT(1), 2104 .hw.init = &(const struct clk_init_data) { 2105 .name = "gcc_pcie1_rchng_clk", 2106 .parent_hws = (const struct clk_hw *[]) { 2107 &gcc_pcie1_rchng_clk_src.clkr.hw 2108 }, 2109 .num_parents = 1, 2110 .flags = CLK_SET_RATE_PARENT, 2111 .ops = &clk_branch2_ops, 2112 }, 2113 }, 2114 }; 2115 2116 static struct clk_branch gcc_qpic_ahb_clk = { 2117 .halt_reg = 0x32010, 2118 .halt_check = BRANCH_HALT, 2119 .clkr = { 2120 .enable_reg = 0x32010, 2121 .enable_mask = BIT(0), 2122 .hw.init = &(const struct clk_init_data) { 2123 .name = "gcc_qpic_ahb_clk", 2124 .parent_hws = (const struct clk_hw*[]) { 2125 &gcc_pcnoc_bfdcd_clk_src.clkr.hw, 2126 }, 2127 .num_parents = 1, 2128 .flags = CLK_SET_RATE_PARENT, 2129 .ops = &clk_branch2_ops, 2130 }, 2131 }, 2132 }; 2133 2134 static struct clk_branch gcc_qpic_clk = { 2135 .halt_reg = 0x32028, 2136 .halt_check = BRANCH_HALT, 2137 .clkr = { 2138 .enable_reg = 0x32028, 2139 .enable_mask = BIT(0), 2140 .hw.init = &(const struct clk_init_data) { 2141 .name = "gcc_qpic_clk", 2142 .parent_hws = (const struct clk_hw*[]) { 2143 &gcc_qpic_clk_src.clkr.hw, 2144 }, 2145 .num_parents = 1, 2146 .flags = CLK_SET_RATE_PARENT, 2147 .ops = &clk_branch2_ops, 2148 }, 2149 }, 2150 }; 2151 2152 static struct clk_branch gcc_qpic_io_macro_clk = { 2153 .halt_reg = 0x3200c, 2154 .halt_check = BRANCH_HALT, 2155 .clkr = { 2156 .enable_reg = 0x3200c, 2157 .enable_mask = BIT(0), 2158 .hw.init = &(const struct clk_init_data) { 2159 .name = "gcc_qpic_io_macro_clk", 2160 .parent_hws = (const struct clk_hw*[]) { 2161 &gcc_qpic_io_macro_clk_src.clkr.hw, 2162 }, 2163 .num_parents = 1, 2164 .flags = CLK_SET_RATE_PARENT, 2165 .ops = &clk_branch2_ops, 2166 }, 2167 }, 2168 }; 2169 2170 static struct clk_branch gcc_cmn_12gpll_ahb_clk = { 2171 .halt_reg = 0x3a004, 2172 .halt_check = BRANCH_HALT, 2173 .clkr = { 2174 .enable_reg = 0x3a004, 2175 .enable_mask = BIT(0), 2176 .hw.init = &(const struct clk_init_data) { 2177 .name = "gcc_cmn_12gpll_ahb_clk", 2178 .parent_hws = (const struct clk_hw*[]) { 2179 &gcc_pcnoc_bfdcd_clk_src.clkr.hw, 2180 }, 2181 .num_parents = 1, 2182 .flags = CLK_SET_RATE_PARENT, 2183 .ops = &clk_branch2_ops, 2184 }, 2185 }, 2186 }; 2187 2188 static struct clk_branch gcc_cmn_12gpll_sys_clk = { 2189 .halt_reg = 0x3a008, 2190 .halt_check = BRANCH_HALT, 2191 .clkr = { 2192 .enable_reg = 0x3a008, 2193 .enable_mask = BIT(0), 2194 .hw.init = &(const struct clk_init_data) { 2195 .name = "gcc_cmn_12gpll_sys_clk", 2196 .parent_hws = (const struct clk_hw*[]) { 2197 &gcc_uniphy_sys_clk_src.clkr.hw, 2198 }, 2199 .num_parents = 1, 2200 .flags = CLK_SET_RATE_PARENT, 2201 .ops = &clk_branch2_ops, 2202 }, 2203 }, 2204 }; 2205 2206 static struct clk_branch gcc_qdss_at_clk = { 2207 .halt_reg = 0x2d034, 2208 .halt_check = BRANCH_HALT, 2209 .clkr = { 2210 .enable_reg = 0x2d034, 2211 .enable_mask = BIT(0), 2212 .hw.init = &(const struct clk_init_data) { 2213 .name = "gcc_qdss_at_clk", 2214 .parent_hws = (const struct clk_hw*[]) { 2215 &gcc_qdss_at_clk_src.clkr.hw, 2216 }, 2217 .num_parents = 1, 2218 .flags = CLK_SET_RATE_PARENT, 2219 .ops = &clk_branch2_ops, 2220 }, 2221 }, 2222 }; 2223 2224 static struct clk_branch gcc_qdss_dap_clk = { 2225 .halt_reg = 0x2d058, 2226 .halt_check = BRANCH_HALT_VOTED, 2227 .clkr = { 2228 .enable_reg = 0xb004, 2229 .enable_mask = BIT(2), 2230 .hw.init = &(const struct clk_init_data) { 2231 .name = "gcc_qdss_dap_clk", 2232 .parent_hws = (const struct clk_hw*[]) { 2233 &gcc_qdss_tsctr_clk_src.clkr.hw, 2234 }, 2235 .num_parents = 1, 2236 .flags = CLK_SET_RATE_PARENT, 2237 .ops = &clk_branch2_ops, 2238 }, 2239 }, 2240 }; 2241 2242 static struct clk_branch gcc_pon_apb_clk = { 2243 .halt_reg = 0x3c01c, 2244 .halt_check = BRANCH_HALT, 2245 .clkr = { 2246 .enable_reg = 0x3c01c, 2247 .enable_mask = BIT(0), 2248 .hw.init = &(const struct clk_init_data) { 2249 .name = "gcc_pon_apb_clk", 2250 .parent_hws = (const struct clk_hw*[]) { 2251 &gcc_pcnoc_bfdcd_clk_src.clkr.hw, 2252 }, 2253 .num_parents = 1, 2254 .flags = CLK_SET_RATE_PARENT, 2255 .ops = &clk_branch2_ops, 2256 }, 2257 }, 2258 }; 2259 2260 static struct clk_branch gcc_pon_tm_clk = { 2261 .halt_reg = 0x3c014, 2262 .halt_check = BRANCH_HALT, 2263 .clkr = { 2264 .enable_reg = 0x3c014, 2265 .enable_mask = BIT(0), 2266 .hw.init = &(const struct clk_init_data) { 2267 .name = "gcc_pon_tm_clk", 2268 .parent_hws = (const struct clk_hw*[]) { 2269 &gcc_pon_tm_div_clk_src.hw, 2270 }, 2271 .num_parents = 1, 2272 .flags = CLK_SET_RATE_PARENT, 2273 .ops = &clk_branch2_ops, 2274 }, 2275 }, 2276 }; 2277 2278 static struct clk_branch gcc_pon_tm2x_clk = { 2279 .halt_reg = 0x3c00c, 2280 .halt_check = BRANCH_HALT, 2281 .clkr = { 2282 .enable_reg = 0x3c00c, 2283 .enable_mask = BIT(0), 2284 .hw.init = &(const struct clk_init_data) { 2285 .name = "gcc_pon_tm2x_clk", 2286 .parent_hws = (const struct clk_hw*[]) { 2287 &gcc_pon_tm2x_clk_src.clkr.hw, 2288 }, 2289 .num_parents = 1, 2290 .flags = CLK_SET_RATE_PARENT, 2291 .ops = &clk_branch2_ops, 2292 }, 2293 }, 2294 }; 2295 2296 static struct clk_branch gcc_snoc_lpass_clk = { 2297 .halt_reg = 0x2e028, 2298 .halt_check = BRANCH_HALT, 2299 .clkr = { 2300 .enable_reg = 0x2e028, 2301 .enable_mask = BIT(0), 2302 .hw.init = &(const struct clk_init_data) { 2303 .name = "gcc_snoc_lpass_clk", 2304 .parent_hws = (const struct clk_hw*[]) { 2305 &gcc_lpass_axim_clk_src.clkr.hw, 2306 }, 2307 .num_parents = 1, 2308 .flags = CLK_SET_RATE_PARENT, 2309 .ops = &clk_branch2_ops, 2310 }, 2311 }, 2312 }; 2313 2314 static struct clk_branch gcc_lpass_sway_clk = { 2315 .halt_reg = 0x27014, 2316 .halt_check = BRANCH_HALT, 2317 .clkr = { 2318 .enable_reg = 0x27014, 2319 .enable_mask = BIT(0), 2320 .hw.init = &(const struct clk_init_data) { 2321 .name = "gcc_lpass_sway_clk", 2322 .parent_hws = (const struct clk_hw*[]) { 2323 &gcc_lpass_sway_clk_src.clkr.hw, 2324 }, 2325 .num_parents = 1, 2326 .flags = CLK_SET_RATE_PARENT, 2327 .ops = &clk_branch2_ops, 2328 }, 2329 }, 2330 }; 2331 2332 static struct clk_branch gcc_cnoc_lpass_cfg_clk = { 2333 .halt_reg = 0x31020, 2334 .halt_check = BRANCH_HALT, 2335 .clkr = { 2336 .enable_reg = 0x31020, 2337 .enable_mask = BIT(0), 2338 .hw.init = &(const struct clk_init_data) { 2339 .name = "gcc_cnoc_lpass_cfg_clk", 2340 .parent_hws = (const struct clk_hw*[]) { 2341 &gcc_lpass_sway_clk_src.clkr.hw, 2342 }, 2343 .num_parents = 1, 2344 .flags = CLK_SET_RATE_PARENT, 2345 .ops = &clk_branch2_ops, 2346 }, 2347 }, 2348 }; 2349 2350 static struct clk_branch gcc_lpass_core_axim_clk = { 2351 .halt_reg = 0x27018, 2352 .halt_check = BRANCH_HALT, 2353 .clkr = { 2354 .enable_reg = 0x27018, 2355 .enable_mask = BIT(0), 2356 .hw.init = &(const struct clk_init_data) { 2357 .name = "gcc_lpass_core_axim_clk", 2358 .parent_hws = (const struct clk_hw*[]) { 2359 &gcc_lpass_axim_clk_src.clkr.hw, 2360 }, 2361 .num_parents = 1, 2362 .flags = CLK_SET_RATE_PARENT, 2363 .ops = &clk_branch2_ops, 2364 }, 2365 }, 2366 }; 2367 2368 static __maybe_unused struct clk_regmap *gcc_ipq5210_clocks[] = { 2369 [GCC_ADSS_PWM_CLK] = &gcc_adss_pwm_clk.clkr, 2370 [GCC_ADSS_PWM_CLK_SRC] = &gcc_adss_pwm_clk_src.clkr, 2371 [GCC_CMN_12GPLL_AHB_CLK] = &gcc_cmn_12gpll_ahb_clk.clkr, 2372 [GCC_CMN_12GPLL_SYS_CLK] = &gcc_cmn_12gpll_sys_clk.clkr, 2373 [GCC_CNOC_LPASS_CFG_CLK] = &gcc_cnoc_lpass_cfg_clk.clkr, 2374 [GCC_CNOC_PCIE0_1LANE_S_CLK] = &gcc_cnoc_pcie0_1lane_s_clk.clkr, 2375 [GCC_CNOC_PCIE1_2LANE_S_CLK] = &gcc_cnoc_pcie1_2lane_s_clk.clkr, 2376 [GCC_CNOC_USB_CLK] = &gcc_cnoc_usb_clk.clkr, 2377 [GCC_GEPHY_SYS_CLK] = &gcc_gephy_sys_clk.clkr, 2378 [GCC_LPASS_AXIM_CLK_SRC] = &gcc_lpass_axim_clk_src.clkr, 2379 [GCC_LPASS_CORE_AXIM_CLK] = &gcc_lpass_core_axim_clk.clkr, 2380 [GCC_LPASS_SWAY_CLK] = &gcc_lpass_sway_clk.clkr, 2381 [GCC_LPASS_SWAY_CLK_SRC] = &gcc_lpass_sway_clk_src.clkr, 2382 [GCC_MDIO_AHB_CLK] = &gcc_mdio_ahb_clk.clkr, 2383 [GCC_MDIO_GEPHY_AHB_CLK] = &gcc_mdio_gephy_ahb_clk.clkr, 2384 [GCC_NSS_TS_CLK] = &gcc_nss_ts_clk.clkr, 2385 [GCC_NSS_TS_CLK_SRC] = &gcc_nss_ts_clk_src.clkr, 2386 [GCC_NSSCC_CLK] = &gcc_nsscc_clk.clkr, 2387 [GCC_NSSCFG_CLK] = &gcc_nsscfg_clk.clkr, 2388 [GCC_NSSNOC_ATB_CLK] = &gcc_nssnoc_atb_clk.clkr, 2389 [GCC_NSSNOC_MEMNOC_1_CLK] = &gcc_nssnoc_memnoc_1_clk.clkr, 2390 [GCC_NSSNOC_MEMNOC_BFDCD_CLK_SRC] = &gcc_nssnoc_memnoc_bfdcd_clk_src.clkr, 2391 [GCC_NSSNOC_MEMNOC_CLK] = &gcc_nssnoc_memnoc_clk.clkr, 2392 [GCC_NSSNOC_MEMNOC_DIV_CLK_SRC] = &gcc_nssnoc_memnoc_div_clk_src.clkr, 2393 [GCC_NSSNOC_NSSCC_CLK] = &gcc_nssnoc_nsscc_clk.clkr, 2394 [GCC_NSSNOC_PCNOC_1_CLK] = &gcc_nssnoc_pcnoc_1_clk.clkr, 2395 [GCC_NSSNOC_QOSGEN_REF_CLK] = &gcc_nssnoc_qosgen_ref_clk.clkr, 2396 [GCC_NSSNOC_SNOC_1_CLK] = &gcc_nssnoc_snoc_1_clk.clkr, 2397 [GCC_NSSNOC_SNOC_CLK] = &gcc_nssnoc_snoc_clk.clkr, 2398 [GCC_NSSNOC_TIMEOUT_REF_CLK] = &gcc_nssnoc_timeout_ref_clk.clkr, 2399 [GCC_NSSNOC_XO_DCD_CLK] = &gcc_nssnoc_xo_dcd_clk.clkr, 2400 [GCC_PCIE0_AHB_CLK] = &gcc_pcie0_ahb_clk.clkr, 2401 [GCC_PCIE0_AUX_CLK] = &gcc_pcie0_aux_clk.clkr, 2402 [GCC_PCIE0_AXI_M_CLK] = &gcc_pcie0_axi_m_clk.clkr, 2403 [GCC_PCIE0_AXI_M_CLK_SRC] = &gcc_pcie0_axi_m_clk_src.clkr, 2404 [GCC_PCIE0_AXI_S_BRIDGE_CLK] = &gcc_pcie0_axi_s_bridge_clk.clkr, 2405 [GCC_PCIE0_AXI_S_CLK] = &gcc_pcie0_axi_s_clk.clkr, 2406 [GCC_PCIE0_AXI_S_CLK_SRC] = &gcc_pcie0_axi_s_clk_src.clkr, 2407 [GCC_PCIE0_PIPE_CLK] = &gcc_pcie0_pipe_clk.clkr, 2408 [GCC_PCIE0_PIPE_CLK_SRC] = &gcc_pcie0_pipe_clk_src.clkr, 2409 [GCC_PCIE0_RCHNG_CLK] = &gcc_pcie0_rchng_clk.clkr, 2410 [GCC_PCIE0_RCHNG_CLK_SRC] = &gcc_pcie0_rchng_clk_src.clkr, 2411 [GCC_PCIE1_AHB_CLK] = &gcc_pcie1_ahb_clk.clkr, 2412 [GCC_PCIE1_AUX_CLK] = &gcc_pcie1_aux_clk.clkr, 2413 [GCC_PCIE1_AXI_M_CLK] = &gcc_pcie1_axi_m_clk.clkr, 2414 [GCC_PCIE1_AXI_M_CLK_SRC] = &gcc_pcie1_axi_m_clk_src.clkr, 2415 [GCC_PCIE1_AXI_S_BRIDGE_CLK] = &gcc_pcie1_axi_s_bridge_clk.clkr, 2416 [GCC_PCIE1_AXI_S_CLK] = &gcc_pcie1_axi_s_clk.clkr, 2417 [GCC_PCIE1_AXI_S_CLK_SRC] = &gcc_pcie1_axi_s_clk_src.clkr, 2418 [GCC_PCIE1_PIPE_CLK] = &gcc_pcie1_pipe_clk.clkr, 2419 [GCC_PCIE1_PIPE_CLK_SRC] = &gcc_pcie1_pipe_clk_src.clkr, 2420 [GCC_PCIE1_RCHNG_CLK] = &gcc_pcie1_rchng_clk.clkr, 2421 [GCC_PCIE1_RCHNG_CLK_SRC] = &gcc_pcie1_rchng_clk_src.clkr, 2422 [GCC_PCIE_AUX_CLK_SRC] = &gcc_pcie_aux_clk_src.clkr, 2423 [GCC_PCNOC_BFDCD_CLK_SRC] = &gcc_pcnoc_bfdcd_clk_src.clkr, 2424 [GCC_PON_APB_CLK] = &gcc_pon_apb_clk.clkr, 2425 [GCC_PON_TM_CLK] = &gcc_pon_tm_clk.clkr, 2426 [GCC_PON_TM2X_CLK] = &gcc_pon_tm2x_clk.clkr, 2427 [GCC_PON_TM2X_CLK_SRC] = &gcc_pon_tm2x_clk_src.clkr, 2428 [GCC_QDSS_AT_CLK] = &gcc_qdss_at_clk.clkr, 2429 [GCC_QDSS_AT_CLK_SRC] = &gcc_qdss_at_clk_src.clkr, 2430 [GCC_QDSS_DAP_CLK] = &gcc_qdss_dap_clk.clkr, 2431 [GCC_QDSS_TSCTR_CLK_SRC] = &gcc_qdss_tsctr_clk_src.clkr, 2432 [GCC_QPIC_AHB_CLK] = &gcc_qpic_ahb_clk.clkr, 2433 [GCC_QPIC_CLK] = &gcc_qpic_clk.clkr, 2434 [GCC_QPIC_CLK_SRC] = &gcc_qpic_clk_src.clkr, 2435 [GCC_QPIC_IO_MACRO_CLK] = &gcc_qpic_io_macro_clk.clkr, 2436 [GCC_QPIC_IO_MACRO_CLK_SRC] = &gcc_qpic_io_macro_clk_src.clkr, 2437 [GCC_QRNG_AHB_CLK] = &gcc_qrng_ahb_clk.clkr, 2438 [GCC_QUPV3_AHB_MST_CLK] = &gcc_qupv3_ahb_mst_clk.clkr, 2439 [GCC_QUPV3_AHB_SLV_CLK] = &gcc_qupv3_ahb_slv_clk.clkr, 2440 [GCC_QUPV3_WRAP_SE0_CLK] = &gcc_qupv3_wrap_se0_clk.clkr, 2441 [GCC_QUPV3_WRAP_SE0_CLK_SRC] = &gcc_qupv3_wrap_se0_clk_src.clkr, 2442 [GCC_QUPV3_WRAP_SE1_CLK] = &gcc_qupv3_wrap_se1_clk.clkr, 2443 [GCC_QUPV3_WRAP_SE1_CLK_SRC] = &gcc_qupv3_wrap_se1_clk_src.clkr, 2444 [GCC_QUPV3_WRAP_SE2_CLK] = &gcc_qupv3_wrap_se2_clk.clkr, 2445 [GCC_QUPV3_WRAP_SE2_CLK_SRC] = &gcc_qupv3_wrap_se2_clk_src.clkr, 2446 [GCC_QUPV3_WRAP_SE3_CLK] = &gcc_qupv3_wrap_se3_clk.clkr, 2447 [GCC_QUPV3_WRAP_SE3_CLK_SRC] = &gcc_qupv3_wrap_se3_clk_src.clkr, 2448 [GCC_QUPV3_WRAP_SE4_CLK] = &gcc_qupv3_wrap_se4_clk.clkr, 2449 [GCC_QUPV3_WRAP_SE4_CLK_SRC] = &gcc_qupv3_wrap_se4_clk_src.clkr, 2450 [GCC_QUPV3_WRAP_SE5_CLK] = &gcc_qupv3_wrap_se5_clk.clkr, 2451 [GCC_QUPV3_WRAP_SE5_CLK_SRC] = &gcc_qupv3_wrap_se5_clk_src.clkr, 2452 [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr, 2453 [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr, 2454 [GCC_SDCC1_APPS_CLK_SRC] = &gcc_sdcc1_apps_clk_src.clkr, 2455 [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr, 2456 [GCC_SDCC1_ICE_CORE_CLK_SRC] = &gcc_sdcc1_ice_core_clk_src.clkr, 2457 [GCC_SLEEP_CLK_SRC] = &gcc_sleep_clk_src.clkr, 2458 [GCC_SNOC_LPASS_CLK] = &gcc_snoc_lpass_clk.clkr, 2459 [GCC_SNOC_PCIE0_AXI_M_CLK] = &gcc_snoc_pcie0_axi_m_clk.clkr, 2460 [GCC_SNOC_PCIE1_AXI_M_CLK] = &gcc_snoc_pcie1_axi_m_clk.clkr, 2461 [GCC_SYSTEM_NOC_BFDCD_CLK_SRC] = &gcc_system_noc_bfdcd_clk_src.clkr, 2462 [GCC_UNIPHY0_AHB_CLK] = &gcc_uniphy0_ahb_clk.clkr, 2463 [GCC_UNIPHY0_SYS_CLK] = &gcc_uniphy0_sys_clk.clkr, 2464 [GCC_UNIPHY1_AHB_CLK] = &gcc_uniphy1_ahb_clk.clkr, 2465 [GCC_UNIPHY1_SYS_CLK] = &gcc_uniphy1_sys_clk.clkr, 2466 [GCC_UNIPHY2_AHB_CLK] = &gcc_uniphy2_ahb_clk.clkr, 2467 [GCC_UNIPHY2_SYS_CLK] = &gcc_uniphy2_sys_clk.clkr, 2468 [GCC_UNIPHY_SYS_CLK_SRC] = &gcc_uniphy_sys_clk_src.clkr, 2469 [GCC_USB0_AUX_CLK] = &gcc_usb0_aux_clk.clkr, 2470 [GCC_USB0_AUX_CLK_SRC] = &gcc_usb0_aux_clk_src.clkr, 2471 [GCC_USB0_MASTER_CLK] = &gcc_usb0_master_clk.clkr, 2472 [GCC_USB0_MASTER_CLK_SRC] = &gcc_usb0_master_clk_src.clkr, 2473 [GCC_USB0_MOCK_UTMI_CLK] = &gcc_usb0_mock_utmi_clk.clkr, 2474 [GCC_USB0_MOCK_UTMI_CLK_SRC] = &gcc_usb0_mock_utmi_clk_src.clkr, 2475 [GCC_USB0_MOCK_UTMI_DIV_CLK_SRC] = &gcc_usb0_mock_utmi_div_clk_src.clkr, 2476 [GCC_USB0_PHY_CFG_AHB_CLK] = &gcc_usb0_phy_cfg_ahb_clk.clkr, 2477 [GCC_USB0_PIPE_CLK] = &gcc_usb0_pipe_clk.clkr, 2478 [GCC_USB0_PIPE_CLK_SRC] = &gcc_usb0_pipe_clk_src.clkr, 2479 [GCC_USB0_SLEEP_CLK] = &gcc_usb0_sleep_clk.clkr, 2480 [GCC_XO_CLK_SRC] = &gcc_xo_clk_src.clkr, 2481 [GPLL0_MAIN] = &gpll0_main.clkr, 2482 [GPLL0] = &gpll0.clkr, 2483 [GPLL2_MAIN] = &gpll2_main.clkr, 2484 [GPLL2] = &gpll2.clkr, 2485 [GPLL4_MAIN] = &gpll4_main.clkr, 2486 }; 2487 2488 static const struct qcom_reset_map gcc_ipq5210_resets[] = { 2489 [GCC_ADSS_BCR] = { 0x1c000 }, 2490 [GCC_ADSS_PWM_ARES] = { 0x1c00c, 2 }, 2491 [GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR] = { 0x38000 }, 2492 [GCC_APC0_VOLTAGE_DROOP_DETECTOR_GPLL0_ARES] = { 0x3800c, 2 }, 2493 [GCC_APSS_AHB_ARES] = { 0x24014, 2 }, 2494 [GCC_APSS_ATB_ARES] = { 0x24034, 2 }, 2495 [GCC_APSS_AXI_ARES] = { 0x24018, 2 }, 2496 [GCC_APSS_TS_ARES] = { 0x24030, 2 }, 2497 [GCC_BOOT_ROM_AHB_ARES] = { 0x1302c, 2 }, 2498 [GCC_BOOT_ROM_BCR] = { 0x13028 }, 2499 [GCC_GEPHY_BCR] = { 0x2a000 }, 2500 [GCC_GEPHY_SYS_ARES] = { 0x2a004, 2 }, 2501 [GCC_GP1_ARES] = { 0x8018, 2 }, 2502 [GCC_GP2_ARES] = { 0x9018, 2 }, 2503 [GCC_GP3_ARES] = { 0xa018, 2 }, 2504 [GCC_MDIO_AHB_ARES] = { 0x17040, 2 }, 2505 [GCC_MDIO_BCR] = { 0x1703c }, 2506 [GCC_MDIO_GEPHY_AHB_ARES] = { 0x17098, 2 }, 2507 [GCC_NSS_BCR] = { 0x17000 }, 2508 [GCC_NSS_TS_ARES] = { 0x17018, 2 }, 2509 [GCC_NSSCC_ARES] = { 0x17034, 2 }, 2510 [GCC_NSSCFG_ARES] = { 0x1702c, 2 }, 2511 [GCC_NSSNOC_ATB_ARES] = { 0x17014, 2 }, 2512 [GCC_NSSNOC_MEMNOC_1_ARES] = { 0x17084, 2 }, 2513 [GCC_NSSNOC_MEMNOC_ARES] = { 0x17024, 2 }, 2514 [GCC_NSSNOC_NSSCC_ARES] = { 0x17030, 2 }, 2515 [GCC_NSSNOC_PCNOC_1_ARES] = { 0x17080, 2 }, 2516 [GCC_NSSNOC_QOSGEN_REF_ARES] = { 0x1701c, 2 }, 2517 [GCC_NSSNOC_SNOC_1_ARES] = { 0x1707c, 2 }, 2518 [GCC_NSSNOC_SNOC_ARES] = { 0x17028, 2 }, 2519 [GCC_NSSNOC_TIMEOUT_REF_ARES] = { 0x17020, 2 }, 2520 [GCC_NSSNOC_XO_DCD_ARES] = { 0x17074, 2 }, 2521 [GCC_PCIE0_AHB_ARES] = { 0x28030, 2 }, 2522 [GCC_PCIE0_AUX_ARES] = { 0x28070, 2 }, 2523 [GCC_PCIE0_AXI_M_ARES] = { 0x28038, 2 }, 2524 [GCC_PCIE0_AXI_S_BRIDGE_ARES] = { 0x28048, 2 }, 2525 [GCC_PCIE0_AXI_S_ARES] = { 0x28040, 2 }, 2526 [GCC_PCIE0_BCR] = { 0x28000 }, 2527 [GCC_PCIE0_LINK_DOWN_BCR] = { 0x28054 }, 2528 [GCC_PCIE0_PIPE_RESET] = { 0x28058, 0 }, 2529 [GCC_PCIE0_CORE_STICKY_RESET] = { 0x28058, 1 }, 2530 [GCC_PCIE0_AXI_S_STICKY_RESET] = { 0x28058, 2 }, 2531 [GCC_PCIE0_AXI_S_RESET] = { 0x28058, 3 }, 2532 [GCC_PCIE0_AXI_M_STICKY_RESET] = { 0x28058, 4 }, 2533 [GCC_PCIE0_AXI_M_RESET] = { 0x28058, 5 }, 2534 [GCC_PCIE0_AUX_RESET] = { 0x28058, 6 }, 2535 [GCC_PCIE0_AHB_RESET] = { 0x28058, 7 }, 2536 [GCC_PCIE0_PHY_BCR] = { 0x28060 }, 2537 [GCC_PCIE0_PIPE_ARES] = { 0x28068, 2 }, 2538 [GCC_PCIE0PHY_PHY_BCR] = { 0x2805c }, 2539 [GCC_PCIE1_AHB_ARES] = { 0x29030, 2 }, 2540 [GCC_PCIE1_AUX_ARES] = { 0x29074, 2 }, 2541 [GCC_PCIE1_AXI_M_ARES] = { 0x29038, 2 }, 2542 [GCC_PCIE1_AXI_S_BRIDGE_ARES] = { 0x29048, 2 }, 2543 [GCC_PCIE1_AXI_S_ARES] = { 0x29040, 2 }, 2544 [GCC_PCIE1_BCR] = { 0x29000 }, 2545 [GCC_PCIE1_LINK_DOWN_BCR] = { 0x29054 }, 2546 [GCC_PCIE1_PIPE_RESET] = { 0x29058, 0 }, 2547 [GCC_PCIE1_CORE_STICKY_RESET] = { 0x29058, 1 }, 2548 [GCC_PCIE1_AXI_S_STICKY_RESET] = { 0x29058, 2 }, 2549 [GCC_PCIE1_AXI_S_RESET] = { 0x29058, 3 }, 2550 [GCC_PCIE1_AXI_M_STICKY_RESET] = { 0x29058, 4 }, 2551 [GCC_PCIE1_AXI_M_RESET] = { 0x29058, 5 }, 2552 [GCC_PCIE1_AUX_RESET] = { 0x29058, 6 }, 2553 [GCC_PCIE1_AHB_RESET] = { 0x29058, 7 }, 2554 [GCC_PCIE1_PHY_BCR] = { 0x29060 }, 2555 [GCC_PCIE1_PIPE_ARES] = { 0x29068, 2 }, 2556 [GCC_PCIE1PHY_PHY_BCR] = { 0x2905c }, 2557 [GCC_QRNG_AHB_ARES] = { 0x13024, 2 }, 2558 [GCC_QRNG_BCR] = { 0x13020 }, 2559 [GCC_QUPV3_2X_CORE_ARES] = { 0x1020, 2 }, 2560 [GCC_QUPV3_AHB_MST_ARES] = { 0x1014, 2 }, 2561 [GCC_QUPV3_AHB_SLV_ARES] = { 0x102c, 2 }, 2562 [GCC_QUPV3_BCR] = { 0x1000 }, 2563 [GCC_QUPV3_CORE_ARES] = { 0x1018, 2 }, 2564 [GCC_QUPV3_WRAP_SE0_ARES] = { 0x4020, 2 }, 2565 [GCC_QUPV3_WRAP_SE0_BCR] = { 0x4000 }, 2566 [GCC_QUPV3_WRAP_SE1_ARES] = { 0x5020, 2 }, 2567 [GCC_QUPV3_WRAP_SE1_BCR] = { 0x5000 }, 2568 [GCC_QUPV3_WRAP_SE2_ARES] = { 0x202c, 2 }, 2569 [GCC_QUPV3_WRAP_SE2_BCR] = { 0x2000 }, 2570 [GCC_QUPV3_WRAP_SE3_ARES] = { 0x2048, 2 }, 2571 [GCC_QUPV3_WRAP_SE3_BCR] = { 0x2030 }, 2572 [GCC_QUPV3_WRAP_SE4_ARES] = { 0x302c, 2 }, 2573 [GCC_QUPV3_WRAP_SE4_BCR] = { 0x3000 }, 2574 [GCC_QUPV3_WRAP_SE5_ARES] = { 0x3048, 2 }, 2575 [GCC_QUPV3_WRAP_SE5_BCR] = { 0x3030 }, 2576 [GCC_QUSB2_0_PHY_BCR] = { 0x2c068 }, 2577 [GCC_SDCC1_AHB_ARES] = { 0x3303c, 2 }, 2578 [GCC_SDCC1_APPS_ARES] = { 0x3302c, 2 }, 2579 [GCC_SDCC1_ICE_CORE_ARES] = { 0x33034, 2 }, 2580 [GCC_SDCC_BCR] = { 0x33000 }, 2581 [GCC_TLMM_AHB_ARES] = { 0x3e004, 2 }, 2582 [GCC_TLMM_ARES] = { 0x3e008, 2 }, 2583 [GCC_TLMM_BCR] = { 0x3e000 }, 2584 [GCC_UNIPHY0_AHB_ARES] = { 0x1704c, 2 }, 2585 [GCC_UNIPHY0_BCR] = { 0x17044 }, 2586 [GCC_UNIPHY0_SYS_ARES] = { 0x17048, 2 }, 2587 [GCC_UNIPHY1_AHB_ARES] = { 0x1705c, 2 }, 2588 [GCC_UNIPHY1_BCR] = { 0x17054 }, 2589 [GCC_UNIPHY1_SYS_ARES] = { 0x17058, 2 }, 2590 [GCC_UNIPHY2_AHB_ARES] = { 0x1706c, 2 }, 2591 [GCC_UNIPHY2_BCR] = { 0x17064 }, 2592 [GCC_UNIPHY2_SYS_ARES] = { 0x17068, 2 }, 2593 [GCC_USB0_AUX_ARES] = { 0x2c04c, 2 }, 2594 [GCC_USB0_MASTER_ARES] = { 0x2c044, 2 }, 2595 [GCC_USB0_MOCK_UTMI_ARES] = { 0x2c050, 2 }, 2596 [GCC_USB0_PHY_BCR] = { 0x2c06c }, 2597 [GCC_USB0_PHY_CFG_AHB_ARES] = { 0x2c05c, 2 }, 2598 [GCC_USB0_PIPE_ARES] = { 0x2c054, 2 }, 2599 [GCC_USB0_SLEEP_ARES] = { 0x2c058, 2 }, 2600 [GCC_USB3PHY_0_PHY_BCR] = { 0x2c070 }, 2601 [GCC_USB_BCR] = { 0x2c000 }, 2602 [GCC_QDSS_BCR] = { 0x2d000 }, 2603 }; 2604 2605 static const struct of_device_id gcc_ipq5210_match_table[] = { 2606 { .compatible = "qcom,ipq5210-gcc" }, 2607 { } 2608 }; 2609 MODULE_DEVICE_TABLE(of, gcc_ipq5210_match_table); 2610 2611 static const struct regmap_config gcc_ipq5210_regmap_config = { 2612 .reg_bits = 32, 2613 .reg_stride = 4, 2614 .val_bits = 32, 2615 .max_register = 0x3f024, 2616 .fast_io = true, 2617 }; 2618 2619 static struct clk_hw *gcc_ipq5210_hws[] = { 2620 &gpll0_div2.hw, 2621 &gcc_xo_div4_clk_src.hw, 2622 &gcc_pon_tm_div_clk_src.hw, 2623 }; 2624 2625 static const struct qcom_cc_desc gcc_ipq5210_desc = { 2626 .config = &gcc_ipq5210_regmap_config, 2627 .clks = gcc_ipq5210_clocks, 2628 .num_clks = ARRAY_SIZE(gcc_ipq5210_clocks), 2629 .resets = gcc_ipq5210_resets, 2630 .num_resets = ARRAY_SIZE(gcc_ipq5210_resets), 2631 .clk_hws = gcc_ipq5210_hws, 2632 .num_clk_hws = ARRAY_SIZE(gcc_ipq5210_hws), 2633 }; 2634 2635 static int gcc_ipq5210_probe(struct platform_device *pdev) 2636 { 2637 return qcom_cc_probe(pdev, &gcc_ipq5210_desc); 2638 } 2639 2640 static struct platform_driver gcc_ipq5210_driver = { 2641 .probe = gcc_ipq5210_probe, 2642 .driver = { 2643 .name = "qcom,gcc-ipq5210", 2644 .of_match_table = gcc_ipq5210_match_table, 2645 }, 2646 }; 2647 2648 static int __init gcc_ipq5210_init(void) 2649 { 2650 return platform_driver_register(&gcc_ipq5210_driver); 2651 } 2652 core_initcall(gcc_ipq5210_init); 2653 2654 static void __exit gcc_ipq5210_exit(void) 2655 { 2656 platform_driver_unregister(&gcc_ipq5210_driver); 2657 } 2658 module_exit(gcc_ipq5210_exit); 2659 2660 MODULE_DESCRIPTION("QTI GCC IPQ5210 Driver"); 2661 MODULE_LICENSE("GPL"); 2662