1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 4 */ 5 6 #include <linux/clk-provider.h> 7 #include <linux/module.h> 8 #include <linux/platform_device.h> 9 #include <linux/regmap.h> 10 11 #include <dt-bindings/clock/qcom,eliza-gcc.h> 12 13 #include "clk-alpha-pll.h" 14 #include "clk-branch.h" 15 #include "clk-pll.h" 16 #include "clk-rcg.h" 17 #include "clk-regmap.h" 18 #include "clk-regmap-divider.h" 19 #include "clk-regmap-mux.h" 20 #include "clk-regmap-phy-mux.h" 21 #include "common.h" 22 #include "gdsc.h" 23 #include "reset.h" 24 25 enum { 26 DT_BI_TCXO, 27 DT_SLEEP_CLK, 28 DT_PCIE_0_PIPE_CLK, 29 DT_PCIE_1_PIPE_CLK, 30 DT_UFS_PHY_RX_SYMBOL_0_CLK, 31 DT_UFS_PHY_RX_SYMBOL_1_CLK, 32 DT_UFS_PHY_TX_SYMBOL_0_CLK, 33 DT_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 34 }; 35 36 enum { 37 P_BI_TCXO, 38 P_GCC_GPLL0_OUT_EVEN, 39 P_GCC_GPLL0_OUT_MAIN, 40 P_GCC_GPLL4_OUT_MAIN, 41 P_GCC_GPLL7_OUT_MAIN, 42 P_GCC_GPLL8_OUT_MAIN, 43 P_GCC_GPLL9_OUT_MAIN, 44 P_PCIE_0_PIPE_CLK, 45 P_PCIE_1_PIPE_CLK, 46 P_SLEEP_CLK, 47 P_UFS_PHY_RX_SYMBOL_0_CLK, 48 P_UFS_PHY_RX_SYMBOL_1_CLK, 49 P_UFS_PHY_TX_SYMBOL_0_CLK, 50 P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 51 }; 52 53 static struct clk_alpha_pll gcc_gpll0 = { 54 .offset = 0x0, 55 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 56 .clkr = { 57 .enable_reg = 0x52020, 58 .enable_mask = BIT(0), 59 .hw.init = &(const struct clk_init_data) { 60 .name = "gcc_gpll0", 61 .parent_data = &(const struct clk_parent_data) { 62 .index = DT_BI_TCXO, 63 }, 64 .num_parents = 1, 65 .ops = &clk_alpha_pll_fixed_lucid_ole_ops, 66 }, 67 }, 68 }; 69 70 static const struct clk_div_table post_div_table_gcc_gpll0_out_even[] = { 71 { 0x1, 2 }, 72 { } 73 }; 74 75 static struct clk_alpha_pll_postdiv gcc_gpll0_out_even = { 76 .offset = 0x0, 77 .post_div_shift = 10, 78 .post_div_table = post_div_table_gcc_gpll0_out_even, 79 .num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_even), 80 .width = 4, 81 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 82 .clkr.hw.init = &(const struct clk_init_data) { 83 .name = "gcc_gpll0_out_even", 84 .parent_hws = (const struct clk_hw*[]) { 85 &gcc_gpll0.clkr.hw, 86 }, 87 .num_parents = 1, 88 .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, 89 }, 90 }; 91 92 static struct clk_alpha_pll gcc_gpll4 = { 93 .offset = 0x4000, 94 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 95 .clkr = { 96 .enable_reg = 0x52020, 97 .enable_mask = BIT(4), 98 .hw.init = &(const struct clk_init_data) { 99 .name = "gcc_gpll4", 100 .parent_data = &(const struct clk_parent_data) { 101 .index = DT_BI_TCXO, 102 }, 103 .num_parents = 1, 104 .ops = &clk_alpha_pll_fixed_lucid_ole_ops, 105 }, 106 }, 107 }; 108 109 static struct clk_alpha_pll gcc_gpll7 = { 110 .offset = 0x7000, 111 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 112 .clkr = { 113 .enable_reg = 0x52020, 114 .enable_mask = BIT(7), 115 .hw.init = &(const struct clk_init_data) { 116 .name = "gcc_gpll7", 117 .parent_data = &(const struct clk_parent_data) { 118 .index = DT_BI_TCXO, 119 }, 120 .num_parents = 1, 121 .ops = &clk_alpha_pll_fixed_lucid_ole_ops, 122 }, 123 }, 124 }; 125 126 static struct clk_alpha_pll gcc_gpll8 = { 127 .offset = 0x8000, 128 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 129 .clkr = { 130 .enable_reg = 0x52020, 131 .enable_mask = BIT(8), 132 .hw.init = &(const struct clk_init_data) { 133 .name = "gcc_gpll8", 134 .parent_data = &(const struct clk_parent_data) { 135 .index = DT_BI_TCXO, 136 }, 137 .num_parents = 1, 138 .ops = &clk_alpha_pll_fixed_lucid_ole_ops, 139 }, 140 }, 141 }; 142 143 static struct clk_alpha_pll gcc_gpll9 = { 144 .offset = 0x9000, 145 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 146 .clkr = { 147 .enable_reg = 0x52020, 148 .enable_mask = BIT(9), 149 .hw.init = &(const struct clk_init_data) { 150 .name = "gcc_gpll9", 151 .parent_data = &(const struct clk_parent_data) { 152 .index = DT_BI_TCXO, 153 }, 154 .num_parents = 1, 155 .ops = &clk_alpha_pll_fixed_lucid_ole_ops, 156 }, 157 }, 158 }; 159 160 static const struct parent_map gcc_parent_map_0[] = { 161 { P_BI_TCXO, 0 }, 162 { P_GCC_GPLL0_OUT_MAIN, 1 }, 163 { P_GCC_GPLL0_OUT_EVEN, 6 }, 164 }; 165 166 static const struct clk_parent_data gcc_parent_data_0[] = { 167 { .index = DT_BI_TCXO }, 168 { .hw = &gcc_gpll0.clkr.hw }, 169 { .hw = &gcc_gpll0_out_even.clkr.hw }, 170 }; 171 172 static const struct parent_map gcc_parent_map_1[] = { 173 { P_BI_TCXO, 0 }, 174 { P_GCC_GPLL0_OUT_MAIN, 1 }, 175 { P_SLEEP_CLK, 5 }, 176 { P_GCC_GPLL0_OUT_EVEN, 6 }, 177 }; 178 179 static const struct clk_parent_data gcc_parent_data_1[] = { 180 { .index = DT_BI_TCXO }, 181 { .hw = &gcc_gpll0.clkr.hw }, 182 { .index = DT_SLEEP_CLK }, 183 { .hw = &gcc_gpll0_out_even.clkr.hw }, 184 }; 185 186 static const struct parent_map gcc_parent_map_2[] = { 187 { P_BI_TCXO, 0 }, 188 { P_GCC_GPLL0_OUT_MAIN, 1 }, 189 { P_GCC_GPLL4_OUT_MAIN, 5 }, 190 { P_GCC_GPLL0_OUT_EVEN, 6 }, 191 }; 192 193 static const struct clk_parent_data gcc_parent_data_2[] = { 194 { .index = DT_BI_TCXO }, 195 { .hw = &gcc_gpll0.clkr.hw }, 196 { .hw = &gcc_gpll4.clkr.hw }, 197 { .hw = &gcc_gpll0_out_even.clkr.hw }, 198 }; 199 200 static const struct parent_map gcc_parent_map_3[] = { 201 { P_BI_TCXO, 0 }, 202 { P_SLEEP_CLK, 5 }, 203 }; 204 205 static const struct clk_parent_data gcc_parent_data_3[] = { 206 { .index = DT_BI_TCXO }, 207 { .index = DT_SLEEP_CLK }, 208 }; 209 210 static const struct parent_map gcc_parent_map_4[] = { 211 { P_BI_TCXO, 0 }, 212 { P_GCC_GPLL0_OUT_MAIN, 1 }, 213 { P_GCC_GPLL7_OUT_MAIN, 2 }, 214 { P_GCC_GPLL0_OUT_EVEN, 6 }, 215 }; 216 217 static const struct clk_parent_data gcc_parent_data_4[] = { 218 { .index = DT_BI_TCXO }, 219 { .hw = &gcc_gpll0.clkr.hw }, 220 { .hw = &gcc_gpll7.clkr.hw }, 221 { .hw = &gcc_gpll0_out_even.clkr.hw }, 222 }; 223 224 static const struct parent_map gcc_parent_map_5[] = { 225 { P_BI_TCXO, 0 }, 226 { P_GCC_GPLL0_OUT_MAIN, 1 }, 227 { P_GCC_GPLL8_OUT_MAIN, 2 }, 228 { P_GCC_GPLL0_OUT_EVEN, 6 }, 229 }; 230 231 static const struct clk_parent_data gcc_parent_data_5[] = { 232 { .index = DT_BI_TCXO }, 233 { .hw = &gcc_gpll0.clkr.hw }, 234 { .hw = &gcc_gpll8.clkr.hw }, 235 { .hw = &gcc_gpll0_out_even.clkr.hw }, 236 }; 237 238 static const struct parent_map gcc_parent_map_6[] = { 239 { P_BI_TCXO, 0 }, 240 }; 241 242 static const struct clk_parent_data gcc_parent_data_6[] = { 243 { .index = DT_BI_TCXO }, 244 }; 245 246 static const struct parent_map gcc_parent_map_7[] = { 247 { P_BI_TCXO, 0 }, 248 { P_GCC_GPLL0_OUT_MAIN, 1 }, 249 { P_GCC_GPLL9_OUT_MAIN, 2 }, 250 { P_GCC_GPLL4_OUT_MAIN, 5 }, 251 { P_GCC_GPLL0_OUT_EVEN, 6 }, 252 }; 253 254 static const struct clk_parent_data gcc_parent_data_7[] = { 255 { .index = DT_BI_TCXO }, 256 { .hw = &gcc_gpll0.clkr.hw }, 257 { .hw = &gcc_gpll9.clkr.hw }, 258 { .hw = &gcc_gpll4.clkr.hw }, 259 { .hw = &gcc_gpll0_out_even.clkr.hw }, 260 }; 261 262 static const struct parent_map gcc_parent_map_8[] = { 263 { P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 0 }, 264 { P_BI_TCXO, 2 }, 265 { P_GCC_GPLL0_OUT_EVEN, 3 }, 266 }; 267 268 static const struct clk_parent_data gcc_parent_data_8[] = { 269 { .index = DT_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK }, 270 { .index = DT_BI_TCXO }, 271 { .hw = &gcc_gpll0_out_even.clkr.hw }, 272 }; 273 274 static struct clk_regmap_phy_mux gcc_pcie_0_pipe_clk_src = { 275 .reg = 0x6b080, 276 .clkr = { 277 .hw.init = &(const struct clk_init_data) { 278 .name = "gcc_pcie_0_pipe_clk_src", 279 .parent_data = &(const struct clk_parent_data){ 280 .index = DT_PCIE_0_PIPE_CLK, 281 }, 282 .num_parents = 1, 283 .ops = &clk_regmap_phy_mux_ops, 284 }, 285 }, 286 }; 287 288 static struct clk_regmap_phy_mux gcc_pcie_1_pipe_clk_src = { 289 .reg = 0xac07c, 290 .clkr = { 291 .hw.init = &(const struct clk_init_data) { 292 .name = "gcc_pcie_1_pipe_clk_src", 293 .parent_data = &(const struct clk_parent_data){ 294 .index = DT_PCIE_1_PIPE_CLK, 295 }, 296 .num_parents = 1, 297 .ops = &clk_regmap_phy_mux_ops, 298 }, 299 }, 300 }; 301 302 static struct clk_regmap_phy_mux gcc_ufs_phy_rx_symbol_0_clk_src = { 303 .reg = 0x77068, 304 .clkr = { 305 .hw.init = &(const struct clk_init_data) { 306 .name = "gcc_ufs_phy_rx_symbol_0_clk_src", 307 .parent_data = &(const struct clk_parent_data){ 308 .index = DT_UFS_PHY_RX_SYMBOL_0_CLK, 309 }, 310 .num_parents = 1, 311 .ops = &clk_regmap_phy_mux_ops, 312 }, 313 }, 314 }; 315 316 static struct clk_regmap_phy_mux gcc_ufs_phy_rx_symbol_1_clk_src = { 317 .reg = 0x770ec, 318 .clkr = { 319 .hw.init = &(const struct clk_init_data) { 320 .name = "gcc_ufs_phy_rx_symbol_1_clk_src", 321 .parent_data = &(const struct clk_parent_data){ 322 .index = DT_UFS_PHY_RX_SYMBOL_1_CLK, 323 }, 324 .num_parents = 1, 325 .ops = &clk_regmap_phy_mux_ops, 326 }, 327 }, 328 }; 329 330 static struct clk_regmap_phy_mux gcc_ufs_phy_tx_symbol_0_clk_src = { 331 .reg = 0x77058, 332 .clkr = { 333 .hw.init = &(const struct clk_init_data) { 334 .name = "gcc_ufs_phy_tx_symbol_0_clk_src", 335 .parent_data = &(const struct clk_parent_data){ 336 .index = DT_UFS_PHY_TX_SYMBOL_0_CLK, 337 }, 338 .num_parents = 1, 339 .ops = &clk_regmap_phy_mux_ops, 340 }, 341 }, 342 }; 343 344 static struct clk_regmap_mux gcc_usb3_prim_phy_pipe_clk_src = { 345 .reg = 0x39070, 346 .shift = 0, 347 .width = 2, 348 .parent_map = gcc_parent_map_8, 349 .clkr = { 350 .hw.init = &(const struct clk_init_data) { 351 .name = "gcc_usb3_prim_phy_pipe_clk_src", 352 .parent_data = gcc_parent_data_8, 353 .num_parents = ARRAY_SIZE(gcc_parent_data_8), 354 .ops = &clk_regmap_mux_closest_ops, 355 }, 356 }, 357 }; 358 359 static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = { 360 F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0), 361 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 362 F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0), 363 { } 364 }; 365 366 static struct clk_rcg2 gcc_gp1_clk_src = { 367 .cmd_rcgr = 0x64004, 368 .mnd_width = 16, 369 .hid_width = 5, 370 .parent_map = gcc_parent_map_1, 371 .freq_tbl = ftbl_gcc_gp1_clk_src, 372 .hw_clk_ctrl = true, 373 .clkr.hw.init = &(const struct clk_init_data) { 374 .name = "gcc_gp1_clk_src", 375 .parent_data = gcc_parent_data_1, 376 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 377 .flags = CLK_SET_RATE_PARENT, 378 .ops = &clk_rcg2_shared_ops, 379 }, 380 }; 381 382 static struct clk_rcg2 gcc_gp2_clk_src = { 383 .cmd_rcgr = 0x65004, 384 .mnd_width = 16, 385 .hid_width = 5, 386 .parent_map = gcc_parent_map_1, 387 .freq_tbl = ftbl_gcc_gp1_clk_src, 388 .hw_clk_ctrl = true, 389 .clkr.hw.init = &(const struct clk_init_data) { 390 .name = "gcc_gp2_clk_src", 391 .parent_data = gcc_parent_data_1, 392 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 393 .flags = CLK_SET_RATE_PARENT, 394 .ops = &clk_rcg2_shared_ops, 395 }, 396 }; 397 398 static struct clk_rcg2 gcc_gp3_clk_src = { 399 .cmd_rcgr = 0x66004, 400 .mnd_width = 16, 401 .hid_width = 5, 402 .parent_map = gcc_parent_map_1, 403 .freq_tbl = ftbl_gcc_gp1_clk_src, 404 .hw_clk_ctrl = true, 405 .clkr.hw.init = &(const struct clk_init_data) { 406 .name = "gcc_gp3_clk_src", 407 .parent_data = gcc_parent_data_1, 408 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 409 .flags = CLK_SET_RATE_PARENT, 410 .ops = &clk_rcg2_shared_ops, 411 }, 412 }; 413 414 static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = { 415 F(19200000, P_BI_TCXO, 1, 0, 0), 416 { } 417 }; 418 419 static struct clk_rcg2 gcc_pcie_0_aux_clk_src = { 420 .cmd_rcgr = 0x6b084, 421 .mnd_width = 16, 422 .hid_width = 5, 423 .parent_map = gcc_parent_map_3, 424 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 425 .hw_clk_ctrl = true, 426 .clkr.hw.init = &(const struct clk_init_data) { 427 .name = "gcc_pcie_0_aux_clk_src", 428 .parent_data = gcc_parent_data_3, 429 .num_parents = ARRAY_SIZE(gcc_parent_data_3), 430 .flags = CLK_SET_RATE_PARENT, 431 .ops = &clk_rcg2_shared_ops, 432 }, 433 }; 434 435 static const struct freq_tbl ftbl_gcc_pcie_0_phy_rchng_clk_src[] = { 436 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0), 437 { } 438 }; 439 440 static struct clk_rcg2 gcc_pcie_0_phy_rchng_clk_src = { 441 .cmd_rcgr = 0x6b068, 442 .mnd_width = 0, 443 .hid_width = 5, 444 .parent_map = gcc_parent_map_0, 445 .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src, 446 .hw_clk_ctrl = true, 447 .clkr.hw.init = &(const struct clk_init_data) { 448 .name = "gcc_pcie_0_phy_rchng_clk_src", 449 .parent_data = gcc_parent_data_0, 450 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 451 .flags = CLK_SET_RATE_PARENT, 452 .ops = &clk_rcg2_shared_ops, 453 }, 454 }; 455 456 static struct clk_rcg2 gcc_pcie_1_aux_clk_src = { 457 .cmd_rcgr = 0xac080, 458 .mnd_width = 16, 459 .hid_width = 5, 460 .parent_map = gcc_parent_map_3, 461 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 462 .hw_clk_ctrl = true, 463 .clkr.hw.init = &(const struct clk_init_data) { 464 .name = "gcc_pcie_1_aux_clk_src", 465 .parent_data = gcc_parent_data_3, 466 .num_parents = ARRAY_SIZE(gcc_parent_data_3), 467 .flags = CLK_SET_RATE_PARENT, 468 .ops = &clk_rcg2_shared_ops, 469 }, 470 }; 471 472 static struct clk_rcg2 gcc_pcie_1_phy_rchng_clk_src = { 473 .cmd_rcgr = 0xac064, 474 .mnd_width = 0, 475 .hid_width = 5, 476 .parent_map = gcc_parent_map_0, 477 .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src, 478 .hw_clk_ctrl = true, 479 .clkr.hw.init = &(const struct clk_init_data) { 480 .name = "gcc_pcie_1_phy_rchng_clk_src", 481 .parent_data = gcc_parent_data_0, 482 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 483 .flags = CLK_SET_RATE_PARENT, 484 .ops = &clk_rcg2_shared_ops, 485 }, 486 }; 487 488 static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = { 489 F(60000000, P_GCC_GPLL0_OUT_MAIN, 10, 0, 0), 490 { } 491 }; 492 493 static struct clk_rcg2 gcc_pdm2_clk_src = { 494 .cmd_rcgr = 0x33010, 495 .mnd_width = 0, 496 .hid_width = 5, 497 .parent_map = gcc_parent_map_0, 498 .freq_tbl = ftbl_gcc_pdm2_clk_src, 499 .hw_clk_ctrl = true, 500 .clkr.hw.init = &(const struct clk_init_data) { 501 .name = "gcc_pdm2_clk_src", 502 .parent_data = gcc_parent_data_0, 503 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 504 .flags = CLK_SET_RATE_PARENT, 505 .ops = &clk_rcg2_shared_ops, 506 }, 507 }; 508 509 static const struct freq_tbl ftbl_gcc_qupv3_wrap1_qspi_ref_clk_src[] = { 510 F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625), 511 F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625), 512 F(19200000, P_BI_TCXO, 1, 0, 0), 513 F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625), 514 F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75), 515 F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25), 516 F(51200000, P_GCC_GPLL0_OUT_EVEN, 1, 64, 375), 517 F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75), 518 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), 519 F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15), 520 F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25), 521 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 522 F(102400000, P_GCC_GPLL0_OUT_EVEN, 1, 128, 375), 523 F(112000000, P_GCC_GPLL0_OUT_EVEN, 1, 28, 75), 524 F(117964800, P_GCC_GPLL0_OUT_EVEN, 1, 6144, 15625), 525 F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0), 526 F(150000000, P_GCC_GPLL0_OUT_EVEN, 2, 0, 0), 527 F(250000000, P_GCC_GPLL7_OUT_MAIN, 2, 0, 0), 528 { } 529 }; 530 531 static struct clk_init_data gcc_qupv3_wrap1_qspi_ref_clk_src_init = { 532 .name = "gcc_qupv3_wrap1_qspi_ref_clk_src", 533 .parent_data = gcc_parent_data_4, 534 .num_parents = ARRAY_SIZE(gcc_parent_data_4), 535 .flags = CLK_SET_RATE_PARENT, 536 .ops = &clk_rcg2_shared_no_init_park_ops, 537 }; 538 539 static struct clk_rcg2 gcc_qupv3_wrap1_qspi_ref_clk_src = { 540 .cmd_rcgr = 0x188c0, 541 .mnd_width = 16, 542 .hid_width = 5, 543 .parent_map = gcc_parent_map_4, 544 .freq_tbl = ftbl_gcc_qupv3_wrap1_qspi_ref_clk_src, 545 .hw_clk_ctrl = true, 546 .clkr.hw.init = &gcc_qupv3_wrap1_qspi_ref_clk_src_init, 547 }; 548 549 static const struct freq_tbl ftbl_gcc_qupv3_wrap1_s0_clk_src[] = { 550 F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625), 551 F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625), 552 F(19200000, P_BI_TCXO, 1, 0, 0), 553 F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625), 554 F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75), 555 F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25), 556 F(51200000, P_GCC_GPLL0_OUT_EVEN, 1, 64, 375), 557 F(61440000, P_GCC_GPLL0_OUT_EVEN, 1, 128, 625), 558 F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75), 559 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), 560 F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15), 561 F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25), 562 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 563 F(102400000, P_GCC_GPLL0_OUT_EVEN, 1, 128, 375), 564 F(112000000, P_GCC_GPLL0_OUT_EVEN, 1, 28, 75), 565 F(117964800, P_GCC_GPLL0_OUT_EVEN, 1, 6144, 15625), 566 F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0), 567 { } 568 }; 569 570 static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = { 571 .name = "gcc_qupv3_wrap1_s0_clk_src", 572 .parent_data = gcc_parent_data_0, 573 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 574 .flags = CLK_SET_RATE_PARENT, 575 .ops = &clk_rcg2_shared_no_init_park_ops, 576 }; 577 578 static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = { 579 .cmd_rcgr = 0x18014, 580 .mnd_width = 16, 581 .hid_width = 5, 582 .parent_map = gcc_parent_map_0, 583 .freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src, 584 .hw_clk_ctrl = true, 585 .clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init, 586 }; 587 588 static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = { 589 .name = "gcc_qupv3_wrap1_s1_clk_src", 590 .parent_data = gcc_parent_data_0, 591 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 592 .flags = CLK_SET_RATE_PARENT, 593 .ops = &clk_rcg2_shared_no_init_park_ops, 594 }; 595 596 static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = { 597 .cmd_rcgr = 0x18150, 598 .mnd_width = 16, 599 .hid_width = 5, 600 .parent_map = gcc_parent_map_0, 601 .freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src, 602 .hw_clk_ctrl = true, 603 .clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init, 604 }; 605 606 static const struct freq_tbl ftbl_gcc_qupv3_wrap1_s3_clk_src[] = { 607 F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625), 608 F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625), 609 F(19200000, P_BI_TCXO, 1, 0, 0), 610 F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625), 611 F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75), 612 F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25), 613 F(51200000, P_GCC_GPLL0_OUT_EVEN, 1, 64, 375), 614 F(61440000, P_GCC_GPLL0_OUT_EVEN, 1, 128, 625), 615 F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75), 616 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), 617 F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15), 618 F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25), 619 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 620 { } 621 }; 622 623 static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = { 624 .name = "gcc_qupv3_wrap1_s3_clk_src", 625 .parent_data = gcc_parent_data_0, 626 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 627 .flags = CLK_SET_RATE_PARENT, 628 .ops = &clk_rcg2_shared_no_init_park_ops, 629 }; 630 631 static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = { 632 .cmd_rcgr = 0x182a0, 633 .mnd_width = 16, 634 .hid_width = 5, 635 .parent_map = gcc_parent_map_0, 636 .freq_tbl = ftbl_gcc_qupv3_wrap1_s3_clk_src, 637 .hw_clk_ctrl = true, 638 .clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init, 639 }; 640 641 static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = { 642 .name = "gcc_qupv3_wrap1_s4_clk_src", 643 .parent_data = gcc_parent_data_0, 644 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 645 .flags = CLK_SET_RATE_PARENT, 646 .ops = &clk_rcg2_shared_no_init_park_ops, 647 }; 648 649 static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = { 650 .cmd_rcgr = 0x183dc, 651 .mnd_width = 16, 652 .hid_width = 5, 653 .parent_map = gcc_parent_map_0, 654 .freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src, 655 .hw_clk_ctrl = true, 656 .clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init, 657 }; 658 659 static const struct freq_tbl ftbl_gcc_qupv3_wrap1_s5_clk_src[] = { 660 F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625), 661 F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625), 662 F(19200000, P_BI_TCXO, 1, 0, 0), 663 F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625), 664 F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75), 665 F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25), 666 F(51200000, P_GCC_GPLL0_OUT_EVEN, 1, 64, 375), 667 F(61440000, P_GCC_GPLL0_OUT_EVEN, 1, 128, 625), 668 F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75), 669 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), 670 F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15), 671 F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25), 672 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 673 F(102400000, P_GCC_GPLL0_OUT_EVEN, 1, 128, 375), 674 F(112000000, P_GCC_GPLL0_OUT_EVEN, 1, 28, 75), 675 F(117964800, P_GCC_GPLL0_OUT_EVEN, 1, 6144, 15625), 676 F(128000000, P_GCC_GPLL0_OUT_MAIN, 1, 16, 75), 677 { } 678 }; 679 680 static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = { 681 .name = "gcc_qupv3_wrap1_s5_clk_src", 682 .parent_data = gcc_parent_data_0, 683 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 684 .flags = CLK_SET_RATE_PARENT, 685 .ops = &clk_rcg2_shared_no_init_park_ops, 686 }; 687 688 static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = { 689 .cmd_rcgr = 0x18518, 690 .mnd_width = 16, 691 .hid_width = 5, 692 .parent_map = gcc_parent_map_0, 693 .freq_tbl = ftbl_gcc_qupv3_wrap1_s5_clk_src, 694 .hw_clk_ctrl = true, 695 .clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init, 696 }; 697 698 static struct clk_init_data gcc_qupv3_wrap1_s6_clk_src_init = { 699 .name = "gcc_qupv3_wrap1_s6_clk_src", 700 .parent_data = gcc_parent_data_0, 701 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 702 .flags = CLK_SET_RATE_PARENT, 703 .ops = &clk_rcg2_shared_no_init_park_ops, 704 }; 705 706 static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = { 707 .cmd_rcgr = 0x18654, 708 .mnd_width = 16, 709 .hid_width = 5, 710 .parent_map = gcc_parent_map_0, 711 .freq_tbl = ftbl_gcc_qupv3_wrap1_s3_clk_src, 712 .hw_clk_ctrl = true, 713 .clkr.hw.init = &gcc_qupv3_wrap1_s6_clk_src_init, 714 }; 715 716 static struct clk_init_data gcc_qupv3_wrap1_s7_clk_src_init = { 717 .name = "gcc_qupv3_wrap1_s7_clk_src", 718 .parent_data = gcc_parent_data_0, 719 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 720 .flags = CLK_SET_RATE_PARENT, 721 .ops = &clk_rcg2_shared_no_init_park_ops, 722 }; 723 724 static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src = { 725 .cmd_rcgr = 0x18790, 726 .mnd_width = 16, 727 .hid_width = 5, 728 .parent_map = gcc_parent_map_0, 729 .freq_tbl = ftbl_gcc_qupv3_wrap1_s3_clk_src, 730 .hw_clk_ctrl = true, 731 .clkr.hw.init = &gcc_qupv3_wrap1_s7_clk_src_init, 732 }; 733 734 static struct clk_init_data gcc_qupv3_wrap2_s0_clk_src_init = { 735 .name = "gcc_qupv3_wrap2_s0_clk_src", 736 .parent_data = gcc_parent_data_0, 737 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 738 .flags = CLK_SET_RATE_PARENT, 739 .ops = &clk_rcg2_shared_no_init_park_ops, 740 }; 741 742 static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = { 743 .cmd_rcgr = 0x1e014, 744 .mnd_width = 16, 745 .hid_width = 5, 746 .parent_map = gcc_parent_map_0, 747 .freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src, 748 .hw_clk_ctrl = true, 749 .clkr.hw.init = &gcc_qupv3_wrap2_s0_clk_src_init, 750 }; 751 752 static struct clk_init_data gcc_qupv3_wrap2_s1_clk_src_init = { 753 .name = "gcc_qupv3_wrap2_s1_clk_src", 754 .parent_data = gcc_parent_data_0, 755 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 756 .flags = CLK_SET_RATE_PARENT, 757 .ops = &clk_rcg2_shared_no_init_park_ops, 758 }; 759 760 static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = { 761 .cmd_rcgr = 0x1e150, 762 .mnd_width = 16, 763 .hid_width = 5, 764 .parent_map = gcc_parent_map_0, 765 .freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src, 766 .hw_clk_ctrl = true, 767 .clkr.hw.init = &gcc_qupv3_wrap2_s1_clk_src_init, 768 }; 769 770 static const struct freq_tbl ftbl_gcc_qupv3_wrap2_s2_clk_src[] = { 771 F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625), 772 F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625), 773 F(19200000, P_BI_TCXO, 1, 0, 0), 774 F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625), 775 F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75), 776 F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25), 777 F(51200000, P_GCC_GPLL0_OUT_EVEN, 1, 64, 375), 778 F(61440000, P_GCC_GPLL0_OUT_EVEN, 1, 128, 625), 779 F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75), 780 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), 781 F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15), 782 F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25), 783 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 784 F(102400000, P_GCC_GPLL0_OUT_EVEN, 1, 128, 375), 785 F(112000000, P_GCC_GPLL0_OUT_EVEN, 1, 28, 75), 786 F(117964800, P_GCC_GPLL0_OUT_EVEN, 1, 6144, 15625), 787 F(125000000, P_GCC_GPLL7_OUT_MAIN, 4, 0, 0), 788 { } 789 }; 790 791 static struct clk_init_data gcc_qupv3_wrap2_s2_clk_src_init = { 792 .name = "gcc_qupv3_wrap2_s2_clk_src", 793 .parent_data = gcc_parent_data_4, 794 .num_parents = ARRAY_SIZE(gcc_parent_data_4), 795 .flags = CLK_SET_RATE_PARENT, 796 .ops = &clk_rcg2_shared_no_init_park_ops, 797 }; 798 799 static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = { 800 .cmd_rcgr = 0x1e28c, 801 .mnd_width = 16, 802 .hid_width = 5, 803 .parent_map = gcc_parent_map_4, 804 .freq_tbl = ftbl_gcc_qupv3_wrap2_s2_clk_src, 805 .hw_clk_ctrl = true, 806 .clkr.hw.init = &gcc_qupv3_wrap2_s2_clk_src_init, 807 }; 808 809 static struct clk_init_data gcc_qupv3_wrap2_s3_clk_src_init = { 810 .name = "gcc_qupv3_wrap2_s3_clk_src", 811 .parent_data = gcc_parent_data_0, 812 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 813 .flags = CLK_SET_RATE_PARENT, 814 .ops = &clk_rcg2_shared_no_init_park_ops, 815 }; 816 817 static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = { 818 .cmd_rcgr = 0x1e3c8, 819 .mnd_width = 16, 820 .hid_width = 5, 821 .parent_map = gcc_parent_map_0, 822 .freq_tbl = ftbl_gcc_qupv3_wrap1_s3_clk_src, 823 .hw_clk_ctrl = true, 824 .clkr.hw.init = &gcc_qupv3_wrap2_s3_clk_src_init, 825 }; 826 827 static struct clk_init_data gcc_qupv3_wrap2_s4_clk_src_init = { 828 .name = "gcc_qupv3_wrap2_s4_clk_src", 829 .parent_data = gcc_parent_data_0, 830 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 831 .flags = CLK_SET_RATE_PARENT, 832 .ops = &clk_rcg2_shared_no_init_park_ops, 833 }; 834 835 static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = { 836 .cmd_rcgr = 0x1e504, 837 .mnd_width = 16, 838 .hid_width = 5, 839 .parent_map = gcc_parent_map_0, 840 .freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src, 841 .hw_clk_ctrl = true, 842 .clkr.hw.init = &gcc_qupv3_wrap2_s4_clk_src_init, 843 }; 844 845 static struct clk_init_data gcc_qupv3_wrap2_s5_clk_src_init = { 846 .name = "gcc_qupv3_wrap2_s5_clk_src", 847 .parent_data = gcc_parent_data_0, 848 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 849 .flags = CLK_SET_RATE_PARENT, 850 .ops = &clk_rcg2_shared_no_init_park_ops, 851 }; 852 853 static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = { 854 .cmd_rcgr = 0x1e640, 855 .mnd_width = 16, 856 .hid_width = 5, 857 .parent_map = gcc_parent_map_0, 858 .freq_tbl = ftbl_gcc_qupv3_wrap1_s5_clk_src, 859 .hw_clk_ctrl = true, 860 .clkr.hw.init = &gcc_qupv3_wrap2_s5_clk_src_init, 861 }; 862 863 static struct clk_init_data gcc_qupv3_wrap2_s6_clk_src_init = { 864 .name = "gcc_qupv3_wrap2_s6_clk_src", 865 .parent_data = gcc_parent_data_4, 866 .num_parents = ARRAY_SIZE(gcc_parent_data_4), 867 .flags = CLK_SET_RATE_PARENT, 868 .ops = &clk_rcg2_shared_no_init_park_ops, 869 }; 870 871 static struct clk_rcg2 gcc_qupv3_wrap2_s6_clk_src = { 872 .cmd_rcgr = 0x1e77c, 873 .mnd_width = 16, 874 .hid_width = 5, 875 .parent_map = gcc_parent_map_4, 876 .freq_tbl = ftbl_gcc_qupv3_wrap1_s3_clk_src, 877 .hw_clk_ctrl = true, 878 .clkr.hw.init = &gcc_qupv3_wrap2_s6_clk_src_init, 879 }; 880 881 static struct clk_init_data gcc_qupv3_wrap2_s7_clk_src_init = { 882 .name = "gcc_qupv3_wrap2_s7_clk_src", 883 .parent_data = gcc_parent_data_0, 884 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 885 .flags = CLK_SET_RATE_PARENT, 886 .ops = &clk_rcg2_shared_no_init_park_ops, 887 }; 888 889 static struct clk_rcg2 gcc_qupv3_wrap2_s7_clk_src = { 890 .cmd_rcgr = 0x1e8b8, 891 .mnd_width = 16, 892 .hid_width = 5, 893 .parent_map = gcc_parent_map_0, 894 .freq_tbl = ftbl_gcc_qupv3_wrap1_s3_clk_src, 895 .hw_clk_ctrl = true, 896 .clkr.hw.init = &gcc_qupv3_wrap2_s7_clk_src_init, 897 }; 898 899 static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = { 900 F(144000, P_BI_TCXO, 16, 3, 25), 901 F(400000, P_BI_TCXO, 12, 1, 4), 902 F(20000000, P_GCC_GPLL0_OUT_EVEN, 5, 1, 3), 903 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0), 904 F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0), 905 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0), 906 F(192000000, P_GCC_GPLL8_OUT_MAIN, 2, 0, 0), 907 F(384000000, P_GCC_GPLL8_OUT_MAIN, 1, 0, 0), 908 { } 909 }; 910 911 static struct clk_rcg2 gcc_sdcc1_apps_clk_src = { 912 .cmd_rcgr = 0xa9018, 913 .mnd_width = 8, 914 .hid_width = 5, 915 .parent_map = gcc_parent_map_5, 916 .freq_tbl = ftbl_gcc_sdcc1_apps_clk_src, 917 .hw_clk_ctrl = true, 918 .clkr.hw.init = &(const struct clk_init_data) { 919 .name = "gcc_sdcc1_apps_clk_src", 920 .parent_data = gcc_parent_data_5, 921 .num_parents = ARRAY_SIZE(gcc_parent_data_5), 922 .flags = CLK_SET_RATE_PARENT, 923 .ops = &clk_rcg2_shared_floor_ops, 924 }, 925 }; 926 927 static const struct freq_tbl ftbl_gcc_sdcc1_ice_core_clk_src[] = { 928 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0), 929 F(150000000, P_GCC_GPLL0_OUT_EVEN, 2, 0, 0), 930 F(300000000, P_GCC_GPLL0_OUT_EVEN, 1, 0, 0), 931 { } 932 }; 933 934 static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src = { 935 .cmd_rcgr = 0xa9040, 936 .mnd_width = 0, 937 .hid_width = 5, 938 .parent_map = gcc_parent_map_5, 939 .freq_tbl = ftbl_gcc_sdcc1_ice_core_clk_src, 940 .hw_clk_ctrl = true, 941 .clkr.hw.init = &(const struct clk_init_data) { 942 .name = "gcc_sdcc1_ice_core_clk_src", 943 .parent_data = gcc_parent_data_5, 944 .num_parents = ARRAY_SIZE(gcc_parent_data_5), 945 .flags = CLK_SET_RATE_PARENT, 946 .ops = &clk_rcg2_shared_floor_ops, 947 }, 948 }; 949 950 static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = { 951 F(400000, P_BI_TCXO, 12, 1, 4), 952 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0), 953 F(37500000, P_GCC_GPLL0_OUT_EVEN, 8, 0, 0), 954 F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0), 955 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0), 956 F(202000000, P_GCC_GPLL9_OUT_MAIN, 4, 0, 0), 957 { } 958 }; 959 960 static struct clk_rcg2 gcc_sdcc2_apps_clk_src = { 961 .cmd_rcgr = 0x1401c, 962 .mnd_width = 8, 963 .hid_width = 5, 964 .parent_map = gcc_parent_map_7, 965 .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src, 966 .hw_clk_ctrl = true, 967 .clkr.hw.init = &(const struct clk_init_data) { 968 .name = "gcc_sdcc2_apps_clk_src", 969 .parent_data = gcc_parent_data_7, 970 .num_parents = ARRAY_SIZE(gcc_parent_data_7), 971 .flags = CLK_SET_RATE_PARENT, 972 .ops = &clk_rcg2_shared_floor_ops, 973 }, 974 }; 975 976 static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = { 977 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0), 978 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0), 979 F(201500000, P_GCC_GPLL4_OUT_MAIN, 4, 0, 0), 980 F(403000000, P_GCC_GPLL4_OUT_MAIN, 2, 0, 0), 981 { } 982 }; 983 984 static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = { 985 .cmd_rcgr = 0x77034, 986 .mnd_width = 8, 987 .hid_width = 5, 988 .parent_map = gcc_parent_map_2, 989 .freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src, 990 .hw_clk_ctrl = true, 991 .clkr.hw.init = &(const struct clk_init_data) { 992 .name = "gcc_ufs_phy_axi_clk_src", 993 .parent_data = gcc_parent_data_2, 994 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 995 .flags = CLK_SET_RATE_PARENT, 996 .ops = &clk_rcg2_shared_no_init_park_ops, 997 }, 998 }; 999 1000 static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = { 1001 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0), 1002 F(201500000, P_GCC_GPLL4_OUT_MAIN, 4, 0, 0), 1003 F(403000000, P_GCC_GPLL4_OUT_MAIN, 2, 0, 0), 1004 { } 1005 }; 1006 1007 static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = { 1008 .cmd_rcgr = 0x7708c, 1009 .mnd_width = 0, 1010 .hid_width = 5, 1011 .parent_map = gcc_parent_map_2, 1012 .freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src, 1013 .hw_clk_ctrl = true, 1014 .clkr.hw.init = &(const struct clk_init_data) { 1015 .name = "gcc_ufs_phy_ice_core_clk_src", 1016 .parent_data = gcc_parent_data_2, 1017 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 1018 .flags = CLK_SET_RATE_PARENT, 1019 .ops = &clk_rcg2_shared_no_init_park_ops, 1020 }, 1021 }; 1022 1023 static const struct freq_tbl ftbl_gcc_ufs_phy_phy_aux_clk_src[] = { 1024 F(9600000, P_BI_TCXO, 2, 0, 0), 1025 F(19200000, P_BI_TCXO, 1, 0, 0), 1026 { } 1027 }; 1028 1029 static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = { 1030 .cmd_rcgr = 0x770c0, 1031 .mnd_width = 0, 1032 .hid_width = 5, 1033 .parent_map = gcc_parent_map_6, 1034 .freq_tbl = ftbl_gcc_ufs_phy_phy_aux_clk_src, 1035 .hw_clk_ctrl = true, 1036 .clkr.hw.init = &(const struct clk_init_data) { 1037 .name = "gcc_ufs_phy_phy_aux_clk_src", 1038 .parent_data = gcc_parent_data_6, 1039 .num_parents = ARRAY_SIZE(gcc_parent_data_6), 1040 .flags = CLK_SET_RATE_PARENT, 1041 .ops = &clk_rcg2_shared_no_init_park_ops, 1042 }, 1043 }; 1044 1045 static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = { 1046 .cmd_rcgr = 0x770a4, 1047 .mnd_width = 0, 1048 .hid_width = 5, 1049 .parent_map = gcc_parent_map_2, 1050 .freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src, 1051 .hw_clk_ctrl = true, 1052 .clkr.hw.init = &(const struct clk_init_data) { 1053 .name = "gcc_ufs_phy_unipro_core_clk_src", 1054 .parent_data = gcc_parent_data_2, 1055 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 1056 .flags = CLK_SET_RATE_PARENT, 1057 .ops = &clk_rcg2_shared_no_init_park_ops, 1058 }, 1059 }; 1060 1061 static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = { 1062 F(66666667, P_GCC_GPLL0_OUT_EVEN, 4.5, 0, 0), 1063 F(133333333, P_GCC_GPLL0_OUT_MAIN, 4.5, 0, 0), 1064 F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0), 1065 F(240000000, P_GCC_GPLL0_OUT_MAIN, 2.5, 0, 0), 1066 { } 1067 }; 1068 1069 static struct clk_rcg2 gcc_usb30_prim_master_clk_src = { 1070 .cmd_rcgr = 0x39030, 1071 .mnd_width = 8, 1072 .hid_width = 5, 1073 .parent_map = gcc_parent_map_0, 1074 .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src, 1075 .hw_clk_ctrl = true, 1076 .clkr.hw.init = &(const struct clk_init_data) { 1077 .name = "gcc_usb30_prim_master_clk_src", 1078 .parent_data = gcc_parent_data_0, 1079 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1080 .flags = CLK_SET_RATE_PARENT, 1081 .ops = &clk_rcg2_shared_ops, 1082 }, 1083 }; 1084 1085 static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = { 1086 .cmd_rcgr = 0x39048, 1087 .mnd_width = 0, 1088 .hid_width = 5, 1089 .parent_map = gcc_parent_map_0, 1090 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 1091 .hw_clk_ctrl = true, 1092 .clkr.hw.init = &(const struct clk_init_data) { 1093 .name = "gcc_usb30_prim_mock_utmi_clk_src", 1094 .parent_data = gcc_parent_data_0, 1095 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1096 .flags = CLK_SET_RATE_PARENT, 1097 .ops = &clk_rcg2_shared_ops, 1098 }, 1099 }; 1100 1101 static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = { 1102 .cmd_rcgr = 0x39074, 1103 .mnd_width = 0, 1104 .hid_width = 5, 1105 .parent_map = gcc_parent_map_3, 1106 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 1107 .hw_clk_ctrl = true, 1108 .clkr.hw.init = &(const struct clk_init_data) { 1109 .name = "gcc_usb3_prim_phy_aux_clk_src", 1110 .parent_data = gcc_parent_data_3, 1111 .num_parents = ARRAY_SIZE(gcc_parent_data_3), 1112 .flags = CLK_SET_RATE_PARENT, 1113 .ops = &clk_rcg2_shared_ops, 1114 }, 1115 }; 1116 1117 static struct clk_regmap_div gcc_pcie_0_pipe_div2_clk_src = { 1118 .reg = 0x6b0a4, 1119 .shift = 0, 1120 .width = 4, 1121 .clkr.hw.init = &(const struct clk_init_data) { 1122 .name = "gcc_pcie_0_pipe_div2_clk_src", 1123 .parent_hws = (const struct clk_hw*[]) { 1124 &gcc_pcie_0_pipe_clk_src.clkr.hw, 1125 }, 1126 .num_parents = 1, 1127 .flags = CLK_SET_RATE_PARENT, 1128 .ops = &clk_regmap_div_ro_ops, 1129 }, 1130 }; 1131 1132 static struct clk_regmap_div gcc_pcie_1_pipe_div2_clk_src = { 1133 .reg = 0xac0a0, 1134 .shift = 0, 1135 .width = 4, 1136 .clkr.hw.init = &(const struct clk_init_data) { 1137 .name = "gcc_pcie_1_pipe_div2_clk_src", 1138 .parent_hws = (const struct clk_hw*[]) { 1139 &gcc_pcie_1_pipe_clk_src.clkr.hw, 1140 }, 1141 .num_parents = 1, 1142 .flags = CLK_SET_RATE_PARENT, 1143 .ops = &clk_regmap_div_ro_ops, 1144 }, 1145 }; 1146 1147 static struct clk_regmap_div gcc_qupv3_wrap1_s2_clk_src = { 1148 .reg = 0x1828c, 1149 .shift = 0, 1150 .width = 4, 1151 .clkr.hw.init = &(const struct clk_init_data) { 1152 .name = "gcc_qupv3_wrap1_s2_clk_src", 1153 .parent_hws = (const struct clk_hw*[]) { 1154 &gcc_qupv3_wrap1_qspi_ref_clk_src.clkr.hw, 1155 }, 1156 .num_parents = 1, 1157 .flags = CLK_SET_RATE_PARENT, 1158 .ops = &clk_regmap_div_ro_ops, 1159 }, 1160 }; 1161 1162 static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv_clk_src = { 1163 .reg = 0x39060, 1164 .shift = 0, 1165 .width = 4, 1166 .clkr.hw.init = &(const struct clk_init_data) { 1167 .name = "gcc_usb30_prim_mock_utmi_postdiv_clk_src", 1168 .parent_hws = (const struct clk_hw*[]) { 1169 &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw, 1170 }, 1171 .num_parents = 1, 1172 .flags = CLK_SET_RATE_PARENT, 1173 .ops = &clk_regmap_div_ro_ops, 1174 }, 1175 }; 1176 1177 static struct clk_branch gcc_aggre_noc_pcie_axi_clk = { 1178 .halt_reg = 0x10068, 1179 .halt_check = BRANCH_HALT_SKIP, 1180 .hwcg_reg = 0x10068, 1181 .hwcg_bit = 1, 1182 .clkr = { 1183 .enable_reg = 0x52000, 1184 .enable_mask = BIT(30), 1185 .hw.init = &(const struct clk_init_data) { 1186 .name = "gcc_aggre_noc_pcie_axi_clk", 1187 .ops = &clk_branch2_ops, 1188 }, 1189 }, 1190 }; 1191 1192 static struct clk_branch gcc_aggre_ufs_phy_axi_clk = { 1193 .halt_reg = 0x770f4, 1194 .halt_check = BRANCH_HALT_VOTED, 1195 .hwcg_reg = 0x770f4, 1196 .hwcg_bit = 1, 1197 .clkr = { 1198 .enable_reg = 0x770f4, 1199 .enable_mask = BIT(0), 1200 .hw.init = &(const struct clk_init_data) { 1201 .name = "gcc_aggre_ufs_phy_axi_clk", 1202 .parent_hws = (const struct clk_hw*[]) { 1203 &gcc_ufs_phy_axi_clk_src.clkr.hw, 1204 }, 1205 .num_parents = 1, 1206 .flags = CLK_SET_RATE_PARENT, 1207 .ops = &clk_branch2_ops, 1208 }, 1209 }, 1210 }; 1211 1212 static struct clk_branch gcc_aggre_usb3_prim_axi_clk = { 1213 .halt_reg = 0x39094, 1214 .halt_check = BRANCH_HALT_VOTED, 1215 .clkr = { 1216 .enable_reg = 0x39094, 1217 .enable_mask = BIT(0), 1218 .hw.init = &(const struct clk_init_data) { 1219 .name = "gcc_aggre_usb3_prim_axi_clk", 1220 .parent_hws = (const struct clk_hw*[]) { 1221 &gcc_usb30_prim_master_clk_src.clkr.hw, 1222 }, 1223 .num_parents = 1, 1224 .flags = CLK_SET_RATE_PARENT, 1225 .ops = &clk_branch2_ops, 1226 }, 1227 }, 1228 }; 1229 1230 static struct clk_branch gcc_boot_rom_ahb_clk = { 1231 .halt_reg = 0x38004, 1232 .halt_check = BRANCH_HALT_VOTED, 1233 .hwcg_reg = 0x38004, 1234 .hwcg_bit = 1, 1235 .clkr = { 1236 .enable_reg = 0x52000, 1237 .enable_mask = BIT(10), 1238 .hw.init = &(const struct clk_init_data) { 1239 .name = "gcc_boot_rom_ahb_clk", 1240 .ops = &clk_branch2_ops, 1241 }, 1242 }, 1243 }; 1244 1245 static struct clk_branch gcc_camera_hf_axi_clk = { 1246 .halt_reg = 0x26014, 1247 .halt_check = BRANCH_HALT_SKIP, 1248 .hwcg_reg = 0x26014, 1249 .hwcg_bit = 1, 1250 .clkr = { 1251 .enable_reg = 0x26014, 1252 .enable_mask = BIT(0), 1253 .hw.init = &(const struct clk_init_data) { 1254 .name = "gcc_camera_hf_axi_clk", 1255 .ops = &clk_branch2_ops, 1256 }, 1257 }, 1258 }; 1259 1260 static struct clk_branch gcc_camera_sf_axi_clk = { 1261 .halt_reg = 0x26024, 1262 .halt_check = BRANCH_HALT_SKIP, 1263 .hwcg_reg = 0x26024, 1264 .hwcg_bit = 1, 1265 .clkr = { 1266 .enable_reg = 0x26024, 1267 .enable_mask = BIT(0), 1268 .hw.init = &(const struct clk_init_data) { 1269 .name = "gcc_camera_sf_axi_clk", 1270 .ops = &clk_branch2_ops, 1271 }, 1272 }, 1273 }; 1274 1275 static struct clk_branch gcc_cfg_noc_pcie_anoc_ahb_clk = { 1276 .halt_reg = 0x10050, 1277 .halt_check = BRANCH_HALT_SKIP, 1278 .hwcg_reg = 0x10050, 1279 .hwcg_bit = 1, 1280 .clkr = { 1281 .enable_reg = 0x52000, 1282 .enable_mask = BIT(20), 1283 .hw.init = &(const struct clk_init_data) { 1284 .name = "gcc_cfg_noc_pcie_anoc_ahb_clk", 1285 .ops = &clk_branch2_ops, 1286 }, 1287 }, 1288 }; 1289 1290 static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = { 1291 .halt_reg = 0x39090, 1292 .halt_check = BRANCH_HALT_VOTED, 1293 .clkr = { 1294 .enable_reg = 0x39090, 1295 .enable_mask = BIT(0), 1296 .hw.init = &(const struct clk_init_data) { 1297 .name = "gcc_cfg_noc_usb3_prim_axi_clk", 1298 .parent_hws = (const struct clk_hw*[]) { 1299 &gcc_usb30_prim_master_clk_src.clkr.hw, 1300 }, 1301 .num_parents = 1, 1302 .flags = CLK_SET_RATE_PARENT, 1303 .ops = &clk_branch2_ops, 1304 }, 1305 }, 1306 }; 1307 1308 static struct clk_branch gcc_cnoc_pcie_sf_axi_clk = { 1309 .halt_reg = 0x10058, 1310 .halt_check = BRANCH_HALT_VOTED, 1311 .hwcg_reg = 0x10058, 1312 .hwcg_bit = 1, 1313 .clkr = { 1314 .enable_reg = 0x52008, 1315 .enable_mask = BIT(6), 1316 .hw.init = &(const struct clk_init_data) { 1317 .name = "gcc_cnoc_pcie_sf_axi_clk", 1318 .ops = &clk_branch2_ops, 1319 }, 1320 }, 1321 }; 1322 1323 static struct clk_branch gcc_ddrss_gpu_axi_clk = { 1324 .halt_reg = 0x71158, 1325 .halt_check = BRANCH_HALT_SKIP, 1326 .hwcg_reg = 0x71158, 1327 .hwcg_bit = 1, 1328 .clkr = { 1329 .enable_reg = 0x71158, 1330 .enable_mask = BIT(0), 1331 .hw.init = &(const struct clk_init_data) { 1332 .name = "gcc_ddrss_gpu_axi_clk", 1333 .ops = &clk_branch2_aon_ops, 1334 }, 1335 }, 1336 }; 1337 1338 static struct clk_branch gcc_ddrss_pcie_sf_qtb_clk = { 1339 .halt_reg = 0x1007c, 1340 .halt_check = BRANCH_HALT_SKIP, 1341 .hwcg_reg = 0x1007c, 1342 .hwcg_bit = 1, 1343 .clkr = { 1344 .enable_reg = 0x52000, 1345 .enable_mask = BIT(19), 1346 .hw.init = &(const struct clk_init_data) { 1347 .name = "gcc_ddrss_pcie_sf_qtb_clk", 1348 .ops = &clk_branch2_ops, 1349 }, 1350 }, 1351 }; 1352 1353 static struct clk_branch gcc_disp_hf_axi_clk = { 1354 .halt_reg = 0x27008, 1355 .halt_check = BRANCH_HALT_SKIP, 1356 .clkr = { 1357 .enable_reg = 0x27008, 1358 .enable_mask = BIT(0), 1359 .hw.init = &(const struct clk_init_data) { 1360 .name = "gcc_disp_hf_axi_clk", 1361 .ops = &clk_branch2_ops, 1362 }, 1363 }, 1364 }; 1365 1366 static struct clk_branch gcc_gp1_clk = { 1367 .halt_reg = 0x64000, 1368 .halt_check = BRANCH_HALT, 1369 .clkr = { 1370 .enable_reg = 0x64000, 1371 .enable_mask = BIT(0), 1372 .hw.init = &(const struct clk_init_data) { 1373 .name = "gcc_gp1_clk", 1374 .parent_hws = (const struct clk_hw*[]) { 1375 &gcc_gp1_clk_src.clkr.hw, 1376 }, 1377 .num_parents = 1, 1378 .flags = CLK_SET_RATE_PARENT, 1379 .ops = &clk_branch2_ops, 1380 }, 1381 }, 1382 }; 1383 1384 static struct clk_branch gcc_gp2_clk = { 1385 .halt_reg = 0x65000, 1386 .halt_check = BRANCH_HALT, 1387 .clkr = { 1388 .enable_reg = 0x65000, 1389 .enable_mask = BIT(0), 1390 .hw.init = &(const struct clk_init_data) { 1391 .name = "gcc_gp2_clk", 1392 .parent_hws = (const struct clk_hw*[]) { 1393 &gcc_gp2_clk_src.clkr.hw, 1394 }, 1395 .num_parents = 1, 1396 .flags = CLK_SET_RATE_PARENT, 1397 .ops = &clk_branch2_ops, 1398 }, 1399 }, 1400 }; 1401 1402 static struct clk_branch gcc_gp3_clk = { 1403 .halt_reg = 0x66000, 1404 .halt_check = BRANCH_HALT, 1405 .clkr = { 1406 .enable_reg = 0x66000, 1407 .enable_mask = BIT(0), 1408 .hw.init = &(const struct clk_init_data) { 1409 .name = "gcc_gp3_clk", 1410 .parent_hws = (const struct clk_hw*[]) { 1411 &gcc_gp3_clk_src.clkr.hw, 1412 }, 1413 .num_parents = 1, 1414 .flags = CLK_SET_RATE_PARENT, 1415 .ops = &clk_branch2_ops, 1416 }, 1417 }, 1418 }; 1419 1420 static struct clk_branch gcc_gpu_gemnoc_gfx_clk = { 1421 .halt_reg = 0x71010, 1422 .halt_check = BRANCH_HALT_VOTED, 1423 .hwcg_reg = 0x71010, 1424 .hwcg_bit = 1, 1425 .clkr = { 1426 .enable_reg = 0x71010, 1427 .enable_mask = BIT(0), 1428 .hw.init = &(const struct clk_init_data) { 1429 .name = "gcc_gpu_gemnoc_gfx_clk", 1430 .ops = &clk_branch2_ops, 1431 }, 1432 }, 1433 }; 1434 1435 static struct clk_branch gcc_gpu_gpll0_cph_clk_src = { 1436 .halt_reg = 0x71150, 1437 .halt_check = BRANCH_HALT_ENABLE_VOTED, 1438 .clkr = { 1439 .enable_reg = 0x71150, 1440 .enable_mask = BIT(0), 1441 .hw.init = &(const struct clk_init_data) { 1442 .name = "gcc_gpu_gpll0_cph_clk_src", 1443 .parent_hws = (const struct clk_hw*[]) { 1444 &gcc_gpll0.clkr.hw, 1445 }, 1446 .num_parents = 1, 1447 .flags = CLK_SET_RATE_PARENT, 1448 .ops = &clk_branch2_ops, 1449 }, 1450 }, 1451 }; 1452 1453 static struct clk_branch gcc_gpu_gpll0_div_cph_clk_src = { 1454 .halt_reg = 0x71154, 1455 .halt_check = BRANCH_HALT_ENABLE_VOTED, 1456 .clkr = { 1457 .enable_reg = 0x71154, 1458 .enable_mask = BIT(0), 1459 .hw.init = &(const struct clk_init_data) { 1460 .name = "gcc_gpu_gpll0_div_cph_clk_src", 1461 .parent_hws = (const struct clk_hw*[]) { 1462 &gcc_gpll0_out_even.clkr.hw, 1463 }, 1464 .num_parents = 1, 1465 .flags = CLK_SET_RATE_PARENT, 1466 .ops = &clk_branch2_ops, 1467 }, 1468 }, 1469 }; 1470 1471 static struct clk_branch gcc_gpu_smmu_vote_clk = { 1472 .halt_reg = 0x7d000, 1473 .halt_check = BRANCH_HALT_VOTED, 1474 .clkr = { 1475 .enable_reg = 0x7d000, 1476 .enable_mask = BIT(0), 1477 .hw.init = &(const struct clk_init_data) { 1478 .name = "gcc_gpu_smmu_vote_clk", 1479 .ops = &clk_branch2_ops, 1480 }, 1481 }, 1482 }; 1483 1484 static struct clk_branch gcc_mmu_tcu_vote_clk = { 1485 .halt_reg = 0x7d02c, 1486 .halt_check = BRANCH_HALT_VOTED, 1487 .clkr = { 1488 .enable_reg = 0x7d02c, 1489 .enable_mask = BIT(0), 1490 .hw.init = &(const struct clk_init_data) { 1491 .name = "gcc_mmu_tcu_vote_clk", 1492 .ops = &clk_branch2_ops, 1493 }, 1494 }, 1495 }; 1496 1497 static struct clk_branch gcc_pcie_0_aux_clk = { 1498 .halt_reg = 0x6b044, 1499 .halt_check = BRANCH_HALT_VOTED, 1500 .clkr = { 1501 .enable_reg = 0x52008, 1502 .enable_mask = BIT(3), 1503 .hw.init = &(const struct clk_init_data) { 1504 .name = "gcc_pcie_0_aux_clk", 1505 .parent_hws = (const struct clk_hw*[]) { 1506 &gcc_pcie_0_aux_clk_src.clkr.hw, 1507 }, 1508 .num_parents = 1, 1509 .flags = CLK_SET_RATE_PARENT, 1510 .ops = &clk_branch2_ops, 1511 }, 1512 }, 1513 }; 1514 1515 static struct clk_branch gcc_pcie_0_cfg_ahb_clk = { 1516 .halt_reg = 0x6b040, 1517 .halt_check = BRANCH_HALT_VOTED, 1518 .hwcg_reg = 0x6b040, 1519 .hwcg_bit = 1, 1520 .clkr = { 1521 .enable_reg = 0x52008, 1522 .enable_mask = BIT(2), 1523 .hw.init = &(const struct clk_init_data) { 1524 .name = "gcc_pcie_0_cfg_ahb_clk", 1525 .ops = &clk_branch2_ops, 1526 }, 1527 }, 1528 }; 1529 1530 static struct clk_branch gcc_pcie_0_mstr_axi_clk = { 1531 .halt_reg = 0x6b030, 1532 .halt_check = BRANCH_HALT_SKIP, 1533 .hwcg_reg = 0x6b030, 1534 .hwcg_bit = 1, 1535 .clkr = { 1536 .enable_reg = 0x52008, 1537 .enable_mask = BIT(1), 1538 .hw.init = &(const struct clk_init_data) { 1539 .name = "gcc_pcie_0_mstr_axi_clk", 1540 .ops = &clk_branch2_ops, 1541 }, 1542 }, 1543 }; 1544 1545 static struct clk_branch gcc_pcie_0_phy_rchng_clk = { 1546 .halt_reg = 0x6b064, 1547 .halt_check = BRANCH_HALT_VOTED, 1548 .clkr = { 1549 .enable_reg = 0x52000, 1550 .enable_mask = BIT(22), 1551 .hw.init = &(const struct clk_init_data) { 1552 .name = "gcc_pcie_0_phy_rchng_clk", 1553 .parent_hws = (const struct clk_hw*[]) { 1554 &gcc_pcie_0_phy_rchng_clk_src.clkr.hw, 1555 }, 1556 .num_parents = 1, 1557 .flags = CLK_SET_RATE_PARENT, 1558 .ops = &clk_branch2_ops, 1559 }, 1560 }, 1561 }; 1562 1563 static struct clk_branch gcc_pcie_0_pipe_clk = { 1564 .halt_reg = 0x6b054, 1565 .halt_check = BRANCH_HALT_SKIP, 1566 .clkr = { 1567 .enable_reg = 0x52008, 1568 .enable_mask = BIT(4), 1569 .hw.init = &(const struct clk_init_data) { 1570 .name = "gcc_pcie_0_pipe_clk", 1571 .parent_hws = (const struct clk_hw*[]) { 1572 &gcc_pcie_0_pipe_clk_src.clkr.hw, 1573 }, 1574 .num_parents = 1, 1575 .flags = CLK_SET_RATE_PARENT, 1576 .ops = &clk_branch2_ops, 1577 }, 1578 }, 1579 }; 1580 1581 static struct clk_branch gcc_pcie_0_pipe_div2_clk = { 1582 .halt_reg = 0x6b0a8, 1583 .halt_check = BRANCH_HALT_SKIP, 1584 .clkr = { 1585 .enable_reg = 0x52018, 1586 .enable_mask = BIT(13), 1587 .hw.init = &(const struct clk_init_data) { 1588 .name = "gcc_pcie_0_pipe_div2_clk", 1589 .parent_hws = (const struct clk_hw*[]) { 1590 &gcc_pcie_0_pipe_div2_clk_src.clkr.hw, 1591 }, 1592 .num_parents = 1, 1593 .flags = CLK_SET_RATE_PARENT, 1594 .ops = &clk_branch2_ops, 1595 }, 1596 }, 1597 }; 1598 1599 static struct clk_branch gcc_pcie_0_slv_axi_clk = { 1600 .halt_reg = 0x6b020, 1601 .halt_check = BRANCH_HALT_VOTED, 1602 .hwcg_reg = 0x6b020, 1603 .hwcg_bit = 1, 1604 .clkr = { 1605 .enable_reg = 0x52008, 1606 .enable_mask = BIT(0), 1607 .hw.init = &(const struct clk_init_data) { 1608 .name = "gcc_pcie_0_slv_axi_clk", 1609 .ops = &clk_branch2_ops, 1610 }, 1611 }, 1612 }; 1613 1614 static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = { 1615 .halt_reg = 0x6b01c, 1616 .halt_check = BRANCH_HALT_VOTED, 1617 .clkr = { 1618 .enable_reg = 0x52008, 1619 .enable_mask = BIT(5), 1620 .hw.init = &(const struct clk_init_data) { 1621 .name = "gcc_pcie_0_slv_q2a_axi_clk", 1622 .ops = &clk_branch2_ops, 1623 }, 1624 }, 1625 }; 1626 1627 static struct clk_branch gcc_pcie_1_aux_clk = { 1628 .halt_reg = 0xac040, 1629 .halt_check = BRANCH_HALT_VOTED, 1630 .clkr = { 1631 .enable_reg = 0x52000, 1632 .enable_mask = BIT(29), 1633 .hw.init = &(const struct clk_init_data) { 1634 .name = "gcc_pcie_1_aux_clk", 1635 .parent_hws = (const struct clk_hw*[]) { 1636 &gcc_pcie_1_aux_clk_src.clkr.hw, 1637 }, 1638 .num_parents = 1, 1639 .flags = CLK_SET_RATE_PARENT, 1640 .ops = &clk_branch2_ops, 1641 }, 1642 }, 1643 }; 1644 1645 static struct clk_branch gcc_pcie_1_cfg_ahb_clk = { 1646 .halt_reg = 0xac03c, 1647 .halt_check = BRANCH_HALT_VOTED, 1648 .hwcg_reg = 0xac03c, 1649 .hwcg_bit = 1, 1650 .clkr = { 1651 .enable_reg = 0x52000, 1652 .enable_mask = BIT(28), 1653 .hw.init = &(const struct clk_init_data) { 1654 .name = "gcc_pcie_1_cfg_ahb_clk", 1655 .ops = &clk_branch2_ops, 1656 }, 1657 }, 1658 }; 1659 1660 static struct clk_branch gcc_pcie_1_mstr_axi_clk = { 1661 .halt_reg = 0xac02c, 1662 .halt_check = BRANCH_HALT_SKIP, 1663 .hwcg_reg = 0xac02c, 1664 .hwcg_bit = 1, 1665 .clkr = { 1666 .enable_reg = 0x52000, 1667 .enable_mask = BIT(27), 1668 .hw.init = &(const struct clk_init_data) { 1669 .name = "gcc_pcie_1_mstr_axi_clk", 1670 .ops = &clk_branch2_ops, 1671 }, 1672 }, 1673 }; 1674 1675 static struct clk_branch gcc_pcie_1_phy_rchng_clk = { 1676 .halt_reg = 0xac060, 1677 .halt_check = BRANCH_HALT_VOTED, 1678 .clkr = { 1679 .enable_reg = 0x52000, 1680 .enable_mask = BIT(24), 1681 .hw.init = &(const struct clk_init_data) { 1682 .name = "gcc_pcie_1_phy_rchng_clk", 1683 .parent_hws = (const struct clk_hw*[]) { 1684 &gcc_pcie_1_phy_rchng_clk_src.clkr.hw, 1685 }, 1686 .num_parents = 1, 1687 .flags = CLK_SET_RATE_PARENT, 1688 .ops = &clk_branch2_ops, 1689 }, 1690 }, 1691 }; 1692 1693 static struct clk_branch gcc_pcie_1_pipe_clk = { 1694 .halt_reg = 0xac050, 1695 .halt_check = BRANCH_HALT_SKIP, 1696 .clkr = { 1697 .enable_reg = 0x52000, 1698 .enable_mask = BIT(23), 1699 .hw.init = &(const struct clk_init_data) { 1700 .name = "gcc_pcie_1_pipe_clk", 1701 .parent_hws = (const struct clk_hw*[]) { 1702 &gcc_pcie_1_pipe_clk_src.clkr.hw, 1703 }, 1704 .num_parents = 1, 1705 .flags = CLK_SET_RATE_PARENT, 1706 .ops = &clk_branch2_ops, 1707 }, 1708 }, 1709 }; 1710 1711 static struct clk_branch gcc_pcie_1_pipe_div2_clk = { 1712 .halt_reg = 0xac0a4, 1713 .halt_check = BRANCH_HALT_SKIP, 1714 .clkr = { 1715 .enable_reg = 0x52018, 1716 .enable_mask = BIT(15), 1717 .hw.init = &(const struct clk_init_data) { 1718 .name = "gcc_pcie_1_pipe_div2_clk", 1719 .parent_hws = (const struct clk_hw*[]) { 1720 &gcc_pcie_1_pipe_div2_clk_src.clkr.hw, 1721 }, 1722 .num_parents = 1, 1723 .flags = CLK_SET_RATE_PARENT, 1724 .ops = &clk_branch2_ops, 1725 }, 1726 }, 1727 }; 1728 1729 static struct clk_branch gcc_pcie_1_slv_axi_clk = { 1730 .halt_reg = 0xac01c, 1731 .halt_check = BRANCH_HALT_VOTED, 1732 .hwcg_reg = 0xac01c, 1733 .hwcg_bit = 1, 1734 .clkr = { 1735 .enable_reg = 0x52000, 1736 .enable_mask = BIT(26), 1737 .hw.init = &(const struct clk_init_data) { 1738 .name = "gcc_pcie_1_slv_axi_clk", 1739 .ops = &clk_branch2_ops, 1740 }, 1741 }, 1742 }; 1743 1744 static struct clk_branch gcc_pcie_1_slv_q2a_axi_clk = { 1745 .halt_reg = 0xac018, 1746 .halt_check = BRANCH_HALT_VOTED, 1747 .clkr = { 1748 .enable_reg = 0x52000, 1749 .enable_mask = BIT(25), 1750 .hw.init = &(const struct clk_init_data) { 1751 .name = "gcc_pcie_1_slv_q2a_axi_clk", 1752 .ops = &clk_branch2_ops, 1753 }, 1754 }, 1755 }; 1756 1757 static struct clk_branch gcc_pdm2_clk = { 1758 .halt_reg = 0x3300c, 1759 .halt_check = BRANCH_HALT, 1760 .clkr = { 1761 .enable_reg = 0x3300c, 1762 .enable_mask = BIT(0), 1763 .hw.init = &(const struct clk_init_data) { 1764 .name = "gcc_pdm2_clk", 1765 .parent_hws = (const struct clk_hw*[]) { 1766 &gcc_pdm2_clk_src.clkr.hw, 1767 }, 1768 .num_parents = 1, 1769 .flags = CLK_SET_RATE_PARENT, 1770 .ops = &clk_branch2_ops, 1771 }, 1772 }, 1773 }; 1774 1775 static struct clk_branch gcc_pdm_ahb_clk = { 1776 .halt_reg = 0x33004, 1777 .halt_check = BRANCH_HALT_VOTED, 1778 .hwcg_reg = 0x33004, 1779 .hwcg_bit = 1, 1780 .clkr = { 1781 .enable_reg = 0x33004, 1782 .enable_mask = BIT(0), 1783 .hw.init = &(const struct clk_init_data) { 1784 .name = "gcc_pdm_ahb_clk", 1785 .ops = &clk_branch2_ops, 1786 }, 1787 }, 1788 }; 1789 1790 static struct clk_branch gcc_pdm_xo4_clk = { 1791 .halt_reg = 0x33008, 1792 .halt_check = BRANCH_HALT, 1793 .clkr = { 1794 .enable_reg = 0x33008, 1795 .enable_mask = BIT(0), 1796 .hw.init = &(const struct clk_init_data) { 1797 .name = "gcc_pdm_xo4_clk", 1798 .ops = &clk_branch2_ops, 1799 }, 1800 }, 1801 }; 1802 1803 static struct clk_branch gcc_qmip_camera_cmd_ahb_clk = { 1804 .halt_reg = 0x26010, 1805 .halt_check = BRANCH_HALT_VOTED, 1806 .hwcg_reg = 0x26010, 1807 .hwcg_bit = 1, 1808 .clkr = { 1809 .enable_reg = 0x26010, 1810 .enable_mask = BIT(0), 1811 .hw.init = &(const struct clk_init_data) { 1812 .name = "gcc_qmip_camera_cmd_ahb_clk", 1813 .ops = &clk_branch2_ops, 1814 }, 1815 }, 1816 }; 1817 1818 static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = { 1819 .halt_reg = 0x26008, 1820 .halt_check = BRANCH_HALT_VOTED, 1821 .hwcg_reg = 0x26008, 1822 .hwcg_bit = 1, 1823 .clkr = { 1824 .enable_reg = 0x26008, 1825 .enable_mask = BIT(0), 1826 .hw.init = &(const struct clk_init_data) { 1827 .name = "gcc_qmip_camera_nrt_ahb_clk", 1828 .ops = &clk_branch2_ops, 1829 }, 1830 }, 1831 }; 1832 1833 static struct clk_branch gcc_qmip_camera_rt_ahb_clk = { 1834 .halt_reg = 0x2600c, 1835 .halt_check = BRANCH_HALT_VOTED, 1836 .hwcg_reg = 0x2600c, 1837 .hwcg_bit = 1, 1838 .clkr = { 1839 .enable_reg = 0x2600c, 1840 .enable_mask = BIT(0), 1841 .hw.init = &(const struct clk_init_data) { 1842 .name = "gcc_qmip_camera_rt_ahb_clk", 1843 .ops = &clk_branch2_ops, 1844 }, 1845 }, 1846 }; 1847 1848 static struct clk_branch gcc_qmip_gpu_ahb_clk = { 1849 .halt_reg = 0x71008, 1850 .halt_check = BRANCH_HALT_VOTED, 1851 .hwcg_reg = 0x71008, 1852 .hwcg_bit = 1, 1853 .clkr = { 1854 .enable_reg = 0x71008, 1855 .enable_mask = BIT(0), 1856 .hw.init = &(const struct clk_init_data) { 1857 .name = "gcc_qmip_gpu_ahb_clk", 1858 .ops = &clk_branch2_ops, 1859 }, 1860 }, 1861 }; 1862 1863 static struct clk_branch gcc_qmip_pcie_ahb_clk = { 1864 .halt_reg = 0x6b018, 1865 .halt_check = BRANCH_HALT_VOTED, 1866 .hwcg_reg = 0x6b018, 1867 .hwcg_bit = 1, 1868 .clkr = { 1869 .enable_reg = 0x52000, 1870 .enable_mask = BIT(11), 1871 .hw.init = &(const struct clk_init_data) { 1872 .name = "gcc_qmip_pcie_ahb_clk", 1873 .ops = &clk_branch2_ops, 1874 }, 1875 }, 1876 }; 1877 1878 static struct clk_branch gcc_qmip_video_v_cpu_ahb_clk = { 1879 .halt_reg = 0x32010, 1880 .halt_check = BRANCH_HALT_VOTED, 1881 .hwcg_reg = 0x32010, 1882 .hwcg_bit = 1, 1883 .clkr = { 1884 .enable_reg = 0x32010, 1885 .enable_mask = BIT(0), 1886 .hw.init = &(const struct clk_init_data) { 1887 .name = "gcc_qmip_video_v_cpu_ahb_clk", 1888 .ops = &clk_branch2_ops, 1889 }, 1890 }, 1891 }; 1892 1893 static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = { 1894 .halt_reg = 0x3200c, 1895 .halt_check = BRANCH_HALT_VOTED, 1896 .hwcg_reg = 0x3200c, 1897 .hwcg_bit = 1, 1898 .clkr = { 1899 .enable_reg = 0x3200c, 1900 .enable_mask = BIT(0), 1901 .hw.init = &(const struct clk_init_data) { 1902 .name = "gcc_qmip_video_vcodec_ahb_clk", 1903 .ops = &clk_branch2_ops, 1904 }, 1905 }, 1906 }; 1907 1908 static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = { 1909 .halt_reg = 0x2301c, 1910 .halt_check = BRANCH_HALT_VOTED, 1911 .clkr = { 1912 .enable_reg = 0x52008, 1913 .enable_mask = BIT(18), 1914 .hw.init = &(const struct clk_init_data) { 1915 .name = "gcc_qupv3_wrap1_core_2x_clk", 1916 .ops = &clk_branch2_ops, 1917 }, 1918 }, 1919 }; 1920 1921 static struct clk_branch gcc_qupv3_wrap1_core_clk = { 1922 .halt_reg = 0x23008, 1923 .halt_check = BRANCH_HALT_VOTED, 1924 .clkr = { 1925 .enable_reg = 0x52008, 1926 .enable_mask = BIT(19), 1927 .hw.init = &(const struct clk_init_data) { 1928 .name = "gcc_qupv3_wrap1_core_clk", 1929 .ops = &clk_branch2_ops, 1930 }, 1931 }, 1932 }; 1933 1934 static struct clk_branch gcc_qupv3_wrap1_qspi_ref_clk = { 1935 .halt_reg = 0x188bc, 1936 .halt_check = BRANCH_HALT_VOTED, 1937 .clkr = { 1938 .enable_reg = 0x52010, 1939 .enable_mask = BIT(29), 1940 .hw.init = &(const struct clk_init_data) { 1941 .name = "gcc_qupv3_wrap1_qspi_ref_clk", 1942 .parent_hws = (const struct clk_hw*[]) { 1943 &gcc_qupv3_wrap1_qspi_ref_clk_src.clkr.hw, 1944 }, 1945 .num_parents = 1, 1946 .flags = CLK_SET_RATE_PARENT, 1947 .ops = &clk_branch2_ops, 1948 }, 1949 }, 1950 }; 1951 1952 static struct clk_branch gcc_qupv3_wrap1_s0_clk = { 1953 .halt_reg = 0x18004, 1954 .halt_check = BRANCH_HALT_VOTED, 1955 .clkr = { 1956 .enable_reg = 0x52008, 1957 .enable_mask = BIT(22), 1958 .hw.init = &(const struct clk_init_data) { 1959 .name = "gcc_qupv3_wrap1_s0_clk", 1960 .parent_hws = (const struct clk_hw*[]) { 1961 &gcc_qupv3_wrap1_s0_clk_src.clkr.hw, 1962 }, 1963 .num_parents = 1, 1964 .flags = CLK_SET_RATE_PARENT, 1965 .ops = &clk_branch2_ops, 1966 }, 1967 }, 1968 }; 1969 1970 static struct clk_branch gcc_qupv3_wrap1_s1_clk = { 1971 .halt_reg = 0x18140, 1972 .halt_check = BRANCH_HALT_VOTED, 1973 .clkr = { 1974 .enable_reg = 0x52008, 1975 .enable_mask = BIT(23), 1976 .hw.init = &(const struct clk_init_data) { 1977 .name = "gcc_qupv3_wrap1_s1_clk", 1978 .parent_hws = (const struct clk_hw*[]) { 1979 &gcc_qupv3_wrap1_s1_clk_src.clkr.hw, 1980 }, 1981 .num_parents = 1, 1982 .flags = CLK_SET_RATE_PARENT, 1983 .ops = &clk_branch2_ops, 1984 }, 1985 }, 1986 }; 1987 1988 static struct clk_branch gcc_qupv3_wrap1_s2_clk = { 1989 .halt_reg = 0x1827c, 1990 .halt_check = BRANCH_HALT_VOTED, 1991 .clkr = { 1992 .enable_reg = 0x52008, 1993 .enable_mask = BIT(24), 1994 .hw.init = &(const struct clk_init_data) { 1995 .name = "gcc_qupv3_wrap1_s2_clk", 1996 .parent_hws = (const struct clk_hw*[]) { 1997 &gcc_qupv3_wrap1_s2_clk_src.clkr.hw, 1998 }, 1999 .num_parents = 1, 2000 .flags = CLK_SET_RATE_PARENT, 2001 .ops = &clk_branch2_ops, 2002 }, 2003 }, 2004 }; 2005 2006 static struct clk_branch gcc_qupv3_wrap1_s3_clk = { 2007 .halt_reg = 0x18290, 2008 .halt_check = BRANCH_HALT_VOTED, 2009 .clkr = { 2010 .enable_reg = 0x52008, 2011 .enable_mask = BIT(25), 2012 .hw.init = &(const struct clk_init_data) { 2013 .name = "gcc_qupv3_wrap1_s3_clk", 2014 .parent_hws = (const struct clk_hw*[]) { 2015 &gcc_qupv3_wrap1_s3_clk_src.clkr.hw, 2016 }, 2017 .num_parents = 1, 2018 .flags = CLK_SET_RATE_PARENT, 2019 .ops = &clk_branch2_ops, 2020 }, 2021 }, 2022 }; 2023 2024 static struct clk_branch gcc_qupv3_wrap1_s4_clk = { 2025 .halt_reg = 0x183cc, 2026 .halt_check = BRANCH_HALT_VOTED, 2027 .clkr = { 2028 .enable_reg = 0x52008, 2029 .enable_mask = BIT(26), 2030 .hw.init = &(const struct clk_init_data) { 2031 .name = "gcc_qupv3_wrap1_s4_clk", 2032 .parent_hws = (const struct clk_hw*[]) { 2033 &gcc_qupv3_wrap1_s4_clk_src.clkr.hw, 2034 }, 2035 .num_parents = 1, 2036 .flags = CLK_SET_RATE_PARENT, 2037 .ops = &clk_branch2_ops, 2038 }, 2039 }, 2040 }; 2041 2042 static struct clk_branch gcc_qupv3_wrap1_s5_clk = { 2043 .halt_reg = 0x18508, 2044 .halt_check = BRANCH_HALT_VOTED, 2045 .clkr = { 2046 .enable_reg = 0x52008, 2047 .enable_mask = BIT(27), 2048 .hw.init = &(const struct clk_init_data) { 2049 .name = "gcc_qupv3_wrap1_s5_clk", 2050 .parent_hws = (const struct clk_hw*[]) { 2051 &gcc_qupv3_wrap1_s5_clk_src.clkr.hw, 2052 }, 2053 .num_parents = 1, 2054 .flags = CLK_SET_RATE_PARENT, 2055 .ops = &clk_branch2_ops, 2056 }, 2057 }, 2058 }; 2059 2060 static struct clk_branch gcc_qupv3_wrap1_s6_clk = { 2061 .halt_reg = 0x18644, 2062 .halt_check = BRANCH_HALT_VOTED, 2063 .clkr = { 2064 .enable_reg = 0x52008, 2065 .enable_mask = BIT(28), 2066 .hw.init = &(const struct clk_init_data) { 2067 .name = "gcc_qupv3_wrap1_s6_clk", 2068 .parent_hws = (const struct clk_hw*[]) { 2069 &gcc_qupv3_wrap1_s6_clk_src.clkr.hw, 2070 }, 2071 .num_parents = 1, 2072 .flags = CLK_SET_RATE_PARENT, 2073 .ops = &clk_branch2_ops, 2074 }, 2075 }, 2076 }; 2077 2078 static struct clk_branch gcc_qupv3_wrap1_s7_clk = { 2079 .halt_reg = 0x18780, 2080 .halt_check = BRANCH_HALT_VOTED, 2081 .clkr = { 2082 .enable_reg = 0x52010, 2083 .enable_mask = BIT(16), 2084 .hw.init = &(const struct clk_init_data) { 2085 .name = "gcc_qupv3_wrap1_s7_clk", 2086 .parent_hws = (const struct clk_hw*[]) { 2087 &gcc_qupv3_wrap1_s7_clk_src.clkr.hw, 2088 }, 2089 .num_parents = 1, 2090 .flags = CLK_SET_RATE_PARENT, 2091 .ops = &clk_branch2_ops, 2092 }, 2093 }, 2094 }; 2095 2096 static struct clk_branch gcc_qupv3_wrap2_core_2x_clk = { 2097 .halt_reg = 0x23174, 2098 .halt_check = BRANCH_HALT_VOTED, 2099 .clkr = { 2100 .enable_reg = 0x52010, 2101 .enable_mask = BIT(3), 2102 .hw.init = &(const struct clk_init_data) { 2103 .name = "gcc_qupv3_wrap2_core_2x_clk", 2104 .ops = &clk_branch2_ops, 2105 }, 2106 }, 2107 }; 2108 2109 static struct clk_branch gcc_qupv3_wrap2_core_clk = { 2110 .halt_reg = 0x23160, 2111 .halt_check = BRANCH_HALT_VOTED, 2112 .clkr = { 2113 .enable_reg = 0x52010, 2114 .enable_mask = BIT(0), 2115 .hw.init = &(const struct clk_init_data) { 2116 .name = "gcc_qupv3_wrap2_core_clk", 2117 .ops = &clk_branch2_ops, 2118 }, 2119 }, 2120 }; 2121 2122 static struct clk_branch gcc_qupv3_wrap2_s0_clk = { 2123 .halt_reg = 0x1e004, 2124 .halt_check = BRANCH_HALT_VOTED, 2125 .clkr = { 2126 .enable_reg = 0x52010, 2127 .enable_mask = BIT(4), 2128 .hw.init = &(const struct clk_init_data) { 2129 .name = "gcc_qupv3_wrap2_s0_clk", 2130 .parent_hws = (const struct clk_hw*[]) { 2131 &gcc_qupv3_wrap2_s0_clk_src.clkr.hw, 2132 }, 2133 .num_parents = 1, 2134 .flags = CLK_SET_RATE_PARENT, 2135 .ops = &clk_branch2_ops, 2136 }, 2137 }, 2138 }; 2139 2140 static struct clk_branch gcc_qupv3_wrap2_s1_clk = { 2141 .halt_reg = 0x1e140, 2142 .halt_check = BRANCH_HALT_VOTED, 2143 .clkr = { 2144 .enable_reg = 0x52010, 2145 .enable_mask = BIT(5), 2146 .hw.init = &(const struct clk_init_data) { 2147 .name = "gcc_qupv3_wrap2_s1_clk", 2148 .parent_hws = (const struct clk_hw*[]) { 2149 &gcc_qupv3_wrap2_s1_clk_src.clkr.hw, 2150 }, 2151 .num_parents = 1, 2152 .flags = CLK_SET_RATE_PARENT, 2153 .ops = &clk_branch2_ops, 2154 }, 2155 }, 2156 }; 2157 2158 static struct clk_branch gcc_qupv3_wrap2_s2_clk = { 2159 .halt_reg = 0x1e27c, 2160 .halt_check = BRANCH_HALT_VOTED, 2161 .clkr = { 2162 .enable_reg = 0x52010, 2163 .enable_mask = BIT(6), 2164 .hw.init = &(const struct clk_init_data) { 2165 .name = "gcc_qupv3_wrap2_s2_clk", 2166 .parent_hws = (const struct clk_hw*[]) { 2167 &gcc_qupv3_wrap2_s2_clk_src.clkr.hw, 2168 }, 2169 .num_parents = 1, 2170 .flags = CLK_SET_RATE_PARENT, 2171 .ops = &clk_branch2_ops, 2172 }, 2173 }, 2174 }; 2175 2176 static struct clk_branch gcc_qupv3_wrap2_s3_clk = { 2177 .halt_reg = 0x1e3b8, 2178 .halt_check = BRANCH_HALT_VOTED, 2179 .clkr = { 2180 .enable_reg = 0x52010, 2181 .enable_mask = BIT(7), 2182 .hw.init = &(const struct clk_init_data) { 2183 .name = "gcc_qupv3_wrap2_s3_clk", 2184 .parent_hws = (const struct clk_hw*[]) { 2185 &gcc_qupv3_wrap2_s3_clk_src.clkr.hw, 2186 }, 2187 .num_parents = 1, 2188 .flags = CLK_SET_RATE_PARENT, 2189 .ops = &clk_branch2_ops, 2190 }, 2191 }, 2192 }; 2193 2194 static struct clk_branch gcc_qupv3_wrap2_s4_clk = { 2195 .halt_reg = 0x1e4f4, 2196 .halt_check = BRANCH_HALT_VOTED, 2197 .clkr = { 2198 .enable_reg = 0x52010, 2199 .enable_mask = BIT(8), 2200 .hw.init = &(const struct clk_init_data) { 2201 .name = "gcc_qupv3_wrap2_s4_clk", 2202 .parent_hws = (const struct clk_hw*[]) { 2203 &gcc_qupv3_wrap2_s4_clk_src.clkr.hw, 2204 }, 2205 .num_parents = 1, 2206 .flags = CLK_SET_RATE_PARENT, 2207 .ops = &clk_branch2_ops, 2208 }, 2209 }, 2210 }; 2211 2212 static struct clk_branch gcc_qupv3_wrap2_s5_clk = { 2213 .halt_reg = 0x1e630, 2214 .halt_check = BRANCH_HALT_VOTED, 2215 .clkr = { 2216 .enable_reg = 0x52010, 2217 .enable_mask = BIT(9), 2218 .hw.init = &(const struct clk_init_data) { 2219 .name = "gcc_qupv3_wrap2_s5_clk", 2220 .parent_hws = (const struct clk_hw*[]) { 2221 &gcc_qupv3_wrap2_s5_clk_src.clkr.hw, 2222 }, 2223 .num_parents = 1, 2224 .flags = CLK_SET_RATE_PARENT, 2225 .ops = &clk_branch2_ops, 2226 }, 2227 }, 2228 }; 2229 2230 static struct clk_branch gcc_qupv3_wrap2_s6_clk = { 2231 .halt_reg = 0x1e76c, 2232 .halt_check = BRANCH_HALT_VOTED, 2233 .clkr = { 2234 .enable_reg = 0x52010, 2235 .enable_mask = BIT(10), 2236 .hw.init = &(const struct clk_init_data) { 2237 .name = "gcc_qupv3_wrap2_s6_clk", 2238 .parent_hws = (const struct clk_hw*[]) { 2239 &gcc_qupv3_wrap2_s6_clk_src.clkr.hw, 2240 }, 2241 .num_parents = 1, 2242 .flags = CLK_SET_RATE_PARENT, 2243 .ops = &clk_branch2_ops, 2244 }, 2245 }, 2246 }; 2247 2248 static struct clk_branch gcc_qupv3_wrap2_s7_clk = { 2249 .halt_reg = 0x1e8a8, 2250 .halt_check = BRANCH_HALT_VOTED, 2251 .clkr = { 2252 .enable_reg = 0x52010, 2253 .enable_mask = BIT(17), 2254 .hw.init = &(const struct clk_init_data) { 2255 .name = "gcc_qupv3_wrap2_s7_clk", 2256 .parent_hws = (const struct clk_hw*[]) { 2257 &gcc_qupv3_wrap2_s7_clk_src.clkr.hw, 2258 }, 2259 .num_parents = 1, 2260 .flags = CLK_SET_RATE_PARENT, 2261 .ops = &clk_branch2_ops, 2262 }, 2263 }, 2264 }; 2265 2266 static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = { 2267 .halt_reg = 0x23000, 2268 .halt_check = BRANCH_HALT_VOTED, 2269 .clkr = { 2270 .enable_reg = 0x52008, 2271 .enable_mask = BIT(20), 2272 .hw.init = &(const struct clk_init_data) { 2273 .name = "gcc_qupv3_wrap_1_m_ahb_clk", 2274 .ops = &clk_branch2_ops, 2275 }, 2276 }, 2277 }; 2278 2279 static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = { 2280 .halt_reg = 0x23004, 2281 .halt_check = BRANCH_HALT_VOTED, 2282 .hwcg_reg = 0x23004, 2283 .hwcg_bit = 1, 2284 .clkr = { 2285 .enable_reg = 0x52008, 2286 .enable_mask = BIT(21), 2287 .hw.init = &(const struct clk_init_data) { 2288 .name = "gcc_qupv3_wrap_1_s_ahb_clk", 2289 .ops = &clk_branch2_ops, 2290 }, 2291 }, 2292 }; 2293 2294 static struct clk_branch gcc_qupv3_wrap_2_m_ahb_clk = { 2295 .halt_reg = 0x23158, 2296 .halt_check = BRANCH_HALT_VOTED, 2297 .hwcg_reg = 0x23158, 2298 .hwcg_bit = 1, 2299 .clkr = { 2300 .enable_reg = 0x52010, 2301 .enable_mask = BIT(2), 2302 .hw.init = &(const struct clk_init_data) { 2303 .name = "gcc_qupv3_wrap_2_m_ahb_clk", 2304 .ops = &clk_branch2_ops, 2305 }, 2306 }, 2307 }; 2308 2309 static struct clk_branch gcc_qupv3_wrap_2_s_ahb_clk = { 2310 .halt_reg = 0x2315c, 2311 .halt_check = BRANCH_HALT_VOTED, 2312 .hwcg_reg = 0x2315c, 2313 .hwcg_bit = 1, 2314 .clkr = { 2315 .enable_reg = 0x52010, 2316 .enable_mask = BIT(1), 2317 .hw.init = &(const struct clk_init_data) { 2318 .name = "gcc_qupv3_wrap_2_s_ahb_clk", 2319 .ops = &clk_branch2_ops, 2320 }, 2321 }, 2322 }; 2323 2324 static struct clk_branch gcc_sdcc1_ahb_clk = { 2325 .halt_reg = 0xa9004, 2326 .halt_check = BRANCH_HALT, 2327 .clkr = { 2328 .enable_reg = 0xa9004, 2329 .enable_mask = BIT(0), 2330 .hw.init = &(const struct clk_init_data) { 2331 .name = "gcc_sdcc1_ahb_clk", 2332 .ops = &clk_branch2_ops, 2333 }, 2334 }, 2335 }; 2336 2337 static struct clk_branch gcc_sdcc1_apps_clk = { 2338 .halt_reg = 0xa9008, 2339 .halt_check = BRANCH_HALT, 2340 .clkr = { 2341 .enable_reg = 0xa9008, 2342 .enable_mask = BIT(0), 2343 .hw.init = &(const struct clk_init_data) { 2344 .name = "gcc_sdcc1_apps_clk", 2345 .parent_hws = (const struct clk_hw*[]) { 2346 &gcc_sdcc1_apps_clk_src.clkr.hw, 2347 }, 2348 .num_parents = 1, 2349 .flags = CLK_SET_RATE_PARENT, 2350 .ops = &clk_branch2_ops, 2351 }, 2352 }, 2353 }; 2354 2355 static struct clk_branch gcc_sdcc1_ice_core_clk = { 2356 .halt_reg = 0xa9030, 2357 .halt_check = BRANCH_HALT_VOTED, 2358 .hwcg_reg = 0xa9030, 2359 .hwcg_bit = 1, 2360 .clkr = { 2361 .enable_reg = 0xa9030, 2362 .enable_mask = BIT(0), 2363 .hw.init = &(const struct clk_init_data) { 2364 .name = "gcc_sdcc1_ice_core_clk", 2365 .parent_hws = (const struct clk_hw*[]) { 2366 &gcc_sdcc1_ice_core_clk_src.clkr.hw, 2367 }, 2368 .num_parents = 1, 2369 .flags = CLK_SET_RATE_PARENT, 2370 .ops = &clk_branch2_ops, 2371 }, 2372 }, 2373 }; 2374 2375 static struct clk_branch gcc_sdcc2_ahb_clk = { 2376 .halt_reg = 0x14014, 2377 .halt_check = BRANCH_HALT, 2378 .clkr = { 2379 .enable_reg = 0x14014, 2380 .enable_mask = BIT(0), 2381 .hw.init = &(const struct clk_init_data) { 2382 .name = "gcc_sdcc2_ahb_clk", 2383 .ops = &clk_branch2_ops, 2384 }, 2385 }, 2386 }; 2387 2388 static struct clk_branch gcc_sdcc2_apps_clk = { 2389 .halt_reg = 0x14004, 2390 .halt_check = BRANCH_HALT, 2391 .clkr = { 2392 .enable_reg = 0x14004, 2393 .enable_mask = BIT(0), 2394 .hw.init = &(const struct clk_init_data) { 2395 .name = "gcc_sdcc2_apps_clk", 2396 .parent_hws = (const struct clk_hw*[]) { 2397 &gcc_sdcc2_apps_clk_src.clkr.hw, 2398 }, 2399 .num_parents = 1, 2400 .flags = CLK_SET_RATE_PARENT, 2401 .ops = &clk_branch2_ops, 2402 }, 2403 }, 2404 }; 2405 2406 static struct clk_branch gcc_ufs_phy_ahb_clk = { 2407 .halt_reg = 0x77028, 2408 .halt_check = BRANCH_HALT_VOTED, 2409 .hwcg_reg = 0x77028, 2410 .hwcg_bit = 1, 2411 .clkr = { 2412 .enable_reg = 0x77028, 2413 .enable_mask = BIT(0), 2414 .hw.init = &(const struct clk_init_data) { 2415 .name = "gcc_ufs_phy_ahb_clk", 2416 .ops = &clk_branch2_ops, 2417 }, 2418 }, 2419 }; 2420 2421 static struct clk_branch gcc_ufs_phy_axi_clk = { 2422 .halt_reg = 0x77018, 2423 .halt_check = BRANCH_HALT_VOTED, 2424 .hwcg_reg = 0x77018, 2425 .hwcg_bit = 1, 2426 .clkr = { 2427 .enable_reg = 0x77018, 2428 .enable_mask = BIT(0), 2429 .hw.init = &(const struct clk_init_data) { 2430 .name = "gcc_ufs_phy_axi_clk", 2431 .parent_hws = (const struct clk_hw*[]) { 2432 &gcc_ufs_phy_axi_clk_src.clkr.hw, 2433 }, 2434 .num_parents = 1, 2435 .flags = CLK_SET_RATE_PARENT, 2436 .ops = &clk_branch2_ops, 2437 }, 2438 }, 2439 }; 2440 2441 static struct clk_branch gcc_ufs_phy_ice_core_clk = { 2442 .halt_reg = 0x7707c, 2443 .halt_check = BRANCH_HALT_VOTED, 2444 .hwcg_reg = 0x7707c, 2445 .hwcg_bit = 1, 2446 .clkr = { 2447 .enable_reg = 0x7707c, 2448 .enable_mask = BIT(0), 2449 .hw.init = &(const struct clk_init_data) { 2450 .name = "gcc_ufs_phy_ice_core_clk", 2451 .parent_hws = (const struct clk_hw*[]) { 2452 &gcc_ufs_phy_ice_core_clk_src.clkr.hw, 2453 }, 2454 .num_parents = 1, 2455 .flags = CLK_SET_RATE_PARENT, 2456 .ops = &clk_branch2_ops, 2457 }, 2458 }, 2459 }; 2460 2461 static struct clk_branch gcc_ufs_phy_phy_aux_clk = { 2462 .halt_reg = 0x770bc, 2463 .halt_check = BRANCH_HALT_VOTED, 2464 .hwcg_reg = 0x770bc, 2465 .hwcg_bit = 1, 2466 .clkr = { 2467 .enable_reg = 0x770bc, 2468 .enable_mask = BIT(0), 2469 .hw.init = &(const struct clk_init_data) { 2470 .name = "gcc_ufs_phy_phy_aux_clk", 2471 .parent_hws = (const struct clk_hw*[]) { 2472 &gcc_ufs_phy_phy_aux_clk_src.clkr.hw, 2473 }, 2474 .num_parents = 1, 2475 .flags = CLK_SET_RATE_PARENT, 2476 .ops = &clk_branch2_ops, 2477 }, 2478 }, 2479 }; 2480 2481 static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = { 2482 .halt_reg = 0x77030, 2483 .halt_check = BRANCH_HALT_DELAY, 2484 .clkr = { 2485 .enable_reg = 0x77030, 2486 .enable_mask = BIT(0), 2487 .hw.init = &(const struct clk_init_data) { 2488 .name = "gcc_ufs_phy_rx_symbol_0_clk", 2489 .parent_hws = (const struct clk_hw*[]) { 2490 &gcc_ufs_phy_rx_symbol_0_clk_src.clkr.hw, 2491 }, 2492 .num_parents = 1, 2493 .flags = CLK_SET_RATE_PARENT, 2494 .ops = &clk_branch2_ops, 2495 }, 2496 }, 2497 }; 2498 2499 static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = { 2500 .halt_reg = 0x770d8, 2501 .halt_check = BRANCH_HALT_DELAY, 2502 .clkr = { 2503 .enable_reg = 0x770d8, 2504 .enable_mask = BIT(0), 2505 .hw.init = &(const struct clk_init_data) { 2506 .name = "gcc_ufs_phy_rx_symbol_1_clk", 2507 .parent_hws = (const struct clk_hw*[]) { 2508 &gcc_ufs_phy_rx_symbol_1_clk_src.clkr.hw, 2509 }, 2510 .num_parents = 1, 2511 .flags = CLK_SET_RATE_PARENT, 2512 .ops = &clk_branch2_ops, 2513 }, 2514 }, 2515 }; 2516 2517 static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = { 2518 .halt_reg = 0x7702c, 2519 .halt_check = BRANCH_HALT_DELAY, 2520 .clkr = { 2521 .enable_reg = 0x7702c, 2522 .enable_mask = BIT(0), 2523 .hw.init = &(const struct clk_init_data) { 2524 .name = "gcc_ufs_phy_tx_symbol_0_clk", 2525 .parent_hws = (const struct clk_hw*[]) { 2526 &gcc_ufs_phy_tx_symbol_0_clk_src.clkr.hw, 2527 }, 2528 .num_parents = 1, 2529 .flags = CLK_SET_RATE_PARENT, 2530 .ops = &clk_branch2_ops, 2531 }, 2532 }, 2533 }; 2534 2535 static struct clk_branch gcc_ufs_phy_unipro_core_clk = { 2536 .halt_reg = 0x7706c, 2537 .halt_check = BRANCH_HALT_VOTED, 2538 .hwcg_reg = 0x7706c, 2539 .hwcg_bit = 1, 2540 .clkr = { 2541 .enable_reg = 0x7706c, 2542 .enable_mask = BIT(0), 2543 .hw.init = &(const struct clk_init_data) { 2544 .name = "gcc_ufs_phy_unipro_core_clk", 2545 .parent_hws = (const struct clk_hw*[]) { 2546 &gcc_ufs_phy_unipro_core_clk_src.clkr.hw, 2547 }, 2548 .num_parents = 1, 2549 .flags = CLK_SET_RATE_PARENT, 2550 .ops = &clk_branch2_ops, 2551 }, 2552 }, 2553 }; 2554 2555 static struct clk_branch gcc_usb30_prim_atb_clk = { 2556 .halt_reg = 0x3908c, 2557 .halt_check = BRANCH_HALT_VOTED, 2558 .clkr = { 2559 .enable_reg = 0x3908c, 2560 .enable_mask = BIT(0), 2561 .hw.init = &(const struct clk_init_data) { 2562 .name = "gcc_usb30_prim_atb_clk", 2563 .parent_hws = (const struct clk_hw*[]) { 2564 &gcc_usb30_prim_master_clk_src.clkr.hw, 2565 }, 2566 .num_parents = 1, 2567 .flags = CLK_SET_RATE_PARENT, 2568 .ops = &clk_branch2_ops, 2569 }, 2570 }, 2571 }; 2572 2573 static struct clk_branch gcc_usb30_prim_master_clk = { 2574 .halt_reg = 0x39018, 2575 .halt_check = BRANCH_HALT, 2576 .clkr = { 2577 .enable_reg = 0x39018, 2578 .enable_mask = BIT(0), 2579 .hw.init = &(const struct clk_init_data) { 2580 .name = "gcc_usb30_prim_master_clk", 2581 .parent_hws = (const struct clk_hw*[]) { 2582 &gcc_usb30_prim_master_clk_src.clkr.hw, 2583 }, 2584 .num_parents = 1, 2585 .flags = CLK_SET_RATE_PARENT, 2586 .ops = &clk_branch2_ops, 2587 }, 2588 }, 2589 }; 2590 2591 static struct clk_branch gcc_usb30_prim_mock_utmi_clk = { 2592 .halt_reg = 0x3902c, 2593 .halt_check = BRANCH_HALT, 2594 .clkr = { 2595 .enable_reg = 0x3902c, 2596 .enable_mask = BIT(0), 2597 .hw.init = &(const struct clk_init_data) { 2598 .name = "gcc_usb30_prim_mock_utmi_clk", 2599 .parent_hws = (const struct clk_hw*[]) { 2600 &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr.hw, 2601 }, 2602 .num_parents = 1, 2603 .flags = CLK_SET_RATE_PARENT, 2604 .ops = &clk_branch2_ops, 2605 }, 2606 }, 2607 }; 2608 2609 static struct clk_branch gcc_usb30_prim_sleep_clk = { 2610 .halt_reg = 0x39028, 2611 .halt_check = BRANCH_HALT, 2612 .clkr = { 2613 .enable_reg = 0x39028, 2614 .enable_mask = BIT(0), 2615 .hw.init = &(const struct clk_init_data) { 2616 .name = "gcc_usb30_prim_sleep_clk", 2617 .ops = &clk_branch2_ops, 2618 }, 2619 }, 2620 }; 2621 2622 static struct clk_branch gcc_usb3_prim_phy_aux_clk = { 2623 .halt_reg = 0x39064, 2624 .halt_check = BRANCH_HALT, 2625 .clkr = { 2626 .enable_reg = 0x39064, 2627 .enable_mask = BIT(0), 2628 .hw.init = &(const struct clk_init_data) { 2629 .name = "gcc_usb3_prim_phy_aux_clk", 2630 .parent_hws = (const struct clk_hw*[]) { 2631 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, 2632 }, 2633 .num_parents = 1, 2634 .flags = CLK_SET_RATE_PARENT, 2635 .ops = &clk_branch2_ops, 2636 }, 2637 }, 2638 }; 2639 2640 static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = { 2641 .halt_reg = 0x39068, 2642 .halt_check = BRANCH_HALT, 2643 .clkr = { 2644 .enable_reg = 0x39068, 2645 .enable_mask = BIT(0), 2646 .hw.init = &(const struct clk_init_data) { 2647 .name = "gcc_usb3_prim_phy_com_aux_clk", 2648 .parent_hws = (const struct clk_hw*[]) { 2649 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, 2650 }, 2651 .num_parents = 1, 2652 .flags = CLK_SET_RATE_PARENT, 2653 .ops = &clk_branch2_ops, 2654 }, 2655 }, 2656 }; 2657 2658 static struct clk_branch gcc_usb3_prim_phy_pipe_clk = { 2659 .halt_reg = 0x3906c, 2660 .halt_check = BRANCH_HALT_DELAY, 2661 .hwcg_reg = 0x3906c, 2662 .hwcg_bit = 1, 2663 .clkr = { 2664 .enable_reg = 0x3906c, 2665 .enable_mask = BIT(0), 2666 .hw.init = &(const struct clk_init_data) { 2667 .name = "gcc_usb3_prim_phy_pipe_clk", 2668 .parent_hws = (const struct clk_hw*[]) { 2669 &gcc_usb3_prim_phy_pipe_clk_src.clkr.hw, 2670 }, 2671 .num_parents = 1, 2672 .flags = CLK_SET_RATE_PARENT, 2673 .ops = &clk_branch2_ops, 2674 }, 2675 }, 2676 }; 2677 2678 static struct clk_branch gcc_video_axi0_clk = { 2679 .halt_reg = 0x32018, 2680 .halt_check = BRANCH_HALT_SKIP, 2681 .hwcg_reg = 0x32018, 2682 .hwcg_bit = 1, 2683 .clkr = { 2684 .enable_reg = 0x32018, 2685 .enable_mask = BIT(0), 2686 .hw.init = &(const struct clk_init_data) { 2687 .name = "gcc_video_axi0_clk", 2688 .ops = &clk_branch2_ops, 2689 }, 2690 }, 2691 }; 2692 2693 static struct clk_branch gcc_video_axi1_clk = { 2694 .halt_reg = 0x32028, 2695 .halt_check = BRANCH_HALT_SKIP, 2696 .hwcg_reg = 0x32028, 2697 .hwcg_bit = 1, 2698 .clkr = { 2699 .enable_reg = 0x32028, 2700 .enable_mask = BIT(0), 2701 .hw.init = &(const struct clk_init_data) { 2702 .name = "gcc_video_axi1_clk", 2703 .ops = &clk_branch2_ops, 2704 }, 2705 }, 2706 }; 2707 2708 static struct gdsc gcc_pcie_0_gdsc = { 2709 .gdscr = 0x6b004, 2710 .en_rest_wait_val = 0x2, 2711 .en_few_wait_val = 0x2, 2712 .clk_dis_wait_val = 0xf, 2713 .collapse_ctrl = 0x5214c, 2714 .collapse_mask = BIT(0), 2715 .pd = { 2716 .name = "gcc_pcie_0_gdsc", 2717 }, 2718 .pwrsts = PWRSTS_OFF_ON, 2719 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, 2720 }; 2721 2722 static struct gdsc gcc_pcie_0_phy_gdsc = { 2723 .gdscr = 0x6c000, 2724 .en_rest_wait_val = 0x2, 2725 .en_few_wait_val = 0x2, 2726 .clk_dis_wait_val = 0x2, 2727 .collapse_ctrl = 0x5214c, 2728 .collapse_mask = BIT(2), 2729 .pd = { 2730 .name = "gcc_pcie_0_phy_gdsc", 2731 }, 2732 .pwrsts = PWRSTS_OFF_ON, 2733 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, 2734 }; 2735 2736 static struct gdsc gcc_pcie_1_gdsc = { 2737 .gdscr = 0xac004, 2738 .en_rest_wait_val = 0x2, 2739 .en_few_wait_val = 0x2, 2740 .clk_dis_wait_val = 0xf, 2741 .collapse_ctrl = 0x5214c, 2742 .collapse_mask = BIT(3), 2743 .pd = { 2744 .name = "gcc_pcie_1_gdsc", 2745 }, 2746 .pwrsts = PWRSTS_OFF_ON, 2747 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, 2748 }; 2749 2750 static struct gdsc gcc_pcie_1_phy_gdsc = { 2751 .gdscr = 0xad000, 2752 .en_rest_wait_val = 0x2, 2753 .en_few_wait_val = 0x2, 2754 .clk_dis_wait_val = 0x2, 2755 .collapse_ctrl = 0x5214c, 2756 .collapse_mask = BIT(4), 2757 .pd = { 2758 .name = "gcc_pcie_1_phy_gdsc", 2759 }, 2760 .pwrsts = PWRSTS_OFF_ON, 2761 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, 2762 }; 2763 2764 static struct gdsc gcc_ufs_mem_phy_gdsc = { 2765 .gdscr = 0x9e000, 2766 .en_rest_wait_val = 0x2, 2767 .en_few_wait_val = 0x2, 2768 .clk_dis_wait_val = 0x2, 2769 .pd = { 2770 .name = "gcc_ufs_mem_phy_gdsc", 2771 }, 2772 .pwrsts = PWRSTS_OFF_ON, 2773 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 2774 }; 2775 2776 static struct gdsc gcc_ufs_phy_gdsc = { 2777 .gdscr = 0x77004, 2778 .en_rest_wait_val = 0x2, 2779 .en_few_wait_val = 0x2, 2780 .clk_dis_wait_val = 0xf, 2781 .pd = { 2782 .name = "gcc_ufs_phy_gdsc", 2783 }, 2784 .pwrsts = PWRSTS_OFF_ON, 2785 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 2786 }; 2787 2788 static struct gdsc gcc_usb30_prim_gdsc = { 2789 .gdscr = 0x39004, 2790 .en_rest_wait_val = 0x2, 2791 .en_few_wait_val = 0x2, 2792 .clk_dis_wait_val = 0xf, 2793 .pd = { 2794 .name = "gcc_usb30_prim_gdsc", 2795 }, 2796 .pwrsts = PWRSTS_OFF_ON, 2797 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 2798 }; 2799 2800 static struct gdsc gcc_usb3_phy_gdsc = { 2801 .gdscr = 0x50018, 2802 .en_rest_wait_val = 0x2, 2803 .en_few_wait_val = 0x2, 2804 .clk_dis_wait_val = 0x2, 2805 .pd = { 2806 .name = "gcc_usb3_phy_gdsc", 2807 }, 2808 .pwrsts = PWRSTS_OFF_ON, 2809 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 2810 }; 2811 2812 static struct clk_regmap *gcc_eliza_clocks[] = { 2813 [GCC_AGGRE_NOC_PCIE_AXI_CLK] = &gcc_aggre_noc_pcie_axi_clk.clkr, 2814 [GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr, 2815 [GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr, 2816 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, 2817 [GCC_CAMERA_HF_AXI_CLK] = &gcc_camera_hf_axi_clk.clkr, 2818 [GCC_CAMERA_SF_AXI_CLK] = &gcc_camera_sf_axi_clk.clkr, 2819 [GCC_CFG_NOC_PCIE_ANOC_AHB_CLK] = &gcc_cfg_noc_pcie_anoc_ahb_clk.clkr, 2820 [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr, 2821 [GCC_CNOC_PCIE_SF_AXI_CLK] = &gcc_cnoc_pcie_sf_axi_clk.clkr, 2822 [GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr, 2823 [GCC_DDRSS_PCIE_SF_QTB_CLK] = &gcc_ddrss_pcie_sf_qtb_clk.clkr, 2824 [GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr, 2825 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, 2826 [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr, 2827 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, 2828 [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr, 2829 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, 2830 [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr, 2831 [GCC_GPLL0] = &gcc_gpll0.clkr, 2832 [GCC_GPLL0_OUT_EVEN] = &gcc_gpll0_out_even.clkr, 2833 [GCC_GPLL4] = &gcc_gpll4.clkr, 2834 [GCC_GPLL7] = &gcc_gpll7.clkr, 2835 [GCC_GPLL8] = &gcc_gpll8.clkr, 2836 [GCC_GPLL9] = &gcc_gpll9.clkr, 2837 [GCC_GPU_GEMNOC_GFX_CLK] = &gcc_gpu_gemnoc_gfx_clk.clkr, 2838 [GCC_GPU_GPLL0_CPH_CLK_SRC] = &gcc_gpu_gpll0_cph_clk_src.clkr, 2839 [GCC_GPU_GPLL0_DIV_CPH_CLK_SRC] = &gcc_gpu_gpll0_div_cph_clk_src.clkr, 2840 [GCC_GPU_SMMU_VOTE_CLK] = &gcc_gpu_smmu_vote_clk.clkr, 2841 [GCC_MMU_TCU_VOTE_CLK] = &gcc_mmu_tcu_vote_clk.clkr, 2842 [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr, 2843 [GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr, 2844 [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr, 2845 [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr, 2846 [GCC_PCIE_0_PHY_RCHNG_CLK] = &gcc_pcie_0_phy_rchng_clk.clkr, 2847 [GCC_PCIE_0_PHY_RCHNG_CLK_SRC] = &gcc_pcie_0_phy_rchng_clk_src.clkr, 2848 [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr, 2849 [GCC_PCIE_0_PIPE_CLK_SRC] = &gcc_pcie_0_pipe_clk_src.clkr, 2850 [GCC_PCIE_0_PIPE_DIV2_CLK] = &gcc_pcie_0_pipe_div2_clk.clkr, 2851 [GCC_PCIE_0_PIPE_DIV2_CLK_SRC] = &gcc_pcie_0_pipe_div2_clk_src.clkr, 2852 [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr, 2853 [GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr, 2854 [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr, 2855 [GCC_PCIE_1_AUX_CLK_SRC] = &gcc_pcie_1_aux_clk_src.clkr, 2856 [GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr, 2857 [GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr, 2858 [GCC_PCIE_1_PHY_RCHNG_CLK] = &gcc_pcie_1_phy_rchng_clk.clkr, 2859 [GCC_PCIE_1_PHY_RCHNG_CLK_SRC] = &gcc_pcie_1_phy_rchng_clk_src.clkr, 2860 [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr, 2861 [GCC_PCIE_1_PIPE_CLK_SRC] = &gcc_pcie_1_pipe_clk_src.clkr, 2862 [GCC_PCIE_1_PIPE_DIV2_CLK] = &gcc_pcie_1_pipe_div2_clk.clkr, 2863 [GCC_PCIE_1_PIPE_DIV2_CLK_SRC] = &gcc_pcie_1_pipe_div2_clk_src.clkr, 2864 [GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr, 2865 [GCC_PCIE_1_SLV_Q2A_AXI_CLK] = &gcc_pcie_1_slv_q2a_axi_clk.clkr, 2866 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, 2867 [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr, 2868 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, 2869 [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr, 2870 [GCC_QMIP_CAMERA_CMD_AHB_CLK] = &gcc_qmip_camera_cmd_ahb_clk.clkr, 2871 [GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr, 2872 [GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr, 2873 [GCC_QMIP_GPU_AHB_CLK] = &gcc_qmip_gpu_ahb_clk.clkr, 2874 [GCC_QMIP_PCIE_AHB_CLK] = &gcc_qmip_pcie_ahb_clk.clkr, 2875 [GCC_QMIP_VIDEO_V_CPU_AHB_CLK] = &gcc_qmip_video_v_cpu_ahb_clk.clkr, 2876 [GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr, 2877 [GCC_QUPV3_WRAP1_CORE_2X_CLK] = &gcc_qupv3_wrap1_core_2x_clk.clkr, 2878 [GCC_QUPV3_WRAP1_CORE_CLK] = &gcc_qupv3_wrap1_core_clk.clkr, 2879 [GCC_QUPV3_WRAP1_QSPI_REF_CLK] = &gcc_qupv3_wrap1_qspi_ref_clk.clkr, 2880 [GCC_QUPV3_WRAP1_QSPI_REF_CLK_SRC] = &gcc_qupv3_wrap1_qspi_ref_clk_src.clkr, 2881 [GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr, 2882 [GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr, 2883 [GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr, 2884 [GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr, 2885 [GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr, 2886 [GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr, 2887 [GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr, 2888 [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr, 2889 [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr, 2890 [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr, 2891 [GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr, 2892 [GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr, 2893 [GCC_QUPV3_WRAP1_S6_CLK] = &gcc_qupv3_wrap1_s6_clk.clkr, 2894 [GCC_QUPV3_WRAP1_S6_CLK_SRC] = &gcc_qupv3_wrap1_s6_clk_src.clkr, 2895 [GCC_QUPV3_WRAP1_S7_CLK] = &gcc_qupv3_wrap1_s7_clk.clkr, 2896 [GCC_QUPV3_WRAP1_S7_CLK_SRC] = &gcc_qupv3_wrap1_s7_clk_src.clkr, 2897 [GCC_QUPV3_WRAP2_CORE_2X_CLK] = &gcc_qupv3_wrap2_core_2x_clk.clkr, 2898 [GCC_QUPV3_WRAP2_CORE_CLK] = &gcc_qupv3_wrap2_core_clk.clkr, 2899 [GCC_QUPV3_WRAP2_S0_CLK] = &gcc_qupv3_wrap2_s0_clk.clkr, 2900 [GCC_QUPV3_WRAP2_S0_CLK_SRC] = &gcc_qupv3_wrap2_s0_clk_src.clkr, 2901 [GCC_QUPV3_WRAP2_S1_CLK] = &gcc_qupv3_wrap2_s1_clk.clkr, 2902 [GCC_QUPV3_WRAP2_S1_CLK_SRC] = &gcc_qupv3_wrap2_s1_clk_src.clkr, 2903 [GCC_QUPV3_WRAP2_S2_CLK] = &gcc_qupv3_wrap2_s2_clk.clkr, 2904 [GCC_QUPV3_WRAP2_S2_CLK_SRC] = &gcc_qupv3_wrap2_s2_clk_src.clkr, 2905 [GCC_QUPV3_WRAP2_S3_CLK] = &gcc_qupv3_wrap2_s3_clk.clkr, 2906 [GCC_QUPV3_WRAP2_S3_CLK_SRC] = &gcc_qupv3_wrap2_s3_clk_src.clkr, 2907 [GCC_QUPV3_WRAP2_S4_CLK] = &gcc_qupv3_wrap2_s4_clk.clkr, 2908 [GCC_QUPV3_WRAP2_S4_CLK_SRC] = &gcc_qupv3_wrap2_s4_clk_src.clkr, 2909 [GCC_QUPV3_WRAP2_S5_CLK] = &gcc_qupv3_wrap2_s5_clk.clkr, 2910 [GCC_QUPV3_WRAP2_S5_CLK_SRC] = &gcc_qupv3_wrap2_s5_clk_src.clkr, 2911 [GCC_QUPV3_WRAP2_S6_CLK] = &gcc_qupv3_wrap2_s6_clk.clkr, 2912 [GCC_QUPV3_WRAP2_S6_CLK_SRC] = &gcc_qupv3_wrap2_s6_clk_src.clkr, 2913 [GCC_QUPV3_WRAP2_S7_CLK] = &gcc_qupv3_wrap2_s7_clk.clkr, 2914 [GCC_QUPV3_WRAP2_S7_CLK_SRC] = &gcc_qupv3_wrap2_s7_clk_src.clkr, 2915 [GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr, 2916 [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr, 2917 [GCC_QUPV3_WRAP_2_M_AHB_CLK] = &gcc_qupv3_wrap_2_m_ahb_clk.clkr, 2918 [GCC_QUPV3_WRAP_2_S_AHB_CLK] = &gcc_qupv3_wrap_2_s_ahb_clk.clkr, 2919 [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr, 2920 [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr, 2921 [GCC_SDCC1_APPS_CLK_SRC] = &gcc_sdcc1_apps_clk_src.clkr, 2922 [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr, 2923 [GCC_SDCC1_ICE_CORE_CLK_SRC] = &gcc_sdcc1_ice_core_clk_src.clkr, 2924 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, 2925 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, 2926 [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr, 2927 [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr, 2928 [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr, 2929 [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr, 2930 [GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr, 2931 [GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr, 2932 [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr, 2933 [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr, 2934 [GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr, 2935 [GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC] = &gcc_ufs_phy_rx_symbol_0_clk_src.clkr, 2936 [GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &gcc_ufs_phy_rx_symbol_1_clk.clkr, 2937 [GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC] = &gcc_ufs_phy_rx_symbol_1_clk_src.clkr, 2938 [GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr, 2939 [GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC] = &gcc_ufs_phy_tx_symbol_0_clk_src.clkr, 2940 [GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr, 2941 [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] = &gcc_ufs_phy_unipro_core_clk_src.clkr, 2942 [GCC_USB30_PRIM_ATB_CLK] = &gcc_usb30_prim_atb_clk.clkr, 2943 [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr, 2944 [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr, 2945 [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr, 2946 [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = &gcc_usb30_prim_mock_utmi_clk_src.clkr, 2947 [GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr, 2948 [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr, 2949 [GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr, 2950 [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr, 2951 [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr, 2952 [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr, 2953 [GCC_USB3_PRIM_PHY_PIPE_CLK_SRC] = &gcc_usb3_prim_phy_pipe_clk_src.clkr, 2954 [GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr, 2955 [GCC_VIDEO_AXI1_CLK] = &gcc_video_axi1_clk.clkr, 2956 }; 2957 2958 static struct gdsc *gcc_eliza_gdscs[] = { 2959 [GCC_PCIE_0_GDSC] = &gcc_pcie_0_gdsc, 2960 [GCC_PCIE_0_PHY_GDSC] = &gcc_pcie_0_phy_gdsc, 2961 [GCC_PCIE_1_GDSC] = &gcc_pcie_1_gdsc, 2962 [GCC_PCIE_1_PHY_GDSC] = &gcc_pcie_1_phy_gdsc, 2963 [GCC_UFS_MEM_PHY_GDSC] = &gcc_ufs_mem_phy_gdsc, 2964 [GCC_UFS_PHY_GDSC] = &gcc_ufs_phy_gdsc, 2965 [GCC_USB30_PRIM_GDSC] = &gcc_usb30_prim_gdsc, 2966 [GCC_USB3_PHY_GDSC] = &gcc_usb3_phy_gdsc, 2967 }; 2968 2969 static const struct qcom_reset_map gcc_eliza_resets[] = { 2970 [GCC_CAMERA_BCR] = { 0x26000 }, 2971 [GCC_DISPLAY_BCR] = { 0x27000 }, 2972 [GCC_GPU_BCR] = { 0x71000 }, 2973 [GCC_PCIE_0_BCR] = { 0x6b000 }, 2974 [GCC_PCIE_0_LINK_DOWN_BCR] = { 0x6c014 }, 2975 [GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0x6c020 }, 2976 [GCC_PCIE_0_PHY_BCR] = { 0x6c01c }, 2977 [GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR] = { 0x6c028 }, 2978 [GCC_PCIE_1_BCR] = { 0xac000 }, 2979 [GCC_PCIE_1_LINK_DOWN_BCR] = { 0x8e014 }, 2980 [GCC_PCIE_1_NOCSR_COM_PHY_BCR] = { 0x8e020 }, 2981 [GCC_PCIE_1_PHY_BCR] = { 0x8e01c }, 2982 [GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR] = { 0x8e024 }, 2983 [GCC_PCIE_PHY_BCR] = { 0x6f000 }, 2984 [GCC_PCIE_PHY_CFG_AHB_BCR] = { 0x6f00c }, 2985 [GCC_PCIE_PHY_COM_BCR] = { 0x6f010 }, 2986 [GCC_PCIE_RSCC_BCR] = { 0x11000 }, 2987 [GCC_PDM_BCR] = { 0x33000 }, 2988 [GCC_QUPV3_WRAPPER_1_BCR] = { 0x18000 }, 2989 [GCC_QUPV3_WRAPPER_2_BCR] = { 0x1e000 }, 2990 [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 }, 2991 [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 }, 2992 [GCC_SDCC1_BCR] = { 0xa9000 }, 2993 [GCC_SDCC2_BCR] = { 0x14000 }, 2994 [GCC_UFS_PHY_BCR] = { 0x77000 }, 2995 [GCC_USB30_PRIM_BCR] = { 0x39000 }, 2996 [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 }, 2997 [GCC_USB3_DP_PHY_SEC_BCR] = { 0x50014 }, 2998 [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 }, 2999 [GCC_USB3_PHY_SEC_BCR] = { 0x5000c }, 3000 [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 }, 3001 [GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 }, 3002 [GCC_VIDEO_AXI0_CLK_ARES] = { 0x32018, 2 }, 3003 [GCC_VIDEO_AXI1_CLK_ARES] = { 0x32028, 2 }, 3004 [GCC_VIDEO_BCR] = { 0x32000 }, 3005 }; 3006 3007 static const u32 gcc_eliza_critical_cbcrs[] = { 3008 0xa0004, /* GCC_CAM_BIST_MCLK_AHB_CLK */ 3009 0x26004, /* GCC_CAMERA_AHB_CLK */ 3010 0x26034, /* GCC_CAMERA_XO_CLK */ 3011 0x27004, /* GCC_DISP_AHB_CLK */ 3012 0x71004, /* GCC_GPU_CFG_AHB_CLK */ 3013 0x52010, /* GCC_PCIE_RSCC_CFG_AHB_CLK */ 3014 0x52010, /* GCC_PCIE_RSCC_XO_CLK */ 3015 0x32004, /* GCC_VIDEO_AHB_CLK */ 3016 0x32038, /* GCC_VIDEO_XO_CLK */ 3017 }; 3018 3019 static const struct clk_rcg_dfs_data gcc_eliza_dfs_clocks[] = { 3020 DEFINE_RCG_DFS(gcc_qupv3_wrap1_qspi_ref_clk_src), 3021 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src), 3022 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src), 3023 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src), 3024 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src), 3025 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src), 3026 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s6_clk_src), 3027 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s7_clk_src), 3028 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s0_clk_src), 3029 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s1_clk_src), 3030 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s2_clk_src), 3031 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s3_clk_src), 3032 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s4_clk_src), 3033 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s5_clk_src), 3034 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s6_clk_src), 3035 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s7_clk_src), 3036 }; 3037 3038 static const struct regmap_config gcc_eliza_regmap_config = { 3039 .reg_bits = 32, 3040 .reg_stride = 4, 3041 .val_bits = 32, 3042 .max_register = 0x1f41f0, 3043 .fast_io = true, 3044 }; 3045 3046 static void clk_eliza_regs_configure(struct device *dev, struct regmap *regmap) 3047 { 3048 /* FORCE_MEM_CORE_ON for ufs phy ice core and gcc ufs phy axi clocks */ 3049 qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_ice_core_clk, true); 3050 qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_axi_clk, true); 3051 } 3052 3053 static const struct qcom_cc_driver_data gcc_eliza_driver_data = { 3054 .clk_cbcrs = gcc_eliza_critical_cbcrs, 3055 .num_clk_cbcrs = ARRAY_SIZE(gcc_eliza_critical_cbcrs), 3056 .dfs_rcgs = gcc_eliza_dfs_clocks, 3057 .num_dfs_rcgs = ARRAY_SIZE(gcc_eliza_dfs_clocks), 3058 .clk_regs_configure = clk_eliza_regs_configure, 3059 }; 3060 3061 static const struct qcom_cc_desc gcc_eliza_desc = { 3062 .config = &gcc_eliza_regmap_config, 3063 .clks = gcc_eliza_clocks, 3064 .num_clks = ARRAY_SIZE(gcc_eliza_clocks), 3065 .resets = gcc_eliza_resets, 3066 .num_resets = ARRAY_SIZE(gcc_eliza_resets), 3067 .gdscs = gcc_eliza_gdscs, 3068 .num_gdscs = ARRAY_SIZE(gcc_eliza_gdscs), 3069 .driver_data = &gcc_eliza_driver_data, 3070 }; 3071 3072 static const struct of_device_id gcc_eliza_match_table[] = { 3073 { .compatible = "qcom,eliza-gcc" }, 3074 { } 3075 }; 3076 MODULE_DEVICE_TABLE(of, gcc_eliza_match_table); 3077 3078 static int gcc_eliza_probe(struct platform_device *pdev) 3079 { 3080 return qcom_cc_probe(pdev, &gcc_eliza_desc); 3081 } 3082 3083 static struct platform_driver gcc_eliza_driver = { 3084 .probe = gcc_eliza_probe, 3085 .driver = { 3086 .name = "gcc-eliza", 3087 .of_match_table = gcc_eliza_match_table, 3088 }, 3089 }; 3090 3091 static int __init gcc_eliza_init(void) 3092 { 3093 return platform_driver_register(&gcc_eliza_driver); 3094 } 3095 subsys_initcall(gcc_eliza_init); 3096 3097 static void __exit gcc_eliza_exit(void) 3098 { 3099 platform_driver_unregister(&gcc_eliza_driver); 3100 } 3101 module_exit(gcc_eliza_exit); 3102 3103 MODULE_DESCRIPTION("QTI GCC Eliza Driver"); 3104 MODULE_LICENSE("GPL"); 3105