1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
4 */
5
6 #include <linux/clk-provider.h>
7 #include <linux/module.h>
8 #include <linux/platform_device.h>
9 #include <linux/regmap.h>
10
11 #include <dt-bindings/clock/qcom,nord-dispcc.h>
12
13 #include "clk-alpha-pll.h"
14 #include "clk-branch.h"
15 #include "clk-pll.h"
16 #include "clk-rcg.h"
17 #include "clk-regmap.h"
18 #include "clk-regmap-divider.h"
19 #include "clk-regmap-mux.h"
20 #include "common.h"
21 #include "gdsc.h"
22 #include "reset.h"
23
24 enum {
25 DT_BI_TCXO,
26 DT_BI_TCXO_AO,
27 DT_AHB_CLK,
28 DT_SLEEP_CLK,
29
30 DT_DSI0_PHY_PLL_OUT_BYTECLK,
31 DT_DSI0_PHY_PLL_OUT_DSICLK,
32 DT_DSI1_PHY_PLL_OUT_BYTECLK,
33 DT_DSI1_PHY_PLL_OUT_DSICLK,
34
35 DT_DP0_PHY_PLL_LINK_CLK,
36 DT_DP0_PHY_PLL_VCO_DIV_CLK,
37 DT_DP1_PHY_PLL_LINK_CLK,
38 DT_DP1_PHY_PLL_VCO_DIV_CLK,
39 DT_DP2_PHY_PLL_LINK_CLK,
40 DT_DP2_PHY_PLL_VCO_DIV_CLK,
41 DT_DP3_PHY_PLL_LINK_CLK,
42 DT_DP3_PHY_PLL_VCO_DIV_CLK,
43 };
44
45 enum {
46 P_BI_TCXO,
47 P_MDSS_0_DISP_CC_PLL0_OUT_MAIN,
48 P_MDSS_0_DISP_CC_PLL1_OUT_EVEN,
49 P_MDSS_0_DISP_CC_PLL1_OUT_MAIN,
50 P_MDSS_0_DISP_CC_PLL2_OUT_MAIN,
51 P_MDSS_0_DISP_CC_PLL3_OUT_MAIN,
52 P_DP0_PHY_PLL_LINK_CLK,
53 P_DP0_PHY_PLL_VCO_DIV_CLK,
54 P_DP1_PHY_PLL_LINK_CLK,
55 P_DP1_PHY_PLL_VCO_DIV_CLK,
56 P_DP2_PHY_PLL_LINK_CLK,
57 P_DP2_PHY_PLL_VCO_DIV_CLK,
58 P_DP3_PHY_PLL_LINK_CLK,
59 P_DP3_PHY_PLL_VCO_DIV_CLK,
60 P_DSI0_PHY_PLL_OUT_BYTECLK,
61 P_DSI0_PHY_PLL_OUT_DSICLK,
62 P_DSI1_PHY_PLL_OUT_BYTECLK,
63 P_DSI1_PHY_PLL_OUT_DSICLK,
64 P_SLEEP_CLK,
65 };
66
67 static const struct pll_vco lucid_ole_vco[] = {
68 { 249600000, 2300000000, 0 },
69 };
70
71 static const struct pll_vco zonda_ole_vco[] = {
72 { 700000000, 3600000000, 0 },
73 };
74
75 /* 900.0 MHz Configuration */
76 static const struct alpha_pll_config mdss_0_disp_cc_pll0_config = {
77 .l = 0x2e,
78 .alpha = 0xe000,
79 .config_ctl_val = 0x20485699,
80 .config_ctl_hi_val = 0x00182261,
81 .config_ctl_hi1_val = 0x82aa299c,
82 .test_ctl_val = 0x00000000,
83 .test_ctl_hi_val = 0x00000003,
84 .test_ctl_hi1_val = 0x00009000,
85 .test_ctl_hi2_val = 0x00000034,
86 .user_ctl_val = 0x00000000,
87 .user_ctl_hi_val = 0x00400005,
88 };
89
90 static struct clk_alpha_pll mdss_0_disp_cc_pll0 = {
91 .offset = 0x0,
92 .config = &mdss_0_disp_cc_pll0_config,
93 .vco_table = lucid_ole_vco,
94 .num_vco = ARRAY_SIZE(lucid_ole_vco),
95 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
96 .clkr = {
97 .hw.init = &(const struct clk_init_data) {
98 .name = "mdss_0_disp_cc_pll0",
99 .parent_data = &(const struct clk_parent_data) {
100 .index = DT_BI_TCXO,
101 },
102 .num_parents = 1,
103 .ops = &clk_alpha_pll_lucid_evo_ops,
104 },
105 },
106 };
107
108 /* 600.0 MHz Configuration */
109 static const struct alpha_pll_config mdss_0_disp_cc_pll1_config = {
110 .l = 0x1f,
111 .alpha = 0x4000,
112 .config_ctl_val = 0x20485699,
113 .config_ctl_hi_val = 0x00182261,
114 .config_ctl_hi1_val = 0x82aa299c,
115 .test_ctl_val = 0x00000000,
116 .test_ctl_hi_val = 0x00000003,
117 .test_ctl_hi1_val = 0x00009000,
118 .test_ctl_hi2_val = 0x00000034,
119 .user_ctl_val = 0x00000000,
120 .user_ctl_hi_val = 0x00400005,
121 };
122
123 static struct clk_alpha_pll mdss_0_disp_cc_pll1 = {
124 .offset = 0x1000,
125 .config = &mdss_0_disp_cc_pll1_config,
126 .vco_table = lucid_ole_vco,
127 .num_vco = ARRAY_SIZE(lucid_ole_vco),
128 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
129 .clkr = {
130 .hw.init = &(const struct clk_init_data) {
131 .name = "mdss_0_disp_cc_pll1",
132 .parent_data = &(const struct clk_parent_data) {
133 .index = DT_BI_TCXO,
134 },
135 .num_parents = 1,
136 .ops = &clk_alpha_pll_lucid_evo_ops,
137 },
138 },
139 };
140
141 /* 1363.2 MHz Configuration */
142 static const struct alpha_pll_config mdss_0_disp_cc_pll2_config = {
143 .l = 0x47,
144 .alpha = 0x0,
145 .config_ctl_val = 0x08240800,
146 .config_ctl_hi_val = 0x05008001,
147 .config_ctl_hi1_val = 0x00000000,
148 .config_ctl_hi2_val = 0x00000000,
149 .user_ctl_val = 0x00000000,
150 .user_ctl_hi_val = 0x00000080,
151 };
152
153 static struct clk_alpha_pll mdss_0_disp_cc_pll2 = {
154 .offset = 0x2000,
155 .config = &mdss_0_disp_cc_pll2_config,
156 .vco_table = zonda_ole_vco,
157 .num_vco = ARRAY_SIZE(zonda_ole_vco),
158 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_ZONDA_OLE],
159 .clkr = {
160 .hw.init = &(const struct clk_init_data) {
161 .name = "mdss_0_disp_cc_pll2",
162 .parent_data = &(const struct clk_parent_data) {
163 .index = DT_BI_TCXO,
164 },
165 .num_parents = 1,
166 .ops = &clk_alpha_pll_zonda_ole_ops,
167 },
168 },
169 };
170
171 /* 1363.2 MHz Configuration */
172 static const struct alpha_pll_config mdss_0_disp_cc_pll3_config = {
173 .l = 0x47,
174 .alpha = 0x0,
175 .config_ctl_val = 0x08240800,
176 .config_ctl_hi_val = 0x05008001,
177 .config_ctl_hi1_val = 0x00000000,
178 .config_ctl_hi2_val = 0x00000000,
179 .user_ctl_val = 0x00000000,
180 .user_ctl_hi_val = 0x00000080,
181 };
182
183 static struct clk_alpha_pll mdss_0_disp_cc_pll3 = {
184 .offset = 0x3000,
185 .config = &mdss_0_disp_cc_pll3_config,
186 .vco_table = zonda_ole_vco,
187 .num_vco = ARRAY_SIZE(zonda_ole_vco),
188 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_ZONDA_OLE],
189 .clkr = {
190 .hw.init = &(const struct clk_init_data) {
191 .name = "mdss_0_disp_cc_pll3",
192 .parent_data = &(const struct clk_parent_data) {
193 .index = DT_BI_TCXO,
194 },
195 .num_parents = 1,
196 .ops = &clk_alpha_pll_zonda_ole_ops,
197 },
198 },
199 };
200
201 static const struct parent_map disp_cc_0_parent_map_0[] = {
202 { P_BI_TCXO, 0 },
203 { P_MDSS_0_DISP_CC_PLL2_OUT_MAIN, 1 },
204 { P_DP0_PHY_PLL_VCO_DIV_CLK, 2 },
205 { P_DP3_PHY_PLL_VCO_DIV_CLK, 3 },
206 { P_DP1_PHY_PLL_VCO_DIV_CLK, 4 },
207 { P_MDSS_0_DISP_CC_PLL3_OUT_MAIN, 5 },
208 { P_DP2_PHY_PLL_VCO_DIV_CLK, 6 },
209 };
210
211 static const struct clk_parent_data disp_cc_0_parent_data_0[] = {
212 { .index = DT_BI_TCXO },
213 { .hw = &mdss_0_disp_cc_pll2.clkr.hw },
214 { .index = DT_DP0_PHY_PLL_VCO_DIV_CLK },
215 { .index = DT_DP3_PHY_PLL_VCO_DIV_CLK },
216 { .index = DT_DP1_PHY_PLL_VCO_DIV_CLK },
217 { .hw = &mdss_0_disp_cc_pll3.clkr.hw },
218 { .index = DT_DP2_PHY_PLL_VCO_DIV_CLK },
219 };
220
221 static const struct parent_map disp_cc_0_parent_map_1[] = {
222 { P_BI_TCXO, 0 },
223 };
224
225 static const struct clk_parent_data disp_cc_0_parent_data_1[] = {
226 { .index = DT_BI_TCXO },
227 };
228
229 static const struct parent_map disp_cc_0_parent_map_2[] = {
230 { P_BI_TCXO, 0 },
231 { P_DSI0_PHY_PLL_OUT_DSICLK, 1 },
232 { P_DSI0_PHY_PLL_OUT_BYTECLK, 2 },
233 { P_DSI1_PHY_PLL_OUT_DSICLK, 3 },
234 { P_DSI1_PHY_PLL_OUT_BYTECLK, 4 },
235 };
236
237 static const struct clk_parent_data disp_cc_0_parent_data_2[] = {
238 { .index = DT_BI_TCXO },
239 { .index = DT_DSI0_PHY_PLL_OUT_DSICLK },
240 { .index = DT_DSI0_PHY_PLL_OUT_BYTECLK },
241 { .index = DT_DSI1_PHY_PLL_OUT_DSICLK },
242 { .index = DT_DSI1_PHY_PLL_OUT_BYTECLK },
243 };
244
245 static const struct parent_map disp_cc_0_parent_map_3[] = {
246 { P_BI_TCXO, 0 },
247 { P_MDSS_0_DISP_CC_PLL2_OUT_MAIN, 1 },
248 { P_DP3_PHY_PLL_VCO_DIV_CLK, 3 },
249 { P_MDSS_0_DISP_CC_PLL3_OUT_MAIN, 5 },
250 { P_DP2_PHY_PLL_VCO_DIV_CLK, 6 },
251 };
252
253 static const struct clk_parent_data disp_cc_0_parent_data_3[] = {
254 { .index = DT_BI_TCXO },
255 { .hw = &mdss_0_disp_cc_pll2.clkr.hw },
256 { .index = DT_DP3_PHY_PLL_VCO_DIV_CLK },
257 { .hw = &mdss_0_disp_cc_pll3.clkr.hw },
258 { .index = DT_DP2_PHY_PLL_VCO_DIV_CLK },
259 };
260
261 static const struct parent_map disp_cc_0_parent_map_4[] = {
262 { P_BI_TCXO, 0 },
263 { P_DP0_PHY_PLL_LINK_CLK, 1 },
264 { P_DP1_PHY_PLL_LINK_CLK, 2 },
265 { P_DP2_PHY_PLL_LINK_CLK, 3 },
266 { P_DP3_PHY_PLL_LINK_CLK, 4 },
267 };
268
269 static const struct clk_parent_data disp_cc_0_parent_data_4[] = {
270 { .index = DT_BI_TCXO },
271 { .index = DT_DP0_PHY_PLL_LINK_CLK },
272 { .index = DT_DP1_PHY_PLL_LINK_CLK },
273 { .index = DT_DP2_PHY_PLL_LINK_CLK },
274 { .index = DT_DP3_PHY_PLL_LINK_CLK },
275 };
276
277 static const struct parent_map disp_cc_0_parent_map_5[] = {
278 { P_BI_TCXO, 0 },
279 { P_DP2_PHY_PLL_LINK_CLK, 3 },
280 { P_DP3_PHY_PLL_LINK_CLK, 4 },
281 };
282
283 static const struct clk_parent_data disp_cc_0_parent_data_5[] = {
284 { .index = DT_BI_TCXO },
285 { .index = DT_DP2_PHY_PLL_LINK_CLK },
286 { .index = DT_DP3_PHY_PLL_LINK_CLK },
287 };
288
289 static const struct parent_map disp_cc_0_parent_map_6[] = {
290 { P_BI_TCXO, 0 },
291 { P_DSI0_PHY_PLL_OUT_BYTECLK, 2 },
292 { P_DSI1_PHY_PLL_OUT_BYTECLK, 4 },
293 };
294
295 static const struct clk_parent_data disp_cc_0_parent_data_6[] = {
296 { .index = DT_BI_TCXO },
297 { .index = DT_DSI0_PHY_PLL_OUT_BYTECLK },
298 { .index = DT_DSI1_PHY_PLL_OUT_BYTECLK },
299 };
300
301 static const struct parent_map disp_cc_0_parent_map_7[] = {
302 { P_BI_TCXO, 0 },
303 { P_MDSS_0_DISP_CC_PLL1_OUT_MAIN, 4 },
304 { P_MDSS_0_DISP_CC_PLL1_OUT_EVEN, 6 },
305 };
306
307 static const struct clk_parent_data disp_cc_0_parent_data_7[] = {
308 { .index = DT_BI_TCXO },
309 { .hw = &mdss_0_disp_cc_pll1.clkr.hw },
310 { .hw = &mdss_0_disp_cc_pll1.clkr.hw },
311 };
312
313 static const struct parent_map disp_cc_0_parent_map_8[] = {
314 { P_BI_TCXO, 0 },
315 { P_MDSS_0_DISP_CC_PLL0_OUT_MAIN, 1 },
316 { P_MDSS_0_DISP_CC_PLL1_OUT_MAIN, 4 },
317 { P_MDSS_0_DISP_CC_PLL1_OUT_EVEN, 6 },
318 };
319
320 static const struct clk_parent_data disp_cc_0_parent_data_8[] = {
321 { .index = DT_BI_TCXO },
322 { .hw = &mdss_0_disp_cc_pll0.clkr.hw },
323 { .hw = &mdss_0_disp_cc_pll1.clkr.hw },
324 { .hw = &mdss_0_disp_cc_pll1.clkr.hw },
325 };
326
327 static const struct parent_map disp_cc_0_parent_map_9[] = {
328 { P_SLEEP_CLK, 0 },
329 };
330
331 static const struct clk_parent_data disp_cc_0_parent_data_9[] = {
332 { .index = DT_SLEEP_CLK },
333 };
334
335 static const struct freq_tbl ftbl_mdss_0_disp_cc_mdss_ahb_clk_src[] = {
336 F(37500000, P_MDSS_0_DISP_CC_PLL1_OUT_MAIN, 16, 0, 0),
337 F(75000000, P_MDSS_0_DISP_CC_PLL1_OUT_MAIN, 8, 0, 0),
338 { }
339 };
340
341 static struct clk_rcg2 mdss_0_disp_cc_mdss_ahb_clk_src = {
342 .cmd_rcgr = 0x837c,
343 .mnd_width = 0,
344 .hid_width = 5,
345 .parent_map = disp_cc_0_parent_map_7,
346 .freq_tbl = ftbl_mdss_0_disp_cc_mdss_ahb_clk_src,
347 .hw_clk_ctrl = true,
348 .clkr.hw.init = &(const struct clk_init_data) {
349 .name = "mdss_0_disp_cc_mdss_ahb_clk_src",
350 .parent_data = disp_cc_0_parent_data_7,
351 .num_parents = ARRAY_SIZE(disp_cc_0_parent_data_7),
352 .flags = CLK_SET_RATE_PARENT,
353 .ops = &clk_rcg2_shared_ops,
354 },
355 };
356
357 static const struct freq_tbl ftbl_mdss_0_disp_cc_mdss_byte0_clk_src[] = {
358 F(19200000, P_BI_TCXO, 1, 0, 0),
359 { }
360 };
361
362 static struct clk_rcg2 mdss_0_disp_cc_mdss_byte0_clk_src = {
363 .cmd_rcgr = 0x813c,
364 .mnd_width = 0,
365 .hid_width = 5,
366 .parent_map = disp_cc_0_parent_map_2,
367 .freq_tbl = ftbl_mdss_0_disp_cc_mdss_byte0_clk_src,
368 .hw_clk_ctrl = true,
369 .clkr.hw.init = &(const struct clk_init_data) {
370 .name = "mdss_0_disp_cc_mdss_byte0_clk_src",
371 .parent_data = disp_cc_0_parent_data_2,
372 .num_parents = ARRAY_SIZE(disp_cc_0_parent_data_2),
373 .flags = CLK_SET_RATE_PARENT,
374 .ops = &clk_byte2_ops,
375 },
376 };
377
378 static struct clk_rcg2 mdss_0_disp_cc_mdss_byte1_clk_src = {
379 .cmd_rcgr = 0x8158,
380 .mnd_width = 0,
381 .hid_width = 5,
382 .parent_map = disp_cc_0_parent_map_2,
383 .freq_tbl = ftbl_mdss_0_disp_cc_mdss_byte0_clk_src,
384 .hw_clk_ctrl = true,
385 .clkr.hw.init = &(const struct clk_init_data) {
386 .name = "mdss_0_disp_cc_mdss_byte1_clk_src",
387 .parent_data = disp_cc_0_parent_data_2,
388 .num_parents = ARRAY_SIZE(disp_cc_0_parent_data_2),
389 .flags = CLK_SET_RATE_PARENT,
390 .ops = &clk_byte2_ops,
391 },
392 };
393
394 static struct clk_rcg2 mdss_0_disp_cc_mdss_dptx0_aux_clk_src = {
395 .cmd_rcgr = 0x8220,
396 .mnd_width = 0,
397 .hid_width = 5,
398 .parent_map = disp_cc_0_parent_map_1,
399 .freq_tbl = ftbl_mdss_0_disp_cc_mdss_byte0_clk_src,
400 .hw_clk_ctrl = true,
401 .clkr.hw.init = &(const struct clk_init_data) {
402 .name = "mdss_0_disp_cc_mdss_dptx0_aux_clk_src",
403 .parent_data = disp_cc_0_parent_data_1,
404 .num_parents = ARRAY_SIZE(disp_cc_0_parent_data_1),
405 .flags = CLK_SET_RATE_PARENT,
406 .ops = &clk_rcg2_shared_ops,
407 },
408 };
409
410 static struct clk_rcg2 mdss_0_disp_cc_mdss_dptx0_link_clk_src = {
411 .cmd_rcgr = 0x81a4,
412 .mnd_width = 0,
413 .hid_width = 5,
414 .parent_map = disp_cc_0_parent_map_4,
415 .freq_tbl = ftbl_mdss_0_disp_cc_mdss_byte0_clk_src,
416 .hw_clk_ctrl = true,
417 .clkr.hw.init = &(const struct clk_init_data) {
418 .name = "mdss_0_disp_cc_mdss_dptx0_link_clk_src",
419 .parent_data = disp_cc_0_parent_data_4,
420 .num_parents = ARRAY_SIZE(disp_cc_0_parent_data_4),
421 .flags = CLK_SET_RATE_PARENT,
422 .ops = &clk_byte2_ops,
423 },
424 };
425
426 static struct clk_rcg2 mdss_0_disp_cc_mdss_dptx0_pixel0_clk_src = {
427 .cmd_rcgr = 0x81c0,
428 .mnd_width = 16,
429 .hid_width = 5,
430 .parent_map = disp_cc_0_parent_map_0,
431 .freq_tbl = ftbl_mdss_0_disp_cc_mdss_byte0_clk_src,
432 .hw_clk_ctrl = true,
433 .clkr.hw.init = &(const struct clk_init_data) {
434 .name = "mdss_0_disp_cc_mdss_dptx0_pixel0_clk_src",
435 .parent_data = disp_cc_0_parent_data_0,
436 .num_parents = ARRAY_SIZE(disp_cc_0_parent_data_0),
437 .flags = CLK_SET_RATE_PARENT,
438 .ops = &clk_dp_ops,
439 },
440 };
441
442 static struct clk_rcg2 mdss_0_disp_cc_mdss_dptx0_pixel1_clk_src = {
443 .cmd_rcgr = 0x81d8,
444 .mnd_width = 16,
445 .hid_width = 5,
446 .parent_map = disp_cc_0_parent_map_0,
447 .freq_tbl = ftbl_mdss_0_disp_cc_mdss_byte0_clk_src,
448 .hw_clk_ctrl = true,
449 .clkr.hw.init = &(const struct clk_init_data) {
450 .name = "mdss_0_disp_cc_mdss_dptx0_pixel1_clk_src",
451 .parent_data = disp_cc_0_parent_data_0,
452 .num_parents = ARRAY_SIZE(disp_cc_0_parent_data_0),
453 .flags = CLK_SET_RATE_PARENT,
454 .ops = &clk_dp_ops,
455 },
456 };
457
458 static struct clk_rcg2 mdss_0_disp_cc_mdss_dptx0_pixel2_clk_src = {
459 .cmd_rcgr = 0x81f0,
460 .mnd_width = 16,
461 .hid_width = 5,
462 .parent_map = disp_cc_0_parent_map_0,
463 .freq_tbl = ftbl_mdss_0_disp_cc_mdss_byte0_clk_src,
464 .hw_clk_ctrl = true,
465 .clkr.hw.init = &(const struct clk_init_data) {
466 .name = "mdss_0_disp_cc_mdss_dptx0_pixel2_clk_src",
467 .parent_data = disp_cc_0_parent_data_0,
468 .num_parents = ARRAY_SIZE(disp_cc_0_parent_data_0),
469 .flags = CLK_SET_RATE_PARENT,
470 .ops = &clk_dp_ops,
471 },
472 };
473
474 static struct clk_rcg2 mdss_0_disp_cc_mdss_dptx0_pixel3_clk_src = {
475 .cmd_rcgr = 0x8208,
476 .mnd_width = 16,
477 .hid_width = 5,
478 .parent_map = disp_cc_0_parent_map_0,
479 .freq_tbl = ftbl_mdss_0_disp_cc_mdss_byte0_clk_src,
480 .hw_clk_ctrl = true,
481 .clkr.hw.init = &(const struct clk_init_data) {
482 .name = "mdss_0_disp_cc_mdss_dptx0_pixel3_clk_src",
483 .parent_data = disp_cc_0_parent_data_0,
484 .num_parents = ARRAY_SIZE(disp_cc_0_parent_data_0),
485 .flags = CLK_SET_RATE_PARENT,
486 .ops = &clk_dp_ops,
487 },
488 };
489
490 static struct clk_rcg2 mdss_0_disp_cc_mdss_dptx1_aux_clk_src = {
491 .cmd_rcgr = 0x82b4,
492 .mnd_width = 0,
493 .hid_width = 5,
494 .parent_map = disp_cc_0_parent_map_1,
495 .freq_tbl = ftbl_mdss_0_disp_cc_mdss_byte0_clk_src,
496 .hw_clk_ctrl = true,
497 .clkr.hw.init = &(const struct clk_init_data) {
498 .name = "mdss_0_disp_cc_mdss_dptx1_aux_clk_src",
499 .parent_data = disp_cc_0_parent_data_1,
500 .num_parents = ARRAY_SIZE(disp_cc_0_parent_data_1),
501 .flags = CLK_SET_RATE_PARENT,
502 .ops = &clk_rcg2_shared_ops,
503 },
504 };
505
506 static struct clk_rcg2 mdss_0_disp_cc_mdss_dptx1_link_clk_src = {
507 .cmd_rcgr = 0x8298,
508 .mnd_width = 0,
509 .hid_width = 5,
510 .parent_map = disp_cc_0_parent_map_4,
511 .freq_tbl = ftbl_mdss_0_disp_cc_mdss_byte0_clk_src,
512 .hw_clk_ctrl = true,
513 .clkr.hw.init = &(const struct clk_init_data) {
514 .name = "mdss_0_disp_cc_mdss_dptx1_link_clk_src",
515 .parent_data = disp_cc_0_parent_data_4,
516 .num_parents = ARRAY_SIZE(disp_cc_0_parent_data_4),
517 .flags = CLK_SET_RATE_PARENT,
518 .ops = &clk_byte2_ops,
519 },
520 };
521
522 static struct clk_rcg2 mdss_0_disp_cc_mdss_dptx1_pixel0_clk_src = {
523 .cmd_rcgr = 0x8238,
524 .mnd_width = 16,
525 .hid_width = 5,
526 .parent_map = disp_cc_0_parent_map_0,
527 .freq_tbl = ftbl_mdss_0_disp_cc_mdss_byte0_clk_src,
528 .hw_clk_ctrl = true,
529 .clkr.hw.init = &(const struct clk_init_data) {
530 .name = "mdss_0_disp_cc_mdss_dptx1_pixel0_clk_src",
531 .parent_data = disp_cc_0_parent_data_0,
532 .num_parents = ARRAY_SIZE(disp_cc_0_parent_data_0),
533 .flags = CLK_SET_RATE_PARENT,
534 .ops = &clk_dp_ops,
535 },
536 };
537
538 static struct clk_rcg2 mdss_0_disp_cc_mdss_dptx1_pixel1_clk_src = {
539 .cmd_rcgr = 0x8250,
540 .mnd_width = 16,
541 .hid_width = 5,
542 .parent_map = disp_cc_0_parent_map_0,
543 .freq_tbl = ftbl_mdss_0_disp_cc_mdss_byte0_clk_src,
544 .hw_clk_ctrl = true,
545 .clkr.hw.init = &(const struct clk_init_data) {
546 .name = "mdss_0_disp_cc_mdss_dptx1_pixel1_clk_src",
547 .parent_data = disp_cc_0_parent_data_0,
548 .num_parents = ARRAY_SIZE(disp_cc_0_parent_data_0),
549 .flags = CLK_SET_RATE_PARENT,
550 .ops = &clk_dp_ops,
551 },
552 };
553
554 static struct clk_rcg2 mdss_0_disp_cc_mdss_dptx1_pixel2_clk_src = {
555 .cmd_rcgr = 0x8268,
556 .mnd_width = 16,
557 .hid_width = 5,
558 .parent_map = disp_cc_0_parent_map_0,
559 .freq_tbl = ftbl_mdss_0_disp_cc_mdss_byte0_clk_src,
560 .hw_clk_ctrl = true,
561 .clkr.hw.init = &(const struct clk_init_data) {
562 .name = "mdss_0_disp_cc_mdss_dptx1_pixel2_clk_src",
563 .parent_data = disp_cc_0_parent_data_0,
564 .num_parents = ARRAY_SIZE(disp_cc_0_parent_data_0),
565 .flags = CLK_SET_RATE_PARENT,
566 .ops = &clk_dp_ops,
567 },
568 };
569
570 static struct clk_rcg2 mdss_0_disp_cc_mdss_dptx1_pixel3_clk_src = {
571 .cmd_rcgr = 0x8280,
572 .mnd_width = 16,
573 .hid_width = 5,
574 .parent_map = disp_cc_0_parent_map_0,
575 .freq_tbl = ftbl_mdss_0_disp_cc_mdss_byte0_clk_src,
576 .hw_clk_ctrl = true,
577 .clkr.hw.init = &(const struct clk_init_data) {
578 .name = "mdss_0_disp_cc_mdss_dptx1_pixel3_clk_src",
579 .parent_data = disp_cc_0_parent_data_0,
580 .num_parents = ARRAY_SIZE(disp_cc_0_parent_data_0),
581 .flags = CLK_SET_RATE_PARENT,
582 .ops = &clk_dp_ops,
583 },
584 };
585
586 static struct clk_rcg2 mdss_0_disp_cc_mdss_dptx2_aux_clk_src = {
587 .cmd_rcgr = 0x8318,
588 .mnd_width = 0,
589 .hid_width = 5,
590 .parent_map = disp_cc_0_parent_map_1,
591 .freq_tbl = ftbl_mdss_0_disp_cc_mdss_byte0_clk_src,
592 .hw_clk_ctrl = true,
593 .clkr.hw.init = &(const struct clk_init_data) {
594 .name = "mdss_0_disp_cc_mdss_dptx2_aux_clk_src",
595 .parent_data = disp_cc_0_parent_data_1,
596 .num_parents = ARRAY_SIZE(disp_cc_0_parent_data_1),
597 .flags = CLK_SET_RATE_PARENT,
598 .ops = &clk_rcg2_shared_ops,
599 },
600 };
601
602 static struct clk_rcg2 mdss_0_disp_cc_mdss_dptx2_link_clk_src = {
603 .cmd_rcgr = 0x82cc,
604 .mnd_width = 0,
605 .hid_width = 5,
606 .parent_map = disp_cc_0_parent_map_5,
607 .freq_tbl = ftbl_mdss_0_disp_cc_mdss_byte0_clk_src,
608 .hw_clk_ctrl = true,
609 .clkr.hw.init = &(const struct clk_init_data) {
610 .name = "mdss_0_disp_cc_mdss_dptx2_link_clk_src",
611 .parent_data = disp_cc_0_parent_data_5,
612 .num_parents = ARRAY_SIZE(disp_cc_0_parent_data_5),
613 .flags = CLK_SET_RATE_PARENT,
614 .ops = &clk_byte2_ops,
615 },
616 };
617
618 static struct clk_rcg2 mdss_0_disp_cc_mdss_dptx2_pixel0_clk_src = {
619 .cmd_rcgr = 0x82e8,
620 .mnd_width = 16,
621 .hid_width = 5,
622 .parent_map = disp_cc_0_parent_map_3,
623 .freq_tbl = ftbl_mdss_0_disp_cc_mdss_byte0_clk_src,
624 .hw_clk_ctrl = true,
625 .clkr.hw.init = &(const struct clk_init_data) {
626 .name = "mdss_0_disp_cc_mdss_dptx2_pixel0_clk_src",
627 .parent_data = disp_cc_0_parent_data_3,
628 .num_parents = ARRAY_SIZE(disp_cc_0_parent_data_3),
629 .flags = CLK_SET_RATE_PARENT,
630 .ops = &clk_dp_ops,
631 },
632 };
633
634 static struct clk_rcg2 mdss_0_disp_cc_mdss_dptx2_pixel1_clk_src = {
635 .cmd_rcgr = 0x8300,
636 .mnd_width = 16,
637 .hid_width = 5,
638 .parent_map = disp_cc_0_parent_map_3,
639 .freq_tbl = ftbl_mdss_0_disp_cc_mdss_byte0_clk_src,
640 .hw_clk_ctrl = true,
641 .clkr.hw.init = &(const struct clk_init_data) {
642 .name = "mdss_0_disp_cc_mdss_dptx2_pixel1_clk_src",
643 .parent_data = disp_cc_0_parent_data_3,
644 .num_parents = ARRAY_SIZE(disp_cc_0_parent_data_3),
645 .flags = CLK_SET_RATE_PARENT,
646 .ops = &clk_dp_ops,
647 },
648 };
649
650 static struct clk_rcg2 mdss_0_disp_cc_mdss_dptx3_aux_clk_src = {
651 .cmd_rcgr = 0x8364,
652 .mnd_width = 0,
653 .hid_width = 5,
654 .parent_map = disp_cc_0_parent_map_1,
655 .freq_tbl = ftbl_mdss_0_disp_cc_mdss_byte0_clk_src,
656 .hw_clk_ctrl = true,
657 .clkr.hw.init = &(const struct clk_init_data) {
658 .name = "mdss_0_disp_cc_mdss_dptx3_aux_clk_src",
659 .parent_data = disp_cc_0_parent_data_1,
660 .num_parents = ARRAY_SIZE(disp_cc_0_parent_data_1),
661 .flags = CLK_SET_RATE_PARENT,
662 .ops = &clk_rcg2_shared_ops,
663 },
664 };
665
666 static struct clk_rcg2 mdss_0_disp_cc_mdss_dptx3_link_clk_src = {
667 .cmd_rcgr = 0x8348,
668 .mnd_width = 0,
669 .hid_width = 5,
670 .parent_map = disp_cc_0_parent_map_5,
671 .freq_tbl = ftbl_mdss_0_disp_cc_mdss_byte0_clk_src,
672 .hw_clk_ctrl = true,
673 .clkr.hw.init = &(const struct clk_init_data) {
674 .name = "mdss_0_disp_cc_mdss_dptx3_link_clk_src",
675 .parent_data = disp_cc_0_parent_data_5,
676 .num_parents = ARRAY_SIZE(disp_cc_0_parent_data_5),
677 .flags = CLK_SET_RATE_PARENT,
678 .ops = &clk_byte2_ops,
679 },
680 };
681
682 static struct clk_rcg2 mdss_0_disp_cc_mdss_dptx3_pixel0_clk_src = {
683 .cmd_rcgr = 0x8330,
684 .mnd_width = 16,
685 .hid_width = 5,
686 .parent_map = disp_cc_0_parent_map_3,
687 .freq_tbl = ftbl_mdss_0_disp_cc_mdss_byte0_clk_src,
688 .hw_clk_ctrl = true,
689 .clkr.hw.init = &(const struct clk_init_data) {
690 .name = "mdss_0_disp_cc_mdss_dptx3_pixel0_clk_src",
691 .parent_data = disp_cc_0_parent_data_3,
692 .num_parents = ARRAY_SIZE(disp_cc_0_parent_data_3),
693 .flags = CLK_SET_RATE_PARENT,
694 .ops = &clk_dp_ops,
695 },
696 };
697
698 static struct clk_rcg2 mdss_0_disp_cc_mdss_esc0_clk_src = {
699 .cmd_rcgr = 0x8174,
700 .mnd_width = 0,
701 .hid_width = 5,
702 .parent_map = disp_cc_0_parent_map_6,
703 .freq_tbl = ftbl_mdss_0_disp_cc_mdss_byte0_clk_src,
704 .hw_clk_ctrl = true,
705 .clkr.hw.init = &(const struct clk_init_data) {
706 .name = "mdss_0_disp_cc_mdss_esc0_clk_src",
707 .parent_data = disp_cc_0_parent_data_6,
708 .num_parents = ARRAY_SIZE(disp_cc_0_parent_data_6),
709 .flags = CLK_SET_RATE_PARENT,
710 .ops = &clk_rcg2_shared_ops,
711 },
712 };
713
714 static struct clk_rcg2 mdss_0_disp_cc_mdss_esc1_clk_src = {
715 .cmd_rcgr = 0x818c,
716 .mnd_width = 0,
717 .hid_width = 5,
718 .parent_map = disp_cc_0_parent_map_6,
719 .freq_tbl = ftbl_mdss_0_disp_cc_mdss_byte0_clk_src,
720 .hw_clk_ctrl = true,
721 .clkr.hw.init = &(const struct clk_init_data) {
722 .name = "mdss_0_disp_cc_mdss_esc1_clk_src",
723 .parent_data = disp_cc_0_parent_data_6,
724 .num_parents = ARRAY_SIZE(disp_cc_0_parent_data_6),
725 .flags = CLK_SET_RATE_PARENT,
726 .ops = &clk_rcg2_shared_ops,
727 },
728 };
729
730 static const struct freq_tbl ftbl_mdss_0_disp_cc_mdss_mdp_clk_src[] = {
731 F(300000000, P_MDSS_0_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
732 F(417000000, P_MDSS_0_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
733 F(532000000, P_MDSS_0_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
734 F(650000000, P_MDSS_0_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
735 F(710000000, P_MDSS_0_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
736 { }
737 };
738
739 static struct clk_rcg2 mdss_0_disp_cc_mdss_mdp_clk_src = {
740 .cmd_rcgr = 0x810c,
741 .mnd_width = 0,
742 .hid_width = 5,
743 .parent_map = disp_cc_0_parent_map_8,
744 .freq_tbl = ftbl_mdss_0_disp_cc_mdss_mdp_clk_src,
745 .hw_clk_ctrl = true,
746 .clkr.hw.init = &(const struct clk_init_data) {
747 .name = "mdss_0_disp_cc_mdss_mdp_clk_src",
748 .parent_data = disp_cc_0_parent_data_8,
749 .num_parents = ARRAY_SIZE(disp_cc_0_parent_data_8),
750 .flags = CLK_SET_RATE_PARENT,
751 .ops = &clk_rcg2_shared_ops,
752 },
753 };
754
755 static struct clk_rcg2 mdss_0_disp_cc_mdss_pclk0_clk_src = {
756 .cmd_rcgr = 0x80c4,
757 .mnd_width = 8,
758 .hid_width = 5,
759 .parent_map = disp_cc_0_parent_map_2,
760 .freq_tbl = ftbl_mdss_0_disp_cc_mdss_byte0_clk_src,
761 .hw_clk_ctrl = true,
762 .clkr.hw.init = &(const struct clk_init_data) {
763 .name = "mdss_0_disp_cc_mdss_pclk0_clk_src",
764 .parent_data = disp_cc_0_parent_data_2,
765 .num_parents = ARRAY_SIZE(disp_cc_0_parent_data_2),
766 .flags = CLK_SET_RATE_PARENT,
767 .ops = &clk_pixel_ops,
768 },
769 };
770
771 static struct clk_rcg2 mdss_0_disp_cc_mdss_pclk1_clk_src = {
772 .cmd_rcgr = 0x80dc,
773 .mnd_width = 8,
774 .hid_width = 5,
775 .parent_map = disp_cc_0_parent_map_2,
776 .freq_tbl = ftbl_mdss_0_disp_cc_mdss_byte0_clk_src,
777 .hw_clk_ctrl = true,
778 .clkr.hw.init = &(const struct clk_init_data) {
779 .name = "mdss_0_disp_cc_mdss_pclk1_clk_src",
780 .parent_data = disp_cc_0_parent_data_2,
781 .num_parents = ARRAY_SIZE(disp_cc_0_parent_data_2),
782 .flags = CLK_SET_RATE_PARENT,
783 .ops = &clk_pixel_ops,
784 },
785 };
786
787 static struct clk_rcg2 mdss_0_disp_cc_mdss_pclk2_clk_src = {
788 .cmd_rcgr = 0x80f4,
789 .mnd_width = 8,
790 .hid_width = 5,
791 .parent_map = disp_cc_0_parent_map_2,
792 .freq_tbl = ftbl_mdss_0_disp_cc_mdss_byte0_clk_src,
793 .hw_clk_ctrl = true,
794 .clkr.hw.init = &(const struct clk_init_data) {
795 .name = "mdss_0_disp_cc_mdss_pclk2_clk_src",
796 .parent_data = disp_cc_0_parent_data_2,
797 .num_parents = ARRAY_SIZE(disp_cc_0_parent_data_2),
798 .flags = CLK_SET_RATE_PARENT,
799 .ops = &clk_pixel_ops,
800 },
801 };
802
803 static struct clk_rcg2 mdss_0_disp_cc_mdss_vsync_clk_src = {
804 .cmd_rcgr = 0x8124,
805 .mnd_width = 0,
806 .hid_width = 5,
807 .parent_map = disp_cc_0_parent_map_1,
808 .freq_tbl = ftbl_mdss_0_disp_cc_mdss_byte0_clk_src,
809 .hw_clk_ctrl = true,
810 .clkr.hw.init = &(const struct clk_init_data) {
811 .name = "mdss_0_disp_cc_mdss_vsync_clk_src",
812 .parent_data = disp_cc_0_parent_data_1,
813 .num_parents = ARRAY_SIZE(disp_cc_0_parent_data_1),
814 .flags = CLK_SET_RATE_PARENT,
815 .ops = &clk_rcg2_shared_ops,
816 },
817 };
818
819 static const struct freq_tbl ftbl_mdss_0_disp_cc_sleep_clk_src[] = {
820 F(32000, P_SLEEP_CLK, 1, 0, 0),
821 { }
822 };
823
824 static struct clk_rcg2 mdss_0_disp_cc_sleep_clk_src = {
825 .cmd_rcgr = 0xe064,
826 .mnd_width = 0,
827 .hid_width = 5,
828 .parent_map = disp_cc_0_parent_map_9,
829 .freq_tbl = ftbl_mdss_0_disp_cc_sleep_clk_src,
830 .hw_clk_ctrl = true,
831 .clkr.hw.init = &(const struct clk_init_data) {
832 .name = "mdss_0_disp_cc_sleep_clk_src",
833 .parent_data = disp_cc_0_parent_data_9,
834 .num_parents = ARRAY_SIZE(disp_cc_0_parent_data_9),
835 .flags = CLK_SET_RATE_PARENT,
836 .ops = &clk_rcg2_ops,
837 },
838 };
839
840 static struct clk_rcg2 mdss_0_disp_cc_xo_clk_src = {
841 .cmd_rcgr = 0xe044,
842 .mnd_width = 0,
843 .hid_width = 5,
844 .parent_map = disp_cc_0_parent_map_1,
845 .freq_tbl = ftbl_mdss_0_disp_cc_mdss_byte0_clk_src,
846 .hw_clk_ctrl = true,
847 .clkr.hw.init = &(const struct clk_init_data) {
848 .name = "mdss_0_disp_cc_xo_clk_src",
849 .parent_data = disp_cc_0_parent_data_1,
850 .num_parents = ARRAY_SIZE(disp_cc_0_parent_data_1),
851 .flags = CLK_SET_RATE_PARENT,
852 .ops = &clk_rcg2_ops,
853 },
854 };
855
856 static struct clk_regmap_div mdss_0_disp_cc_mdss_byte0_div_clk_src = {
857 .reg = 0x8154,
858 .shift = 0,
859 .width = 4,
860 .clkr.hw.init = &(const struct clk_init_data) {
861 .name = "mdss_0_disp_cc_mdss_byte0_div_clk_src",
862 .parent_hws = (const struct clk_hw*[]) {
863 &mdss_0_disp_cc_mdss_byte0_clk_src.clkr.hw,
864 },
865 .num_parents = 1,
866 .ops = &clk_regmap_div_ro_ops,
867 },
868 };
869
870 static struct clk_regmap_div mdss_0_disp_cc_mdss_byte1_div_clk_src = {
871 .reg = 0x8170,
872 .shift = 0,
873 .width = 4,
874 .clkr.hw.init = &(const struct clk_init_data) {
875 .name = "mdss_0_disp_cc_mdss_byte1_div_clk_src",
876 .parent_hws = (const struct clk_hw*[]) {
877 &mdss_0_disp_cc_mdss_byte1_clk_src.clkr.hw,
878 },
879 .num_parents = 1,
880 .ops = &clk_regmap_div_ro_ops,
881 },
882 };
883
884 static struct clk_regmap_div mdss_0_disp_cc_mdss_dptx0_link_div_clk_src = {
885 .reg = 0x81bc,
886 .shift = 0,
887 .width = 4,
888 .clkr.hw.init = &(const struct clk_init_data) {
889 .name = "mdss_0_disp_cc_mdss_dptx0_link_div_clk_src",
890 .parent_hws = (const struct clk_hw*[]) {
891 &mdss_0_disp_cc_mdss_dptx0_link_clk_src.clkr.hw,
892 },
893 .num_parents = 1,
894 .flags = CLK_SET_RATE_PARENT,
895 .ops = &clk_regmap_div_ro_ops,
896 },
897 };
898
899 static struct clk_regmap_div mdss_0_disp_cc_mdss_dptx1_link_div_clk_src = {
900 .reg = 0x82b0,
901 .shift = 0,
902 .width = 4,
903 .clkr.hw.init = &(const struct clk_init_data) {
904 .name = "mdss_0_disp_cc_mdss_dptx1_link_div_clk_src",
905 .parent_hws = (const struct clk_hw*[]) {
906 &mdss_0_disp_cc_mdss_dptx1_link_clk_src.clkr.hw,
907 },
908 .num_parents = 1,
909 .flags = CLK_SET_RATE_PARENT,
910 .ops = &clk_regmap_div_ro_ops,
911 },
912 };
913
914 static struct clk_regmap_div mdss_0_disp_cc_mdss_dptx2_link_div_clk_src = {
915 .reg = 0x82e4,
916 .shift = 0,
917 .width = 4,
918 .clkr.hw.init = &(const struct clk_init_data) {
919 .name = "mdss_0_disp_cc_mdss_dptx2_link_div_clk_src",
920 .parent_hws = (const struct clk_hw*[]) {
921 &mdss_0_disp_cc_mdss_dptx2_link_clk_src.clkr.hw,
922 },
923 .num_parents = 1,
924 .flags = CLK_SET_RATE_PARENT,
925 .ops = &clk_regmap_div_ro_ops,
926 },
927 };
928
929 static struct clk_regmap_div mdss_0_disp_cc_mdss_dptx3_link_div_clk_src = {
930 .reg = 0x8360,
931 .shift = 0,
932 .width = 4,
933 .clkr.hw.init = &(const struct clk_init_data) {
934 .name = "mdss_0_disp_cc_mdss_dptx3_link_div_clk_src",
935 .parent_hws = (const struct clk_hw*[]) {
936 &mdss_0_disp_cc_mdss_dptx3_link_clk_src.clkr.hw,
937 },
938 .num_parents = 1,
939 .flags = CLK_SET_RATE_PARENT,
940 .ops = &clk_regmap_div_ro_ops,
941 },
942 };
943
944 static struct clk_branch mdss_0_disp_cc_mdss_accu_shift_clk = {
945 .halt_reg = 0xe060,
946 .halt_check = BRANCH_HALT_VOTED,
947 .clkr = {
948 .enable_reg = 0xe060,
949 .enable_mask = BIT(0),
950 .hw.init = &(const struct clk_init_data) {
951 .name = "mdss_0_disp_cc_mdss_accu_shift_clk",
952 .parent_hws = (const struct clk_hw*[]) {
953 &mdss_0_disp_cc_xo_clk_src.clkr.hw,
954 },
955 .num_parents = 1,
956 .flags = CLK_SET_RATE_PARENT,
957 .ops = &clk_branch2_ops,
958 },
959 },
960 };
961
962 static struct clk_branch mdss_0_disp_cc_mdss_ahb1_clk = {
963 .halt_reg = 0xa028,
964 .halt_check = BRANCH_HALT,
965 .clkr = {
966 .enable_reg = 0xa028,
967 .enable_mask = BIT(0),
968 .hw.init = &(const struct clk_init_data) {
969 .name = "mdss_0_disp_cc_mdss_ahb1_clk",
970 .parent_hws = (const struct clk_hw*[]) {
971 &mdss_0_disp_cc_mdss_ahb_clk_src.clkr.hw,
972 },
973 .num_parents = 1,
974 .flags = CLK_SET_RATE_PARENT,
975 .ops = &clk_branch2_ops,
976 },
977 },
978 };
979
980 static struct clk_branch mdss_0_disp_cc_mdss_ahb_clk = {
981 .halt_reg = 0x80c0,
982 .halt_check = BRANCH_HALT,
983 .clkr = {
984 .enable_reg = 0x80c0,
985 .enable_mask = BIT(0),
986 .hw.init = &(const struct clk_init_data) {
987 .name = "mdss_0_disp_cc_mdss_ahb_clk",
988 .parent_hws = (const struct clk_hw*[]) {
989 &mdss_0_disp_cc_mdss_ahb_clk_src.clkr.hw,
990 },
991 .num_parents = 1,
992 .flags = CLK_SET_RATE_PARENT,
993 .ops = &clk_branch2_ops,
994 },
995 },
996 };
997
998 static struct clk_branch mdss_0_disp_cc_mdss_byte0_clk = {
999 .halt_reg = 0x8034,
1000 .halt_check = BRANCH_HALT,
1001 .clkr = {
1002 .enable_reg = 0x8034,
1003 .enable_mask = BIT(0),
1004 .hw.init = &(const struct clk_init_data) {
1005 .name = "mdss_0_disp_cc_mdss_byte0_clk",
1006 .parent_hws = (const struct clk_hw*[]) {
1007 &mdss_0_disp_cc_mdss_byte0_clk_src.clkr.hw,
1008 },
1009 .num_parents = 1,
1010 .flags = CLK_SET_RATE_PARENT,
1011 .ops = &clk_branch2_ops,
1012 },
1013 },
1014 };
1015
1016 static struct clk_branch mdss_0_disp_cc_mdss_byte0_intf_clk = {
1017 .halt_reg = 0x8038,
1018 .halt_check = BRANCH_HALT,
1019 .clkr = {
1020 .enable_reg = 0x8038,
1021 .enable_mask = BIT(0),
1022 .hw.init = &(const struct clk_init_data) {
1023 .name = "mdss_0_disp_cc_mdss_byte0_intf_clk",
1024 .parent_hws = (const struct clk_hw*[]) {
1025 &mdss_0_disp_cc_mdss_byte0_div_clk_src.clkr.hw,
1026 },
1027 .num_parents = 1,
1028 .flags = CLK_SET_RATE_PARENT,
1029 .ops = &clk_branch2_ops,
1030 },
1031 },
1032 };
1033
1034 static struct clk_branch mdss_0_disp_cc_mdss_byte1_clk = {
1035 .halt_reg = 0x803c,
1036 .halt_check = BRANCH_HALT,
1037 .clkr = {
1038 .enable_reg = 0x803c,
1039 .enable_mask = BIT(0),
1040 .hw.init = &(const struct clk_init_data) {
1041 .name = "mdss_0_disp_cc_mdss_byte1_clk",
1042 .parent_hws = (const struct clk_hw*[]) {
1043 &mdss_0_disp_cc_mdss_byte1_clk_src.clkr.hw,
1044 },
1045 .num_parents = 1,
1046 .flags = CLK_SET_RATE_PARENT,
1047 .ops = &clk_branch2_ops,
1048 },
1049 },
1050 };
1051
1052 static struct clk_branch mdss_0_disp_cc_mdss_byte1_intf_clk = {
1053 .halt_reg = 0x8040,
1054 .halt_check = BRANCH_HALT,
1055 .clkr = {
1056 .enable_reg = 0x8040,
1057 .enable_mask = BIT(0),
1058 .hw.init = &(const struct clk_init_data) {
1059 .name = "mdss_0_disp_cc_mdss_byte1_intf_clk",
1060 .parent_hws = (const struct clk_hw*[]) {
1061 &mdss_0_disp_cc_mdss_byte1_div_clk_src.clkr.hw,
1062 },
1063 .num_parents = 1,
1064 .flags = CLK_SET_RATE_PARENT,
1065 .ops = &clk_branch2_ops,
1066 },
1067 },
1068 };
1069
1070 static struct clk_branch mdss_0_disp_cc_mdss_dptx0_aux_clk = {
1071 .halt_reg = 0x806c,
1072 .halt_check = BRANCH_HALT,
1073 .clkr = {
1074 .enable_reg = 0x806c,
1075 .enable_mask = BIT(0),
1076 .hw.init = &(const struct clk_init_data) {
1077 .name = "mdss_0_disp_cc_mdss_dptx0_aux_clk",
1078 .parent_hws = (const struct clk_hw*[]) {
1079 &mdss_0_disp_cc_mdss_dptx0_aux_clk_src.clkr.hw,
1080 },
1081 .num_parents = 1,
1082 .flags = CLK_SET_RATE_PARENT,
1083 .ops = &clk_branch2_ops,
1084 },
1085 },
1086 };
1087
1088 static struct clk_branch mdss_0_disp_cc_mdss_dptx0_crypto_clk = {
1089 .halt_reg = 0x8058,
1090 .halt_check = BRANCH_HALT_VOTED,
1091 .clkr = {
1092 .enable_reg = 0x8058,
1093 .enable_mask = BIT(0),
1094 .hw.init = &(const struct clk_init_data) {
1095 .name = "mdss_0_disp_cc_mdss_dptx0_crypto_clk",
1096 .parent_hws = (const struct clk_hw*[]) {
1097 &mdss_0_disp_cc_mdss_dptx0_link_clk_src.clkr.hw,
1098 },
1099 .num_parents = 1,
1100 .flags = CLK_SET_RATE_PARENT,
1101 .ops = &clk_branch2_ops,
1102 },
1103 },
1104 };
1105
1106 static struct clk_branch mdss_0_disp_cc_mdss_dptx0_link_clk = {
1107 .halt_reg = 0x804c,
1108 .halt_check = BRANCH_HALT,
1109 .clkr = {
1110 .enable_reg = 0x804c,
1111 .enable_mask = BIT(0),
1112 .hw.init = &(const struct clk_init_data) {
1113 .name = "mdss_0_disp_cc_mdss_dptx0_link_clk",
1114 .parent_hws = (const struct clk_hw*[]) {
1115 &mdss_0_disp_cc_mdss_dptx0_link_clk_src.clkr.hw,
1116 },
1117 .num_parents = 1,
1118 .flags = CLK_SET_RATE_PARENT,
1119 .ops = &clk_branch2_ops,
1120 },
1121 },
1122 };
1123
1124 static struct clk_branch mdss_0_disp_cc_mdss_dptx0_link_intf_clk = {
1125 .halt_reg = 0x8054,
1126 .halt_check = BRANCH_HALT,
1127 .clkr = {
1128 .enable_reg = 0x8054,
1129 .enable_mask = BIT(0),
1130 .hw.init = &(const struct clk_init_data) {
1131 .name = "mdss_0_disp_cc_mdss_dptx0_link_intf_clk",
1132 .parent_hws = (const struct clk_hw*[]) {
1133 &mdss_0_disp_cc_mdss_dptx0_link_div_clk_src.clkr.hw,
1134 },
1135 .num_parents = 1,
1136 .flags = CLK_SET_RATE_PARENT,
1137 .ops = &clk_branch2_ops,
1138 },
1139 },
1140 };
1141
1142 static struct clk_branch mdss_0_disp_cc_mdss_dptx0_pixel0_clk = {
1143 .halt_reg = 0x805c,
1144 .halt_check = BRANCH_HALT,
1145 .clkr = {
1146 .enable_reg = 0x805c,
1147 .enable_mask = BIT(0),
1148 .hw.init = &(const struct clk_init_data) {
1149 .name = "mdss_0_disp_cc_mdss_dptx0_pixel0_clk",
1150 .parent_hws = (const struct clk_hw*[]) {
1151 &mdss_0_disp_cc_mdss_dptx0_pixel0_clk_src.clkr.hw,
1152 },
1153 .num_parents = 1,
1154 .flags = CLK_SET_RATE_PARENT,
1155 .ops = &clk_branch2_ops,
1156 },
1157 },
1158 };
1159
1160 static struct clk_branch mdss_0_disp_cc_mdss_dptx0_pixel1_clk = {
1161 .halt_reg = 0x8060,
1162 .halt_check = BRANCH_HALT,
1163 .clkr = {
1164 .enable_reg = 0x8060,
1165 .enable_mask = BIT(0),
1166 .hw.init = &(const struct clk_init_data) {
1167 .name = "mdss_0_disp_cc_mdss_dptx0_pixel1_clk",
1168 .parent_hws = (const struct clk_hw*[]) {
1169 &mdss_0_disp_cc_mdss_dptx0_pixel1_clk_src.clkr.hw,
1170 },
1171 .num_parents = 1,
1172 .flags = CLK_SET_RATE_PARENT,
1173 .ops = &clk_branch2_ops,
1174 },
1175 },
1176 };
1177
1178 static struct clk_branch mdss_0_disp_cc_mdss_dptx0_pixel2_clk = {
1179 .halt_reg = 0x8064,
1180 .halt_check = BRANCH_HALT,
1181 .clkr = {
1182 .enable_reg = 0x8064,
1183 .enable_mask = BIT(0),
1184 .hw.init = &(const struct clk_init_data) {
1185 .name = "mdss_0_disp_cc_mdss_dptx0_pixel2_clk",
1186 .parent_hws = (const struct clk_hw*[]) {
1187 &mdss_0_disp_cc_mdss_dptx0_pixel2_clk_src.clkr.hw,
1188 },
1189 .num_parents = 1,
1190 .flags = CLK_SET_RATE_PARENT,
1191 .ops = &clk_branch2_ops,
1192 },
1193 },
1194 };
1195
1196 static struct clk_branch mdss_0_disp_cc_mdss_dptx0_pixel3_clk = {
1197 .halt_reg = 0x8068,
1198 .halt_check = BRANCH_HALT,
1199 .clkr = {
1200 .enable_reg = 0x8068,
1201 .enable_mask = BIT(0),
1202 .hw.init = &(const struct clk_init_data) {
1203 .name = "mdss_0_disp_cc_mdss_dptx0_pixel3_clk",
1204 .parent_hws = (const struct clk_hw*[]) {
1205 &mdss_0_disp_cc_mdss_dptx0_pixel3_clk_src.clkr.hw,
1206 },
1207 .num_parents = 1,
1208 .flags = CLK_SET_RATE_PARENT,
1209 .ops = &clk_branch2_ops,
1210 },
1211 },
1212 };
1213
1214 static struct clk_branch mdss_0_disp_cc_mdss_dptx0_usb_router_link_intf_clk = {
1215 .halt_reg = 0x8050,
1216 .halt_check = BRANCH_HALT,
1217 .clkr = {
1218 .enable_reg = 0x8050,
1219 .enable_mask = BIT(0),
1220 .hw.init = &(const struct clk_init_data) {
1221 .name = "mdss_0_disp_cc_mdss_dptx0_usb_router_link_intf_clk",
1222 .parent_hws = (const struct clk_hw*[]) {
1223 &mdss_0_disp_cc_mdss_dptx0_link_div_clk_src.clkr.hw,
1224 },
1225 .num_parents = 1,
1226 .flags = CLK_SET_RATE_PARENT,
1227 .ops = &clk_branch2_ops,
1228 },
1229 },
1230 };
1231
1232 static struct clk_branch mdss_0_disp_cc_mdss_dptx1_aux_clk = {
1233 .halt_reg = 0x8090,
1234 .halt_check = BRANCH_HALT,
1235 .clkr = {
1236 .enable_reg = 0x8090,
1237 .enable_mask = BIT(0),
1238 .hw.init = &(const struct clk_init_data) {
1239 .name = "mdss_0_disp_cc_mdss_dptx1_aux_clk",
1240 .parent_hws = (const struct clk_hw*[]) {
1241 &mdss_0_disp_cc_mdss_dptx1_aux_clk_src.clkr.hw,
1242 },
1243 .num_parents = 1,
1244 .flags = CLK_SET_RATE_PARENT,
1245 .ops = &clk_branch2_ops,
1246 },
1247 },
1248 };
1249
1250 static struct clk_branch mdss_0_disp_cc_mdss_dptx1_crypto_clk = {
1251 .halt_reg = 0x808c,
1252 .halt_check = BRANCH_HALT_VOTED,
1253 .clkr = {
1254 .enable_reg = 0x808c,
1255 .enable_mask = BIT(0),
1256 .hw.init = &(const struct clk_init_data) {
1257 .name = "mdss_0_disp_cc_mdss_dptx1_crypto_clk",
1258 .parent_hws = (const struct clk_hw*[]) {
1259 &mdss_0_disp_cc_mdss_dptx1_link_clk_src.clkr.hw,
1260 },
1261 .num_parents = 1,
1262 .flags = CLK_SET_RATE_PARENT,
1263 .ops = &clk_branch2_ops,
1264 },
1265 },
1266 };
1267
1268 static struct clk_branch mdss_0_disp_cc_mdss_dptx1_link_clk = {
1269 .halt_reg = 0x8080,
1270 .halt_check = BRANCH_HALT,
1271 .clkr = {
1272 .enable_reg = 0x8080,
1273 .enable_mask = BIT(0),
1274 .hw.init = &(const struct clk_init_data) {
1275 .name = "mdss_0_disp_cc_mdss_dptx1_link_clk",
1276 .parent_hws = (const struct clk_hw*[]) {
1277 &mdss_0_disp_cc_mdss_dptx1_link_clk_src.clkr.hw,
1278 },
1279 .num_parents = 1,
1280 .flags = CLK_SET_RATE_PARENT,
1281 .ops = &clk_branch2_ops,
1282 },
1283 },
1284 };
1285
1286 static struct clk_branch mdss_0_disp_cc_mdss_dptx1_link_intf_clk = {
1287 .halt_reg = 0x8088,
1288 .halt_check = BRANCH_HALT,
1289 .clkr = {
1290 .enable_reg = 0x8088,
1291 .enable_mask = BIT(0),
1292 .hw.init = &(const struct clk_init_data) {
1293 .name = "mdss_0_disp_cc_mdss_dptx1_link_intf_clk",
1294 .parent_hws = (const struct clk_hw*[]) {
1295 &mdss_0_disp_cc_mdss_dptx1_link_div_clk_src.clkr.hw,
1296 },
1297 .num_parents = 1,
1298 .flags = CLK_SET_RATE_PARENT,
1299 .ops = &clk_branch2_ops,
1300 },
1301 },
1302 };
1303
1304 static struct clk_branch mdss_0_disp_cc_mdss_dptx1_pixel0_clk = {
1305 .halt_reg = 0x8070,
1306 .halt_check = BRANCH_HALT,
1307 .clkr = {
1308 .enable_reg = 0x8070,
1309 .enable_mask = BIT(0),
1310 .hw.init = &(const struct clk_init_data) {
1311 .name = "mdss_0_disp_cc_mdss_dptx1_pixel0_clk",
1312 .parent_hws = (const struct clk_hw*[]) {
1313 &mdss_0_disp_cc_mdss_dptx1_pixel0_clk_src.clkr.hw,
1314 },
1315 .num_parents = 1,
1316 .flags = CLK_SET_RATE_PARENT,
1317 .ops = &clk_branch2_ops,
1318 },
1319 },
1320 };
1321
1322 static struct clk_branch mdss_0_disp_cc_mdss_dptx1_pixel1_clk = {
1323 .halt_reg = 0x8074,
1324 .halt_check = BRANCH_HALT,
1325 .clkr = {
1326 .enable_reg = 0x8074,
1327 .enable_mask = BIT(0),
1328 .hw.init = &(const struct clk_init_data) {
1329 .name = "mdss_0_disp_cc_mdss_dptx1_pixel1_clk",
1330 .parent_hws = (const struct clk_hw*[]) {
1331 &mdss_0_disp_cc_mdss_dptx1_pixel1_clk_src.clkr.hw,
1332 },
1333 .num_parents = 1,
1334 .flags = CLK_SET_RATE_PARENT,
1335 .ops = &clk_branch2_ops,
1336 },
1337 },
1338 };
1339
1340 static struct clk_branch mdss_0_disp_cc_mdss_dptx1_pixel2_clk = {
1341 .halt_reg = 0x8078,
1342 .halt_check = BRANCH_HALT,
1343 .clkr = {
1344 .enable_reg = 0x8078,
1345 .enable_mask = BIT(0),
1346 .hw.init = &(const struct clk_init_data) {
1347 .name = "mdss_0_disp_cc_mdss_dptx1_pixel2_clk",
1348 .parent_hws = (const struct clk_hw*[]) {
1349 &mdss_0_disp_cc_mdss_dptx1_pixel2_clk_src.clkr.hw,
1350 },
1351 .num_parents = 1,
1352 .flags = CLK_SET_RATE_PARENT,
1353 .ops = &clk_branch2_ops,
1354 },
1355 },
1356 };
1357
1358 static struct clk_branch mdss_0_disp_cc_mdss_dptx1_pixel3_clk = {
1359 .halt_reg = 0x807c,
1360 .halt_check = BRANCH_HALT,
1361 .clkr = {
1362 .enable_reg = 0x807c,
1363 .enable_mask = BIT(0),
1364 .hw.init = &(const struct clk_init_data) {
1365 .name = "mdss_0_disp_cc_mdss_dptx1_pixel3_clk",
1366 .parent_hws = (const struct clk_hw*[]) {
1367 &mdss_0_disp_cc_mdss_dptx1_pixel3_clk_src.clkr.hw,
1368 },
1369 .num_parents = 1,
1370 .flags = CLK_SET_RATE_PARENT,
1371 .ops = &clk_branch2_ops,
1372 },
1373 },
1374 };
1375
1376 static struct clk_branch mdss_0_disp_cc_mdss_dptx1_usb_router_link_intf_clk = {
1377 .halt_reg = 0x8084,
1378 .halt_check = BRANCH_HALT,
1379 .clkr = {
1380 .enable_reg = 0x8084,
1381 .enable_mask = BIT(0),
1382 .hw.init = &(const struct clk_init_data) {
1383 .name = "mdss_0_disp_cc_mdss_dptx1_usb_router_link_intf_clk",
1384 .parent_hws = (const struct clk_hw*[]) {
1385 &mdss_0_disp_cc_mdss_dptx1_link_div_clk_src.clkr.hw,
1386 },
1387 .num_parents = 1,
1388 .flags = CLK_SET_RATE_PARENT,
1389 .ops = &clk_branch2_ops,
1390 },
1391 },
1392 };
1393
1394 static struct clk_branch mdss_0_disp_cc_mdss_dptx2_aux_clk = {
1395 .halt_reg = 0x80a8,
1396 .halt_check = BRANCH_HALT,
1397 .clkr = {
1398 .enable_reg = 0x80a8,
1399 .enable_mask = BIT(0),
1400 .hw.init = &(const struct clk_init_data) {
1401 .name = "mdss_0_disp_cc_mdss_dptx2_aux_clk",
1402 .parent_hws = (const struct clk_hw*[]) {
1403 &mdss_0_disp_cc_mdss_dptx2_aux_clk_src.clkr.hw,
1404 },
1405 .num_parents = 1,
1406 .flags = CLK_SET_RATE_PARENT,
1407 .ops = &clk_branch2_ops,
1408 },
1409 },
1410 };
1411
1412 static struct clk_branch mdss_0_disp_cc_mdss_dptx2_crypto_clk = {
1413 .halt_reg = 0x80a4,
1414 .halt_check = BRANCH_HALT_VOTED,
1415 .clkr = {
1416 .enable_reg = 0x80a4,
1417 .enable_mask = BIT(0),
1418 .hw.init = &(const struct clk_init_data) {
1419 .name = "mdss_0_disp_cc_mdss_dptx2_crypto_clk",
1420 .parent_hws = (const struct clk_hw*[]) {
1421 &mdss_0_disp_cc_mdss_dptx2_link_clk_src.clkr.hw,
1422 },
1423 .num_parents = 1,
1424 .flags = CLK_SET_RATE_PARENT,
1425 .ops = &clk_branch2_ops,
1426 },
1427 },
1428 };
1429
1430 static struct clk_branch mdss_0_disp_cc_mdss_dptx2_link_clk = {
1431 .halt_reg = 0x809c,
1432 .halt_check = BRANCH_HALT,
1433 .clkr = {
1434 .enable_reg = 0x809c,
1435 .enable_mask = BIT(0),
1436 .hw.init = &(const struct clk_init_data) {
1437 .name = "mdss_0_disp_cc_mdss_dptx2_link_clk",
1438 .parent_hws = (const struct clk_hw*[]) {
1439 &mdss_0_disp_cc_mdss_dptx2_link_clk_src.clkr.hw,
1440 },
1441 .num_parents = 1,
1442 .flags = CLK_SET_RATE_PARENT,
1443 .ops = &clk_branch2_ops,
1444 },
1445 },
1446 };
1447
1448 static struct clk_branch mdss_0_disp_cc_mdss_dptx2_link_intf_clk = {
1449 .halt_reg = 0x80a0,
1450 .halt_check = BRANCH_HALT,
1451 .clkr = {
1452 .enable_reg = 0x80a0,
1453 .enable_mask = BIT(0),
1454 .hw.init = &(const struct clk_init_data) {
1455 .name = "mdss_0_disp_cc_mdss_dptx2_link_intf_clk",
1456 .parent_hws = (const struct clk_hw*[]) {
1457 &mdss_0_disp_cc_mdss_dptx2_link_div_clk_src.clkr.hw,
1458 },
1459 .num_parents = 1,
1460 .flags = CLK_SET_RATE_PARENT,
1461 .ops = &clk_branch2_ops,
1462 },
1463 },
1464 };
1465
1466 static struct clk_branch mdss_0_disp_cc_mdss_dptx2_pixel0_clk = {
1467 .halt_reg = 0x8094,
1468 .halt_check = BRANCH_HALT,
1469 .clkr = {
1470 .enable_reg = 0x8094,
1471 .enable_mask = BIT(0),
1472 .hw.init = &(const struct clk_init_data) {
1473 .name = "mdss_0_disp_cc_mdss_dptx2_pixel0_clk",
1474 .parent_hws = (const struct clk_hw*[]) {
1475 &mdss_0_disp_cc_mdss_dptx2_pixel0_clk_src.clkr.hw,
1476 },
1477 .num_parents = 1,
1478 .flags = CLK_SET_RATE_PARENT,
1479 .ops = &clk_branch2_ops,
1480 },
1481 },
1482 };
1483
1484 static struct clk_branch mdss_0_disp_cc_mdss_dptx2_pixel1_clk = {
1485 .halt_reg = 0x8098,
1486 .halt_check = BRANCH_HALT,
1487 .clkr = {
1488 .enable_reg = 0x8098,
1489 .enable_mask = BIT(0),
1490 .hw.init = &(const struct clk_init_data) {
1491 .name = "mdss_0_disp_cc_mdss_dptx2_pixel1_clk",
1492 .parent_hws = (const struct clk_hw*[]) {
1493 &mdss_0_disp_cc_mdss_dptx2_pixel1_clk_src.clkr.hw,
1494 },
1495 .num_parents = 1,
1496 .flags = CLK_SET_RATE_PARENT,
1497 .ops = &clk_branch2_ops,
1498 },
1499 },
1500 };
1501
1502 static struct clk_branch mdss_0_disp_cc_mdss_dptx3_aux_clk = {
1503 .halt_reg = 0x80b8,
1504 .halt_check = BRANCH_HALT,
1505 .clkr = {
1506 .enable_reg = 0x80b8,
1507 .enable_mask = BIT(0),
1508 .hw.init = &(const struct clk_init_data) {
1509 .name = "mdss_0_disp_cc_mdss_dptx3_aux_clk",
1510 .parent_hws = (const struct clk_hw*[]) {
1511 &mdss_0_disp_cc_mdss_dptx3_aux_clk_src.clkr.hw,
1512 },
1513 .num_parents = 1,
1514 .flags = CLK_SET_RATE_PARENT,
1515 .ops = &clk_branch2_ops,
1516 },
1517 },
1518 };
1519
1520 static struct clk_branch mdss_0_disp_cc_mdss_dptx3_crypto_clk = {
1521 .halt_reg = 0x80bc,
1522 .halt_check = BRANCH_HALT_VOTED,
1523 .clkr = {
1524 .enable_reg = 0x80bc,
1525 .enable_mask = BIT(0),
1526 .hw.init = &(const struct clk_init_data) {
1527 .name = "mdss_0_disp_cc_mdss_dptx3_crypto_clk",
1528 .parent_hws = (const struct clk_hw*[]) {
1529 &mdss_0_disp_cc_mdss_dptx3_link_clk_src.clkr.hw,
1530 },
1531 .num_parents = 1,
1532 .flags = CLK_SET_RATE_PARENT,
1533 .ops = &clk_branch2_ops,
1534 },
1535 },
1536 };
1537
1538 static struct clk_branch mdss_0_disp_cc_mdss_dptx3_link_clk = {
1539 .halt_reg = 0x80b0,
1540 .halt_check = BRANCH_HALT,
1541 .clkr = {
1542 .enable_reg = 0x80b0,
1543 .enable_mask = BIT(0),
1544 .hw.init = &(const struct clk_init_data) {
1545 .name = "mdss_0_disp_cc_mdss_dptx3_link_clk",
1546 .parent_hws = (const struct clk_hw*[]) {
1547 &mdss_0_disp_cc_mdss_dptx3_link_clk_src.clkr.hw,
1548 },
1549 .num_parents = 1,
1550 .flags = CLK_SET_RATE_PARENT,
1551 .ops = &clk_branch2_ops,
1552 },
1553 },
1554 };
1555
1556 static struct clk_branch mdss_0_disp_cc_mdss_dptx3_link_intf_clk = {
1557 .halt_reg = 0x80b4,
1558 .halt_check = BRANCH_HALT,
1559 .clkr = {
1560 .enable_reg = 0x80b4,
1561 .enable_mask = BIT(0),
1562 .hw.init = &(const struct clk_init_data) {
1563 .name = "mdss_0_disp_cc_mdss_dptx3_link_intf_clk",
1564 .parent_hws = (const struct clk_hw*[]) {
1565 &mdss_0_disp_cc_mdss_dptx3_link_div_clk_src.clkr.hw,
1566 },
1567 .num_parents = 1,
1568 .flags = CLK_SET_RATE_PARENT,
1569 .ops = &clk_branch2_ops,
1570 },
1571 },
1572 };
1573
1574 static struct clk_branch mdss_0_disp_cc_mdss_dptx3_pixel0_clk = {
1575 .halt_reg = 0x80ac,
1576 .halt_check = BRANCH_HALT,
1577 .clkr = {
1578 .enable_reg = 0x80ac,
1579 .enable_mask = BIT(0),
1580 .hw.init = &(const struct clk_init_data) {
1581 .name = "mdss_0_disp_cc_mdss_dptx3_pixel0_clk",
1582 .parent_hws = (const struct clk_hw*[]) {
1583 &mdss_0_disp_cc_mdss_dptx3_pixel0_clk_src.clkr.hw,
1584 },
1585 .num_parents = 1,
1586 .flags = CLK_SET_RATE_PARENT,
1587 .ops = &clk_branch2_ops,
1588 },
1589 },
1590 };
1591
1592 static struct clk_branch mdss_0_disp_cc_mdss_esc0_clk = {
1593 .halt_reg = 0x8044,
1594 .halt_check = BRANCH_HALT,
1595 .clkr = {
1596 .enable_reg = 0x8044,
1597 .enable_mask = BIT(0),
1598 .hw.init = &(const struct clk_init_data) {
1599 .name = "mdss_0_disp_cc_mdss_esc0_clk",
1600 .parent_hws = (const struct clk_hw*[]) {
1601 &mdss_0_disp_cc_mdss_esc0_clk_src.clkr.hw,
1602 },
1603 .num_parents = 1,
1604 .flags = CLK_SET_RATE_PARENT,
1605 .ops = &clk_branch2_ops,
1606 },
1607 },
1608 };
1609
1610 static struct clk_branch mdss_0_disp_cc_mdss_esc1_clk = {
1611 .halt_reg = 0x8048,
1612 .halt_check = BRANCH_HALT,
1613 .clkr = {
1614 .enable_reg = 0x8048,
1615 .enable_mask = BIT(0),
1616 .hw.init = &(const struct clk_init_data) {
1617 .name = "mdss_0_disp_cc_mdss_esc1_clk",
1618 .parent_hws = (const struct clk_hw*[]) {
1619 &mdss_0_disp_cc_mdss_esc1_clk_src.clkr.hw,
1620 },
1621 .num_parents = 1,
1622 .flags = CLK_SET_RATE_PARENT,
1623 .ops = &clk_branch2_ops,
1624 },
1625 },
1626 };
1627
1628 static struct clk_branch mdss_0_disp_cc_mdss_mdp1_clk = {
1629 .halt_reg = 0xa004,
1630 .halt_check = BRANCH_HALT,
1631 .clkr = {
1632 .enable_reg = 0xa004,
1633 .enable_mask = BIT(0),
1634 .hw.init = &(const struct clk_init_data) {
1635 .name = "mdss_0_disp_cc_mdss_mdp1_clk",
1636 .parent_hws = (const struct clk_hw*[]) {
1637 &mdss_0_disp_cc_mdss_mdp_clk_src.clkr.hw,
1638 },
1639 .num_parents = 1,
1640 .flags = CLK_SET_RATE_PARENT,
1641 .ops = &clk_branch2_ops,
1642 },
1643 },
1644 };
1645
1646 static struct clk_branch mdss_0_disp_cc_mdss_mdp_clk = {
1647 .halt_reg = 0x8010,
1648 .halt_check = BRANCH_HALT,
1649 .clkr = {
1650 .enable_reg = 0x8010,
1651 .enable_mask = BIT(0),
1652 .hw.init = &(const struct clk_init_data) {
1653 .name = "mdss_0_disp_cc_mdss_mdp_clk",
1654 .parent_hws = (const struct clk_hw*[]) {
1655 &mdss_0_disp_cc_mdss_mdp_clk_src.clkr.hw,
1656 },
1657 .num_parents = 1,
1658 .flags = CLK_SET_RATE_PARENT,
1659 .ops = &clk_branch2_ops,
1660 },
1661 },
1662 };
1663
1664 static struct clk_branch mdss_0_disp_cc_mdss_mdp_lut1_clk = {
1665 .halt_reg = 0xa014,
1666 .halt_check = BRANCH_HALT_VOTED,
1667 .clkr = {
1668 .enable_reg = 0xa014,
1669 .enable_mask = BIT(0),
1670 .hw.init = &(const struct clk_init_data) {
1671 .name = "mdss_0_disp_cc_mdss_mdp_lut1_clk",
1672 .parent_hws = (const struct clk_hw*[]) {
1673 &mdss_0_disp_cc_mdss_mdp_clk_src.clkr.hw,
1674 },
1675 .num_parents = 1,
1676 .flags = CLK_SET_RATE_PARENT,
1677 .ops = &clk_branch2_ops,
1678 },
1679 },
1680 };
1681
1682 static struct clk_branch mdss_0_disp_cc_mdss_mdp_lut_clk = {
1683 .halt_reg = 0x8020,
1684 .halt_check = BRANCH_HALT_VOTED,
1685 .clkr = {
1686 .enable_reg = 0x8020,
1687 .enable_mask = BIT(0),
1688 .hw.init = &(const struct clk_init_data) {
1689 .name = "mdss_0_disp_cc_mdss_mdp_lut_clk",
1690 .parent_hws = (const struct clk_hw*[]) {
1691 &mdss_0_disp_cc_mdss_mdp_clk_src.clkr.hw,
1692 },
1693 .num_parents = 1,
1694 .flags = CLK_SET_RATE_PARENT,
1695 .ops = &clk_branch2_ops,
1696 },
1697 },
1698 };
1699
1700 static struct clk_branch mdss_0_disp_cc_mdss_non_gdsc_ahb_clk = {
1701 .halt_reg = 0xc004,
1702 .halt_check = BRANCH_HALT_VOTED,
1703 .clkr = {
1704 .enable_reg = 0xc004,
1705 .enable_mask = BIT(0),
1706 .hw.init = &(const struct clk_init_data) {
1707 .name = "mdss_0_disp_cc_mdss_non_gdsc_ahb_clk",
1708 .parent_hws = (const struct clk_hw*[]) {
1709 &mdss_0_disp_cc_mdss_ahb_clk_src.clkr.hw,
1710 },
1711 .num_parents = 1,
1712 .flags = CLK_SET_RATE_PARENT,
1713 .ops = &clk_branch2_ops,
1714 },
1715 },
1716 };
1717
1718 static struct clk_branch mdss_0_disp_cc_mdss_pclk0_clk = {
1719 .halt_reg = 0x8004,
1720 .halt_check = BRANCH_HALT,
1721 .clkr = {
1722 .enable_reg = 0x8004,
1723 .enable_mask = BIT(0),
1724 .hw.init = &(const struct clk_init_data) {
1725 .name = "mdss_0_disp_cc_mdss_pclk0_clk",
1726 .parent_hws = (const struct clk_hw*[]) {
1727 &mdss_0_disp_cc_mdss_pclk0_clk_src.clkr.hw,
1728 },
1729 .num_parents = 1,
1730 .flags = CLK_SET_RATE_PARENT,
1731 .ops = &clk_branch2_ops,
1732 },
1733 },
1734 };
1735
1736 static struct clk_branch mdss_0_disp_cc_mdss_pclk1_clk = {
1737 .halt_reg = 0x8008,
1738 .halt_check = BRANCH_HALT,
1739 .clkr = {
1740 .enable_reg = 0x8008,
1741 .enable_mask = BIT(0),
1742 .hw.init = &(const struct clk_init_data) {
1743 .name = "mdss_0_disp_cc_mdss_pclk1_clk",
1744 .parent_hws = (const struct clk_hw*[]) {
1745 &mdss_0_disp_cc_mdss_pclk1_clk_src.clkr.hw,
1746 },
1747 .num_parents = 1,
1748 .flags = CLK_SET_RATE_PARENT,
1749 .ops = &clk_branch2_ops,
1750 },
1751 },
1752 };
1753
1754 static struct clk_branch mdss_0_disp_cc_mdss_pclk2_clk = {
1755 .halt_reg = 0x800c,
1756 .halt_check = BRANCH_HALT,
1757 .clkr = {
1758 .enable_reg = 0x800c,
1759 .enable_mask = BIT(0),
1760 .hw.init = &(const struct clk_init_data) {
1761 .name = "mdss_0_disp_cc_mdss_pclk2_clk",
1762 .parent_hws = (const struct clk_hw*[]) {
1763 &mdss_0_disp_cc_mdss_pclk2_clk_src.clkr.hw,
1764 },
1765 .num_parents = 1,
1766 .flags = CLK_SET_RATE_PARENT,
1767 .ops = &clk_branch2_ops,
1768 },
1769 },
1770 };
1771
1772 static struct clk_branch mdss_0_disp_cc_mdss_vsync1_clk = {
1773 .halt_reg = 0xa024,
1774 .halt_check = BRANCH_HALT,
1775 .clkr = {
1776 .enable_reg = 0xa024,
1777 .enable_mask = BIT(0),
1778 .hw.init = &(const struct clk_init_data) {
1779 .name = "mdss_0_disp_cc_mdss_vsync1_clk",
1780 .parent_hws = (const struct clk_hw*[]) {
1781 &mdss_0_disp_cc_mdss_vsync_clk_src.clkr.hw,
1782 },
1783 .num_parents = 1,
1784 .flags = CLK_SET_RATE_PARENT,
1785 .ops = &clk_branch2_ops,
1786 },
1787 },
1788 };
1789
1790 static struct clk_branch mdss_0_disp_cc_mdss_vsync_clk = {
1791 .halt_reg = 0x8030,
1792 .halt_check = BRANCH_HALT,
1793 .clkr = {
1794 .enable_reg = 0x8030,
1795 .enable_mask = BIT(0),
1796 .hw.init = &(const struct clk_init_data) {
1797 .name = "mdss_0_disp_cc_mdss_vsync_clk",
1798 .parent_hws = (const struct clk_hw*[]) {
1799 &mdss_0_disp_cc_mdss_vsync_clk_src.clkr.hw,
1800 },
1801 .num_parents = 1,
1802 .flags = CLK_SET_RATE_PARENT,
1803 .ops = &clk_branch2_ops,
1804 },
1805 },
1806 };
1807
1808 static struct gdsc mdss_0_disp_cc_mdss_core_gdsc = {
1809 .gdscr = 0x9000,
1810 .en_rest_wait_val = 0x2,
1811 .en_few_wait_val = 0x2,
1812 .clk_dis_wait_val = 0xf,
1813 .pd = {
1814 .name = "mdss_0_disp_cc_mdss_core_gdsc",
1815 },
1816 .pwrsts = PWRSTS_OFF_ON,
1817 .flags = HW_CTRL_TRIGGER | POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
1818 };
1819
1820 static struct gdsc mdss_0_disp_cc_mdss_core_int2_gdsc = {
1821 .gdscr = 0xb000,
1822 .en_rest_wait_val = 0x2,
1823 .en_few_wait_val = 0x2,
1824 .clk_dis_wait_val = 0xf,
1825 .pd = {
1826 .name = "mdss_0_disp_cc_mdss_core_int2_gdsc",
1827 },
1828 .pwrsts = PWRSTS_OFF_ON,
1829 .flags = HW_CTRL_TRIGGER | POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
1830 };
1831
1832 static struct clk_regmap *disp_cc_0_nord_clocks[] = {
1833 [MDSS_DISP_CC_MDSS_ACCU_SHIFT_CLK] = &mdss_0_disp_cc_mdss_accu_shift_clk.clkr,
1834 [MDSS_DISP_CC_MDSS_AHB1_CLK] = &mdss_0_disp_cc_mdss_ahb1_clk.clkr,
1835 [MDSS_DISP_CC_MDSS_AHB_CLK] = &mdss_0_disp_cc_mdss_ahb_clk.clkr,
1836 [MDSS_DISP_CC_MDSS_AHB_CLK_SRC] = &mdss_0_disp_cc_mdss_ahb_clk_src.clkr,
1837 [MDSS_DISP_CC_MDSS_BYTE0_CLK] = &mdss_0_disp_cc_mdss_byte0_clk.clkr,
1838 [MDSS_DISP_CC_MDSS_BYTE0_CLK_SRC] = &mdss_0_disp_cc_mdss_byte0_clk_src.clkr,
1839 [MDSS_DISP_CC_MDSS_BYTE0_DIV_CLK_SRC] = &mdss_0_disp_cc_mdss_byte0_div_clk_src.clkr,
1840 [MDSS_DISP_CC_MDSS_BYTE0_INTF_CLK] = &mdss_0_disp_cc_mdss_byte0_intf_clk.clkr,
1841 [MDSS_DISP_CC_MDSS_BYTE1_CLK] = &mdss_0_disp_cc_mdss_byte1_clk.clkr,
1842 [MDSS_DISP_CC_MDSS_BYTE1_CLK_SRC] = &mdss_0_disp_cc_mdss_byte1_clk_src.clkr,
1843 [MDSS_DISP_CC_MDSS_BYTE1_DIV_CLK_SRC] = &mdss_0_disp_cc_mdss_byte1_div_clk_src.clkr,
1844 [MDSS_DISP_CC_MDSS_BYTE1_INTF_CLK] = &mdss_0_disp_cc_mdss_byte1_intf_clk.clkr,
1845 [MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK] = &mdss_0_disp_cc_mdss_dptx0_aux_clk.clkr,
1846 [MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK_SRC] = &mdss_0_disp_cc_mdss_dptx0_aux_clk_src.clkr,
1847 [MDSS_DISP_CC_MDSS_DPTX0_CRYPTO_CLK] = &mdss_0_disp_cc_mdss_dptx0_crypto_clk.clkr,
1848 [MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK] = &mdss_0_disp_cc_mdss_dptx0_link_clk.clkr,
1849 [MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK_SRC] = &mdss_0_disp_cc_mdss_dptx0_link_clk_src.clkr,
1850 [MDSS_DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC] =
1851 &mdss_0_disp_cc_mdss_dptx0_link_div_clk_src.clkr,
1852 [MDSS_DISP_CC_MDSS_DPTX0_LINK_INTF_CLK] = &mdss_0_disp_cc_mdss_dptx0_link_intf_clk.clkr,
1853 [MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK] = &mdss_0_disp_cc_mdss_dptx0_pixel0_clk.clkr,
1854 [MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC] = &mdss_0_disp_cc_mdss_dptx0_pixel0_clk_src.clkr,
1855 [MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK] = &mdss_0_disp_cc_mdss_dptx0_pixel1_clk.clkr,
1856 [MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC] = &mdss_0_disp_cc_mdss_dptx0_pixel1_clk_src.clkr,
1857 [MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK] = &mdss_0_disp_cc_mdss_dptx0_pixel2_clk.clkr,
1858 [MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK_SRC] = &mdss_0_disp_cc_mdss_dptx0_pixel2_clk_src.clkr,
1859 [MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK] = &mdss_0_disp_cc_mdss_dptx0_pixel3_clk.clkr,
1860 [MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK_SRC] = &mdss_0_disp_cc_mdss_dptx0_pixel3_clk_src.clkr,
1861 [MDSS_DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK] =
1862 &mdss_0_disp_cc_mdss_dptx0_usb_router_link_intf_clk.clkr,
1863 [MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK] = &mdss_0_disp_cc_mdss_dptx1_aux_clk.clkr,
1864 [MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK_SRC] = &mdss_0_disp_cc_mdss_dptx1_aux_clk_src.clkr,
1865 [MDSS_DISP_CC_MDSS_DPTX1_CRYPTO_CLK] = &mdss_0_disp_cc_mdss_dptx1_crypto_clk.clkr,
1866 [MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK] = &mdss_0_disp_cc_mdss_dptx1_link_clk.clkr,
1867 [MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK_SRC] = &mdss_0_disp_cc_mdss_dptx1_link_clk_src.clkr,
1868 [MDSS_DISP_CC_MDSS_DPTX1_LINK_DIV_CLK_SRC] =
1869 &mdss_0_disp_cc_mdss_dptx1_link_div_clk_src.clkr,
1870 [MDSS_DISP_CC_MDSS_DPTX1_LINK_INTF_CLK] = &mdss_0_disp_cc_mdss_dptx1_link_intf_clk.clkr,
1871 [MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK] = &mdss_0_disp_cc_mdss_dptx1_pixel0_clk.clkr,
1872 [MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC] = &mdss_0_disp_cc_mdss_dptx1_pixel0_clk_src.clkr,
1873 [MDSS_DISP_CC_MDSS_DPTX1_PIXEL1_CLK] = &mdss_0_disp_cc_mdss_dptx1_pixel1_clk.clkr,
1874 [MDSS_DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC] = &mdss_0_disp_cc_mdss_dptx1_pixel1_clk_src.clkr,
1875 [MDSS_DISP_CC_MDSS_DPTX1_PIXEL2_CLK] = &mdss_0_disp_cc_mdss_dptx1_pixel2_clk.clkr,
1876 [MDSS_DISP_CC_MDSS_DPTX1_PIXEL2_CLK_SRC] = &mdss_0_disp_cc_mdss_dptx1_pixel2_clk_src.clkr,
1877 [MDSS_DISP_CC_MDSS_DPTX1_PIXEL3_CLK] = &mdss_0_disp_cc_mdss_dptx1_pixel3_clk.clkr,
1878 [MDSS_DISP_CC_MDSS_DPTX1_PIXEL3_CLK_SRC] = &mdss_0_disp_cc_mdss_dptx1_pixel3_clk_src.clkr,
1879 [MDSS_DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INTF_CLK] =
1880 &mdss_0_disp_cc_mdss_dptx1_usb_router_link_intf_clk.clkr,
1881 [MDSS_DISP_CC_MDSS_DPTX2_AUX_CLK] = &mdss_0_disp_cc_mdss_dptx2_aux_clk.clkr,
1882 [MDSS_DISP_CC_MDSS_DPTX2_AUX_CLK_SRC] = &mdss_0_disp_cc_mdss_dptx2_aux_clk_src.clkr,
1883 [MDSS_DISP_CC_MDSS_DPTX2_CRYPTO_CLK] = &mdss_0_disp_cc_mdss_dptx2_crypto_clk.clkr,
1884 [MDSS_DISP_CC_MDSS_DPTX2_LINK_CLK] = &mdss_0_disp_cc_mdss_dptx2_link_clk.clkr,
1885 [MDSS_DISP_CC_MDSS_DPTX2_LINK_CLK_SRC] = &mdss_0_disp_cc_mdss_dptx2_link_clk_src.clkr,
1886 [MDSS_DISP_CC_MDSS_DPTX2_LINK_DIV_CLK_SRC] =
1887 &mdss_0_disp_cc_mdss_dptx2_link_div_clk_src.clkr,
1888 [MDSS_DISP_CC_MDSS_DPTX2_LINK_INTF_CLK] = &mdss_0_disp_cc_mdss_dptx2_link_intf_clk.clkr,
1889 [MDSS_DISP_CC_MDSS_DPTX2_PIXEL0_CLK] = &mdss_0_disp_cc_mdss_dptx2_pixel0_clk.clkr,
1890 [MDSS_DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC] = &mdss_0_disp_cc_mdss_dptx2_pixel0_clk_src.clkr,
1891 [MDSS_DISP_CC_MDSS_DPTX2_PIXEL1_CLK] = &mdss_0_disp_cc_mdss_dptx2_pixel1_clk.clkr,
1892 [MDSS_DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC] = &mdss_0_disp_cc_mdss_dptx2_pixel1_clk_src.clkr,
1893 [MDSS_DISP_CC_MDSS_DPTX3_AUX_CLK] = &mdss_0_disp_cc_mdss_dptx3_aux_clk.clkr,
1894 [MDSS_DISP_CC_MDSS_DPTX3_AUX_CLK_SRC] = &mdss_0_disp_cc_mdss_dptx3_aux_clk_src.clkr,
1895 [MDSS_DISP_CC_MDSS_DPTX3_CRYPTO_CLK] = &mdss_0_disp_cc_mdss_dptx3_crypto_clk.clkr,
1896 [MDSS_DISP_CC_MDSS_DPTX3_LINK_CLK] = &mdss_0_disp_cc_mdss_dptx3_link_clk.clkr,
1897 [MDSS_DISP_CC_MDSS_DPTX3_LINK_CLK_SRC] = &mdss_0_disp_cc_mdss_dptx3_link_clk_src.clkr,
1898 [MDSS_DISP_CC_MDSS_DPTX3_LINK_DIV_CLK_SRC] =
1899 &mdss_0_disp_cc_mdss_dptx3_link_div_clk_src.clkr,
1900 [MDSS_DISP_CC_MDSS_DPTX3_LINK_INTF_CLK] = &mdss_0_disp_cc_mdss_dptx3_link_intf_clk.clkr,
1901 [MDSS_DISP_CC_MDSS_DPTX3_PIXEL0_CLK] = &mdss_0_disp_cc_mdss_dptx3_pixel0_clk.clkr,
1902 [MDSS_DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC] = &mdss_0_disp_cc_mdss_dptx3_pixel0_clk_src.clkr,
1903 [MDSS_DISP_CC_MDSS_ESC0_CLK] = &mdss_0_disp_cc_mdss_esc0_clk.clkr,
1904 [MDSS_DISP_CC_MDSS_ESC0_CLK_SRC] = &mdss_0_disp_cc_mdss_esc0_clk_src.clkr,
1905 [MDSS_DISP_CC_MDSS_ESC1_CLK] = &mdss_0_disp_cc_mdss_esc1_clk.clkr,
1906 [MDSS_DISP_CC_MDSS_ESC1_CLK_SRC] = &mdss_0_disp_cc_mdss_esc1_clk_src.clkr,
1907 [MDSS_DISP_CC_MDSS_MDP1_CLK] = &mdss_0_disp_cc_mdss_mdp1_clk.clkr,
1908 [MDSS_DISP_CC_MDSS_MDP_CLK] = &mdss_0_disp_cc_mdss_mdp_clk.clkr,
1909 [MDSS_DISP_CC_MDSS_MDP_CLK_SRC] = &mdss_0_disp_cc_mdss_mdp_clk_src.clkr,
1910 [MDSS_DISP_CC_MDSS_MDP_LUT1_CLK] = &mdss_0_disp_cc_mdss_mdp_lut1_clk.clkr,
1911 [MDSS_DISP_CC_MDSS_MDP_LUT_CLK] = &mdss_0_disp_cc_mdss_mdp_lut_clk.clkr,
1912 [MDSS_DISP_CC_MDSS_NON_GDSC_AHB_CLK] = &mdss_0_disp_cc_mdss_non_gdsc_ahb_clk.clkr,
1913 [MDSS_DISP_CC_MDSS_PCLK0_CLK] = &mdss_0_disp_cc_mdss_pclk0_clk.clkr,
1914 [MDSS_DISP_CC_MDSS_PCLK0_CLK_SRC] = &mdss_0_disp_cc_mdss_pclk0_clk_src.clkr,
1915 [MDSS_DISP_CC_MDSS_PCLK1_CLK] = &mdss_0_disp_cc_mdss_pclk1_clk.clkr,
1916 [MDSS_DISP_CC_MDSS_PCLK1_CLK_SRC] = &mdss_0_disp_cc_mdss_pclk1_clk_src.clkr,
1917 [MDSS_DISP_CC_MDSS_PCLK2_CLK] = &mdss_0_disp_cc_mdss_pclk2_clk.clkr,
1918 [MDSS_DISP_CC_MDSS_PCLK2_CLK_SRC] = &mdss_0_disp_cc_mdss_pclk2_clk_src.clkr,
1919 [MDSS_DISP_CC_MDSS_VSYNC1_CLK] = &mdss_0_disp_cc_mdss_vsync1_clk.clkr,
1920 [MDSS_DISP_CC_MDSS_VSYNC_CLK] = &mdss_0_disp_cc_mdss_vsync_clk.clkr,
1921 [MDSS_DISP_CC_MDSS_VSYNC_CLK_SRC] = &mdss_0_disp_cc_mdss_vsync_clk_src.clkr,
1922 [MDSS_DISP_CC_PLL0] = &mdss_0_disp_cc_pll0.clkr,
1923 [MDSS_DISP_CC_PLL1] = &mdss_0_disp_cc_pll1.clkr,
1924 [MDSS_DISP_CC_PLL2] = &mdss_0_disp_cc_pll2.clkr,
1925 [MDSS_DISP_CC_PLL3] = &mdss_0_disp_cc_pll3.clkr,
1926 [MDSS_DISP_CC_SLEEP_CLK_SRC] = &mdss_0_disp_cc_sleep_clk_src.clkr,
1927 [MDSS_DISP_CC_XO_CLK_SRC] = &mdss_0_disp_cc_xo_clk_src.clkr,
1928 };
1929
1930 static struct gdsc *disp_cc_0_nord_gdscs[] = {
1931 [MDSS_DISP_CC_MDSS_CORE_GDSC] = &mdss_0_disp_cc_mdss_core_gdsc,
1932 [MDSS_DISP_CC_MDSS_CORE_INT2_GDSC] = &mdss_0_disp_cc_mdss_core_int2_gdsc,
1933 };
1934
1935 static const struct qcom_reset_map disp_cc_0_nord_resets[] = {
1936 [MDSS_DISP_CC_MDSS_CORE_BCR] = { 0x8000 },
1937 [MDSS_DISP_CC_MDSS_CORE_INT2_BCR] = { 0xa000 },
1938 [MDSS_DISP_CC_MDSS_RSCC_BCR] = { 0xc000 },
1939 };
1940
1941 static struct clk_alpha_pll *disp_cc_0_nord_plls[] = {
1942 &mdss_0_disp_cc_pll0,
1943 &mdss_0_disp_cc_pll1,
1944 &mdss_0_disp_cc_pll2,
1945 &mdss_0_disp_cc_pll3,
1946 };
1947
1948 static const u32 disp_cc_0_nord_critical_cbcrs[] = {
1949 0xc00c, /* MDSS_DISP_CC_RSCC_AHB_CLK */
1950 0xc008, /* MDSS_DISP_CC_RSCC_VSYNC_CLK */
1951 0xe07c, /* MDSS_DISP_CC_SLEEP_CLK */
1952 0xe05c, /* MDSS_DISP_CC_XO_CLK */
1953 };
1954
1955 static const struct regmap_config disp_cc_0_nord_regmap_config = {
1956 .reg_bits = 32,
1957 .reg_stride = 4,
1958 .val_bits = 32,
1959 .max_register = 0x1a00c,
1960 .fast_io = true,
1961 };
1962
1963 static const struct qcom_cc_driver_data disp_cc_0_nord_driver_data = {
1964 .alpha_plls = disp_cc_0_nord_plls,
1965 .num_alpha_plls = ARRAY_SIZE(disp_cc_0_nord_plls),
1966 .clk_cbcrs = disp_cc_0_nord_critical_cbcrs,
1967 .num_clk_cbcrs = ARRAY_SIZE(disp_cc_0_nord_critical_cbcrs),
1968 };
1969
1970 static const struct qcom_cc_desc disp_cc_0_nord_desc = {
1971 .config = &disp_cc_0_nord_regmap_config,
1972 .clks = disp_cc_0_nord_clocks,
1973 .num_clks = ARRAY_SIZE(disp_cc_0_nord_clocks),
1974 .resets = disp_cc_0_nord_resets,
1975 .num_resets = ARRAY_SIZE(disp_cc_0_nord_resets),
1976 .gdscs = disp_cc_0_nord_gdscs,
1977 .num_gdscs = ARRAY_SIZE(disp_cc_0_nord_gdscs),
1978 .use_rpm = true,
1979 .driver_data = &disp_cc_0_nord_driver_data,
1980 };
1981
1982 static const struct of_device_id disp_cc_0_nord_match_table[] = {
1983 { .compatible = "qcom,nord-dispcc0" },
1984 { }
1985 };
1986 MODULE_DEVICE_TABLE(of, disp_cc_0_nord_match_table);
1987
disp_cc_0_nord_probe(struct platform_device * pdev)1988 static int disp_cc_0_nord_probe(struct platform_device *pdev)
1989 {
1990 return qcom_cc_probe(pdev, &disp_cc_0_nord_desc);
1991 }
1992
1993 static struct platform_driver disp_cc_0_nord_driver = {
1994 .probe = disp_cc_0_nord_probe,
1995 .driver = {
1996 .name = "dispcc0-nord",
1997 .of_match_table = disp_cc_0_nord_match_table,
1998 },
1999 };
2000
2001 module_platform_driver(disp_cc_0_nord_driver);
2002
2003 MODULE_DESCRIPTION("QTI DISPCC0 NORD Driver");
2004 MODULE_LICENSE("GPL");
2005