1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 4 */ 5 6 #include <linux/clk-provider.h> 7 #include <linux/mod_devicetable.h> 8 #include <linux/module.h> 9 #include <linux/platform_device.h> 10 #include <linux/regmap.h> 11 12 #include <dt-bindings/clock/qcom,kaanapali-dispcc.h> 13 14 #include "clk-alpha-pll.h" 15 #include "clk-branch.h" 16 #include "clk-pll.h" 17 #include "clk-rcg.h" 18 #include "clk-regmap.h" 19 #include "clk-regmap-divider.h" 20 #include "clk-regmap-mux.h" 21 #include "common.h" 22 #include "gdsc.h" 23 #include "reset.h" 24 25 #define DISP_CC_MISC_CMD 0xF000 26 27 enum { 28 DT_BI_TCXO, 29 DT_BI_TCXO_AO, 30 DT_AHB_CLK, 31 DT_SLEEP_CLK, 32 DT_DP0_PHY_PLL_LINK_CLK, 33 DT_DP0_PHY_PLL_VCO_DIV_CLK, 34 DT_DP1_PHY_PLL_LINK_CLK, 35 DT_DP1_PHY_PLL_VCO_DIV_CLK, 36 DT_DP2_PHY_PLL_LINK_CLK, 37 DT_DP2_PHY_PLL_VCO_DIV_CLK, 38 DT_DP3_PHY_PLL_LINK_CLK, 39 DT_DP3_PHY_PLL_VCO_DIV_CLK, 40 DT_DSI0_PHY_PLL_OUT_BYTECLK, 41 DT_DSI0_PHY_PLL_OUT_DSICLK, 42 DT_DSI1_PHY_PLL_OUT_BYTECLK, 43 DT_DSI1_PHY_PLL_OUT_DSICLK, 44 }; 45 46 enum { 47 P_BI_TCXO, 48 P_DISP_CC_PLL0_OUT_MAIN, 49 P_DISP_CC_PLL1_OUT_EVEN, 50 P_DISP_CC_PLL1_OUT_MAIN, 51 P_DISP_CC_PLL2_OUT_MAIN, 52 P_DP0_PHY_PLL_LINK_CLK, 53 P_DP0_PHY_PLL_VCO_DIV_CLK, 54 P_DP1_PHY_PLL_LINK_CLK, 55 P_DP1_PHY_PLL_VCO_DIV_CLK, 56 P_DP2_PHY_PLL_LINK_CLK, 57 P_DP2_PHY_PLL_VCO_DIV_CLK, 58 P_DP3_PHY_PLL_LINK_CLK, 59 P_DP3_PHY_PLL_VCO_DIV_CLK, 60 P_DSI0_PHY_PLL_OUT_BYTECLK, 61 P_DSI0_PHY_PLL_OUT_DSICLK, 62 P_DSI1_PHY_PLL_OUT_BYTECLK, 63 P_DSI1_PHY_PLL_OUT_DSICLK, 64 }; 65 66 static const struct pll_vco pongo_eko_t_vco[] = { 67 { 38400000, 153600000, 0 }, 68 }; 69 70 static const struct pll_vco taycan_eko_t_vco[] = { 71 { 249600000, 2500000000, 0 }, 72 }; 73 74 /* 257.142858 MHz Configuration */ 75 static const struct alpha_pll_config disp_cc_pll0_config = { 76 .l = 0xd, 77 .cal_l = 0x48, 78 .alpha = 0x6492, 79 .config_ctl_val = 0x25c400e7, 80 .config_ctl_hi_val = 0x0a8062e0, 81 .config_ctl_hi1_val = 0xf51dea20, 82 .user_ctl_val = 0x00000008, 83 .user_ctl_hi_val = 0x00000002, 84 }; 85 86 static struct clk_alpha_pll disp_cc_pll0 = { 87 .offset = 0x0, 88 .config = &disp_cc_pll0_config, 89 .vco_table = taycan_eko_t_vco, 90 .num_vco = ARRAY_SIZE(taycan_eko_t_vco), 91 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], 92 .clkr = { 93 .hw.init = &(const struct clk_init_data) { 94 .name = "disp_cc_pll0", 95 .parent_data = &(const struct clk_parent_data) { 96 .index = DT_BI_TCXO, 97 }, 98 .num_parents = 1, 99 .ops = &clk_alpha_pll_taycan_eko_t_ops, 100 }, 101 }, 102 }; 103 104 /* 300.0 MHz Configuration */ 105 static const struct alpha_pll_config disp_cc_pll1_config = { 106 .l = 0xf, 107 .cal_l = 0x48, 108 .alpha = 0xa000, 109 .config_ctl_val = 0x25c400e7, 110 .config_ctl_hi_val = 0x0a8062e0, 111 .config_ctl_hi1_val = 0xf51dea20, 112 .user_ctl_val = 0x00000008, 113 .user_ctl_hi_val = 0x00000002, 114 }; 115 116 static struct clk_alpha_pll disp_cc_pll1 = { 117 .offset = 0x1000, 118 .config = &disp_cc_pll1_config, 119 .vco_table = taycan_eko_t_vco, 120 .num_vco = ARRAY_SIZE(taycan_eko_t_vco), 121 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], 122 .clkr = { 123 .hw.init = &(const struct clk_init_data) { 124 .name = "disp_cc_pll1", 125 .parent_data = &(const struct clk_parent_data) { 126 .index = DT_BI_TCXO, 127 }, 128 .num_parents = 1, 129 .ops = &clk_alpha_pll_taycan_eko_t_ops, 130 }, 131 }, 132 }; 133 134 /* 38.4 MHz Configuration */ 135 static const struct alpha_pll_config disp_cc_pll2_config = { 136 .l = 0x493, 137 .cal_l = 0x493, 138 .alpha = 0x0, 139 .config_ctl_val = 0x60000f68, 140 .config_ctl_hi_val = 0x0001c808, 141 .config_ctl_hi1_val = 0x00000000, 142 .config_ctl_hi2_val = 0x040082f4, 143 .test_ctl_val = 0x00000000, 144 .test_ctl_hi_val = 0x0080c496, 145 .test_ctl_hi1_val = 0x40100080, 146 .test_ctl_hi2_val = 0x001001bc, 147 .test_ctl_hi3_val = 0x002003d8, 148 .user_ctl_val = 0x00000400, 149 .user_ctl_hi_val = 0x00e50302, 150 }; 151 152 static struct clk_alpha_pll disp_cc_pll2 = { 153 .offset = 0x2000, 154 .config = &disp_cc_pll2_config, 155 .vco_table = pongo_eko_t_vco, 156 .num_vco = ARRAY_SIZE(pongo_eko_t_vco), 157 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_PONGO_EKO_T], 158 .clkr = { 159 .hw.init = &(const struct clk_init_data) { 160 .name = "disp_cc_pll2", 161 .parent_data = &(const struct clk_parent_data) { 162 .index = DT_SLEEP_CLK, 163 }, 164 .num_parents = 1, 165 .ops = &clk_alpha_pll_pongo_eko_t_ops, 166 }, 167 }, 168 }; 169 170 static const struct parent_map disp_cc_parent_map_0[] = { 171 { P_BI_TCXO, 0 }, 172 }; 173 174 static const struct clk_parent_data disp_cc_parent_data_0[] = { 175 { .index = DT_BI_TCXO }, 176 }; 177 178 static const struct parent_map disp_cc_parent_map_1[] = { 179 { P_BI_TCXO, 0 }, 180 { P_DSI0_PHY_PLL_OUT_DSICLK, 1 }, 181 { P_DSI0_PHY_PLL_OUT_BYTECLK, 2 }, 182 { P_DSI1_PHY_PLL_OUT_DSICLK, 3 }, 183 { P_DSI1_PHY_PLL_OUT_BYTECLK, 4 }, 184 }; 185 186 static const struct clk_parent_data disp_cc_parent_data_1[] = { 187 { .index = DT_BI_TCXO }, 188 { .index = DT_DSI0_PHY_PLL_OUT_DSICLK }, 189 { .index = DT_DSI0_PHY_PLL_OUT_BYTECLK }, 190 { .index = DT_DSI1_PHY_PLL_OUT_DSICLK }, 191 { .index = DT_DSI1_PHY_PLL_OUT_BYTECLK }, 192 }; 193 194 static const struct parent_map disp_cc_parent_map_2[] = { 195 { P_BI_TCXO, 0 }, 196 { P_DP3_PHY_PLL_VCO_DIV_CLK, 3 }, 197 { P_DP1_PHY_PLL_VCO_DIV_CLK, 4 }, 198 { P_DP2_PHY_PLL_VCO_DIV_CLK, 6 }, 199 }; 200 201 static const struct clk_parent_data disp_cc_parent_data_2[] = { 202 { .index = DT_BI_TCXO }, 203 { .index = DT_DP3_PHY_PLL_VCO_DIV_CLK }, 204 { .index = DT_DP1_PHY_PLL_VCO_DIV_CLK }, 205 { .index = DT_DP2_PHY_PLL_VCO_DIV_CLK }, 206 }; 207 208 static const struct parent_map disp_cc_parent_map_3[] = { 209 { P_BI_TCXO, 0 }, 210 { P_DP1_PHY_PLL_LINK_CLK, 2 }, 211 { P_DP2_PHY_PLL_LINK_CLK, 3 }, 212 { P_DP3_PHY_PLL_LINK_CLK, 4 }, 213 }; 214 215 static const struct clk_parent_data disp_cc_parent_data_3[] = { 216 { .index = DT_BI_TCXO }, 217 { .index = DT_DP1_PHY_PLL_LINK_CLK }, 218 { .index = DT_DP2_PHY_PLL_LINK_CLK }, 219 { .index = DT_DP3_PHY_PLL_LINK_CLK }, 220 }; 221 222 static const struct parent_map disp_cc_parent_map_4[] = { 223 { P_BI_TCXO, 0 }, 224 { P_DSI0_PHY_PLL_OUT_DSICLK, 1 }, 225 { P_DISP_CC_PLL2_OUT_MAIN, 2 }, 226 { P_DSI1_PHY_PLL_OUT_DSICLK, 3 }, 227 }; 228 229 static const struct clk_parent_data disp_cc_parent_data_4[] = { 230 { .index = DT_BI_TCXO }, 231 { .index = DT_DSI0_PHY_PLL_OUT_DSICLK }, 232 { .hw = &disp_cc_pll2.clkr.hw }, 233 { .index = DT_DSI1_PHY_PLL_OUT_DSICLK }, 234 }; 235 236 static const struct parent_map disp_cc_parent_map_5[] = { 237 { P_BI_TCXO, 0 }, 238 { P_DP0_PHY_PLL_LINK_CLK, 1 }, 239 { P_DP0_PHY_PLL_VCO_DIV_CLK, 2 }, 240 { P_DP3_PHY_PLL_VCO_DIV_CLK, 3 }, 241 { P_DP1_PHY_PLL_VCO_DIV_CLK, 4 }, 242 { P_DP2_PHY_PLL_VCO_DIV_CLK, 6 }, 243 }; 244 245 static const struct clk_parent_data disp_cc_parent_data_5[] = { 246 { .index = DT_BI_TCXO }, 247 { .index = DT_DP0_PHY_PLL_LINK_CLK }, 248 { .index = DT_DP0_PHY_PLL_VCO_DIV_CLK }, 249 { .index = DT_DP3_PHY_PLL_VCO_DIV_CLK }, 250 { .index = DT_DP1_PHY_PLL_VCO_DIV_CLK }, 251 { .index = DT_DP2_PHY_PLL_VCO_DIV_CLK }, 252 }; 253 254 static const struct parent_map disp_cc_parent_map_6[] = { 255 { P_BI_TCXO, 0 }, 256 { P_DSI0_PHY_PLL_OUT_BYTECLK, 2 }, 257 { P_DSI1_PHY_PLL_OUT_BYTECLK, 4 }, 258 }; 259 260 static const struct clk_parent_data disp_cc_parent_data_6[] = { 261 { .index = DT_BI_TCXO }, 262 { .index = DT_DSI0_PHY_PLL_OUT_BYTECLK }, 263 { .index = DT_DSI1_PHY_PLL_OUT_BYTECLK }, 264 }; 265 266 static const struct parent_map disp_cc_parent_map_7[] = { 267 { P_BI_TCXO, 0 }, 268 { P_DISP_CC_PLL1_OUT_MAIN, 4 }, 269 { P_DISP_CC_PLL1_OUT_EVEN, 6 }, 270 }; 271 272 static const struct clk_parent_data disp_cc_parent_data_7[] = { 273 { .index = DT_BI_TCXO }, 274 { .hw = &disp_cc_pll1.clkr.hw }, 275 { .hw = &disp_cc_pll1.clkr.hw }, 276 }; 277 278 static const struct parent_map disp_cc_parent_map_8[] = { 279 { P_BI_TCXO, 0 }, 280 { P_DP0_PHY_PLL_LINK_CLK, 1 }, 281 { P_DP1_PHY_PLL_LINK_CLK, 2 }, 282 { P_DP2_PHY_PLL_LINK_CLK, 3 }, 283 { P_DP3_PHY_PLL_LINK_CLK, 4 }, 284 }; 285 286 static const struct clk_parent_data disp_cc_parent_data_8[] = { 287 { .index = DT_BI_TCXO }, 288 { .index = DT_DP0_PHY_PLL_LINK_CLK }, 289 { .index = DT_DP1_PHY_PLL_LINK_CLK }, 290 { .index = DT_DP2_PHY_PLL_LINK_CLK }, 291 { .index = DT_DP3_PHY_PLL_LINK_CLK }, 292 }; 293 294 static const struct parent_map disp_cc_parent_map_9[] = { 295 { P_BI_TCXO, 0 }, 296 { P_DISP_CC_PLL0_OUT_MAIN, 1 }, 297 { P_DISP_CC_PLL1_OUT_MAIN, 4 }, 298 { P_DISP_CC_PLL1_OUT_EVEN, 6 }, 299 }; 300 301 static const struct clk_parent_data disp_cc_parent_data_9[] = { 302 { .index = DT_BI_TCXO }, 303 { .hw = &disp_cc_pll0.clkr.hw }, 304 { .hw = &disp_cc_pll1.clkr.hw }, 305 { .hw = &disp_cc_pll1.clkr.hw }, 306 }; 307 308 static const struct parent_map disp_cc_parent_map_10[] = { 309 { P_BI_TCXO, 0 }, 310 { P_DISP_CC_PLL2_OUT_MAIN, 2 }, 311 }; 312 313 static const struct clk_parent_data disp_cc_parent_data_10[] = { 314 { .index = DT_BI_TCXO }, 315 { .hw = &disp_cc_pll2.clkr.hw }, 316 }; 317 318 static const struct freq_tbl ftbl_disp_cc_esync0_clk_src[] = { 319 F(19200000, P_BI_TCXO, 1, 0, 0), 320 { } 321 }; 322 323 static struct clk_rcg2 disp_cc_esync0_clk_src = { 324 .cmd_rcgr = 0x80d4, 325 .mnd_width = 16, 326 .hid_width = 5, 327 .parent_map = disp_cc_parent_map_4, 328 .freq_tbl = ftbl_disp_cc_esync0_clk_src, 329 .clkr.hw.init = &(const struct clk_init_data) { 330 .name = "disp_cc_esync0_clk_src", 331 .parent_data = disp_cc_parent_data_4, 332 .num_parents = ARRAY_SIZE(disp_cc_parent_data_4), 333 .flags = CLK_SET_RATE_PARENT, 334 .ops = &clk_pixel_ops, 335 }, 336 }; 337 338 static struct clk_rcg2 disp_cc_esync1_clk_src = { 339 .cmd_rcgr = 0x80ec, 340 .mnd_width = 16, 341 .hid_width = 5, 342 .parent_map = disp_cc_parent_map_4, 343 .freq_tbl = ftbl_disp_cc_esync0_clk_src, 344 .clkr.hw.init = &(const struct clk_init_data) { 345 .name = "disp_cc_esync1_clk_src", 346 .parent_data = disp_cc_parent_data_4, 347 .num_parents = ARRAY_SIZE(disp_cc_parent_data_4), 348 .flags = CLK_SET_RATE_PARENT, 349 .ops = &clk_pixel_ops, 350 }, 351 }; 352 353 static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = { 354 F(19200000, P_BI_TCXO, 1, 0, 0), 355 F(100000000, P_DISP_CC_PLL1_OUT_EVEN, 3, 0, 0), 356 F(120000000, P_DISP_CC_PLL1_OUT_EVEN, 3, 0, 0), 357 F(165000000, P_DISP_CC_PLL1_OUT_EVEN, 3, 0, 0), 358 F(200000000, P_DISP_CC_PLL1_OUT_EVEN, 3, 0, 0), 359 F(233333333, P_DISP_CC_PLL1_OUT_EVEN, 3, 0, 0), 360 F(261666667, P_DISP_CC_PLL1_OUT_EVEN, 3, 0, 0), 361 F(283333333, P_DISP_CC_PLL1_OUT_EVEN, 3, 0, 0), 362 { } 363 }; 364 365 static struct clk_rcg2 disp_cc_mdss_ahb_clk_src = { 366 .cmd_rcgr = 0x8378, 367 .mnd_width = 0, 368 .hid_width = 5, 369 .parent_map = disp_cc_parent_map_7, 370 .freq_tbl = ftbl_disp_cc_mdss_ahb_clk_src, 371 .hw_clk_ctrl = true, 372 .clkr.hw.init = &(const struct clk_init_data) { 373 .name = "disp_cc_mdss_ahb_clk_src", 374 .parent_data = disp_cc_parent_data_7, 375 .num_parents = ARRAY_SIZE(disp_cc_parent_data_7), 376 .flags = CLK_SET_RATE_PARENT, 377 .ops = &clk_rcg2_shared_ops, 378 }, 379 }; 380 381 static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = { 382 .cmd_rcgr = 0x8194, 383 .mnd_width = 0, 384 .hid_width = 5, 385 .parent_map = disp_cc_parent_map_1, 386 .freq_tbl = ftbl_disp_cc_esync0_clk_src, 387 .clkr.hw.init = &(const struct clk_init_data) { 388 .name = "disp_cc_mdss_byte0_clk_src", 389 .parent_data = disp_cc_parent_data_1, 390 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), 391 .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, 392 .ops = &clk_byte2_ops, 393 }, 394 }; 395 396 static struct clk_rcg2 disp_cc_mdss_byte1_clk_src = { 397 .cmd_rcgr = 0x81b0, 398 .mnd_width = 0, 399 .hid_width = 5, 400 .parent_map = disp_cc_parent_map_1, 401 .freq_tbl = ftbl_disp_cc_esync0_clk_src, 402 .clkr.hw.init = &(const struct clk_init_data) { 403 .name = "disp_cc_mdss_byte1_clk_src", 404 .parent_data = disp_cc_parent_data_1, 405 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), 406 .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, 407 .ops = &clk_byte2_ops, 408 }, 409 }; 410 411 static struct clk_rcg2 disp_cc_mdss_dptx0_aux_clk_src = { 412 .cmd_rcgr = 0x8248, 413 .mnd_width = 0, 414 .hid_width = 5, 415 .parent_map = disp_cc_parent_map_0, 416 .freq_tbl = ftbl_disp_cc_esync0_clk_src, 417 .clkr.hw.init = &(const struct clk_init_data) { 418 .name = "disp_cc_mdss_dptx0_aux_clk_src", 419 .parent_data = disp_cc_parent_data_0, 420 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), 421 .flags = CLK_SET_RATE_PARENT, 422 .ops = &clk_rcg2_ops, 423 }, 424 }; 425 426 static struct clk_rcg2 disp_cc_mdss_dptx0_link_clk_src = { 427 .cmd_rcgr = 0x81fc, 428 .mnd_width = 0, 429 .hid_width = 5, 430 .parent_map = disp_cc_parent_map_8, 431 .freq_tbl = ftbl_disp_cc_esync0_clk_src, 432 .clkr.hw.init = &(const struct clk_init_data) { 433 .name = "disp_cc_mdss_dptx0_link_clk_src", 434 .parent_data = disp_cc_parent_data_8, 435 .num_parents = ARRAY_SIZE(disp_cc_parent_data_8), 436 .flags = CLK_SET_RATE_PARENT, 437 .ops = &clk_byte2_ops, 438 }, 439 }; 440 441 static struct clk_rcg2 disp_cc_mdss_dptx0_pixel0_clk_src = { 442 .cmd_rcgr = 0x8218, 443 .mnd_width = 16, 444 .hid_width = 5, 445 .parent_map = disp_cc_parent_map_5, 446 .freq_tbl = ftbl_disp_cc_esync0_clk_src, 447 .clkr.hw.init = &(const struct clk_init_data) { 448 .name = "disp_cc_mdss_dptx0_pixel0_clk_src", 449 .parent_data = disp_cc_parent_data_5, 450 .num_parents = ARRAY_SIZE(disp_cc_parent_data_5), 451 .flags = CLK_SET_RATE_PARENT, 452 .ops = &clk_dp_ops, 453 }, 454 }; 455 456 static struct clk_rcg2 disp_cc_mdss_dptx0_pixel1_clk_src = { 457 .cmd_rcgr = 0x8230, 458 .mnd_width = 16, 459 .hid_width = 5, 460 .parent_map = disp_cc_parent_map_5, 461 .freq_tbl = ftbl_disp_cc_esync0_clk_src, 462 .clkr.hw.init = &(const struct clk_init_data) { 463 .name = "disp_cc_mdss_dptx0_pixel1_clk_src", 464 .parent_data = disp_cc_parent_data_5, 465 .num_parents = ARRAY_SIZE(disp_cc_parent_data_5), 466 .flags = CLK_SET_RATE_PARENT, 467 .ops = &clk_dp_ops, 468 }, 469 }; 470 471 static struct clk_rcg2 disp_cc_mdss_dptx1_aux_clk_src = { 472 .cmd_rcgr = 0x82ac, 473 .mnd_width = 0, 474 .hid_width = 5, 475 .parent_map = disp_cc_parent_map_0, 476 .freq_tbl = ftbl_disp_cc_esync0_clk_src, 477 .clkr.hw.init = &(const struct clk_init_data) { 478 .name = "disp_cc_mdss_dptx1_aux_clk_src", 479 .parent_data = disp_cc_parent_data_0, 480 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), 481 .flags = CLK_SET_RATE_PARENT, 482 .ops = &clk_rcg2_shared_ops, 483 }, 484 }; 485 486 static struct clk_rcg2 disp_cc_mdss_dptx1_link_clk_src = { 487 .cmd_rcgr = 0x8290, 488 .mnd_width = 0, 489 .hid_width = 5, 490 .parent_map = disp_cc_parent_map_3, 491 .freq_tbl = ftbl_disp_cc_esync0_clk_src, 492 .clkr.hw.init = &(const struct clk_init_data) { 493 .name = "disp_cc_mdss_dptx1_link_clk_src", 494 .parent_data = disp_cc_parent_data_3, 495 .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), 496 .flags = CLK_SET_RATE_PARENT, 497 .ops = &clk_byte2_ops, 498 }, 499 }; 500 501 static struct clk_rcg2 disp_cc_mdss_dptx1_pixel0_clk_src = { 502 .cmd_rcgr = 0x8260, 503 .mnd_width = 16, 504 .hid_width = 5, 505 .parent_map = disp_cc_parent_map_2, 506 .freq_tbl = ftbl_disp_cc_esync0_clk_src, 507 .clkr.hw.init = &(const struct clk_init_data) { 508 .name = "disp_cc_mdss_dptx1_pixel0_clk_src", 509 .parent_data = disp_cc_parent_data_2, 510 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), 511 .flags = CLK_SET_RATE_PARENT, 512 .ops = &clk_dp_ops, 513 }, 514 }; 515 516 static struct clk_rcg2 disp_cc_mdss_dptx1_pixel1_clk_src = { 517 .cmd_rcgr = 0x8278, 518 .mnd_width = 16, 519 .hid_width = 5, 520 .parent_map = disp_cc_parent_map_2, 521 .freq_tbl = ftbl_disp_cc_esync0_clk_src, 522 .clkr.hw.init = &(const struct clk_init_data) { 523 .name = "disp_cc_mdss_dptx1_pixel1_clk_src", 524 .parent_data = disp_cc_parent_data_2, 525 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), 526 .flags = CLK_SET_RATE_PARENT, 527 .ops = &clk_dp_ops, 528 }, 529 }; 530 531 static struct clk_rcg2 disp_cc_mdss_dptx2_aux_clk_src = { 532 .cmd_rcgr = 0x8310, 533 .mnd_width = 0, 534 .hid_width = 5, 535 .parent_map = disp_cc_parent_map_0, 536 .freq_tbl = ftbl_disp_cc_esync0_clk_src, 537 .clkr.hw.init = &(const struct clk_init_data) { 538 .name = "disp_cc_mdss_dptx2_aux_clk_src", 539 .parent_data = disp_cc_parent_data_0, 540 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), 541 .flags = CLK_SET_RATE_PARENT, 542 .ops = &clk_rcg2_shared_ops, 543 }, 544 }; 545 546 static struct clk_rcg2 disp_cc_mdss_dptx2_link_clk_src = { 547 .cmd_rcgr = 0x82c4, 548 .mnd_width = 0, 549 .hid_width = 5, 550 .parent_map = disp_cc_parent_map_3, 551 .freq_tbl = ftbl_disp_cc_esync0_clk_src, 552 .clkr.hw.init = &(const struct clk_init_data) { 553 .name = "disp_cc_mdss_dptx2_link_clk_src", 554 .parent_data = disp_cc_parent_data_3, 555 .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), 556 .flags = CLK_SET_RATE_PARENT, 557 .ops = &clk_byte2_ops, 558 }, 559 }; 560 561 static struct clk_rcg2 disp_cc_mdss_dptx2_pixel0_clk_src = { 562 .cmd_rcgr = 0x82e0, 563 .mnd_width = 16, 564 .hid_width = 5, 565 .parent_map = disp_cc_parent_map_2, 566 .freq_tbl = ftbl_disp_cc_esync0_clk_src, 567 .clkr.hw.init = &(const struct clk_init_data) { 568 .name = "disp_cc_mdss_dptx2_pixel0_clk_src", 569 .parent_data = disp_cc_parent_data_2, 570 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), 571 .flags = CLK_SET_RATE_PARENT, 572 .ops = &clk_dp_ops, 573 }, 574 }; 575 576 static struct clk_rcg2 disp_cc_mdss_dptx2_pixel1_clk_src = { 577 .cmd_rcgr = 0x82f8, 578 .mnd_width = 16, 579 .hid_width = 5, 580 .parent_map = disp_cc_parent_map_2, 581 .freq_tbl = ftbl_disp_cc_esync0_clk_src, 582 .clkr.hw.init = &(const struct clk_init_data) { 583 .name = "disp_cc_mdss_dptx2_pixel1_clk_src", 584 .parent_data = disp_cc_parent_data_2, 585 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), 586 .flags = CLK_SET_RATE_PARENT, 587 .ops = &clk_dp_ops, 588 }, 589 }; 590 591 static struct clk_rcg2 disp_cc_mdss_dptx3_aux_clk_src = { 592 .cmd_rcgr = 0x835c, 593 .mnd_width = 0, 594 .hid_width = 5, 595 .parent_map = disp_cc_parent_map_0, 596 .freq_tbl = ftbl_disp_cc_esync0_clk_src, 597 .clkr.hw.init = &(const struct clk_init_data) { 598 .name = "disp_cc_mdss_dptx3_aux_clk_src", 599 .parent_data = disp_cc_parent_data_0, 600 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), 601 .flags = CLK_SET_RATE_PARENT, 602 .ops = &clk_rcg2_shared_ops, 603 }, 604 }; 605 606 static struct clk_rcg2 disp_cc_mdss_dptx3_link_clk_src = { 607 .cmd_rcgr = 0x8340, 608 .mnd_width = 0, 609 .hid_width = 5, 610 .parent_map = disp_cc_parent_map_3, 611 .freq_tbl = ftbl_disp_cc_esync0_clk_src, 612 .clkr.hw.init = &(const struct clk_init_data) { 613 .name = "disp_cc_mdss_dptx3_link_clk_src", 614 .parent_data = disp_cc_parent_data_3, 615 .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), 616 .flags = CLK_SET_RATE_PARENT, 617 .ops = &clk_byte2_ops, 618 }, 619 }; 620 621 static struct clk_rcg2 disp_cc_mdss_dptx3_pixel0_clk_src = { 622 .cmd_rcgr = 0x8328, 623 .mnd_width = 16, 624 .hid_width = 5, 625 .parent_map = disp_cc_parent_map_2, 626 .freq_tbl = ftbl_disp_cc_esync0_clk_src, 627 .clkr.hw.init = &(const struct clk_init_data) { 628 .name = "disp_cc_mdss_dptx3_pixel0_clk_src", 629 .parent_data = disp_cc_parent_data_2, 630 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), 631 .flags = CLK_SET_RATE_PARENT, 632 .ops = &clk_dp_ops, 633 }, 634 }; 635 636 static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = { 637 .cmd_rcgr = 0x81cc, 638 .mnd_width = 0, 639 .hid_width = 5, 640 .parent_map = disp_cc_parent_map_6, 641 .freq_tbl = ftbl_disp_cc_esync0_clk_src, 642 .clkr.hw.init = &(const struct clk_init_data) { 643 .name = "disp_cc_mdss_esc0_clk_src", 644 .parent_data = disp_cc_parent_data_6, 645 .num_parents = ARRAY_SIZE(disp_cc_parent_data_6), 646 .flags = CLK_SET_RATE_PARENT, 647 .ops = &clk_rcg2_shared_ops, 648 }, 649 }; 650 651 static struct clk_rcg2 disp_cc_mdss_esc1_clk_src = { 652 .cmd_rcgr = 0x81e4, 653 .mnd_width = 0, 654 .hid_width = 5, 655 .parent_map = disp_cc_parent_map_6, 656 .freq_tbl = ftbl_disp_cc_esync0_clk_src, 657 .clkr.hw.init = &(const struct clk_init_data) { 658 .name = "disp_cc_mdss_esc1_clk_src", 659 .parent_data = disp_cc_parent_data_6, 660 .num_parents = ARRAY_SIZE(disp_cc_parent_data_6), 661 .flags = CLK_SET_RATE_PARENT, 662 .ops = &clk_rcg2_shared_ops, 663 }, 664 }; 665 666 static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] = { 667 F(19200000, P_BI_TCXO, 1, 0, 0), 668 F(85714286, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 669 F(100000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 670 F(156000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 671 F(207000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 672 F(337000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 673 F(417000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 674 F(532000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 675 F(600000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 676 F(650000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 677 { } 678 }; 679 680 static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = { 681 .cmd_rcgr = 0x8164, 682 .mnd_width = 0, 683 .hid_width = 5, 684 .parent_map = disp_cc_parent_map_9, 685 .freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src, 686 .hw_clk_ctrl = true, 687 .clkr.hw.init = &(const struct clk_init_data) { 688 .name = "disp_cc_mdss_mdp_clk_src", 689 .parent_data = disp_cc_parent_data_9, 690 .num_parents = ARRAY_SIZE(disp_cc_parent_data_9), 691 .flags = CLK_SET_RATE_PARENT, 692 .ops = &clk_rcg2_shared_ops, 693 }, 694 }; 695 696 static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = { 697 .cmd_rcgr = 0x811c, 698 .mnd_width = 8, 699 .hid_width = 5, 700 .parent_map = disp_cc_parent_map_1, 701 .freq_tbl = ftbl_disp_cc_esync0_clk_src, 702 .clkr.hw.init = &(const struct clk_init_data) { 703 .name = "disp_cc_mdss_pclk0_clk_src", 704 .parent_data = disp_cc_parent_data_1, 705 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), 706 .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, 707 .ops = &clk_pixel_ops, 708 }, 709 }; 710 711 static struct clk_rcg2 disp_cc_mdss_pclk1_clk_src = { 712 .cmd_rcgr = 0x8134, 713 .mnd_width = 8, 714 .hid_width = 5, 715 .parent_map = disp_cc_parent_map_1, 716 .freq_tbl = ftbl_disp_cc_esync0_clk_src, 717 .clkr.hw.init = &(const struct clk_init_data) { 718 .name = "disp_cc_mdss_pclk1_clk_src", 719 .parent_data = disp_cc_parent_data_1, 720 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), 721 .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, 722 .ops = &clk_pixel_ops, 723 }, 724 }; 725 726 static struct clk_rcg2 disp_cc_mdss_pclk2_clk_src = { 727 .cmd_rcgr = 0x814c, 728 .mnd_width = 8, 729 .hid_width = 5, 730 .parent_map = disp_cc_parent_map_1, 731 .freq_tbl = ftbl_disp_cc_esync0_clk_src, 732 .clkr.hw.init = &(const struct clk_init_data) { 733 .name = "disp_cc_mdss_pclk2_clk_src", 734 .parent_data = disp_cc_parent_data_1, 735 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), 736 .flags = CLK_SET_RATE_PARENT, 737 .ops = &clk_pixel_ops, 738 }, 739 }; 740 741 static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = { 742 .cmd_rcgr = 0x817c, 743 .mnd_width = 0, 744 .hid_width = 5, 745 .parent_map = disp_cc_parent_map_0, 746 .freq_tbl = ftbl_disp_cc_esync0_clk_src, 747 .clkr.hw.init = &(const struct clk_init_data) { 748 .name = "disp_cc_mdss_vsync_clk_src", 749 .parent_data = disp_cc_parent_data_0, 750 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), 751 .flags = CLK_SET_RATE_PARENT, 752 .ops = &clk_rcg2_shared_ops, 753 }, 754 }; 755 756 static const struct freq_tbl ftbl_disp_cc_osc_clk_src[] = { 757 F(38400000, P_DISP_CC_PLL2_OUT_MAIN, 1, 0, 0), 758 { } 759 }; 760 761 static struct clk_rcg2 disp_cc_osc_clk_src = { 762 .cmd_rcgr = 0x8104, 763 .mnd_width = 0, 764 .hid_width = 5, 765 .parent_map = disp_cc_parent_map_10, 766 .freq_tbl = ftbl_disp_cc_osc_clk_src, 767 .clkr.hw.init = &(const struct clk_init_data) { 768 .name = "disp_cc_osc_clk_src", 769 .parent_data = disp_cc_parent_data_10, 770 .num_parents = ARRAY_SIZE(disp_cc_parent_data_10), 771 .flags = CLK_SET_RATE_PARENT, 772 .ops = &clk_rcg2_shared_ops, 773 }, 774 }; 775 776 static struct clk_regmap_div disp_cc_mdss_ahb_swi_div_clk_src = { 777 .reg = 0x8374, 778 .shift = 0, 779 .width = 4, 780 .clkr.hw.init = &(const struct clk_init_data) { 781 .name = "disp_cc_mdss_ahb_swi_div_clk_src", 782 .parent_hws = (const struct clk_hw*[]) { 783 &disp_cc_mdss_ahb_clk_src.clkr.hw, 784 }, 785 .num_parents = 1, 786 .flags = CLK_SET_RATE_PARENT, 787 .ops = &clk_regmap_div_ro_ops, 788 }, 789 }; 790 791 static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = { 792 .reg = 0x81ac, 793 .shift = 0, 794 .width = 4, 795 .clkr.hw.init = &(const struct clk_init_data) { 796 .name = "disp_cc_mdss_byte0_div_clk_src", 797 .parent_hws = (const struct clk_hw*[]) { 798 &disp_cc_mdss_byte0_clk_src.clkr.hw, 799 }, 800 .num_parents = 1, 801 .ops = &clk_regmap_div_ops, 802 }, 803 }; 804 805 static struct clk_regmap_div disp_cc_mdss_byte1_div_clk_src = { 806 .reg = 0x81c8, 807 .shift = 0, 808 .width = 4, 809 .clkr.hw.init = &(const struct clk_init_data) { 810 .name = "disp_cc_mdss_byte1_div_clk_src", 811 .parent_hws = (const struct clk_hw*[]) { 812 &disp_cc_mdss_byte1_clk_src.clkr.hw, 813 }, 814 .num_parents = 1, 815 .ops = &clk_regmap_div_ops, 816 }, 817 }; 818 819 static struct clk_regmap_div disp_cc_mdss_dptx0_link_div_clk_src = { 820 .reg = 0x8214, 821 .shift = 0, 822 .width = 4, 823 .clkr.hw.init = &(const struct clk_init_data) { 824 .name = "disp_cc_mdss_dptx0_link_div_clk_src", 825 .parent_hws = (const struct clk_hw*[]) { 826 &disp_cc_mdss_dptx0_link_clk_src.clkr.hw, 827 }, 828 .num_parents = 1, 829 .flags = CLK_SET_RATE_PARENT, 830 .ops = &clk_regmap_div_ro_ops, 831 }, 832 }; 833 834 static struct clk_regmap_div disp_cc_mdss_dptx1_link_div_clk_src = { 835 .reg = 0x82a8, 836 .shift = 0, 837 .width = 4, 838 .clkr.hw.init = &(const struct clk_init_data) { 839 .name = "disp_cc_mdss_dptx1_link_div_clk_src", 840 .parent_hws = (const struct clk_hw*[]) { 841 &disp_cc_mdss_dptx1_link_clk_src.clkr.hw, 842 }, 843 .num_parents = 1, 844 .flags = CLK_SET_RATE_PARENT, 845 .ops = &clk_regmap_div_ro_ops, 846 }, 847 }; 848 849 static struct clk_regmap_div disp_cc_mdss_dptx2_link_div_clk_src = { 850 .reg = 0x82dc, 851 .shift = 0, 852 .width = 4, 853 .clkr.hw.init = &(const struct clk_init_data) { 854 .name = "disp_cc_mdss_dptx2_link_div_clk_src", 855 .parent_hws = (const struct clk_hw*[]) { 856 &disp_cc_mdss_dptx2_link_clk_src.clkr.hw, 857 }, 858 .num_parents = 1, 859 .flags = CLK_SET_RATE_PARENT, 860 .ops = &clk_regmap_div_ro_ops, 861 }, 862 }; 863 864 static struct clk_regmap_div disp_cc_mdss_dptx3_link_div_clk_src = { 865 .reg = 0x8358, 866 .shift = 0, 867 .width = 4, 868 .clkr.hw.init = &(const struct clk_init_data) { 869 .name = "disp_cc_mdss_dptx3_link_div_clk_src", 870 .parent_hws = (const struct clk_hw*[]) { 871 &disp_cc_mdss_dptx3_link_clk_src.clkr.hw, 872 }, 873 .num_parents = 1, 874 .flags = CLK_SET_RATE_PARENT, 875 .ops = &clk_regmap_div_ro_ops, 876 }, 877 }; 878 879 static struct clk_branch disp_cc_esync0_clk = { 880 .halt_reg = 0x80cc, 881 .halt_check = BRANCH_HALT, 882 .clkr = { 883 .enable_reg = 0x80cc, 884 .enable_mask = BIT(0), 885 .hw.init = &(const struct clk_init_data) { 886 .name = "disp_cc_esync0_clk", 887 .parent_hws = (const struct clk_hw*[]) { 888 &disp_cc_esync0_clk_src.clkr.hw, 889 }, 890 .num_parents = 1, 891 .flags = CLK_SET_RATE_PARENT, 892 .ops = &clk_branch2_ops, 893 }, 894 }, 895 }; 896 897 static struct clk_branch disp_cc_esync1_clk = { 898 .halt_reg = 0x80d0, 899 .halt_check = BRANCH_HALT, 900 .clkr = { 901 .enable_reg = 0x80d0, 902 .enable_mask = BIT(0), 903 .hw.init = &(const struct clk_init_data) { 904 .name = "disp_cc_esync1_clk", 905 .parent_hws = (const struct clk_hw*[]) { 906 &disp_cc_esync1_clk_src.clkr.hw, 907 }, 908 .num_parents = 1, 909 .flags = CLK_SET_RATE_PARENT, 910 .ops = &clk_branch2_ops, 911 }, 912 }, 913 }; 914 915 static struct clk_branch disp_cc_mdss_accu_shift_clk = { 916 .halt_reg = 0xe060, 917 .halt_check = BRANCH_HALT_VOTED, 918 .clkr = { 919 .enable_reg = 0xe060, 920 .enable_mask = BIT(0), 921 .hw.init = &(const struct clk_init_data) { 922 .name = "disp_cc_mdss_accu_shift_clk", 923 .ops = &clk_branch2_ops, 924 }, 925 }, 926 }; 927 928 static struct clk_branch disp_cc_mdss_ahb1_clk = { 929 .halt_reg = 0xa028, 930 .halt_check = BRANCH_HALT, 931 .clkr = { 932 .enable_reg = 0xa028, 933 .enable_mask = BIT(0), 934 .hw.init = &(const struct clk_init_data) { 935 .name = "disp_cc_mdss_ahb1_clk", 936 .parent_hws = (const struct clk_hw*[]) { 937 &disp_cc_mdss_ahb_clk_src.clkr.hw, 938 }, 939 .num_parents = 1, 940 .flags = CLK_SET_RATE_PARENT, 941 .ops = &clk_branch2_ops, 942 }, 943 }, 944 }; 945 946 static struct clk_branch disp_cc_mdss_ahb_clk = { 947 .halt_reg = 0x80c4, 948 .halt_check = BRANCH_HALT, 949 .clkr = { 950 .enable_reg = 0x80c4, 951 .enable_mask = BIT(0), 952 .hw.init = &(const struct clk_init_data) { 953 .name = "disp_cc_mdss_ahb_clk", 954 .parent_hws = (const struct clk_hw*[]) { 955 &disp_cc_mdss_ahb_clk_src.clkr.hw, 956 }, 957 .num_parents = 1, 958 .flags = CLK_SET_RATE_PARENT, 959 .ops = &clk_branch2_ops, 960 }, 961 }, 962 }; 963 964 static struct clk_branch disp_cc_mdss_ahb_swi_clk = { 965 .halt_reg = 0x80c0, 966 .halt_check = BRANCH_HALT, 967 .clkr = { 968 .enable_reg = 0x80c0, 969 .enable_mask = BIT(0), 970 .hw.init = &(const struct clk_init_data) { 971 .name = "disp_cc_mdss_ahb_swi_clk", 972 .parent_hws = (const struct clk_hw*[]) { 973 &disp_cc_mdss_ahb_swi_div_clk_src.clkr.hw, 974 }, 975 .num_parents = 1, 976 .flags = CLK_SET_RATE_PARENT, 977 .ops = &clk_branch2_ops, 978 }, 979 }, 980 }; 981 982 static struct clk_branch disp_cc_mdss_byte0_clk = { 983 .halt_reg = 0x8044, 984 .halt_check = BRANCH_HALT, 985 .clkr = { 986 .enable_reg = 0x8044, 987 .enable_mask = BIT(0), 988 .hw.init = &(const struct clk_init_data) { 989 .name = "disp_cc_mdss_byte0_clk", 990 .parent_hws = (const struct clk_hw*[]) { 991 &disp_cc_mdss_byte0_clk_src.clkr.hw, 992 }, 993 .num_parents = 1, 994 .flags = CLK_SET_RATE_PARENT, 995 .ops = &clk_branch2_ops, 996 }, 997 }, 998 }; 999 1000 static struct clk_branch disp_cc_mdss_byte0_intf_clk = { 1001 .halt_reg = 0x8048, 1002 .halt_check = BRANCH_HALT, 1003 .clkr = { 1004 .enable_reg = 0x8048, 1005 .enable_mask = BIT(0), 1006 .hw.init = &(const struct clk_init_data) { 1007 .name = "disp_cc_mdss_byte0_intf_clk", 1008 .parent_hws = (const struct clk_hw*[]) { 1009 &disp_cc_mdss_byte0_div_clk_src.clkr.hw, 1010 }, 1011 .num_parents = 1, 1012 .flags = CLK_SET_RATE_PARENT, 1013 .ops = &clk_branch2_ops, 1014 }, 1015 }, 1016 }; 1017 1018 static struct clk_branch disp_cc_mdss_byte1_clk = { 1019 .halt_reg = 0x804c, 1020 .halt_check = BRANCH_HALT, 1021 .clkr = { 1022 .enable_reg = 0x804c, 1023 .enable_mask = BIT(0), 1024 .hw.init = &(const struct clk_init_data) { 1025 .name = "disp_cc_mdss_byte1_clk", 1026 .parent_hws = (const struct clk_hw*[]) { 1027 &disp_cc_mdss_byte1_clk_src.clkr.hw, 1028 }, 1029 .num_parents = 1, 1030 .flags = CLK_SET_RATE_PARENT, 1031 .ops = &clk_branch2_ops, 1032 }, 1033 }, 1034 }; 1035 1036 static struct clk_branch disp_cc_mdss_byte1_intf_clk = { 1037 .halt_reg = 0x8050, 1038 .halt_check = BRANCH_HALT, 1039 .clkr = { 1040 .enable_reg = 0x8050, 1041 .enable_mask = BIT(0), 1042 .hw.init = &(const struct clk_init_data) { 1043 .name = "disp_cc_mdss_byte1_intf_clk", 1044 .parent_hws = (const struct clk_hw*[]) { 1045 &disp_cc_mdss_byte1_div_clk_src.clkr.hw, 1046 }, 1047 .num_parents = 1, 1048 .flags = CLK_SET_RATE_PARENT, 1049 .ops = &clk_branch2_ops, 1050 }, 1051 }, 1052 }; 1053 1054 static struct clk_branch disp_cc_mdss_dptx0_aux_clk = { 1055 .halt_reg = 0x8074, 1056 .halt_check = BRANCH_HALT, 1057 .clkr = { 1058 .enable_reg = 0x8074, 1059 .enable_mask = BIT(0), 1060 .hw.init = &(const struct clk_init_data) { 1061 .name = "disp_cc_mdss_dptx0_aux_clk", 1062 .parent_hws = (const struct clk_hw*[]) { 1063 &disp_cc_mdss_dptx0_aux_clk_src.clkr.hw, 1064 }, 1065 .num_parents = 1, 1066 .flags = CLK_SET_RATE_PARENT, 1067 .ops = &clk_branch2_ops, 1068 }, 1069 }, 1070 }; 1071 1072 static struct clk_branch disp_cc_mdss_dptx0_crypto_clk = { 1073 .halt_reg = 0x8068, 1074 .halt_check = BRANCH_HALT_VOTED, 1075 .clkr = { 1076 .enable_reg = 0x8068, 1077 .enable_mask = BIT(0), 1078 .hw.init = &(const struct clk_init_data) { 1079 .name = "disp_cc_mdss_dptx0_crypto_clk", 1080 .parent_hws = (const struct clk_hw*[]) { 1081 &disp_cc_mdss_dptx0_link_clk_src.clkr.hw, 1082 }, 1083 .num_parents = 1, 1084 .flags = CLK_SET_RATE_PARENT, 1085 .ops = &clk_branch2_ops, 1086 }, 1087 }, 1088 }; 1089 1090 static struct clk_branch disp_cc_mdss_dptx0_link_clk = { 1091 .halt_reg = 0x805c, 1092 .halt_check = BRANCH_HALT, 1093 .clkr = { 1094 .enable_reg = 0x805c, 1095 .enable_mask = BIT(0), 1096 .hw.init = &(const struct clk_init_data) { 1097 .name = "disp_cc_mdss_dptx0_link_clk", 1098 .parent_hws = (const struct clk_hw*[]) { 1099 &disp_cc_mdss_dptx0_link_clk_src.clkr.hw, 1100 }, 1101 .num_parents = 1, 1102 .flags = CLK_SET_RATE_PARENT, 1103 .ops = &clk_branch2_ops, 1104 }, 1105 }, 1106 }; 1107 1108 static struct clk_branch disp_cc_mdss_dptx0_link_intf_clk = { 1109 .halt_reg = 0x8064, 1110 .halt_check = BRANCH_HALT, 1111 .clkr = { 1112 .enable_reg = 0x8064, 1113 .enable_mask = BIT(0), 1114 .hw.init = &(const struct clk_init_data) { 1115 .name = "disp_cc_mdss_dptx0_link_intf_clk", 1116 .parent_hws = (const struct clk_hw*[]) { 1117 &disp_cc_mdss_dptx0_link_div_clk_src.clkr.hw, 1118 }, 1119 .num_parents = 1, 1120 .flags = CLK_SET_RATE_PARENT, 1121 .ops = &clk_branch2_ops, 1122 }, 1123 }, 1124 }; 1125 1126 static struct clk_branch disp_cc_mdss_dptx0_pixel0_clk = { 1127 .halt_reg = 0x806c, 1128 .halt_check = BRANCH_HALT, 1129 .clkr = { 1130 .enable_reg = 0x806c, 1131 .enable_mask = BIT(0), 1132 .hw.init = &(const struct clk_init_data) { 1133 .name = "disp_cc_mdss_dptx0_pixel0_clk", 1134 .parent_hws = (const struct clk_hw*[]) { 1135 &disp_cc_mdss_dptx0_pixel0_clk_src.clkr.hw, 1136 }, 1137 .num_parents = 1, 1138 .flags = CLK_SET_RATE_PARENT, 1139 .ops = &clk_branch2_ops, 1140 }, 1141 }, 1142 }; 1143 1144 static struct clk_branch disp_cc_mdss_dptx0_pixel1_clk = { 1145 .halt_reg = 0x8070, 1146 .halt_check = BRANCH_HALT, 1147 .clkr = { 1148 .enable_reg = 0x8070, 1149 .enable_mask = BIT(0), 1150 .hw.init = &(const struct clk_init_data) { 1151 .name = "disp_cc_mdss_dptx0_pixel1_clk", 1152 .parent_hws = (const struct clk_hw*[]) { 1153 &disp_cc_mdss_dptx0_pixel1_clk_src.clkr.hw, 1154 }, 1155 .num_parents = 1, 1156 .flags = CLK_SET_RATE_PARENT, 1157 .ops = &clk_branch2_ops, 1158 }, 1159 }, 1160 }; 1161 1162 static struct clk_branch disp_cc_mdss_dptx0_usb_router_link_intf_clk = { 1163 .halt_reg = 0x8060, 1164 .halt_check = BRANCH_HALT, 1165 .clkr = { 1166 .enable_reg = 0x8060, 1167 .enable_mask = BIT(0), 1168 .hw.init = &(const struct clk_init_data) { 1169 .name = "disp_cc_mdss_dptx0_usb_router_link_intf_clk", 1170 .parent_hws = (const struct clk_hw*[]) { 1171 &disp_cc_mdss_dptx0_link_div_clk_src.clkr.hw, 1172 }, 1173 .num_parents = 1, 1174 .flags = CLK_SET_RATE_PARENT, 1175 .ops = &clk_branch2_ops, 1176 }, 1177 }, 1178 }; 1179 1180 static struct clk_branch disp_cc_mdss_dptx1_aux_clk = { 1181 .halt_reg = 0x8090, 1182 .halt_check = BRANCH_HALT, 1183 .clkr = { 1184 .enable_reg = 0x8090, 1185 .enable_mask = BIT(0), 1186 .hw.init = &(const struct clk_init_data) { 1187 .name = "disp_cc_mdss_dptx1_aux_clk", 1188 .parent_hws = (const struct clk_hw*[]) { 1189 &disp_cc_mdss_dptx1_aux_clk_src.clkr.hw, 1190 }, 1191 .num_parents = 1, 1192 .flags = CLK_SET_RATE_PARENT, 1193 .ops = &clk_branch2_ops, 1194 }, 1195 }, 1196 }; 1197 1198 static struct clk_branch disp_cc_mdss_dptx1_crypto_clk = { 1199 .halt_reg = 0x808c, 1200 .halt_check = BRANCH_HALT_VOTED, 1201 .clkr = { 1202 .enable_reg = 0x808c, 1203 .enable_mask = BIT(0), 1204 .hw.init = &(const struct clk_init_data) { 1205 .name = "disp_cc_mdss_dptx1_crypto_clk", 1206 .parent_hws = (const struct clk_hw*[]) { 1207 &disp_cc_mdss_dptx1_link_clk_src.clkr.hw, 1208 }, 1209 .num_parents = 1, 1210 .flags = CLK_SET_RATE_PARENT, 1211 .ops = &clk_branch2_ops, 1212 }, 1213 }, 1214 }; 1215 1216 static struct clk_branch disp_cc_mdss_dptx1_link_clk = { 1217 .halt_reg = 0x8080, 1218 .halt_check = BRANCH_HALT, 1219 .clkr = { 1220 .enable_reg = 0x8080, 1221 .enable_mask = BIT(0), 1222 .hw.init = &(const struct clk_init_data) { 1223 .name = "disp_cc_mdss_dptx1_link_clk", 1224 .parent_hws = (const struct clk_hw*[]) { 1225 &disp_cc_mdss_dptx1_link_clk_src.clkr.hw, 1226 }, 1227 .num_parents = 1, 1228 .flags = CLK_SET_RATE_PARENT, 1229 .ops = &clk_branch2_ops, 1230 }, 1231 }, 1232 }; 1233 1234 static struct clk_branch disp_cc_mdss_dptx1_link_intf_clk = { 1235 .halt_reg = 0x8088, 1236 .halt_check = BRANCH_HALT, 1237 .clkr = { 1238 .enable_reg = 0x8088, 1239 .enable_mask = BIT(0), 1240 .hw.init = &(const struct clk_init_data) { 1241 .name = "disp_cc_mdss_dptx1_link_intf_clk", 1242 .parent_hws = (const struct clk_hw*[]) { 1243 &disp_cc_mdss_dptx1_link_div_clk_src.clkr.hw, 1244 }, 1245 .num_parents = 1, 1246 .flags = CLK_SET_RATE_PARENT, 1247 .ops = &clk_branch2_ops, 1248 }, 1249 }, 1250 }; 1251 1252 static struct clk_branch disp_cc_mdss_dptx1_pixel0_clk = { 1253 .halt_reg = 0x8078, 1254 .halt_check = BRANCH_HALT, 1255 .clkr = { 1256 .enable_reg = 0x8078, 1257 .enable_mask = BIT(0), 1258 .hw.init = &(const struct clk_init_data) { 1259 .name = "disp_cc_mdss_dptx1_pixel0_clk", 1260 .parent_hws = (const struct clk_hw*[]) { 1261 &disp_cc_mdss_dptx1_pixel0_clk_src.clkr.hw, 1262 }, 1263 .num_parents = 1, 1264 .flags = CLK_SET_RATE_PARENT, 1265 .ops = &clk_branch2_ops, 1266 }, 1267 }, 1268 }; 1269 1270 static struct clk_branch disp_cc_mdss_dptx1_pixel1_clk = { 1271 .halt_reg = 0x807c, 1272 .halt_check = BRANCH_HALT, 1273 .clkr = { 1274 .enable_reg = 0x807c, 1275 .enable_mask = BIT(0), 1276 .hw.init = &(const struct clk_init_data) { 1277 .name = "disp_cc_mdss_dptx1_pixel1_clk", 1278 .parent_hws = (const struct clk_hw*[]) { 1279 &disp_cc_mdss_dptx1_pixel1_clk_src.clkr.hw, 1280 }, 1281 .num_parents = 1, 1282 .flags = CLK_SET_RATE_PARENT, 1283 .ops = &clk_branch2_ops, 1284 }, 1285 }, 1286 }; 1287 1288 static struct clk_branch disp_cc_mdss_dptx1_usb_router_link_intf_clk = { 1289 .halt_reg = 0x8084, 1290 .halt_check = BRANCH_HALT, 1291 .clkr = { 1292 .enable_reg = 0x8084, 1293 .enable_mask = BIT(0), 1294 .hw.init = &(const struct clk_init_data) { 1295 .name = "disp_cc_mdss_dptx1_usb_router_link_intf_clk", 1296 .parent_hws = (const struct clk_hw*[]) { 1297 &disp_cc_mdss_dptx1_link_div_clk_src.clkr.hw, 1298 }, 1299 .num_parents = 1, 1300 .flags = CLK_SET_RATE_PARENT, 1301 .ops = &clk_branch2_ops, 1302 }, 1303 }, 1304 }; 1305 1306 static struct clk_branch disp_cc_mdss_dptx2_aux_clk = { 1307 .halt_reg = 0x80a8, 1308 .halt_check = BRANCH_HALT, 1309 .clkr = { 1310 .enable_reg = 0x80a8, 1311 .enable_mask = BIT(0), 1312 .hw.init = &(const struct clk_init_data) { 1313 .name = "disp_cc_mdss_dptx2_aux_clk", 1314 .parent_hws = (const struct clk_hw*[]) { 1315 &disp_cc_mdss_dptx2_aux_clk_src.clkr.hw, 1316 }, 1317 .num_parents = 1, 1318 .flags = CLK_SET_RATE_PARENT, 1319 .ops = &clk_branch2_ops, 1320 }, 1321 }, 1322 }; 1323 1324 static struct clk_branch disp_cc_mdss_dptx2_crypto_clk = { 1325 .halt_reg = 0x80a4, 1326 .halt_check = BRANCH_HALT_VOTED, 1327 .clkr = { 1328 .enable_reg = 0x80a4, 1329 .enable_mask = BIT(0), 1330 .hw.init = &(const struct clk_init_data) { 1331 .name = "disp_cc_mdss_dptx2_crypto_clk", 1332 .parent_hws = (const struct clk_hw*[]) { 1333 &disp_cc_mdss_dptx2_link_clk_src.clkr.hw, 1334 }, 1335 .num_parents = 1, 1336 .flags = CLK_SET_RATE_PARENT, 1337 .ops = &clk_branch2_ops, 1338 }, 1339 }, 1340 }; 1341 1342 static struct clk_branch disp_cc_mdss_dptx2_link_clk = { 1343 .halt_reg = 0x809c, 1344 .halt_check = BRANCH_HALT, 1345 .clkr = { 1346 .enable_reg = 0x809c, 1347 .enable_mask = BIT(0), 1348 .hw.init = &(const struct clk_init_data) { 1349 .name = "disp_cc_mdss_dptx2_link_clk", 1350 .parent_hws = (const struct clk_hw*[]) { 1351 &disp_cc_mdss_dptx2_link_clk_src.clkr.hw, 1352 }, 1353 .num_parents = 1, 1354 .flags = CLK_SET_RATE_PARENT, 1355 .ops = &clk_branch2_ops, 1356 }, 1357 }, 1358 }; 1359 1360 static struct clk_branch disp_cc_mdss_dptx2_link_intf_clk = { 1361 .halt_reg = 0x80a0, 1362 .halt_check = BRANCH_HALT, 1363 .clkr = { 1364 .enable_reg = 0x80a0, 1365 .enable_mask = BIT(0), 1366 .hw.init = &(const struct clk_init_data) { 1367 .name = "disp_cc_mdss_dptx2_link_intf_clk", 1368 .parent_hws = (const struct clk_hw*[]) { 1369 &disp_cc_mdss_dptx2_link_div_clk_src.clkr.hw, 1370 }, 1371 .num_parents = 1, 1372 .flags = CLK_SET_RATE_PARENT, 1373 .ops = &clk_branch2_ops, 1374 }, 1375 }, 1376 }; 1377 1378 static struct clk_branch disp_cc_mdss_dptx2_pixel0_clk = { 1379 .halt_reg = 0x8094, 1380 .halt_check = BRANCH_HALT, 1381 .clkr = { 1382 .enable_reg = 0x8094, 1383 .enable_mask = BIT(0), 1384 .hw.init = &(const struct clk_init_data) { 1385 .name = "disp_cc_mdss_dptx2_pixel0_clk", 1386 .parent_hws = (const struct clk_hw*[]) { 1387 &disp_cc_mdss_dptx2_pixel0_clk_src.clkr.hw, 1388 }, 1389 .num_parents = 1, 1390 .flags = CLK_SET_RATE_PARENT, 1391 .ops = &clk_branch2_ops, 1392 }, 1393 }, 1394 }; 1395 1396 static struct clk_branch disp_cc_mdss_dptx2_pixel1_clk = { 1397 .halt_reg = 0x8098, 1398 .halt_check = BRANCH_HALT, 1399 .clkr = { 1400 .enable_reg = 0x8098, 1401 .enable_mask = BIT(0), 1402 .hw.init = &(const struct clk_init_data) { 1403 .name = "disp_cc_mdss_dptx2_pixel1_clk", 1404 .parent_hws = (const struct clk_hw*[]) { 1405 &disp_cc_mdss_dptx2_pixel1_clk_src.clkr.hw, 1406 }, 1407 .num_parents = 1, 1408 .flags = CLK_SET_RATE_PARENT, 1409 .ops = &clk_branch2_ops, 1410 }, 1411 }, 1412 }; 1413 1414 static struct clk_branch disp_cc_mdss_dptx3_aux_clk = { 1415 .halt_reg = 0x80b8, 1416 .halt_check = BRANCH_HALT, 1417 .clkr = { 1418 .enable_reg = 0x80b8, 1419 .enable_mask = BIT(0), 1420 .hw.init = &(const struct clk_init_data) { 1421 .name = "disp_cc_mdss_dptx3_aux_clk", 1422 .parent_hws = (const struct clk_hw*[]) { 1423 &disp_cc_mdss_dptx3_aux_clk_src.clkr.hw, 1424 }, 1425 .num_parents = 1, 1426 .flags = CLK_SET_RATE_PARENT, 1427 .ops = &clk_branch2_ops, 1428 }, 1429 }, 1430 }; 1431 1432 static struct clk_branch disp_cc_mdss_dptx3_crypto_clk = { 1433 .halt_reg = 0x80bc, 1434 .halt_check = BRANCH_HALT_VOTED, 1435 .clkr = { 1436 .enable_reg = 0x80bc, 1437 .enable_mask = BIT(0), 1438 .hw.init = &(const struct clk_init_data) { 1439 .name = "disp_cc_mdss_dptx3_crypto_clk", 1440 .parent_hws = (const struct clk_hw*[]) { 1441 &disp_cc_mdss_dptx3_link_clk_src.clkr.hw, 1442 }, 1443 .num_parents = 1, 1444 .flags = CLK_SET_RATE_PARENT, 1445 .ops = &clk_branch2_ops, 1446 }, 1447 }, 1448 }; 1449 1450 static struct clk_branch disp_cc_mdss_dptx3_link_clk = { 1451 .halt_reg = 0x80b0, 1452 .halt_check = BRANCH_HALT, 1453 .clkr = { 1454 .enable_reg = 0x80b0, 1455 .enable_mask = BIT(0), 1456 .hw.init = &(const struct clk_init_data) { 1457 .name = "disp_cc_mdss_dptx3_link_clk", 1458 .parent_hws = (const struct clk_hw*[]) { 1459 &disp_cc_mdss_dptx3_link_clk_src.clkr.hw, 1460 }, 1461 .num_parents = 1, 1462 .flags = CLK_SET_RATE_PARENT, 1463 .ops = &clk_branch2_ops, 1464 }, 1465 }, 1466 }; 1467 1468 static struct clk_branch disp_cc_mdss_dptx3_link_intf_clk = { 1469 .halt_reg = 0x80b4, 1470 .halt_check = BRANCH_HALT, 1471 .clkr = { 1472 .enable_reg = 0x80b4, 1473 .enable_mask = BIT(0), 1474 .hw.init = &(const struct clk_init_data) { 1475 .name = "disp_cc_mdss_dptx3_link_intf_clk", 1476 .parent_hws = (const struct clk_hw*[]) { 1477 &disp_cc_mdss_dptx3_link_div_clk_src.clkr.hw, 1478 }, 1479 .num_parents = 1, 1480 .flags = CLK_SET_RATE_PARENT, 1481 .ops = &clk_branch2_ops, 1482 }, 1483 }, 1484 }; 1485 1486 static struct clk_branch disp_cc_mdss_dptx3_pixel0_clk = { 1487 .halt_reg = 0x80ac, 1488 .halt_check = BRANCH_HALT, 1489 .clkr = { 1490 .enable_reg = 0x80ac, 1491 .enable_mask = BIT(0), 1492 .hw.init = &(const struct clk_init_data) { 1493 .name = "disp_cc_mdss_dptx3_pixel0_clk", 1494 .parent_hws = (const struct clk_hw*[]) { 1495 &disp_cc_mdss_dptx3_pixel0_clk_src.clkr.hw, 1496 }, 1497 .num_parents = 1, 1498 .flags = CLK_SET_RATE_PARENT, 1499 .ops = &clk_branch2_ops, 1500 }, 1501 }, 1502 }; 1503 1504 static struct clk_branch disp_cc_mdss_esc0_clk = { 1505 .halt_reg = 0x8054, 1506 .halt_check = BRANCH_HALT, 1507 .clkr = { 1508 .enable_reg = 0x8054, 1509 .enable_mask = BIT(0), 1510 .hw.init = &(const struct clk_init_data) { 1511 .name = "disp_cc_mdss_esc0_clk", 1512 .parent_hws = (const struct clk_hw*[]) { 1513 &disp_cc_mdss_esc0_clk_src.clkr.hw, 1514 }, 1515 .num_parents = 1, 1516 .flags = CLK_SET_RATE_PARENT, 1517 .ops = &clk_branch2_ops, 1518 }, 1519 }, 1520 }; 1521 1522 static struct clk_branch disp_cc_mdss_esc1_clk = { 1523 .halt_reg = 0x8058, 1524 .halt_check = BRANCH_HALT, 1525 .clkr = { 1526 .enable_reg = 0x8058, 1527 .enable_mask = BIT(0), 1528 .hw.init = &(const struct clk_init_data) { 1529 .name = "disp_cc_mdss_esc1_clk", 1530 .parent_hws = (const struct clk_hw*[]) { 1531 &disp_cc_mdss_esc1_clk_src.clkr.hw, 1532 }, 1533 .num_parents = 1, 1534 .flags = CLK_SET_RATE_PARENT, 1535 .ops = &clk_branch2_ops, 1536 }, 1537 }, 1538 }; 1539 1540 static struct clk_branch disp_cc_mdss_mdp1_clk = { 1541 .halt_reg = 0xa004, 1542 .halt_check = BRANCH_HALT, 1543 .clkr = { 1544 .enable_reg = 0xa004, 1545 .enable_mask = BIT(0), 1546 .hw.init = &(const struct clk_init_data) { 1547 .name = "disp_cc_mdss_mdp1_clk", 1548 .parent_hws = (const struct clk_hw*[]) { 1549 &disp_cc_mdss_mdp_clk_src.clkr.hw, 1550 }, 1551 .num_parents = 1, 1552 .flags = CLK_SET_RATE_PARENT, 1553 .ops = &clk_branch2_ops, 1554 }, 1555 }, 1556 }; 1557 1558 static struct clk_branch disp_cc_mdss_mdp_clk = { 1559 .halt_reg = 0x8010, 1560 .halt_check = BRANCH_HALT_VOTED, 1561 .clkr = { 1562 .enable_reg = 0x8010, 1563 .enable_mask = BIT(0), 1564 .hw.init = &(const struct clk_init_data) { 1565 .name = "disp_cc_mdss_mdp_clk", 1566 .parent_hws = (const struct clk_hw*[]) { 1567 &disp_cc_mdss_mdp_clk_src.clkr.hw, 1568 }, 1569 .num_parents = 1, 1570 .flags = CLK_SET_RATE_PARENT, 1571 .ops = &clk_branch2_aon_ops, 1572 }, 1573 }, 1574 }; 1575 1576 static struct clk_branch disp_cc_mdss_mdp_lut1_clk = { 1577 .halt_reg = 0xa014, 1578 .halt_check = BRANCH_HALT_VOTED, 1579 .clkr = { 1580 .enable_reg = 0xa014, 1581 .enable_mask = BIT(0), 1582 .hw.init = &(const struct clk_init_data) { 1583 .name = "disp_cc_mdss_mdp_lut1_clk", 1584 .parent_hws = (const struct clk_hw*[]) { 1585 &disp_cc_mdss_mdp_clk_src.clkr.hw, 1586 }, 1587 .num_parents = 1, 1588 .flags = CLK_SET_RATE_PARENT, 1589 .ops = &clk_branch2_ops, 1590 }, 1591 }, 1592 }; 1593 1594 static struct clk_branch disp_cc_mdss_mdp_lut_clk = { 1595 .halt_reg = 0x8020, 1596 .halt_check = BRANCH_HALT_VOTED, 1597 .clkr = { 1598 .enable_reg = 0x8020, 1599 .enable_mask = BIT(0), 1600 .hw.init = &(const struct clk_init_data) { 1601 .name = "disp_cc_mdss_mdp_lut_clk", 1602 .parent_hws = (const struct clk_hw*[]) { 1603 &disp_cc_mdss_mdp_clk_src.clkr.hw, 1604 }, 1605 .num_parents = 1, 1606 .flags = CLK_SET_RATE_PARENT, 1607 .ops = &clk_branch2_ops, 1608 }, 1609 }, 1610 }; 1611 1612 static struct clk_branch disp_cc_mdss_mdp_ss_ip_clk = { 1613 .halt_reg = 0x8030, 1614 .halt_check = BRANCH_HALT_VOTED, 1615 .clkr = { 1616 .enable_reg = 0x8030, 1617 .enable_mask = BIT(0), 1618 .hw.init = &(const struct clk_init_data) { 1619 .name = "disp_cc_mdss_mdp_ss_ip_clk", 1620 .parent_hws = (const struct clk_hw*[]) { 1621 &disp_cc_mdss_mdp_clk_src.clkr.hw, 1622 }, 1623 .num_parents = 1, 1624 .flags = CLK_SET_RATE_PARENT, 1625 .ops = &clk_branch2_ops, 1626 }, 1627 }, 1628 }; 1629 1630 static struct clk_branch disp_cc_mdss_non_gdsc_ahb_clk = { 1631 .halt_reg = 0xc004, 1632 .halt_check = BRANCH_HALT_VOTED, 1633 .clkr = { 1634 .enable_reg = 0xc004, 1635 .enable_mask = BIT(0), 1636 .hw.init = &(const struct clk_init_data) { 1637 .name = "disp_cc_mdss_non_gdsc_ahb_clk", 1638 .parent_hws = (const struct clk_hw*[]) { 1639 &disp_cc_mdss_ahb_clk_src.clkr.hw, 1640 }, 1641 .num_parents = 1, 1642 .flags = CLK_SET_RATE_PARENT, 1643 .ops = &clk_branch2_ops, 1644 }, 1645 }, 1646 }; 1647 1648 static struct clk_branch disp_cc_mdss_pclk0_clk = { 1649 .halt_reg = 0x8004, 1650 .halt_check = BRANCH_HALT, 1651 .clkr = { 1652 .enable_reg = 0x8004, 1653 .enable_mask = BIT(0), 1654 .hw.init = &(const struct clk_init_data) { 1655 .name = "disp_cc_mdss_pclk0_clk", 1656 .parent_hws = (const struct clk_hw*[]) { 1657 &disp_cc_mdss_pclk0_clk_src.clkr.hw, 1658 }, 1659 .num_parents = 1, 1660 .flags = CLK_SET_RATE_PARENT, 1661 .ops = &clk_branch2_ops, 1662 }, 1663 }, 1664 }; 1665 1666 static struct clk_branch disp_cc_mdss_pclk1_clk = { 1667 .halt_reg = 0x8008, 1668 .halt_check = BRANCH_HALT, 1669 .clkr = { 1670 .enable_reg = 0x8008, 1671 .enable_mask = BIT(0), 1672 .hw.init = &(const struct clk_init_data) { 1673 .name = "disp_cc_mdss_pclk1_clk", 1674 .parent_hws = (const struct clk_hw*[]) { 1675 &disp_cc_mdss_pclk1_clk_src.clkr.hw, 1676 }, 1677 .num_parents = 1, 1678 .flags = CLK_SET_RATE_PARENT, 1679 .ops = &clk_branch2_ops, 1680 }, 1681 }, 1682 }; 1683 1684 static struct clk_branch disp_cc_mdss_pclk2_clk = { 1685 .halt_reg = 0x800c, 1686 .halt_check = BRANCH_HALT, 1687 .clkr = { 1688 .enable_reg = 0x800c, 1689 .enable_mask = BIT(0), 1690 .hw.init = &(const struct clk_init_data) { 1691 .name = "disp_cc_mdss_pclk2_clk", 1692 .parent_hws = (const struct clk_hw*[]) { 1693 &disp_cc_mdss_pclk2_clk_src.clkr.hw, 1694 }, 1695 .num_parents = 1, 1696 .flags = CLK_SET_RATE_PARENT, 1697 .ops = &clk_branch2_ops, 1698 }, 1699 }, 1700 }; 1701 1702 static struct clk_branch disp_cc_mdss_vsync1_clk = { 1703 .halt_reg = 0xa024, 1704 .halt_check = BRANCH_HALT, 1705 .clkr = { 1706 .enable_reg = 0xa024, 1707 .enable_mask = BIT(0), 1708 .hw.init = &(const struct clk_init_data) { 1709 .name = "disp_cc_mdss_vsync1_clk", 1710 .parent_hws = (const struct clk_hw*[]) { 1711 &disp_cc_mdss_vsync_clk_src.clkr.hw, 1712 }, 1713 .num_parents = 1, 1714 .flags = CLK_SET_RATE_PARENT, 1715 .ops = &clk_branch2_ops, 1716 }, 1717 }, 1718 }; 1719 1720 static struct clk_branch disp_cc_mdss_vsync_clk = { 1721 .halt_reg = 0x8040, 1722 .halt_check = BRANCH_HALT, 1723 .clkr = { 1724 .enable_reg = 0x8040, 1725 .enable_mask = BIT(0), 1726 .hw.init = &(const struct clk_init_data) { 1727 .name = "disp_cc_mdss_vsync_clk", 1728 .parent_hws = (const struct clk_hw*[]) { 1729 &disp_cc_mdss_vsync_clk_src.clkr.hw, 1730 }, 1731 .num_parents = 1, 1732 .flags = CLK_SET_RATE_PARENT, 1733 .ops = &clk_branch2_ops, 1734 }, 1735 }, 1736 }; 1737 1738 static struct clk_branch disp_cc_osc_clk = { 1739 .halt_reg = 0x80c8, 1740 .halt_check = BRANCH_HALT, 1741 .clkr = { 1742 .enable_reg = 0x80c8, 1743 .enable_mask = BIT(0), 1744 .hw.init = &(const struct clk_init_data) { 1745 .name = "disp_cc_osc_clk", 1746 .parent_hws = (const struct clk_hw*[]) { 1747 &disp_cc_osc_clk_src.clkr.hw, 1748 }, 1749 .num_parents = 1, 1750 .flags = CLK_SET_RATE_PARENT, 1751 .ops = &clk_branch2_ops, 1752 }, 1753 }, 1754 }; 1755 1756 static struct gdsc disp_cc_mdss_core_gdsc = { 1757 .gdscr = 0x9000, 1758 .en_rest_wait_val = 0x2, 1759 .en_few_wait_val = 0x2, 1760 .clk_dis_wait_val = 0xf, 1761 .pd = { 1762 .name = "disp_cc_mdss_core_gdsc", 1763 }, 1764 .pwrsts = PWRSTS_OFF_ON, 1765 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | HW_CTRL_TRIGGER, 1766 }; 1767 1768 static struct gdsc disp_cc_mdss_core_int2_gdsc = { 1769 .gdscr = 0xb000, 1770 .en_rest_wait_val = 0x2, 1771 .en_few_wait_val = 0x2, 1772 .clk_dis_wait_val = 0xf, 1773 .pd = { 1774 .name = "disp_cc_mdss_core_int2_gdsc", 1775 }, 1776 .pwrsts = PWRSTS_OFF_ON, 1777 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | HW_CTRL_TRIGGER, 1778 }; 1779 1780 static struct clk_regmap *disp_cc_kaanapali_clocks[] = { 1781 [DISP_CC_ESYNC0_CLK] = &disp_cc_esync0_clk.clkr, 1782 [DISP_CC_ESYNC0_CLK_SRC] = &disp_cc_esync0_clk_src.clkr, 1783 [DISP_CC_ESYNC1_CLK] = &disp_cc_esync1_clk.clkr, 1784 [DISP_CC_ESYNC1_CLK_SRC] = &disp_cc_esync1_clk_src.clkr, 1785 [DISP_CC_MDSS_ACCU_SHIFT_CLK] = &disp_cc_mdss_accu_shift_clk.clkr, 1786 [DISP_CC_MDSS_AHB1_CLK] = &disp_cc_mdss_ahb1_clk.clkr, 1787 [DISP_CC_MDSS_AHB_CLK] = &disp_cc_mdss_ahb_clk.clkr, 1788 [DISP_CC_MDSS_AHB_CLK_SRC] = &disp_cc_mdss_ahb_clk_src.clkr, 1789 [DISP_CC_MDSS_AHB_SWI_CLK] = &disp_cc_mdss_ahb_swi_clk.clkr, 1790 [DISP_CC_MDSS_AHB_SWI_DIV_CLK_SRC] = &disp_cc_mdss_ahb_swi_div_clk_src.clkr, 1791 [DISP_CC_MDSS_BYTE0_CLK] = &disp_cc_mdss_byte0_clk.clkr, 1792 [DISP_CC_MDSS_BYTE0_CLK_SRC] = &disp_cc_mdss_byte0_clk_src.clkr, 1793 [DISP_CC_MDSS_BYTE0_DIV_CLK_SRC] = &disp_cc_mdss_byte0_div_clk_src.clkr, 1794 [DISP_CC_MDSS_BYTE0_INTF_CLK] = &disp_cc_mdss_byte0_intf_clk.clkr, 1795 [DISP_CC_MDSS_BYTE1_CLK] = &disp_cc_mdss_byte1_clk.clkr, 1796 [DISP_CC_MDSS_BYTE1_CLK_SRC] = &disp_cc_mdss_byte1_clk_src.clkr, 1797 [DISP_CC_MDSS_BYTE1_DIV_CLK_SRC] = &disp_cc_mdss_byte1_div_clk_src.clkr, 1798 [DISP_CC_MDSS_BYTE1_INTF_CLK] = &disp_cc_mdss_byte1_intf_clk.clkr, 1799 [DISP_CC_MDSS_DPTX0_AUX_CLK] = &disp_cc_mdss_dptx0_aux_clk.clkr, 1800 [DISP_CC_MDSS_DPTX0_AUX_CLK_SRC] = &disp_cc_mdss_dptx0_aux_clk_src.clkr, 1801 [DISP_CC_MDSS_DPTX0_CRYPTO_CLK] = &disp_cc_mdss_dptx0_crypto_clk.clkr, 1802 [DISP_CC_MDSS_DPTX0_LINK_CLK] = &disp_cc_mdss_dptx0_link_clk.clkr, 1803 [DISP_CC_MDSS_DPTX0_LINK_CLK_SRC] = &disp_cc_mdss_dptx0_link_clk_src.clkr, 1804 [DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dptx0_link_div_clk_src.clkr, 1805 [DISP_CC_MDSS_DPTX0_LINK_INTF_CLK] = &disp_cc_mdss_dptx0_link_intf_clk.clkr, 1806 [DISP_CC_MDSS_DPTX0_PIXEL0_CLK] = &disp_cc_mdss_dptx0_pixel0_clk.clkr, 1807 [DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC] = &disp_cc_mdss_dptx0_pixel0_clk_src.clkr, 1808 [DISP_CC_MDSS_DPTX0_PIXEL1_CLK] = &disp_cc_mdss_dptx0_pixel1_clk.clkr, 1809 [DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC] = &disp_cc_mdss_dptx0_pixel1_clk_src.clkr, 1810 [DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK] = 1811 &disp_cc_mdss_dptx0_usb_router_link_intf_clk.clkr, 1812 [DISP_CC_MDSS_DPTX1_AUX_CLK] = &disp_cc_mdss_dptx1_aux_clk.clkr, 1813 [DISP_CC_MDSS_DPTX1_AUX_CLK_SRC] = &disp_cc_mdss_dptx1_aux_clk_src.clkr, 1814 [DISP_CC_MDSS_DPTX1_CRYPTO_CLK] = &disp_cc_mdss_dptx1_crypto_clk.clkr, 1815 [DISP_CC_MDSS_DPTX1_LINK_CLK] = &disp_cc_mdss_dptx1_link_clk.clkr, 1816 [DISP_CC_MDSS_DPTX1_LINK_CLK_SRC] = &disp_cc_mdss_dptx1_link_clk_src.clkr, 1817 [DISP_CC_MDSS_DPTX1_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dptx1_link_div_clk_src.clkr, 1818 [DISP_CC_MDSS_DPTX1_LINK_INTF_CLK] = &disp_cc_mdss_dptx1_link_intf_clk.clkr, 1819 [DISP_CC_MDSS_DPTX1_PIXEL0_CLK] = &disp_cc_mdss_dptx1_pixel0_clk.clkr, 1820 [DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC] = &disp_cc_mdss_dptx1_pixel0_clk_src.clkr, 1821 [DISP_CC_MDSS_DPTX1_PIXEL1_CLK] = &disp_cc_mdss_dptx1_pixel1_clk.clkr, 1822 [DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC] = &disp_cc_mdss_dptx1_pixel1_clk_src.clkr, 1823 [DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INTF_CLK] = 1824 &disp_cc_mdss_dptx1_usb_router_link_intf_clk.clkr, 1825 [DISP_CC_MDSS_DPTX2_AUX_CLK] = &disp_cc_mdss_dptx2_aux_clk.clkr, 1826 [DISP_CC_MDSS_DPTX2_AUX_CLK_SRC] = &disp_cc_mdss_dptx2_aux_clk_src.clkr, 1827 [DISP_CC_MDSS_DPTX2_CRYPTO_CLK] = &disp_cc_mdss_dptx2_crypto_clk.clkr, 1828 [DISP_CC_MDSS_DPTX2_LINK_CLK] = &disp_cc_mdss_dptx2_link_clk.clkr, 1829 [DISP_CC_MDSS_DPTX2_LINK_CLK_SRC] = &disp_cc_mdss_dptx2_link_clk_src.clkr, 1830 [DISP_CC_MDSS_DPTX2_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dptx2_link_div_clk_src.clkr, 1831 [DISP_CC_MDSS_DPTX2_LINK_INTF_CLK] = &disp_cc_mdss_dptx2_link_intf_clk.clkr, 1832 [DISP_CC_MDSS_DPTX2_PIXEL0_CLK] = &disp_cc_mdss_dptx2_pixel0_clk.clkr, 1833 [DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC] = &disp_cc_mdss_dptx2_pixel0_clk_src.clkr, 1834 [DISP_CC_MDSS_DPTX2_PIXEL1_CLK] = &disp_cc_mdss_dptx2_pixel1_clk.clkr, 1835 [DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC] = &disp_cc_mdss_dptx2_pixel1_clk_src.clkr, 1836 [DISP_CC_MDSS_DPTX3_AUX_CLK] = &disp_cc_mdss_dptx3_aux_clk.clkr, 1837 [DISP_CC_MDSS_DPTX3_AUX_CLK_SRC] = &disp_cc_mdss_dptx3_aux_clk_src.clkr, 1838 [DISP_CC_MDSS_DPTX3_CRYPTO_CLK] = &disp_cc_mdss_dptx3_crypto_clk.clkr, 1839 [DISP_CC_MDSS_DPTX3_LINK_CLK] = &disp_cc_mdss_dptx3_link_clk.clkr, 1840 [DISP_CC_MDSS_DPTX3_LINK_CLK_SRC] = &disp_cc_mdss_dptx3_link_clk_src.clkr, 1841 [DISP_CC_MDSS_DPTX3_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dptx3_link_div_clk_src.clkr, 1842 [DISP_CC_MDSS_DPTX3_LINK_INTF_CLK] = &disp_cc_mdss_dptx3_link_intf_clk.clkr, 1843 [DISP_CC_MDSS_DPTX3_PIXEL0_CLK] = &disp_cc_mdss_dptx3_pixel0_clk.clkr, 1844 [DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC] = &disp_cc_mdss_dptx3_pixel0_clk_src.clkr, 1845 [DISP_CC_MDSS_ESC0_CLK] = &disp_cc_mdss_esc0_clk.clkr, 1846 [DISP_CC_MDSS_ESC0_CLK_SRC] = &disp_cc_mdss_esc0_clk_src.clkr, 1847 [DISP_CC_MDSS_ESC1_CLK] = &disp_cc_mdss_esc1_clk.clkr, 1848 [DISP_CC_MDSS_ESC1_CLK_SRC] = &disp_cc_mdss_esc1_clk_src.clkr, 1849 [DISP_CC_MDSS_MDP1_CLK] = &disp_cc_mdss_mdp1_clk.clkr, 1850 [DISP_CC_MDSS_MDP_CLK] = &disp_cc_mdss_mdp_clk.clkr, 1851 [DISP_CC_MDSS_MDP_CLK_SRC] = &disp_cc_mdss_mdp_clk_src.clkr, 1852 [DISP_CC_MDSS_MDP_LUT1_CLK] = &disp_cc_mdss_mdp_lut1_clk.clkr, 1853 [DISP_CC_MDSS_MDP_LUT_CLK] = &disp_cc_mdss_mdp_lut_clk.clkr, 1854 [DISP_CC_MDSS_MDP_SS_IP_CLK] = &disp_cc_mdss_mdp_ss_ip_clk.clkr, 1855 [DISP_CC_MDSS_NON_GDSC_AHB_CLK] = &disp_cc_mdss_non_gdsc_ahb_clk.clkr, 1856 [DISP_CC_MDSS_PCLK0_CLK] = &disp_cc_mdss_pclk0_clk.clkr, 1857 [DISP_CC_MDSS_PCLK0_CLK_SRC] = &disp_cc_mdss_pclk0_clk_src.clkr, 1858 [DISP_CC_MDSS_PCLK1_CLK] = &disp_cc_mdss_pclk1_clk.clkr, 1859 [DISP_CC_MDSS_PCLK1_CLK_SRC] = &disp_cc_mdss_pclk1_clk_src.clkr, 1860 [DISP_CC_MDSS_PCLK2_CLK] = &disp_cc_mdss_pclk2_clk.clkr, 1861 [DISP_CC_MDSS_PCLK2_CLK_SRC] = &disp_cc_mdss_pclk2_clk_src.clkr, 1862 [DISP_CC_MDSS_VSYNC1_CLK] = &disp_cc_mdss_vsync1_clk.clkr, 1863 [DISP_CC_MDSS_VSYNC_CLK] = &disp_cc_mdss_vsync_clk.clkr, 1864 [DISP_CC_MDSS_VSYNC_CLK_SRC] = &disp_cc_mdss_vsync_clk_src.clkr, 1865 [DISP_CC_OSC_CLK] = &disp_cc_osc_clk.clkr, 1866 [DISP_CC_OSC_CLK_SRC] = &disp_cc_osc_clk_src.clkr, 1867 [DISP_CC_PLL0] = &disp_cc_pll0.clkr, 1868 [DISP_CC_PLL1] = &disp_cc_pll1.clkr, 1869 [DISP_CC_PLL2] = &disp_cc_pll2.clkr, 1870 }; 1871 1872 static struct gdsc *disp_cc_kaanapali_gdscs[] = { 1873 [DISP_CC_MDSS_CORE_GDSC] = &disp_cc_mdss_core_gdsc, 1874 [DISP_CC_MDSS_CORE_INT2_GDSC] = &disp_cc_mdss_core_int2_gdsc, 1875 }; 1876 1877 static const struct qcom_reset_map disp_cc_kaanapali_resets[] = { 1878 [DISP_CC_MDSS_CORE_BCR] = { 0x8000 }, 1879 [DISP_CC_MDSS_CORE_INT2_BCR] = { 0xa000 }, 1880 [DISP_CC_MDSS_RSCC_BCR] = { 0xc000 }, 1881 }; 1882 1883 static struct clk_alpha_pll *disp_cc_kaanapali_plls[] = { 1884 &disp_cc_pll0, 1885 &disp_cc_pll1, 1886 &disp_cc_pll2, 1887 }; 1888 1889 static const u32 disp_cc_kaanapali_critical_cbcrs[] = { 1890 0xe064, /* DISP_CC_SLEEP_CLK */ 1891 0xe05c, /* DISP_CC_XO_CLK */ 1892 0xc00c, /* DISP_CC_MDSS_RSCC_AHB_CLK */ 1893 0xc008, /* DISP_CC_MDSS_RSCC_VSYNC_CLK */ 1894 }; 1895 1896 static const struct regmap_config disp_cc_kaanapali_regmap_config = { 1897 .reg_bits = 32, 1898 .reg_stride = 4, 1899 .val_bits = 32, 1900 .max_register = 0x12094, 1901 .fast_io = true, 1902 }; 1903 1904 static void clk_kaanapali_regs_configure(struct device *dev, struct regmap *regmap) 1905 { 1906 /* Enable clock gating for MDP clocks */ 1907 regmap_update_bits(regmap, DISP_CC_MISC_CMD, BIT(4), BIT(4)); 1908 } 1909 1910 static const struct qcom_cc_driver_data disp_cc_kaanapali_driver_data = { 1911 .alpha_plls = disp_cc_kaanapali_plls, 1912 .num_alpha_plls = ARRAY_SIZE(disp_cc_kaanapali_plls), 1913 .clk_cbcrs = disp_cc_kaanapali_critical_cbcrs, 1914 .num_clk_cbcrs = ARRAY_SIZE(disp_cc_kaanapali_critical_cbcrs), 1915 .clk_regs_configure = clk_kaanapali_regs_configure, 1916 }; 1917 1918 static const struct qcom_cc_desc disp_cc_kaanapali_desc = { 1919 .config = &disp_cc_kaanapali_regmap_config, 1920 .clks = disp_cc_kaanapali_clocks, 1921 .num_clks = ARRAY_SIZE(disp_cc_kaanapali_clocks), 1922 .resets = disp_cc_kaanapali_resets, 1923 .num_resets = ARRAY_SIZE(disp_cc_kaanapali_resets), 1924 .gdscs = disp_cc_kaanapali_gdscs, 1925 .num_gdscs = ARRAY_SIZE(disp_cc_kaanapali_gdscs), 1926 .use_rpm = true, 1927 .driver_data = &disp_cc_kaanapali_driver_data, 1928 }; 1929 1930 static const struct of_device_id disp_cc_kaanapali_match_table[] = { 1931 { .compatible = "qcom,kaanapali-dispcc" }, 1932 { } 1933 }; 1934 MODULE_DEVICE_TABLE(of, disp_cc_kaanapali_match_table); 1935 1936 static int disp_cc_kaanapali_probe(struct platform_device *pdev) 1937 { 1938 return qcom_cc_probe(pdev, &disp_cc_kaanapali_desc); 1939 } 1940 1941 static struct platform_driver disp_cc_kaanapali_driver = { 1942 .probe = disp_cc_kaanapali_probe, 1943 .driver = { 1944 .name = "dispcc-kaanapali", 1945 .of_match_table = disp_cc_kaanapali_match_table, 1946 }, 1947 }; 1948 1949 module_platform_driver(disp_cc_kaanapali_driver); 1950 1951 MODULE_DESCRIPTION("QTI DISPCC Kaanapali Driver"); 1952 MODULE_LICENSE("GPL"); 1953