1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 4 */ 5 6 #include <linux/clk-provider.h> 7 #include <linux/mod_devicetable.h> 8 #include <linux/module.h> 9 #include <linux/of.h> 10 #include <linux/platform_device.h> 11 #include <linux/pm_runtime.h> 12 #include <linux/regmap.h> 13 14 #include <dt-bindings/clock/qcom,kaanapali-dispcc.h> 15 16 #include "clk-alpha-pll.h" 17 #include "clk-branch.h" 18 #include "clk-pll.h" 19 #include "clk-rcg.h" 20 #include "clk-regmap.h" 21 #include "clk-regmap-divider.h" 22 #include "clk-regmap-mux.h" 23 #include "common.h" 24 #include "gdsc.h" 25 #include "reset.h" 26 27 #define DISP_CC_MISC_CMD 0xF000 28 29 enum { 30 DT_BI_TCXO, 31 DT_BI_TCXO_AO, 32 DT_AHB_CLK, 33 DT_SLEEP_CLK, 34 DT_DP0_PHY_PLL_LINK_CLK, 35 DT_DP0_PHY_PLL_VCO_DIV_CLK, 36 DT_DP1_PHY_PLL_LINK_CLK, 37 DT_DP1_PHY_PLL_VCO_DIV_CLK, 38 DT_DP2_PHY_PLL_LINK_CLK, 39 DT_DP2_PHY_PLL_VCO_DIV_CLK, 40 DT_DP3_PHY_PLL_LINK_CLK, 41 DT_DP3_PHY_PLL_VCO_DIV_CLK, 42 DT_DSI0_PHY_PLL_OUT_BYTECLK, 43 DT_DSI0_PHY_PLL_OUT_DSICLK, 44 DT_DSI1_PHY_PLL_OUT_BYTECLK, 45 DT_DSI1_PHY_PLL_OUT_DSICLK, 46 }; 47 48 enum { 49 P_BI_TCXO, 50 P_DISP_CC_PLL0_OUT_MAIN, 51 P_DISP_CC_PLL1_OUT_EVEN, 52 P_DISP_CC_PLL1_OUT_MAIN, 53 P_DISP_CC_PLL2_OUT_MAIN, 54 P_DP0_PHY_PLL_LINK_CLK, 55 P_DP0_PHY_PLL_VCO_DIV_CLK, 56 P_DP1_PHY_PLL_LINK_CLK, 57 P_DP1_PHY_PLL_VCO_DIV_CLK, 58 P_DP2_PHY_PLL_LINK_CLK, 59 P_DP2_PHY_PLL_VCO_DIV_CLK, 60 P_DP3_PHY_PLL_LINK_CLK, 61 P_DP3_PHY_PLL_VCO_DIV_CLK, 62 P_DSI0_PHY_PLL_OUT_BYTECLK, 63 P_DSI0_PHY_PLL_OUT_DSICLK, 64 P_DSI1_PHY_PLL_OUT_BYTECLK, 65 P_DSI1_PHY_PLL_OUT_DSICLK, 66 }; 67 68 static const struct pll_vco pongo_eko_t_vco[] = { 69 { 38400000, 153600000, 0 }, 70 }; 71 72 static const struct pll_vco taycan_eko_t_vco[] = { 73 { 249600000, 2500000000, 0 }, 74 }; 75 76 /* 257.142858 MHz Configuration */ 77 static const struct alpha_pll_config disp_cc_pll0_config = { 78 .l = 0xd, 79 .cal_l = 0x48, 80 .alpha = 0x6492, 81 .config_ctl_val = 0x25c400e7, 82 .config_ctl_hi_val = 0x0a8062e0, 83 .config_ctl_hi1_val = 0xf51dea20, 84 .user_ctl_val = 0x00000008, 85 .user_ctl_hi_val = 0x00000002, 86 }; 87 88 static struct clk_alpha_pll disp_cc_pll0 = { 89 .offset = 0x0, 90 .config = &disp_cc_pll0_config, 91 .vco_table = taycan_eko_t_vco, 92 .num_vco = ARRAY_SIZE(taycan_eko_t_vco), 93 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], 94 .clkr = { 95 .hw.init = &(const struct clk_init_data) { 96 .name = "disp_cc_pll0", 97 .parent_data = &(const struct clk_parent_data) { 98 .index = DT_BI_TCXO, 99 }, 100 .num_parents = 1, 101 .ops = &clk_alpha_pll_taycan_eko_t_ops, 102 }, 103 }, 104 }; 105 106 /* 300.0 MHz Configuration */ 107 static const struct alpha_pll_config disp_cc_pll1_config = { 108 .l = 0xf, 109 .cal_l = 0x48, 110 .alpha = 0xa000, 111 .config_ctl_val = 0x25c400e7, 112 .config_ctl_hi_val = 0x0a8062e0, 113 .config_ctl_hi1_val = 0xf51dea20, 114 .user_ctl_val = 0x00000008, 115 .user_ctl_hi_val = 0x00000002, 116 }; 117 118 static struct clk_alpha_pll disp_cc_pll1 = { 119 .offset = 0x1000, 120 .config = &disp_cc_pll1_config, 121 .vco_table = taycan_eko_t_vco, 122 .num_vco = ARRAY_SIZE(taycan_eko_t_vco), 123 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], 124 .clkr = { 125 .hw.init = &(const struct clk_init_data) { 126 .name = "disp_cc_pll1", 127 .parent_data = &(const struct clk_parent_data) { 128 .index = DT_BI_TCXO, 129 }, 130 .num_parents = 1, 131 .ops = &clk_alpha_pll_taycan_eko_t_ops, 132 }, 133 }, 134 }; 135 136 /* 38.4 MHz Configuration */ 137 static const struct alpha_pll_config disp_cc_pll2_config = { 138 .l = 0x493, 139 .cal_l = 0x493, 140 .alpha = 0x0, 141 .config_ctl_val = 0x60000f68, 142 .config_ctl_hi_val = 0x0001c808, 143 .config_ctl_hi1_val = 0x00000000, 144 .config_ctl_hi2_val = 0x040082f4, 145 .test_ctl_val = 0x00000000, 146 .test_ctl_hi_val = 0x0080c496, 147 .test_ctl_hi1_val = 0x40100080, 148 .test_ctl_hi2_val = 0x001001bc, 149 .test_ctl_hi3_val = 0x002003d8, 150 .user_ctl_val = 0x00000400, 151 .user_ctl_hi_val = 0x00e50302, 152 }; 153 154 static struct clk_alpha_pll disp_cc_pll2 = { 155 .offset = 0x2000, 156 .config = &disp_cc_pll2_config, 157 .vco_table = pongo_eko_t_vco, 158 .num_vco = ARRAY_SIZE(pongo_eko_t_vco), 159 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_PONGO_EKO_T], 160 .clkr = { 161 .hw.init = &(const struct clk_init_data) { 162 .name = "disp_cc_pll2", 163 .parent_data = &(const struct clk_parent_data) { 164 .index = DT_SLEEP_CLK, 165 }, 166 .num_parents = 1, 167 .ops = &clk_alpha_pll_pongo_eko_t_ops, 168 }, 169 }, 170 }; 171 172 static const struct parent_map disp_cc_parent_map_0[] = { 173 { P_BI_TCXO, 0 }, 174 }; 175 176 static const struct clk_parent_data disp_cc_parent_data_0[] = { 177 { .index = DT_BI_TCXO }, 178 }; 179 180 static const struct parent_map disp_cc_parent_map_1[] = { 181 { P_BI_TCXO, 0 }, 182 { P_DSI0_PHY_PLL_OUT_DSICLK, 1 }, 183 { P_DSI0_PHY_PLL_OUT_BYTECLK, 2 }, 184 { P_DSI1_PHY_PLL_OUT_DSICLK, 3 }, 185 { P_DSI1_PHY_PLL_OUT_BYTECLK, 4 }, 186 }; 187 188 static const struct clk_parent_data disp_cc_parent_data_1[] = { 189 { .index = DT_BI_TCXO }, 190 { .index = DT_DSI0_PHY_PLL_OUT_DSICLK }, 191 { .index = DT_DSI0_PHY_PLL_OUT_BYTECLK }, 192 { .index = DT_DSI1_PHY_PLL_OUT_DSICLK }, 193 { .index = DT_DSI1_PHY_PLL_OUT_BYTECLK }, 194 }; 195 196 static const struct parent_map disp_cc_parent_map_2[] = { 197 { P_BI_TCXO, 0 }, 198 { P_DP3_PHY_PLL_VCO_DIV_CLK, 3 }, 199 { P_DP1_PHY_PLL_VCO_DIV_CLK, 4 }, 200 { P_DP2_PHY_PLL_VCO_DIV_CLK, 6 }, 201 }; 202 203 static const struct clk_parent_data disp_cc_parent_data_2[] = { 204 { .index = DT_BI_TCXO }, 205 { .index = DT_DP3_PHY_PLL_VCO_DIV_CLK }, 206 { .index = DT_DP1_PHY_PLL_VCO_DIV_CLK }, 207 { .index = DT_DP2_PHY_PLL_VCO_DIV_CLK }, 208 }; 209 210 static const struct parent_map disp_cc_parent_map_3[] = { 211 { P_BI_TCXO, 0 }, 212 { P_DP1_PHY_PLL_LINK_CLK, 2 }, 213 { P_DP2_PHY_PLL_LINK_CLK, 3 }, 214 { P_DP3_PHY_PLL_LINK_CLK, 4 }, 215 }; 216 217 static const struct clk_parent_data disp_cc_parent_data_3[] = { 218 { .index = DT_BI_TCXO }, 219 { .index = DT_DP1_PHY_PLL_LINK_CLK }, 220 { .index = DT_DP2_PHY_PLL_LINK_CLK }, 221 { .index = DT_DP3_PHY_PLL_LINK_CLK }, 222 }; 223 224 static const struct parent_map disp_cc_parent_map_4[] = { 225 { P_BI_TCXO, 0 }, 226 { P_DSI0_PHY_PLL_OUT_DSICLK, 1 }, 227 { P_DISP_CC_PLL2_OUT_MAIN, 2 }, 228 { P_DSI1_PHY_PLL_OUT_DSICLK, 3 }, 229 }; 230 231 static const struct clk_parent_data disp_cc_parent_data_4[] = { 232 { .index = DT_BI_TCXO }, 233 { .index = DT_DSI0_PHY_PLL_OUT_DSICLK }, 234 { .hw = &disp_cc_pll2.clkr.hw }, 235 { .index = DT_DSI1_PHY_PLL_OUT_DSICLK }, 236 }; 237 238 static const struct parent_map disp_cc_parent_map_5[] = { 239 { P_BI_TCXO, 0 }, 240 { P_DP0_PHY_PLL_LINK_CLK, 1 }, 241 { P_DP0_PHY_PLL_VCO_DIV_CLK, 2 }, 242 { P_DP3_PHY_PLL_VCO_DIV_CLK, 3 }, 243 { P_DP1_PHY_PLL_VCO_DIV_CLK, 4 }, 244 { P_DP2_PHY_PLL_VCO_DIV_CLK, 6 }, 245 }; 246 247 static const struct clk_parent_data disp_cc_parent_data_5[] = { 248 { .index = DT_BI_TCXO }, 249 { .index = DT_DP0_PHY_PLL_LINK_CLK }, 250 { .index = DT_DP0_PHY_PLL_VCO_DIV_CLK }, 251 { .index = DT_DP3_PHY_PLL_VCO_DIV_CLK }, 252 { .index = DT_DP1_PHY_PLL_VCO_DIV_CLK }, 253 { .index = DT_DP2_PHY_PLL_VCO_DIV_CLK }, 254 }; 255 256 static const struct parent_map disp_cc_parent_map_6[] = { 257 { P_BI_TCXO, 0 }, 258 { P_DSI0_PHY_PLL_OUT_BYTECLK, 2 }, 259 { P_DSI1_PHY_PLL_OUT_BYTECLK, 4 }, 260 }; 261 262 static const struct clk_parent_data disp_cc_parent_data_6[] = { 263 { .index = DT_BI_TCXO }, 264 { .index = DT_DSI0_PHY_PLL_OUT_BYTECLK }, 265 { .index = DT_DSI1_PHY_PLL_OUT_BYTECLK }, 266 }; 267 268 static const struct parent_map disp_cc_parent_map_7[] = { 269 { P_BI_TCXO, 0 }, 270 { P_DISP_CC_PLL1_OUT_MAIN, 4 }, 271 { P_DISP_CC_PLL1_OUT_EVEN, 6 }, 272 }; 273 274 static const struct clk_parent_data disp_cc_parent_data_7[] = { 275 { .index = DT_BI_TCXO }, 276 { .hw = &disp_cc_pll1.clkr.hw }, 277 { .hw = &disp_cc_pll1.clkr.hw }, 278 }; 279 280 static const struct parent_map disp_cc_parent_map_8[] = { 281 { P_BI_TCXO, 0 }, 282 { P_DP0_PHY_PLL_LINK_CLK, 1 }, 283 { P_DP1_PHY_PLL_LINK_CLK, 2 }, 284 { P_DP2_PHY_PLL_LINK_CLK, 3 }, 285 { P_DP3_PHY_PLL_LINK_CLK, 4 }, 286 }; 287 288 static const struct clk_parent_data disp_cc_parent_data_8[] = { 289 { .index = DT_BI_TCXO }, 290 { .index = DT_DP0_PHY_PLL_LINK_CLK }, 291 { .index = DT_DP1_PHY_PLL_LINK_CLK }, 292 { .index = DT_DP2_PHY_PLL_LINK_CLK }, 293 { .index = DT_DP3_PHY_PLL_LINK_CLK }, 294 }; 295 296 static const struct parent_map disp_cc_parent_map_9[] = { 297 { P_BI_TCXO, 0 }, 298 { P_DISP_CC_PLL0_OUT_MAIN, 1 }, 299 { P_DISP_CC_PLL1_OUT_MAIN, 4 }, 300 { P_DISP_CC_PLL1_OUT_EVEN, 6 }, 301 }; 302 303 static const struct clk_parent_data disp_cc_parent_data_9[] = { 304 { .index = DT_BI_TCXO }, 305 { .hw = &disp_cc_pll0.clkr.hw }, 306 { .hw = &disp_cc_pll1.clkr.hw }, 307 { .hw = &disp_cc_pll1.clkr.hw }, 308 }; 309 310 static const struct parent_map disp_cc_parent_map_10[] = { 311 { P_BI_TCXO, 0 }, 312 { P_DISP_CC_PLL2_OUT_MAIN, 2 }, 313 }; 314 315 static const struct clk_parent_data disp_cc_parent_data_10[] = { 316 { .index = DT_BI_TCXO }, 317 { .hw = &disp_cc_pll2.clkr.hw }, 318 }; 319 320 static const struct freq_tbl ftbl_disp_cc_esync0_clk_src[] = { 321 F(19200000, P_BI_TCXO, 1, 0, 0), 322 { } 323 }; 324 325 static struct clk_rcg2 disp_cc_esync0_clk_src = { 326 .cmd_rcgr = 0x80d4, 327 .mnd_width = 16, 328 .hid_width = 5, 329 .parent_map = disp_cc_parent_map_4, 330 .freq_tbl = ftbl_disp_cc_esync0_clk_src, 331 .clkr.hw.init = &(const struct clk_init_data) { 332 .name = "disp_cc_esync0_clk_src", 333 .parent_data = disp_cc_parent_data_4, 334 .num_parents = ARRAY_SIZE(disp_cc_parent_data_4), 335 .flags = CLK_SET_RATE_PARENT, 336 .ops = &clk_pixel_ops, 337 }, 338 }; 339 340 static struct clk_rcg2 disp_cc_esync1_clk_src = { 341 .cmd_rcgr = 0x80ec, 342 .mnd_width = 16, 343 .hid_width = 5, 344 .parent_map = disp_cc_parent_map_4, 345 .freq_tbl = ftbl_disp_cc_esync0_clk_src, 346 .clkr.hw.init = &(const struct clk_init_data) { 347 .name = "disp_cc_esync1_clk_src", 348 .parent_data = disp_cc_parent_data_4, 349 .num_parents = ARRAY_SIZE(disp_cc_parent_data_4), 350 .flags = CLK_SET_RATE_PARENT, 351 .ops = &clk_pixel_ops, 352 }, 353 }; 354 355 static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = { 356 F(19200000, P_BI_TCXO, 1, 0, 0), 357 F(100000000, P_DISP_CC_PLL1_OUT_EVEN, 3, 0, 0), 358 F(120000000, P_DISP_CC_PLL1_OUT_EVEN, 3, 0, 0), 359 F(165000000, P_DISP_CC_PLL1_OUT_EVEN, 3, 0, 0), 360 F(200000000, P_DISP_CC_PLL1_OUT_EVEN, 3, 0, 0), 361 F(233333333, P_DISP_CC_PLL1_OUT_EVEN, 3, 0, 0), 362 F(261666667, P_DISP_CC_PLL1_OUT_EVEN, 3, 0, 0), 363 F(283333333, P_DISP_CC_PLL1_OUT_EVEN, 3, 0, 0), 364 { } 365 }; 366 367 static struct clk_rcg2 disp_cc_mdss_ahb_clk_src = { 368 .cmd_rcgr = 0x8378, 369 .mnd_width = 0, 370 .hid_width = 5, 371 .parent_map = disp_cc_parent_map_7, 372 .freq_tbl = ftbl_disp_cc_mdss_ahb_clk_src, 373 .hw_clk_ctrl = true, 374 .clkr.hw.init = &(const struct clk_init_data) { 375 .name = "disp_cc_mdss_ahb_clk_src", 376 .parent_data = disp_cc_parent_data_7, 377 .num_parents = ARRAY_SIZE(disp_cc_parent_data_7), 378 .flags = CLK_SET_RATE_PARENT, 379 .ops = &clk_rcg2_shared_ops, 380 }, 381 }; 382 383 static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = { 384 .cmd_rcgr = 0x8194, 385 .mnd_width = 0, 386 .hid_width = 5, 387 .parent_map = disp_cc_parent_map_1, 388 .freq_tbl = ftbl_disp_cc_esync0_clk_src, 389 .clkr.hw.init = &(const struct clk_init_data) { 390 .name = "disp_cc_mdss_byte0_clk_src", 391 .parent_data = disp_cc_parent_data_1, 392 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), 393 .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, 394 .ops = &clk_byte2_ops, 395 }, 396 }; 397 398 static struct clk_rcg2 disp_cc_mdss_byte1_clk_src = { 399 .cmd_rcgr = 0x81b0, 400 .mnd_width = 0, 401 .hid_width = 5, 402 .parent_map = disp_cc_parent_map_1, 403 .freq_tbl = ftbl_disp_cc_esync0_clk_src, 404 .clkr.hw.init = &(const struct clk_init_data) { 405 .name = "disp_cc_mdss_byte1_clk_src", 406 .parent_data = disp_cc_parent_data_1, 407 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), 408 .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, 409 .ops = &clk_byte2_ops, 410 }, 411 }; 412 413 static struct clk_rcg2 disp_cc_mdss_dptx0_aux_clk_src = { 414 .cmd_rcgr = 0x8248, 415 .mnd_width = 0, 416 .hid_width = 5, 417 .parent_map = disp_cc_parent_map_0, 418 .freq_tbl = ftbl_disp_cc_esync0_clk_src, 419 .clkr.hw.init = &(const struct clk_init_data) { 420 .name = "disp_cc_mdss_dptx0_aux_clk_src", 421 .parent_data = disp_cc_parent_data_0, 422 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), 423 .flags = CLK_SET_RATE_PARENT, 424 .ops = &clk_rcg2_ops, 425 }, 426 }; 427 428 static struct clk_rcg2 disp_cc_mdss_dptx0_link_clk_src = { 429 .cmd_rcgr = 0x81fc, 430 .mnd_width = 0, 431 .hid_width = 5, 432 .parent_map = disp_cc_parent_map_8, 433 .freq_tbl = ftbl_disp_cc_esync0_clk_src, 434 .clkr.hw.init = &(const struct clk_init_data) { 435 .name = "disp_cc_mdss_dptx0_link_clk_src", 436 .parent_data = disp_cc_parent_data_8, 437 .num_parents = ARRAY_SIZE(disp_cc_parent_data_8), 438 .flags = CLK_SET_RATE_PARENT, 439 .ops = &clk_byte2_ops, 440 }, 441 }; 442 443 static struct clk_rcg2 disp_cc_mdss_dptx0_pixel0_clk_src = { 444 .cmd_rcgr = 0x8218, 445 .mnd_width = 16, 446 .hid_width = 5, 447 .parent_map = disp_cc_parent_map_5, 448 .freq_tbl = ftbl_disp_cc_esync0_clk_src, 449 .clkr.hw.init = &(const struct clk_init_data) { 450 .name = "disp_cc_mdss_dptx0_pixel0_clk_src", 451 .parent_data = disp_cc_parent_data_5, 452 .num_parents = ARRAY_SIZE(disp_cc_parent_data_5), 453 .flags = CLK_SET_RATE_PARENT, 454 .ops = &clk_dp_ops, 455 }, 456 }; 457 458 static struct clk_rcg2 disp_cc_mdss_dptx0_pixel1_clk_src = { 459 .cmd_rcgr = 0x8230, 460 .mnd_width = 16, 461 .hid_width = 5, 462 .parent_map = disp_cc_parent_map_5, 463 .freq_tbl = ftbl_disp_cc_esync0_clk_src, 464 .clkr.hw.init = &(const struct clk_init_data) { 465 .name = "disp_cc_mdss_dptx0_pixel1_clk_src", 466 .parent_data = disp_cc_parent_data_5, 467 .num_parents = ARRAY_SIZE(disp_cc_parent_data_5), 468 .flags = CLK_SET_RATE_PARENT, 469 .ops = &clk_dp_ops, 470 }, 471 }; 472 473 static struct clk_rcg2 disp_cc_mdss_dptx1_aux_clk_src = { 474 .cmd_rcgr = 0x82ac, 475 .mnd_width = 0, 476 .hid_width = 5, 477 .parent_map = disp_cc_parent_map_0, 478 .freq_tbl = ftbl_disp_cc_esync0_clk_src, 479 .clkr.hw.init = &(const struct clk_init_data) { 480 .name = "disp_cc_mdss_dptx1_aux_clk_src", 481 .parent_data = disp_cc_parent_data_0, 482 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), 483 .flags = CLK_SET_RATE_PARENT, 484 .ops = &clk_rcg2_shared_ops, 485 }, 486 }; 487 488 static struct clk_rcg2 disp_cc_mdss_dptx1_link_clk_src = { 489 .cmd_rcgr = 0x8290, 490 .mnd_width = 0, 491 .hid_width = 5, 492 .parent_map = disp_cc_parent_map_3, 493 .freq_tbl = ftbl_disp_cc_esync0_clk_src, 494 .clkr.hw.init = &(const struct clk_init_data) { 495 .name = "disp_cc_mdss_dptx1_link_clk_src", 496 .parent_data = disp_cc_parent_data_3, 497 .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), 498 .flags = CLK_SET_RATE_PARENT, 499 .ops = &clk_byte2_ops, 500 }, 501 }; 502 503 static struct clk_rcg2 disp_cc_mdss_dptx1_pixel0_clk_src = { 504 .cmd_rcgr = 0x8260, 505 .mnd_width = 16, 506 .hid_width = 5, 507 .parent_map = disp_cc_parent_map_2, 508 .freq_tbl = ftbl_disp_cc_esync0_clk_src, 509 .clkr.hw.init = &(const struct clk_init_data) { 510 .name = "disp_cc_mdss_dptx1_pixel0_clk_src", 511 .parent_data = disp_cc_parent_data_2, 512 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), 513 .flags = CLK_SET_RATE_PARENT, 514 .ops = &clk_dp_ops, 515 }, 516 }; 517 518 static struct clk_rcg2 disp_cc_mdss_dptx1_pixel1_clk_src = { 519 .cmd_rcgr = 0x8278, 520 .mnd_width = 16, 521 .hid_width = 5, 522 .parent_map = disp_cc_parent_map_2, 523 .freq_tbl = ftbl_disp_cc_esync0_clk_src, 524 .clkr.hw.init = &(const struct clk_init_data) { 525 .name = "disp_cc_mdss_dptx1_pixel1_clk_src", 526 .parent_data = disp_cc_parent_data_2, 527 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), 528 .flags = CLK_SET_RATE_PARENT, 529 .ops = &clk_dp_ops, 530 }, 531 }; 532 533 static struct clk_rcg2 disp_cc_mdss_dptx2_aux_clk_src = { 534 .cmd_rcgr = 0x8310, 535 .mnd_width = 0, 536 .hid_width = 5, 537 .parent_map = disp_cc_parent_map_0, 538 .freq_tbl = ftbl_disp_cc_esync0_clk_src, 539 .clkr.hw.init = &(const struct clk_init_data) { 540 .name = "disp_cc_mdss_dptx2_aux_clk_src", 541 .parent_data = disp_cc_parent_data_0, 542 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), 543 .flags = CLK_SET_RATE_PARENT, 544 .ops = &clk_rcg2_shared_ops, 545 }, 546 }; 547 548 static struct clk_rcg2 disp_cc_mdss_dptx2_link_clk_src = { 549 .cmd_rcgr = 0x82c4, 550 .mnd_width = 0, 551 .hid_width = 5, 552 .parent_map = disp_cc_parent_map_3, 553 .freq_tbl = ftbl_disp_cc_esync0_clk_src, 554 .clkr.hw.init = &(const struct clk_init_data) { 555 .name = "disp_cc_mdss_dptx2_link_clk_src", 556 .parent_data = disp_cc_parent_data_3, 557 .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), 558 .flags = CLK_SET_RATE_PARENT, 559 .ops = &clk_byte2_ops, 560 }, 561 }; 562 563 static struct clk_rcg2 disp_cc_mdss_dptx2_pixel0_clk_src = { 564 .cmd_rcgr = 0x82e0, 565 .mnd_width = 16, 566 .hid_width = 5, 567 .parent_map = disp_cc_parent_map_2, 568 .freq_tbl = ftbl_disp_cc_esync0_clk_src, 569 .clkr.hw.init = &(const struct clk_init_data) { 570 .name = "disp_cc_mdss_dptx2_pixel0_clk_src", 571 .parent_data = disp_cc_parent_data_2, 572 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), 573 .flags = CLK_SET_RATE_PARENT, 574 .ops = &clk_dp_ops, 575 }, 576 }; 577 578 static struct clk_rcg2 disp_cc_mdss_dptx2_pixel1_clk_src = { 579 .cmd_rcgr = 0x82f8, 580 .mnd_width = 16, 581 .hid_width = 5, 582 .parent_map = disp_cc_parent_map_2, 583 .freq_tbl = ftbl_disp_cc_esync0_clk_src, 584 .clkr.hw.init = &(const struct clk_init_data) { 585 .name = "disp_cc_mdss_dptx2_pixel1_clk_src", 586 .parent_data = disp_cc_parent_data_2, 587 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), 588 .flags = CLK_SET_RATE_PARENT, 589 .ops = &clk_dp_ops, 590 }, 591 }; 592 593 static struct clk_rcg2 disp_cc_mdss_dptx3_aux_clk_src = { 594 .cmd_rcgr = 0x835c, 595 .mnd_width = 0, 596 .hid_width = 5, 597 .parent_map = disp_cc_parent_map_0, 598 .freq_tbl = ftbl_disp_cc_esync0_clk_src, 599 .clkr.hw.init = &(const struct clk_init_data) { 600 .name = "disp_cc_mdss_dptx3_aux_clk_src", 601 .parent_data = disp_cc_parent_data_0, 602 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), 603 .flags = CLK_SET_RATE_PARENT, 604 .ops = &clk_rcg2_shared_ops, 605 }, 606 }; 607 608 static struct clk_rcg2 disp_cc_mdss_dptx3_link_clk_src = { 609 .cmd_rcgr = 0x8340, 610 .mnd_width = 0, 611 .hid_width = 5, 612 .parent_map = disp_cc_parent_map_3, 613 .freq_tbl = ftbl_disp_cc_esync0_clk_src, 614 .clkr.hw.init = &(const struct clk_init_data) { 615 .name = "disp_cc_mdss_dptx3_link_clk_src", 616 .parent_data = disp_cc_parent_data_3, 617 .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), 618 .flags = CLK_SET_RATE_PARENT, 619 .ops = &clk_byte2_ops, 620 }, 621 }; 622 623 static struct clk_rcg2 disp_cc_mdss_dptx3_pixel0_clk_src = { 624 .cmd_rcgr = 0x8328, 625 .mnd_width = 16, 626 .hid_width = 5, 627 .parent_map = disp_cc_parent_map_2, 628 .freq_tbl = ftbl_disp_cc_esync0_clk_src, 629 .clkr.hw.init = &(const struct clk_init_data) { 630 .name = "disp_cc_mdss_dptx3_pixel0_clk_src", 631 .parent_data = disp_cc_parent_data_2, 632 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), 633 .flags = CLK_SET_RATE_PARENT, 634 .ops = &clk_dp_ops, 635 }, 636 }; 637 638 static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = { 639 .cmd_rcgr = 0x81cc, 640 .mnd_width = 0, 641 .hid_width = 5, 642 .parent_map = disp_cc_parent_map_6, 643 .freq_tbl = ftbl_disp_cc_esync0_clk_src, 644 .clkr.hw.init = &(const struct clk_init_data) { 645 .name = "disp_cc_mdss_esc0_clk_src", 646 .parent_data = disp_cc_parent_data_6, 647 .num_parents = ARRAY_SIZE(disp_cc_parent_data_6), 648 .flags = CLK_SET_RATE_PARENT, 649 .ops = &clk_rcg2_shared_ops, 650 }, 651 }; 652 653 static struct clk_rcg2 disp_cc_mdss_esc1_clk_src = { 654 .cmd_rcgr = 0x81e4, 655 .mnd_width = 0, 656 .hid_width = 5, 657 .parent_map = disp_cc_parent_map_6, 658 .freq_tbl = ftbl_disp_cc_esync0_clk_src, 659 .clkr.hw.init = &(const struct clk_init_data) { 660 .name = "disp_cc_mdss_esc1_clk_src", 661 .parent_data = disp_cc_parent_data_6, 662 .num_parents = ARRAY_SIZE(disp_cc_parent_data_6), 663 .flags = CLK_SET_RATE_PARENT, 664 .ops = &clk_rcg2_shared_ops, 665 }, 666 }; 667 668 static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] = { 669 F(19200000, P_BI_TCXO, 1, 0, 0), 670 F(85714286, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 671 F(100000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 672 F(156000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 673 F(207000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 674 F(337000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 675 F(417000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 676 F(532000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 677 F(600000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 678 F(650000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 679 { } 680 }; 681 682 static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = { 683 .cmd_rcgr = 0x8164, 684 .mnd_width = 0, 685 .hid_width = 5, 686 .parent_map = disp_cc_parent_map_9, 687 .freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src, 688 .hw_clk_ctrl = true, 689 .clkr.hw.init = &(const struct clk_init_data) { 690 .name = "disp_cc_mdss_mdp_clk_src", 691 .parent_data = disp_cc_parent_data_9, 692 .num_parents = ARRAY_SIZE(disp_cc_parent_data_9), 693 .flags = CLK_SET_RATE_PARENT, 694 .ops = &clk_rcg2_shared_ops, 695 }, 696 }; 697 698 static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = { 699 .cmd_rcgr = 0x811c, 700 .mnd_width = 8, 701 .hid_width = 5, 702 .parent_map = disp_cc_parent_map_1, 703 .freq_tbl = ftbl_disp_cc_esync0_clk_src, 704 .clkr.hw.init = &(const struct clk_init_data) { 705 .name = "disp_cc_mdss_pclk0_clk_src", 706 .parent_data = disp_cc_parent_data_1, 707 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), 708 .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, 709 .ops = &clk_pixel_ops, 710 }, 711 }; 712 713 static struct clk_rcg2 disp_cc_mdss_pclk1_clk_src = { 714 .cmd_rcgr = 0x8134, 715 .mnd_width = 8, 716 .hid_width = 5, 717 .parent_map = disp_cc_parent_map_1, 718 .freq_tbl = ftbl_disp_cc_esync0_clk_src, 719 .clkr.hw.init = &(const struct clk_init_data) { 720 .name = "disp_cc_mdss_pclk1_clk_src", 721 .parent_data = disp_cc_parent_data_1, 722 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), 723 .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, 724 .ops = &clk_pixel_ops, 725 }, 726 }; 727 728 static struct clk_rcg2 disp_cc_mdss_pclk2_clk_src = { 729 .cmd_rcgr = 0x814c, 730 .mnd_width = 8, 731 .hid_width = 5, 732 .parent_map = disp_cc_parent_map_1, 733 .freq_tbl = ftbl_disp_cc_esync0_clk_src, 734 .clkr.hw.init = &(const struct clk_init_data) { 735 .name = "disp_cc_mdss_pclk2_clk_src", 736 .parent_data = disp_cc_parent_data_1, 737 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), 738 .flags = CLK_SET_RATE_PARENT, 739 .ops = &clk_pixel_ops, 740 }, 741 }; 742 743 static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = { 744 .cmd_rcgr = 0x817c, 745 .mnd_width = 0, 746 .hid_width = 5, 747 .parent_map = disp_cc_parent_map_0, 748 .freq_tbl = ftbl_disp_cc_esync0_clk_src, 749 .clkr.hw.init = &(const struct clk_init_data) { 750 .name = "disp_cc_mdss_vsync_clk_src", 751 .parent_data = disp_cc_parent_data_0, 752 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), 753 .flags = CLK_SET_RATE_PARENT, 754 .ops = &clk_rcg2_shared_ops, 755 }, 756 }; 757 758 static const struct freq_tbl ftbl_disp_cc_osc_clk_src[] = { 759 F(38400000, P_DISP_CC_PLL2_OUT_MAIN, 1, 0, 0), 760 { } 761 }; 762 763 static struct clk_rcg2 disp_cc_osc_clk_src = { 764 .cmd_rcgr = 0x8104, 765 .mnd_width = 0, 766 .hid_width = 5, 767 .parent_map = disp_cc_parent_map_10, 768 .freq_tbl = ftbl_disp_cc_osc_clk_src, 769 .clkr.hw.init = &(const struct clk_init_data) { 770 .name = "disp_cc_osc_clk_src", 771 .parent_data = disp_cc_parent_data_10, 772 .num_parents = ARRAY_SIZE(disp_cc_parent_data_10), 773 .flags = CLK_SET_RATE_PARENT, 774 .ops = &clk_rcg2_shared_ops, 775 }, 776 }; 777 778 static struct clk_regmap_div disp_cc_mdss_ahb_swi_div_clk_src = { 779 .reg = 0x8374, 780 .shift = 0, 781 .width = 4, 782 .clkr.hw.init = &(const struct clk_init_data) { 783 .name = "disp_cc_mdss_ahb_swi_div_clk_src", 784 .parent_hws = (const struct clk_hw*[]) { 785 &disp_cc_mdss_ahb_clk_src.clkr.hw, 786 }, 787 .num_parents = 1, 788 .flags = CLK_SET_RATE_PARENT, 789 .ops = &clk_regmap_div_ro_ops, 790 }, 791 }; 792 793 static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = { 794 .reg = 0x81ac, 795 .shift = 0, 796 .width = 4, 797 .clkr.hw.init = &(const struct clk_init_data) { 798 .name = "disp_cc_mdss_byte0_div_clk_src", 799 .parent_hws = (const struct clk_hw*[]) { 800 &disp_cc_mdss_byte0_clk_src.clkr.hw, 801 }, 802 .num_parents = 1, 803 .flags = CLK_SET_RATE_PARENT, 804 .ops = &clk_regmap_div_ops, 805 }, 806 }; 807 808 static struct clk_regmap_div disp_cc_mdss_byte1_div_clk_src = { 809 .reg = 0x81c8, 810 .shift = 0, 811 .width = 4, 812 .clkr.hw.init = &(const struct clk_init_data) { 813 .name = "disp_cc_mdss_byte1_div_clk_src", 814 .parent_hws = (const struct clk_hw*[]) { 815 &disp_cc_mdss_byte1_clk_src.clkr.hw, 816 }, 817 .num_parents = 1, 818 .flags = CLK_SET_RATE_PARENT, 819 .ops = &clk_regmap_div_ops, 820 }, 821 }; 822 823 static struct clk_regmap_div disp_cc_mdss_dptx0_link_div_clk_src = { 824 .reg = 0x8214, 825 .shift = 0, 826 .width = 4, 827 .clkr.hw.init = &(const struct clk_init_data) { 828 .name = "disp_cc_mdss_dptx0_link_div_clk_src", 829 .parent_hws = (const struct clk_hw*[]) { 830 &disp_cc_mdss_dptx0_link_clk_src.clkr.hw, 831 }, 832 .num_parents = 1, 833 .flags = CLK_SET_RATE_PARENT, 834 .ops = &clk_regmap_div_ro_ops, 835 }, 836 }; 837 838 static struct clk_regmap_div disp_cc_mdss_dptx1_link_div_clk_src = { 839 .reg = 0x82a8, 840 .shift = 0, 841 .width = 4, 842 .clkr.hw.init = &(const struct clk_init_data) { 843 .name = "disp_cc_mdss_dptx1_link_div_clk_src", 844 .parent_hws = (const struct clk_hw*[]) { 845 &disp_cc_mdss_dptx1_link_clk_src.clkr.hw, 846 }, 847 .num_parents = 1, 848 .flags = CLK_SET_RATE_PARENT, 849 .ops = &clk_regmap_div_ro_ops, 850 }, 851 }; 852 853 static struct clk_regmap_div disp_cc_mdss_dptx2_link_div_clk_src = { 854 .reg = 0x82dc, 855 .shift = 0, 856 .width = 4, 857 .clkr.hw.init = &(const struct clk_init_data) { 858 .name = "disp_cc_mdss_dptx2_link_div_clk_src", 859 .parent_hws = (const struct clk_hw*[]) { 860 &disp_cc_mdss_dptx2_link_clk_src.clkr.hw, 861 }, 862 .num_parents = 1, 863 .flags = CLK_SET_RATE_PARENT, 864 .ops = &clk_regmap_div_ro_ops, 865 }, 866 }; 867 868 static struct clk_regmap_div disp_cc_mdss_dptx3_link_div_clk_src = { 869 .reg = 0x8358, 870 .shift = 0, 871 .width = 4, 872 .clkr.hw.init = &(const struct clk_init_data) { 873 .name = "disp_cc_mdss_dptx3_link_div_clk_src", 874 .parent_hws = (const struct clk_hw*[]) { 875 &disp_cc_mdss_dptx3_link_clk_src.clkr.hw, 876 }, 877 .num_parents = 1, 878 .flags = CLK_SET_RATE_PARENT, 879 .ops = &clk_regmap_div_ro_ops, 880 }, 881 }; 882 883 static struct clk_branch disp_cc_esync0_clk = { 884 .halt_reg = 0x80cc, 885 .halt_check = BRANCH_HALT, 886 .clkr = { 887 .enable_reg = 0x80cc, 888 .enable_mask = BIT(0), 889 .hw.init = &(const struct clk_init_data) { 890 .name = "disp_cc_esync0_clk", 891 .parent_hws = (const struct clk_hw*[]) { 892 &disp_cc_esync0_clk_src.clkr.hw, 893 }, 894 .num_parents = 1, 895 .flags = CLK_SET_RATE_PARENT, 896 .ops = &clk_branch2_ops, 897 }, 898 }, 899 }; 900 901 static struct clk_branch disp_cc_esync1_clk = { 902 .halt_reg = 0x80d0, 903 .halt_check = BRANCH_HALT, 904 .clkr = { 905 .enable_reg = 0x80d0, 906 .enable_mask = BIT(0), 907 .hw.init = &(const struct clk_init_data) { 908 .name = "disp_cc_esync1_clk", 909 .parent_hws = (const struct clk_hw*[]) { 910 &disp_cc_esync1_clk_src.clkr.hw, 911 }, 912 .num_parents = 1, 913 .flags = CLK_SET_RATE_PARENT, 914 .ops = &clk_branch2_ops, 915 }, 916 }, 917 }; 918 919 static struct clk_branch disp_cc_mdss_accu_shift_clk = { 920 .halt_reg = 0xe060, 921 .halt_check = BRANCH_HALT_VOTED, 922 .clkr = { 923 .enable_reg = 0xe060, 924 .enable_mask = BIT(0), 925 .hw.init = &(const struct clk_init_data) { 926 .name = "disp_cc_mdss_accu_shift_clk", 927 .ops = &clk_branch2_ops, 928 }, 929 }, 930 }; 931 932 static struct clk_branch disp_cc_mdss_ahb1_clk = { 933 .halt_reg = 0xa028, 934 .halt_check = BRANCH_HALT, 935 .clkr = { 936 .enable_reg = 0xa028, 937 .enable_mask = BIT(0), 938 .hw.init = &(const struct clk_init_data) { 939 .name = "disp_cc_mdss_ahb1_clk", 940 .parent_hws = (const struct clk_hw*[]) { 941 &disp_cc_mdss_ahb_clk_src.clkr.hw, 942 }, 943 .num_parents = 1, 944 .flags = CLK_SET_RATE_PARENT, 945 .ops = &clk_branch2_ops, 946 }, 947 }, 948 }; 949 950 static struct clk_branch disp_cc_mdss_ahb_clk = { 951 .halt_reg = 0x80c4, 952 .halt_check = BRANCH_HALT, 953 .clkr = { 954 .enable_reg = 0x80c4, 955 .enable_mask = BIT(0), 956 .hw.init = &(const struct clk_init_data) { 957 .name = "disp_cc_mdss_ahb_clk", 958 .parent_hws = (const struct clk_hw*[]) { 959 &disp_cc_mdss_ahb_clk_src.clkr.hw, 960 }, 961 .num_parents = 1, 962 .flags = CLK_SET_RATE_PARENT, 963 .ops = &clk_branch2_ops, 964 }, 965 }, 966 }; 967 968 static struct clk_branch disp_cc_mdss_ahb_swi_clk = { 969 .halt_reg = 0x80c0, 970 .halt_check = BRANCH_HALT, 971 .clkr = { 972 .enable_reg = 0x80c0, 973 .enable_mask = BIT(0), 974 .hw.init = &(const struct clk_init_data) { 975 .name = "disp_cc_mdss_ahb_swi_clk", 976 .parent_hws = (const struct clk_hw*[]) { 977 &disp_cc_mdss_ahb_swi_div_clk_src.clkr.hw, 978 }, 979 .num_parents = 1, 980 .flags = CLK_SET_RATE_PARENT, 981 .ops = &clk_branch2_ops, 982 }, 983 }, 984 }; 985 986 static struct clk_branch disp_cc_mdss_byte0_clk = { 987 .halt_reg = 0x8044, 988 .halt_check = BRANCH_HALT, 989 .clkr = { 990 .enable_reg = 0x8044, 991 .enable_mask = BIT(0), 992 .hw.init = &(const struct clk_init_data) { 993 .name = "disp_cc_mdss_byte0_clk", 994 .parent_hws = (const struct clk_hw*[]) { 995 &disp_cc_mdss_byte0_clk_src.clkr.hw, 996 }, 997 .num_parents = 1, 998 .flags = CLK_SET_RATE_PARENT, 999 .ops = &clk_branch2_ops, 1000 }, 1001 }, 1002 }; 1003 1004 static struct clk_branch disp_cc_mdss_byte0_intf_clk = { 1005 .halt_reg = 0x8048, 1006 .halt_check = BRANCH_HALT, 1007 .clkr = { 1008 .enable_reg = 0x8048, 1009 .enable_mask = BIT(0), 1010 .hw.init = &(const struct clk_init_data) { 1011 .name = "disp_cc_mdss_byte0_intf_clk", 1012 .parent_hws = (const struct clk_hw*[]) { 1013 &disp_cc_mdss_byte0_div_clk_src.clkr.hw, 1014 }, 1015 .num_parents = 1, 1016 .flags = CLK_SET_RATE_PARENT, 1017 .ops = &clk_branch2_ops, 1018 }, 1019 }, 1020 }; 1021 1022 static struct clk_branch disp_cc_mdss_byte1_clk = { 1023 .halt_reg = 0x804c, 1024 .halt_check = BRANCH_HALT, 1025 .clkr = { 1026 .enable_reg = 0x804c, 1027 .enable_mask = BIT(0), 1028 .hw.init = &(const struct clk_init_data) { 1029 .name = "disp_cc_mdss_byte1_clk", 1030 .parent_hws = (const struct clk_hw*[]) { 1031 &disp_cc_mdss_byte1_clk_src.clkr.hw, 1032 }, 1033 .num_parents = 1, 1034 .flags = CLK_SET_RATE_PARENT, 1035 .ops = &clk_branch2_ops, 1036 }, 1037 }, 1038 }; 1039 1040 static struct clk_branch disp_cc_mdss_byte1_intf_clk = { 1041 .halt_reg = 0x8050, 1042 .halt_check = BRANCH_HALT, 1043 .clkr = { 1044 .enable_reg = 0x8050, 1045 .enable_mask = BIT(0), 1046 .hw.init = &(const struct clk_init_data) { 1047 .name = "disp_cc_mdss_byte1_intf_clk", 1048 .parent_hws = (const struct clk_hw*[]) { 1049 &disp_cc_mdss_byte1_div_clk_src.clkr.hw, 1050 }, 1051 .num_parents = 1, 1052 .flags = CLK_SET_RATE_PARENT, 1053 .ops = &clk_branch2_ops, 1054 }, 1055 }, 1056 }; 1057 1058 static struct clk_branch disp_cc_mdss_dptx0_aux_clk = { 1059 .halt_reg = 0x8074, 1060 .halt_check = BRANCH_HALT, 1061 .clkr = { 1062 .enable_reg = 0x8074, 1063 .enable_mask = BIT(0), 1064 .hw.init = &(const struct clk_init_data) { 1065 .name = "disp_cc_mdss_dptx0_aux_clk", 1066 .parent_hws = (const struct clk_hw*[]) { 1067 &disp_cc_mdss_dptx0_aux_clk_src.clkr.hw, 1068 }, 1069 .num_parents = 1, 1070 .flags = CLK_SET_RATE_PARENT, 1071 .ops = &clk_branch2_ops, 1072 }, 1073 }, 1074 }; 1075 1076 static struct clk_branch disp_cc_mdss_dptx0_crypto_clk = { 1077 .halt_reg = 0x8068, 1078 .halt_check = BRANCH_HALT_VOTED, 1079 .clkr = { 1080 .enable_reg = 0x8068, 1081 .enable_mask = BIT(0), 1082 .hw.init = &(const struct clk_init_data) { 1083 .name = "disp_cc_mdss_dptx0_crypto_clk", 1084 .parent_hws = (const struct clk_hw*[]) { 1085 &disp_cc_mdss_dptx0_link_clk_src.clkr.hw, 1086 }, 1087 .num_parents = 1, 1088 .flags = CLK_SET_RATE_PARENT, 1089 .ops = &clk_branch2_ops, 1090 }, 1091 }, 1092 }; 1093 1094 static struct clk_branch disp_cc_mdss_dptx0_link_clk = { 1095 .halt_reg = 0x805c, 1096 .halt_check = BRANCH_HALT, 1097 .clkr = { 1098 .enable_reg = 0x805c, 1099 .enable_mask = BIT(0), 1100 .hw.init = &(const struct clk_init_data) { 1101 .name = "disp_cc_mdss_dptx0_link_clk", 1102 .parent_hws = (const struct clk_hw*[]) { 1103 &disp_cc_mdss_dptx0_link_clk_src.clkr.hw, 1104 }, 1105 .num_parents = 1, 1106 .flags = CLK_SET_RATE_PARENT, 1107 .ops = &clk_branch2_ops, 1108 }, 1109 }, 1110 }; 1111 1112 static struct clk_branch disp_cc_mdss_dptx0_link_intf_clk = { 1113 .halt_reg = 0x8064, 1114 .halt_check = BRANCH_HALT, 1115 .clkr = { 1116 .enable_reg = 0x8064, 1117 .enable_mask = BIT(0), 1118 .hw.init = &(const struct clk_init_data) { 1119 .name = "disp_cc_mdss_dptx0_link_intf_clk", 1120 .parent_hws = (const struct clk_hw*[]) { 1121 &disp_cc_mdss_dptx0_link_div_clk_src.clkr.hw, 1122 }, 1123 .num_parents = 1, 1124 .flags = CLK_SET_RATE_PARENT, 1125 .ops = &clk_branch2_ops, 1126 }, 1127 }, 1128 }; 1129 1130 static struct clk_branch disp_cc_mdss_dptx0_pixel0_clk = { 1131 .halt_reg = 0x806c, 1132 .halt_check = BRANCH_HALT, 1133 .clkr = { 1134 .enable_reg = 0x806c, 1135 .enable_mask = BIT(0), 1136 .hw.init = &(const struct clk_init_data) { 1137 .name = "disp_cc_mdss_dptx0_pixel0_clk", 1138 .parent_hws = (const struct clk_hw*[]) { 1139 &disp_cc_mdss_dptx0_pixel0_clk_src.clkr.hw, 1140 }, 1141 .num_parents = 1, 1142 .flags = CLK_SET_RATE_PARENT, 1143 .ops = &clk_branch2_ops, 1144 }, 1145 }, 1146 }; 1147 1148 static struct clk_branch disp_cc_mdss_dptx0_pixel1_clk = { 1149 .halt_reg = 0x8070, 1150 .halt_check = BRANCH_HALT, 1151 .clkr = { 1152 .enable_reg = 0x8070, 1153 .enable_mask = BIT(0), 1154 .hw.init = &(const struct clk_init_data) { 1155 .name = "disp_cc_mdss_dptx0_pixel1_clk", 1156 .parent_hws = (const struct clk_hw*[]) { 1157 &disp_cc_mdss_dptx0_pixel1_clk_src.clkr.hw, 1158 }, 1159 .num_parents = 1, 1160 .flags = CLK_SET_RATE_PARENT, 1161 .ops = &clk_branch2_ops, 1162 }, 1163 }, 1164 }; 1165 1166 static struct clk_branch disp_cc_mdss_dptx0_usb_router_link_intf_clk = { 1167 .halt_reg = 0x8060, 1168 .halt_check = BRANCH_HALT, 1169 .clkr = { 1170 .enable_reg = 0x8060, 1171 .enable_mask = BIT(0), 1172 .hw.init = &(const struct clk_init_data) { 1173 .name = "disp_cc_mdss_dptx0_usb_router_link_intf_clk", 1174 .parent_hws = (const struct clk_hw*[]) { 1175 &disp_cc_mdss_dptx0_link_div_clk_src.clkr.hw, 1176 }, 1177 .num_parents = 1, 1178 .flags = CLK_SET_RATE_PARENT, 1179 .ops = &clk_branch2_ops, 1180 }, 1181 }, 1182 }; 1183 1184 static struct clk_branch disp_cc_mdss_dptx1_aux_clk = { 1185 .halt_reg = 0x8090, 1186 .halt_check = BRANCH_HALT, 1187 .clkr = { 1188 .enable_reg = 0x8090, 1189 .enable_mask = BIT(0), 1190 .hw.init = &(const struct clk_init_data) { 1191 .name = "disp_cc_mdss_dptx1_aux_clk", 1192 .parent_hws = (const struct clk_hw*[]) { 1193 &disp_cc_mdss_dptx1_aux_clk_src.clkr.hw, 1194 }, 1195 .num_parents = 1, 1196 .flags = CLK_SET_RATE_PARENT, 1197 .ops = &clk_branch2_ops, 1198 }, 1199 }, 1200 }; 1201 1202 static struct clk_branch disp_cc_mdss_dptx1_crypto_clk = { 1203 .halt_reg = 0x808c, 1204 .halt_check = BRANCH_HALT_VOTED, 1205 .clkr = { 1206 .enable_reg = 0x808c, 1207 .enable_mask = BIT(0), 1208 .hw.init = &(const struct clk_init_data) { 1209 .name = "disp_cc_mdss_dptx1_crypto_clk", 1210 .parent_hws = (const struct clk_hw*[]) { 1211 &disp_cc_mdss_dptx1_link_clk_src.clkr.hw, 1212 }, 1213 .num_parents = 1, 1214 .flags = CLK_SET_RATE_PARENT, 1215 .ops = &clk_branch2_ops, 1216 }, 1217 }, 1218 }; 1219 1220 static struct clk_branch disp_cc_mdss_dptx1_link_clk = { 1221 .halt_reg = 0x8080, 1222 .halt_check = BRANCH_HALT, 1223 .clkr = { 1224 .enable_reg = 0x8080, 1225 .enable_mask = BIT(0), 1226 .hw.init = &(const struct clk_init_data) { 1227 .name = "disp_cc_mdss_dptx1_link_clk", 1228 .parent_hws = (const struct clk_hw*[]) { 1229 &disp_cc_mdss_dptx1_link_clk_src.clkr.hw, 1230 }, 1231 .num_parents = 1, 1232 .flags = CLK_SET_RATE_PARENT, 1233 .ops = &clk_branch2_ops, 1234 }, 1235 }, 1236 }; 1237 1238 static struct clk_branch disp_cc_mdss_dptx1_link_intf_clk = { 1239 .halt_reg = 0x8088, 1240 .halt_check = BRANCH_HALT, 1241 .clkr = { 1242 .enable_reg = 0x8088, 1243 .enable_mask = BIT(0), 1244 .hw.init = &(const struct clk_init_data) { 1245 .name = "disp_cc_mdss_dptx1_link_intf_clk", 1246 .parent_hws = (const struct clk_hw*[]) { 1247 &disp_cc_mdss_dptx1_link_div_clk_src.clkr.hw, 1248 }, 1249 .num_parents = 1, 1250 .flags = CLK_SET_RATE_PARENT, 1251 .ops = &clk_branch2_ops, 1252 }, 1253 }, 1254 }; 1255 1256 static struct clk_branch disp_cc_mdss_dptx1_pixel0_clk = { 1257 .halt_reg = 0x8078, 1258 .halt_check = BRANCH_HALT, 1259 .clkr = { 1260 .enable_reg = 0x8078, 1261 .enable_mask = BIT(0), 1262 .hw.init = &(const struct clk_init_data) { 1263 .name = "disp_cc_mdss_dptx1_pixel0_clk", 1264 .parent_hws = (const struct clk_hw*[]) { 1265 &disp_cc_mdss_dptx1_pixel0_clk_src.clkr.hw, 1266 }, 1267 .num_parents = 1, 1268 .flags = CLK_SET_RATE_PARENT, 1269 .ops = &clk_branch2_ops, 1270 }, 1271 }, 1272 }; 1273 1274 static struct clk_branch disp_cc_mdss_dptx1_pixel1_clk = { 1275 .halt_reg = 0x807c, 1276 .halt_check = BRANCH_HALT, 1277 .clkr = { 1278 .enable_reg = 0x807c, 1279 .enable_mask = BIT(0), 1280 .hw.init = &(const struct clk_init_data) { 1281 .name = "disp_cc_mdss_dptx1_pixel1_clk", 1282 .parent_hws = (const struct clk_hw*[]) { 1283 &disp_cc_mdss_dptx1_pixel1_clk_src.clkr.hw, 1284 }, 1285 .num_parents = 1, 1286 .flags = CLK_SET_RATE_PARENT, 1287 .ops = &clk_branch2_ops, 1288 }, 1289 }, 1290 }; 1291 1292 static struct clk_branch disp_cc_mdss_dptx1_usb_router_link_intf_clk = { 1293 .halt_reg = 0x8084, 1294 .halt_check = BRANCH_HALT, 1295 .clkr = { 1296 .enable_reg = 0x8084, 1297 .enable_mask = BIT(0), 1298 .hw.init = &(const struct clk_init_data) { 1299 .name = "disp_cc_mdss_dptx1_usb_router_link_intf_clk", 1300 .parent_hws = (const struct clk_hw*[]) { 1301 &disp_cc_mdss_dptx1_link_div_clk_src.clkr.hw, 1302 }, 1303 .num_parents = 1, 1304 .flags = CLK_SET_RATE_PARENT, 1305 .ops = &clk_branch2_ops, 1306 }, 1307 }, 1308 }; 1309 1310 static struct clk_branch disp_cc_mdss_dptx2_aux_clk = { 1311 .halt_reg = 0x80a8, 1312 .halt_check = BRANCH_HALT, 1313 .clkr = { 1314 .enable_reg = 0x80a8, 1315 .enable_mask = BIT(0), 1316 .hw.init = &(const struct clk_init_data) { 1317 .name = "disp_cc_mdss_dptx2_aux_clk", 1318 .parent_hws = (const struct clk_hw*[]) { 1319 &disp_cc_mdss_dptx2_aux_clk_src.clkr.hw, 1320 }, 1321 .num_parents = 1, 1322 .flags = CLK_SET_RATE_PARENT, 1323 .ops = &clk_branch2_ops, 1324 }, 1325 }, 1326 }; 1327 1328 static struct clk_branch disp_cc_mdss_dptx2_crypto_clk = { 1329 .halt_reg = 0x80a4, 1330 .halt_check = BRANCH_HALT_VOTED, 1331 .clkr = { 1332 .enable_reg = 0x80a4, 1333 .enable_mask = BIT(0), 1334 .hw.init = &(const struct clk_init_data) { 1335 .name = "disp_cc_mdss_dptx2_crypto_clk", 1336 .parent_hws = (const struct clk_hw*[]) { 1337 &disp_cc_mdss_dptx2_link_clk_src.clkr.hw, 1338 }, 1339 .num_parents = 1, 1340 .flags = CLK_SET_RATE_PARENT, 1341 .ops = &clk_branch2_ops, 1342 }, 1343 }, 1344 }; 1345 1346 static struct clk_branch disp_cc_mdss_dptx2_link_clk = { 1347 .halt_reg = 0x809c, 1348 .halt_check = BRANCH_HALT, 1349 .clkr = { 1350 .enable_reg = 0x809c, 1351 .enable_mask = BIT(0), 1352 .hw.init = &(const struct clk_init_data) { 1353 .name = "disp_cc_mdss_dptx2_link_clk", 1354 .parent_hws = (const struct clk_hw*[]) { 1355 &disp_cc_mdss_dptx2_link_clk_src.clkr.hw, 1356 }, 1357 .num_parents = 1, 1358 .flags = CLK_SET_RATE_PARENT, 1359 .ops = &clk_branch2_ops, 1360 }, 1361 }, 1362 }; 1363 1364 static struct clk_branch disp_cc_mdss_dptx2_link_intf_clk = { 1365 .halt_reg = 0x80a0, 1366 .halt_check = BRANCH_HALT, 1367 .clkr = { 1368 .enable_reg = 0x80a0, 1369 .enable_mask = BIT(0), 1370 .hw.init = &(const struct clk_init_data) { 1371 .name = "disp_cc_mdss_dptx2_link_intf_clk", 1372 .parent_hws = (const struct clk_hw*[]) { 1373 &disp_cc_mdss_dptx2_link_div_clk_src.clkr.hw, 1374 }, 1375 .num_parents = 1, 1376 .flags = CLK_SET_RATE_PARENT, 1377 .ops = &clk_branch2_ops, 1378 }, 1379 }, 1380 }; 1381 1382 static struct clk_branch disp_cc_mdss_dptx2_pixel0_clk = { 1383 .halt_reg = 0x8094, 1384 .halt_check = BRANCH_HALT, 1385 .clkr = { 1386 .enable_reg = 0x8094, 1387 .enable_mask = BIT(0), 1388 .hw.init = &(const struct clk_init_data) { 1389 .name = "disp_cc_mdss_dptx2_pixel0_clk", 1390 .parent_hws = (const struct clk_hw*[]) { 1391 &disp_cc_mdss_dptx2_pixel0_clk_src.clkr.hw, 1392 }, 1393 .num_parents = 1, 1394 .flags = CLK_SET_RATE_PARENT, 1395 .ops = &clk_branch2_ops, 1396 }, 1397 }, 1398 }; 1399 1400 static struct clk_branch disp_cc_mdss_dptx2_pixel1_clk = { 1401 .halt_reg = 0x8098, 1402 .halt_check = BRANCH_HALT, 1403 .clkr = { 1404 .enable_reg = 0x8098, 1405 .enable_mask = BIT(0), 1406 .hw.init = &(const struct clk_init_data) { 1407 .name = "disp_cc_mdss_dptx2_pixel1_clk", 1408 .parent_hws = (const struct clk_hw*[]) { 1409 &disp_cc_mdss_dptx2_pixel1_clk_src.clkr.hw, 1410 }, 1411 .num_parents = 1, 1412 .flags = CLK_SET_RATE_PARENT, 1413 .ops = &clk_branch2_ops, 1414 }, 1415 }, 1416 }; 1417 1418 static struct clk_branch disp_cc_mdss_dptx3_aux_clk = { 1419 .halt_reg = 0x80b8, 1420 .halt_check = BRANCH_HALT, 1421 .clkr = { 1422 .enable_reg = 0x80b8, 1423 .enable_mask = BIT(0), 1424 .hw.init = &(const struct clk_init_data) { 1425 .name = "disp_cc_mdss_dptx3_aux_clk", 1426 .parent_hws = (const struct clk_hw*[]) { 1427 &disp_cc_mdss_dptx3_aux_clk_src.clkr.hw, 1428 }, 1429 .num_parents = 1, 1430 .flags = CLK_SET_RATE_PARENT, 1431 .ops = &clk_branch2_ops, 1432 }, 1433 }, 1434 }; 1435 1436 static struct clk_branch disp_cc_mdss_dptx3_crypto_clk = { 1437 .halt_reg = 0x80bc, 1438 .halt_check = BRANCH_HALT_VOTED, 1439 .clkr = { 1440 .enable_reg = 0x80bc, 1441 .enable_mask = BIT(0), 1442 .hw.init = &(const struct clk_init_data) { 1443 .name = "disp_cc_mdss_dptx3_crypto_clk", 1444 .parent_hws = (const struct clk_hw*[]) { 1445 &disp_cc_mdss_dptx3_link_clk_src.clkr.hw, 1446 }, 1447 .num_parents = 1, 1448 .flags = CLK_SET_RATE_PARENT, 1449 .ops = &clk_branch2_ops, 1450 }, 1451 }, 1452 }; 1453 1454 static struct clk_branch disp_cc_mdss_dptx3_link_clk = { 1455 .halt_reg = 0x80b0, 1456 .halt_check = BRANCH_HALT, 1457 .clkr = { 1458 .enable_reg = 0x80b0, 1459 .enable_mask = BIT(0), 1460 .hw.init = &(const struct clk_init_data) { 1461 .name = "disp_cc_mdss_dptx3_link_clk", 1462 .parent_hws = (const struct clk_hw*[]) { 1463 &disp_cc_mdss_dptx3_link_clk_src.clkr.hw, 1464 }, 1465 .num_parents = 1, 1466 .flags = CLK_SET_RATE_PARENT, 1467 .ops = &clk_branch2_ops, 1468 }, 1469 }, 1470 }; 1471 1472 static struct clk_branch disp_cc_mdss_dptx3_link_intf_clk = { 1473 .halt_reg = 0x80b4, 1474 .halt_check = BRANCH_HALT, 1475 .clkr = { 1476 .enable_reg = 0x80b4, 1477 .enable_mask = BIT(0), 1478 .hw.init = &(const struct clk_init_data) { 1479 .name = "disp_cc_mdss_dptx3_link_intf_clk", 1480 .parent_hws = (const struct clk_hw*[]) { 1481 &disp_cc_mdss_dptx3_link_div_clk_src.clkr.hw, 1482 }, 1483 .num_parents = 1, 1484 .flags = CLK_SET_RATE_PARENT, 1485 .ops = &clk_branch2_ops, 1486 }, 1487 }, 1488 }; 1489 1490 static struct clk_branch disp_cc_mdss_dptx3_pixel0_clk = { 1491 .halt_reg = 0x80ac, 1492 .halt_check = BRANCH_HALT, 1493 .clkr = { 1494 .enable_reg = 0x80ac, 1495 .enable_mask = BIT(0), 1496 .hw.init = &(const struct clk_init_data) { 1497 .name = "disp_cc_mdss_dptx3_pixel0_clk", 1498 .parent_hws = (const struct clk_hw*[]) { 1499 &disp_cc_mdss_dptx3_pixel0_clk_src.clkr.hw, 1500 }, 1501 .num_parents = 1, 1502 .flags = CLK_SET_RATE_PARENT, 1503 .ops = &clk_branch2_ops, 1504 }, 1505 }, 1506 }; 1507 1508 static struct clk_branch disp_cc_mdss_esc0_clk = { 1509 .halt_reg = 0x8054, 1510 .halt_check = BRANCH_HALT, 1511 .clkr = { 1512 .enable_reg = 0x8054, 1513 .enable_mask = BIT(0), 1514 .hw.init = &(const struct clk_init_data) { 1515 .name = "disp_cc_mdss_esc0_clk", 1516 .parent_hws = (const struct clk_hw*[]) { 1517 &disp_cc_mdss_esc0_clk_src.clkr.hw, 1518 }, 1519 .num_parents = 1, 1520 .flags = CLK_SET_RATE_PARENT, 1521 .ops = &clk_branch2_ops, 1522 }, 1523 }, 1524 }; 1525 1526 static struct clk_branch disp_cc_mdss_esc1_clk = { 1527 .halt_reg = 0x8058, 1528 .halt_check = BRANCH_HALT, 1529 .clkr = { 1530 .enable_reg = 0x8058, 1531 .enable_mask = BIT(0), 1532 .hw.init = &(const struct clk_init_data) { 1533 .name = "disp_cc_mdss_esc1_clk", 1534 .parent_hws = (const struct clk_hw*[]) { 1535 &disp_cc_mdss_esc1_clk_src.clkr.hw, 1536 }, 1537 .num_parents = 1, 1538 .flags = CLK_SET_RATE_PARENT, 1539 .ops = &clk_branch2_ops, 1540 }, 1541 }, 1542 }; 1543 1544 static struct clk_branch disp_cc_mdss_mdp1_clk = { 1545 .halt_reg = 0xa004, 1546 .halt_check = BRANCH_HALT, 1547 .clkr = { 1548 .enable_reg = 0xa004, 1549 .enable_mask = BIT(0), 1550 .hw.init = &(const struct clk_init_data) { 1551 .name = "disp_cc_mdss_mdp1_clk", 1552 .parent_hws = (const struct clk_hw*[]) { 1553 &disp_cc_mdss_mdp_clk_src.clkr.hw, 1554 }, 1555 .num_parents = 1, 1556 .flags = CLK_SET_RATE_PARENT, 1557 .ops = &clk_branch2_ops, 1558 }, 1559 }, 1560 }; 1561 1562 static struct clk_branch disp_cc_mdss_mdp_clk = { 1563 .halt_reg = 0x8010, 1564 .halt_check = BRANCH_HALT_VOTED, 1565 .clkr = { 1566 .enable_reg = 0x8010, 1567 .enable_mask = BIT(0), 1568 .hw.init = &(const struct clk_init_data) { 1569 .name = "disp_cc_mdss_mdp_clk", 1570 .parent_hws = (const struct clk_hw*[]) { 1571 &disp_cc_mdss_mdp_clk_src.clkr.hw, 1572 }, 1573 .num_parents = 1, 1574 .flags = CLK_SET_RATE_PARENT, 1575 .ops = &clk_branch2_aon_ops, 1576 }, 1577 }, 1578 }; 1579 1580 static struct clk_branch disp_cc_mdss_mdp_lut1_clk = { 1581 .halt_reg = 0xa014, 1582 .halt_check = BRANCH_HALT_VOTED, 1583 .clkr = { 1584 .enable_reg = 0xa014, 1585 .enable_mask = BIT(0), 1586 .hw.init = &(const struct clk_init_data) { 1587 .name = "disp_cc_mdss_mdp_lut1_clk", 1588 .parent_hws = (const struct clk_hw*[]) { 1589 &disp_cc_mdss_mdp_clk_src.clkr.hw, 1590 }, 1591 .num_parents = 1, 1592 .flags = CLK_SET_RATE_PARENT, 1593 .ops = &clk_branch2_ops, 1594 }, 1595 }, 1596 }; 1597 1598 static struct clk_branch disp_cc_mdss_mdp_lut_clk = { 1599 .halt_reg = 0x8020, 1600 .halt_check = BRANCH_HALT_VOTED, 1601 .clkr = { 1602 .enable_reg = 0x8020, 1603 .enable_mask = BIT(0), 1604 .hw.init = &(const struct clk_init_data) { 1605 .name = "disp_cc_mdss_mdp_lut_clk", 1606 .parent_hws = (const struct clk_hw*[]) { 1607 &disp_cc_mdss_mdp_clk_src.clkr.hw, 1608 }, 1609 .num_parents = 1, 1610 .flags = CLK_SET_RATE_PARENT, 1611 .ops = &clk_branch2_ops, 1612 }, 1613 }, 1614 }; 1615 1616 static struct clk_branch disp_cc_mdss_mdp_ss_ip_clk = { 1617 .halt_reg = 0x8030, 1618 .halt_check = BRANCH_HALT_VOTED, 1619 .clkr = { 1620 .enable_reg = 0x8030, 1621 .enable_mask = BIT(0), 1622 .hw.init = &(const struct clk_init_data) { 1623 .name = "disp_cc_mdss_mdp_ss_ip_clk", 1624 .parent_hws = (const struct clk_hw*[]) { 1625 &disp_cc_mdss_mdp_clk_src.clkr.hw, 1626 }, 1627 .num_parents = 1, 1628 .flags = CLK_SET_RATE_PARENT, 1629 .ops = &clk_branch2_ops, 1630 }, 1631 }, 1632 }; 1633 1634 static struct clk_branch disp_cc_mdss_non_gdsc_ahb_clk = { 1635 .halt_reg = 0xc004, 1636 .halt_check = BRANCH_HALT_VOTED, 1637 .clkr = { 1638 .enable_reg = 0xc004, 1639 .enable_mask = BIT(0), 1640 .hw.init = &(const struct clk_init_data) { 1641 .name = "disp_cc_mdss_non_gdsc_ahb_clk", 1642 .parent_hws = (const struct clk_hw*[]) { 1643 &disp_cc_mdss_ahb_clk_src.clkr.hw, 1644 }, 1645 .num_parents = 1, 1646 .flags = CLK_SET_RATE_PARENT, 1647 .ops = &clk_branch2_ops, 1648 }, 1649 }, 1650 }; 1651 1652 static struct clk_branch disp_cc_mdss_pclk0_clk = { 1653 .halt_reg = 0x8004, 1654 .halt_check = BRANCH_HALT, 1655 .clkr = { 1656 .enable_reg = 0x8004, 1657 .enable_mask = BIT(0), 1658 .hw.init = &(const struct clk_init_data) { 1659 .name = "disp_cc_mdss_pclk0_clk", 1660 .parent_hws = (const struct clk_hw*[]) { 1661 &disp_cc_mdss_pclk0_clk_src.clkr.hw, 1662 }, 1663 .num_parents = 1, 1664 .flags = CLK_SET_RATE_PARENT, 1665 .ops = &clk_branch2_ops, 1666 }, 1667 }, 1668 }; 1669 1670 static struct clk_branch disp_cc_mdss_pclk1_clk = { 1671 .halt_reg = 0x8008, 1672 .halt_check = BRANCH_HALT, 1673 .clkr = { 1674 .enable_reg = 0x8008, 1675 .enable_mask = BIT(0), 1676 .hw.init = &(const struct clk_init_data) { 1677 .name = "disp_cc_mdss_pclk1_clk", 1678 .parent_hws = (const struct clk_hw*[]) { 1679 &disp_cc_mdss_pclk1_clk_src.clkr.hw, 1680 }, 1681 .num_parents = 1, 1682 .flags = CLK_SET_RATE_PARENT, 1683 .ops = &clk_branch2_ops, 1684 }, 1685 }, 1686 }; 1687 1688 static struct clk_branch disp_cc_mdss_pclk2_clk = { 1689 .halt_reg = 0x800c, 1690 .halt_check = BRANCH_HALT, 1691 .clkr = { 1692 .enable_reg = 0x800c, 1693 .enable_mask = BIT(0), 1694 .hw.init = &(const struct clk_init_data) { 1695 .name = "disp_cc_mdss_pclk2_clk", 1696 .parent_hws = (const struct clk_hw*[]) { 1697 &disp_cc_mdss_pclk2_clk_src.clkr.hw, 1698 }, 1699 .num_parents = 1, 1700 .flags = CLK_SET_RATE_PARENT, 1701 .ops = &clk_branch2_ops, 1702 }, 1703 }, 1704 }; 1705 1706 static struct clk_branch disp_cc_mdss_vsync1_clk = { 1707 .halt_reg = 0xa024, 1708 .halt_check = BRANCH_HALT, 1709 .clkr = { 1710 .enable_reg = 0xa024, 1711 .enable_mask = BIT(0), 1712 .hw.init = &(const struct clk_init_data) { 1713 .name = "disp_cc_mdss_vsync1_clk", 1714 .parent_hws = (const struct clk_hw*[]) { 1715 &disp_cc_mdss_vsync_clk_src.clkr.hw, 1716 }, 1717 .num_parents = 1, 1718 .flags = CLK_SET_RATE_PARENT, 1719 .ops = &clk_branch2_ops, 1720 }, 1721 }, 1722 }; 1723 1724 static struct clk_branch disp_cc_mdss_vsync_clk = { 1725 .halt_reg = 0x8040, 1726 .halt_check = BRANCH_HALT, 1727 .clkr = { 1728 .enable_reg = 0x8040, 1729 .enable_mask = BIT(0), 1730 .hw.init = &(const struct clk_init_data) { 1731 .name = "disp_cc_mdss_vsync_clk", 1732 .parent_hws = (const struct clk_hw*[]) { 1733 &disp_cc_mdss_vsync_clk_src.clkr.hw, 1734 }, 1735 .num_parents = 1, 1736 .flags = CLK_SET_RATE_PARENT, 1737 .ops = &clk_branch2_ops, 1738 }, 1739 }, 1740 }; 1741 1742 static struct clk_branch disp_cc_osc_clk = { 1743 .halt_reg = 0x80c8, 1744 .halt_check = BRANCH_HALT, 1745 .clkr = { 1746 .enable_reg = 0x80c8, 1747 .enable_mask = BIT(0), 1748 .hw.init = &(const struct clk_init_data) { 1749 .name = "disp_cc_osc_clk", 1750 .parent_hws = (const struct clk_hw*[]) { 1751 &disp_cc_osc_clk_src.clkr.hw, 1752 }, 1753 .num_parents = 1, 1754 .flags = CLK_SET_RATE_PARENT, 1755 .ops = &clk_branch2_ops, 1756 }, 1757 }, 1758 }; 1759 1760 static struct gdsc disp_cc_mdss_core_gdsc = { 1761 .gdscr = 0x9000, 1762 .en_rest_wait_val = 0x2, 1763 .en_few_wait_val = 0x2, 1764 .clk_dis_wait_val = 0xf, 1765 .pd = { 1766 .name = "disp_cc_mdss_core_gdsc", 1767 }, 1768 .pwrsts = PWRSTS_OFF_ON, 1769 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | HW_CTRL_TRIGGER, 1770 }; 1771 1772 static struct gdsc disp_cc_mdss_core_int2_gdsc = { 1773 .gdscr = 0xb000, 1774 .en_rest_wait_val = 0x2, 1775 .en_few_wait_val = 0x2, 1776 .clk_dis_wait_val = 0xf, 1777 .pd = { 1778 .name = "disp_cc_mdss_core_int2_gdsc", 1779 }, 1780 .pwrsts = PWRSTS_OFF_ON, 1781 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | HW_CTRL_TRIGGER, 1782 }; 1783 1784 static struct clk_regmap *disp_cc_kaanapali_clocks[] = { 1785 [DISP_CC_ESYNC0_CLK] = &disp_cc_esync0_clk.clkr, 1786 [DISP_CC_ESYNC0_CLK_SRC] = &disp_cc_esync0_clk_src.clkr, 1787 [DISP_CC_ESYNC1_CLK] = &disp_cc_esync1_clk.clkr, 1788 [DISP_CC_ESYNC1_CLK_SRC] = &disp_cc_esync1_clk_src.clkr, 1789 [DISP_CC_MDSS_ACCU_SHIFT_CLK] = &disp_cc_mdss_accu_shift_clk.clkr, 1790 [DISP_CC_MDSS_AHB1_CLK] = &disp_cc_mdss_ahb1_clk.clkr, 1791 [DISP_CC_MDSS_AHB_CLK] = &disp_cc_mdss_ahb_clk.clkr, 1792 [DISP_CC_MDSS_AHB_CLK_SRC] = &disp_cc_mdss_ahb_clk_src.clkr, 1793 [DISP_CC_MDSS_AHB_SWI_CLK] = &disp_cc_mdss_ahb_swi_clk.clkr, 1794 [DISP_CC_MDSS_AHB_SWI_DIV_CLK_SRC] = &disp_cc_mdss_ahb_swi_div_clk_src.clkr, 1795 [DISP_CC_MDSS_BYTE0_CLK] = &disp_cc_mdss_byte0_clk.clkr, 1796 [DISP_CC_MDSS_BYTE0_CLK_SRC] = &disp_cc_mdss_byte0_clk_src.clkr, 1797 [DISP_CC_MDSS_BYTE0_DIV_CLK_SRC] = &disp_cc_mdss_byte0_div_clk_src.clkr, 1798 [DISP_CC_MDSS_BYTE0_INTF_CLK] = &disp_cc_mdss_byte0_intf_clk.clkr, 1799 [DISP_CC_MDSS_BYTE1_CLK] = &disp_cc_mdss_byte1_clk.clkr, 1800 [DISP_CC_MDSS_BYTE1_CLK_SRC] = &disp_cc_mdss_byte1_clk_src.clkr, 1801 [DISP_CC_MDSS_BYTE1_DIV_CLK_SRC] = &disp_cc_mdss_byte1_div_clk_src.clkr, 1802 [DISP_CC_MDSS_BYTE1_INTF_CLK] = &disp_cc_mdss_byte1_intf_clk.clkr, 1803 [DISP_CC_MDSS_DPTX0_AUX_CLK] = &disp_cc_mdss_dptx0_aux_clk.clkr, 1804 [DISP_CC_MDSS_DPTX0_AUX_CLK_SRC] = &disp_cc_mdss_dptx0_aux_clk_src.clkr, 1805 [DISP_CC_MDSS_DPTX0_CRYPTO_CLK] = &disp_cc_mdss_dptx0_crypto_clk.clkr, 1806 [DISP_CC_MDSS_DPTX0_LINK_CLK] = &disp_cc_mdss_dptx0_link_clk.clkr, 1807 [DISP_CC_MDSS_DPTX0_LINK_CLK_SRC] = &disp_cc_mdss_dptx0_link_clk_src.clkr, 1808 [DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dptx0_link_div_clk_src.clkr, 1809 [DISP_CC_MDSS_DPTX0_LINK_INTF_CLK] = &disp_cc_mdss_dptx0_link_intf_clk.clkr, 1810 [DISP_CC_MDSS_DPTX0_PIXEL0_CLK] = &disp_cc_mdss_dptx0_pixel0_clk.clkr, 1811 [DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC] = &disp_cc_mdss_dptx0_pixel0_clk_src.clkr, 1812 [DISP_CC_MDSS_DPTX0_PIXEL1_CLK] = &disp_cc_mdss_dptx0_pixel1_clk.clkr, 1813 [DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC] = &disp_cc_mdss_dptx0_pixel1_clk_src.clkr, 1814 [DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK] = 1815 &disp_cc_mdss_dptx0_usb_router_link_intf_clk.clkr, 1816 [DISP_CC_MDSS_DPTX1_AUX_CLK] = &disp_cc_mdss_dptx1_aux_clk.clkr, 1817 [DISP_CC_MDSS_DPTX1_AUX_CLK_SRC] = &disp_cc_mdss_dptx1_aux_clk_src.clkr, 1818 [DISP_CC_MDSS_DPTX1_CRYPTO_CLK] = &disp_cc_mdss_dptx1_crypto_clk.clkr, 1819 [DISP_CC_MDSS_DPTX1_LINK_CLK] = &disp_cc_mdss_dptx1_link_clk.clkr, 1820 [DISP_CC_MDSS_DPTX1_LINK_CLK_SRC] = &disp_cc_mdss_dptx1_link_clk_src.clkr, 1821 [DISP_CC_MDSS_DPTX1_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dptx1_link_div_clk_src.clkr, 1822 [DISP_CC_MDSS_DPTX1_LINK_INTF_CLK] = &disp_cc_mdss_dptx1_link_intf_clk.clkr, 1823 [DISP_CC_MDSS_DPTX1_PIXEL0_CLK] = &disp_cc_mdss_dptx1_pixel0_clk.clkr, 1824 [DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC] = &disp_cc_mdss_dptx1_pixel0_clk_src.clkr, 1825 [DISP_CC_MDSS_DPTX1_PIXEL1_CLK] = &disp_cc_mdss_dptx1_pixel1_clk.clkr, 1826 [DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC] = &disp_cc_mdss_dptx1_pixel1_clk_src.clkr, 1827 [DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INTF_CLK] = 1828 &disp_cc_mdss_dptx1_usb_router_link_intf_clk.clkr, 1829 [DISP_CC_MDSS_DPTX2_AUX_CLK] = &disp_cc_mdss_dptx2_aux_clk.clkr, 1830 [DISP_CC_MDSS_DPTX2_AUX_CLK_SRC] = &disp_cc_mdss_dptx2_aux_clk_src.clkr, 1831 [DISP_CC_MDSS_DPTX2_CRYPTO_CLK] = &disp_cc_mdss_dptx2_crypto_clk.clkr, 1832 [DISP_CC_MDSS_DPTX2_LINK_CLK] = &disp_cc_mdss_dptx2_link_clk.clkr, 1833 [DISP_CC_MDSS_DPTX2_LINK_CLK_SRC] = &disp_cc_mdss_dptx2_link_clk_src.clkr, 1834 [DISP_CC_MDSS_DPTX2_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dptx2_link_div_clk_src.clkr, 1835 [DISP_CC_MDSS_DPTX2_LINK_INTF_CLK] = &disp_cc_mdss_dptx2_link_intf_clk.clkr, 1836 [DISP_CC_MDSS_DPTX2_PIXEL0_CLK] = &disp_cc_mdss_dptx2_pixel0_clk.clkr, 1837 [DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC] = &disp_cc_mdss_dptx2_pixel0_clk_src.clkr, 1838 [DISP_CC_MDSS_DPTX2_PIXEL1_CLK] = &disp_cc_mdss_dptx2_pixel1_clk.clkr, 1839 [DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC] = &disp_cc_mdss_dptx2_pixel1_clk_src.clkr, 1840 [DISP_CC_MDSS_DPTX3_AUX_CLK] = &disp_cc_mdss_dptx3_aux_clk.clkr, 1841 [DISP_CC_MDSS_DPTX3_AUX_CLK_SRC] = &disp_cc_mdss_dptx3_aux_clk_src.clkr, 1842 [DISP_CC_MDSS_DPTX3_CRYPTO_CLK] = &disp_cc_mdss_dptx3_crypto_clk.clkr, 1843 [DISP_CC_MDSS_DPTX3_LINK_CLK] = &disp_cc_mdss_dptx3_link_clk.clkr, 1844 [DISP_CC_MDSS_DPTX3_LINK_CLK_SRC] = &disp_cc_mdss_dptx3_link_clk_src.clkr, 1845 [DISP_CC_MDSS_DPTX3_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dptx3_link_div_clk_src.clkr, 1846 [DISP_CC_MDSS_DPTX3_LINK_INTF_CLK] = &disp_cc_mdss_dptx3_link_intf_clk.clkr, 1847 [DISP_CC_MDSS_DPTX3_PIXEL0_CLK] = &disp_cc_mdss_dptx3_pixel0_clk.clkr, 1848 [DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC] = &disp_cc_mdss_dptx3_pixel0_clk_src.clkr, 1849 [DISP_CC_MDSS_ESC0_CLK] = &disp_cc_mdss_esc0_clk.clkr, 1850 [DISP_CC_MDSS_ESC0_CLK_SRC] = &disp_cc_mdss_esc0_clk_src.clkr, 1851 [DISP_CC_MDSS_ESC1_CLK] = &disp_cc_mdss_esc1_clk.clkr, 1852 [DISP_CC_MDSS_ESC1_CLK_SRC] = &disp_cc_mdss_esc1_clk_src.clkr, 1853 [DISP_CC_MDSS_MDP1_CLK] = &disp_cc_mdss_mdp1_clk.clkr, 1854 [DISP_CC_MDSS_MDP_CLK] = &disp_cc_mdss_mdp_clk.clkr, 1855 [DISP_CC_MDSS_MDP_CLK_SRC] = &disp_cc_mdss_mdp_clk_src.clkr, 1856 [DISP_CC_MDSS_MDP_LUT1_CLK] = &disp_cc_mdss_mdp_lut1_clk.clkr, 1857 [DISP_CC_MDSS_MDP_LUT_CLK] = &disp_cc_mdss_mdp_lut_clk.clkr, 1858 [DISP_CC_MDSS_MDP_SS_IP_CLK] = &disp_cc_mdss_mdp_ss_ip_clk.clkr, 1859 [DISP_CC_MDSS_NON_GDSC_AHB_CLK] = &disp_cc_mdss_non_gdsc_ahb_clk.clkr, 1860 [DISP_CC_MDSS_PCLK0_CLK] = &disp_cc_mdss_pclk0_clk.clkr, 1861 [DISP_CC_MDSS_PCLK0_CLK_SRC] = &disp_cc_mdss_pclk0_clk_src.clkr, 1862 [DISP_CC_MDSS_PCLK1_CLK] = &disp_cc_mdss_pclk1_clk.clkr, 1863 [DISP_CC_MDSS_PCLK1_CLK_SRC] = &disp_cc_mdss_pclk1_clk_src.clkr, 1864 [DISP_CC_MDSS_PCLK2_CLK] = &disp_cc_mdss_pclk2_clk.clkr, 1865 [DISP_CC_MDSS_PCLK2_CLK_SRC] = &disp_cc_mdss_pclk2_clk_src.clkr, 1866 [DISP_CC_MDSS_VSYNC1_CLK] = &disp_cc_mdss_vsync1_clk.clkr, 1867 [DISP_CC_MDSS_VSYNC_CLK] = &disp_cc_mdss_vsync_clk.clkr, 1868 [DISP_CC_MDSS_VSYNC_CLK_SRC] = &disp_cc_mdss_vsync_clk_src.clkr, 1869 [DISP_CC_OSC_CLK] = &disp_cc_osc_clk.clkr, 1870 [DISP_CC_OSC_CLK_SRC] = &disp_cc_osc_clk_src.clkr, 1871 [DISP_CC_PLL0] = &disp_cc_pll0.clkr, 1872 [DISP_CC_PLL1] = &disp_cc_pll1.clkr, 1873 [DISP_CC_PLL2] = &disp_cc_pll2.clkr, 1874 }; 1875 1876 static struct gdsc *disp_cc_kaanapali_gdscs[] = { 1877 [DISP_CC_MDSS_CORE_GDSC] = &disp_cc_mdss_core_gdsc, 1878 [DISP_CC_MDSS_CORE_INT2_GDSC] = &disp_cc_mdss_core_int2_gdsc, 1879 }; 1880 1881 static const struct qcom_reset_map disp_cc_kaanapali_resets[] = { 1882 [DISP_CC_MDSS_CORE_BCR] = { 0x8000 }, 1883 [DISP_CC_MDSS_CORE_INT2_BCR] = { 0xa000 }, 1884 [DISP_CC_MDSS_RSCC_BCR] = { 0xc000 }, 1885 }; 1886 1887 static struct clk_alpha_pll *disp_cc_kaanapali_plls[] = { 1888 &disp_cc_pll0, 1889 &disp_cc_pll1, 1890 &disp_cc_pll2, 1891 }; 1892 1893 static u32 disp_cc_kaanapali_critical_cbcrs[] = { 1894 0xe064, /* DISP_CC_SLEEP_CLK */ 1895 0xe05c, /* DISP_CC_XO_CLK */ 1896 0xc00c, /* DISP_CC_MDSS_RSCC_AHB_CLK */ 1897 0xc008, /* DISP_CC_MDSS_RSCC_VSYNC_CLK */ 1898 }; 1899 1900 static const struct regmap_config disp_cc_kaanapali_regmap_config = { 1901 .reg_bits = 32, 1902 .reg_stride = 4, 1903 .val_bits = 32, 1904 .max_register = 0x12094, 1905 .fast_io = true, 1906 }; 1907 1908 static void clk_kaanapali_regs_configure(struct device *dev, struct regmap *regmap) 1909 { 1910 /* Enable clock gating for MDP clocks */ 1911 regmap_update_bits(regmap, DISP_CC_MISC_CMD, BIT(4), BIT(4)); 1912 } 1913 1914 static struct qcom_cc_driver_data disp_cc_kaanapali_driver_data = { 1915 .alpha_plls = disp_cc_kaanapali_plls, 1916 .num_alpha_plls = ARRAY_SIZE(disp_cc_kaanapali_plls), 1917 .clk_cbcrs = disp_cc_kaanapali_critical_cbcrs, 1918 .num_clk_cbcrs = ARRAY_SIZE(disp_cc_kaanapali_critical_cbcrs), 1919 .clk_regs_configure = clk_kaanapali_regs_configure, 1920 }; 1921 1922 static const struct qcom_cc_desc disp_cc_kaanapali_desc = { 1923 .config = &disp_cc_kaanapali_regmap_config, 1924 .clks = disp_cc_kaanapali_clocks, 1925 .num_clks = ARRAY_SIZE(disp_cc_kaanapali_clocks), 1926 .resets = disp_cc_kaanapali_resets, 1927 .num_resets = ARRAY_SIZE(disp_cc_kaanapali_resets), 1928 .gdscs = disp_cc_kaanapali_gdscs, 1929 .num_gdscs = ARRAY_SIZE(disp_cc_kaanapali_gdscs), 1930 .use_rpm = true, 1931 .driver_data = &disp_cc_kaanapali_driver_data, 1932 }; 1933 1934 static const struct of_device_id disp_cc_kaanapali_match_table[] = { 1935 { .compatible = "qcom,kaanapali-dispcc" }, 1936 { } 1937 }; 1938 MODULE_DEVICE_TABLE(of, disp_cc_kaanapali_match_table); 1939 1940 static int disp_cc_kaanapali_probe(struct platform_device *pdev) 1941 { 1942 return qcom_cc_probe(pdev, &disp_cc_kaanapali_desc); 1943 } 1944 1945 static struct platform_driver disp_cc_kaanapali_driver = { 1946 .probe = disp_cc_kaanapali_probe, 1947 .driver = { 1948 .name = "dispcc-kaanapali", 1949 .of_match_table = disp_cc_kaanapali_match_table, 1950 }, 1951 }; 1952 1953 module_platform_driver(disp_cc_kaanapali_driver); 1954 1955 MODULE_DESCRIPTION("QTI DISPCC Kaanapali Driver"); 1956 MODULE_LICENSE("GPL"); 1957