1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2021, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2023-2024, Linaro Ltd. 5 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 6 */ 7 8 #include <linux/clk-provider.h> 9 #include <linux/kernel.h> 10 #include <linux/mod_devicetable.h> 11 #include <linux/module.h> 12 #include <linux/platform_device.h> 13 #include <linux/regmap.h> 14 15 #include <dt-bindings/clock/qcom,eliza-dispcc.h> 16 17 #include "common.h" 18 #include "clk-alpha-pll.h" 19 #include "clk-branch.h" 20 #include "clk-pll.h" 21 #include "clk-rcg.h" 22 #include "clk-regmap.h" 23 #include "clk-regmap-divider.h" 24 #include "clk-regmap-mux.h" 25 #include "gdsc.h" 26 #include "reset.h" 27 28 /* Need to match the order of clocks in DT binding */ 29 enum { 30 DT_BI_TCXO, 31 DT_BI_TCXO_AO, 32 DT_AHB_CLK, 33 DT_SLEEP_CLK, 34 35 DT_DSI0_PHY_PLL_OUT_BYTECLK, 36 DT_DSI0_PHY_PLL_OUT_DSICLK, 37 DT_DSI1_PHY_PLL_OUT_BYTECLK, 38 DT_DSI1_PHY_PLL_OUT_DSICLK, 39 40 DT_DP0_PHY_PLL_LINK_CLK, 41 DT_DP0_PHY_PLL_VCO_DIV_CLK, 42 DT_DP1_PHY_PLL_LINK_CLK, 43 DT_DP1_PHY_PLL_VCO_DIV_CLK, 44 DT_DP2_PHY_PLL_LINK_CLK, 45 DT_DP2_PHY_PLL_VCO_DIV_CLK, 46 DT_DP3_PHY_PLL_LINK_CLK, 47 DT_DP3_PHY_PLL_VCO_DIV_CLK, 48 DT_HDMI_PHY_PLL_CLK, 49 }; 50 51 #define DISP_CC_MISC_CMD 0xF000 52 53 enum { 54 P_BI_TCXO, 55 P_DISP_CC_PLL0_OUT_MAIN, 56 P_DISP_CC_PLL1_OUT_EVEN, 57 P_DISP_CC_PLL1_OUT_MAIN, 58 P_DISP_CC_PLL2_OUT_MAIN, 59 P_DP0_PHY_PLL_LINK_CLK, 60 P_DP0_PHY_PLL_VCO_DIV_CLK, 61 P_DP1_PHY_PLL_LINK_CLK, 62 P_DP1_PHY_PLL_VCO_DIV_CLK, 63 P_DP2_PHY_PLL_LINK_CLK, 64 P_DP2_PHY_PLL_VCO_DIV_CLK, 65 P_DP3_PHY_PLL_LINK_CLK, 66 P_DP3_PHY_PLL_VCO_DIV_CLK, 67 P_DSI0_PHY_PLL_OUT_BYTECLK, 68 P_DSI0_PHY_PLL_OUT_DSICLK, 69 P_DSI1_PHY_PLL_OUT_BYTECLK, 70 P_DSI1_PHY_PLL_OUT_DSICLK, 71 P_HDMI_PHY_PLL_CLK, 72 P_SLEEP_CLK, 73 }; 74 75 static const struct pll_vco lucid_ole_vco[] = { 76 { 249600000, 2300000000, 0 }, 77 }; 78 79 static const struct pll_vco pongo_ole_vco[] = { 80 { 38400000, 38400000, 0 }, 81 }; 82 83 static struct alpha_pll_config disp_cc_pll0_config = { 84 .l = 0xd, 85 .cal_l = 0x44, 86 .alpha = 0x6492, 87 .config_ctl_val = 0x20485699, 88 .config_ctl_hi_val = 0x00182261, 89 .config_ctl_hi1_val = 0x82aa299c, 90 .test_ctl_val = 0x00000000, 91 .test_ctl_hi_val = 0x00000003, 92 .test_ctl_hi1_val = 0x00009000, 93 .test_ctl_hi2_val = 0x00000034, 94 .user_ctl_val = 0x00000000, 95 .user_ctl_hi_val = 0x00000005, 96 }; 97 98 static struct clk_alpha_pll disp_cc_pll0 = { 99 .offset = 0x0, 100 .config = &disp_cc_pll0_config, 101 .vco_table = lucid_ole_vco, 102 .num_vco = ARRAY_SIZE(lucid_ole_vco), 103 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 104 .clkr = { 105 .hw.init = &(const struct clk_init_data) { 106 .name = "disp_cc_pll0", 107 .parent_data = &(const struct clk_parent_data) { 108 .index = DT_BI_TCXO, 109 }, 110 .num_parents = 1, 111 .ops = &clk_alpha_pll_lucid_evo_ops, 112 }, 113 }, 114 }; 115 116 static struct alpha_pll_config disp_cc_pll1_config = { 117 .l = 0x1f, 118 .cal_l = 0x44, 119 .alpha = 0x4000, 120 .config_ctl_val = 0x20485699, 121 .config_ctl_hi_val = 0x00182261, 122 .config_ctl_hi1_val = 0x82aa299c, 123 .test_ctl_val = 0x00000000, 124 .test_ctl_hi_val = 0x00000003, 125 .test_ctl_hi1_val = 0x00009000, 126 .test_ctl_hi2_val = 0x00000034, 127 .user_ctl_val = 0x00000000, 128 .user_ctl_hi_val = 0x00000005, 129 }; 130 131 static struct clk_alpha_pll disp_cc_pll1 = { 132 .offset = 0x1000, 133 .config = &disp_cc_pll1_config, 134 .vco_table = lucid_ole_vco, 135 .num_vco = ARRAY_SIZE(lucid_ole_vco), 136 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 137 .clkr = { 138 .hw.init = &(const struct clk_init_data) { 139 .name = "disp_cc_pll1", 140 .parent_data = &(const struct clk_parent_data) { 141 .index = DT_BI_TCXO, 142 }, 143 .num_parents = 1, 144 .ops = &clk_alpha_pll_lucid_evo_ops, 145 }, 146 }, 147 }; 148 149 static const struct alpha_pll_config disp_cc_pll2_config = { 150 .l = 0x493, 151 .cal_l = 0x493, 152 .alpha = 0x0, 153 .config_ctl_val = 0x60000f6a, 154 .config_ctl_hi_val = 0x0001c808, 155 .config_ctl_hi1_val = 0x00000000, 156 .config_ctl_hi2_val = 0x04008174, 157 .test_ctl_val = 0x00000000, 158 .test_ctl_hi_val = 0x0080c496, 159 .test_ctl_hi1_val = 0x40100180, 160 .test_ctl_hi2_val = 0x441001bc, 161 .test_ctl_hi3_val = 0x000003d8, 162 .user_ctl_val = 0x00000000, 163 .user_ctl_hi_val = 0x00e50302, 164 }; 165 166 static struct clk_alpha_pll disp_cc_pll2 = { 167 .offset = 0x2000, 168 .config = &disp_cc_pll2_config, 169 .vco_table = pongo_ole_vco, 170 .num_vco = ARRAY_SIZE(pongo_ole_vco), 171 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_PONGO_ELU], 172 .clkr = { 173 .hw.init = &(const struct clk_init_data) { 174 .name = "disp_cc_pll2", 175 .parent_data = &(const struct clk_parent_data) { 176 .index = DT_SLEEP_CLK, 177 }, 178 .num_parents = 1, 179 .ops = &clk_alpha_pll_pongo_elu_ops, 180 }, 181 }, 182 }; 183 184 static const struct parent_map disp_cc_parent_map_0[] = { 185 { P_BI_TCXO, 0 }, 186 }; 187 188 static const struct clk_parent_data disp_cc_parent_data_0[] = { 189 { .index = DT_BI_TCXO }, 190 }; 191 192 static const struct clk_parent_data disp_cc_parent_data_0_ao[] = { 193 { .index = DT_BI_TCXO_AO }, 194 }; 195 196 static const struct parent_map disp_cc_parent_map_1[] = { 197 { P_BI_TCXO, 0 }, 198 { P_DSI0_PHY_PLL_OUT_DSICLK, 1 }, 199 { P_DSI0_PHY_PLL_OUT_BYTECLK, 2 }, 200 { P_DSI1_PHY_PLL_OUT_DSICLK, 3 }, 201 { P_DSI1_PHY_PLL_OUT_BYTECLK, 4 }, 202 }; 203 204 static const struct clk_parent_data disp_cc_parent_data_1[] = { 205 { .index = DT_BI_TCXO }, 206 { .index = DT_DSI0_PHY_PLL_OUT_DSICLK }, 207 { .index = DT_DSI0_PHY_PLL_OUT_BYTECLK }, 208 { .index = DT_DSI1_PHY_PLL_OUT_DSICLK }, 209 { .index = DT_DSI1_PHY_PLL_OUT_BYTECLK }, 210 }; 211 212 static const struct parent_map disp_cc_parent_map_2[] = { 213 { P_BI_TCXO, 0 }, 214 { P_DP3_PHY_PLL_VCO_DIV_CLK, 3 }, 215 { P_DP1_PHY_PLL_VCO_DIV_CLK, 4 }, 216 { P_DP2_PHY_PLL_VCO_DIV_CLK, 6 }, 217 }; 218 219 static const struct clk_parent_data disp_cc_parent_data_2[] = { 220 { .index = DT_BI_TCXO }, 221 { .index = DT_DP3_PHY_PLL_VCO_DIV_CLK }, 222 { .index = DT_DP1_PHY_PLL_VCO_DIV_CLK }, 223 { .index = DT_DP2_PHY_PLL_VCO_DIV_CLK }, 224 }; 225 226 static const struct parent_map disp_cc_parent_map_3[] = { 227 { P_BI_TCXO, 0 }, 228 { P_DP1_PHY_PLL_LINK_CLK, 2 }, 229 { P_DP2_PHY_PLL_LINK_CLK, 3 }, 230 { P_DP3_PHY_PLL_LINK_CLK, 4 }, 231 }; 232 233 static const struct clk_parent_data disp_cc_parent_data_3[] = { 234 { .index = DT_BI_TCXO }, 235 { .index = DT_DP1_PHY_PLL_LINK_CLK }, 236 { .index = DT_DP2_PHY_PLL_LINK_CLK }, 237 { .index = DT_DP3_PHY_PLL_LINK_CLK }, 238 }; 239 240 static const struct parent_map disp_cc_parent_map_4[] = { 241 { P_BI_TCXO, 0 }, 242 { P_DSI0_PHY_PLL_OUT_DSICLK, 1 }, 243 { P_DISP_CC_PLL2_OUT_MAIN, 2 }, 244 { P_DSI1_PHY_PLL_OUT_DSICLK, 3 }, 245 }; 246 247 static const struct clk_parent_data disp_cc_parent_data_4[] = { 248 { .index = DT_BI_TCXO }, 249 { .index = DT_DSI0_PHY_PLL_OUT_DSICLK }, 250 { .hw = &disp_cc_pll2.clkr.hw }, 251 { .index = DT_DSI1_PHY_PLL_OUT_DSICLK }, 252 }; 253 254 static const struct parent_map disp_cc_parent_map_5[] = { 255 { P_BI_TCXO, 0 }, 256 { P_DP0_PHY_PLL_LINK_CLK, 1 }, 257 { P_DP0_PHY_PLL_VCO_DIV_CLK, 2 }, 258 { P_DP3_PHY_PLL_VCO_DIV_CLK, 3 }, 259 { P_DP1_PHY_PLL_VCO_DIV_CLK, 4 }, 260 { P_DP2_PHY_PLL_VCO_DIV_CLK, 6 }, 261 }; 262 263 static const struct clk_parent_data disp_cc_parent_data_5[] = { 264 { .index = DT_BI_TCXO }, 265 { .index = DT_DP0_PHY_PLL_LINK_CLK }, 266 { .index = DT_DP0_PHY_PLL_VCO_DIV_CLK }, 267 { .index = DT_DP3_PHY_PLL_VCO_DIV_CLK }, 268 { .index = DT_DP1_PHY_PLL_VCO_DIV_CLK }, 269 { .index = DT_DP2_PHY_PLL_VCO_DIV_CLK }, 270 }; 271 272 static const struct parent_map disp_cc_parent_map_6[] = { 273 { P_BI_TCXO, 0 }, 274 { P_DSI0_PHY_PLL_OUT_BYTECLK, 2 }, 275 { P_DSI1_PHY_PLL_OUT_BYTECLK, 4 }, 276 }; 277 278 static const struct clk_parent_data disp_cc_parent_data_6[] = { 279 { .index = DT_BI_TCXO }, 280 { .index = DT_DSI0_PHY_PLL_OUT_BYTECLK }, 281 { .index = DT_DSI1_PHY_PLL_OUT_BYTECLK }, 282 }; 283 284 static const struct parent_map disp_cc_parent_map_7[] = { 285 { P_BI_TCXO, 0 }, 286 { P_DISP_CC_PLL1_OUT_MAIN, 4 }, 287 { P_DISP_CC_PLL1_OUT_EVEN, 6 }, 288 }; 289 290 static const struct clk_parent_data disp_cc_parent_data_7[] = { 291 { .index = DT_BI_TCXO }, 292 { .hw = &disp_cc_pll1.clkr.hw }, 293 { .hw = &disp_cc_pll1.clkr.hw }, 294 }; 295 296 static const struct parent_map disp_cc_parent_map_8[] = { 297 { P_BI_TCXO, 0 }, 298 { P_DP0_PHY_PLL_LINK_CLK, 1 }, 299 { P_DP1_PHY_PLL_LINK_CLK, 2 }, 300 { P_DP2_PHY_PLL_LINK_CLK, 3 }, 301 { P_DP3_PHY_PLL_LINK_CLK, 4 }, 302 }; 303 304 static const struct clk_parent_data disp_cc_parent_data_8[] = { 305 { .index = DT_BI_TCXO }, 306 { .index = DT_DP0_PHY_PLL_LINK_CLK }, 307 { .index = DT_DP1_PHY_PLL_LINK_CLK }, 308 { .index = DT_DP2_PHY_PLL_LINK_CLK }, 309 { .index = DT_DP3_PHY_PLL_LINK_CLK }, 310 }; 311 312 static const struct parent_map disp_cc_parent_map_9[] = { 313 { P_BI_TCXO, 0 }, 314 { P_DISP_CC_PLL0_OUT_MAIN, 1 }, 315 }; 316 317 static const struct clk_parent_data disp_cc_parent_data_9[] = { 318 { .index = DT_BI_TCXO }, 319 { .hw = &disp_cc_pll0.clkr.hw }, 320 }; 321 322 static const struct parent_map disp_cc_parent_map_10[] = { 323 { P_BI_TCXO, 0 }, 324 { P_HDMI_PHY_PLL_CLK, 1 }, 325 }; 326 327 static const struct clk_parent_data disp_cc_parent_data_10[] = { 328 { .index = DT_BI_TCXO }, 329 { .index = DT_HDMI_PHY_PLL_CLK }, 330 }; 331 332 static const struct parent_map disp_cc_parent_map_11[] = { 333 { P_BI_TCXO, 0 }, 334 { P_DISP_CC_PLL0_OUT_MAIN, 1 }, 335 { P_DISP_CC_PLL1_OUT_MAIN, 4 }, 336 { P_DISP_CC_PLL1_OUT_EVEN, 6 }, 337 }; 338 339 static const struct clk_parent_data disp_cc_parent_data_11[] = { 340 { .index = DT_BI_TCXO }, 341 { .hw = &disp_cc_pll0.clkr.hw }, 342 { .hw = &disp_cc_pll1.clkr.hw }, 343 { .hw = &disp_cc_pll1.clkr.hw }, 344 }; 345 346 static const struct parent_map disp_cc_parent_map_12[] = { 347 { P_BI_TCXO, 0 }, 348 { P_DISP_CC_PLL2_OUT_MAIN, 2 }, 349 }; 350 351 static const struct clk_parent_data disp_cc_parent_data_12[] = { 352 { .index = DT_BI_TCXO }, 353 { .hw = &disp_cc_pll2.clkr.hw }, 354 }; 355 356 static const struct parent_map disp_cc_parent_map_13[] = { 357 { P_SLEEP_CLK, 0 }, 358 }; 359 360 static const struct clk_parent_data disp_cc_parent_data_13_ao[] = { 361 { .index = DT_SLEEP_CLK }, 362 }; 363 364 static const struct freq_tbl ftbl_disp_cc_esync0_clk_src[] = { 365 F(19200000, P_BI_TCXO, 1, 0, 0), 366 { } 367 }; 368 369 static struct clk_rcg2 disp_cc_esync0_clk_src = { 370 .cmd_rcgr = 0x80c0, 371 .mnd_width = 16, 372 .hid_width = 5, 373 .parent_map = disp_cc_parent_map_4, 374 .freq_tbl = ftbl_disp_cc_esync0_clk_src, 375 .clkr.hw.init = &(const struct clk_init_data) { 376 .name = "disp_cc_esync0_clk_src", 377 .parent_data = disp_cc_parent_data_4, 378 .num_parents = ARRAY_SIZE(disp_cc_parent_data_4), 379 .flags = CLK_SET_RATE_PARENT, 380 .ops = &clk_byte2_ops, 381 }, 382 }; 383 384 static struct clk_rcg2 disp_cc_esync1_clk_src = { 385 .cmd_rcgr = 0x80d8, 386 .mnd_width = 16, 387 .hid_width = 5, 388 .parent_map = disp_cc_parent_map_4, 389 .freq_tbl = ftbl_disp_cc_esync0_clk_src, 390 .clkr.hw.init = &(const struct clk_init_data) { 391 .name = "disp_cc_esync1_clk_src", 392 .parent_data = disp_cc_parent_data_4, 393 .num_parents = ARRAY_SIZE(disp_cc_parent_data_4), 394 .flags = CLK_SET_RATE_PARENT, 395 .ops = &clk_byte2_ops, 396 }, 397 }; 398 399 static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = { 400 F(19200000, P_BI_TCXO, 1, 0, 0), 401 F(37500000, P_DISP_CC_PLL1_OUT_MAIN, 16, 0, 0), 402 F(75000000, P_DISP_CC_PLL1_OUT_MAIN, 8, 0, 0), 403 { } 404 }; 405 406 static struct clk_rcg2 disp_cc_mdss_ahb_clk_src = { 407 .cmd_rcgr = 0x8360, 408 .mnd_width = 0, 409 .hid_width = 5, 410 .parent_map = disp_cc_parent_map_7, 411 .freq_tbl = ftbl_disp_cc_mdss_ahb_clk_src, 412 .clkr.hw.init = &(const struct clk_init_data) { 413 .name = "disp_cc_mdss_ahb_clk_src", 414 .parent_data = disp_cc_parent_data_7, 415 .num_parents = ARRAY_SIZE(disp_cc_parent_data_7), 416 .flags = CLK_SET_RATE_PARENT, 417 .ops = &clk_rcg2_shared_ops, 418 }, 419 }; 420 421 static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = { 422 .cmd_rcgr = 0x8180, 423 .mnd_width = 0, 424 .hid_width = 5, 425 .parent_map = disp_cc_parent_map_1, 426 .freq_tbl = ftbl_disp_cc_esync0_clk_src, 427 .clkr.hw.init = &(const struct clk_init_data) { 428 .name = "disp_cc_mdss_byte0_clk_src", 429 .parent_data = disp_cc_parent_data_1, 430 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), 431 .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, 432 .ops = &clk_byte2_ops, 433 }, 434 }; 435 436 static struct clk_rcg2 disp_cc_mdss_byte1_clk_src = { 437 .cmd_rcgr = 0x819c, 438 .mnd_width = 0, 439 .hid_width = 5, 440 .parent_map = disp_cc_parent_map_1, 441 .freq_tbl = ftbl_disp_cc_esync0_clk_src, 442 .clkr.hw.init = &(const struct clk_init_data) { 443 .name = "disp_cc_mdss_byte1_clk_src", 444 .parent_data = disp_cc_parent_data_1, 445 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), 446 .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, 447 .ops = &clk_byte2_ops, 448 }, 449 }; 450 451 static struct clk_rcg2 disp_cc_mdss_dptx0_aux_clk_src = { 452 .cmd_rcgr = 0x8234, 453 .mnd_width = 0, 454 .hid_width = 5, 455 .parent_map = disp_cc_parent_map_0, 456 .freq_tbl = ftbl_disp_cc_esync0_clk_src, 457 .clkr.hw.init = &(const struct clk_init_data) { 458 .name = "disp_cc_mdss_dptx0_aux_clk_src", 459 .parent_data = disp_cc_parent_data_0, 460 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), 461 .flags = CLK_SET_RATE_PARENT, 462 .ops = &clk_rcg2_ops, 463 }, 464 }; 465 466 static struct clk_rcg2 disp_cc_mdss_dptx0_link_clk_src = { 467 .cmd_rcgr = 0x81e8, 468 .mnd_width = 0, 469 .hid_width = 5, 470 .parent_map = disp_cc_parent_map_8, 471 .freq_tbl = ftbl_disp_cc_esync0_clk_src, 472 .clkr.hw.init = &(const struct clk_init_data) { 473 .name = "disp_cc_mdss_dptx0_link_clk_src", 474 .parent_data = disp_cc_parent_data_8, 475 .num_parents = ARRAY_SIZE(disp_cc_parent_data_8), 476 .flags = CLK_SET_RATE_PARENT, 477 .ops = &clk_byte2_ops, 478 }, 479 }; 480 481 static struct clk_rcg2 disp_cc_mdss_dptx0_pixel0_clk_src = { 482 .cmd_rcgr = 0x8204, 483 .mnd_width = 16, 484 .hid_width = 5, 485 .parent_map = disp_cc_parent_map_5, 486 .freq_tbl = ftbl_disp_cc_esync0_clk_src, 487 .clkr.hw.init = &(const struct clk_init_data) { 488 .name = "disp_cc_mdss_dptx0_pixel0_clk_src", 489 .parent_data = disp_cc_parent_data_5, 490 .num_parents = ARRAY_SIZE(disp_cc_parent_data_5), 491 .flags = CLK_SET_RATE_PARENT, 492 .ops = &clk_dp_ops, 493 }, 494 }; 495 496 static struct clk_rcg2 disp_cc_mdss_dptx0_pixel1_clk_src = { 497 .cmd_rcgr = 0x821c, 498 .mnd_width = 16, 499 .hid_width = 5, 500 .parent_map = disp_cc_parent_map_5, 501 .freq_tbl = ftbl_disp_cc_esync0_clk_src, 502 .clkr.hw.init = &(const struct clk_init_data) { 503 .name = "disp_cc_mdss_dptx0_pixel1_clk_src", 504 .parent_data = disp_cc_parent_data_5, 505 .num_parents = ARRAY_SIZE(disp_cc_parent_data_5), 506 .flags = CLK_SET_RATE_PARENT, 507 .ops = &clk_dp_ops, 508 }, 509 }; 510 511 static struct clk_rcg2 disp_cc_mdss_dptx1_aux_clk_src = { 512 .cmd_rcgr = 0x8298, 513 .mnd_width = 0, 514 .hid_width = 5, 515 .parent_map = disp_cc_parent_map_0, 516 .freq_tbl = ftbl_disp_cc_esync0_clk_src, 517 .clkr.hw.init = &(const struct clk_init_data) { 518 .name = "disp_cc_mdss_dptx1_aux_clk_src", 519 .parent_data = disp_cc_parent_data_0, 520 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), 521 .flags = CLK_SET_RATE_PARENT, 522 .ops = &clk_rcg2_ops, 523 }, 524 }; 525 526 static struct clk_rcg2 disp_cc_mdss_dptx1_link_clk_src = { 527 .cmd_rcgr = 0x827c, 528 .mnd_width = 0, 529 .hid_width = 5, 530 .parent_map = disp_cc_parent_map_3, 531 .freq_tbl = ftbl_disp_cc_esync0_clk_src, 532 .clkr.hw.init = &(const struct clk_init_data) { 533 .name = "disp_cc_mdss_dptx1_link_clk_src", 534 .parent_data = disp_cc_parent_data_3, 535 .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), 536 .flags = CLK_SET_RATE_PARENT, 537 .ops = &clk_byte2_ops, 538 }, 539 }; 540 541 static struct clk_rcg2 disp_cc_mdss_dptx1_pixel0_clk_src = { 542 .cmd_rcgr = 0x824c, 543 .mnd_width = 16, 544 .hid_width = 5, 545 .parent_map = disp_cc_parent_map_2, 546 .freq_tbl = ftbl_disp_cc_esync0_clk_src, 547 .clkr.hw.init = &(const struct clk_init_data) { 548 .name = "disp_cc_mdss_dptx1_pixel0_clk_src", 549 .parent_data = disp_cc_parent_data_2, 550 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), 551 .flags = CLK_SET_RATE_PARENT, 552 .ops = &clk_dp_ops, 553 }, 554 }; 555 556 static struct clk_rcg2 disp_cc_mdss_dptx1_pixel1_clk_src = { 557 .cmd_rcgr = 0x8264, 558 .mnd_width = 16, 559 .hid_width = 5, 560 .parent_map = disp_cc_parent_map_2, 561 .freq_tbl = ftbl_disp_cc_esync0_clk_src, 562 .clkr.hw.init = &(const struct clk_init_data) { 563 .name = "disp_cc_mdss_dptx1_pixel1_clk_src", 564 .parent_data = disp_cc_parent_data_2, 565 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), 566 .flags = CLK_SET_RATE_PARENT, 567 .ops = &clk_dp_ops, 568 }, 569 }; 570 571 static struct clk_rcg2 disp_cc_mdss_dptx2_aux_clk_src = { 572 .cmd_rcgr = 0x82fc, 573 .mnd_width = 0, 574 .hid_width = 5, 575 .parent_map = disp_cc_parent_map_0, 576 .freq_tbl = ftbl_disp_cc_esync0_clk_src, 577 .clkr.hw.init = &(const struct clk_init_data) { 578 .name = "disp_cc_mdss_dptx2_aux_clk_src", 579 .parent_data = disp_cc_parent_data_0, 580 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), 581 .flags = CLK_SET_RATE_PARENT, 582 .ops = &clk_rcg2_ops, 583 }, 584 }; 585 586 static struct clk_rcg2 disp_cc_mdss_dptx2_link_clk_src = { 587 .cmd_rcgr = 0x82b0, 588 .mnd_width = 0, 589 .hid_width = 5, 590 .parent_map = disp_cc_parent_map_3, 591 .freq_tbl = ftbl_disp_cc_esync0_clk_src, 592 .clkr.hw.init = &(const struct clk_init_data) { 593 .name = "disp_cc_mdss_dptx2_link_clk_src", 594 .parent_data = disp_cc_parent_data_3, 595 .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), 596 .flags = CLK_SET_RATE_PARENT, 597 .ops = &clk_byte2_ops, 598 }, 599 }; 600 601 static struct clk_rcg2 disp_cc_mdss_dptx2_pixel0_clk_src = { 602 .cmd_rcgr = 0x82cc, 603 .mnd_width = 16, 604 .hid_width = 5, 605 .parent_map = disp_cc_parent_map_2, 606 .freq_tbl = ftbl_disp_cc_esync0_clk_src, 607 .clkr.hw.init = &(const struct clk_init_data) { 608 .name = "disp_cc_mdss_dptx2_pixel0_clk_src", 609 .parent_data = disp_cc_parent_data_2, 610 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), 611 .flags = CLK_SET_RATE_PARENT, 612 .ops = &clk_dp_ops, 613 }, 614 }; 615 616 static struct clk_rcg2 disp_cc_mdss_dptx2_pixel1_clk_src = { 617 .cmd_rcgr = 0x82e4, 618 .mnd_width = 16, 619 .hid_width = 5, 620 .parent_map = disp_cc_parent_map_2, 621 .freq_tbl = ftbl_disp_cc_esync0_clk_src, 622 .clkr.hw.init = &(const struct clk_init_data) { 623 .name = "disp_cc_mdss_dptx2_pixel1_clk_src", 624 .parent_data = disp_cc_parent_data_2, 625 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), 626 .flags = CLK_SET_RATE_PARENT, 627 .ops = &clk_dp_ops, 628 }, 629 }; 630 631 static struct clk_rcg2 disp_cc_mdss_dptx3_aux_clk_src = { 632 .cmd_rcgr = 0x8348, 633 .mnd_width = 0, 634 .hid_width = 5, 635 .parent_map = disp_cc_parent_map_0, 636 .freq_tbl = ftbl_disp_cc_esync0_clk_src, 637 .clkr.hw.init = &(const struct clk_init_data) { 638 .name = "disp_cc_mdss_dptx3_aux_clk_src", 639 .parent_data = disp_cc_parent_data_0, 640 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), 641 .flags = CLK_SET_RATE_PARENT, 642 .ops = &clk_rcg2_ops, 643 }, 644 }; 645 646 static struct clk_rcg2 disp_cc_mdss_dptx3_link_clk_src = { 647 .cmd_rcgr = 0x832c, 648 .mnd_width = 0, 649 .hid_width = 5, 650 .parent_map = disp_cc_parent_map_3, 651 .freq_tbl = ftbl_disp_cc_esync0_clk_src, 652 .clkr.hw.init = &(const struct clk_init_data) { 653 .name = "disp_cc_mdss_dptx3_link_clk_src", 654 .parent_data = disp_cc_parent_data_3, 655 .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), 656 .flags = CLK_SET_RATE_PARENT, 657 .ops = &clk_byte2_ops, 658 }, 659 }; 660 661 static struct clk_rcg2 disp_cc_mdss_dptx3_pixel0_clk_src = { 662 .cmd_rcgr = 0x8314, 663 .mnd_width = 16, 664 .hid_width = 5, 665 .parent_map = disp_cc_parent_map_2, 666 .freq_tbl = ftbl_disp_cc_esync0_clk_src, 667 .clkr.hw.init = &(const struct clk_init_data) { 668 .name = "disp_cc_mdss_dptx3_pixel0_clk_src", 669 .parent_data = disp_cc_parent_data_2, 670 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), 671 .flags = CLK_SET_RATE_PARENT, 672 .ops = &clk_dp_ops, 673 }, 674 }; 675 676 static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = { 677 .cmd_rcgr = 0x81b8, 678 .mnd_width = 0, 679 .hid_width = 5, 680 .parent_map = disp_cc_parent_map_6, 681 .freq_tbl = ftbl_disp_cc_esync0_clk_src, 682 .clkr.hw.init = &(const struct clk_init_data) { 683 .name = "disp_cc_mdss_esc0_clk_src", 684 .parent_data = disp_cc_parent_data_6, 685 .num_parents = ARRAY_SIZE(disp_cc_parent_data_6), 686 .flags = CLK_SET_RATE_PARENT, 687 .ops = &clk_rcg2_shared_ops, 688 }, 689 }; 690 691 static struct clk_rcg2 disp_cc_mdss_esc1_clk_src = { 692 .cmd_rcgr = 0x81d0, 693 .mnd_width = 0, 694 .hid_width = 5, 695 .parent_map = disp_cc_parent_map_6, 696 .freq_tbl = ftbl_disp_cc_esync0_clk_src, 697 .clkr.hw.init = &(const struct clk_init_data) { 698 .name = "disp_cc_mdss_esc1_clk_src", 699 .parent_data = disp_cc_parent_data_6, 700 .num_parents = ARRAY_SIZE(disp_cc_parent_data_6), 701 .flags = CLK_SET_RATE_PARENT, 702 .ops = &clk_rcg2_shared_ops, 703 }, 704 }; 705 706 static struct clk_rcg2 disp_cc_mdss_hdmi_app_clk_src = { 707 .cmd_rcgr = 0x83a8, 708 .mnd_width = 0, 709 .hid_width = 5, 710 .parent_map = disp_cc_parent_map_9, 711 .freq_tbl = ftbl_disp_cc_esync0_clk_src, 712 .clkr.hw.init = &(const struct clk_init_data) { 713 .name = "disp_cc_mdss_hdmi_app_clk_src", 714 .parent_data = disp_cc_parent_data_9, 715 .num_parents = ARRAY_SIZE(disp_cc_parent_data_9), 716 .flags = CLK_SET_RATE_PARENT, 717 .ops = &clk_rcg2_shared_ops, 718 }, 719 }; 720 721 static struct clk_rcg2 disp_cc_mdss_hdmi_pclk_clk_src = { 722 .cmd_rcgr = 0x8390, 723 .mnd_width = 16, 724 .hid_width = 5, 725 .parent_map = disp_cc_parent_map_10, 726 .freq_tbl = ftbl_disp_cc_esync0_clk_src, 727 .clkr.hw.init = &(const struct clk_init_data) { 728 .name = "disp_cc_mdss_hdmi_pclk_clk_src", 729 .parent_data = disp_cc_parent_data_10, 730 .num_parents = ARRAY_SIZE(disp_cc_parent_data_10), 731 .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, 732 .ops = &clk_pixel_ops, 733 }, 734 }; 735 736 static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] = { 737 F(85714286, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 738 F(100000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 739 F(150000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 740 F(207000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 741 F(342000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 742 F(417000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 743 F(535000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 744 F(600000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 745 F(660000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 746 { } 747 }; 748 749 static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = { 750 .cmd_rcgr = 0x8150, 751 .mnd_width = 0, 752 .hid_width = 5, 753 .parent_map = disp_cc_parent_map_11, 754 .freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src, 755 .clkr.hw.init = &(const struct clk_init_data) { 756 .name = "disp_cc_mdss_mdp_clk_src", 757 .parent_data = disp_cc_parent_data_11, 758 .num_parents = ARRAY_SIZE(disp_cc_parent_data_11), 759 .flags = CLK_SET_RATE_PARENT, 760 .ops = &clk_rcg2_shared_ops, 761 }, 762 }; 763 764 static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = { 765 .cmd_rcgr = 0x8108, 766 .mnd_width = 8, 767 .hid_width = 5, 768 .parent_map = disp_cc_parent_map_1, 769 .freq_tbl = ftbl_disp_cc_esync0_clk_src, 770 .clkr.hw.init = &(const struct clk_init_data) { 771 .name = "disp_cc_mdss_pclk0_clk_src", 772 .parent_data = disp_cc_parent_data_1, 773 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), 774 .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, 775 .ops = &clk_pixel_ops, 776 }, 777 }; 778 779 static struct clk_rcg2 disp_cc_mdss_pclk1_clk_src = { 780 .cmd_rcgr = 0x8120, 781 .mnd_width = 8, 782 .hid_width = 5, 783 .parent_map = disp_cc_parent_map_1, 784 .freq_tbl = ftbl_disp_cc_esync0_clk_src, 785 .clkr.hw.init = &(const struct clk_init_data) { 786 .name = "disp_cc_mdss_pclk1_clk_src", 787 .parent_data = disp_cc_parent_data_1, 788 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), 789 .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, 790 .ops = &clk_pixel_ops, 791 }, 792 }; 793 794 static struct clk_rcg2 disp_cc_mdss_pclk2_clk_src = { 795 .cmd_rcgr = 0x8138, 796 .mnd_width = 8, 797 .hid_width = 5, 798 .parent_map = disp_cc_parent_map_1, 799 .freq_tbl = ftbl_disp_cc_esync0_clk_src, 800 .clkr.hw.init = &(const struct clk_init_data) { 801 .name = "disp_cc_mdss_pclk2_clk_src", 802 .parent_data = disp_cc_parent_data_1, 803 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), 804 .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, 805 .ops = &clk_pixel_ops, 806 }, 807 }; 808 809 static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = { 810 .cmd_rcgr = 0x8168, 811 .mnd_width = 0, 812 .hid_width = 5, 813 .parent_map = disp_cc_parent_map_0, 814 .freq_tbl = ftbl_disp_cc_esync0_clk_src, 815 .clkr.hw.init = &(const struct clk_init_data) { 816 .name = "disp_cc_mdss_vsync_clk_src", 817 .parent_data = disp_cc_parent_data_0, 818 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), 819 .flags = CLK_SET_RATE_PARENT, 820 .ops = &clk_rcg2_ops, 821 }, 822 }; 823 824 static const struct freq_tbl ftbl_disp_cc_osc_clk_src[] = { 825 F(38400000, P_DISP_CC_PLL2_OUT_MAIN, 1, 0, 0), 826 { } 827 }; 828 829 static struct clk_rcg2 disp_cc_osc_clk_src = { 830 .cmd_rcgr = 0x80f0, 831 .mnd_width = 0, 832 .hid_width = 5, 833 .parent_map = disp_cc_parent_map_12, 834 .freq_tbl = ftbl_disp_cc_osc_clk_src, 835 .clkr.hw.init = &(const struct clk_init_data) { 836 .name = "disp_cc_osc_clk_src", 837 .parent_data = disp_cc_parent_data_12, 838 .num_parents = ARRAY_SIZE(disp_cc_parent_data_12), 839 .flags = CLK_SET_RATE_PARENT, 840 .ops = &clk_rcg2_ops, 841 }, 842 }; 843 844 static const struct freq_tbl ftbl_disp_cc_sleep_clk_src[] = { 845 F(32000, P_SLEEP_CLK, 1, 0, 0), 846 { } 847 }; 848 849 static struct clk_rcg2 disp_cc_sleep_clk_src = { 850 .cmd_rcgr = 0xe064, 851 .mnd_width = 0, 852 .hid_width = 5, 853 .parent_map = disp_cc_parent_map_13, 854 .freq_tbl = ftbl_disp_cc_sleep_clk_src, 855 .clkr.hw.init = &(const struct clk_init_data) { 856 .name = "disp_cc_sleep_clk_src", 857 .parent_data = disp_cc_parent_data_13_ao, 858 .num_parents = ARRAY_SIZE(disp_cc_parent_data_13_ao), 859 .flags = CLK_SET_RATE_PARENT, 860 .ops = &clk_rcg2_ops, 861 }, 862 }; 863 864 static struct clk_rcg2 disp_cc_xo_clk_src = { 865 .cmd_rcgr = 0xe044, 866 .mnd_width = 0, 867 .hid_width = 5, 868 .parent_map = disp_cc_parent_map_0, 869 .freq_tbl = ftbl_disp_cc_esync0_clk_src, 870 .clkr.hw.init = &(const struct clk_init_data) { 871 .name = "disp_cc_xo_clk_src", 872 .parent_data = disp_cc_parent_data_0_ao, 873 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0_ao), 874 .flags = CLK_SET_RATE_PARENT, 875 .ops = &clk_rcg2_ops, 876 }, 877 }; 878 879 static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = { 880 .reg = 0x8198, 881 .shift = 0, 882 .width = 4, 883 .clkr.hw.init = &(const struct clk_init_data) { 884 .name = "disp_cc_mdss_byte0_div_clk_src", 885 .parent_hws = (const struct clk_hw*[]) { 886 &disp_cc_mdss_byte0_clk_src.clkr.hw, 887 }, 888 .num_parents = 1, 889 .ops = &clk_regmap_div_ops, 890 }, 891 }; 892 893 static struct clk_regmap_div disp_cc_mdss_byte1_div_clk_src = { 894 .reg = 0x81b4, 895 .shift = 0, 896 .width = 4, 897 .clkr.hw.init = &(const struct clk_init_data) { 898 .name = "disp_cc_mdss_byte1_div_clk_src", 899 .parent_hws = (const struct clk_hw*[]) { 900 &disp_cc_mdss_byte1_clk_src.clkr.hw, 901 }, 902 .num_parents = 1, 903 .ops = &clk_regmap_div_ops, 904 }, 905 }; 906 907 static struct clk_regmap_div disp_cc_mdss_dptx0_link_div_clk_src = { 908 .reg = 0x8200, 909 .shift = 0, 910 .width = 4, 911 .clkr.hw.init = &(const struct clk_init_data) { 912 .name = "disp_cc_mdss_dptx0_link_div_clk_src", 913 .parent_hws = (const struct clk_hw*[]) { 914 &disp_cc_mdss_dptx0_link_clk_src.clkr.hw, 915 }, 916 .num_parents = 1, 917 .flags = CLK_SET_RATE_PARENT, 918 .ops = &clk_regmap_div_ro_ops, 919 }, 920 }; 921 922 static struct clk_regmap_div disp_cc_mdss_dptx1_link_div_clk_src = { 923 .reg = 0x8294, 924 .shift = 0, 925 .width = 4, 926 .clkr.hw.init = &(const struct clk_init_data) { 927 .name = "disp_cc_mdss_dptx1_link_div_clk_src", 928 .parent_hws = (const struct clk_hw*[]) { 929 &disp_cc_mdss_dptx1_link_clk_src.clkr.hw, 930 }, 931 .num_parents = 1, 932 .flags = CLK_SET_RATE_PARENT, 933 .ops = &clk_regmap_div_ro_ops, 934 }, 935 }; 936 937 static struct clk_regmap_div disp_cc_mdss_dptx2_link_div_clk_src = { 938 .reg = 0x82c8, 939 .shift = 0, 940 .width = 4, 941 .clkr.hw.init = &(const struct clk_init_data) { 942 .name = "disp_cc_mdss_dptx2_link_div_clk_src", 943 .parent_hws = (const struct clk_hw*[]) { 944 &disp_cc_mdss_dptx2_link_clk_src.clkr.hw, 945 }, 946 .num_parents = 1, 947 .flags = CLK_SET_RATE_PARENT, 948 .ops = &clk_regmap_div_ro_ops, 949 }, 950 }; 951 952 static struct clk_regmap_div disp_cc_mdss_dptx3_link_div_clk_src = { 953 .reg = 0x8344, 954 .shift = 0, 955 .width = 4, 956 .clkr.hw.init = &(const struct clk_init_data) { 957 .name = "disp_cc_mdss_dptx3_link_div_clk_src", 958 .parent_hws = (const struct clk_hw*[]) { 959 &disp_cc_mdss_dptx3_link_clk_src.clkr.hw, 960 }, 961 .num_parents = 1, 962 .flags = CLK_SET_RATE_PARENT, 963 .ops = &clk_regmap_div_ro_ops, 964 }, 965 }; 966 967 static struct clk_regmap_div disp_cc_mdss_hdmi_pclk_div_clk_src = { 968 .reg = 0x838c, 969 .shift = 0, 970 .width = 4, 971 .clkr.hw.init = &(const struct clk_init_data) { 972 .name = "disp_cc_mdss_hdmi_pclk_div_clk_src", 973 .parent_hws = (const struct clk_hw*[]) { 974 &disp_cc_mdss_hdmi_pclk_clk_src.clkr.hw, 975 }, 976 .num_parents = 1, 977 .flags = CLK_SET_RATE_PARENT, 978 .ops = &clk_regmap_div_ro_ops, 979 }, 980 }; 981 982 static struct clk_branch disp_cc_esync0_clk = { 983 .halt_reg = 0x80b8, 984 .halt_check = BRANCH_HALT, 985 .clkr = { 986 .enable_reg = 0x80b8, 987 .enable_mask = BIT(0), 988 .hw.init = &(const struct clk_init_data) { 989 .name = "disp_cc_esync0_clk", 990 .parent_hws = (const struct clk_hw*[]) { 991 &disp_cc_esync0_clk_src.clkr.hw, 992 }, 993 .num_parents = 1, 994 .flags = CLK_SET_RATE_PARENT, 995 .ops = &clk_branch2_ops, 996 }, 997 }, 998 }; 999 1000 static struct clk_branch disp_cc_esync1_clk = { 1001 .halt_reg = 0x80bc, 1002 .halt_check = BRANCH_HALT, 1003 .clkr = { 1004 .enable_reg = 0x80bc, 1005 .enable_mask = BIT(0), 1006 .hw.init = &(const struct clk_init_data) { 1007 .name = "disp_cc_esync1_clk", 1008 .parent_hws = (const struct clk_hw*[]) { 1009 &disp_cc_esync1_clk_src.clkr.hw, 1010 }, 1011 .num_parents = 1, 1012 .flags = CLK_SET_RATE_PARENT, 1013 .ops = &clk_branch2_ops, 1014 }, 1015 }, 1016 }; 1017 1018 static struct clk_branch disp_cc_mdss_accu_shift_clk = { 1019 .halt_reg = 0xe060, 1020 .halt_check = BRANCH_HALT_VOTED, 1021 .clkr = { 1022 .enable_reg = 0xe060, 1023 .enable_mask = BIT(0), 1024 .hw.init = &(const struct clk_init_data) { 1025 .name = "disp_cc_mdss_accu_shift_clk", 1026 .parent_hws = (const struct clk_hw*[]) { 1027 &disp_cc_xo_clk_src.clkr.hw, 1028 }, 1029 .num_parents = 1, 1030 .flags = CLK_SET_RATE_PARENT, 1031 .ops = &clk_branch2_ops, 1032 }, 1033 }, 1034 }; 1035 1036 static struct clk_branch disp_cc_mdss_ahb1_clk = { 1037 .halt_reg = 0xa028, 1038 .halt_check = BRANCH_HALT, 1039 .clkr = { 1040 .enable_reg = 0xa028, 1041 .enable_mask = BIT(0), 1042 .hw.init = &(const struct clk_init_data) { 1043 .name = "disp_cc_mdss_ahb1_clk", 1044 .parent_hws = (const struct clk_hw*[]) { 1045 &disp_cc_mdss_ahb_clk_src.clkr.hw, 1046 }, 1047 .num_parents = 1, 1048 .flags = CLK_SET_RATE_PARENT, 1049 .ops = &clk_branch2_ops, 1050 }, 1051 }, 1052 }; 1053 1054 static struct clk_branch disp_cc_mdss_ahb_clk = { 1055 .halt_reg = 0x80b0, 1056 .halt_check = BRANCH_HALT, 1057 .clkr = { 1058 .enable_reg = 0x80b0, 1059 .enable_mask = BIT(0), 1060 .hw.init = &(const struct clk_init_data) { 1061 .name = "disp_cc_mdss_ahb_clk", 1062 .parent_hws = (const struct clk_hw*[]) { 1063 &disp_cc_mdss_ahb_clk_src.clkr.hw, 1064 }, 1065 .num_parents = 1, 1066 .flags = CLK_SET_RATE_PARENT, 1067 .ops = &clk_branch2_ops, 1068 }, 1069 }, 1070 }; 1071 1072 static struct clk_branch disp_cc_mdss_byte0_clk = { 1073 .halt_reg = 0x8034, 1074 .halt_check = BRANCH_HALT, 1075 .clkr = { 1076 .enable_reg = 0x8034, 1077 .enable_mask = BIT(0), 1078 .hw.init = &(const struct clk_init_data) { 1079 .name = "disp_cc_mdss_byte0_clk", 1080 .parent_hws = (const struct clk_hw*[]) { 1081 &disp_cc_mdss_byte0_clk_src.clkr.hw, 1082 }, 1083 .num_parents = 1, 1084 .flags = CLK_SET_RATE_PARENT, 1085 .ops = &clk_branch2_ops, 1086 }, 1087 }, 1088 }; 1089 1090 static struct clk_branch disp_cc_mdss_byte0_intf_clk = { 1091 .halt_reg = 0x8038, 1092 .halt_check = BRANCH_HALT, 1093 .clkr = { 1094 .enable_reg = 0x8038, 1095 .enable_mask = BIT(0), 1096 .hw.init = &(const struct clk_init_data) { 1097 .name = "disp_cc_mdss_byte0_intf_clk", 1098 .parent_hws = (const struct clk_hw*[]) { 1099 &disp_cc_mdss_byte0_div_clk_src.clkr.hw, 1100 }, 1101 .num_parents = 1, 1102 .flags = CLK_SET_RATE_PARENT, 1103 .ops = &clk_branch2_ops, 1104 }, 1105 }, 1106 }; 1107 1108 static struct clk_branch disp_cc_mdss_byte1_clk = { 1109 .halt_reg = 0x803c, 1110 .halt_check = BRANCH_HALT, 1111 .clkr = { 1112 .enable_reg = 0x803c, 1113 .enable_mask = BIT(0), 1114 .hw.init = &(const struct clk_init_data) { 1115 .name = "disp_cc_mdss_byte1_clk", 1116 .parent_hws = (const struct clk_hw*[]) { 1117 &disp_cc_mdss_byte1_clk_src.clkr.hw, 1118 }, 1119 .num_parents = 1, 1120 .flags = CLK_SET_RATE_PARENT, 1121 .ops = &clk_branch2_ops, 1122 }, 1123 }, 1124 }; 1125 1126 static struct clk_branch disp_cc_mdss_byte1_intf_clk = { 1127 .halt_reg = 0x8040, 1128 .halt_check = BRANCH_HALT, 1129 .clkr = { 1130 .enable_reg = 0x8040, 1131 .enable_mask = BIT(0), 1132 .hw.init = &(const struct clk_init_data) { 1133 .name = "disp_cc_mdss_byte1_intf_clk", 1134 .parent_hws = (const struct clk_hw*[]) { 1135 &disp_cc_mdss_byte1_div_clk_src.clkr.hw, 1136 }, 1137 .num_parents = 1, 1138 .flags = CLK_SET_RATE_PARENT, 1139 .ops = &clk_branch2_ops, 1140 }, 1141 }, 1142 }; 1143 1144 static struct clk_branch disp_cc_mdss_dptx0_aux_clk = { 1145 .halt_reg = 0x8064, 1146 .halt_check = BRANCH_HALT, 1147 .clkr = { 1148 .enable_reg = 0x8064, 1149 .enable_mask = BIT(0), 1150 .hw.init = &(const struct clk_init_data) { 1151 .name = "disp_cc_mdss_dptx0_aux_clk", 1152 .parent_hws = (const struct clk_hw*[]) { 1153 &disp_cc_mdss_dptx0_aux_clk_src.clkr.hw, 1154 }, 1155 .num_parents = 1, 1156 .flags = CLK_SET_RATE_PARENT, 1157 .ops = &clk_branch2_ops, 1158 }, 1159 }, 1160 }; 1161 1162 static struct clk_branch disp_cc_mdss_dptx0_crypto_clk = { 1163 .halt_reg = 0x8058, 1164 .halt_check = BRANCH_HALT, 1165 .clkr = { 1166 .enable_reg = 0x8058, 1167 .enable_mask = BIT(0), 1168 .hw.init = &(const struct clk_init_data) { 1169 .name = "disp_cc_mdss_dptx0_crypto_clk", 1170 .parent_hws = (const struct clk_hw*[]) { 1171 &disp_cc_mdss_dptx0_link_clk_src.clkr.hw, 1172 }, 1173 .num_parents = 1, 1174 .flags = CLK_SET_RATE_PARENT, 1175 .ops = &clk_branch2_ops, 1176 }, 1177 }, 1178 }; 1179 1180 static struct clk_branch disp_cc_mdss_dptx0_link_clk = { 1181 .halt_reg = 0x804c, 1182 .halt_check = BRANCH_HALT, 1183 .clkr = { 1184 .enable_reg = 0x804c, 1185 .enable_mask = BIT(0), 1186 .hw.init = &(const struct clk_init_data) { 1187 .name = "disp_cc_mdss_dptx0_link_clk", 1188 .parent_hws = (const struct clk_hw*[]) { 1189 &disp_cc_mdss_dptx0_link_clk_src.clkr.hw, 1190 }, 1191 .num_parents = 1, 1192 .flags = CLK_SET_RATE_PARENT, 1193 .ops = &clk_branch2_ops, 1194 }, 1195 }, 1196 }; 1197 1198 static struct clk_branch disp_cc_mdss_dptx0_link_intf_clk = { 1199 .halt_reg = 0x8054, 1200 .halt_check = BRANCH_HALT, 1201 .clkr = { 1202 .enable_reg = 0x8054, 1203 .enable_mask = BIT(0), 1204 .hw.init = &(const struct clk_init_data) { 1205 .name = "disp_cc_mdss_dptx0_link_intf_clk", 1206 .parent_hws = (const struct clk_hw*[]) { 1207 &disp_cc_mdss_dptx0_link_div_clk_src.clkr.hw, 1208 }, 1209 .num_parents = 1, 1210 .flags = CLK_SET_RATE_PARENT, 1211 .ops = &clk_branch2_ops, 1212 }, 1213 }, 1214 }; 1215 1216 static struct clk_branch disp_cc_mdss_dptx0_pixel0_clk = { 1217 .halt_reg = 0x805c, 1218 .halt_check = BRANCH_HALT, 1219 .clkr = { 1220 .enable_reg = 0x805c, 1221 .enable_mask = BIT(0), 1222 .hw.init = &(const struct clk_init_data) { 1223 .name = "disp_cc_mdss_dptx0_pixel0_clk", 1224 .parent_hws = (const struct clk_hw*[]) { 1225 &disp_cc_mdss_dptx0_pixel0_clk_src.clkr.hw, 1226 }, 1227 .num_parents = 1, 1228 .flags = CLK_SET_RATE_PARENT, 1229 .ops = &clk_branch2_ops, 1230 }, 1231 }, 1232 }; 1233 1234 static struct clk_branch disp_cc_mdss_dptx0_pixel1_clk = { 1235 .halt_reg = 0x8060, 1236 .halt_check = BRANCH_HALT, 1237 .clkr = { 1238 .enable_reg = 0x8060, 1239 .enable_mask = BIT(0), 1240 .hw.init = &(const struct clk_init_data) { 1241 .name = "disp_cc_mdss_dptx0_pixel1_clk", 1242 .parent_hws = (const struct clk_hw*[]) { 1243 &disp_cc_mdss_dptx0_pixel1_clk_src.clkr.hw, 1244 }, 1245 .num_parents = 1, 1246 .flags = CLK_SET_RATE_PARENT, 1247 .ops = &clk_branch2_ops, 1248 }, 1249 }, 1250 }; 1251 1252 static struct clk_branch disp_cc_mdss_dptx0_usb_router_link_intf_clk = { 1253 .halt_reg = 0x8050, 1254 .halt_check = BRANCH_HALT, 1255 .clkr = { 1256 .enable_reg = 0x8050, 1257 .enable_mask = BIT(0), 1258 .hw.init = &(const struct clk_init_data) { 1259 .name = "disp_cc_mdss_dptx0_usb_router_link_intf_clk", 1260 .parent_hws = (const struct clk_hw*[]) { 1261 &disp_cc_mdss_dptx0_link_div_clk_src.clkr.hw, 1262 }, 1263 .num_parents = 1, 1264 .flags = CLK_SET_RATE_PARENT, 1265 .ops = &clk_branch2_ops, 1266 }, 1267 }, 1268 }; 1269 1270 static struct clk_branch disp_cc_mdss_dptx1_aux_clk = { 1271 .halt_reg = 0x8080, 1272 .halt_check = BRANCH_HALT, 1273 .clkr = { 1274 .enable_reg = 0x8080, 1275 .enable_mask = BIT(0), 1276 .hw.init = &(const struct clk_init_data) { 1277 .name = "disp_cc_mdss_dptx1_aux_clk", 1278 .parent_hws = (const struct clk_hw*[]) { 1279 &disp_cc_mdss_dptx1_aux_clk_src.clkr.hw, 1280 }, 1281 .num_parents = 1, 1282 .flags = CLK_SET_RATE_PARENT, 1283 .ops = &clk_branch2_ops, 1284 }, 1285 }, 1286 }; 1287 1288 static struct clk_branch disp_cc_mdss_dptx1_crypto_clk = { 1289 .halt_reg = 0x807c, 1290 .halt_check = BRANCH_HALT, 1291 .clkr = { 1292 .enable_reg = 0x807c, 1293 .enable_mask = BIT(0), 1294 .hw.init = &(const struct clk_init_data) { 1295 .name = "disp_cc_mdss_dptx1_crypto_clk", 1296 .parent_hws = (const struct clk_hw*[]) { 1297 &disp_cc_mdss_dptx1_link_clk_src.clkr.hw, 1298 }, 1299 .num_parents = 1, 1300 .flags = CLK_SET_RATE_PARENT, 1301 .ops = &clk_branch2_ops, 1302 }, 1303 }, 1304 }; 1305 1306 static struct clk_branch disp_cc_mdss_dptx1_link_clk = { 1307 .halt_reg = 0x8070, 1308 .halt_check = BRANCH_HALT, 1309 .clkr = { 1310 .enable_reg = 0x8070, 1311 .enable_mask = BIT(0), 1312 .hw.init = &(const struct clk_init_data) { 1313 .name = "disp_cc_mdss_dptx1_link_clk", 1314 .parent_hws = (const struct clk_hw*[]) { 1315 &disp_cc_mdss_dptx1_link_clk_src.clkr.hw, 1316 }, 1317 .num_parents = 1, 1318 .flags = CLK_SET_RATE_PARENT, 1319 .ops = &clk_branch2_ops, 1320 }, 1321 }, 1322 }; 1323 1324 static struct clk_branch disp_cc_mdss_dptx1_link_intf_clk = { 1325 .halt_reg = 0x8078, 1326 .halt_check = BRANCH_HALT, 1327 .clkr = { 1328 .enable_reg = 0x8078, 1329 .enable_mask = BIT(0), 1330 .hw.init = &(const struct clk_init_data) { 1331 .name = "disp_cc_mdss_dptx1_link_intf_clk", 1332 .parent_hws = (const struct clk_hw*[]) { 1333 &disp_cc_mdss_dptx1_link_div_clk_src.clkr.hw, 1334 }, 1335 .num_parents = 1, 1336 .flags = CLK_SET_RATE_PARENT, 1337 .ops = &clk_branch2_ops, 1338 }, 1339 }, 1340 }; 1341 1342 static struct clk_branch disp_cc_mdss_dptx1_pixel0_clk = { 1343 .halt_reg = 0x8068, 1344 .halt_check = BRANCH_HALT, 1345 .clkr = { 1346 .enable_reg = 0x8068, 1347 .enable_mask = BIT(0), 1348 .hw.init = &(const struct clk_init_data) { 1349 .name = "disp_cc_mdss_dptx1_pixel0_clk", 1350 .parent_hws = (const struct clk_hw*[]) { 1351 &disp_cc_mdss_dptx1_pixel0_clk_src.clkr.hw, 1352 }, 1353 .num_parents = 1, 1354 .flags = CLK_SET_RATE_PARENT, 1355 .ops = &clk_branch2_ops, 1356 }, 1357 }, 1358 }; 1359 1360 static struct clk_branch disp_cc_mdss_dptx1_pixel1_clk = { 1361 .halt_reg = 0x806c, 1362 .halt_check = BRANCH_HALT, 1363 .clkr = { 1364 .enable_reg = 0x806c, 1365 .enable_mask = BIT(0), 1366 .hw.init = &(const struct clk_init_data) { 1367 .name = "disp_cc_mdss_dptx1_pixel1_clk", 1368 .parent_hws = (const struct clk_hw*[]) { 1369 &disp_cc_mdss_dptx1_pixel1_clk_src.clkr.hw, 1370 }, 1371 .num_parents = 1, 1372 .flags = CLK_SET_RATE_PARENT, 1373 .ops = &clk_branch2_ops, 1374 }, 1375 }, 1376 }; 1377 1378 static struct clk_branch disp_cc_mdss_dptx1_usb_router_link_intf_clk = { 1379 .halt_reg = 0x8074, 1380 .halt_check = BRANCH_HALT, 1381 .clkr = { 1382 .enable_reg = 0x8074, 1383 .enable_mask = BIT(0), 1384 .hw.init = &(const struct clk_init_data) { 1385 .name = "disp_cc_mdss_dptx1_usb_router_link_intf_clk", 1386 .parent_hws = (const struct clk_hw*[]) { 1387 &disp_cc_mdss_dptx1_link_div_clk_src.clkr.hw, 1388 }, 1389 .num_parents = 1, 1390 .flags = CLK_SET_RATE_PARENT, 1391 .ops = &clk_branch2_ops, 1392 }, 1393 }, 1394 }; 1395 1396 static struct clk_branch disp_cc_mdss_dptx2_aux_clk = { 1397 .halt_reg = 0x8098, 1398 .halt_check = BRANCH_HALT, 1399 .clkr = { 1400 .enable_reg = 0x8098, 1401 .enable_mask = BIT(0), 1402 .hw.init = &(const struct clk_init_data) { 1403 .name = "disp_cc_mdss_dptx2_aux_clk", 1404 .parent_hws = (const struct clk_hw*[]) { 1405 &disp_cc_mdss_dptx2_aux_clk_src.clkr.hw, 1406 }, 1407 .num_parents = 1, 1408 .flags = CLK_SET_RATE_PARENT, 1409 .ops = &clk_branch2_ops, 1410 }, 1411 }, 1412 }; 1413 1414 static struct clk_branch disp_cc_mdss_dptx2_crypto_clk = { 1415 .halt_reg = 0x8094, 1416 .halt_check = BRANCH_HALT, 1417 .clkr = { 1418 .enable_reg = 0x8094, 1419 .enable_mask = BIT(0), 1420 .hw.init = &(const struct clk_init_data) { 1421 .name = "disp_cc_mdss_dptx2_crypto_clk", 1422 .parent_hws = (const struct clk_hw*[]) { 1423 &disp_cc_mdss_dptx2_link_clk_src.clkr.hw, 1424 }, 1425 .num_parents = 1, 1426 .flags = CLK_SET_RATE_PARENT, 1427 .ops = &clk_branch2_ops, 1428 }, 1429 }, 1430 }; 1431 1432 static struct clk_branch disp_cc_mdss_dptx2_link_clk = { 1433 .halt_reg = 0x808c, 1434 .halt_check = BRANCH_HALT, 1435 .clkr = { 1436 .enable_reg = 0x808c, 1437 .enable_mask = BIT(0), 1438 .hw.init = &(const struct clk_init_data) { 1439 .name = "disp_cc_mdss_dptx2_link_clk", 1440 .parent_hws = (const struct clk_hw*[]) { 1441 &disp_cc_mdss_dptx2_link_clk_src.clkr.hw, 1442 }, 1443 .num_parents = 1, 1444 .flags = CLK_SET_RATE_PARENT, 1445 .ops = &clk_branch2_ops, 1446 }, 1447 }, 1448 }; 1449 1450 static struct clk_branch disp_cc_mdss_dptx2_link_intf_clk = { 1451 .halt_reg = 0x8090, 1452 .halt_check = BRANCH_HALT, 1453 .clkr = { 1454 .enable_reg = 0x8090, 1455 .enable_mask = BIT(0), 1456 .hw.init = &(const struct clk_init_data) { 1457 .name = "disp_cc_mdss_dptx2_link_intf_clk", 1458 .parent_hws = (const struct clk_hw*[]) { 1459 &disp_cc_mdss_dptx2_link_div_clk_src.clkr.hw, 1460 }, 1461 .num_parents = 1, 1462 .flags = CLK_SET_RATE_PARENT, 1463 .ops = &clk_branch2_ops, 1464 }, 1465 }, 1466 }; 1467 1468 static struct clk_branch disp_cc_mdss_dptx2_pixel0_clk = { 1469 .halt_reg = 0x8084, 1470 .halt_check = BRANCH_HALT, 1471 .clkr = { 1472 .enable_reg = 0x8084, 1473 .enable_mask = BIT(0), 1474 .hw.init = &(const struct clk_init_data) { 1475 .name = "disp_cc_mdss_dptx2_pixel0_clk", 1476 .parent_hws = (const struct clk_hw*[]) { 1477 &disp_cc_mdss_dptx2_pixel0_clk_src.clkr.hw, 1478 }, 1479 .num_parents = 1, 1480 .flags = CLK_SET_RATE_PARENT, 1481 .ops = &clk_branch2_ops, 1482 }, 1483 }, 1484 }; 1485 1486 static struct clk_branch disp_cc_mdss_dptx2_pixel1_clk = { 1487 .halt_reg = 0x8088, 1488 .halt_check = BRANCH_HALT, 1489 .clkr = { 1490 .enable_reg = 0x8088, 1491 .enable_mask = BIT(0), 1492 .hw.init = &(const struct clk_init_data) { 1493 .name = "disp_cc_mdss_dptx2_pixel1_clk", 1494 .parent_hws = (const struct clk_hw*[]) { 1495 &disp_cc_mdss_dptx2_pixel1_clk_src.clkr.hw, 1496 }, 1497 .num_parents = 1, 1498 .flags = CLK_SET_RATE_PARENT, 1499 .ops = &clk_branch2_ops, 1500 }, 1501 }, 1502 }; 1503 1504 static struct clk_branch disp_cc_mdss_dptx3_aux_clk = { 1505 .halt_reg = 0x80a8, 1506 .halt_check = BRANCH_HALT, 1507 .clkr = { 1508 .enable_reg = 0x80a8, 1509 .enable_mask = BIT(0), 1510 .hw.init = &(const struct clk_init_data) { 1511 .name = "disp_cc_mdss_dptx3_aux_clk", 1512 .parent_hws = (const struct clk_hw*[]) { 1513 &disp_cc_mdss_dptx3_aux_clk_src.clkr.hw, 1514 }, 1515 .num_parents = 1, 1516 .flags = CLK_SET_RATE_PARENT, 1517 .ops = &clk_branch2_ops, 1518 }, 1519 }, 1520 }; 1521 1522 static struct clk_branch disp_cc_mdss_dptx3_crypto_clk = { 1523 .halt_reg = 0x80ac, 1524 .halt_check = BRANCH_HALT, 1525 .clkr = { 1526 .enable_reg = 0x80ac, 1527 .enable_mask = BIT(0), 1528 .hw.init = &(const struct clk_init_data) { 1529 .name = "disp_cc_mdss_dptx3_crypto_clk", 1530 .parent_hws = (const struct clk_hw*[]) { 1531 &disp_cc_mdss_dptx3_link_clk_src.clkr.hw, 1532 }, 1533 .num_parents = 1, 1534 .flags = CLK_SET_RATE_PARENT, 1535 .ops = &clk_branch2_ops, 1536 }, 1537 }, 1538 }; 1539 1540 static struct clk_branch disp_cc_mdss_dptx3_link_clk = { 1541 .halt_reg = 0x80a0, 1542 .halt_check = BRANCH_HALT, 1543 .clkr = { 1544 .enable_reg = 0x80a0, 1545 .enable_mask = BIT(0), 1546 .hw.init = &(const struct clk_init_data) { 1547 .name = "disp_cc_mdss_dptx3_link_clk", 1548 .parent_hws = (const struct clk_hw*[]) { 1549 &disp_cc_mdss_dptx3_link_clk_src.clkr.hw, 1550 }, 1551 .num_parents = 1, 1552 .flags = CLK_SET_RATE_PARENT, 1553 .ops = &clk_branch2_ops, 1554 }, 1555 }, 1556 }; 1557 1558 static struct clk_branch disp_cc_mdss_dptx3_link_intf_clk = { 1559 .halt_reg = 0x80a4, 1560 .halt_check = BRANCH_HALT, 1561 .clkr = { 1562 .enable_reg = 0x80a4, 1563 .enable_mask = BIT(0), 1564 .hw.init = &(const struct clk_init_data) { 1565 .name = "disp_cc_mdss_dptx3_link_intf_clk", 1566 .parent_hws = (const struct clk_hw*[]) { 1567 &disp_cc_mdss_dptx3_link_div_clk_src.clkr.hw, 1568 }, 1569 .num_parents = 1, 1570 .flags = CLK_SET_RATE_PARENT, 1571 .ops = &clk_branch2_ops, 1572 }, 1573 }, 1574 }; 1575 1576 static struct clk_branch disp_cc_mdss_dptx3_pixel0_clk = { 1577 .halt_reg = 0x809c, 1578 .halt_check = BRANCH_HALT, 1579 .clkr = { 1580 .enable_reg = 0x809c, 1581 .enable_mask = BIT(0), 1582 .hw.init = &(const struct clk_init_data) { 1583 .name = "disp_cc_mdss_dptx3_pixel0_clk", 1584 .parent_hws = (const struct clk_hw*[]) { 1585 &disp_cc_mdss_dptx3_pixel0_clk_src.clkr.hw, 1586 }, 1587 .num_parents = 1, 1588 .flags = CLK_SET_RATE_PARENT, 1589 .ops = &clk_branch2_ops, 1590 }, 1591 }, 1592 }; 1593 1594 static struct clk_branch disp_cc_mdss_esc0_clk = { 1595 .halt_reg = 0x8044, 1596 .halt_check = BRANCH_HALT, 1597 .clkr = { 1598 .enable_reg = 0x8044, 1599 .enable_mask = BIT(0), 1600 .hw.init = &(const struct clk_init_data) { 1601 .name = "disp_cc_mdss_esc0_clk", 1602 .parent_hws = (const struct clk_hw*[]) { 1603 &disp_cc_mdss_esc0_clk_src.clkr.hw, 1604 }, 1605 .num_parents = 1, 1606 .flags = CLK_SET_RATE_PARENT, 1607 .ops = &clk_branch2_ops, 1608 }, 1609 }, 1610 }; 1611 1612 static struct clk_branch disp_cc_mdss_esc1_clk = { 1613 .halt_reg = 0x8048, 1614 .halt_check = BRANCH_HALT, 1615 .clkr = { 1616 .enable_reg = 0x8048, 1617 .enable_mask = BIT(0), 1618 .hw.init = &(const struct clk_init_data) { 1619 .name = "disp_cc_mdss_esc1_clk", 1620 .parent_hws = (const struct clk_hw*[]) { 1621 &disp_cc_mdss_esc1_clk_src.clkr.hw, 1622 }, 1623 .num_parents = 1, 1624 .flags = CLK_SET_RATE_PARENT, 1625 .ops = &clk_branch2_ops, 1626 }, 1627 }, 1628 }; 1629 1630 static struct clk_branch disp_cc_mdss_hdmi_ahbm_clk = { 1631 .halt_reg = 0x8378, 1632 .halt_check = BRANCH_HALT, 1633 .clkr = { 1634 .enable_reg = 0x8378, 1635 .enable_mask = BIT(0), 1636 .hw.init = &(const struct clk_init_data) { 1637 .name = "disp_cc_mdss_hdmi_ahbm_clk", 1638 .parent_hws = (const struct clk_hw*[]) { 1639 &disp_cc_mdss_ahb_clk_src.clkr.hw, 1640 }, 1641 .num_parents = 1, 1642 .flags = CLK_SET_RATE_PARENT, 1643 .ops = &clk_branch2_ops, 1644 }, 1645 }, 1646 }; 1647 1648 static struct clk_branch disp_cc_mdss_hdmi_app_clk = { 1649 .halt_reg = 0x8388, 1650 .halt_check = BRANCH_HALT, 1651 .clkr = { 1652 .enable_reg = 0x8388, 1653 .enable_mask = BIT(0), 1654 .hw.init = &(const struct clk_init_data) { 1655 .name = "disp_cc_mdss_hdmi_app_clk", 1656 .parent_hws = (const struct clk_hw*[]) { 1657 &disp_cc_mdss_hdmi_app_clk_src.clkr.hw, 1658 }, 1659 .num_parents = 1, 1660 .flags = CLK_SET_RATE_PARENT, 1661 .ops = &clk_branch2_ops, 1662 }, 1663 }, 1664 }; 1665 1666 static struct clk_branch disp_cc_mdss_hdmi_crypto_clk = { 1667 .halt_reg = 0x8384, 1668 .halt_check = BRANCH_HALT, 1669 .clkr = { 1670 .enable_reg = 0x8384, 1671 .enable_mask = BIT(0), 1672 .hw.init = &(const struct clk_init_data) { 1673 .name = "disp_cc_mdss_hdmi_crypto_clk", 1674 .parent_hws = (const struct clk_hw*[]) { 1675 &disp_cc_mdss_hdmi_pclk_clk_src.clkr.hw, 1676 }, 1677 .num_parents = 1, 1678 .flags = CLK_SET_RATE_PARENT, 1679 .ops = &clk_branch2_ops, 1680 }, 1681 }, 1682 }; 1683 1684 static struct clk_branch disp_cc_mdss_hdmi_intf_clk = { 1685 .halt_reg = 0x8380, 1686 .halt_check = BRANCH_HALT, 1687 .clkr = { 1688 .enable_reg = 0x8380, 1689 .enable_mask = BIT(0), 1690 .hw.init = &(const struct clk_init_data) { 1691 .name = "disp_cc_mdss_hdmi_intf_clk", 1692 .parent_hws = (const struct clk_hw*[]) { 1693 &disp_cc_mdss_hdmi_pclk_div_clk_src.clkr.hw, 1694 }, 1695 .num_parents = 1, 1696 .flags = CLK_SET_RATE_PARENT, 1697 .ops = &clk_branch2_ops, 1698 }, 1699 }, 1700 }; 1701 1702 static struct clk_branch disp_cc_mdss_hdmi_pclk_clk = { 1703 .halt_reg = 0x837c, 1704 .halt_check = BRANCH_HALT, 1705 .clkr = { 1706 .enable_reg = 0x837c, 1707 .enable_mask = BIT(0), 1708 .hw.init = &(const struct clk_init_data) { 1709 .name = "disp_cc_mdss_hdmi_pclk_clk", 1710 .parent_hws = (const struct clk_hw*[]) { 1711 &disp_cc_mdss_hdmi_pclk_clk_src.clkr.hw, 1712 }, 1713 .num_parents = 1, 1714 .flags = CLK_SET_RATE_PARENT, 1715 .ops = &clk_branch2_ops, 1716 }, 1717 }, 1718 }; 1719 1720 static struct clk_branch disp_cc_mdss_mdp1_clk = { 1721 .halt_reg = 0xa004, 1722 .halt_check = BRANCH_HALT, 1723 .clkr = { 1724 .enable_reg = 0xa004, 1725 .enable_mask = BIT(0), 1726 .hw.init = &(const struct clk_init_data) { 1727 .name = "disp_cc_mdss_mdp1_clk", 1728 .parent_hws = (const struct clk_hw*[]) { 1729 &disp_cc_mdss_mdp_clk_src.clkr.hw, 1730 }, 1731 .num_parents = 1, 1732 .flags = CLK_SET_RATE_PARENT, 1733 .ops = &clk_branch2_ops, 1734 }, 1735 }, 1736 }; 1737 1738 static struct clk_branch disp_cc_mdss_mdp_clk = { 1739 .halt_reg = 0x8010, 1740 .halt_check = BRANCH_HALT, 1741 .clkr = { 1742 .enable_reg = 0x8010, 1743 .enable_mask = BIT(0), 1744 .hw.init = &(const struct clk_init_data) { 1745 .name = "disp_cc_mdss_mdp_clk", 1746 .parent_hws = (const struct clk_hw*[]) { 1747 &disp_cc_mdss_mdp_clk_src.clkr.hw, 1748 }, 1749 .num_parents = 1, 1750 .flags = CLK_SET_RATE_PARENT, 1751 .ops = &clk_branch2_aon_ops, 1752 }, 1753 }, 1754 }; 1755 1756 static struct clk_branch disp_cc_mdss_mdp_lut1_clk = { 1757 .halt_reg = 0xa014, 1758 .halt_check = BRANCH_HALT, 1759 .clkr = { 1760 .enable_reg = 0xa014, 1761 .enable_mask = BIT(0), 1762 .hw.init = &(const struct clk_init_data) { 1763 .name = "disp_cc_mdss_mdp_lut1_clk", 1764 .parent_hws = (const struct clk_hw*[]) { 1765 &disp_cc_mdss_mdp_clk_src.clkr.hw, 1766 }, 1767 .num_parents = 1, 1768 .flags = CLK_SET_RATE_PARENT, 1769 .ops = &clk_branch2_ops, 1770 }, 1771 }, 1772 }; 1773 1774 static struct clk_branch disp_cc_mdss_mdp_lut_clk = { 1775 .halt_reg = 0x8020, 1776 .halt_check = BRANCH_HALT_VOTED, 1777 .clkr = { 1778 .enable_reg = 0x8020, 1779 .enable_mask = BIT(0), 1780 .hw.init = &(const struct clk_init_data) { 1781 .name = "disp_cc_mdss_mdp_lut_clk", 1782 .parent_hws = (const struct clk_hw*[]) { 1783 &disp_cc_mdss_mdp_clk_src.clkr.hw, 1784 }, 1785 .num_parents = 1, 1786 .flags = CLK_SET_RATE_PARENT, 1787 .ops = &clk_branch2_ops, 1788 }, 1789 }, 1790 }; 1791 1792 static struct clk_branch disp_cc_mdss_non_gdsc_ahb_clk = { 1793 .halt_reg = 0xc004, 1794 .halt_check = BRANCH_HALT_VOTED, 1795 .clkr = { 1796 .enable_reg = 0xc004, 1797 .enable_mask = BIT(0), 1798 .hw.init = &(const struct clk_init_data) { 1799 .name = "disp_cc_mdss_non_gdsc_ahb_clk", 1800 .parent_hws = (const struct clk_hw*[]) { 1801 &disp_cc_mdss_ahb_clk_src.clkr.hw, 1802 }, 1803 .num_parents = 1, 1804 .flags = CLK_SET_RATE_PARENT, 1805 .ops = &clk_branch2_ops, 1806 }, 1807 }, 1808 }; 1809 1810 static struct clk_branch disp_cc_mdss_pclk0_clk = { 1811 .halt_reg = 0x8004, 1812 .halt_check = BRANCH_HALT, 1813 .clkr = { 1814 .enable_reg = 0x8004, 1815 .enable_mask = BIT(0), 1816 .hw.init = &(const struct clk_init_data) { 1817 .name = "disp_cc_mdss_pclk0_clk", 1818 .parent_hws = (const struct clk_hw*[]) { 1819 &disp_cc_mdss_pclk0_clk_src.clkr.hw, 1820 }, 1821 .num_parents = 1, 1822 .flags = CLK_SET_RATE_PARENT, 1823 .ops = &clk_branch2_ops, 1824 }, 1825 }, 1826 }; 1827 1828 static struct clk_branch disp_cc_mdss_pclk1_clk = { 1829 .halt_reg = 0x8008, 1830 .halt_check = BRANCH_HALT, 1831 .clkr = { 1832 .enable_reg = 0x8008, 1833 .enable_mask = BIT(0), 1834 .hw.init = &(const struct clk_init_data) { 1835 .name = "disp_cc_mdss_pclk1_clk", 1836 .parent_hws = (const struct clk_hw*[]) { 1837 &disp_cc_mdss_pclk1_clk_src.clkr.hw, 1838 }, 1839 .num_parents = 1, 1840 .flags = CLK_SET_RATE_PARENT, 1841 .ops = &clk_branch2_ops, 1842 }, 1843 }, 1844 }; 1845 1846 static struct clk_branch disp_cc_mdss_pclk2_clk = { 1847 .halt_reg = 0x800c, 1848 .halt_check = BRANCH_HALT, 1849 .clkr = { 1850 .enable_reg = 0x800c, 1851 .enable_mask = BIT(0), 1852 .hw.init = &(const struct clk_init_data) { 1853 .name = "disp_cc_mdss_pclk2_clk", 1854 .parent_hws = (const struct clk_hw*[]) { 1855 &disp_cc_mdss_pclk2_clk_src.clkr.hw, 1856 }, 1857 .num_parents = 1, 1858 .flags = CLK_SET_RATE_PARENT, 1859 .ops = &clk_branch2_ops, 1860 }, 1861 }, 1862 }; 1863 1864 static struct clk_branch disp_cc_mdss_vsync1_clk = { 1865 .halt_reg = 0xa024, 1866 .halt_check = BRANCH_HALT, 1867 .clkr = { 1868 .enable_reg = 0xa024, 1869 .enable_mask = BIT(0), 1870 .hw.init = &(const struct clk_init_data) { 1871 .name = "disp_cc_mdss_vsync1_clk", 1872 .parent_hws = (const struct clk_hw*[]) { 1873 &disp_cc_mdss_vsync_clk_src.clkr.hw, 1874 }, 1875 .num_parents = 1, 1876 .flags = CLK_SET_RATE_PARENT, 1877 .ops = &clk_branch2_ops, 1878 }, 1879 }, 1880 }; 1881 1882 static struct clk_branch disp_cc_mdss_vsync_clk = { 1883 .halt_reg = 0x8030, 1884 .halt_check = BRANCH_HALT, 1885 .clkr = { 1886 .enable_reg = 0x8030, 1887 .enable_mask = BIT(0), 1888 .hw.init = &(const struct clk_init_data) { 1889 .name = "disp_cc_mdss_vsync_clk", 1890 .parent_hws = (const struct clk_hw*[]) { 1891 &disp_cc_mdss_vsync_clk_src.clkr.hw, 1892 }, 1893 .num_parents = 1, 1894 .flags = CLK_SET_RATE_PARENT, 1895 .ops = &clk_branch2_ops, 1896 }, 1897 }, 1898 }; 1899 1900 static struct clk_branch disp_cc_osc_clk = { 1901 .halt_reg = 0x80b4, 1902 .halt_check = BRANCH_HALT, 1903 .clkr = { 1904 .enable_reg = 0x80b4, 1905 .enable_mask = BIT(0), 1906 .hw.init = &(const struct clk_init_data) { 1907 .name = "disp_cc_osc_clk", 1908 .parent_hws = (const struct clk_hw*[]) { 1909 &disp_cc_osc_clk_src.clkr.hw, 1910 }, 1911 .num_parents = 1, 1912 .flags = CLK_SET_RATE_PARENT, 1913 .ops = &clk_branch2_ops, 1914 }, 1915 }, 1916 }; 1917 1918 static struct gdsc mdss_gdsc = { 1919 .gdscr = 0x9000, 1920 .en_rest_wait_val = 0x2, 1921 .en_few_wait_val = 0x2, 1922 .clk_dis_wait_val = 0xf, 1923 .pd = { 1924 .name = "mdss_gdsc", 1925 }, 1926 .pwrsts = PWRSTS_OFF_ON, 1927 .flags = POLL_CFG_GDSCR | HW_CTRL | RETAIN_FF_ENABLE, 1928 }; 1929 1930 static struct gdsc mdss_int2_gdsc = { 1931 .gdscr = 0xb000, 1932 .en_rest_wait_val = 0x2, 1933 .en_few_wait_val = 0x2, 1934 .clk_dis_wait_val = 0xf, 1935 .pd = { 1936 .name = "mdss_int2_gdsc", 1937 }, 1938 .pwrsts = PWRSTS_OFF_ON, 1939 .flags = POLL_CFG_GDSCR | HW_CTRL | RETAIN_FF_ENABLE, 1940 }; 1941 1942 static struct clk_regmap *disp_cc_eliza_clocks[] = { 1943 [DISP_CC_ESYNC0_CLK] = &disp_cc_esync0_clk.clkr, 1944 [DISP_CC_ESYNC0_CLK_SRC] = &disp_cc_esync0_clk_src.clkr, 1945 [DISP_CC_ESYNC1_CLK] = &disp_cc_esync1_clk.clkr, 1946 [DISP_CC_ESYNC1_CLK_SRC] = &disp_cc_esync1_clk_src.clkr, 1947 [DISP_CC_MDSS_ACCU_SHIFT_CLK] = &disp_cc_mdss_accu_shift_clk.clkr, 1948 [DISP_CC_MDSS_AHB1_CLK] = &disp_cc_mdss_ahb1_clk.clkr, 1949 [DISP_CC_MDSS_AHB_CLK] = &disp_cc_mdss_ahb_clk.clkr, 1950 [DISP_CC_MDSS_AHB_CLK_SRC] = &disp_cc_mdss_ahb_clk_src.clkr, 1951 [DISP_CC_MDSS_BYTE0_CLK] = &disp_cc_mdss_byte0_clk.clkr, 1952 [DISP_CC_MDSS_BYTE0_CLK_SRC] = &disp_cc_mdss_byte0_clk_src.clkr, 1953 [DISP_CC_MDSS_BYTE0_DIV_CLK_SRC] = &disp_cc_mdss_byte0_div_clk_src.clkr, 1954 [DISP_CC_MDSS_BYTE0_INTF_CLK] = &disp_cc_mdss_byte0_intf_clk.clkr, 1955 [DISP_CC_MDSS_BYTE1_CLK] = &disp_cc_mdss_byte1_clk.clkr, 1956 [DISP_CC_MDSS_BYTE1_CLK_SRC] = &disp_cc_mdss_byte1_clk_src.clkr, 1957 [DISP_CC_MDSS_BYTE1_DIV_CLK_SRC] = &disp_cc_mdss_byte1_div_clk_src.clkr, 1958 [DISP_CC_MDSS_BYTE1_INTF_CLK] = &disp_cc_mdss_byte1_intf_clk.clkr, 1959 [DISP_CC_MDSS_DPTX0_AUX_CLK] = &disp_cc_mdss_dptx0_aux_clk.clkr, 1960 [DISP_CC_MDSS_DPTX0_AUX_CLK_SRC] = &disp_cc_mdss_dptx0_aux_clk_src.clkr, 1961 [DISP_CC_MDSS_DPTX0_CRYPTO_CLK] = &disp_cc_mdss_dptx0_crypto_clk.clkr, 1962 [DISP_CC_MDSS_DPTX0_LINK_CLK] = &disp_cc_mdss_dptx0_link_clk.clkr, 1963 [DISP_CC_MDSS_DPTX0_LINK_CLK_SRC] = &disp_cc_mdss_dptx0_link_clk_src.clkr, 1964 [DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dptx0_link_div_clk_src.clkr, 1965 [DISP_CC_MDSS_DPTX0_LINK_INTF_CLK] = &disp_cc_mdss_dptx0_link_intf_clk.clkr, 1966 [DISP_CC_MDSS_DPTX0_PIXEL0_CLK] = &disp_cc_mdss_dptx0_pixel0_clk.clkr, 1967 [DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC] = &disp_cc_mdss_dptx0_pixel0_clk_src.clkr, 1968 [DISP_CC_MDSS_DPTX0_PIXEL1_CLK] = &disp_cc_mdss_dptx0_pixel1_clk.clkr, 1969 [DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC] = &disp_cc_mdss_dptx0_pixel1_clk_src.clkr, 1970 [DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK] = 1971 &disp_cc_mdss_dptx0_usb_router_link_intf_clk.clkr, 1972 [DISP_CC_MDSS_DPTX1_AUX_CLK] = &disp_cc_mdss_dptx1_aux_clk.clkr, 1973 [DISP_CC_MDSS_DPTX1_AUX_CLK_SRC] = &disp_cc_mdss_dptx1_aux_clk_src.clkr, 1974 [DISP_CC_MDSS_DPTX1_CRYPTO_CLK] = &disp_cc_mdss_dptx1_crypto_clk.clkr, 1975 [DISP_CC_MDSS_DPTX1_LINK_CLK] = &disp_cc_mdss_dptx1_link_clk.clkr, 1976 [DISP_CC_MDSS_DPTX1_LINK_CLK_SRC] = &disp_cc_mdss_dptx1_link_clk_src.clkr, 1977 [DISP_CC_MDSS_DPTX1_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dptx1_link_div_clk_src.clkr, 1978 [DISP_CC_MDSS_DPTX1_LINK_INTF_CLK] = &disp_cc_mdss_dptx1_link_intf_clk.clkr, 1979 [DISP_CC_MDSS_DPTX1_PIXEL0_CLK] = &disp_cc_mdss_dptx1_pixel0_clk.clkr, 1980 [DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC] = &disp_cc_mdss_dptx1_pixel0_clk_src.clkr, 1981 [DISP_CC_MDSS_DPTX1_PIXEL1_CLK] = &disp_cc_mdss_dptx1_pixel1_clk.clkr, 1982 [DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC] = &disp_cc_mdss_dptx1_pixel1_clk_src.clkr, 1983 [DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INTF_CLK] = 1984 &disp_cc_mdss_dptx1_usb_router_link_intf_clk.clkr, 1985 [DISP_CC_MDSS_DPTX2_AUX_CLK] = &disp_cc_mdss_dptx2_aux_clk.clkr, 1986 [DISP_CC_MDSS_DPTX2_AUX_CLK_SRC] = &disp_cc_mdss_dptx2_aux_clk_src.clkr, 1987 [DISP_CC_MDSS_DPTX2_CRYPTO_CLK] = &disp_cc_mdss_dptx2_crypto_clk.clkr, 1988 [DISP_CC_MDSS_DPTX2_LINK_CLK] = &disp_cc_mdss_dptx2_link_clk.clkr, 1989 [DISP_CC_MDSS_DPTX2_LINK_CLK_SRC] = &disp_cc_mdss_dptx2_link_clk_src.clkr, 1990 [DISP_CC_MDSS_DPTX2_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dptx2_link_div_clk_src.clkr, 1991 [DISP_CC_MDSS_DPTX2_LINK_INTF_CLK] = &disp_cc_mdss_dptx2_link_intf_clk.clkr, 1992 [DISP_CC_MDSS_DPTX2_PIXEL0_CLK] = &disp_cc_mdss_dptx2_pixel0_clk.clkr, 1993 [DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC] = &disp_cc_mdss_dptx2_pixel0_clk_src.clkr, 1994 [DISP_CC_MDSS_DPTX2_PIXEL1_CLK] = &disp_cc_mdss_dptx2_pixel1_clk.clkr, 1995 [DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC] = &disp_cc_mdss_dptx2_pixel1_clk_src.clkr, 1996 [DISP_CC_MDSS_DPTX3_AUX_CLK] = &disp_cc_mdss_dptx3_aux_clk.clkr, 1997 [DISP_CC_MDSS_DPTX3_AUX_CLK_SRC] = &disp_cc_mdss_dptx3_aux_clk_src.clkr, 1998 [DISP_CC_MDSS_DPTX3_CRYPTO_CLK] = &disp_cc_mdss_dptx3_crypto_clk.clkr, 1999 [DISP_CC_MDSS_DPTX3_LINK_CLK] = &disp_cc_mdss_dptx3_link_clk.clkr, 2000 [DISP_CC_MDSS_DPTX3_LINK_CLK_SRC] = &disp_cc_mdss_dptx3_link_clk_src.clkr, 2001 [DISP_CC_MDSS_DPTX3_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dptx3_link_div_clk_src.clkr, 2002 [DISP_CC_MDSS_DPTX3_LINK_INTF_CLK] = &disp_cc_mdss_dptx3_link_intf_clk.clkr, 2003 [DISP_CC_MDSS_DPTX3_PIXEL0_CLK] = &disp_cc_mdss_dptx3_pixel0_clk.clkr, 2004 [DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC] = &disp_cc_mdss_dptx3_pixel0_clk_src.clkr, 2005 [DISP_CC_MDSS_ESC0_CLK] = &disp_cc_mdss_esc0_clk.clkr, 2006 [DISP_CC_MDSS_ESC0_CLK_SRC] = &disp_cc_mdss_esc0_clk_src.clkr, 2007 [DISP_CC_MDSS_ESC1_CLK] = &disp_cc_mdss_esc1_clk.clkr, 2008 [DISP_CC_MDSS_ESC1_CLK_SRC] = &disp_cc_mdss_esc1_clk_src.clkr, 2009 [DISP_CC_MDSS_HDMI_AHBM_CLK] = &disp_cc_mdss_hdmi_ahbm_clk.clkr, 2010 [DISP_CC_MDSS_HDMI_APP_CLK] = &disp_cc_mdss_hdmi_app_clk.clkr, 2011 [DISP_CC_MDSS_HDMI_APP_CLK_SRC] = &disp_cc_mdss_hdmi_app_clk_src.clkr, 2012 [DISP_CC_MDSS_HDMI_CRYPTO_CLK] = &disp_cc_mdss_hdmi_crypto_clk.clkr, 2013 [DISP_CC_MDSS_HDMI_INTF_CLK] = &disp_cc_mdss_hdmi_intf_clk.clkr, 2014 [DISP_CC_MDSS_HDMI_PCLK_CLK] = &disp_cc_mdss_hdmi_pclk_clk.clkr, 2015 [DISP_CC_MDSS_HDMI_PCLK_CLK_SRC] = &disp_cc_mdss_hdmi_pclk_clk_src.clkr, 2016 [DISP_CC_MDSS_HDMI_PCLK_DIV_CLK_SRC] = &disp_cc_mdss_hdmi_pclk_div_clk_src.clkr, 2017 [DISP_CC_MDSS_MDP1_CLK] = &disp_cc_mdss_mdp1_clk.clkr, 2018 [DISP_CC_MDSS_MDP_CLK] = &disp_cc_mdss_mdp_clk.clkr, 2019 [DISP_CC_MDSS_MDP_CLK_SRC] = &disp_cc_mdss_mdp_clk_src.clkr, 2020 [DISP_CC_MDSS_MDP_LUT1_CLK] = &disp_cc_mdss_mdp_lut1_clk.clkr, 2021 [DISP_CC_MDSS_MDP_LUT_CLK] = &disp_cc_mdss_mdp_lut_clk.clkr, 2022 [DISP_CC_MDSS_NON_GDSC_AHB_CLK] = &disp_cc_mdss_non_gdsc_ahb_clk.clkr, 2023 [DISP_CC_MDSS_PCLK0_CLK] = &disp_cc_mdss_pclk0_clk.clkr, 2024 [DISP_CC_MDSS_PCLK0_CLK_SRC] = &disp_cc_mdss_pclk0_clk_src.clkr, 2025 [DISP_CC_MDSS_PCLK1_CLK] = &disp_cc_mdss_pclk1_clk.clkr, 2026 [DISP_CC_MDSS_PCLK1_CLK_SRC] = &disp_cc_mdss_pclk1_clk_src.clkr, 2027 [DISP_CC_MDSS_PCLK2_CLK] = &disp_cc_mdss_pclk2_clk.clkr, 2028 [DISP_CC_MDSS_PCLK2_CLK_SRC] = &disp_cc_mdss_pclk2_clk_src.clkr, 2029 [DISP_CC_MDSS_VSYNC1_CLK] = &disp_cc_mdss_vsync1_clk.clkr, 2030 [DISP_CC_MDSS_VSYNC_CLK] = &disp_cc_mdss_vsync_clk.clkr, 2031 [DISP_CC_MDSS_VSYNC_CLK_SRC] = &disp_cc_mdss_vsync_clk_src.clkr, 2032 [DISP_CC_OSC_CLK] = &disp_cc_osc_clk.clkr, 2033 [DISP_CC_OSC_CLK_SRC] = &disp_cc_osc_clk_src.clkr, 2034 [DISP_CC_PLL0] = &disp_cc_pll0.clkr, 2035 [DISP_CC_PLL1] = &disp_cc_pll1.clkr, 2036 [DISP_CC_PLL2] = &disp_cc_pll2.clkr, 2037 [DISP_CC_SLEEP_CLK_SRC] = &disp_cc_sleep_clk_src.clkr, 2038 [DISP_CC_XO_CLK_SRC] = &disp_cc_xo_clk_src.clkr, 2039 }; 2040 2041 static const struct qcom_reset_map disp_cc_eliza_resets[] = { 2042 [DISP_CC_MDSS_CORE_BCR] = { 0x8000 }, 2043 [DISP_CC_MDSS_CORE_INT2_BCR] = { 0xa000 }, 2044 [DISP_CC_MDSS_RSCC_BCR] = { 0xc000 }, 2045 }; 2046 2047 static struct gdsc *disp_cc_eliza_gdscs[] = { 2048 [MDSS_GDSC] = &mdss_gdsc, 2049 [MDSS_INT2_GDSC] = &mdss_int2_gdsc, 2050 }; 2051 2052 static const struct regmap_config disp_cc_eliza_regmap_config = { 2053 .reg_bits = 32, 2054 .reg_stride = 4, 2055 .val_bits = 32, 2056 .max_register = 0xf004, /* 0x10000, 0x10004 and maybe others are for TZ */ 2057 .fast_io = true, 2058 }; 2059 2060 static struct clk_alpha_pll *disp_cc_eliza_plls[] = { 2061 &disp_cc_pll0, 2062 &disp_cc_pll1, 2063 &disp_cc_pll2, 2064 }; 2065 2066 static const u32 disp_cc_eliza_critical_cbcrs[] = { 2067 0xe07c, /* DISP_CC_SLEEP_CLK */ 2068 0xe05c, /* DISP_CC_XO_CLK */ 2069 0xc00c, /* DISP_CC_MDSS_RSCC_AHB_CLK */ 2070 0xc008, /* DISP_CC_MDSS_RSCC_VSYNC_CLK */ 2071 }; 2072 2073 static void clk_eliza_regs_configure(struct device *dev, struct regmap *regmap) 2074 { 2075 /* Enable clock gating for MDP clocks */ 2076 regmap_set_bits(regmap, DISP_CC_MISC_CMD, BIT(4)); 2077 } 2078 2079 static const struct qcom_cc_driver_data disp_cc_eliza_driver_data = { 2080 .alpha_plls = disp_cc_eliza_plls, 2081 .num_alpha_plls = ARRAY_SIZE(disp_cc_eliza_plls), 2082 .clk_cbcrs = disp_cc_eliza_critical_cbcrs, 2083 .num_clk_cbcrs = ARRAY_SIZE(disp_cc_eliza_critical_cbcrs), 2084 .clk_regs_configure = clk_eliza_regs_configure, 2085 }; 2086 2087 static const struct qcom_cc_desc disp_cc_eliza_desc = { 2088 .config = &disp_cc_eliza_regmap_config, 2089 .clks = disp_cc_eliza_clocks, 2090 .num_clks = ARRAY_SIZE(disp_cc_eliza_clocks), 2091 .resets = disp_cc_eliza_resets, 2092 .num_resets = ARRAY_SIZE(disp_cc_eliza_resets), 2093 .gdscs = disp_cc_eliza_gdscs, 2094 .num_gdscs = ARRAY_SIZE(disp_cc_eliza_gdscs), 2095 .use_rpm = true, 2096 .driver_data = &disp_cc_eliza_driver_data, 2097 }; 2098 2099 static const struct of_device_id disp_cc_eliza_match_table[] = { 2100 { .compatible = "qcom,eliza-dispcc" }, 2101 { } 2102 }; 2103 MODULE_DEVICE_TABLE(of, disp_cc_eliza_match_table); 2104 2105 static int disp_cc_eliza_probe(struct platform_device *pdev) 2106 { 2107 return qcom_cc_probe(pdev, &disp_cc_eliza_desc); 2108 } 2109 2110 static struct platform_driver disp_cc_eliza_driver = { 2111 .probe = disp_cc_eliza_probe, 2112 .driver = { 2113 .name = "dispcc-eliza", 2114 .of_match_table = disp_cc_eliza_match_table, 2115 }, 2116 }; 2117 2118 module_platform_driver(disp_cc_eliza_driver); 2119 2120 MODULE_DESCRIPTION("QTI DISPCC Eliza Driver"); 2121 MODULE_LICENSE("GPL"); 2122