1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 4 */ 5 6 #include <linux/clk-provider.h> 7 #include <linux/mod_devicetable.h> 8 #include <linux/module.h> 9 #include <linux/platform_device.h> 10 #include <linux/regmap.h> 11 12 #include <dt-bindings/clock/qcom,x1e80100-camcc.h> 13 14 #include "clk-alpha-pll.h" 15 #include "clk-branch.h" 16 #include "clk-rcg.h" 17 #include "clk-regmap.h" 18 #include "common.h" 19 #include "gdsc.h" 20 #include "reset.h" 21 22 enum { 23 DT_IFACE, 24 DT_BI_TCXO, 25 DT_BI_TCXO_AO, 26 DT_SLEEP_CLK, 27 }; 28 29 enum { 30 P_BI_TCXO, 31 P_BI_TCXO_AO, 32 P_CAM_CC_PLL0_OUT_EVEN, 33 P_CAM_CC_PLL0_OUT_MAIN, 34 P_CAM_CC_PLL0_OUT_ODD, 35 P_CAM_CC_PLL1_OUT_EVEN, 36 P_CAM_CC_PLL2_OUT_EVEN, 37 P_CAM_CC_PLL2_OUT_MAIN, 38 P_CAM_CC_PLL3_OUT_EVEN, 39 P_CAM_CC_PLL6_OUT_EVEN, 40 P_SLEEP_CLK, 41 }; 42 43 static const struct pll_vco lucid_ole_vco[] = { 44 { 249600000, 2300000000, 0 }, 45 }; 46 47 static const struct pll_vco rivian_ole_vco[] = { 48 { 777000000, 1285000000, 0 }, 49 }; 50 51 /* 1200.0 MHz Configuration */ 52 static const struct alpha_pll_config cam_cc_pll0_config = { 53 .l = 0x3e, 54 .alpha = 0x8000, 55 .config_ctl_val = 0x20485699, 56 .config_ctl_hi_val = 0x00182261, 57 .config_ctl_hi1_val = 0x82aa299c, 58 .test_ctl_val = 0x00000000, 59 .test_ctl_hi_val = 0x00000003, 60 .test_ctl_hi1_val = 0x00009000, 61 .test_ctl_hi2_val = 0x00000034, 62 .user_ctl_val = 0x00008400, 63 .user_ctl_hi_val = 0x00000005, 64 }; 65 66 static struct clk_alpha_pll cam_cc_pll0 = { 67 .offset = 0x0, 68 .config = &cam_cc_pll0_config, 69 .vco_table = lucid_ole_vco, 70 .num_vco = ARRAY_SIZE(lucid_ole_vco), 71 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 72 .clkr = { 73 .hw.init = &(const struct clk_init_data) { 74 .name = "cam_cc_pll0", 75 .parent_data = &(const struct clk_parent_data) { 76 .index = DT_BI_TCXO, 77 }, 78 .num_parents = 1, 79 .ops = &clk_alpha_pll_lucid_evo_ops, 80 }, 81 }, 82 }; 83 84 static const struct clk_div_table post_div_table_cam_cc_pll0_out_even[] = { 85 { 0x1, 2 }, 86 { } 87 }; 88 89 static struct clk_alpha_pll_postdiv cam_cc_pll0_out_even = { 90 .offset = 0x0, 91 .post_div_shift = 10, 92 .post_div_table = post_div_table_cam_cc_pll0_out_even, 93 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll0_out_even), 94 .width = 4, 95 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 96 .clkr.hw.init = &(const struct clk_init_data) { 97 .name = "cam_cc_pll0_out_even", 98 .parent_hws = (const struct clk_hw*[]) { 99 &cam_cc_pll0.clkr.hw, 100 }, 101 .num_parents = 1, 102 .flags = CLK_SET_RATE_PARENT, 103 .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, 104 }, 105 }; 106 107 static const struct clk_div_table post_div_table_cam_cc_pll0_out_odd[] = { 108 { 0x2, 3 }, 109 { } 110 }; 111 112 static struct clk_alpha_pll_postdiv cam_cc_pll0_out_odd = { 113 .offset = 0x0, 114 .post_div_shift = 14, 115 .post_div_table = post_div_table_cam_cc_pll0_out_odd, 116 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll0_out_odd), 117 .width = 4, 118 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 119 .clkr.hw.init = &(const struct clk_init_data) { 120 .name = "cam_cc_pll0_out_odd", 121 .parent_hws = (const struct clk_hw*[]) { 122 &cam_cc_pll0.clkr.hw, 123 }, 124 .num_parents = 1, 125 .flags = CLK_SET_RATE_PARENT, 126 .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, 127 }, 128 }; 129 130 /* 728.0 MHz Configuration */ 131 static const struct alpha_pll_config cam_cc_pll1_config = { 132 .l = 0x25, 133 .alpha = 0xeaaa, 134 .config_ctl_val = 0x20485699, 135 .config_ctl_hi_val = 0x00182261, 136 .config_ctl_hi1_val = 0x82aa299c, 137 .test_ctl_val = 0x00000000, 138 .test_ctl_hi_val = 0x00000003, 139 .test_ctl_hi1_val = 0x00009000, 140 .test_ctl_hi2_val = 0x00000034, 141 .user_ctl_val = 0x00000400, 142 .user_ctl_hi_val = 0x00000005, 143 }; 144 145 static struct clk_alpha_pll cam_cc_pll1 = { 146 .offset = 0x1000, 147 .config = &cam_cc_pll1_config, 148 .vco_table = lucid_ole_vco, 149 .num_vco = ARRAY_SIZE(lucid_ole_vco), 150 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 151 .clkr = { 152 .hw.init = &(const struct clk_init_data) { 153 .name = "cam_cc_pll1", 154 .parent_data = &(const struct clk_parent_data) { 155 .index = DT_BI_TCXO, 156 }, 157 .num_parents = 1, 158 .ops = &clk_alpha_pll_lucid_evo_ops, 159 }, 160 }, 161 }; 162 163 static const struct clk_div_table post_div_table_cam_cc_pll1_out_even[] = { 164 { 0x1, 2 }, 165 { } 166 }; 167 168 static struct clk_alpha_pll_postdiv cam_cc_pll1_out_even = { 169 .offset = 0x1000, 170 .post_div_shift = 10, 171 .post_div_table = post_div_table_cam_cc_pll1_out_even, 172 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll1_out_even), 173 .width = 4, 174 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 175 .clkr.hw.init = &(const struct clk_init_data) { 176 .name = "cam_cc_pll1_out_even", 177 .parent_hws = (const struct clk_hw*[]) { 178 &cam_cc_pll1.clkr.hw, 179 }, 180 .num_parents = 1, 181 .flags = CLK_SET_RATE_PARENT, 182 .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, 183 }, 184 }; 185 186 /* 960.0 MHz Configuration */ 187 static const struct alpha_pll_config cam_cc_pll2_config = { 188 .l = 0x32, 189 .alpha = 0x0, 190 .config_ctl_val = 0x10000030, 191 .config_ctl_hi_val = 0x80890263, 192 .config_ctl_hi1_val = 0x00000217, 193 .user_ctl_val = 0x00000000, 194 .user_ctl_hi_val = 0x00100000, 195 }; 196 197 static struct clk_alpha_pll cam_cc_pll2 = { 198 .offset = 0x2000, 199 .config = &cam_cc_pll2_config, 200 .vco_table = rivian_ole_vco, 201 .num_vco = ARRAY_SIZE(rivian_ole_vco), 202 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_RIVIAN_EVO], 203 .clkr = { 204 .hw.init = &(const struct clk_init_data) { 205 .name = "cam_cc_pll2", 206 .parent_data = &(const struct clk_parent_data) { 207 .index = DT_BI_TCXO, 208 }, 209 .num_parents = 1, 210 .ops = &clk_alpha_pll_rivian_evo_ops, 211 }, 212 }, 213 }; 214 215 /* 864.0 MHz Configuration */ 216 static const struct alpha_pll_config cam_cc_pll3_config = { 217 .l = 0x2d, 218 .alpha = 0x0, 219 .config_ctl_val = 0x20485699, 220 .config_ctl_hi_val = 0x00182261, 221 .config_ctl_hi1_val = 0x82aa299c, 222 .test_ctl_val = 0x00000000, 223 .test_ctl_hi_val = 0x00000003, 224 .test_ctl_hi1_val = 0x00009000, 225 .test_ctl_hi2_val = 0x00000034, 226 .user_ctl_val = 0x00000400, 227 .user_ctl_hi_val = 0x00000005, 228 }; 229 230 static struct clk_alpha_pll cam_cc_pll3 = { 231 .offset = 0x3000, 232 .config = &cam_cc_pll3_config, 233 .vco_table = lucid_ole_vco, 234 .num_vco = ARRAY_SIZE(lucid_ole_vco), 235 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 236 .clkr = { 237 .hw.init = &(const struct clk_init_data) { 238 .name = "cam_cc_pll3", 239 .parent_data = &(const struct clk_parent_data) { 240 .index = DT_BI_TCXO, 241 }, 242 .num_parents = 1, 243 .ops = &clk_alpha_pll_lucid_evo_ops, 244 }, 245 }, 246 }; 247 248 static const struct clk_div_table post_div_table_cam_cc_pll3_out_even[] = { 249 { 0x1, 2 }, 250 { } 251 }; 252 253 static struct clk_alpha_pll_postdiv cam_cc_pll3_out_even = { 254 .offset = 0x3000, 255 .post_div_shift = 10, 256 .post_div_table = post_div_table_cam_cc_pll3_out_even, 257 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll3_out_even), 258 .width = 4, 259 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 260 .clkr.hw.init = &(const struct clk_init_data) { 261 .name = "cam_cc_pll3_out_even", 262 .parent_hws = (const struct clk_hw*[]) { 263 &cam_cc_pll3.clkr.hw, 264 }, 265 .num_parents = 1, 266 .flags = CLK_SET_RATE_PARENT, 267 .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, 268 }, 269 }; 270 271 /* 960.0 MHz Configuration */ 272 static const struct alpha_pll_config cam_cc_pll6_config = { 273 .l = 0x32, 274 .alpha = 0x0, 275 .config_ctl_val = 0x20485699, 276 .config_ctl_hi_val = 0x00182261, 277 .config_ctl_hi1_val = 0x82aa299c, 278 .test_ctl_val = 0x00000000, 279 .test_ctl_hi_val = 0x00000003, 280 .test_ctl_hi1_val = 0x00009000, 281 .test_ctl_hi2_val = 0x00000034, 282 .user_ctl_val = 0x00000400, 283 .user_ctl_hi_val = 0x00000005, 284 }; 285 286 static struct clk_alpha_pll cam_cc_pll6 = { 287 .offset = 0x6000, 288 .config = &cam_cc_pll6_config, 289 .vco_table = lucid_ole_vco, 290 .num_vco = ARRAY_SIZE(lucid_ole_vco), 291 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 292 .clkr = { 293 .hw.init = &(const struct clk_init_data) { 294 .name = "cam_cc_pll6", 295 .parent_data = &(const struct clk_parent_data) { 296 .index = DT_BI_TCXO, 297 }, 298 .num_parents = 1, 299 .ops = &clk_alpha_pll_lucid_evo_ops, 300 }, 301 }, 302 }; 303 304 static const struct clk_div_table post_div_table_cam_cc_pll6_out_even[] = { 305 { 0x1, 2 }, 306 { } 307 }; 308 309 static struct clk_alpha_pll_postdiv cam_cc_pll6_out_even = { 310 .offset = 0x6000, 311 .post_div_shift = 10, 312 .post_div_table = post_div_table_cam_cc_pll6_out_even, 313 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll6_out_even), 314 .width = 4, 315 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 316 .clkr.hw.init = &(const struct clk_init_data) { 317 .name = "cam_cc_pll6_out_even", 318 .parent_hws = (const struct clk_hw*[]) { 319 &cam_cc_pll6.clkr.hw, 320 }, 321 .num_parents = 1, 322 .flags = CLK_SET_RATE_PARENT, 323 .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, 324 }, 325 }; 326 327 static const struct parent_map cam_cc_parent_map_0[] = { 328 { P_BI_TCXO, 0 }, 329 { P_CAM_CC_PLL0_OUT_MAIN, 1 }, 330 { P_CAM_CC_PLL0_OUT_EVEN, 2 }, 331 { P_CAM_CC_PLL0_OUT_ODD, 3 }, 332 { P_CAM_CC_PLL6_OUT_EVEN, 5 }, 333 }; 334 335 static const struct clk_parent_data cam_cc_parent_data_0[] = { 336 { .index = DT_BI_TCXO }, 337 { .hw = &cam_cc_pll0.clkr.hw }, 338 { .hw = &cam_cc_pll0_out_even.clkr.hw }, 339 { .hw = &cam_cc_pll0_out_odd.clkr.hw }, 340 { .hw = &cam_cc_pll6_out_even.clkr.hw }, 341 }; 342 343 static const struct parent_map cam_cc_parent_map_1[] = { 344 { P_BI_TCXO, 0 }, 345 { P_CAM_CC_PLL2_OUT_EVEN, 3 }, 346 { P_CAM_CC_PLL2_OUT_MAIN, 5 }, 347 }; 348 349 static const struct clk_parent_data cam_cc_parent_data_1[] = { 350 { .index = DT_BI_TCXO }, 351 { .hw = &cam_cc_pll2.clkr.hw }, 352 { .hw = &cam_cc_pll2.clkr.hw }, 353 }; 354 355 static const struct parent_map cam_cc_parent_map_2[] = { 356 { P_BI_TCXO, 0 }, 357 { P_CAM_CC_PLL3_OUT_EVEN, 6 }, 358 }; 359 360 static const struct clk_parent_data cam_cc_parent_data_2[] = { 361 { .index = DT_BI_TCXO }, 362 { .hw = &cam_cc_pll3_out_even.clkr.hw }, 363 }; 364 365 static const struct parent_map cam_cc_parent_map_3[] = { 366 { P_BI_TCXO, 0 }, 367 { P_CAM_CC_PLL1_OUT_EVEN, 4 }, 368 }; 369 370 static const struct clk_parent_data cam_cc_parent_data_3[] = { 371 { .index = DT_BI_TCXO }, 372 { .hw = &cam_cc_pll1_out_even.clkr.hw }, 373 }; 374 375 static const struct parent_map cam_cc_parent_map_4[] = { 376 { P_SLEEP_CLK, 0 }, 377 }; 378 379 static const struct clk_parent_data cam_cc_parent_data_4[] = { 380 { .index = DT_SLEEP_CLK }, 381 }; 382 383 static const struct parent_map cam_cc_parent_map_5[] = { 384 { P_BI_TCXO, 0 }, 385 }; 386 387 static const struct clk_parent_data cam_cc_parent_data_5[] = { 388 { .index = DT_BI_TCXO }, 389 }; 390 391 static const struct freq_tbl ftbl_cam_cc_bps_clk_src[] = { 392 F(19200000, P_BI_TCXO, 1, 0, 0), 393 F(200000000, P_CAM_CC_PLL0_OUT_ODD, 2, 0, 0), 394 F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), 395 F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0), 396 { } 397 }; 398 399 static struct clk_rcg2 cam_cc_bps_clk_src = { 400 .cmd_rcgr = 0x10278, 401 .mnd_width = 0, 402 .hid_width = 5, 403 .parent_map = cam_cc_parent_map_0, 404 .freq_tbl = ftbl_cam_cc_bps_clk_src, 405 .hw_clk_ctrl = true, 406 .clkr.hw.init = &(const struct clk_init_data) { 407 .name = "cam_cc_bps_clk_src", 408 .parent_data = cam_cc_parent_data_0, 409 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 410 .flags = CLK_SET_RATE_PARENT, 411 .ops = &clk_rcg2_shared_ops, 412 }, 413 }; 414 415 static const struct freq_tbl ftbl_cam_cc_camnoc_axi_rt_clk_src[] = { 416 F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0), 417 F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), 418 { } 419 }; 420 421 static struct clk_rcg2 cam_cc_camnoc_axi_rt_clk_src = { 422 .cmd_rcgr = 0x138f8, 423 .mnd_width = 0, 424 .hid_width = 5, 425 .parent_map = cam_cc_parent_map_0, 426 .freq_tbl = ftbl_cam_cc_camnoc_axi_rt_clk_src, 427 .hw_clk_ctrl = true, 428 .clkr.hw.init = &(const struct clk_init_data) { 429 .name = "cam_cc_camnoc_axi_rt_clk_src", 430 .parent_data = cam_cc_parent_data_0, 431 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 432 .flags = CLK_SET_RATE_PARENT, 433 .ops = &clk_rcg2_shared_ops, 434 }, 435 }; 436 437 static const struct freq_tbl ftbl_cam_cc_cci_0_clk_src[] = { 438 F(19200000, P_BI_TCXO, 1, 0, 0), 439 F(37500000, P_CAM_CC_PLL0_OUT_EVEN, 16, 0, 0), 440 { } 441 }; 442 443 static struct clk_rcg2 cam_cc_cci_0_clk_src = { 444 .cmd_rcgr = 0x1365c, 445 .mnd_width = 8, 446 .hid_width = 5, 447 .parent_map = cam_cc_parent_map_0, 448 .freq_tbl = ftbl_cam_cc_cci_0_clk_src, 449 .hw_clk_ctrl = true, 450 .clkr.hw.init = &(const struct clk_init_data) { 451 .name = "cam_cc_cci_0_clk_src", 452 .parent_data = cam_cc_parent_data_0, 453 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 454 .flags = CLK_SET_RATE_PARENT, 455 .ops = &clk_rcg2_shared_ops, 456 }, 457 }; 458 459 static struct clk_rcg2 cam_cc_cci_1_clk_src = { 460 .cmd_rcgr = 0x1378c, 461 .mnd_width = 8, 462 .hid_width = 5, 463 .parent_map = cam_cc_parent_map_0, 464 .freq_tbl = ftbl_cam_cc_cci_0_clk_src, 465 .hw_clk_ctrl = true, 466 .clkr.hw.init = &(const struct clk_init_data) { 467 .name = "cam_cc_cci_1_clk_src", 468 .parent_data = cam_cc_parent_data_0, 469 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 470 .flags = CLK_SET_RATE_PARENT, 471 .ops = &clk_rcg2_shared_ops, 472 }, 473 }; 474 475 static const struct freq_tbl ftbl_cam_cc_cphy_rx_clk_src[] = { 476 F(19200000, P_BI_TCXO, 1, 0, 0), 477 F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0), 478 F(480000000, P_CAM_CC_PLL0_OUT_MAIN, 2.5, 0, 0), 479 { } 480 }; 481 482 static struct clk_rcg2 cam_cc_cphy_rx_clk_src = { 483 .cmd_rcgr = 0x11164, 484 .mnd_width = 0, 485 .hid_width = 5, 486 .parent_map = cam_cc_parent_map_0, 487 .freq_tbl = ftbl_cam_cc_cphy_rx_clk_src, 488 .hw_clk_ctrl = true, 489 .clkr.hw.init = &(const struct clk_init_data) { 490 .name = "cam_cc_cphy_rx_clk_src", 491 .parent_data = cam_cc_parent_data_0, 492 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 493 .flags = CLK_SET_RATE_PARENT, 494 .ops = &clk_rcg2_shared_ops, 495 }, 496 }; 497 498 static const struct freq_tbl ftbl_cam_cc_csi0phytimer_clk_src[] = { 499 F(19200000, P_BI_TCXO, 1, 0, 0), 500 F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), 501 { } 502 }; 503 504 static struct clk_rcg2 cam_cc_csi0phytimer_clk_src = { 505 .cmd_rcgr = 0x150e0, 506 .mnd_width = 0, 507 .hid_width = 5, 508 .parent_map = cam_cc_parent_map_0, 509 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, 510 .hw_clk_ctrl = true, 511 .clkr.hw.init = &(const struct clk_init_data) { 512 .name = "cam_cc_csi0phytimer_clk_src", 513 .parent_data = cam_cc_parent_data_0, 514 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 515 .flags = CLK_SET_RATE_PARENT, 516 .ops = &clk_rcg2_shared_ops, 517 }, 518 }; 519 520 static struct clk_rcg2 cam_cc_csi1phytimer_clk_src = { 521 .cmd_rcgr = 0x15104, 522 .mnd_width = 0, 523 .hid_width = 5, 524 .parent_map = cam_cc_parent_map_0, 525 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, 526 .hw_clk_ctrl = true, 527 .clkr.hw.init = &(const struct clk_init_data) { 528 .name = "cam_cc_csi1phytimer_clk_src", 529 .parent_data = cam_cc_parent_data_0, 530 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 531 .flags = CLK_SET_RATE_PARENT, 532 .ops = &clk_rcg2_shared_ops, 533 }, 534 }; 535 536 static struct clk_rcg2 cam_cc_csi2phytimer_clk_src = { 537 .cmd_rcgr = 0x15124, 538 .mnd_width = 0, 539 .hid_width = 5, 540 .parent_map = cam_cc_parent_map_0, 541 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, 542 .hw_clk_ctrl = true, 543 .clkr.hw.init = &(const struct clk_init_data) { 544 .name = "cam_cc_csi2phytimer_clk_src", 545 .parent_data = cam_cc_parent_data_0, 546 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 547 .flags = CLK_SET_RATE_PARENT, 548 .ops = &clk_rcg2_shared_ops, 549 }, 550 }; 551 552 static struct clk_rcg2 cam_cc_csi3phytimer_clk_src = { 553 .cmd_rcgr = 0x15258, 554 .mnd_width = 0, 555 .hid_width = 5, 556 .parent_map = cam_cc_parent_map_0, 557 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, 558 .hw_clk_ctrl = true, 559 .clkr.hw.init = &(const struct clk_init_data) { 560 .name = "cam_cc_csi3phytimer_clk_src", 561 .parent_data = cam_cc_parent_data_0, 562 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 563 .flags = CLK_SET_RATE_PARENT, 564 .ops = &clk_rcg2_shared_ops, 565 }, 566 }; 567 568 static struct clk_rcg2 cam_cc_csi4phytimer_clk_src = { 569 .cmd_rcgr = 0x1538c, 570 .mnd_width = 0, 571 .hid_width = 5, 572 .parent_map = cam_cc_parent_map_0, 573 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, 574 .hw_clk_ctrl = true, 575 .clkr.hw.init = &(const struct clk_init_data) { 576 .name = "cam_cc_csi4phytimer_clk_src", 577 .parent_data = cam_cc_parent_data_0, 578 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 579 .flags = CLK_SET_RATE_PARENT, 580 .ops = &clk_rcg2_shared_ops, 581 }, 582 }; 583 584 static struct clk_rcg2 cam_cc_csi5phytimer_clk_src = { 585 .cmd_rcgr = 0x154c0, 586 .mnd_width = 0, 587 .hid_width = 5, 588 .parent_map = cam_cc_parent_map_0, 589 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, 590 .hw_clk_ctrl = true, 591 .clkr.hw.init = &(const struct clk_init_data) { 592 .name = "cam_cc_csi5phytimer_clk_src", 593 .parent_data = cam_cc_parent_data_0, 594 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 595 .flags = CLK_SET_RATE_PARENT, 596 .ops = &clk_rcg2_shared_ops, 597 }, 598 }; 599 600 static const struct freq_tbl ftbl_cam_cc_csid_clk_src[] = { 601 F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0), 602 F(480000000, P_CAM_CC_PLL0_OUT_MAIN, 2.5, 0, 0), 603 { } 604 }; 605 606 static struct clk_rcg2 cam_cc_csid_clk_src = { 607 .cmd_rcgr = 0x138d4, 608 .mnd_width = 0, 609 .hid_width = 5, 610 .parent_map = cam_cc_parent_map_0, 611 .freq_tbl = ftbl_cam_cc_csid_clk_src, 612 .hw_clk_ctrl = true, 613 .clkr.hw.init = &(const struct clk_init_data) { 614 .name = "cam_cc_csid_clk_src", 615 .parent_data = cam_cc_parent_data_0, 616 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 617 .flags = CLK_SET_RATE_PARENT, 618 .ops = &clk_rcg2_shared_ops, 619 }, 620 }; 621 622 static const struct freq_tbl ftbl_cam_cc_fast_ahb_clk_src[] = { 623 F(19200000, P_BI_TCXO, 1, 0, 0), 624 F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0), 625 F(200000000, P_CAM_CC_PLL0_OUT_EVEN, 3, 0, 0), 626 F(300000000, P_CAM_CC_PLL0_OUT_MAIN, 4, 0, 0), 627 F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0), 628 { } 629 }; 630 631 static struct clk_rcg2 cam_cc_fast_ahb_clk_src = { 632 .cmd_rcgr = 0x10018, 633 .mnd_width = 0, 634 .hid_width = 5, 635 .parent_map = cam_cc_parent_map_0, 636 .freq_tbl = ftbl_cam_cc_fast_ahb_clk_src, 637 .hw_clk_ctrl = true, 638 .clkr.hw.init = &(const struct clk_init_data) { 639 .name = "cam_cc_fast_ahb_clk_src", 640 .parent_data = cam_cc_parent_data_0, 641 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 642 .flags = CLK_SET_RATE_PARENT, 643 .ops = &clk_rcg2_shared_ops, 644 }, 645 }; 646 647 static const struct freq_tbl ftbl_cam_cc_icp_clk_src[] = { 648 F(19200000, P_BI_TCXO, 1, 0, 0), 649 F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), 650 F(480000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0), 651 F(600000000, P_CAM_CC_PLL0_OUT_MAIN, 2, 0, 0), 652 { } 653 }; 654 655 static struct clk_rcg2 cam_cc_icp_clk_src = { 656 .cmd_rcgr = 0x13520, 657 .mnd_width = 0, 658 .hid_width = 5, 659 .parent_map = cam_cc_parent_map_0, 660 .freq_tbl = ftbl_cam_cc_icp_clk_src, 661 .hw_clk_ctrl = true, 662 .clkr.hw.init = &(const struct clk_init_data) { 663 .name = "cam_cc_icp_clk_src", 664 .parent_data = cam_cc_parent_data_0, 665 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 666 .flags = CLK_SET_RATE_PARENT, 667 .ops = &clk_rcg2_shared_ops, 668 }, 669 }; 670 671 static const struct freq_tbl ftbl_cam_cc_ife_0_clk_src[] = { 672 F(19200000, P_BI_TCXO, 1, 0, 0), 673 F(432000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), 674 F(594000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), 675 F(675000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), 676 F(727000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), 677 { } 678 }; 679 680 static struct clk_rcg2 cam_cc_ife_0_clk_src = { 681 .cmd_rcgr = 0x11018, 682 .mnd_width = 0, 683 .hid_width = 5, 684 .parent_map = cam_cc_parent_map_2, 685 .freq_tbl = ftbl_cam_cc_ife_0_clk_src, 686 .hw_clk_ctrl = true, 687 .clkr.hw.init = &(const struct clk_init_data) { 688 .name = "cam_cc_ife_0_clk_src", 689 .parent_data = cam_cc_parent_data_2, 690 .num_parents = ARRAY_SIZE(cam_cc_parent_data_2), 691 .flags = CLK_SET_RATE_PARENT, 692 .ops = &clk_rcg2_shared_ops, 693 }, 694 }; 695 696 static const struct freq_tbl ftbl_cam_cc_ife_lite_clk_src[] = { 697 F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), 698 F(480000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0), 699 { } 700 }; 701 702 static struct clk_rcg2 cam_cc_ife_lite_clk_src = { 703 .cmd_rcgr = 0x13000, 704 .mnd_width = 0, 705 .hid_width = 5, 706 .parent_map = cam_cc_parent_map_0, 707 .freq_tbl = ftbl_cam_cc_ife_lite_clk_src, 708 .hw_clk_ctrl = true, 709 .clkr.hw.init = &(const struct clk_init_data) { 710 .name = "cam_cc_ife_lite_clk_src", 711 .parent_data = cam_cc_parent_data_0, 712 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 713 .flags = CLK_SET_RATE_PARENT, 714 .ops = &clk_rcg2_shared_ops, 715 }, 716 }; 717 718 static struct clk_rcg2 cam_cc_ife_lite_csid_clk_src = { 719 .cmd_rcgr = 0x1313c, 720 .mnd_width = 0, 721 .hid_width = 5, 722 .parent_map = cam_cc_parent_map_0, 723 .freq_tbl = ftbl_cam_cc_ife_lite_clk_src, 724 .hw_clk_ctrl = true, 725 .clkr.hw.init = &(const struct clk_init_data) { 726 .name = "cam_cc_ife_lite_csid_clk_src", 727 .parent_data = cam_cc_parent_data_0, 728 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 729 .flags = CLK_SET_RATE_PARENT, 730 .ops = &clk_rcg2_shared_ops, 731 }, 732 }; 733 734 static const struct freq_tbl ftbl_cam_cc_ipe_nps_clk_src[] = { 735 F(364000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), 736 F(500000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), 737 F(600000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), 738 F(700000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), 739 { } 740 }; 741 742 static struct clk_rcg2 cam_cc_ipe_nps_clk_src = { 743 .cmd_rcgr = 0x103cc, 744 .mnd_width = 0, 745 .hid_width = 5, 746 .parent_map = cam_cc_parent_map_3, 747 .freq_tbl = ftbl_cam_cc_ipe_nps_clk_src, 748 .hw_clk_ctrl = true, 749 .clkr.hw.init = &(const struct clk_init_data) { 750 .name = "cam_cc_ipe_nps_clk_src", 751 .parent_data = cam_cc_parent_data_3, 752 .num_parents = ARRAY_SIZE(cam_cc_parent_data_3), 753 .flags = CLK_SET_RATE_PARENT, 754 .ops = &clk_rcg2_shared_ops, 755 }, 756 }; 757 758 static const struct freq_tbl ftbl_cam_cc_jpeg_clk_src[] = { 759 F(19200000, P_BI_TCXO, 1, 0, 0), 760 F(200000000, P_CAM_CC_PLL0_OUT_ODD, 2, 0, 0), 761 F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), 762 F(480000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0), 763 F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0), 764 { } 765 }; 766 767 static struct clk_rcg2 cam_cc_jpeg_clk_src = { 768 .cmd_rcgr = 0x133dc, 769 .mnd_width = 0, 770 .hid_width = 5, 771 .parent_map = cam_cc_parent_map_0, 772 .freq_tbl = ftbl_cam_cc_jpeg_clk_src, 773 .hw_clk_ctrl = true, 774 .clkr.hw.init = &(const struct clk_init_data) { 775 .name = "cam_cc_jpeg_clk_src", 776 .parent_data = cam_cc_parent_data_0, 777 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 778 .flags = CLK_SET_RATE_PARENT, 779 .ops = &clk_rcg2_shared_ops, 780 }, 781 }; 782 783 static const struct freq_tbl ftbl_cam_cc_mclk0_clk_src[] = { 784 F(19200000, P_BI_TCXO, 1, 0, 0), 785 F(24000000, P_CAM_CC_PLL2_OUT_MAIN, 10, 1, 4), 786 F(68571429, P_CAM_CC_PLL2_OUT_MAIN, 14, 0, 0), 787 { } 788 }; 789 790 static struct clk_rcg2 cam_cc_mclk0_clk_src = { 791 .cmd_rcgr = 0x15000, 792 .mnd_width = 8, 793 .hid_width = 5, 794 .parent_map = cam_cc_parent_map_1, 795 .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 796 .hw_clk_ctrl = true, 797 .clkr.hw.init = &(const struct clk_init_data) { 798 .name = "cam_cc_mclk0_clk_src", 799 .parent_data = cam_cc_parent_data_1, 800 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 801 .flags = CLK_SET_RATE_PARENT, 802 .ops = &clk_rcg2_shared_ops, 803 }, 804 }; 805 806 static struct clk_rcg2 cam_cc_mclk1_clk_src = { 807 .cmd_rcgr = 0x1501c, 808 .mnd_width = 8, 809 .hid_width = 5, 810 .parent_map = cam_cc_parent_map_1, 811 .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 812 .hw_clk_ctrl = true, 813 .clkr.hw.init = &(const struct clk_init_data) { 814 .name = "cam_cc_mclk1_clk_src", 815 .parent_data = cam_cc_parent_data_1, 816 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 817 .flags = CLK_SET_RATE_PARENT, 818 .ops = &clk_rcg2_shared_ops, 819 }, 820 }; 821 822 static struct clk_rcg2 cam_cc_mclk2_clk_src = { 823 .cmd_rcgr = 0x15038, 824 .mnd_width = 8, 825 .hid_width = 5, 826 .parent_map = cam_cc_parent_map_1, 827 .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 828 .hw_clk_ctrl = true, 829 .clkr.hw.init = &(const struct clk_init_data) { 830 .name = "cam_cc_mclk2_clk_src", 831 .parent_data = cam_cc_parent_data_1, 832 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 833 .flags = CLK_SET_RATE_PARENT, 834 .ops = &clk_rcg2_shared_ops, 835 }, 836 }; 837 838 static struct clk_rcg2 cam_cc_mclk3_clk_src = { 839 .cmd_rcgr = 0x15054, 840 .mnd_width = 8, 841 .hid_width = 5, 842 .parent_map = cam_cc_parent_map_1, 843 .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 844 .hw_clk_ctrl = true, 845 .clkr.hw.init = &(const struct clk_init_data) { 846 .name = "cam_cc_mclk3_clk_src", 847 .parent_data = cam_cc_parent_data_1, 848 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 849 .flags = CLK_SET_RATE_PARENT, 850 .ops = &clk_rcg2_shared_ops, 851 }, 852 }; 853 854 static struct clk_rcg2 cam_cc_mclk4_clk_src = { 855 .cmd_rcgr = 0x15070, 856 .mnd_width = 8, 857 .hid_width = 5, 858 .parent_map = cam_cc_parent_map_1, 859 .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 860 .hw_clk_ctrl = true, 861 .clkr.hw.init = &(const struct clk_init_data) { 862 .name = "cam_cc_mclk4_clk_src", 863 .parent_data = cam_cc_parent_data_1, 864 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 865 .flags = CLK_SET_RATE_PARENT, 866 .ops = &clk_rcg2_shared_ops, 867 }, 868 }; 869 870 static struct clk_rcg2 cam_cc_mclk5_clk_src = { 871 .cmd_rcgr = 0x1508c, 872 .mnd_width = 8, 873 .hid_width = 5, 874 .parent_map = cam_cc_parent_map_1, 875 .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 876 .hw_clk_ctrl = true, 877 .clkr.hw.init = &(const struct clk_init_data) { 878 .name = "cam_cc_mclk5_clk_src", 879 .parent_data = cam_cc_parent_data_1, 880 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 881 .flags = CLK_SET_RATE_PARENT, 882 .ops = &clk_rcg2_shared_ops, 883 }, 884 }; 885 886 static struct clk_rcg2 cam_cc_mclk6_clk_src = { 887 .cmd_rcgr = 0x150a8, 888 .mnd_width = 8, 889 .hid_width = 5, 890 .parent_map = cam_cc_parent_map_1, 891 .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 892 .hw_clk_ctrl = true, 893 .clkr.hw.init = &(const struct clk_init_data) { 894 .name = "cam_cc_mclk6_clk_src", 895 .parent_data = cam_cc_parent_data_1, 896 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 897 .flags = CLK_SET_RATE_PARENT, 898 .ops = &clk_rcg2_shared_ops, 899 }, 900 }; 901 902 static struct clk_rcg2 cam_cc_mclk7_clk_src = { 903 .cmd_rcgr = 0x150c4, 904 .mnd_width = 8, 905 .hid_width = 5, 906 .parent_map = cam_cc_parent_map_1, 907 .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 908 .hw_clk_ctrl = true, 909 .clkr.hw.init = &(const struct clk_init_data) { 910 .name = "cam_cc_mclk7_clk_src", 911 .parent_data = cam_cc_parent_data_1, 912 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 913 .flags = CLK_SET_RATE_PARENT, 914 .ops = &clk_rcg2_shared_ops, 915 }, 916 }; 917 918 static const struct freq_tbl ftbl_cam_cc_qdss_debug_clk_src[] = { 919 F(19200000, P_BI_TCXO, 1, 0, 0), 920 F(75000000, P_CAM_CC_PLL0_OUT_EVEN, 8, 0, 0), 921 F(150000000, P_CAM_CC_PLL0_OUT_EVEN, 4, 0, 0), 922 F(300000000, P_CAM_CC_PLL0_OUT_MAIN, 4, 0, 0), 923 { } 924 }; 925 926 static struct clk_rcg2 cam_cc_qdss_debug_clk_src = { 927 .cmd_rcgr = 0x13938, 928 .mnd_width = 0, 929 .hid_width = 5, 930 .parent_map = cam_cc_parent_map_0, 931 .freq_tbl = ftbl_cam_cc_qdss_debug_clk_src, 932 .hw_clk_ctrl = true, 933 .clkr.hw.init = &(const struct clk_init_data) { 934 .name = "cam_cc_qdss_debug_clk_src", 935 .parent_data = cam_cc_parent_data_0, 936 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 937 .flags = CLK_SET_RATE_PARENT, 938 .ops = &clk_rcg2_shared_ops, 939 }, 940 }; 941 942 static const struct freq_tbl ftbl_cam_cc_sleep_clk_src[] = { 943 F(32000, P_SLEEP_CLK, 1, 0, 0), 944 { } 945 }; 946 947 static struct clk_rcg2 cam_cc_sleep_clk_src = { 948 .cmd_rcgr = 0x13aa0, 949 .mnd_width = 0, 950 .hid_width = 5, 951 .parent_map = cam_cc_parent_map_4, 952 .freq_tbl = ftbl_cam_cc_sleep_clk_src, 953 .clkr.hw.init = &(const struct clk_init_data) { 954 .name = "cam_cc_sleep_clk_src", 955 .parent_data = cam_cc_parent_data_4, 956 .num_parents = ARRAY_SIZE(cam_cc_parent_data_4), 957 .flags = CLK_SET_RATE_PARENT, 958 .ops = &clk_rcg2_shared_ops, 959 }, 960 }; 961 962 static const struct freq_tbl ftbl_cam_cc_slow_ahb_clk_src[] = { 963 F(19200000, P_BI_TCXO, 1, 0, 0), 964 F(80000000, P_CAM_CC_PLL0_OUT_EVEN, 7.5, 0, 0), 965 { } 966 }; 967 968 static struct clk_rcg2 cam_cc_slow_ahb_clk_src = { 969 .cmd_rcgr = 0x10148, 970 .mnd_width = 8, 971 .hid_width = 5, 972 .parent_map = cam_cc_parent_map_0, 973 .freq_tbl = ftbl_cam_cc_slow_ahb_clk_src, 974 .hw_clk_ctrl = true, 975 .clkr.hw.init = &(const struct clk_init_data) { 976 .name = "cam_cc_slow_ahb_clk_src", 977 .parent_data = cam_cc_parent_data_0, 978 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 979 .flags = CLK_SET_RATE_PARENT, 980 .ops = &clk_rcg2_shared_ops, 981 }, 982 }; 983 984 static const struct freq_tbl ftbl_cam_cc_xo_clk_src[] = { 985 F(19200000, P_BI_TCXO, 1, 0, 0), 986 { } 987 }; 988 989 static struct clk_rcg2 cam_cc_xo_clk_src = { 990 .cmd_rcgr = 0x13a84, 991 .mnd_width = 0, 992 .hid_width = 5, 993 .parent_map = cam_cc_parent_map_5, 994 .freq_tbl = ftbl_cam_cc_xo_clk_src, 995 .hw_clk_ctrl = true, 996 .clkr.hw.init = &(const struct clk_init_data) { 997 .name = "cam_cc_xo_clk_src", 998 .parent_data = cam_cc_parent_data_5, 999 .num_parents = ARRAY_SIZE(cam_cc_parent_data_5), 1000 .flags = CLK_SET_RATE_PARENT, 1001 .ops = &clk_rcg2_shared_ops, 1002 }, 1003 }; 1004 1005 static struct clk_branch cam_cc_bps_ahb_clk = { 1006 .halt_reg = 0x10274, 1007 .halt_check = BRANCH_HALT, 1008 .clkr = { 1009 .enable_reg = 0x10274, 1010 .enable_mask = BIT(0), 1011 .hw.init = &(const struct clk_init_data) { 1012 .name = "cam_cc_bps_ahb_clk", 1013 .parent_hws = (const struct clk_hw*[]) { 1014 &cam_cc_slow_ahb_clk_src.clkr.hw, 1015 }, 1016 .num_parents = 1, 1017 .flags = CLK_SET_RATE_PARENT, 1018 .ops = &clk_branch2_ops, 1019 }, 1020 }, 1021 }; 1022 1023 static struct clk_branch cam_cc_bps_clk = { 1024 .halt_reg = 0x103a4, 1025 .halt_check = BRANCH_HALT, 1026 .clkr = { 1027 .enable_reg = 0x103a4, 1028 .enable_mask = BIT(0), 1029 .hw.init = &(const struct clk_init_data) { 1030 .name = "cam_cc_bps_clk", 1031 .parent_hws = (const struct clk_hw*[]) { 1032 &cam_cc_bps_clk_src.clkr.hw, 1033 }, 1034 .num_parents = 1, 1035 .flags = CLK_SET_RATE_PARENT, 1036 .ops = &clk_branch2_ops, 1037 }, 1038 }, 1039 }; 1040 1041 static struct clk_branch cam_cc_bps_fast_ahb_clk = { 1042 .halt_reg = 0x10144, 1043 .halt_check = BRANCH_HALT, 1044 .clkr = { 1045 .enable_reg = 0x10144, 1046 .enable_mask = BIT(0), 1047 .hw.init = &(const struct clk_init_data) { 1048 .name = "cam_cc_bps_fast_ahb_clk", 1049 .parent_hws = (const struct clk_hw*[]) { 1050 &cam_cc_fast_ahb_clk_src.clkr.hw, 1051 }, 1052 .num_parents = 1, 1053 .flags = CLK_SET_RATE_PARENT, 1054 .ops = &clk_branch2_ops, 1055 }, 1056 }, 1057 }; 1058 1059 static struct clk_branch cam_cc_camnoc_axi_nrt_clk = { 1060 .halt_reg = 0x13920, 1061 .halt_check = BRANCH_HALT_VOTED, 1062 .hwcg_reg = 0x13920, 1063 .hwcg_bit = 1, 1064 .clkr = { 1065 .enable_reg = 0x13920, 1066 .enable_mask = BIT(0), 1067 .hw.init = &(const struct clk_init_data) { 1068 .name = "cam_cc_camnoc_axi_nrt_clk", 1069 .parent_hws = (const struct clk_hw*[]) { 1070 &cam_cc_camnoc_axi_rt_clk_src.clkr.hw, 1071 }, 1072 .num_parents = 1, 1073 .flags = CLK_SET_RATE_PARENT, 1074 .ops = &clk_branch2_ops, 1075 }, 1076 }, 1077 }; 1078 1079 static struct clk_branch cam_cc_camnoc_axi_rt_clk = { 1080 .halt_reg = 0x13910, 1081 .halt_check = BRANCH_HALT, 1082 .clkr = { 1083 .enable_reg = 0x13910, 1084 .enable_mask = BIT(0), 1085 .hw.init = &(const struct clk_init_data) { 1086 .name = "cam_cc_camnoc_axi_rt_clk", 1087 .parent_hws = (const struct clk_hw*[]) { 1088 &cam_cc_camnoc_axi_rt_clk_src.clkr.hw, 1089 }, 1090 .num_parents = 1, 1091 .flags = CLK_SET_RATE_PARENT, 1092 .ops = &clk_branch2_ops, 1093 }, 1094 }, 1095 }; 1096 1097 static struct clk_branch cam_cc_camnoc_dcd_xo_clk = { 1098 .halt_reg = 0x1392c, 1099 .halt_check = BRANCH_HALT, 1100 .clkr = { 1101 .enable_reg = 0x1392c, 1102 .enable_mask = BIT(0), 1103 .hw.init = &(const struct clk_init_data) { 1104 .name = "cam_cc_camnoc_dcd_xo_clk", 1105 .parent_hws = (const struct clk_hw*[]) { 1106 &cam_cc_xo_clk_src.clkr.hw, 1107 }, 1108 .num_parents = 1, 1109 .flags = CLK_SET_RATE_PARENT, 1110 .ops = &clk_branch2_ops, 1111 }, 1112 }, 1113 }; 1114 1115 static struct clk_branch cam_cc_camnoc_xo_clk = { 1116 .halt_reg = 0x13930, 1117 .halt_check = BRANCH_HALT, 1118 .clkr = { 1119 .enable_reg = 0x13930, 1120 .enable_mask = BIT(0), 1121 .hw.init = &(const struct clk_init_data) { 1122 .name = "cam_cc_camnoc_xo_clk", 1123 .parent_hws = (const struct clk_hw*[]) { 1124 &cam_cc_xo_clk_src.clkr.hw, 1125 }, 1126 .num_parents = 1, 1127 .flags = CLK_SET_RATE_PARENT, 1128 .ops = &clk_branch2_ops, 1129 }, 1130 }, 1131 }; 1132 1133 static struct clk_branch cam_cc_cci_0_clk = { 1134 .halt_reg = 0x13788, 1135 .halt_check = BRANCH_HALT, 1136 .clkr = { 1137 .enable_reg = 0x13788, 1138 .enable_mask = BIT(0), 1139 .hw.init = &(const struct clk_init_data) { 1140 .name = "cam_cc_cci_0_clk", 1141 .parent_hws = (const struct clk_hw*[]) { 1142 &cam_cc_cci_0_clk_src.clkr.hw, 1143 }, 1144 .num_parents = 1, 1145 .flags = CLK_SET_RATE_PARENT, 1146 .ops = &clk_branch2_ops, 1147 }, 1148 }, 1149 }; 1150 1151 static struct clk_branch cam_cc_cci_1_clk = { 1152 .halt_reg = 0x138b8, 1153 .halt_check = BRANCH_HALT, 1154 .clkr = { 1155 .enable_reg = 0x138b8, 1156 .enable_mask = BIT(0), 1157 .hw.init = &(const struct clk_init_data) { 1158 .name = "cam_cc_cci_1_clk", 1159 .parent_hws = (const struct clk_hw*[]) { 1160 &cam_cc_cci_1_clk_src.clkr.hw, 1161 }, 1162 .num_parents = 1, 1163 .flags = CLK_SET_RATE_PARENT, 1164 .ops = &clk_branch2_ops, 1165 }, 1166 }, 1167 }; 1168 1169 static struct clk_branch cam_cc_core_ahb_clk = { 1170 .halt_reg = 0x13a80, 1171 .halt_check = BRANCH_HALT_VOTED, 1172 .clkr = { 1173 .enable_reg = 0x13a80, 1174 .enable_mask = BIT(0), 1175 .hw.init = &(const struct clk_init_data) { 1176 .name = "cam_cc_core_ahb_clk", 1177 .parent_hws = (const struct clk_hw*[]) { 1178 &cam_cc_slow_ahb_clk_src.clkr.hw, 1179 }, 1180 .num_parents = 1, 1181 .flags = CLK_SET_RATE_PARENT, 1182 .ops = &clk_branch2_ops, 1183 }, 1184 }, 1185 }; 1186 1187 static struct clk_branch cam_cc_cpas_ahb_clk = { 1188 .halt_reg = 0x138bc, 1189 .halt_check = BRANCH_HALT, 1190 .clkr = { 1191 .enable_reg = 0x138bc, 1192 .enable_mask = BIT(0), 1193 .hw.init = &(const struct clk_init_data) { 1194 .name = "cam_cc_cpas_ahb_clk", 1195 .parent_hws = (const struct clk_hw*[]) { 1196 &cam_cc_slow_ahb_clk_src.clkr.hw, 1197 }, 1198 .num_parents = 1, 1199 .flags = CLK_SET_RATE_PARENT, 1200 .ops = &clk_branch2_ops, 1201 }, 1202 }, 1203 }; 1204 1205 static struct clk_branch cam_cc_cpas_bps_clk = { 1206 .halt_reg = 0x103b0, 1207 .halt_check = BRANCH_HALT, 1208 .clkr = { 1209 .enable_reg = 0x103b0, 1210 .enable_mask = BIT(0), 1211 .hw.init = &(const struct clk_init_data) { 1212 .name = "cam_cc_cpas_bps_clk", 1213 .parent_hws = (const struct clk_hw*[]) { 1214 &cam_cc_bps_clk_src.clkr.hw, 1215 }, 1216 .num_parents = 1, 1217 .flags = CLK_SET_RATE_PARENT, 1218 .ops = &clk_branch2_ops, 1219 }, 1220 }, 1221 }; 1222 1223 static struct clk_branch cam_cc_cpas_fast_ahb_clk = { 1224 .halt_reg = 0x138c8, 1225 .halt_check = BRANCH_HALT, 1226 .clkr = { 1227 .enable_reg = 0x138c8, 1228 .enable_mask = BIT(0), 1229 .hw.init = &(const struct clk_init_data) { 1230 .name = "cam_cc_cpas_fast_ahb_clk", 1231 .parent_hws = (const struct clk_hw*[]) { 1232 &cam_cc_fast_ahb_clk_src.clkr.hw, 1233 }, 1234 .num_parents = 1, 1235 .flags = CLK_SET_RATE_PARENT, 1236 .ops = &clk_branch2_ops, 1237 }, 1238 }, 1239 }; 1240 1241 static struct clk_branch cam_cc_cpas_ife_0_clk = { 1242 .halt_reg = 0x11150, 1243 .halt_check = BRANCH_HALT, 1244 .clkr = { 1245 .enable_reg = 0x11150, 1246 .enable_mask = BIT(0), 1247 .hw.init = &(const struct clk_init_data) { 1248 .name = "cam_cc_cpas_ife_0_clk", 1249 .parent_hws = (const struct clk_hw*[]) { 1250 &cam_cc_ife_0_clk_src.clkr.hw, 1251 }, 1252 .num_parents = 1, 1253 .flags = CLK_SET_RATE_PARENT, 1254 .ops = &clk_branch2_ops, 1255 }, 1256 }, 1257 }; 1258 1259 static struct clk_branch cam_cc_cpas_ife_lite_clk = { 1260 .halt_reg = 0x13138, 1261 .halt_check = BRANCH_HALT, 1262 .clkr = { 1263 .enable_reg = 0x13138, 1264 .enable_mask = BIT(0), 1265 .hw.init = &(const struct clk_init_data) { 1266 .name = "cam_cc_cpas_ife_lite_clk", 1267 .parent_hws = (const struct clk_hw*[]) { 1268 &cam_cc_ife_lite_clk_src.clkr.hw, 1269 }, 1270 .num_parents = 1, 1271 .flags = CLK_SET_RATE_PARENT, 1272 .ops = &clk_branch2_ops, 1273 }, 1274 }, 1275 }; 1276 1277 static struct clk_branch cam_cc_cpas_ipe_nps_clk = { 1278 .halt_reg = 0x10504, 1279 .halt_check = BRANCH_HALT, 1280 .clkr = { 1281 .enable_reg = 0x10504, 1282 .enable_mask = BIT(0), 1283 .hw.init = &(const struct clk_init_data) { 1284 .name = "cam_cc_cpas_ipe_nps_clk", 1285 .parent_hws = (const struct clk_hw*[]) { 1286 &cam_cc_ipe_nps_clk_src.clkr.hw, 1287 }, 1288 .num_parents = 1, 1289 .flags = CLK_SET_RATE_PARENT, 1290 .ops = &clk_branch2_ops, 1291 }, 1292 }, 1293 }; 1294 1295 static struct clk_branch cam_cc_csi0phytimer_clk = { 1296 .halt_reg = 0x150f8, 1297 .halt_check = BRANCH_HALT, 1298 .clkr = { 1299 .enable_reg = 0x150f8, 1300 .enable_mask = BIT(0), 1301 .hw.init = &(const struct clk_init_data) { 1302 .name = "cam_cc_csi0phytimer_clk", 1303 .parent_hws = (const struct clk_hw*[]) { 1304 &cam_cc_csi0phytimer_clk_src.clkr.hw, 1305 }, 1306 .num_parents = 1, 1307 .flags = CLK_SET_RATE_PARENT, 1308 .ops = &clk_branch2_ops, 1309 }, 1310 }, 1311 }; 1312 1313 static struct clk_branch cam_cc_csi1phytimer_clk = { 1314 .halt_reg = 0x1511c, 1315 .halt_check = BRANCH_HALT, 1316 .clkr = { 1317 .enable_reg = 0x1511c, 1318 .enable_mask = BIT(0), 1319 .hw.init = &(const struct clk_init_data) { 1320 .name = "cam_cc_csi1phytimer_clk", 1321 .parent_hws = (const struct clk_hw*[]) { 1322 &cam_cc_csi1phytimer_clk_src.clkr.hw, 1323 }, 1324 .num_parents = 1, 1325 .flags = CLK_SET_RATE_PARENT, 1326 .ops = &clk_branch2_ops, 1327 }, 1328 }, 1329 }; 1330 1331 static struct clk_branch cam_cc_csi2phytimer_clk = { 1332 .halt_reg = 0x15250, 1333 .halt_check = BRANCH_HALT, 1334 .clkr = { 1335 .enable_reg = 0x15250, 1336 .enable_mask = BIT(0), 1337 .hw.init = &(const struct clk_init_data) { 1338 .name = "cam_cc_csi2phytimer_clk", 1339 .parent_hws = (const struct clk_hw*[]) { 1340 &cam_cc_csi2phytimer_clk_src.clkr.hw, 1341 }, 1342 .num_parents = 1, 1343 .flags = CLK_SET_RATE_PARENT, 1344 .ops = &clk_branch2_ops, 1345 }, 1346 }, 1347 }; 1348 1349 static struct clk_branch cam_cc_csi3phytimer_clk = { 1350 .halt_reg = 0x15384, 1351 .halt_check = BRANCH_HALT, 1352 .clkr = { 1353 .enable_reg = 0x15384, 1354 .enable_mask = BIT(0), 1355 .hw.init = &(const struct clk_init_data) { 1356 .name = "cam_cc_csi3phytimer_clk", 1357 .parent_hws = (const struct clk_hw*[]) { 1358 &cam_cc_csi3phytimer_clk_src.clkr.hw, 1359 }, 1360 .num_parents = 1, 1361 .flags = CLK_SET_RATE_PARENT, 1362 .ops = &clk_branch2_ops, 1363 }, 1364 }, 1365 }; 1366 1367 static struct clk_branch cam_cc_csi4phytimer_clk = { 1368 .halt_reg = 0x154b8, 1369 .halt_check = BRANCH_HALT, 1370 .clkr = { 1371 .enable_reg = 0x154b8, 1372 .enable_mask = BIT(0), 1373 .hw.init = &(const struct clk_init_data) { 1374 .name = "cam_cc_csi4phytimer_clk", 1375 .parent_hws = (const struct clk_hw*[]) { 1376 &cam_cc_csi4phytimer_clk_src.clkr.hw, 1377 }, 1378 .num_parents = 1, 1379 .flags = CLK_SET_RATE_PARENT, 1380 .ops = &clk_branch2_ops, 1381 }, 1382 }, 1383 }; 1384 1385 static struct clk_branch cam_cc_csi5phytimer_clk = { 1386 .halt_reg = 0x155ec, 1387 .halt_check = BRANCH_HALT, 1388 .clkr = { 1389 .enable_reg = 0x155ec, 1390 .enable_mask = BIT(0), 1391 .hw.init = &(const struct clk_init_data) { 1392 .name = "cam_cc_csi5phytimer_clk", 1393 .parent_hws = (const struct clk_hw*[]) { 1394 &cam_cc_csi5phytimer_clk_src.clkr.hw, 1395 }, 1396 .num_parents = 1, 1397 .flags = CLK_SET_RATE_PARENT, 1398 .ops = &clk_branch2_ops, 1399 }, 1400 }, 1401 }; 1402 1403 static struct clk_branch cam_cc_csid_clk = { 1404 .halt_reg = 0x138ec, 1405 .halt_check = BRANCH_HALT, 1406 .clkr = { 1407 .enable_reg = 0x138ec, 1408 .enable_mask = BIT(0), 1409 .hw.init = &(const struct clk_init_data) { 1410 .name = "cam_cc_csid_clk", 1411 .parent_hws = (const struct clk_hw*[]) { 1412 &cam_cc_csid_clk_src.clkr.hw, 1413 }, 1414 .num_parents = 1, 1415 .flags = CLK_SET_RATE_PARENT, 1416 .ops = &clk_branch2_ops, 1417 }, 1418 }, 1419 }; 1420 1421 static struct clk_branch cam_cc_csid_csiphy_rx_clk = { 1422 .halt_reg = 0x15100, 1423 .halt_check = BRANCH_HALT, 1424 .clkr = { 1425 .enable_reg = 0x15100, 1426 .enable_mask = BIT(0), 1427 .hw.init = &(const struct clk_init_data) { 1428 .name = "cam_cc_csid_csiphy_rx_clk", 1429 .parent_hws = (const struct clk_hw*[]) { 1430 &cam_cc_cphy_rx_clk_src.clkr.hw, 1431 }, 1432 .num_parents = 1, 1433 .flags = CLK_SET_RATE_PARENT, 1434 .ops = &clk_branch2_ops, 1435 }, 1436 }, 1437 }; 1438 1439 static struct clk_branch cam_cc_csiphy0_clk = { 1440 .halt_reg = 0x150fc, 1441 .halt_check = BRANCH_HALT, 1442 .clkr = { 1443 .enable_reg = 0x150fc, 1444 .enable_mask = BIT(0), 1445 .hw.init = &(const struct clk_init_data) { 1446 .name = "cam_cc_csiphy0_clk", 1447 .parent_hws = (const struct clk_hw*[]) { 1448 &cam_cc_cphy_rx_clk_src.clkr.hw, 1449 }, 1450 .num_parents = 1, 1451 .flags = CLK_SET_RATE_PARENT, 1452 .ops = &clk_branch2_ops, 1453 }, 1454 }, 1455 }; 1456 1457 static struct clk_branch cam_cc_csiphy1_clk = { 1458 .halt_reg = 0x15120, 1459 .halt_check = BRANCH_HALT, 1460 .clkr = { 1461 .enable_reg = 0x15120, 1462 .enable_mask = BIT(0), 1463 .hw.init = &(const struct clk_init_data) { 1464 .name = "cam_cc_csiphy1_clk", 1465 .parent_hws = (const struct clk_hw*[]) { 1466 &cam_cc_cphy_rx_clk_src.clkr.hw, 1467 }, 1468 .num_parents = 1, 1469 .flags = CLK_SET_RATE_PARENT, 1470 .ops = &clk_branch2_ops, 1471 }, 1472 }, 1473 }; 1474 1475 static struct clk_branch cam_cc_csiphy2_clk = { 1476 .halt_reg = 0x15254, 1477 .halt_check = BRANCH_HALT, 1478 .clkr = { 1479 .enable_reg = 0x15254, 1480 .enable_mask = BIT(0), 1481 .hw.init = &(const struct clk_init_data) { 1482 .name = "cam_cc_csiphy2_clk", 1483 .parent_hws = (const struct clk_hw*[]) { 1484 &cam_cc_cphy_rx_clk_src.clkr.hw, 1485 }, 1486 .num_parents = 1, 1487 .flags = CLK_SET_RATE_PARENT, 1488 .ops = &clk_branch2_ops, 1489 }, 1490 }, 1491 }; 1492 1493 static struct clk_branch cam_cc_csiphy3_clk = { 1494 .halt_reg = 0x15388, 1495 .halt_check = BRANCH_HALT, 1496 .clkr = { 1497 .enable_reg = 0x15388, 1498 .enable_mask = BIT(0), 1499 .hw.init = &(const struct clk_init_data) { 1500 .name = "cam_cc_csiphy3_clk", 1501 .parent_hws = (const struct clk_hw*[]) { 1502 &cam_cc_cphy_rx_clk_src.clkr.hw, 1503 }, 1504 .num_parents = 1, 1505 .flags = CLK_SET_RATE_PARENT, 1506 .ops = &clk_branch2_ops, 1507 }, 1508 }, 1509 }; 1510 1511 static struct clk_branch cam_cc_csiphy4_clk = { 1512 .halt_reg = 0x154bc, 1513 .halt_check = BRANCH_HALT, 1514 .clkr = { 1515 .enable_reg = 0x154bc, 1516 .enable_mask = BIT(0), 1517 .hw.init = &(const struct clk_init_data) { 1518 .name = "cam_cc_csiphy4_clk", 1519 .parent_hws = (const struct clk_hw*[]) { 1520 &cam_cc_cphy_rx_clk_src.clkr.hw, 1521 }, 1522 .num_parents = 1, 1523 .flags = CLK_SET_RATE_PARENT, 1524 .ops = &clk_branch2_ops, 1525 }, 1526 }, 1527 }; 1528 1529 static struct clk_branch cam_cc_csiphy5_clk = { 1530 .halt_reg = 0x155f0, 1531 .halt_check = BRANCH_HALT, 1532 .clkr = { 1533 .enable_reg = 0x155f0, 1534 .enable_mask = BIT(0), 1535 .hw.init = &(const struct clk_init_data) { 1536 .name = "cam_cc_csiphy5_clk", 1537 .parent_hws = (const struct clk_hw*[]) { 1538 &cam_cc_cphy_rx_clk_src.clkr.hw, 1539 }, 1540 .num_parents = 1, 1541 .flags = CLK_SET_RATE_PARENT, 1542 .ops = &clk_branch2_ops, 1543 }, 1544 }, 1545 }; 1546 1547 static struct clk_branch cam_cc_icp_ahb_clk = { 1548 .halt_reg = 0x13658, 1549 .halt_check = BRANCH_HALT, 1550 .clkr = { 1551 .enable_reg = 0x13658, 1552 .enable_mask = BIT(0), 1553 .hw.init = &(const struct clk_init_data) { 1554 .name = "cam_cc_icp_ahb_clk", 1555 .parent_hws = (const struct clk_hw*[]) { 1556 &cam_cc_slow_ahb_clk_src.clkr.hw, 1557 }, 1558 .num_parents = 1, 1559 .flags = CLK_SET_RATE_PARENT, 1560 .ops = &clk_branch2_ops, 1561 }, 1562 }, 1563 }; 1564 1565 static struct clk_branch cam_cc_icp_clk = { 1566 .halt_reg = 0x1364c, 1567 .halt_check = BRANCH_HALT, 1568 .clkr = { 1569 .enable_reg = 0x1364c, 1570 .enable_mask = BIT(0), 1571 .hw.init = &(const struct clk_init_data) { 1572 .name = "cam_cc_icp_clk", 1573 .parent_hws = (const struct clk_hw*[]) { 1574 &cam_cc_icp_clk_src.clkr.hw, 1575 }, 1576 .num_parents = 1, 1577 .flags = CLK_SET_RATE_PARENT, 1578 .ops = &clk_branch2_ops, 1579 }, 1580 }, 1581 }; 1582 1583 static struct clk_branch cam_cc_ife_0_clk = { 1584 .halt_reg = 0x11144, 1585 .halt_check = BRANCH_HALT, 1586 .clkr = { 1587 .enable_reg = 0x11144, 1588 .enable_mask = BIT(0), 1589 .hw.init = &(const struct clk_init_data) { 1590 .name = "cam_cc_ife_0_clk", 1591 .parent_hws = (const struct clk_hw*[]) { 1592 &cam_cc_ife_0_clk_src.clkr.hw, 1593 }, 1594 .num_parents = 1, 1595 .flags = CLK_SET_RATE_PARENT, 1596 .ops = &clk_branch2_ops, 1597 }, 1598 }, 1599 }; 1600 1601 static struct clk_branch cam_cc_ife_0_dsp_clk = { 1602 .halt_reg = 0x11154, 1603 .halt_check = BRANCH_HALT, 1604 .clkr = { 1605 .enable_reg = 0x11154, 1606 .enable_mask = BIT(0), 1607 .hw.init = &(const struct clk_init_data) { 1608 .name = "cam_cc_ife_0_dsp_clk", 1609 .parent_hws = (const struct clk_hw*[]) { 1610 &cam_cc_ife_0_clk_src.clkr.hw, 1611 }, 1612 .num_parents = 1, 1613 .flags = CLK_SET_RATE_PARENT, 1614 .ops = &clk_branch2_ops, 1615 }, 1616 }, 1617 }; 1618 1619 static struct clk_branch cam_cc_ife_0_fast_ahb_clk = { 1620 .halt_reg = 0x11160, 1621 .halt_check = BRANCH_HALT, 1622 .clkr = { 1623 .enable_reg = 0x11160, 1624 .enable_mask = BIT(0), 1625 .hw.init = &(const struct clk_init_data) { 1626 .name = "cam_cc_ife_0_fast_ahb_clk", 1627 .parent_hws = (const struct clk_hw*[]) { 1628 &cam_cc_fast_ahb_clk_src.clkr.hw, 1629 }, 1630 .num_parents = 1, 1631 .flags = CLK_SET_RATE_PARENT, 1632 .ops = &clk_branch2_ops, 1633 }, 1634 }, 1635 }; 1636 1637 static struct clk_branch cam_cc_ife_lite_ahb_clk = { 1638 .halt_reg = 0x13278, 1639 .halt_check = BRANCH_HALT, 1640 .clkr = { 1641 .enable_reg = 0x13278, 1642 .enable_mask = BIT(0), 1643 .hw.init = &(const struct clk_init_data) { 1644 .name = "cam_cc_ife_lite_ahb_clk", 1645 .parent_hws = (const struct clk_hw*[]) { 1646 &cam_cc_slow_ahb_clk_src.clkr.hw, 1647 }, 1648 .num_parents = 1, 1649 .flags = CLK_SET_RATE_PARENT, 1650 .ops = &clk_branch2_ops, 1651 }, 1652 }, 1653 }; 1654 1655 static struct clk_branch cam_cc_ife_lite_clk = { 1656 .halt_reg = 0x1312c, 1657 .halt_check = BRANCH_HALT, 1658 .clkr = { 1659 .enable_reg = 0x1312c, 1660 .enable_mask = BIT(0), 1661 .hw.init = &(const struct clk_init_data) { 1662 .name = "cam_cc_ife_lite_clk", 1663 .parent_hws = (const struct clk_hw*[]) { 1664 &cam_cc_ife_lite_clk_src.clkr.hw, 1665 }, 1666 .num_parents = 1, 1667 .flags = CLK_SET_RATE_PARENT, 1668 .ops = &clk_branch2_ops, 1669 }, 1670 }, 1671 }; 1672 1673 static struct clk_branch cam_cc_ife_lite_cphy_rx_clk = { 1674 .halt_reg = 0x13274, 1675 .halt_check = BRANCH_HALT, 1676 .clkr = { 1677 .enable_reg = 0x13274, 1678 .enable_mask = BIT(0), 1679 .hw.init = &(const struct clk_init_data) { 1680 .name = "cam_cc_ife_lite_cphy_rx_clk", 1681 .parent_hws = (const struct clk_hw*[]) { 1682 &cam_cc_cphy_rx_clk_src.clkr.hw, 1683 }, 1684 .num_parents = 1, 1685 .flags = CLK_SET_RATE_PARENT, 1686 .ops = &clk_branch2_ops, 1687 }, 1688 }, 1689 }; 1690 1691 static struct clk_branch cam_cc_ife_lite_csid_clk = { 1692 .halt_reg = 0x13268, 1693 .halt_check = BRANCH_HALT, 1694 .clkr = { 1695 .enable_reg = 0x13268, 1696 .enable_mask = BIT(0), 1697 .hw.init = &(const struct clk_init_data) { 1698 .name = "cam_cc_ife_lite_csid_clk", 1699 .parent_hws = (const struct clk_hw*[]) { 1700 &cam_cc_ife_lite_csid_clk_src.clkr.hw, 1701 }, 1702 .num_parents = 1, 1703 .flags = CLK_SET_RATE_PARENT, 1704 .ops = &clk_branch2_ops, 1705 }, 1706 }, 1707 }; 1708 1709 static struct clk_branch cam_cc_ipe_nps_ahb_clk = { 1710 .halt_reg = 0x1051c, 1711 .halt_check = BRANCH_HALT, 1712 .clkr = { 1713 .enable_reg = 0x1051c, 1714 .enable_mask = BIT(0), 1715 .hw.init = &(const struct clk_init_data) { 1716 .name = "cam_cc_ipe_nps_ahb_clk", 1717 .parent_hws = (const struct clk_hw*[]) { 1718 &cam_cc_slow_ahb_clk_src.clkr.hw, 1719 }, 1720 .num_parents = 1, 1721 .flags = CLK_SET_RATE_PARENT, 1722 .ops = &clk_branch2_ops, 1723 }, 1724 }, 1725 }; 1726 1727 static struct clk_branch cam_cc_ipe_nps_clk = { 1728 .halt_reg = 0x104f8, 1729 .halt_check = BRANCH_HALT, 1730 .clkr = { 1731 .enable_reg = 0x104f8, 1732 .enable_mask = BIT(0), 1733 .hw.init = &(const struct clk_init_data) { 1734 .name = "cam_cc_ipe_nps_clk", 1735 .parent_hws = (const struct clk_hw*[]) { 1736 &cam_cc_ipe_nps_clk_src.clkr.hw, 1737 }, 1738 .num_parents = 1, 1739 .flags = CLK_SET_RATE_PARENT, 1740 .ops = &clk_branch2_ops, 1741 }, 1742 }, 1743 }; 1744 1745 static struct clk_branch cam_cc_ipe_nps_fast_ahb_clk = { 1746 .halt_reg = 0x10520, 1747 .halt_check = BRANCH_HALT, 1748 .clkr = { 1749 .enable_reg = 0x10520, 1750 .enable_mask = BIT(0), 1751 .hw.init = &(const struct clk_init_data) { 1752 .name = "cam_cc_ipe_nps_fast_ahb_clk", 1753 .parent_hws = (const struct clk_hw*[]) { 1754 &cam_cc_fast_ahb_clk_src.clkr.hw, 1755 }, 1756 .num_parents = 1, 1757 .flags = CLK_SET_RATE_PARENT, 1758 .ops = &clk_branch2_ops, 1759 }, 1760 }, 1761 }; 1762 1763 static struct clk_branch cam_cc_ipe_pps_clk = { 1764 .halt_reg = 0x10508, 1765 .halt_check = BRANCH_HALT, 1766 .clkr = { 1767 .enable_reg = 0x10508, 1768 .enable_mask = BIT(0), 1769 .hw.init = &(const struct clk_init_data) { 1770 .name = "cam_cc_ipe_pps_clk", 1771 .parent_hws = (const struct clk_hw*[]) { 1772 &cam_cc_ipe_nps_clk_src.clkr.hw, 1773 }, 1774 .num_parents = 1, 1775 .flags = CLK_SET_RATE_PARENT, 1776 .ops = &clk_branch2_ops, 1777 }, 1778 }, 1779 }; 1780 1781 static struct clk_branch cam_cc_ipe_pps_fast_ahb_clk = { 1782 .halt_reg = 0x10524, 1783 .halt_check = BRANCH_HALT, 1784 .clkr = { 1785 .enable_reg = 0x10524, 1786 .enable_mask = BIT(0), 1787 .hw.init = &(const struct clk_init_data) { 1788 .name = "cam_cc_ipe_pps_fast_ahb_clk", 1789 .parent_hws = (const struct clk_hw*[]) { 1790 &cam_cc_fast_ahb_clk_src.clkr.hw, 1791 }, 1792 .num_parents = 1, 1793 .flags = CLK_SET_RATE_PARENT, 1794 .ops = &clk_branch2_ops, 1795 }, 1796 }, 1797 }; 1798 1799 static struct clk_branch cam_cc_jpeg_clk = { 1800 .halt_reg = 0x13508, 1801 .halt_check = BRANCH_HALT, 1802 .clkr = { 1803 .enable_reg = 0x13508, 1804 .enable_mask = BIT(0), 1805 .hw.init = &(const struct clk_init_data) { 1806 .name = "cam_cc_jpeg_clk", 1807 .parent_hws = (const struct clk_hw*[]) { 1808 &cam_cc_jpeg_clk_src.clkr.hw, 1809 }, 1810 .num_parents = 1, 1811 .flags = CLK_SET_RATE_PARENT, 1812 .ops = &clk_branch2_ops, 1813 }, 1814 }, 1815 }; 1816 1817 static struct clk_branch cam_cc_mclk0_clk = { 1818 .halt_reg = 0x15018, 1819 .halt_check = BRANCH_HALT, 1820 .clkr = { 1821 .enable_reg = 0x15018, 1822 .enable_mask = BIT(0), 1823 .hw.init = &(const struct clk_init_data) { 1824 .name = "cam_cc_mclk0_clk", 1825 .parent_hws = (const struct clk_hw*[]) { 1826 &cam_cc_mclk0_clk_src.clkr.hw, 1827 }, 1828 .num_parents = 1, 1829 .flags = CLK_SET_RATE_PARENT, 1830 .ops = &clk_branch2_ops, 1831 }, 1832 }, 1833 }; 1834 1835 static struct clk_branch cam_cc_mclk1_clk = { 1836 .halt_reg = 0x15034, 1837 .halt_check = BRANCH_HALT, 1838 .clkr = { 1839 .enable_reg = 0x15034, 1840 .enable_mask = BIT(0), 1841 .hw.init = &(const struct clk_init_data) { 1842 .name = "cam_cc_mclk1_clk", 1843 .parent_hws = (const struct clk_hw*[]) { 1844 &cam_cc_mclk1_clk_src.clkr.hw, 1845 }, 1846 .num_parents = 1, 1847 .flags = CLK_SET_RATE_PARENT, 1848 .ops = &clk_branch2_ops, 1849 }, 1850 }, 1851 }; 1852 1853 static struct clk_branch cam_cc_mclk2_clk = { 1854 .halt_reg = 0x15050, 1855 .halt_check = BRANCH_HALT, 1856 .clkr = { 1857 .enable_reg = 0x15050, 1858 .enable_mask = BIT(0), 1859 .hw.init = &(const struct clk_init_data) { 1860 .name = "cam_cc_mclk2_clk", 1861 .parent_hws = (const struct clk_hw*[]) { 1862 &cam_cc_mclk2_clk_src.clkr.hw, 1863 }, 1864 .num_parents = 1, 1865 .flags = CLK_SET_RATE_PARENT, 1866 .ops = &clk_branch2_ops, 1867 }, 1868 }, 1869 }; 1870 1871 static struct clk_branch cam_cc_mclk3_clk = { 1872 .halt_reg = 0x1506c, 1873 .halt_check = BRANCH_HALT, 1874 .clkr = { 1875 .enable_reg = 0x1506c, 1876 .enable_mask = BIT(0), 1877 .hw.init = &(const struct clk_init_data) { 1878 .name = "cam_cc_mclk3_clk", 1879 .parent_hws = (const struct clk_hw*[]) { 1880 &cam_cc_mclk3_clk_src.clkr.hw, 1881 }, 1882 .num_parents = 1, 1883 .flags = CLK_SET_RATE_PARENT, 1884 .ops = &clk_branch2_ops, 1885 }, 1886 }, 1887 }; 1888 1889 static struct clk_branch cam_cc_mclk4_clk = { 1890 .halt_reg = 0x15088, 1891 .halt_check = BRANCH_HALT, 1892 .clkr = { 1893 .enable_reg = 0x15088, 1894 .enable_mask = BIT(0), 1895 .hw.init = &(const struct clk_init_data) { 1896 .name = "cam_cc_mclk4_clk", 1897 .parent_hws = (const struct clk_hw*[]) { 1898 &cam_cc_mclk4_clk_src.clkr.hw, 1899 }, 1900 .num_parents = 1, 1901 .flags = CLK_SET_RATE_PARENT, 1902 .ops = &clk_branch2_ops, 1903 }, 1904 }, 1905 }; 1906 1907 static struct clk_branch cam_cc_mclk5_clk = { 1908 .halt_reg = 0x150a4, 1909 .halt_check = BRANCH_HALT, 1910 .clkr = { 1911 .enable_reg = 0x150a4, 1912 .enable_mask = BIT(0), 1913 .hw.init = &(const struct clk_init_data) { 1914 .name = "cam_cc_mclk5_clk", 1915 .parent_hws = (const struct clk_hw*[]) { 1916 &cam_cc_mclk5_clk_src.clkr.hw, 1917 }, 1918 .num_parents = 1, 1919 .flags = CLK_SET_RATE_PARENT, 1920 .ops = &clk_branch2_ops, 1921 }, 1922 }, 1923 }; 1924 1925 static struct clk_branch cam_cc_mclk6_clk = { 1926 .halt_reg = 0x150c0, 1927 .halt_check = BRANCH_HALT, 1928 .clkr = { 1929 .enable_reg = 0x150c0, 1930 .enable_mask = BIT(0), 1931 .hw.init = &(const struct clk_init_data) { 1932 .name = "cam_cc_mclk6_clk", 1933 .parent_hws = (const struct clk_hw*[]) { 1934 &cam_cc_mclk6_clk_src.clkr.hw, 1935 }, 1936 .num_parents = 1, 1937 .flags = CLK_SET_RATE_PARENT, 1938 .ops = &clk_branch2_ops, 1939 }, 1940 }, 1941 }; 1942 1943 static struct clk_branch cam_cc_mclk7_clk = { 1944 .halt_reg = 0x150dc, 1945 .halt_check = BRANCH_HALT, 1946 .clkr = { 1947 .enable_reg = 0x150dc, 1948 .enable_mask = BIT(0), 1949 .hw.init = &(const struct clk_init_data) { 1950 .name = "cam_cc_mclk7_clk", 1951 .parent_hws = (const struct clk_hw*[]) { 1952 &cam_cc_mclk7_clk_src.clkr.hw, 1953 }, 1954 .num_parents = 1, 1955 .flags = CLK_SET_RATE_PARENT, 1956 .ops = &clk_branch2_ops, 1957 }, 1958 }, 1959 }; 1960 1961 static struct clk_branch cam_cc_qdss_debug_clk = { 1962 .halt_reg = 0x13a64, 1963 .halt_check = BRANCH_HALT, 1964 .clkr = { 1965 .enable_reg = 0x13a64, 1966 .enable_mask = BIT(0), 1967 .hw.init = &(const struct clk_init_data) { 1968 .name = "cam_cc_qdss_debug_clk", 1969 .parent_hws = (const struct clk_hw*[]) { 1970 &cam_cc_qdss_debug_clk_src.clkr.hw, 1971 }, 1972 .num_parents = 1, 1973 .flags = CLK_SET_RATE_PARENT, 1974 .ops = &clk_branch2_ops, 1975 }, 1976 }, 1977 }; 1978 1979 static struct clk_branch cam_cc_qdss_debug_xo_clk = { 1980 .halt_reg = 0x13a68, 1981 .halt_check = BRANCH_HALT, 1982 .clkr = { 1983 .enable_reg = 0x13a68, 1984 .enable_mask = BIT(0), 1985 .hw.init = &(const struct clk_init_data) { 1986 .name = "cam_cc_qdss_debug_xo_clk", 1987 .parent_hws = (const struct clk_hw*[]) { 1988 &cam_cc_xo_clk_src.clkr.hw, 1989 }, 1990 .num_parents = 1, 1991 .flags = CLK_SET_RATE_PARENT, 1992 .ops = &clk_branch2_ops, 1993 }, 1994 }, 1995 }; 1996 1997 static struct gdsc cam_cc_titan_top_gdsc = { 1998 .gdscr = 0x13a6c, 1999 .en_rest_wait_val = 0x2, 2000 .en_few_wait_val = 0x2, 2001 .clk_dis_wait_val = 0xf, 2002 .pd = { 2003 .name = "cam_cc_titan_top_gdsc", 2004 }, 2005 .pwrsts = PWRSTS_OFF_ON, 2006 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 2007 }; 2008 2009 static struct gdsc cam_cc_bps_gdsc = { 2010 .gdscr = 0x10004, 2011 .en_rest_wait_val = 0x2, 2012 .en_few_wait_val = 0x2, 2013 .clk_dis_wait_val = 0xf, 2014 .pd = { 2015 .name = "cam_cc_bps_gdsc", 2016 }, 2017 .pwrsts = PWRSTS_OFF_ON, 2018 .parent = &cam_cc_titan_top_gdsc.pd, 2019 .flags = HW_CTRL_TRIGGER | POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 2020 }; 2021 2022 static struct gdsc cam_cc_ife_0_gdsc = { 2023 .gdscr = 0x11004, 2024 .en_rest_wait_val = 0x2, 2025 .en_few_wait_val = 0x2, 2026 .clk_dis_wait_val = 0xf, 2027 .pd = { 2028 .name = "cam_cc_ife_0_gdsc", 2029 }, 2030 .pwrsts = PWRSTS_OFF_ON, 2031 .parent = &cam_cc_titan_top_gdsc.pd, 2032 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 2033 }; 2034 2035 static struct gdsc cam_cc_ipe_0_gdsc = { 2036 .gdscr = 0x103b8, 2037 .en_rest_wait_val = 0x2, 2038 .en_few_wait_val = 0x2, 2039 .clk_dis_wait_val = 0xf, 2040 .pd = { 2041 .name = "cam_cc_ipe_0_gdsc", 2042 }, 2043 .pwrsts = PWRSTS_OFF_ON, 2044 .parent = &cam_cc_titan_top_gdsc.pd, 2045 .flags = HW_CTRL_TRIGGER | POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 2046 }; 2047 2048 static struct clk_regmap *cam_cc_x1p42100_clocks[] = { 2049 [CAM_CC_BPS_AHB_CLK] = &cam_cc_bps_ahb_clk.clkr, 2050 [CAM_CC_BPS_CLK] = &cam_cc_bps_clk.clkr, 2051 [CAM_CC_BPS_CLK_SRC] = &cam_cc_bps_clk_src.clkr, 2052 [CAM_CC_BPS_FAST_AHB_CLK] = &cam_cc_bps_fast_ahb_clk.clkr, 2053 [CAM_CC_CAMNOC_AXI_NRT_CLK] = &cam_cc_camnoc_axi_nrt_clk.clkr, 2054 [CAM_CC_CAMNOC_AXI_RT_CLK] = &cam_cc_camnoc_axi_rt_clk.clkr, 2055 [CAM_CC_CAMNOC_AXI_RT_CLK_SRC] = &cam_cc_camnoc_axi_rt_clk_src.clkr, 2056 [CAM_CC_CAMNOC_DCD_XO_CLK] = &cam_cc_camnoc_dcd_xo_clk.clkr, 2057 [CAM_CC_CAMNOC_XO_CLK] = &cam_cc_camnoc_xo_clk.clkr, 2058 [CAM_CC_CCI_0_CLK] = &cam_cc_cci_0_clk.clkr, 2059 [CAM_CC_CCI_0_CLK_SRC] = &cam_cc_cci_0_clk_src.clkr, 2060 [CAM_CC_CCI_1_CLK] = &cam_cc_cci_1_clk.clkr, 2061 [CAM_CC_CCI_1_CLK_SRC] = &cam_cc_cci_1_clk_src.clkr, 2062 [CAM_CC_CORE_AHB_CLK] = &cam_cc_core_ahb_clk.clkr, 2063 [CAM_CC_CPAS_AHB_CLK] = &cam_cc_cpas_ahb_clk.clkr, 2064 [CAM_CC_CPAS_BPS_CLK] = &cam_cc_cpas_bps_clk.clkr, 2065 [CAM_CC_CPAS_FAST_AHB_CLK] = &cam_cc_cpas_fast_ahb_clk.clkr, 2066 [CAM_CC_CPAS_IFE_0_CLK] = &cam_cc_cpas_ife_0_clk.clkr, 2067 [CAM_CC_CPAS_IFE_LITE_CLK] = &cam_cc_cpas_ife_lite_clk.clkr, 2068 [CAM_CC_CPAS_IPE_NPS_CLK] = &cam_cc_cpas_ipe_nps_clk.clkr, 2069 [CAM_CC_CPHY_RX_CLK_SRC] = &cam_cc_cphy_rx_clk_src.clkr, 2070 [CAM_CC_CSI0PHYTIMER_CLK] = &cam_cc_csi0phytimer_clk.clkr, 2071 [CAM_CC_CSI0PHYTIMER_CLK_SRC] = &cam_cc_csi0phytimer_clk_src.clkr, 2072 [CAM_CC_CSI1PHYTIMER_CLK] = &cam_cc_csi1phytimer_clk.clkr, 2073 [CAM_CC_CSI1PHYTIMER_CLK_SRC] = &cam_cc_csi1phytimer_clk_src.clkr, 2074 [CAM_CC_CSI2PHYTIMER_CLK] = &cam_cc_csi2phytimer_clk.clkr, 2075 [CAM_CC_CSI2PHYTIMER_CLK_SRC] = &cam_cc_csi2phytimer_clk_src.clkr, 2076 [CAM_CC_CSI3PHYTIMER_CLK] = &cam_cc_csi3phytimer_clk.clkr, 2077 [CAM_CC_CSI3PHYTIMER_CLK_SRC] = &cam_cc_csi3phytimer_clk_src.clkr, 2078 [CAM_CC_CSI4PHYTIMER_CLK] = &cam_cc_csi4phytimer_clk.clkr, 2079 [CAM_CC_CSI4PHYTIMER_CLK_SRC] = &cam_cc_csi4phytimer_clk_src.clkr, 2080 [CAM_CC_CSI5PHYTIMER_CLK] = &cam_cc_csi5phytimer_clk.clkr, 2081 [CAM_CC_CSI5PHYTIMER_CLK_SRC] = &cam_cc_csi5phytimer_clk_src.clkr, 2082 [CAM_CC_CSID_CLK] = &cam_cc_csid_clk.clkr, 2083 [CAM_CC_CSID_CLK_SRC] = &cam_cc_csid_clk_src.clkr, 2084 [CAM_CC_CSID_CSIPHY_RX_CLK] = &cam_cc_csid_csiphy_rx_clk.clkr, 2085 [CAM_CC_CSIPHY0_CLK] = &cam_cc_csiphy0_clk.clkr, 2086 [CAM_CC_CSIPHY1_CLK] = &cam_cc_csiphy1_clk.clkr, 2087 [CAM_CC_CSIPHY2_CLK] = &cam_cc_csiphy2_clk.clkr, 2088 [CAM_CC_CSIPHY3_CLK] = &cam_cc_csiphy3_clk.clkr, 2089 [CAM_CC_CSIPHY4_CLK] = &cam_cc_csiphy4_clk.clkr, 2090 [CAM_CC_CSIPHY5_CLK] = &cam_cc_csiphy5_clk.clkr, 2091 [CAM_CC_FAST_AHB_CLK_SRC] = &cam_cc_fast_ahb_clk_src.clkr, 2092 [CAM_CC_ICP_AHB_CLK] = &cam_cc_icp_ahb_clk.clkr, 2093 [CAM_CC_ICP_CLK] = &cam_cc_icp_clk.clkr, 2094 [CAM_CC_ICP_CLK_SRC] = &cam_cc_icp_clk_src.clkr, 2095 [CAM_CC_IFE_0_CLK] = &cam_cc_ife_0_clk.clkr, 2096 [CAM_CC_IFE_0_CLK_SRC] = &cam_cc_ife_0_clk_src.clkr, 2097 [CAM_CC_IFE_0_DSP_CLK] = &cam_cc_ife_0_dsp_clk.clkr, 2098 [CAM_CC_IFE_0_FAST_AHB_CLK] = &cam_cc_ife_0_fast_ahb_clk.clkr, 2099 [CAM_CC_IFE_LITE_AHB_CLK] = &cam_cc_ife_lite_ahb_clk.clkr, 2100 [CAM_CC_IFE_LITE_CLK] = &cam_cc_ife_lite_clk.clkr, 2101 [CAM_CC_IFE_LITE_CLK_SRC] = &cam_cc_ife_lite_clk_src.clkr, 2102 [CAM_CC_IFE_LITE_CPHY_RX_CLK] = &cam_cc_ife_lite_cphy_rx_clk.clkr, 2103 [CAM_CC_IFE_LITE_CSID_CLK] = &cam_cc_ife_lite_csid_clk.clkr, 2104 [CAM_CC_IFE_LITE_CSID_CLK_SRC] = &cam_cc_ife_lite_csid_clk_src.clkr, 2105 [CAM_CC_IPE_NPS_AHB_CLK] = &cam_cc_ipe_nps_ahb_clk.clkr, 2106 [CAM_CC_IPE_NPS_CLK] = &cam_cc_ipe_nps_clk.clkr, 2107 [CAM_CC_IPE_NPS_CLK_SRC] = &cam_cc_ipe_nps_clk_src.clkr, 2108 [CAM_CC_IPE_NPS_FAST_AHB_CLK] = &cam_cc_ipe_nps_fast_ahb_clk.clkr, 2109 [CAM_CC_IPE_PPS_CLK] = &cam_cc_ipe_pps_clk.clkr, 2110 [CAM_CC_IPE_PPS_FAST_AHB_CLK] = &cam_cc_ipe_pps_fast_ahb_clk.clkr, 2111 [CAM_CC_JPEG_CLK] = &cam_cc_jpeg_clk.clkr, 2112 [CAM_CC_JPEG_CLK_SRC] = &cam_cc_jpeg_clk_src.clkr, 2113 [CAM_CC_MCLK0_CLK] = &cam_cc_mclk0_clk.clkr, 2114 [CAM_CC_MCLK0_CLK_SRC] = &cam_cc_mclk0_clk_src.clkr, 2115 [CAM_CC_MCLK1_CLK] = &cam_cc_mclk1_clk.clkr, 2116 [CAM_CC_MCLK1_CLK_SRC] = &cam_cc_mclk1_clk_src.clkr, 2117 [CAM_CC_MCLK2_CLK] = &cam_cc_mclk2_clk.clkr, 2118 [CAM_CC_MCLK2_CLK_SRC] = &cam_cc_mclk2_clk_src.clkr, 2119 [CAM_CC_MCLK3_CLK] = &cam_cc_mclk3_clk.clkr, 2120 [CAM_CC_MCLK3_CLK_SRC] = &cam_cc_mclk3_clk_src.clkr, 2121 [CAM_CC_MCLK4_CLK] = &cam_cc_mclk4_clk.clkr, 2122 [CAM_CC_MCLK4_CLK_SRC] = &cam_cc_mclk4_clk_src.clkr, 2123 [CAM_CC_MCLK5_CLK] = &cam_cc_mclk5_clk.clkr, 2124 [CAM_CC_MCLK5_CLK_SRC] = &cam_cc_mclk5_clk_src.clkr, 2125 [CAM_CC_MCLK6_CLK] = &cam_cc_mclk6_clk.clkr, 2126 [CAM_CC_MCLK6_CLK_SRC] = &cam_cc_mclk6_clk_src.clkr, 2127 [CAM_CC_MCLK7_CLK] = &cam_cc_mclk7_clk.clkr, 2128 [CAM_CC_MCLK7_CLK_SRC] = &cam_cc_mclk7_clk_src.clkr, 2129 [CAM_CC_PLL0] = &cam_cc_pll0.clkr, 2130 [CAM_CC_PLL0_OUT_EVEN] = &cam_cc_pll0_out_even.clkr, 2131 [CAM_CC_PLL0_OUT_ODD] = &cam_cc_pll0_out_odd.clkr, 2132 [CAM_CC_PLL1] = &cam_cc_pll1.clkr, 2133 [CAM_CC_PLL1_OUT_EVEN] = &cam_cc_pll1_out_even.clkr, 2134 [CAM_CC_PLL2] = &cam_cc_pll2.clkr, 2135 [CAM_CC_PLL3] = &cam_cc_pll3.clkr, 2136 [CAM_CC_PLL3_OUT_EVEN] = &cam_cc_pll3_out_even.clkr, 2137 [CAM_CC_PLL6] = &cam_cc_pll6.clkr, 2138 [CAM_CC_PLL6_OUT_EVEN] = &cam_cc_pll6_out_even.clkr, 2139 [CAM_CC_QDSS_DEBUG_CLK] = &cam_cc_qdss_debug_clk.clkr, 2140 [CAM_CC_QDSS_DEBUG_CLK_SRC] = &cam_cc_qdss_debug_clk_src.clkr, 2141 [CAM_CC_QDSS_DEBUG_XO_CLK] = &cam_cc_qdss_debug_xo_clk.clkr, 2142 [CAM_CC_SLEEP_CLK_SRC] = &cam_cc_sleep_clk_src.clkr, 2143 [CAM_CC_SLOW_AHB_CLK_SRC] = &cam_cc_slow_ahb_clk_src.clkr, 2144 [CAM_CC_XO_CLK_SRC] = &cam_cc_xo_clk_src.clkr, 2145 }; 2146 2147 static struct gdsc *cam_cc_x1p42100_gdscs[] = { 2148 [CAM_CC_BPS_GDSC] = &cam_cc_bps_gdsc, 2149 [CAM_CC_IFE_0_GDSC] = &cam_cc_ife_0_gdsc, 2150 [CAM_CC_IPE_0_GDSC] = &cam_cc_ipe_0_gdsc, 2151 [CAM_CC_TITAN_TOP_GDSC] = &cam_cc_titan_top_gdsc, 2152 }; 2153 2154 static const struct qcom_reset_map cam_cc_x1p42100_resets[] = { 2155 [CAM_CC_BPS_BCR] = { 0x10000 }, 2156 [CAM_CC_ICP_BCR] = { 0x1351c }, 2157 [CAM_CC_IFE_0_BCR] = { 0x11000 }, 2158 [CAM_CC_IPE_0_BCR] = { 0x103b4 }, 2159 }; 2160 2161 static struct clk_alpha_pll *cam_cc_x1p42100_plls[] = { 2162 &cam_cc_pll0, 2163 &cam_cc_pll1, 2164 &cam_cc_pll2, 2165 &cam_cc_pll3, 2166 &cam_cc_pll6, 2167 }; 2168 2169 static u32 cam_cc_x1p42100_critical_cbcrs[] = { 2170 0x13a9c, /* CAM_CC_GDSC_CLK */ 2171 0x13ab8, /* CAM_CC_SLEEP_CLK */ 2172 }; 2173 2174 static const struct regmap_config cam_cc_x1p42100_regmap_config = { 2175 .reg_bits = 32, 2176 .reg_stride = 4, 2177 .val_bits = 32, 2178 .max_register = 0x1603c, 2179 .fast_io = true, 2180 }; 2181 2182 static struct qcom_cc_driver_data cam_cc_x1p42100_driver_data = { 2183 .alpha_plls = cam_cc_x1p42100_plls, 2184 .num_alpha_plls = ARRAY_SIZE(cam_cc_x1p42100_plls), 2185 .clk_cbcrs = cam_cc_x1p42100_critical_cbcrs, 2186 .num_clk_cbcrs = ARRAY_SIZE(cam_cc_x1p42100_critical_cbcrs), 2187 }; 2188 2189 static struct qcom_cc_desc cam_cc_x1p42100_desc = { 2190 .config = &cam_cc_x1p42100_regmap_config, 2191 .clks = cam_cc_x1p42100_clocks, 2192 .num_clks = ARRAY_SIZE(cam_cc_x1p42100_clocks), 2193 .resets = cam_cc_x1p42100_resets, 2194 .num_resets = ARRAY_SIZE(cam_cc_x1p42100_resets), 2195 .gdscs = cam_cc_x1p42100_gdscs, 2196 .num_gdscs = ARRAY_SIZE(cam_cc_x1p42100_gdscs), 2197 .use_rpm = true, 2198 .driver_data = &cam_cc_x1p42100_driver_data, 2199 }; 2200 2201 static const struct of_device_id cam_cc_x1p42100_match_table[] = { 2202 { .compatible = "qcom,x1p42100-camcc" }, 2203 { } 2204 }; 2205 MODULE_DEVICE_TABLE(of, cam_cc_x1p42100_match_table); 2206 2207 static int cam_cc_x1p42100_probe(struct platform_device *pdev) 2208 { 2209 return qcom_cc_probe(pdev, &cam_cc_x1p42100_desc); 2210 } 2211 2212 static struct platform_driver cam_cc_x1p42100_driver = { 2213 .probe = cam_cc_x1p42100_probe, 2214 .driver = { 2215 .name = "camcc-x1p42100", 2216 .of_match_table = cam_cc_x1p42100_match_table, 2217 }, 2218 }; 2219 2220 module_platform_driver(cam_cc_x1p42100_driver); 2221 2222 MODULE_DESCRIPTION("QTI CAMCC X1P42100 Driver"); 2223 MODULE_LICENSE("GPL"); 2224