1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 4 */ 5 6 #include <linux/clk-provider.h> 7 #include <linux/module.h> 8 #include <linux/platform_device.h> 9 #include <linux/regmap.h> 10 11 #include <dt-bindings/clock/qcom,sm8750-camcc.h> 12 13 #include "clk-alpha-pll.h" 14 #include "clk-branch.h" 15 #include "clk-rcg.h" 16 #include "clk-regmap.h" 17 #include "common.h" 18 #include "gdsc.h" 19 #include "reset.h" 20 21 enum { 22 DT_IFACE, 23 DT_BI_TCXO, 24 DT_BI_TCXO_AO, 25 DT_SLEEP_CLK, 26 }; 27 28 enum { 29 P_BI_TCXO, 30 P_BI_TCXO_AO, 31 P_CAM_CC_PLL0_OUT_EVEN, 32 P_CAM_CC_PLL0_OUT_MAIN, 33 P_CAM_CC_PLL0_OUT_ODD, 34 P_CAM_CC_PLL1_OUT_EVEN, 35 P_CAM_CC_PLL2_OUT_EVEN, 36 P_CAM_CC_PLL3_OUT_EVEN, 37 P_CAM_CC_PLL4_OUT_EVEN, 38 P_CAM_CC_PLL5_OUT_EVEN, 39 P_CAM_CC_PLL6_OUT_EVEN, 40 P_CAM_CC_PLL6_OUT_ODD, 41 P_SLEEP_CLK, 42 }; 43 44 static const struct pll_vco taycan_elu_vco[] = { 45 { 249600000, 2500000000, 0 }, 46 }; 47 48 static const struct alpha_pll_config cam_cc_pll0_config = { 49 .l = 0x3e, 50 .alpha = 0x8000, 51 .config_ctl_val = 0x19660387, 52 .config_ctl_hi_val = 0x098060a0, 53 .config_ctl_hi1_val = 0xb416cb20, 54 .user_ctl_val = 0x00008400, 55 .user_ctl_hi_val = 0x00000002, 56 }; 57 58 static struct clk_alpha_pll cam_cc_pll0 = { 59 .offset = 0x0, 60 .config = &cam_cc_pll0_config, 61 .vco_table = taycan_elu_vco, 62 .num_vco = ARRAY_SIZE(taycan_elu_vco), 63 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_ELU], 64 .clkr = { 65 .hw.init = &(const struct clk_init_data) { 66 .name = "cam_cc_pll0", 67 .parent_data = &(const struct clk_parent_data) { 68 .index = DT_BI_TCXO, 69 }, 70 .num_parents = 1, 71 .ops = &clk_alpha_pll_taycan_elu_ops, 72 }, 73 }, 74 }; 75 76 static const struct clk_div_table post_div_table_cam_cc_pll0_out_even[] = { 77 { 0x1, 2 }, 78 { } 79 }; 80 81 static struct clk_alpha_pll_postdiv cam_cc_pll0_out_even = { 82 .offset = 0x0, 83 .post_div_shift = 10, 84 .post_div_table = post_div_table_cam_cc_pll0_out_even, 85 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll0_out_even), 86 .width = 4, 87 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_ELU], 88 .clkr.hw.init = &(const struct clk_init_data) { 89 .name = "cam_cc_pll0_out_even", 90 .parent_hws = (const struct clk_hw*[]) { 91 &cam_cc_pll0.clkr.hw, 92 }, 93 .num_parents = 1, 94 .flags = CLK_SET_RATE_PARENT, 95 .ops = &clk_alpha_pll_postdiv_taycan_elu_ops, 96 }, 97 }; 98 99 static const struct clk_div_table post_div_table_cam_cc_pll0_out_odd[] = { 100 { 0x2, 3 }, 101 { } 102 }; 103 104 static struct clk_alpha_pll_postdiv cam_cc_pll0_out_odd = { 105 .offset = 0x0, 106 .post_div_shift = 14, 107 .post_div_table = post_div_table_cam_cc_pll0_out_odd, 108 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll0_out_odd), 109 .width = 4, 110 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_ELU], 111 .clkr.hw.init = &(const struct clk_init_data) { 112 .name = "cam_cc_pll0_out_odd", 113 .parent_hws = (const struct clk_hw*[]) { 114 &cam_cc_pll0.clkr.hw, 115 }, 116 .num_parents = 1, 117 .flags = CLK_SET_RATE_PARENT, 118 .ops = &clk_alpha_pll_postdiv_taycan_elu_ops, 119 }, 120 }; 121 122 static const struct alpha_pll_config cam_cc_pll1_config = { 123 .l = 0x22, 124 .alpha = 0xa2aa, 125 .config_ctl_val = 0x19660387, 126 .config_ctl_hi_val = 0x098060a0, 127 .config_ctl_hi1_val = 0xb416cb20, 128 .user_ctl_val = 0x00000400, 129 .user_ctl_hi_val = 0x00000002, 130 }; 131 132 static struct clk_alpha_pll cam_cc_pll1 = { 133 .offset = 0x1000, 134 .config = &cam_cc_pll1_config, 135 .vco_table = taycan_elu_vco, 136 .num_vco = ARRAY_SIZE(taycan_elu_vco), 137 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_ELU], 138 .clkr = { 139 .hw.init = &(const struct clk_init_data) { 140 .name = "cam_cc_pll1", 141 .parent_data = &(const struct clk_parent_data) { 142 .index = DT_BI_TCXO, 143 }, 144 .num_parents = 1, 145 .ops = &clk_alpha_pll_taycan_elu_ops, 146 }, 147 }, 148 }; 149 150 static const struct clk_div_table post_div_table_cam_cc_pll1_out_even[] = { 151 { 0x1, 2 }, 152 { } 153 }; 154 155 static struct clk_alpha_pll_postdiv cam_cc_pll1_out_even = { 156 .offset = 0x1000, 157 .post_div_shift = 10, 158 .post_div_table = post_div_table_cam_cc_pll1_out_even, 159 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll1_out_even), 160 .width = 4, 161 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_ELU], 162 .clkr.hw.init = &(const struct clk_init_data) { 163 .name = "cam_cc_pll1_out_even", 164 .parent_hws = (const struct clk_hw*[]) { 165 &cam_cc_pll1.clkr.hw, 166 }, 167 .num_parents = 1, 168 .flags = CLK_SET_RATE_PARENT, 169 .ops = &clk_alpha_pll_postdiv_taycan_elu_ops, 170 }, 171 }; 172 173 static const struct alpha_pll_config cam_cc_pll2_config = { 174 .l = 0x23, 175 .alpha = 0x4aaa, 176 .config_ctl_val = 0x19660387, 177 .config_ctl_hi_val = 0x098060a0, 178 .config_ctl_hi1_val = 0xb416cb20, 179 .user_ctl_val = 0x00000400, 180 .user_ctl_hi_val = 0x00000002, 181 }; 182 183 static struct clk_alpha_pll cam_cc_pll2 = { 184 .offset = 0x2000, 185 .config = &cam_cc_pll2_config, 186 .vco_table = taycan_elu_vco, 187 .num_vco = ARRAY_SIZE(taycan_elu_vco), 188 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_ELU], 189 .clkr = { 190 .hw.init = &(const struct clk_init_data) { 191 .name = "cam_cc_pll2", 192 .parent_data = &(const struct clk_parent_data) { 193 .index = DT_BI_TCXO, 194 }, 195 .num_parents = 1, 196 .ops = &clk_alpha_pll_taycan_elu_ops, 197 }, 198 }, 199 }; 200 201 static const struct clk_div_table post_div_table_cam_cc_pll2_out_even[] = { 202 { 0x1, 2 }, 203 { } 204 }; 205 206 static struct clk_alpha_pll_postdiv cam_cc_pll2_out_even = { 207 .offset = 0x2000, 208 .post_div_shift = 10, 209 .post_div_table = post_div_table_cam_cc_pll2_out_even, 210 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll2_out_even), 211 .width = 4, 212 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_ELU], 213 .clkr.hw.init = &(const struct clk_init_data) { 214 .name = "cam_cc_pll2_out_even", 215 .parent_hws = (const struct clk_hw*[]) { 216 &cam_cc_pll2.clkr.hw, 217 }, 218 .num_parents = 1, 219 .flags = CLK_SET_RATE_PARENT, 220 .ops = &clk_alpha_pll_postdiv_taycan_elu_ops, 221 }, 222 }; 223 224 static const struct alpha_pll_config cam_cc_pll3_config = { 225 .l = 0x25, 226 .alpha = 0x8777, 227 .config_ctl_val = 0x19660387, 228 .config_ctl_hi_val = 0x098060a0, 229 .config_ctl_hi1_val = 0xb416cb20, 230 .user_ctl_val = 0x00000400, 231 .user_ctl_hi_val = 0x00000002, 232 }; 233 234 static struct clk_alpha_pll cam_cc_pll3 = { 235 .offset = 0x3000, 236 .config = &cam_cc_pll3_config, 237 .vco_table = taycan_elu_vco, 238 .num_vco = ARRAY_SIZE(taycan_elu_vco), 239 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_ELU], 240 .clkr = { 241 .hw.init = &(const struct clk_init_data) { 242 .name = "cam_cc_pll3", 243 .parent_data = &(const struct clk_parent_data) { 244 .index = DT_BI_TCXO, 245 }, 246 .num_parents = 1, 247 .ops = &clk_alpha_pll_taycan_elu_ops, 248 }, 249 }, 250 }; 251 252 static const struct clk_div_table post_div_table_cam_cc_pll3_out_even[] = { 253 { 0x1, 2 }, 254 { } 255 }; 256 257 static struct clk_alpha_pll_postdiv cam_cc_pll3_out_even = { 258 .offset = 0x3000, 259 .post_div_shift = 10, 260 .post_div_table = post_div_table_cam_cc_pll3_out_even, 261 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll3_out_even), 262 .width = 4, 263 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_ELU], 264 .clkr.hw.init = &(const struct clk_init_data) { 265 .name = "cam_cc_pll3_out_even", 266 .parent_hws = (const struct clk_hw*[]) { 267 &cam_cc_pll3.clkr.hw, 268 }, 269 .num_parents = 1, 270 .flags = CLK_SET_RATE_PARENT, 271 .ops = &clk_alpha_pll_postdiv_taycan_elu_ops, 272 }, 273 }; 274 275 static const struct alpha_pll_config cam_cc_pll4_config = { 276 .l = 0x25, 277 .alpha = 0x8777, 278 .config_ctl_val = 0x19660387, 279 .config_ctl_hi_val = 0x098060a0, 280 .config_ctl_hi1_val = 0xb416cb20, 281 .user_ctl_val = 0x00000400, 282 .user_ctl_hi_val = 0x00000002, 283 }; 284 285 static struct clk_alpha_pll cam_cc_pll4 = { 286 .offset = 0x4000, 287 .config = &cam_cc_pll4_config, 288 .vco_table = taycan_elu_vco, 289 .num_vco = ARRAY_SIZE(taycan_elu_vco), 290 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_ELU], 291 .clkr = { 292 .hw.init = &(const struct clk_init_data) { 293 .name = "cam_cc_pll4", 294 .parent_data = &(const struct clk_parent_data) { 295 .index = DT_BI_TCXO, 296 }, 297 .num_parents = 1, 298 .ops = &clk_alpha_pll_taycan_elu_ops, 299 }, 300 }, 301 }; 302 303 static const struct clk_div_table post_div_table_cam_cc_pll4_out_even[] = { 304 { 0x1, 2 }, 305 { } 306 }; 307 308 static struct clk_alpha_pll_postdiv cam_cc_pll4_out_even = { 309 .offset = 0x4000, 310 .post_div_shift = 10, 311 .post_div_table = post_div_table_cam_cc_pll4_out_even, 312 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll4_out_even), 313 .width = 4, 314 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_ELU], 315 .clkr.hw.init = &(const struct clk_init_data) { 316 .name = "cam_cc_pll4_out_even", 317 .parent_hws = (const struct clk_hw*[]) { 318 &cam_cc_pll4.clkr.hw, 319 }, 320 .num_parents = 1, 321 .flags = CLK_SET_RATE_PARENT, 322 .ops = &clk_alpha_pll_postdiv_taycan_elu_ops, 323 }, 324 }; 325 326 static const struct alpha_pll_config cam_cc_pll5_config = { 327 .l = 0x25, 328 .alpha = 0x8777, 329 .config_ctl_val = 0x19660387, 330 .config_ctl_hi_val = 0x098060a0, 331 .config_ctl_hi1_val = 0xb416cb20, 332 .user_ctl_val = 0x00000400, 333 .user_ctl_hi_val = 0x00000002, 334 }; 335 336 static struct clk_alpha_pll cam_cc_pll5 = { 337 .offset = 0x5000, 338 .config = &cam_cc_pll5_config, 339 .vco_table = taycan_elu_vco, 340 .num_vco = ARRAY_SIZE(taycan_elu_vco), 341 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_ELU], 342 .clkr = { 343 .hw.init = &(const struct clk_init_data) { 344 .name = "cam_cc_pll5", 345 .parent_data = &(const struct clk_parent_data) { 346 .index = DT_BI_TCXO, 347 }, 348 .num_parents = 1, 349 .ops = &clk_alpha_pll_taycan_elu_ops, 350 }, 351 }, 352 }; 353 354 static const struct clk_div_table post_div_table_cam_cc_pll5_out_even[] = { 355 { 0x1, 2 }, 356 { } 357 }; 358 359 static struct clk_alpha_pll_postdiv cam_cc_pll5_out_even = { 360 .offset = 0x5000, 361 .post_div_shift = 10, 362 .post_div_table = post_div_table_cam_cc_pll5_out_even, 363 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll5_out_even), 364 .width = 4, 365 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_ELU], 366 .clkr.hw.init = &(const struct clk_init_data) { 367 .name = "cam_cc_pll5_out_even", 368 .parent_hws = (const struct clk_hw*[]) { 369 &cam_cc_pll5.clkr.hw, 370 }, 371 .num_parents = 1, 372 .flags = CLK_SET_RATE_PARENT, 373 .ops = &clk_alpha_pll_postdiv_taycan_elu_ops, 374 }, 375 }; 376 377 static const struct alpha_pll_config cam_cc_pll6_config = { 378 .l = 0x32, 379 .alpha = 0x0, 380 .config_ctl_val = 0x19660387, 381 .config_ctl_hi_val = 0x098060a0, 382 .config_ctl_hi1_val = 0xb416cb20, 383 .user_ctl_val = 0x00008400, 384 .user_ctl_hi_val = 0x00000002, 385 }; 386 387 static struct clk_alpha_pll cam_cc_pll6 = { 388 .offset = 0x6000, 389 .config = &cam_cc_pll6_config, 390 .vco_table = taycan_elu_vco, 391 .num_vco = ARRAY_SIZE(taycan_elu_vco), 392 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_ELU], 393 .clkr = { 394 .hw.init = &(const struct clk_init_data) { 395 .name = "cam_cc_pll6", 396 .parent_data = &(const struct clk_parent_data) { 397 .index = DT_BI_TCXO, 398 }, 399 .num_parents = 1, 400 .ops = &clk_alpha_pll_taycan_elu_ops, 401 }, 402 }, 403 }; 404 405 static const struct clk_div_table post_div_table_cam_cc_pll6_out_even[] = { 406 { 0x1, 2 }, 407 { } 408 }; 409 410 static struct clk_alpha_pll_postdiv cam_cc_pll6_out_even = { 411 .offset = 0x6000, 412 .post_div_shift = 10, 413 .post_div_table = post_div_table_cam_cc_pll6_out_even, 414 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll6_out_even), 415 .width = 4, 416 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_ELU], 417 .clkr.hw.init = &(const struct clk_init_data) { 418 .name = "cam_cc_pll6_out_even", 419 .parent_hws = (const struct clk_hw*[]) { 420 &cam_cc_pll6.clkr.hw, 421 }, 422 .num_parents = 1, 423 .flags = CLK_SET_RATE_PARENT, 424 .ops = &clk_alpha_pll_postdiv_taycan_elu_ops, 425 }, 426 }; 427 428 static const struct clk_div_table post_div_table_cam_cc_pll6_out_odd[] = { 429 { 0x2, 3 }, 430 { } 431 }; 432 433 static struct clk_alpha_pll_postdiv cam_cc_pll6_out_odd = { 434 .offset = 0x6000, 435 .post_div_shift = 14, 436 .post_div_table = post_div_table_cam_cc_pll6_out_odd, 437 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll6_out_odd), 438 .width = 4, 439 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_ELU], 440 .clkr.hw.init = &(const struct clk_init_data) { 441 .name = "cam_cc_pll6_out_odd", 442 .parent_hws = (const struct clk_hw*[]) { 443 &cam_cc_pll6.clkr.hw, 444 }, 445 .num_parents = 1, 446 .flags = CLK_SET_RATE_PARENT, 447 .ops = &clk_alpha_pll_postdiv_taycan_elu_ops, 448 }, 449 }; 450 451 static const struct parent_map cam_cc_parent_map_0[] = { 452 { P_BI_TCXO, 0 }, 453 { P_CAM_CC_PLL0_OUT_MAIN, 1 }, 454 { P_CAM_CC_PLL0_OUT_EVEN, 2 }, 455 { P_CAM_CC_PLL0_OUT_ODD, 3 }, 456 { P_CAM_CC_PLL6_OUT_ODD, 4 }, 457 { P_CAM_CC_PLL6_OUT_EVEN, 5 }, 458 }; 459 460 static const struct clk_parent_data cam_cc_parent_data_0[] = { 461 { .index = DT_BI_TCXO }, 462 { .hw = &cam_cc_pll0.clkr.hw }, 463 { .hw = &cam_cc_pll0_out_even.clkr.hw }, 464 { .hw = &cam_cc_pll0_out_odd.clkr.hw }, 465 { .hw = &cam_cc_pll6_out_odd.clkr.hw }, 466 { .hw = &cam_cc_pll6_out_even.clkr.hw }, 467 }; 468 469 static const struct parent_map cam_cc_parent_map_1[] = { 470 { P_BI_TCXO, 0 }, 471 { P_CAM_CC_PLL0_OUT_MAIN, 1 }, 472 { P_CAM_CC_PLL0_OUT_EVEN, 2 }, 473 { P_CAM_CC_PLL0_OUT_ODD, 3 }, 474 { P_CAM_CC_PLL6_OUT_ODD, 4 }, 475 { P_CAM_CC_PLL6_OUT_EVEN, 5 }, 476 }; 477 478 static const struct clk_parent_data cam_cc_parent_data_1[] = { 479 { .index = DT_BI_TCXO }, 480 { .hw = &cam_cc_pll0.clkr.hw }, 481 { .hw = &cam_cc_pll0_out_even.clkr.hw }, 482 { .hw = &cam_cc_pll0_out_odd.clkr.hw }, 483 { .hw = &cam_cc_pll6_out_odd.clkr.hw }, 484 { .hw = &cam_cc_pll6_out_even.clkr.hw }, 485 }; 486 487 static const struct parent_map cam_cc_parent_map_2[] = { 488 { P_BI_TCXO, 0 }, 489 { P_CAM_CC_PLL1_OUT_EVEN, 4 }, 490 }; 491 492 static const struct clk_parent_data cam_cc_parent_data_2[] = { 493 { .index = DT_BI_TCXO }, 494 { .hw = &cam_cc_pll1_out_even.clkr.hw }, 495 }; 496 497 static const struct parent_map cam_cc_parent_map_3[] = { 498 { P_BI_TCXO, 0 }, 499 { P_CAM_CC_PLL2_OUT_EVEN, 5 }, 500 }; 501 502 static const struct clk_parent_data cam_cc_parent_data_3[] = { 503 { .index = DT_BI_TCXO }, 504 { .hw = &cam_cc_pll2_out_even.clkr.hw }, 505 }; 506 507 static const struct parent_map cam_cc_parent_map_4[] = { 508 { P_SLEEP_CLK, 0 }, 509 }; 510 511 static const struct clk_parent_data cam_cc_parent_data_4[] = { 512 { .index = DT_SLEEP_CLK }, 513 }; 514 515 static const struct parent_map cam_cc_parent_map_5[] = { 516 { P_BI_TCXO, 0 }, 517 { P_CAM_CC_PLL3_OUT_EVEN, 6 }, 518 }; 519 520 static const struct clk_parent_data cam_cc_parent_data_5[] = { 521 { .index = DT_BI_TCXO }, 522 { .hw = &cam_cc_pll3_out_even.clkr.hw }, 523 }; 524 525 static const struct parent_map cam_cc_parent_map_6[] = { 526 { P_BI_TCXO, 0 }, 527 { P_CAM_CC_PLL4_OUT_EVEN, 6 }, 528 }; 529 530 static const struct clk_parent_data cam_cc_parent_data_6[] = { 531 { .index = DT_BI_TCXO }, 532 { .hw = &cam_cc_pll4_out_even.clkr.hw }, 533 }; 534 535 static const struct parent_map cam_cc_parent_map_7[] = { 536 { P_BI_TCXO, 0 }, 537 { P_CAM_CC_PLL5_OUT_EVEN, 6 }, 538 }; 539 540 static const struct clk_parent_data cam_cc_parent_data_7[] = { 541 { .index = DT_BI_TCXO }, 542 { .hw = &cam_cc_pll5_out_even.clkr.hw }, 543 }; 544 545 static const struct parent_map cam_cc_parent_map_8_ao[] = { 546 { P_BI_TCXO_AO, 0 }, 547 }; 548 549 static const struct clk_parent_data cam_cc_parent_data_8_ao[] = { 550 { .index = DT_BI_TCXO_AO }, 551 }; 552 553 static const struct freq_tbl ftbl_cam_cc_camnoc_rt_axi_clk_src[] = { 554 F(19200000, P_BI_TCXO, 1, 0, 0), 555 F(200000000, P_CAM_CC_PLL0_OUT_EVEN, 3, 0, 0), 556 F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0), 557 F(400000000, P_CAM_CC_PLL0_OUT_EVEN, 1.5, 0, 0), 558 { } 559 }; 560 561 static struct clk_rcg2 cam_cc_camnoc_rt_axi_clk_src = { 562 .cmd_rcgr = 0x112e8, 563 .mnd_width = 0, 564 .hid_width = 5, 565 .parent_map = cam_cc_parent_map_0, 566 .freq_tbl = ftbl_cam_cc_camnoc_rt_axi_clk_src, 567 .clkr.hw.init = &(const struct clk_init_data) { 568 .name = "cam_cc_camnoc_rt_axi_clk_src", 569 .parent_data = cam_cc_parent_data_0, 570 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 571 .flags = CLK_SET_RATE_PARENT, 572 .ops = &clk_rcg2_shared_ops, 573 }, 574 }; 575 576 static const struct freq_tbl ftbl_cam_cc_cci_0_clk_src[] = { 577 F(37500000, P_CAM_CC_PLL0_OUT_EVEN, 16, 0, 0), 578 { } 579 }; 580 581 static struct clk_rcg2 cam_cc_cci_0_clk_src = { 582 .cmd_rcgr = 0x1126c, 583 .mnd_width = 8, 584 .hid_width = 5, 585 .parent_map = cam_cc_parent_map_0, 586 .freq_tbl = ftbl_cam_cc_cci_0_clk_src, 587 .clkr.hw.init = &(const struct clk_init_data) { 588 .name = "cam_cc_cci_0_clk_src", 589 .parent_data = cam_cc_parent_data_0, 590 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 591 .flags = CLK_SET_RATE_PARENT, 592 .ops = &clk_rcg2_shared_ops, 593 }, 594 }; 595 596 static struct clk_rcg2 cam_cc_cci_1_clk_src = { 597 .cmd_rcgr = 0x11288, 598 .mnd_width = 8, 599 .hid_width = 5, 600 .parent_map = cam_cc_parent_map_0, 601 .freq_tbl = ftbl_cam_cc_cci_0_clk_src, 602 .clkr.hw.init = &(const struct clk_init_data) { 603 .name = "cam_cc_cci_1_clk_src", 604 .parent_data = cam_cc_parent_data_0, 605 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 606 .flags = CLK_SET_RATE_PARENT, 607 .ops = &clk_rcg2_shared_ops, 608 }, 609 }; 610 611 static struct clk_rcg2 cam_cc_cci_2_clk_src = { 612 .cmd_rcgr = 0x112a4, 613 .mnd_width = 8, 614 .hid_width = 5, 615 .parent_map = cam_cc_parent_map_0, 616 .freq_tbl = ftbl_cam_cc_cci_0_clk_src, 617 .clkr.hw.init = &(const struct clk_init_data) { 618 .name = "cam_cc_cci_2_clk_src", 619 .parent_data = cam_cc_parent_data_0, 620 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 621 .flags = CLK_SET_RATE_PARENT, 622 .ops = &clk_rcg2_shared_ops, 623 }, 624 }; 625 626 static const struct freq_tbl ftbl_cam_cc_cphy_rx_clk_src[] = { 627 F(266666667, P_CAM_CC_PLL0_OUT_MAIN, 4.5, 0, 0), 628 F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0), 629 F(480000000, P_CAM_CC_PLL0_OUT_MAIN, 2.5, 0, 0), 630 { } 631 }; 632 633 static struct clk_rcg2 cam_cc_cphy_rx_clk_src = { 634 .cmd_rcgr = 0x11068, 635 .mnd_width = 0, 636 .hid_width = 5, 637 .parent_map = cam_cc_parent_map_1, 638 .freq_tbl = ftbl_cam_cc_cphy_rx_clk_src, 639 .clkr.hw.init = &(const struct clk_init_data) { 640 .name = "cam_cc_cphy_rx_clk_src", 641 .parent_data = cam_cc_parent_data_1, 642 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 643 .flags = CLK_SET_RATE_PARENT, 644 .ops = &clk_rcg2_shared_ops, 645 }, 646 }; 647 648 static const struct freq_tbl ftbl_cam_cc_cre_clk_src[] = { 649 F(137142857, P_CAM_CC_PLL6_OUT_EVEN, 3.5, 0, 0), 650 F(200000000, P_CAM_CC_PLL0_OUT_ODD, 2, 0, 0), 651 F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), 652 F(480000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0), 653 F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0), 654 { } 655 }; 656 657 static struct clk_rcg2 cam_cc_cre_clk_src = { 658 .cmd_rcgr = 0x111ac, 659 .mnd_width = 0, 660 .hid_width = 5, 661 .parent_map = cam_cc_parent_map_0, 662 .freq_tbl = ftbl_cam_cc_cre_clk_src, 663 .clkr.hw.init = &(const struct clk_init_data) { 664 .name = "cam_cc_cre_clk_src", 665 .parent_data = cam_cc_parent_data_0, 666 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 667 .flags = CLK_SET_RATE_PARENT, 668 .ops = &clk_rcg2_shared_ops, 669 }, 670 }; 671 672 static const struct freq_tbl ftbl_cam_cc_csi0phytimer_clk_src[] = { 673 F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0), 674 { } 675 }; 676 677 static struct clk_rcg2 cam_cc_csi0phytimer_clk_src = { 678 .cmd_rcgr = 0x10000, 679 .mnd_width = 0, 680 .hid_width = 5, 681 .parent_map = cam_cc_parent_map_1, 682 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, 683 .clkr.hw.init = &(const struct clk_init_data) { 684 .name = "cam_cc_csi0phytimer_clk_src", 685 .parent_data = cam_cc_parent_data_1, 686 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 687 .flags = CLK_SET_RATE_PARENT, 688 .ops = &clk_rcg2_shared_ops, 689 }, 690 }; 691 692 static struct clk_rcg2 cam_cc_csi1phytimer_clk_src = { 693 .cmd_rcgr = 0x10024, 694 .mnd_width = 0, 695 .hid_width = 5, 696 .parent_map = cam_cc_parent_map_1, 697 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, 698 .clkr.hw.init = &(const struct clk_init_data) { 699 .name = "cam_cc_csi1phytimer_clk_src", 700 .parent_data = cam_cc_parent_data_1, 701 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 702 .flags = CLK_SET_RATE_PARENT, 703 .ops = &clk_rcg2_shared_ops, 704 }, 705 }; 706 707 static struct clk_rcg2 cam_cc_csi2phytimer_clk_src = { 708 .cmd_rcgr = 0x10044, 709 .mnd_width = 0, 710 .hid_width = 5, 711 .parent_map = cam_cc_parent_map_1, 712 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, 713 .clkr.hw.init = &(const struct clk_init_data) { 714 .name = "cam_cc_csi2phytimer_clk_src", 715 .parent_data = cam_cc_parent_data_1, 716 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 717 .flags = CLK_SET_RATE_PARENT, 718 .ops = &clk_rcg2_shared_ops, 719 }, 720 }; 721 722 static struct clk_rcg2 cam_cc_csi3phytimer_clk_src = { 723 .cmd_rcgr = 0x10064, 724 .mnd_width = 0, 725 .hid_width = 5, 726 .parent_map = cam_cc_parent_map_1, 727 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, 728 .clkr.hw.init = &(const struct clk_init_data) { 729 .name = "cam_cc_csi3phytimer_clk_src", 730 .parent_data = cam_cc_parent_data_1, 731 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 732 .flags = CLK_SET_RATE_PARENT, 733 .ops = &clk_rcg2_shared_ops, 734 }, 735 }; 736 737 static struct clk_rcg2 cam_cc_csi4phytimer_clk_src = { 738 .cmd_rcgr = 0x10084, 739 .mnd_width = 0, 740 .hid_width = 5, 741 .parent_map = cam_cc_parent_map_1, 742 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, 743 .clkr.hw.init = &(const struct clk_init_data) { 744 .name = "cam_cc_csi4phytimer_clk_src", 745 .parent_data = cam_cc_parent_data_1, 746 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 747 .flags = CLK_SET_RATE_PARENT, 748 .ops = &clk_rcg2_shared_ops, 749 }, 750 }; 751 752 static struct clk_rcg2 cam_cc_csi5phytimer_clk_src = { 753 .cmd_rcgr = 0x100a4, 754 .mnd_width = 0, 755 .hid_width = 5, 756 .parent_map = cam_cc_parent_map_1, 757 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, 758 .clkr.hw.init = &(const struct clk_init_data) { 759 .name = "cam_cc_csi5phytimer_clk_src", 760 .parent_data = cam_cc_parent_data_1, 761 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 762 .flags = CLK_SET_RATE_PARENT, 763 .ops = &clk_rcg2_shared_ops, 764 }, 765 }; 766 767 static struct clk_rcg2 cam_cc_csid_clk_src = { 768 .cmd_rcgr = 0x112c0, 769 .mnd_width = 0, 770 .hid_width = 5, 771 .parent_map = cam_cc_parent_map_1, 772 .freq_tbl = ftbl_cam_cc_cphy_rx_clk_src, 773 .clkr.hw.init = &(const struct clk_init_data) { 774 .name = "cam_cc_csid_clk_src", 775 .parent_data = cam_cc_parent_data_1, 776 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 777 .flags = CLK_SET_RATE_PARENT, 778 .ops = &clk_rcg2_shared_ops, 779 }, 780 }; 781 782 static const struct freq_tbl ftbl_cam_cc_fast_ahb_clk_src[] = { 783 F(213333333, P_CAM_CC_PLL6_OUT_ODD, 1.5, 0, 0), 784 F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0), 785 F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0), 786 { } 787 }; 788 789 static struct clk_rcg2 cam_cc_fast_ahb_clk_src = { 790 .cmd_rcgr = 0x100dc, 791 .mnd_width = 0, 792 .hid_width = 5, 793 .parent_map = cam_cc_parent_map_0, 794 .freq_tbl = ftbl_cam_cc_fast_ahb_clk_src, 795 .clkr.hw.init = &(const struct clk_init_data) { 796 .name = "cam_cc_fast_ahb_clk_src", 797 .parent_data = cam_cc_parent_data_0, 798 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 799 .flags = CLK_SET_RATE_PARENT, 800 .ops = &clk_rcg2_shared_ops, 801 }, 802 }; 803 804 static const struct freq_tbl ftbl_cam_cc_icp_0_clk_src[] = { 805 F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0), 806 F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), 807 F(480000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0), 808 F(600000000, P_CAM_CC_PLL0_OUT_MAIN, 2, 0, 0), 809 { } 810 }; 811 812 static struct clk_rcg2 cam_cc_icp_0_clk_src = { 813 .cmd_rcgr = 0x11214, 814 .mnd_width = 0, 815 .hid_width = 5, 816 .parent_map = cam_cc_parent_map_0, 817 .freq_tbl = ftbl_cam_cc_icp_0_clk_src, 818 .clkr.hw.init = &(const struct clk_init_data) { 819 .name = "cam_cc_icp_0_clk_src", 820 .parent_data = cam_cc_parent_data_0, 821 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 822 .flags = CLK_SET_RATE_PARENT, 823 .ops = &clk_rcg2_shared_ops, 824 }, 825 }; 826 827 static struct clk_rcg2 cam_cc_icp_1_clk_src = { 828 .cmd_rcgr = 0x1123c, 829 .mnd_width = 0, 830 .hid_width = 5, 831 .parent_map = cam_cc_parent_map_0, 832 .freq_tbl = ftbl_cam_cc_icp_0_clk_src, 833 .clkr.hw.init = &(const struct clk_init_data) { 834 .name = "cam_cc_icp_1_clk_src", 835 .parent_data = cam_cc_parent_data_0, 836 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 837 .flags = CLK_SET_RATE_PARENT, 838 .ops = &clk_rcg2_shared_ops, 839 }, 840 }; 841 842 static struct clk_rcg2 cam_cc_ife_lite_clk_src = { 843 .cmd_rcgr = 0x11150, 844 .mnd_width = 0, 845 .hid_width = 5, 846 .parent_map = cam_cc_parent_map_1, 847 .freq_tbl = ftbl_cam_cc_cphy_rx_clk_src, 848 .clkr.hw.init = &(const struct clk_init_data) { 849 .name = "cam_cc_ife_lite_clk_src", 850 .parent_data = cam_cc_parent_data_1, 851 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 852 .flags = CLK_SET_RATE_PARENT, 853 .ops = &clk_rcg2_shared_ops, 854 }, 855 }; 856 857 static struct clk_rcg2 cam_cc_ife_lite_csid_clk_src = { 858 .cmd_rcgr = 0x1117c, 859 .mnd_width = 0, 860 .hid_width = 5, 861 .parent_map = cam_cc_parent_map_1, 862 .freq_tbl = ftbl_cam_cc_cphy_rx_clk_src, 863 .clkr.hw.init = &(const struct clk_init_data) { 864 .name = "cam_cc_ife_lite_csid_clk_src", 865 .parent_data = cam_cc_parent_data_1, 866 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 867 .flags = CLK_SET_RATE_PARENT, 868 .ops = &clk_rcg2_shared_ops, 869 }, 870 }; 871 872 static const struct freq_tbl ftbl_cam_cc_ipe_nps_clk_src[] = { 873 F(332500000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), 874 F(475000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), 875 F(575000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), 876 F(675000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), 877 F(825000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), 878 { } 879 }; 880 881 static struct clk_rcg2 cam_cc_ipe_nps_clk_src = { 882 .cmd_rcgr = 0x10190, 883 .mnd_width = 0, 884 .hid_width = 5, 885 .parent_map = cam_cc_parent_map_2, 886 .freq_tbl = ftbl_cam_cc_ipe_nps_clk_src, 887 .clkr.hw.init = &(const struct clk_init_data) { 888 .name = "cam_cc_ipe_nps_clk_src", 889 .parent_data = cam_cc_parent_data_2, 890 .num_parents = ARRAY_SIZE(cam_cc_parent_data_2), 891 .flags = CLK_SET_RATE_PARENT, 892 .ops = &clk_rcg2_shared_ops, 893 }, 894 }; 895 896 static struct clk_rcg2 cam_cc_jpeg_clk_src = { 897 .cmd_rcgr = 0x111d0, 898 .mnd_width = 0, 899 .hid_width = 5, 900 .parent_map = cam_cc_parent_map_0, 901 .freq_tbl = ftbl_cam_cc_cre_clk_src, 902 .clkr.hw.init = &(const struct clk_init_data) { 903 .name = "cam_cc_jpeg_clk_src", 904 .parent_data = cam_cc_parent_data_0, 905 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 906 .flags = CLK_SET_RATE_PARENT, 907 .ops = &clk_rcg2_shared_ops, 908 }, 909 }; 910 911 static const struct freq_tbl ftbl_cam_cc_ofe_clk_src[] = { 912 F(338800000, P_CAM_CC_PLL2_OUT_EVEN, 1, 0, 0), 913 F(484000000, P_CAM_CC_PLL2_OUT_EVEN, 1, 0, 0), 914 F(586000000, P_CAM_CC_PLL2_OUT_EVEN, 1, 0, 0), 915 F(688000000, P_CAM_CC_PLL2_OUT_EVEN, 1, 0, 0), 916 F(841000000, P_CAM_CC_PLL2_OUT_EVEN, 1, 0, 0), 917 { } 918 }; 919 920 static struct clk_rcg2 cam_cc_ofe_clk_src = { 921 .cmd_rcgr = 0x1011c, 922 .mnd_width = 0, 923 .hid_width = 5, 924 .parent_map = cam_cc_parent_map_3, 925 .freq_tbl = ftbl_cam_cc_ofe_clk_src, 926 .clkr.hw.init = &(const struct clk_init_data) { 927 .name = "cam_cc_ofe_clk_src", 928 .parent_data = cam_cc_parent_data_3, 929 .num_parents = ARRAY_SIZE(cam_cc_parent_data_3), 930 .flags = CLK_SET_RATE_PARENT, 931 .ops = &clk_rcg2_shared_ops, 932 }, 933 }; 934 935 static const struct freq_tbl ftbl_cam_cc_qdss_debug_clk_src[] = { 936 F(40000000, P_CAM_CC_PLL6_OUT_ODD, 8, 0, 0), 937 F(60000000, P_CAM_CC_PLL6_OUT_EVEN, 8, 0, 0), 938 F(120000000, P_CAM_CC_PLL0_OUT_EVEN, 5, 0, 0), 939 F(240000000, P_CAM_CC_PLL0_OUT_MAIN, 5, 0, 0), 940 { } 941 }; 942 943 static struct clk_rcg2 cam_cc_qdss_debug_clk_src = { 944 .cmd_rcgr = 0x1132c, 945 .mnd_width = 0, 946 .hid_width = 5, 947 .parent_map = cam_cc_parent_map_0, 948 .freq_tbl = ftbl_cam_cc_qdss_debug_clk_src, 949 .clkr.hw.init = &(const struct clk_init_data) { 950 .name = "cam_cc_qdss_debug_clk_src", 951 .parent_data = cam_cc_parent_data_0, 952 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 953 .flags = CLK_SET_RATE_PARENT, 954 .ops = &clk_rcg2_shared_ops, 955 }, 956 }; 957 958 static const struct freq_tbl ftbl_cam_cc_sleep_clk_src[] = { 959 F(32000, P_SLEEP_CLK, 1, 0, 0), 960 { } 961 }; 962 963 static struct clk_rcg2 cam_cc_sleep_clk_src = { 964 .cmd_rcgr = 0x11380, 965 .mnd_width = 0, 966 .hid_width = 5, 967 .parent_map = cam_cc_parent_map_4, 968 .freq_tbl = ftbl_cam_cc_sleep_clk_src, 969 .clkr.hw.init = &(const struct clk_init_data) { 970 .name = "cam_cc_sleep_clk_src", 971 .parent_data = cam_cc_parent_data_4, 972 .num_parents = ARRAY_SIZE(cam_cc_parent_data_4), 973 .flags = CLK_SET_RATE_PARENT, 974 .ops = &clk_rcg2_shared_ops, 975 }, 976 }; 977 978 static const struct freq_tbl ftbl_cam_cc_slow_ahb_clk_src[] = { 979 F(56470588, P_CAM_CC_PLL6_OUT_EVEN, 8.5, 0, 0), 980 F(80000000, P_CAM_CC_PLL0_OUT_EVEN, 7.5, 0, 0), 981 { } 982 }; 983 984 static struct clk_rcg2 cam_cc_slow_ahb_clk_src = { 985 .cmd_rcgr = 0x10100, 986 .mnd_width = 0, 987 .hid_width = 5, 988 .parent_map = cam_cc_parent_map_0, 989 .freq_tbl = ftbl_cam_cc_slow_ahb_clk_src, 990 .clkr.hw.init = &(const struct clk_init_data) { 991 .name = "cam_cc_slow_ahb_clk_src", 992 .parent_data = cam_cc_parent_data_0, 993 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 994 .flags = CLK_SET_RATE_PARENT, 995 .ops = &clk_rcg2_shared_ops, 996 }, 997 }; 998 999 static const struct freq_tbl ftbl_cam_cc_tfe_0_clk_src[] = { 1000 F(360280000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), 1001 F(480000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), 1002 F(630000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), 1003 F(716000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), 1004 F(833000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), 1005 { } 1006 }; 1007 1008 static struct clk_rcg2 cam_cc_tfe_0_clk_src = { 1009 .cmd_rcgr = 0x11018, 1010 .mnd_width = 0, 1011 .hid_width = 5, 1012 .parent_map = cam_cc_parent_map_5, 1013 .freq_tbl = ftbl_cam_cc_tfe_0_clk_src, 1014 .clkr.hw.init = &(const struct clk_init_data) { 1015 .name = "cam_cc_tfe_0_clk_src", 1016 .parent_data = cam_cc_parent_data_5, 1017 .num_parents = ARRAY_SIZE(cam_cc_parent_data_5), 1018 .flags = CLK_SET_RATE_PARENT, 1019 .ops = &clk_rcg2_shared_ops, 1020 }, 1021 }; 1022 1023 static const struct freq_tbl ftbl_cam_cc_tfe_1_clk_src[] = { 1024 F(360280000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), 1025 F(480000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), 1026 F(630000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), 1027 F(716000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), 1028 F(833000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), 1029 { } 1030 }; 1031 1032 static struct clk_rcg2 cam_cc_tfe_1_clk_src = { 1033 .cmd_rcgr = 0x11098, 1034 .mnd_width = 0, 1035 .hid_width = 5, 1036 .parent_map = cam_cc_parent_map_6, 1037 .freq_tbl = ftbl_cam_cc_tfe_1_clk_src, 1038 .clkr.hw.init = &(const struct clk_init_data) { 1039 .name = "cam_cc_tfe_1_clk_src", 1040 .parent_data = cam_cc_parent_data_6, 1041 .num_parents = ARRAY_SIZE(cam_cc_parent_data_6), 1042 .flags = CLK_SET_RATE_PARENT, 1043 .ops = &clk_rcg2_shared_ops, 1044 }, 1045 }; 1046 1047 static const struct freq_tbl ftbl_cam_cc_tfe_2_clk_src[] = { 1048 F(360280000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0), 1049 F(480000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0), 1050 F(630000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0), 1051 F(716000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0), 1052 F(833000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0), 1053 { } 1054 }; 1055 1056 static struct clk_rcg2 cam_cc_tfe_2_clk_src = { 1057 .cmd_rcgr = 0x11100, 1058 .mnd_width = 0, 1059 .hid_width = 5, 1060 .parent_map = cam_cc_parent_map_7, 1061 .freq_tbl = ftbl_cam_cc_tfe_2_clk_src, 1062 .clkr.hw.init = &(const struct clk_init_data) { 1063 .name = "cam_cc_tfe_2_clk_src", 1064 .parent_data = cam_cc_parent_data_7, 1065 .num_parents = ARRAY_SIZE(cam_cc_parent_data_7), 1066 .flags = CLK_SET_RATE_PARENT, 1067 .ops = &clk_rcg2_shared_ops, 1068 }, 1069 }; 1070 1071 static const struct freq_tbl ftbl_cam_cc_xo_clk_src[] = { 1072 F(19200000, P_BI_TCXO_AO, 1, 0, 0), 1073 { } 1074 }; 1075 1076 static struct clk_rcg2 cam_cc_xo_clk_src = { 1077 .cmd_rcgr = 0x11364, 1078 .mnd_width = 0, 1079 .hid_width = 5, 1080 .parent_map = cam_cc_parent_map_8_ao, 1081 .freq_tbl = ftbl_cam_cc_xo_clk_src, 1082 .clkr.hw.init = &(const struct clk_init_data) { 1083 .name = "cam_cc_xo_clk_src", 1084 .parent_data = cam_cc_parent_data_8_ao, 1085 .num_parents = ARRAY_SIZE(cam_cc_parent_data_8_ao), 1086 .flags = CLK_SET_RATE_PARENT, 1087 .ops = &clk_rcg2_shared_ops, 1088 }, 1089 }; 1090 1091 static struct clk_branch cam_cc_cam_top_ahb_clk = { 1092 .halt_reg = 0x113ac, 1093 .halt_check = BRANCH_HALT, 1094 .clkr = { 1095 .enable_reg = 0x113ac, 1096 .enable_mask = BIT(0), 1097 .hw.init = &(const struct clk_init_data) { 1098 .name = "cam_cc_cam_top_ahb_clk", 1099 .parent_hws = (const struct clk_hw*[]) { 1100 &cam_cc_slow_ahb_clk_src.clkr.hw, 1101 }, 1102 .num_parents = 1, 1103 .flags = CLK_SET_RATE_PARENT, 1104 .ops = &clk_branch2_ops, 1105 }, 1106 }, 1107 }; 1108 1109 static struct clk_branch cam_cc_cam_top_fast_ahb_clk = { 1110 .halt_reg = 0x1139c, 1111 .halt_check = BRANCH_HALT, 1112 .clkr = { 1113 .enable_reg = 0x1139c, 1114 .enable_mask = BIT(0), 1115 .hw.init = &(const struct clk_init_data) { 1116 .name = "cam_cc_cam_top_fast_ahb_clk", 1117 .parent_hws = (const struct clk_hw*[]) { 1118 &cam_cc_fast_ahb_clk_src.clkr.hw, 1119 }, 1120 .num_parents = 1, 1121 .flags = CLK_SET_RATE_PARENT, 1122 .ops = &clk_branch2_ops, 1123 }, 1124 }, 1125 }; 1126 1127 static struct clk_branch cam_cc_camnoc_dcd_xo_clk = { 1128 .halt_reg = 0x11320, 1129 .halt_check = BRANCH_HALT, 1130 .clkr = { 1131 .enable_reg = 0x11320, 1132 .enable_mask = BIT(0), 1133 .hw.init = &(const struct clk_init_data) { 1134 .name = "cam_cc_camnoc_dcd_xo_clk", 1135 .parent_hws = (const struct clk_hw*[]) { 1136 &cam_cc_xo_clk_src.clkr.hw, 1137 }, 1138 .num_parents = 1, 1139 .flags = CLK_SET_RATE_PARENT, 1140 .ops = &clk_branch2_ops, 1141 }, 1142 }, 1143 }; 1144 1145 static struct clk_branch cam_cc_camnoc_nrt_axi_clk = { 1146 .halt_reg = 0x11310, 1147 .halt_check = BRANCH_HALT_VOTED, 1148 .hwcg_reg = 0x11310, 1149 .hwcg_bit = 1, 1150 .clkr = { 1151 .enable_reg = 0x11310, 1152 .enable_mask = BIT(0), 1153 .hw.init = &(const struct clk_init_data) { 1154 .name = "cam_cc_camnoc_nrt_axi_clk", 1155 .parent_hws = (const struct clk_hw*[]) { 1156 &cam_cc_camnoc_rt_axi_clk_src.clkr.hw, 1157 }, 1158 .num_parents = 1, 1159 .flags = CLK_SET_RATE_PARENT, 1160 .ops = &clk_branch2_ops, 1161 }, 1162 }, 1163 }; 1164 1165 static struct clk_branch cam_cc_camnoc_nrt_cre_clk = { 1166 .halt_reg = 0x111c8, 1167 .halt_check = BRANCH_HALT, 1168 .clkr = { 1169 .enable_reg = 0x111c8, 1170 .enable_mask = BIT(0), 1171 .hw.init = &(const struct clk_init_data) { 1172 .name = "cam_cc_camnoc_nrt_cre_clk", 1173 .parent_hws = (const struct clk_hw*[]) { 1174 &cam_cc_cre_clk_src.clkr.hw, 1175 }, 1176 .num_parents = 1, 1177 .flags = CLK_SET_RATE_PARENT, 1178 .ops = &clk_branch2_ops, 1179 }, 1180 }, 1181 }; 1182 1183 static struct clk_branch cam_cc_camnoc_nrt_ipe_nps_clk = { 1184 .halt_reg = 0x101b8, 1185 .halt_check = BRANCH_HALT, 1186 .clkr = { 1187 .enable_reg = 0x101b8, 1188 .enable_mask = BIT(0), 1189 .hw.init = &(const struct clk_init_data) { 1190 .name = "cam_cc_camnoc_nrt_ipe_nps_clk", 1191 .parent_hws = (const struct clk_hw*[]) { 1192 &cam_cc_ipe_nps_clk_src.clkr.hw, 1193 }, 1194 .num_parents = 1, 1195 .flags = CLK_SET_RATE_PARENT, 1196 .ops = &clk_branch2_ops, 1197 }, 1198 }, 1199 }; 1200 1201 static struct clk_branch cam_cc_camnoc_nrt_ofe_anchor_clk = { 1202 .halt_reg = 0x10158, 1203 .halt_check = BRANCH_HALT, 1204 .clkr = { 1205 .enable_reg = 0x10158, 1206 .enable_mask = BIT(0), 1207 .hw.init = &(const struct clk_init_data) { 1208 .name = "cam_cc_camnoc_nrt_ofe_anchor_clk", 1209 .parent_hws = (const struct clk_hw*[]) { 1210 &cam_cc_ofe_clk_src.clkr.hw, 1211 }, 1212 .num_parents = 1, 1213 .flags = CLK_SET_RATE_PARENT, 1214 .ops = &clk_branch2_ops, 1215 }, 1216 }, 1217 }; 1218 1219 static struct clk_branch cam_cc_camnoc_nrt_ofe_hdr_clk = { 1220 .halt_reg = 0x1016c, 1221 .halt_check = BRANCH_HALT, 1222 .clkr = { 1223 .enable_reg = 0x1016c, 1224 .enable_mask = BIT(0), 1225 .hw.init = &(const struct clk_init_data) { 1226 .name = "cam_cc_camnoc_nrt_ofe_hdr_clk", 1227 .parent_hws = (const struct clk_hw*[]) { 1228 &cam_cc_ofe_clk_src.clkr.hw, 1229 }, 1230 .num_parents = 1, 1231 .flags = CLK_SET_RATE_PARENT, 1232 .ops = &clk_branch2_ops, 1233 }, 1234 }, 1235 }; 1236 1237 static struct clk_branch cam_cc_camnoc_nrt_ofe_main_clk = { 1238 .halt_reg = 0x10144, 1239 .halt_check = BRANCH_HALT, 1240 .clkr = { 1241 .enable_reg = 0x10144, 1242 .enable_mask = BIT(0), 1243 .hw.init = &(const struct clk_init_data) { 1244 .name = "cam_cc_camnoc_nrt_ofe_main_clk", 1245 .parent_hws = (const struct clk_hw*[]) { 1246 &cam_cc_ofe_clk_src.clkr.hw, 1247 }, 1248 .num_parents = 1, 1249 .flags = CLK_SET_RATE_PARENT, 1250 .ops = &clk_branch2_ops, 1251 }, 1252 }, 1253 }; 1254 1255 static struct clk_branch cam_cc_camnoc_rt_axi_clk = { 1256 .halt_reg = 0x11300, 1257 .halt_check = BRANCH_HALT, 1258 .clkr = { 1259 .enable_reg = 0x11300, 1260 .enable_mask = BIT(0), 1261 .hw.init = &(const struct clk_init_data) { 1262 .name = "cam_cc_camnoc_rt_axi_clk", 1263 .parent_hws = (const struct clk_hw*[]) { 1264 &cam_cc_camnoc_rt_axi_clk_src.clkr.hw, 1265 }, 1266 .num_parents = 1, 1267 .flags = CLK_SET_RATE_PARENT, 1268 .ops = &clk_branch2_ops, 1269 }, 1270 }, 1271 }; 1272 1273 static struct clk_branch cam_cc_camnoc_rt_ife_lite_clk = { 1274 .halt_reg = 0x11178, 1275 .halt_check = BRANCH_HALT, 1276 .clkr = { 1277 .enable_reg = 0x11178, 1278 .enable_mask = BIT(0), 1279 .hw.init = &(const struct clk_init_data) { 1280 .name = "cam_cc_camnoc_rt_ife_lite_clk", 1281 .parent_hws = (const struct clk_hw*[]) { 1282 &cam_cc_ife_lite_clk_src.clkr.hw, 1283 }, 1284 .num_parents = 1, 1285 .flags = CLK_SET_RATE_PARENT, 1286 .ops = &clk_branch2_ops, 1287 }, 1288 }, 1289 }; 1290 1291 static struct clk_branch cam_cc_camnoc_rt_tfe_0_bayer_clk = { 1292 .halt_reg = 0x11054, 1293 .halt_check = BRANCH_HALT, 1294 .clkr = { 1295 .enable_reg = 0x11054, 1296 .enable_mask = BIT(0), 1297 .hw.init = &(const struct clk_init_data) { 1298 .name = "cam_cc_camnoc_rt_tfe_0_bayer_clk", 1299 .parent_hws = (const struct clk_hw*[]) { 1300 &cam_cc_tfe_0_clk_src.clkr.hw, 1301 }, 1302 .num_parents = 1, 1303 .flags = CLK_SET_RATE_PARENT, 1304 .ops = &clk_branch2_ops, 1305 }, 1306 }, 1307 }; 1308 1309 static struct clk_branch cam_cc_camnoc_rt_tfe_0_main_clk = { 1310 .halt_reg = 0x11040, 1311 .halt_check = BRANCH_HALT, 1312 .clkr = { 1313 .enable_reg = 0x11040, 1314 .enable_mask = BIT(0), 1315 .hw.init = &(const struct clk_init_data) { 1316 .name = "cam_cc_camnoc_rt_tfe_0_main_clk", 1317 .parent_hws = (const struct clk_hw*[]) { 1318 &cam_cc_tfe_0_clk_src.clkr.hw, 1319 }, 1320 .num_parents = 1, 1321 .flags = CLK_SET_RATE_PARENT, 1322 .ops = &clk_branch2_ops, 1323 }, 1324 }, 1325 }; 1326 1327 static struct clk_branch cam_cc_camnoc_rt_tfe_1_bayer_clk = { 1328 .halt_reg = 0x110d4, 1329 .halt_check = BRANCH_HALT, 1330 .clkr = { 1331 .enable_reg = 0x110d4, 1332 .enable_mask = BIT(0), 1333 .hw.init = &(const struct clk_init_data) { 1334 .name = "cam_cc_camnoc_rt_tfe_1_bayer_clk", 1335 .parent_hws = (const struct clk_hw*[]) { 1336 &cam_cc_tfe_1_clk_src.clkr.hw, 1337 }, 1338 .num_parents = 1, 1339 .flags = CLK_SET_RATE_PARENT, 1340 .ops = &clk_branch2_ops, 1341 }, 1342 }, 1343 }; 1344 1345 static struct clk_branch cam_cc_camnoc_rt_tfe_1_main_clk = { 1346 .halt_reg = 0x110c0, 1347 .halt_check = BRANCH_HALT, 1348 .clkr = { 1349 .enable_reg = 0x110c0, 1350 .enable_mask = BIT(0), 1351 .hw.init = &(const struct clk_init_data) { 1352 .name = "cam_cc_camnoc_rt_tfe_1_main_clk", 1353 .parent_hws = (const struct clk_hw*[]) { 1354 &cam_cc_tfe_1_clk_src.clkr.hw, 1355 }, 1356 .num_parents = 1, 1357 .flags = CLK_SET_RATE_PARENT, 1358 .ops = &clk_branch2_ops, 1359 }, 1360 }, 1361 }; 1362 1363 static struct clk_branch cam_cc_camnoc_rt_tfe_2_bayer_clk = { 1364 .halt_reg = 0x1113c, 1365 .halt_check = BRANCH_HALT, 1366 .clkr = { 1367 .enable_reg = 0x1113c, 1368 .enable_mask = BIT(0), 1369 .hw.init = &(const struct clk_init_data) { 1370 .name = "cam_cc_camnoc_rt_tfe_2_bayer_clk", 1371 .parent_hws = (const struct clk_hw*[]) { 1372 &cam_cc_tfe_2_clk_src.clkr.hw, 1373 }, 1374 .num_parents = 1, 1375 .flags = CLK_SET_RATE_PARENT, 1376 .ops = &clk_branch2_ops, 1377 }, 1378 }, 1379 }; 1380 1381 static struct clk_branch cam_cc_camnoc_rt_tfe_2_main_clk = { 1382 .halt_reg = 0x11128, 1383 .halt_check = BRANCH_HALT, 1384 .clkr = { 1385 .enable_reg = 0x11128, 1386 .enable_mask = BIT(0), 1387 .hw.init = &(const struct clk_init_data) { 1388 .name = "cam_cc_camnoc_rt_tfe_2_main_clk", 1389 .parent_hws = (const struct clk_hw*[]) { 1390 &cam_cc_tfe_2_clk_src.clkr.hw, 1391 }, 1392 .num_parents = 1, 1393 .flags = CLK_SET_RATE_PARENT, 1394 .ops = &clk_branch2_ops, 1395 }, 1396 }, 1397 }; 1398 1399 static struct clk_branch cam_cc_camnoc_xo_clk = { 1400 .halt_reg = 0x11324, 1401 .halt_check = BRANCH_HALT, 1402 .clkr = { 1403 .enable_reg = 0x11324, 1404 .enable_mask = BIT(0), 1405 .hw.init = &(const struct clk_init_data) { 1406 .name = "cam_cc_camnoc_xo_clk", 1407 .parent_hws = (const struct clk_hw*[]) { 1408 &cam_cc_xo_clk_src.clkr.hw, 1409 }, 1410 .num_parents = 1, 1411 .flags = CLK_SET_RATE_PARENT, 1412 .ops = &clk_branch2_ops, 1413 }, 1414 }, 1415 }; 1416 1417 static struct clk_branch cam_cc_cci_0_clk = { 1418 .halt_reg = 0x11284, 1419 .halt_check = BRANCH_HALT, 1420 .clkr = { 1421 .enable_reg = 0x11284, 1422 .enable_mask = BIT(0), 1423 .hw.init = &(const struct clk_init_data) { 1424 .name = "cam_cc_cci_0_clk", 1425 .parent_hws = (const struct clk_hw*[]) { 1426 &cam_cc_cci_0_clk_src.clkr.hw, 1427 }, 1428 .num_parents = 1, 1429 .flags = CLK_SET_RATE_PARENT, 1430 .ops = &clk_branch2_ops, 1431 }, 1432 }, 1433 }; 1434 1435 static struct clk_branch cam_cc_cci_1_clk = { 1436 .halt_reg = 0x112a0, 1437 .halt_check = BRANCH_HALT, 1438 .clkr = { 1439 .enable_reg = 0x112a0, 1440 .enable_mask = BIT(0), 1441 .hw.init = &(const struct clk_init_data) { 1442 .name = "cam_cc_cci_1_clk", 1443 .parent_hws = (const struct clk_hw*[]) { 1444 &cam_cc_cci_1_clk_src.clkr.hw, 1445 }, 1446 .num_parents = 1, 1447 .flags = CLK_SET_RATE_PARENT, 1448 .ops = &clk_branch2_ops, 1449 }, 1450 }, 1451 }; 1452 1453 static struct clk_branch cam_cc_cci_2_clk = { 1454 .halt_reg = 0x112bc, 1455 .halt_check = BRANCH_HALT, 1456 .clkr = { 1457 .enable_reg = 0x112bc, 1458 .enable_mask = BIT(0), 1459 .hw.init = &(const struct clk_init_data) { 1460 .name = "cam_cc_cci_2_clk", 1461 .parent_hws = (const struct clk_hw*[]) { 1462 &cam_cc_cci_2_clk_src.clkr.hw, 1463 }, 1464 .num_parents = 1, 1465 .flags = CLK_SET_RATE_PARENT, 1466 .ops = &clk_branch2_ops, 1467 }, 1468 }, 1469 }; 1470 1471 static struct clk_branch cam_cc_core_ahb_clk = { 1472 .halt_reg = 0x11360, 1473 .halt_check = BRANCH_HALT_DELAY, 1474 .clkr = { 1475 .enable_reg = 0x11360, 1476 .enable_mask = BIT(0), 1477 .hw.init = &(const struct clk_init_data) { 1478 .name = "cam_cc_core_ahb_clk", 1479 .parent_hws = (const struct clk_hw*[]) { 1480 &cam_cc_slow_ahb_clk_src.clkr.hw, 1481 }, 1482 .num_parents = 1, 1483 .flags = CLK_SET_RATE_PARENT, 1484 .ops = &clk_branch2_ops, 1485 }, 1486 }, 1487 }; 1488 1489 static struct clk_branch cam_cc_cre_ahb_clk = { 1490 .halt_reg = 0x111cc, 1491 .halt_check = BRANCH_HALT, 1492 .clkr = { 1493 .enable_reg = 0x111cc, 1494 .enable_mask = BIT(0), 1495 .hw.init = &(const struct clk_init_data) { 1496 .name = "cam_cc_cre_ahb_clk", 1497 .parent_hws = (const struct clk_hw*[]) { 1498 &cam_cc_slow_ahb_clk_src.clkr.hw, 1499 }, 1500 .num_parents = 1, 1501 .flags = CLK_SET_RATE_PARENT, 1502 .ops = &clk_branch2_ops, 1503 }, 1504 }, 1505 }; 1506 1507 static struct clk_branch cam_cc_cre_clk = { 1508 .halt_reg = 0x111c4, 1509 .halt_check = BRANCH_HALT, 1510 .clkr = { 1511 .enable_reg = 0x111c4, 1512 .enable_mask = BIT(0), 1513 .hw.init = &(const struct clk_init_data) { 1514 .name = "cam_cc_cre_clk", 1515 .parent_hws = (const struct clk_hw*[]) { 1516 &cam_cc_cre_clk_src.clkr.hw, 1517 }, 1518 .num_parents = 1, 1519 .flags = CLK_SET_RATE_PARENT, 1520 .ops = &clk_branch2_ops, 1521 }, 1522 }, 1523 }; 1524 1525 static struct clk_branch cam_cc_csi0phytimer_clk = { 1526 .halt_reg = 0x10018, 1527 .halt_check = BRANCH_HALT, 1528 .clkr = { 1529 .enable_reg = 0x10018, 1530 .enable_mask = BIT(0), 1531 .hw.init = &(const struct clk_init_data) { 1532 .name = "cam_cc_csi0phytimer_clk", 1533 .parent_hws = (const struct clk_hw*[]) { 1534 &cam_cc_csi0phytimer_clk_src.clkr.hw, 1535 }, 1536 .num_parents = 1, 1537 .flags = CLK_SET_RATE_PARENT, 1538 .ops = &clk_branch2_ops, 1539 }, 1540 }, 1541 }; 1542 1543 static struct clk_branch cam_cc_csi1phytimer_clk = { 1544 .halt_reg = 0x1003c, 1545 .halt_check = BRANCH_HALT, 1546 .clkr = { 1547 .enable_reg = 0x1003c, 1548 .enable_mask = BIT(0), 1549 .hw.init = &(const struct clk_init_data) { 1550 .name = "cam_cc_csi1phytimer_clk", 1551 .parent_hws = (const struct clk_hw*[]) { 1552 &cam_cc_csi1phytimer_clk_src.clkr.hw, 1553 }, 1554 .num_parents = 1, 1555 .flags = CLK_SET_RATE_PARENT, 1556 .ops = &clk_branch2_ops, 1557 }, 1558 }, 1559 }; 1560 1561 static struct clk_branch cam_cc_csi2phytimer_clk = { 1562 .halt_reg = 0x1005c, 1563 .halt_check = BRANCH_HALT, 1564 .clkr = { 1565 .enable_reg = 0x1005c, 1566 .enable_mask = BIT(0), 1567 .hw.init = &(const struct clk_init_data) { 1568 .name = "cam_cc_csi2phytimer_clk", 1569 .parent_hws = (const struct clk_hw*[]) { 1570 &cam_cc_csi2phytimer_clk_src.clkr.hw, 1571 }, 1572 .num_parents = 1, 1573 .flags = CLK_SET_RATE_PARENT, 1574 .ops = &clk_branch2_ops, 1575 }, 1576 }, 1577 }; 1578 1579 static struct clk_branch cam_cc_csi3phytimer_clk = { 1580 .halt_reg = 0x1007c, 1581 .halt_check = BRANCH_HALT, 1582 .clkr = { 1583 .enable_reg = 0x1007c, 1584 .enable_mask = BIT(0), 1585 .hw.init = &(const struct clk_init_data) { 1586 .name = "cam_cc_csi3phytimer_clk", 1587 .parent_hws = (const struct clk_hw*[]) { 1588 &cam_cc_csi3phytimer_clk_src.clkr.hw, 1589 }, 1590 .num_parents = 1, 1591 .flags = CLK_SET_RATE_PARENT, 1592 .ops = &clk_branch2_ops, 1593 }, 1594 }, 1595 }; 1596 1597 static struct clk_branch cam_cc_csi4phytimer_clk = { 1598 .halt_reg = 0x1009c, 1599 .halt_check = BRANCH_HALT, 1600 .clkr = { 1601 .enable_reg = 0x1009c, 1602 .enable_mask = BIT(0), 1603 .hw.init = &(const struct clk_init_data) { 1604 .name = "cam_cc_csi4phytimer_clk", 1605 .parent_hws = (const struct clk_hw*[]) { 1606 &cam_cc_csi4phytimer_clk_src.clkr.hw, 1607 }, 1608 .num_parents = 1, 1609 .flags = CLK_SET_RATE_PARENT, 1610 .ops = &clk_branch2_ops, 1611 }, 1612 }, 1613 }; 1614 1615 static struct clk_branch cam_cc_csi5phytimer_clk = { 1616 .halt_reg = 0x100bc, 1617 .halt_check = BRANCH_HALT, 1618 .clkr = { 1619 .enable_reg = 0x100bc, 1620 .enable_mask = BIT(0), 1621 .hw.init = &(const struct clk_init_data) { 1622 .name = "cam_cc_csi5phytimer_clk", 1623 .parent_hws = (const struct clk_hw*[]) { 1624 &cam_cc_csi5phytimer_clk_src.clkr.hw, 1625 }, 1626 .num_parents = 1, 1627 .flags = CLK_SET_RATE_PARENT, 1628 .ops = &clk_branch2_ops, 1629 }, 1630 }, 1631 }; 1632 1633 static struct clk_branch cam_cc_csid_clk = { 1634 .halt_reg = 0x112d8, 1635 .halt_check = BRANCH_HALT, 1636 .clkr = { 1637 .enable_reg = 0x112d8, 1638 .enable_mask = BIT(0), 1639 .hw.init = &(const struct clk_init_data) { 1640 .name = "cam_cc_csid_clk", 1641 .parent_hws = (const struct clk_hw*[]) { 1642 &cam_cc_csid_clk_src.clkr.hw, 1643 }, 1644 .num_parents = 1, 1645 .flags = CLK_SET_RATE_PARENT, 1646 .ops = &clk_branch2_ops, 1647 }, 1648 }, 1649 }; 1650 1651 static struct clk_branch cam_cc_csid_csiphy_rx_clk = { 1652 .halt_reg = 0x10020, 1653 .halt_check = BRANCH_HALT, 1654 .clkr = { 1655 .enable_reg = 0x10020, 1656 .enable_mask = BIT(0), 1657 .hw.init = &(const struct clk_init_data) { 1658 .name = "cam_cc_csid_csiphy_rx_clk", 1659 .parent_hws = (const struct clk_hw*[]) { 1660 &cam_cc_cphy_rx_clk_src.clkr.hw, 1661 }, 1662 .num_parents = 1, 1663 .flags = CLK_SET_RATE_PARENT, 1664 .ops = &clk_branch2_ops, 1665 }, 1666 }, 1667 }; 1668 1669 static struct clk_branch cam_cc_csiphy0_clk = { 1670 .halt_reg = 0x1001c, 1671 .halt_check = BRANCH_HALT, 1672 .clkr = { 1673 .enable_reg = 0x1001c, 1674 .enable_mask = BIT(0), 1675 .hw.init = &(const struct clk_init_data) { 1676 .name = "cam_cc_csiphy0_clk", 1677 .parent_hws = (const struct clk_hw*[]) { 1678 &cam_cc_cphy_rx_clk_src.clkr.hw, 1679 }, 1680 .num_parents = 1, 1681 .flags = CLK_SET_RATE_PARENT, 1682 .ops = &clk_branch2_ops, 1683 }, 1684 }, 1685 }; 1686 1687 static struct clk_branch cam_cc_csiphy1_clk = { 1688 .halt_reg = 0x10040, 1689 .halt_check = BRANCH_HALT, 1690 .clkr = { 1691 .enable_reg = 0x10040, 1692 .enable_mask = BIT(0), 1693 .hw.init = &(const struct clk_init_data) { 1694 .name = "cam_cc_csiphy1_clk", 1695 .parent_hws = (const struct clk_hw*[]) { 1696 &cam_cc_cphy_rx_clk_src.clkr.hw, 1697 }, 1698 .num_parents = 1, 1699 .flags = CLK_SET_RATE_PARENT, 1700 .ops = &clk_branch2_ops, 1701 }, 1702 }, 1703 }; 1704 1705 static struct clk_branch cam_cc_csiphy2_clk = { 1706 .halt_reg = 0x10060, 1707 .halt_check = BRANCH_HALT, 1708 .clkr = { 1709 .enable_reg = 0x10060, 1710 .enable_mask = BIT(0), 1711 .hw.init = &(const struct clk_init_data) { 1712 .name = "cam_cc_csiphy2_clk", 1713 .parent_hws = (const struct clk_hw*[]) { 1714 &cam_cc_cphy_rx_clk_src.clkr.hw, 1715 }, 1716 .num_parents = 1, 1717 .flags = CLK_SET_RATE_PARENT, 1718 .ops = &clk_branch2_ops, 1719 }, 1720 }, 1721 }; 1722 1723 static struct clk_branch cam_cc_csiphy3_clk = { 1724 .halt_reg = 0x10080, 1725 .halt_check = BRANCH_HALT, 1726 .clkr = { 1727 .enable_reg = 0x10080, 1728 .enable_mask = BIT(0), 1729 .hw.init = &(const struct clk_init_data) { 1730 .name = "cam_cc_csiphy3_clk", 1731 .parent_hws = (const struct clk_hw*[]) { 1732 &cam_cc_cphy_rx_clk_src.clkr.hw, 1733 }, 1734 .num_parents = 1, 1735 .flags = CLK_SET_RATE_PARENT, 1736 .ops = &clk_branch2_ops, 1737 }, 1738 }, 1739 }; 1740 1741 static struct clk_branch cam_cc_csiphy4_clk = { 1742 .halt_reg = 0x100a0, 1743 .halt_check = BRANCH_HALT, 1744 .clkr = { 1745 .enable_reg = 0x100a0, 1746 .enable_mask = BIT(0), 1747 .hw.init = &(const struct clk_init_data) { 1748 .name = "cam_cc_csiphy4_clk", 1749 .parent_hws = (const struct clk_hw*[]) { 1750 &cam_cc_cphy_rx_clk_src.clkr.hw, 1751 }, 1752 .num_parents = 1, 1753 .flags = CLK_SET_RATE_PARENT, 1754 .ops = &clk_branch2_ops, 1755 }, 1756 }, 1757 }; 1758 1759 static struct clk_branch cam_cc_csiphy5_clk = { 1760 .halt_reg = 0x100c0, 1761 .halt_check = BRANCH_HALT, 1762 .clkr = { 1763 .enable_reg = 0x100c0, 1764 .enable_mask = BIT(0), 1765 .hw.init = &(const struct clk_init_data) { 1766 .name = "cam_cc_csiphy5_clk", 1767 .parent_hws = (const struct clk_hw*[]) { 1768 &cam_cc_cphy_rx_clk_src.clkr.hw, 1769 }, 1770 .num_parents = 1, 1771 .flags = CLK_SET_RATE_PARENT, 1772 .ops = &clk_branch2_ops, 1773 }, 1774 }, 1775 }; 1776 1777 static struct clk_branch cam_cc_icp_0_ahb_clk = { 1778 .halt_reg = 0x11264, 1779 .halt_check = BRANCH_HALT, 1780 .clkr = { 1781 .enable_reg = 0x11264, 1782 .enable_mask = BIT(0), 1783 .hw.init = &(const struct clk_init_data) { 1784 .name = "cam_cc_icp_0_ahb_clk", 1785 .parent_hws = (const struct clk_hw*[]) { 1786 &cam_cc_slow_ahb_clk_src.clkr.hw, 1787 }, 1788 .num_parents = 1, 1789 .flags = CLK_SET_RATE_PARENT, 1790 .ops = &clk_branch2_ops, 1791 }, 1792 }, 1793 }; 1794 1795 static struct clk_branch cam_cc_icp_0_clk = { 1796 .halt_reg = 0x1122c, 1797 .halt_check = BRANCH_HALT, 1798 .clkr = { 1799 .enable_reg = 0x1122c, 1800 .enable_mask = BIT(0), 1801 .hw.init = &(const struct clk_init_data) { 1802 .name = "cam_cc_icp_0_clk", 1803 .parent_hws = (const struct clk_hw*[]) { 1804 &cam_cc_icp_0_clk_src.clkr.hw, 1805 }, 1806 .num_parents = 1, 1807 .flags = CLK_SET_RATE_PARENT, 1808 .ops = &clk_branch2_ops, 1809 }, 1810 }, 1811 }; 1812 1813 static struct clk_branch cam_cc_icp_1_ahb_clk = { 1814 .halt_reg = 0x11268, 1815 .halt_check = BRANCH_HALT, 1816 .clkr = { 1817 .enable_reg = 0x11268, 1818 .enable_mask = BIT(0), 1819 .hw.init = &(const struct clk_init_data) { 1820 .name = "cam_cc_icp_1_ahb_clk", 1821 .parent_hws = (const struct clk_hw*[]) { 1822 &cam_cc_slow_ahb_clk_src.clkr.hw, 1823 }, 1824 .num_parents = 1, 1825 .flags = CLK_SET_RATE_PARENT, 1826 .ops = &clk_branch2_ops, 1827 }, 1828 }, 1829 }; 1830 1831 static struct clk_branch cam_cc_icp_1_clk = { 1832 .halt_reg = 0x11254, 1833 .halt_check = BRANCH_HALT, 1834 .clkr = { 1835 .enable_reg = 0x11254, 1836 .enable_mask = BIT(0), 1837 .hw.init = &(const struct clk_init_data) { 1838 .name = "cam_cc_icp_1_clk", 1839 .parent_hws = (const struct clk_hw*[]) { 1840 &cam_cc_icp_1_clk_src.clkr.hw, 1841 }, 1842 .num_parents = 1, 1843 .flags = CLK_SET_RATE_PARENT, 1844 .ops = &clk_branch2_ops, 1845 }, 1846 }, 1847 }; 1848 1849 static struct clk_branch cam_cc_ife_lite_ahb_clk = { 1850 .halt_reg = 0x111a8, 1851 .halt_check = BRANCH_HALT, 1852 .clkr = { 1853 .enable_reg = 0x111a8, 1854 .enable_mask = BIT(0), 1855 .hw.init = &(const struct clk_init_data) { 1856 .name = "cam_cc_ife_lite_ahb_clk", 1857 .parent_hws = (const struct clk_hw*[]) { 1858 &cam_cc_slow_ahb_clk_src.clkr.hw, 1859 }, 1860 .num_parents = 1, 1861 .flags = CLK_SET_RATE_PARENT, 1862 .ops = &clk_branch2_ops, 1863 }, 1864 }, 1865 }; 1866 1867 static struct clk_branch cam_cc_ife_lite_clk = { 1868 .halt_reg = 0x11168, 1869 .halt_check = BRANCH_HALT, 1870 .clkr = { 1871 .enable_reg = 0x11168, 1872 .enable_mask = BIT(0), 1873 .hw.init = &(const struct clk_init_data) { 1874 .name = "cam_cc_ife_lite_clk", 1875 .parent_hws = (const struct clk_hw*[]) { 1876 &cam_cc_ife_lite_clk_src.clkr.hw, 1877 }, 1878 .num_parents = 1, 1879 .flags = CLK_SET_RATE_PARENT, 1880 .ops = &clk_branch2_ops, 1881 }, 1882 }, 1883 }; 1884 1885 static struct clk_branch cam_cc_ife_lite_cphy_rx_clk = { 1886 .halt_reg = 0x111a4, 1887 .halt_check = BRANCH_HALT, 1888 .clkr = { 1889 .enable_reg = 0x111a4, 1890 .enable_mask = BIT(0), 1891 .hw.init = &(const struct clk_init_data) { 1892 .name = "cam_cc_ife_lite_cphy_rx_clk", 1893 .parent_hws = (const struct clk_hw*[]) { 1894 &cam_cc_cphy_rx_clk_src.clkr.hw, 1895 }, 1896 .num_parents = 1, 1897 .flags = CLK_SET_RATE_PARENT, 1898 .ops = &clk_branch2_ops, 1899 }, 1900 }, 1901 }; 1902 1903 static struct clk_branch cam_cc_ife_lite_csid_clk = { 1904 .halt_reg = 0x11194, 1905 .halt_check = BRANCH_HALT, 1906 .clkr = { 1907 .enable_reg = 0x11194, 1908 .enable_mask = BIT(0), 1909 .hw.init = &(const struct clk_init_data) { 1910 .name = "cam_cc_ife_lite_csid_clk", 1911 .parent_hws = (const struct clk_hw*[]) { 1912 &cam_cc_ife_lite_csid_clk_src.clkr.hw, 1913 }, 1914 .num_parents = 1, 1915 .flags = CLK_SET_RATE_PARENT, 1916 .ops = &clk_branch2_ops, 1917 }, 1918 }, 1919 }; 1920 1921 static struct clk_branch cam_cc_ipe_nps_ahb_clk = { 1922 .halt_reg = 0x101d4, 1923 .halt_check = BRANCH_HALT, 1924 .clkr = { 1925 .enable_reg = 0x101d4, 1926 .enable_mask = BIT(0), 1927 .hw.init = &(const struct clk_init_data) { 1928 .name = "cam_cc_ipe_nps_ahb_clk", 1929 .parent_hws = (const struct clk_hw*[]) { 1930 &cam_cc_slow_ahb_clk_src.clkr.hw, 1931 }, 1932 .num_parents = 1, 1933 .flags = CLK_SET_RATE_PARENT, 1934 .ops = &clk_branch2_ops, 1935 }, 1936 }, 1937 }; 1938 1939 static struct clk_branch cam_cc_ipe_nps_clk = { 1940 .halt_reg = 0x101a8, 1941 .halt_check = BRANCH_HALT, 1942 .clkr = { 1943 .enable_reg = 0x101a8, 1944 .enable_mask = BIT(0), 1945 .hw.init = &(const struct clk_init_data) { 1946 .name = "cam_cc_ipe_nps_clk", 1947 .parent_hws = (const struct clk_hw*[]) { 1948 &cam_cc_ipe_nps_clk_src.clkr.hw, 1949 }, 1950 .num_parents = 1, 1951 .flags = CLK_SET_RATE_PARENT, 1952 .ops = &clk_branch2_ops, 1953 }, 1954 }, 1955 }; 1956 1957 static struct clk_branch cam_cc_ipe_nps_fast_ahb_clk = { 1958 .halt_reg = 0x101d8, 1959 .halt_check = BRANCH_HALT, 1960 .clkr = { 1961 .enable_reg = 0x101d8, 1962 .enable_mask = BIT(0), 1963 .hw.init = &(const struct clk_init_data) { 1964 .name = "cam_cc_ipe_nps_fast_ahb_clk", 1965 .parent_hws = (const struct clk_hw*[]) { 1966 &cam_cc_fast_ahb_clk_src.clkr.hw, 1967 }, 1968 .num_parents = 1, 1969 .flags = CLK_SET_RATE_PARENT, 1970 .ops = &clk_branch2_ops, 1971 }, 1972 }, 1973 }; 1974 1975 static struct clk_branch cam_cc_ipe_pps_clk = { 1976 .halt_reg = 0x101bc, 1977 .halt_check = BRANCH_HALT, 1978 .clkr = { 1979 .enable_reg = 0x101bc, 1980 .enable_mask = BIT(0), 1981 .hw.init = &(const struct clk_init_data) { 1982 .name = "cam_cc_ipe_pps_clk", 1983 .parent_hws = (const struct clk_hw*[]) { 1984 &cam_cc_ipe_nps_clk_src.clkr.hw, 1985 }, 1986 .num_parents = 1, 1987 .flags = CLK_SET_RATE_PARENT, 1988 .ops = &clk_branch2_ops, 1989 }, 1990 }, 1991 }; 1992 1993 static struct clk_branch cam_cc_ipe_pps_fast_ahb_clk = { 1994 .halt_reg = 0x101dc, 1995 .halt_check = BRANCH_HALT, 1996 .clkr = { 1997 .enable_reg = 0x101dc, 1998 .enable_mask = BIT(0), 1999 .hw.init = &(const struct clk_init_data) { 2000 .name = "cam_cc_ipe_pps_fast_ahb_clk", 2001 .parent_hws = (const struct clk_hw*[]) { 2002 &cam_cc_fast_ahb_clk_src.clkr.hw, 2003 }, 2004 .num_parents = 1, 2005 .flags = CLK_SET_RATE_PARENT, 2006 .ops = &clk_branch2_ops, 2007 }, 2008 }, 2009 }; 2010 2011 static struct clk_branch cam_cc_jpeg_0_clk = { 2012 .halt_reg = 0x111e8, 2013 .halt_check = BRANCH_HALT, 2014 .clkr = { 2015 .enable_reg = 0x111e8, 2016 .enable_mask = BIT(0), 2017 .hw.init = &(const struct clk_init_data) { 2018 .name = "cam_cc_jpeg_0_clk", 2019 .parent_hws = (const struct clk_hw*[]) { 2020 &cam_cc_jpeg_clk_src.clkr.hw, 2021 }, 2022 .num_parents = 1, 2023 .flags = CLK_SET_RATE_PARENT, 2024 .ops = &clk_branch2_ops, 2025 }, 2026 }, 2027 }; 2028 2029 static struct clk_branch cam_cc_jpeg_1_clk = { 2030 .halt_reg = 0x111f8, 2031 .halt_check = BRANCH_HALT, 2032 .clkr = { 2033 .enable_reg = 0x111f8, 2034 .enable_mask = BIT(0), 2035 .hw.init = &(const struct clk_init_data) { 2036 .name = "cam_cc_jpeg_1_clk", 2037 .parent_hws = (const struct clk_hw*[]) { 2038 &cam_cc_jpeg_clk_src.clkr.hw, 2039 }, 2040 .num_parents = 1, 2041 .flags = CLK_SET_RATE_PARENT, 2042 .ops = &clk_branch2_ops, 2043 }, 2044 }, 2045 }; 2046 2047 static struct clk_branch cam_cc_ofe_ahb_clk = { 2048 .halt_reg = 0x10118, 2049 .halt_check = BRANCH_HALT, 2050 .clkr = { 2051 .enable_reg = 0x10118, 2052 .enable_mask = BIT(0), 2053 .hw.init = &(const struct clk_init_data) { 2054 .name = "cam_cc_ofe_ahb_clk", 2055 .parent_hws = (const struct clk_hw*[]) { 2056 &cam_cc_slow_ahb_clk_src.clkr.hw, 2057 }, 2058 .num_parents = 1, 2059 .flags = CLK_SET_RATE_PARENT, 2060 .ops = &clk_branch2_ops, 2061 }, 2062 }, 2063 }; 2064 2065 static struct clk_branch cam_cc_ofe_anchor_clk = { 2066 .halt_reg = 0x10148, 2067 .halt_check = BRANCH_HALT, 2068 .clkr = { 2069 .enable_reg = 0x10148, 2070 .enable_mask = BIT(0), 2071 .hw.init = &(const struct clk_init_data) { 2072 .name = "cam_cc_ofe_anchor_clk", 2073 .parent_hws = (const struct clk_hw*[]) { 2074 &cam_cc_ofe_clk_src.clkr.hw, 2075 }, 2076 .num_parents = 1, 2077 .flags = CLK_SET_RATE_PARENT, 2078 .ops = &clk_branch2_ops, 2079 }, 2080 }, 2081 }; 2082 2083 static struct clk_branch cam_cc_ofe_anchor_fast_ahb_clk = { 2084 .halt_reg = 0x100f8, 2085 .halt_check = BRANCH_HALT, 2086 .clkr = { 2087 .enable_reg = 0x100f8, 2088 .enable_mask = BIT(0), 2089 .hw.init = &(const struct clk_init_data) { 2090 .name = "cam_cc_ofe_anchor_fast_ahb_clk", 2091 .parent_hws = (const struct clk_hw*[]) { 2092 &cam_cc_fast_ahb_clk_src.clkr.hw, 2093 }, 2094 .num_parents = 1, 2095 .flags = CLK_SET_RATE_PARENT, 2096 .ops = &clk_branch2_ops, 2097 }, 2098 }, 2099 }; 2100 2101 static struct clk_branch cam_cc_ofe_hdr_clk = { 2102 .halt_reg = 0x1015c, 2103 .halt_check = BRANCH_HALT, 2104 .clkr = { 2105 .enable_reg = 0x1015c, 2106 .enable_mask = BIT(0), 2107 .hw.init = &(const struct clk_init_data) { 2108 .name = "cam_cc_ofe_hdr_clk", 2109 .parent_hws = (const struct clk_hw*[]) { 2110 &cam_cc_ofe_clk_src.clkr.hw, 2111 }, 2112 .num_parents = 1, 2113 .flags = CLK_SET_RATE_PARENT, 2114 .ops = &clk_branch2_ops, 2115 }, 2116 }, 2117 }; 2118 2119 static struct clk_branch cam_cc_ofe_hdr_fast_ahb_clk = { 2120 .halt_reg = 0x100fc, 2121 .halt_check = BRANCH_HALT, 2122 .clkr = { 2123 .enable_reg = 0x100fc, 2124 .enable_mask = BIT(0), 2125 .hw.init = &(const struct clk_init_data) { 2126 .name = "cam_cc_ofe_hdr_fast_ahb_clk", 2127 .parent_hws = (const struct clk_hw*[]) { 2128 &cam_cc_fast_ahb_clk_src.clkr.hw, 2129 }, 2130 .num_parents = 1, 2131 .flags = CLK_SET_RATE_PARENT, 2132 .ops = &clk_branch2_ops, 2133 }, 2134 }, 2135 }; 2136 2137 static struct clk_branch cam_cc_ofe_main_clk = { 2138 .halt_reg = 0x10134, 2139 .halt_check = BRANCH_HALT, 2140 .clkr = { 2141 .enable_reg = 0x10134, 2142 .enable_mask = BIT(0), 2143 .hw.init = &(const struct clk_init_data) { 2144 .name = "cam_cc_ofe_main_clk", 2145 .parent_hws = (const struct clk_hw*[]) { 2146 &cam_cc_ofe_clk_src.clkr.hw, 2147 }, 2148 .num_parents = 1, 2149 .flags = CLK_SET_RATE_PARENT, 2150 .ops = &clk_branch2_ops, 2151 }, 2152 }, 2153 }; 2154 2155 static struct clk_branch cam_cc_ofe_main_fast_ahb_clk = { 2156 .halt_reg = 0x100f4, 2157 .halt_check = BRANCH_HALT, 2158 .clkr = { 2159 .enable_reg = 0x100f4, 2160 .enable_mask = BIT(0), 2161 .hw.init = &(const struct clk_init_data) { 2162 .name = "cam_cc_ofe_main_fast_ahb_clk", 2163 .parent_hws = (const struct clk_hw*[]) { 2164 &cam_cc_fast_ahb_clk_src.clkr.hw, 2165 }, 2166 .num_parents = 1, 2167 .flags = CLK_SET_RATE_PARENT, 2168 .ops = &clk_branch2_ops, 2169 }, 2170 }, 2171 }; 2172 2173 static struct clk_branch cam_cc_qdss_debug_clk = { 2174 .halt_reg = 0x11344, 2175 .halt_check = BRANCH_HALT, 2176 .clkr = { 2177 .enable_reg = 0x11344, 2178 .enable_mask = BIT(0), 2179 .hw.init = &(const struct clk_init_data) { 2180 .name = "cam_cc_qdss_debug_clk", 2181 .parent_hws = (const struct clk_hw*[]) { 2182 &cam_cc_qdss_debug_clk_src.clkr.hw, 2183 }, 2184 .num_parents = 1, 2185 .flags = CLK_SET_RATE_PARENT, 2186 .ops = &clk_branch2_ops, 2187 }, 2188 }, 2189 }; 2190 2191 static struct clk_branch cam_cc_qdss_debug_xo_clk = { 2192 .halt_reg = 0x11348, 2193 .halt_check = BRANCH_HALT, 2194 .clkr = { 2195 .enable_reg = 0x11348, 2196 .enable_mask = BIT(0), 2197 .hw.init = &(const struct clk_init_data) { 2198 .name = "cam_cc_qdss_debug_xo_clk", 2199 .parent_hws = (const struct clk_hw*[]) { 2200 &cam_cc_xo_clk_src.clkr.hw, 2201 }, 2202 .num_parents = 1, 2203 .flags = CLK_SET_RATE_PARENT, 2204 .ops = &clk_branch2_ops, 2205 }, 2206 }, 2207 }; 2208 2209 static struct clk_branch cam_cc_tfe_0_bayer_clk = { 2210 .halt_reg = 0x11044, 2211 .halt_check = BRANCH_HALT, 2212 .clkr = { 2213 .enable_reg = 0x11044, 2214 .enable_mask = BIT(0), 2215 .hw.init = &(const struct clk_init_data) { 2216 .name = "cam_cc_tfe_0_bayer_clk", 2217 .parent_hws = (const struct clk_hw*[]) { 2218 &cam_cc_tfe_0_clk_src.clkr.hw, 2219 }, 2220 .num_parents = 1, 2221 .flags = CLK_SET_RATE_PARENT, 2222 .ops = &clk_branch2_ops, 2223 }, 2224 }, 2225 }; 2226 2227 static struct clk_branch cam_cc_tfe_0_bayer_fast_ahb_clk = { 2228 .halt_reg = 0x11064, 2229 .halt_check = BRANCH_HALT, 2230 .clkr = { 2231 .enable_reg = 0x11064, 2232 .enable_mask = BIT(0), 2233 .hw.init = &(const struct clk_init_data) { 2234 .name = "cam_cc_tfe_0_bayer_fast_ahb_clk", 2235 .parent_hws = (const struct clk_hw*[]) { 2236 &cam_cc_fast_ahb_clk_src.clkr.hw, 2237 }, 2238 .num_parents = 1, 2239 .flags = CLK_SET_RATE_PARENT, 2240 .ops = &clk_branch2_ops, 2241 }, 2242 }, 2243 }; 2244 2245 static struct clk_branch cam_cc_tfe_0_main_clk = { 2246 .halt_reg = 0x11030, 2247 .halt_check = BRANCH_HALT, 2248 .clkr = { 2249 .enable_reg = 0x11030, 2250 .enable_mask = BIT(0), 2251 .hw.init = &(const struct clk_init_data) { 2252 .name = "cam_cc_tfe_0_main_clk", 2253 .parent_hws = (const struct clk_hw*[]) { 2254 &cam_cc_tfe_0_clk_src.clkr.hw, 2255 }, 2256 .num_parents = 1, 2257 .flags = CLK_SET_RATE_PARENT, 2258 .ops = &clk_branch2_ops, 2259 }, 2260 }, 2261 }; 2262 2263 static struct clk_branch cam_cc_tfe_0_main_fast_ahb_clk = { 2264 .halt_reg = 0x11060, 2265 .halt_check = BRANCH_HALT, 2266 .clkr = { 2267 .enable_reg = 0x11060, 2268 .enable_mask = BIT(0), 2269 .hw.init = &(const struct clk_init_data) { 2270 .name = "cam_cc_tfe_0_main_fast_ahb_clk", 2271 .parent_hws = (const struct clk_hw*[]) { 2272 &cam_cc_fast_ahb_clk_src.clkr.hw, 2273 }, 2274 .num_parents = 1, 2275 .flags = CLK_SET_RATE_PARENT, 2276 .ops = &clk_branch2_ops, 2277 }, 2278 }, 2279 }; 2280 2281 static struct clk_branch cam_cc_tfe_1_bayer_clk = { 2282 .halt_reg = 0x110c4, 2283 .halt_check = BRANCH_HALT, 2284 .clkr = { 2285 .enable_reg = 0x110c4, 2286 .enable_mask = BIT(0), 2287 .hw.init = &(const struct clk_init_data) { 2288 .name = "cam_cc_tfe_1_bayer_clk", 2289 .parent_hws = (const struct clk_hw*[]) { 2290 &cam_cc_tfe_1_clk_src.clkr.hw, 2291 }, 2292 .num_parents = 1, 2293 .flags = CLK_SET_RATE_PARENT, 2294 .ops = &clk_branch2_ops, 2295 }, 2296 }, 2297 }; 2298 2299 static struct clk_branch cam_cc_tfe_1_bayer_fast_ahb_clk = { 2300 .halt_reg = 0x110e4, 2301 .halt_check = BRANCH_HALT, 2302 .clkr = { 2303 .enable_reg = 0x110e4, 2304 .enable_mask = BIT(0), 2305 .hw.init = &(const struct clk_init_data) { 2306 .name = "cam_cc_tfe_1_bayer_fast_ahb_clk", 2307 .parent_hws = (const struct clk_hw*[]) { 2308 &cam_cc_fast_ahb_clk_src.clkr.hw, 2309 }, 2310 .num_parents = 1, 2311 .flags = CLK_SET_RATE_PARENT, 2312 .ops = &clk_branch2_ops, 2313 }, 2314 }, 2315 }; 2316 2317 static struct clk_branch cam_cc_tfe_1_main_clk = { 2318 .halt_reg = 0x110b0, 2319 .halt_check = BRANCH_HALT, 2320 .clkr = { 2321 .enable_reg = 0x110b0, 2322 .enable_mask = BIT(0), 2323 .hw.init = &(const struct clk_init_data) { 2324 .name = "cam_cc_tfe_1_main_clk", 2325 .parent_hws = (const struct clk_hw*[]) { 2326 &cam_cc_tfe_1_clk_src.clkr.hw, 2327 }, 2328 .num_parents = 1, 2329 .flags = CLK_SET_RATE_PARENT, 2330 .ops = &clk_branch2_ops, 2331 }, 2332 }, 2333 }; 2334 2335 static struct clk_branch cam_cc_tfe_1_main_fast_ahb_clk = { 2336 .halt_reg = 0x110e0, 2337 .halt_check = BRANCH_HALT, 2338 .clkr = { 2339 .enable_reg = 0x110e0, 2340 .enable_mask = BIT(0), 2341 .hw.init = &(const struct clk_init_data) { 2342 .name = "cam_cc_tfe_1_main_fast_ahb_clk", 2343 .parent_hws = (const struct clk_hw*[]) { 2344 &cam_cc_fast_ahb_clk_src.clkr.hw, 2345 }, 2346 .num_parents = 1, 2347 .flags = CLK_SET_RATE_PARENT, 2348 .ops = &clk_branch2_ops, 2349 }, 2350 }, 2351 }; 2352 2353 static struct clk_branch cam_cc_tfe_2_bayer_clk = { 2354 .halt_reg = 0x1112c, 2355 .halt_check = BRANCH_HALT, 2356 .clkr = { 2357 .enable_reg = 0x1112c, 2358 .enable_mask = BIT(0), 2359 .hw.init = &(const struct clk_init_data) { 2360 .name = "cam_cc_tfe_2_bayer_clk", 2361 .parent_hws = (const struct clk_hw*[]) { 2362 &cam_cc_tfe_2_clk_src.clkr.hw, 2363 }, 2364 .num_parents = 1, 2365 .flags = CLK_SET_RATE_PARENT, 2366 .ops = &clk_branch2_ops, 2367 }, 2368 }, 2369 }; 2370 2371 static struct clk_branch cam_cc_tfe_2_bayer_fast_ahb_clk = { 2372 .halt_reg = 0x1114c, 2373 .halt_check = BRANCH_HALT, 2374 .clkr = { 2375 .enable_reg = 0x1114c, 2376 .enable_mask = BIT(0), 2377 .hw.init = &(const struct clk_init_data) { 2378 .name = "cam_cc_tfe_2_bayer_fast_ahb_clk", 2379 .parent_hws = (const struct clk_hw*[]) { 2380 &cam_cc_fast_ahb_clk_src.clkr.hw, 2381 }, 2382 .num_parents = 1, 2383 .flags = CLK_SET_RATE_PARENT, 2384 .ops = &clk_branch2_ops, 2385 }, 2386 }, 2387 }; 2388 2389 static struct clk_branch cam_cc_tfe_2_main_clk = { 2390 .halt_reg = 0x11118, 2391 .halt_check = BRANCH_HALT, 2392 .clkr = { 2393 .enable_reg = 0x11118, 2394 .enable_mask = BIT(0), 2395 .hw.init = &(const struct clk_init_data) { 2396 .name = "cam_cc_tfe_2_main_clk", 2397 .parent_hws = (const struct clk_hw*[]) { 2398 &cam_cc_tfe_2_clk_src.clkr.hw, 2399 }, 2400 .num_parents = 1, 2401 .flags = CLK_SET_RATE_PARENT, 2402 .ops = &clk_branch2_ops, 2403 }, 2404 }, 2405 }; 2406 2407 static struct clk_branch cam_cc_tfe_2_main_fast_ahb_clk = { 2408 .halt_reg = 0x11148, 2409 .halt_check = BRANCH_HALT, 2410 .clkr = { 2411 .enable_reg = 0x11148, 2412 .enable_mask = BIT(0), 2413 .hw.init = &(const struct clk_init_data) { 2414 .name = "cam_cc_tfe_2_main_fast_ahb_clk", 2415 .parent_hws = (const struct clk_hw*[]) { 2416 &cam_cc_fast_ahb_clk_src.clkr.hw, 2417 }, 2418 .num_parents = 1, 2419 .flags = CLK_SET_RATE_PARENT, 2420 .ops = &clk_branch2_ops, 2421 }, 2422 }, 2423 }; 2424 2425 static struct gdsc cam_cc_titan_top_gdsc = { 2426 .gdscr = 0x1134c, 2427 .en_rest_wait_val = 0x2, 2428 .en_few_wait_val = 0x2, 2429 .clk_dis_wait_val = 0xf, 2430 .pd = { 2431 .name = "cam_cc_titan_top_gdsc", 2432 }, 2433 .pwrsts = PWRSTS_OFF_ON, 2434 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 2435 }; 2436 2437 static struct gdsc cam_cc_ipe_0_gdsc = { 2438 .gdscr = 0x1017c, 2439 .en_rest_wait_val = 0x2, 2440 .en_few_wait_val = 0x2, 2441 .clk_dis_wait_val = 0xf, 2442 .pd = { 2443 .name = "cam_cc_ipe_0_gdsc", 2444 }, 2445 .pwrsts = PWRSTS_OFF_ON, 2446 .parent = &cam_cc_titan_top_gdsc.pd, 2447 .flags = HW_CTRL_TRIGGER | POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 2448 }; 2449 2450 static struct gdsc cam_cc_ofe_gdsc = { 2451 .gdscr = 0x100c8, 2452 .en_rest_wait_val = 0x2, 2453 .en_few_wait_val = 0x2, 2454 .clk_dis_wait_val = 0xf, 2455 .pd = { 2456 .name = "cam_cc_ofe_gdsc", 2457 }, 2458 .pwrsts = PWRSTS_OFF_ON, 2459 .parent = &cam_cc_titan_top_gdsc.pd, 2460 .flags = HW_CTRL_TRIGGER | POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 2461 }; 2462 2463 static struct gdsc cam_cc_tfe_0_gdsc = { 2464 .gdscr = 0x11004, 2465 .en_rest_wait_val = 0x2, 2466 .en_few_wait_val = 0x2, 2467 .clk_dis_wait_val = 0xf, 2468 .pd = { 2469 .name = "cam_cc_tfe_0_gdsc", 2470 }, 2471 .pwrsts = PWRSTS_OFF_ON, 2472 .parent = &cam_cc_titan_top_gdsc.pd, 2473 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 2474 }; 2475 2476 static struct gdsc cam_cc_tfe_1_gdsc = { 2477 .gdscr = 0x11084, 2478 .en_rest_wait_val = 0x2, 2479 .en_few_wait_val = 0x2, 2480 .clk_dis_wait_val = 0xf, 2481 .pd = { 2482 .name = "cam_cc_tfe_1_gdsc", 2483 }, 2484 .pwrsts = PWRSTS_OFF_ON, 2485 .parent = &cam_cc_titan_top_gdsc.pd, 2486 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 2487 }; 2488 2489 static struct gdsc cam_cc_tfe_2_gdsc = { 2490 .gdscr = 0x110ec, 2491 .en_rest_wait_val = 0x2, 2492 .en_few_wait_val = 0x2, 2493 .clk_dis_wait_val = 0xf, 2494 .pd = { 2495 .name = "cam_cc_tfe_2_gdsc", 2496 }, 2497 .pwrsts = PWRSTS_OFF_ON, 2498 .parent = &cam_cc_titan_top_gdsc.pd, 2499 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 2500 }; 2501 2502 static struct clk_regmap *cam_cc_sm8750_clocks[] = { 2503 [CAM_CC_CAM_TOP_AHB_CLK] = &cam_cc_cam_top_ahb_clk.clkr, 2504 [CAM_CC_CAM_TOP_FAST_AHB_CLK] = &cam_cc_cam_top_fast_ahb_clk.clkr, 2505 [CAM_CC_CAMNOC_DCD_XO_CLK] = &cam_cc_camnoc_dcd_xo_clk.clkr, 2506 [CAM_CC_CAMNOC_NRT_AXI_CLK] = &cam_cc_camnoc_nrt_axi_clk.clkr, 2507 [CAM_CC_CAMNOC_NRT_CRE_CLK] = &cam_cc_camnoc_nrt_cre_clk.clkr, 2508 [CAM_CC_CAMNOC_NRT_IPE_NPS_CLK] = &cam_cc_camnoc_nrt_ipe_nps_clk.clkr, 2509 [CAM_CC_CAMNOC_NRT_OFE_ANCHOR_CLK] = &cam_cc_camnoc_nrt_ofe_anchor_clk.clkr, 2510 [CAM_CC_CAMNOC_NRT_OFE_HDR_CLK] = &cam_cc_camnoc_nrt_ofe_hdr_clk.clkr, 2511 [CAM_CC_CAMNOC_NRT_OFE_MAIN_CLK] = &cam_cc_camnoc_nrt_ofe_main_clk.clkr, 2512 [CAM_CC_CAMNOC_RT_AXI_CLK] = &cam_cc_camnoc_rt_axi_clk.clkr, 2513 [CAM_CC_CAMNOC_RT_AXI_CLK_SRC] = &cam_cc_camnoc_rt_axi_clk_src.clkr, 2514 [CAM_CC_CAMNOC_RT_IFE_LITE_CLK] = &cam_cc_camnoc_rt_ife_lite_clk.clkr, 2515 [CAM_CC_CAMNOC_RT_TFE_0_BAYER_CLK] = &cam_cc_camnoc_rt_tfe_0_bayer_clk.clkr, 2516 [CAM_CC_CAMNOC_RT_TFE_0_MAIN_CLK] = &cam_cc_camnoc_rt_tfe_0_main_clk.clkr, 2517 [CAM_CC_CAMNOC_RT_TFE_1_BAYER_CLK] = &cam_cc_camnoc_rt_tfe_1_bayer_clk.clkr, 2518 [CAM_CC_CAMNOC_RT_TFE_1_MAIN_CLK] = &cam_cc_camnoc_rt_tfe_1_main_clk.clkr, 2519 [CAM_CC_CAMNOC_RT_TFE_2_BAYER_CLK] = &cam_cc_camnoc_rt_tfe_2_bayer_clk.clkr, 2520 [CAM_CC_CAMNOC_RT_TFE_2_MAIN_CLK] = &cam_cc_camnoc_rt_tfe_2_main_clk.clkr, 2521 [CAM_CC_CAMNOC_XO_CLK] = &cam_cc_camnoc_xo_clk.clkr, 2522 [CAM_CC_CCI_0_CLK] = &cam_cc_cci_0_clk.clkr, 2523 [CAM_CC_CCI_0_CLK_SRC] = &cam_cc_cci_0_clk_src.clkr, 2524 [CAM_CC_CCI_1_CLK] = &cam_cc_cci_1_clk.clkr, 2525 [CAM_CC_CCI_1_CLK_SRC] = &cam_cc_cci_1_clk_src.clkr, 2526 [CAM_CC_CCI_2_CLK] = &cam_cc_cci_2_clk.clkr, 2527 [CAM_CC_CCI_2_CLK_SRC] = &cam_cc_cci_2_clk_src.clkr, 2528 [CAM_CC_CORE_AHB_CLK] = &cam_cc_core_ahb_clk.clkr, 2529 [CAM_CC_CPHY_RX_CLK_SRC] = &cam_cc_cphy_rx_clk_src.clkr, 2530 [CAM_CC_CRE_AHB_CLK] = &cam_cc_cre_ahb_clk.clkr, 2531 [CAM_CC_CRE_CLK] = &cam_cc_cre_clk.clkr, 2532 [CAM_CC_CRE_CLK_SRC] = &cam_cc_cre_clk_src.clkr, 2533 [CAM_CC_CSI0PHYTIMER_CLK] = &cam_cc_csi0phytimer_clk.clkr, 2534 [CAM_CC_CSI0PHYTIMER_CLK_SRC] = &cam_cc_csi0phytimer_clk_src.clkr, 2535 [CAM_CC_CSI1PHYTIMER_CLK] = &cam_cc_csi1phytimer_clk.clkr, 2536 [CAM_CC_CSI1PHYTIMER_CLK_SRC] = &cam_cc_csi1phytimer_clk_src.clkr, 2537 [CAM_CC_CSI2PHYTIMER_CLK] = &cam_cc_csi2phytimer_clk.clkr, 2538 [CAM_CC_CSI2PHYTIMER_CLK_SRC] = &cam_cc_csi2phytimer_clk_src.clkr, 2539 [CAM_CC_CSI3PHYTIMER_CLK] = &cam_cc_csi3phytimer_clk.clkr, 2540 [CAM_CC_CSI3PHYTIMER_CLK_SRC] = &cam_cc_csi3phytimer_clk_src.clkr, 2541 [CAM_CC_CSI4PHYTIMER_CLK] = &cam_cc_csi4phytimer_clk.clkr, 2542 [CAM_CC_CSI4PHYTIMER_CLK_SRC] = &cam_cc_csi4phytimer_clk_src.clkr, 2543 [CAM_CC_CSI5PHYTIMER_CLK] = &cam_cc_csi5phytimer_clk.clkr, 2544 [CAM_CC_CSI5PHYTIMER_CLK_SRC] = &cam_cc_csi5phytimer_clk_src.clkr, 2545 [CAM_CC_CSID_CLK] = &cam_cc_csid_clk.clkr, 2546 [CAM_CC_CSID_CLK_SRC] = &cam_cc_csid_clk_src.clkr, 2547 [CAM_CC_CSID_CSIPHY_RX_CLK] = &cam_cc_csid_csiphy_rx_clk.clkr, 2548 [CAM_CC_CSIPHY0_CLK] = &cam_cc_csiphy0_clk.clkr, 2549 [CAM_CC_CSIPHY1_CLK] = &cam_cc_csiphy1_clk.clkr, 2550 [CAM_CC_CSIPHY2_CLK] = &cam_cc_csiphy2_clk.clkr, 2551 [CAM_CC_CSIPHY3_CLK] = &cam_cc_csiphy3_clk.clkr, 2552 [CAM_CC_CSIPHY4_CLK] = &cam_cc_csiphy4_clk.clkr, 2553 [CAM_CC_CSIPHY5_CLK] = &cam_cc_csiphy5_clk.clkr, 2554 [CAM_CC_FAST_AHB_CLK_SRC] = &cam_cc_fast_ahb_clk_src.clkr, 2555 [CAM_CC_ICP_0_AHB_CLK] = &cam_cc_icp_0_ahb_clk.clkr, 2556 [CAM_CC_ICP_0_CLK] = &cam_cc_icp_0_clk.clkr, 2557 [CAM_CC_ICP_0_CLK_SRC] = &cam_cc_icp_0_clk_src.clkr, 2558 [CAM_CC_ICP_1_AHB_CLK] = &cam_cc_icp_1_ahb_clk.clkr, 2559 [CAM_CC_ICP_1_CLK] = &cam_cc_icp_1_clk.clkr, 2560 [CAM_CC_ICP_1_CLK_SRC] = &cam_cc_icp_1_clk_src.clkr, 2561 [CAM_CC_IFE_LITE_AHB_CLK] = &cam_cc_ife_lite_ahb_clk.clkr, 2562 [CAM_CC_IFE_LITE_CLK] = &cam_cc_ife_lite_clk.clkr, 2563 [CAM_CC_IFE_LITE_CLK_SRC] = &cam_cc_ife_lite_clk_src.clkr, 2564 [CAM_CC_IFE_LITE_CPHY_RX_CLK] = &cam_cc_ife_lite_cphy_rx_clk.clkr, 2565 [CAM_CC_IFE_LITE_CSID_CLK] = &cam_cc_ife_lite_csid_clk.clkr, 2566 [CAM_CC_IFE_LITE_CSID_CLK_SRC] = &cam_cc_ife_lite_csid_clk_src.clkr, 2567 [CAM_CC_IPE_NPS_AHB_CLK] = &cam_cc_ipe_nps_ahb_clk.clkr, 2568 [CAM_CC_IPE_NPS_CLK] = &cam_cc_ipe_nps_clk.clkr, 2569 [CAM_CC_IPE_NPS_CLK_SRC] = &cam_cc_ipe_nps_clk_src.clkr, 2570 [CAM_CC_IPE_NPS_FAST_AHB_CLK] = &cam_cc_ipe_nps_fast_ahb_clk.clkr, 2571 [CAM_CC_IPE_PPS_CLK] = &cam_cc_ipe_pps_clk.clkr, 2572 [CAM_CC_IPE_PPS_FAST_AHB_CLK] = &cam_cc_ipe_pps_fast_ahb_clk.clkr, 2573 [CAM_CC_JPEG_0_CLK] = &cam_cc_jpeg_0_clk.clkr, 2574 [CAM_CC_JPEG_1_CLK] = &cam_cc_jpeg_1_clk.clkr, 2575 [CAM_CC_JPEG_CLK_SRC] = &cam_cc_jpeg_clk_src.clkr, 2576 [CAM_CC_OFE_AHB_CLK] = &cam_cc_ofe_ahb_clk.clkr, 2577 [CAM_CC_OFE_ANCHOR_CLK] = &cam_cc_ofe_anchor_clk.clkr, 2578 [CAM_CC_OFE_ANCHOR_FAST_AHB_CLK] = &cam_cc_ofe_anchor_fast_ahb_clk.clkr, 2579 [CAM_CC_OFE_CLK_SRC] = &cam_cc_ofe_clk_src.clkr, 2580 [CAM_CC_OFE_HDR_CLK] = &cam_cc_ofe_hdr_clk.clkr, 2581 [CAM_CC_OFE_HDR_FAST_AHB_CLK] = &cam_cc_ofe_hdr_fast_ahb_clk.clkr, 2582 [CAM_CC_OFE_MAIN_CLK] = &cam_cc_ofe_main_clk.clkr, 2583 [CAM_CC_OFE_MAIN_FAST_AHB_CLK] = &cam_cc_ofe_main_fast_ahb_clk.clkr, 2584 [CAM_CC_PLL0] = &cam_cc_pll0.clkr, 2585 [CAM_CC_PLL0_OUT_EVEN] = &cam_cc_pll0_out_even.clkr, 2586 [CAM_CC_PLL0_OUT_ODD] = &cam_cc_pll0_out_odd.clkr, 2587 [CAM_CC_PLL1] = &cam_cc_pll1.clkr, 2588 [CAM_CC_PLL1_OUT_EVEN] = &cam_cc_pll1_out_even.clkr, 2589 [CAM_CC_PLL2] = &cam_cc_pll2.clkr, 2590 [CAM_CC_PLL2_OUT_EVEN] = &cam_cc_pll2_out_even.clkr, 2591 [CAM_CC_PLL3] = &cam_cc_pll3.clkr, 2592 [CAM_CC_PLL3_OUT_EVEN] = &cam_cc_pll3_out_even.clkr, 2593 [CAM_CC_PLL4] = &cam_cc_pll4.clkr, 2594 [CAM_CC_PLL4_OUT_EVEN] = &cam_cc_pll4_out_even.clkr, 2595 [CAM_CC_PLL5] = &cam_cc_pll5.clkr, 2596 [CAM_CC_PLL5_OUT_EVEN] = &cam_cc_pll5_out_even.clkr, 2597 [CAM_CC_PLL6] = &cam_cc_pll6.clkr, 2598 [CAM_CC_PLL6_OUT_EVEN] = &cam_cc_pll6_out_even.clkr, 2599 [CAM_CC_PLL6_OUT_ODD] = &cam_cc_pll6_out_odd.clkr, 2600 [CAM_CC_QDSS_DEBUG_CLK] = &cam_cc_qdss_debug_clk.clkr, 2601 [CAM_CC_QDSS_DEBUG_CLK_SRC] = &cam_cc_qdss_debug_clk_src.clkr, 2602 [CAM_CC_QDSS_DEBUG_XO_CLK] = &cam_cc_qdss_debug_xo_clk.clkr, 2603 [CAM_CC_SLEEP_CLK_SRC] = &cam_cc_sleep_clk_src.clkr, 2604 [CAM_CC_SLOW_AHB_CLK_SRC] = &cam_cc_slow_ahb_clk_src.clkr, 2605 [CAM_CC_TFE_0_BAYER_CLK] = &cam_cc_tfe_0_bayer_clk.clkr, 2606 [CAM_CC_TFE_0_BAYER_FAST_AHB_CLK] = &cam_cc_tfe_0_bayer_fast_ahb_clk.clkr, 2607 [CAM_CC_TFE_0_CLK_SRC] = &cam_cc_tfe_0_clk_src.clkr, 2608 [CAM_CC_TFE_0_MAIN_CLK] = &cam_cc_tfe_0_main_clk.clkr, 2609 [CAM_CC_TFE_0_MAIN_FAST_AHB_CLK] = &cam_cc_tfe_0_main_fast_ahb_clk.clkr, 2610 [CAM_CC_TFE_1_BAYER_CLK] = &cam_cc_tfe_1_bayer_clk.clkr, 2611 [CAM_CC_TFE_1_BAYER_FAST_AHB_CLK] = &cam_cc_tfe_1_bayer_fast_ahb_clk.clkr, 2612 [CAM_CC_TFE_1_CLK_SRC] = &cam_cc_tfe_1_clk_src.clkr, 2613 [CAM_CC_TFE_1_MAIN_CLK] = &cam_cc_tfe_1_main_clk.clkr, 2614 [CAM_CC_TFE_1_MAIN_FAST_AHB_CLK] = &cam_cc_tfe_1_main_fast_ahb_clk.clkr, 2615 [CAM_CC_TFE_2_BAYER_CLK] = &cam_cc_tfe_2_bayer_clk.clkr, 2616 [CAM_CC_TFE_2_BAYER_FAST_AHB_CLK] = &cam_cc_tfe_2_bayer_fast_ahb_clk.clkr, 2617 [CAM_CC_TFE_2_CLK_SRC] = &cam_cc_tfe_2_clk_src.clkr, 2618 [CAM_CC_TFE_2_MAIN_CLK] = &cam_cc_tfe_2_main_clk.clkr, 2619 [CAM_CC_TFE_2_MAIN_FAST_AHB_CLK] = &cam_cc_tfe_2_main_fast_ahb_clk.clkr, 2620 [CAM_CC_XO_CLK_SRC] = &cam_cc_xo_clk_src.clkr, 2621 }; 2622 2623 static struct gdsc *cam_cc_sm8750_gdscs[] = { 2624 [CAM_CC_TITAN_TOP_GDSC] = &cam_cc_titan_top_gdsc, 2625 [CAM_CC_IPE_0_GDSC] = &cam_cc_ipe_0_gdsc, 2626 [CAM_CC_OFE_GDSC] = &cam_cc_ofe_gdsc, 2627 [CAM_CC_TFE_0_GDSC] = &cam_cc_tfe_0_gdsc, 2628 [CAM_CC_TFE_1_GDSC] = &cam_cc_tfe_1_gdsc, 2629 [CAM_CC_TFE_2_GDSC] = &cam_cc_tfe_2_gdsc, 2630 }; 2631 2632 static const struct qcom_reset_map cam_cc_sm8750_resets[] = { 2633 [CAM_CC_DRV_BCR] = { 0x113bc }, 2634 [CAM_CC_ICP_BCR] = { 0x11210 }, 2635 [CAM_CC_IPE_0_BCR] = { 0x10178 }, 2636 [CAM_CC_OFE_BCR] = { 0x100c4 }, 2637 [CAM_CC_QDSS_DEBUG_BCR] = { 0x11328 }, 2638 [CAM_CC_TFE_0_BCR] = { 0x11000 }, 2639 [CAM_CC_TFE_1_BCR] = { 0x11080 }, 2640 [CAM_CC_TFE_2_BCR] = { 0x110e8 }, 2641 }; 2642 2643 static struct clk_alpha_pll *cam_cc_sm8750_plls[] = { 2644 &cam_cc_pll0, 2645 &cam_cc_pll1, 2646 &cam_cc_pll2, 2647 &cam_cc_pll3, 2648 &cam_cc_pll4, 2649 &cam_cc_pll5, 2650 &cam_cc_pll6, 2651 }; 2652 2653 static const u32 cam_cc_sm8750_critical_cbcrs[] = { 2654 0x113c4, /* CAM_CC_DRV_AHB_CLK */ 2655 0x113c0, /* CAM_CC_DRV_XO_CLK */ 2656 0x1137c, /* CAM_CC_GDSC_CLK */ 2657 0x11398, /* CAM_CC_SLEEP_CLK */ 2658 }; 2659 2660 static const struct regmap_config cam_cc_sm8750_regmap_config = { 2661 .reg_bits = 32, 2662 .reg_stride = 4, 2663 .val_bits = 32, 2664 .max_register = 0x1601c, 2665 .fast_io = true, 2666 }; 2667 2668 static const struct qcom_cc_driver_data cam_cc_sm8750_driver_data = { 2669 .alpha_plls = cam_cc_sm8750_plls, 2670 .num_alpha_plls = ARRAY_SIZE(cam_cc_sm8750_plls), 2671 .clk_cbcrs = cam_cc_sm8750_critical_cbcrs, 2672 .num_clk_cbcrs = ARRAY_SIZE(cam_cc_sm8750_critical_cbcrs), 2673 }; 2674 2675 static const struct qcom_cc_desc cam_cc_sm8750_desc = { 2676 .config = &cam_cc_sm8750_regmap_config, 2677 .clks = cam_cc_sm8750_clocks, 2678 .num_clks = ARRAY_SIZE(cam_cc_sm8750_clocks), 2679 .resets = cam_cc_sm8750_resets, 2680 .num_resets = ARRAY_SIZE(cam_cc_sm8750_resets), 2681 .gdscs = cam_cc_sm8750_gdscs, 2682 .num_gdscs = ARRAY_SIZE(cam_cc_sm8750_gdscs), 2683 .use_rpm = true, 2684 .driver_data = &cam_cc_sm8750_driver_data, 2685 }; 2686 2687 static const struct of_device_id cam_cc_sm8750_match_table[] = { 2688 { .compatible = "qcom,sm8750-camcc" }, 2689 { } 2690 }; 2691 MODULE_DEVICE_TABLE(of, cam_cc_sm8750_match_table); 2692 2693 static int cam_cc_sm8750_probe(struct platform_device *pdev) 2694 { 2695 return qcom_cc_probe(pdev, &cam_cc_sm8750_desc); 2696 } 2697 2698 static struct platform_driver cam_cc_sm8750_driver = { 2699 .probe = cam_cc_sm8750_probe, 2700 .driver = { 2701 .name = "camcc-sm8750", 2702 .of_match_table = cam_cc_sm8750_match_table, 2703 }, 2704 }; 2705 2706 module_platform_driver(cam_cc_sm8750_driver); 2707 2708 MODULE_DESCRIPTION("QTI CAMCC SM8750 Driver"); 2709 MODULE_LICENSE("GPL"); 2710