1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 4 */ 5 6 #include <linux/clk-provider.h> 7 #include <linux/mod_devicetable.h> 8 #include <linux/module.h> 9 #include <linux/platform_device.h> 10 #include <linux/regmap.h> 11 12 #include <dt-bindings/clock/qcom,sm8750-camcc.h> 13 14 #include "clk-alpha-pll.h" 15 #include "clk-branch.h" 16 #include "clk-rcg.h" 17 #include "clk-regmap.h" 18 #include "common.h" 19 #include "gdsc.h" 20 #include "reset.h" 21 22 enum { 23 DT_IFACE, 24 DT_BI_TCXO, 25 DT_BI_TCXO_AO, 26 DT_SLEEP_CLK, 27 }; 28 29 enum { 30 P_BI_TCXO, 31 P_BI_TCXO_AO, 32 P_CAM_CC_PLL0_OUT_EVEN, 33 P_CAM_CC_PLL0_OUT_MAIN, 34 P_CAM_CC_PLL0_OUT_ODD, 35 P_CAM_CC_PLL1_OUT_EVEN, 36 P_CAM_CC_PLL2_OUT_EVEN, 37 P_CAM_CC_PLL3_OUT_EVEN, 38 P_CAM_CC_PLL4_OUT_EVEN, 39 P_CAM_CC_PLL5_OUT_EVEN, 40 P_CAM_CC_PLL6_OUT_EVEN, 41 P_CAM_CC_PLL6_OUT_ODD, 42 P_SLEEP_CLK, 43 }; 44 45 static const struct pll_vco taycan_elu_vco[] = { 46 { 249600000, 2500000000, 0 }, 47 }; 48 49 static const struct alpha_pll_config cam_cc_pll0_config = { 50 .l = 0x3e, 51 .alpha = 0x8000, 52 .config_ctl_val = 0x19660387, 53 .config_ctl_hi_val = 0x098060a0, 54 .config_ctl_hi1_val = 0xb416cb20, 55 .user_ctl_val = 0x00008400, 56 .user_ctl_hi_val = 0x00000002, 57 }; 58 59 static struct clk_alpha_pll cam_cc_pll0 = { 60 .offset = 0x0, 61 .config = &cam_cc_pll0_config, 62 .vco_table = taycan_elu_vco, 63 .num_vco = ARRAY_SIZE(taycan_elu_vco), 64 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_ELU], 65 .clkr = { 66 .hw.init = &(const struct clk_init_data) { 67 .name = "cam_cc_pll0", 68 .parent_data = &(const struct clk_parent_data) { 69 .index = DT_BI_TCXO, 70 }, 71 .num_parents = 1, 72 .ops = &clk_alpha_pll_taycan_elu_ops, 73 }, 74 }, 75 }; 76 77 static const struct clk_div_table post_div_table_cam_cc_pll0_out_even[] = { 78 { 0x1, 2 }, 79 { } 80 }; 81 82 static struct clk_alpha_pll_postdiv cam_cc_pll0_out_even = { 83 .offset = 0x0, 84 .post_div_shift = 10, 85 .post_div_table = post_div_table_cam_cc_pll0_out_even, 86 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll0_out_even), 87 .width = 4, 88 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_ELU], 89 .clkr.hw.init = &(const struct clk_init_data) { 90 .name = "cam_cc_pll0_out_even", 91 .parent_hws = (const struct clk_hw*[]) { 92 &cam_cc_pll0.clkr.hw, 93 }, 94 .num_parents = 1, 95 .flags = CLK_SET_RATE_PARENT, 96 .ops = &clk_alpha_pll_postdiv_taycan_elu_ops, 97 }, 98 }; 99 100 static const struct clk_div_table post_div_table_cam_cc_pll0_out_odd[] = { 101 { 0x2, 3 }, 102 { } 103 }; 104 105 static struct clk_alpha_pll_postdiv cam_cc_pll0_out_odd = { 106 .offset = 0x0, 107 .post_div_shift = 14, 108 .post_div_table = post_div_table_cam_cc_pll0_out_odd, 109 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll0_out_odd), 110 .width = 4, 111 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_ELU], 112 .clkr.hw.init = &(const struct clk_init_data) { 113 .name = "cam_cc_pll0_out_odd", 114 .parent_hws = (const struct clk_hw*[]) { 115 &cam_cc_pll0.clkr.hw, 116 }, 117 .num_parents = 1, 118 .flags = CLK_SET_RATE_PARENT, 119 .ops = &clk_alpha_pll_postdiv_taycan_elu_ops, 120 }, 121 }; 122 123 static const struct alpha_pll_config cam_cc_pll1_config = { 124 .l = 0x22, 125 .alpha = 0xa2aa, 126 .config_ctl_val = 0x19660387, 127 .config_ctl_hi_val = 0x098060a0, 128 .config_ctl_hi1_val = 0xb416cb20, 129 .user_ctl_val = 0x00000400, 130 .user_ctl_hi_val = 0x00000002, 131 }; 132 133 static struct clk_alpha_pll cam_cc_pll1 = { 134 .offset = 0x1000, 135 .config = &cam_cc_pll1_config, 136 .vco_table = taycan_elu_vco, 137 .num_vco = ARRAY_SIZE(taycan_elu_vco), 138 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_ELU], 139 .clkr = { 140 .hw.init = &(const struct clk_init_data) { 141 .name = "cam_cc_pll1", 142 .parent_data = &(const struct clk_parent_data) { 143 .index = DT_BI_TCXO, 144 }, 145 .num_parents = 1, 146 .ops = &clk_alpha_pll_taycan_elu_ops, 147 }, 148 }, 149 }; 150 151 static const struct clk_div_table post_div_table_cam_cc_pll1_out_even[] = { 152 { 0x1, 2 }, 153 { } 154 }; 155 156 static struct clk_alpha_pll_postdiv cam_cc_pll1_out_even = { 157 .offset = 0x1000, 158 .post_div_shift = 10, 159 .post_div_table = post_div_table_cam_cc_pll1_out_even, 160 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll1_out_even), 161 .width = 4, 162 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_ELU], 163 .clkr.hw.init = &(const struct clk_init_data) { 164 .name = "cam_cc_pll1_out_even", 165 .parent_hws = (const struct clk_hw*[]) { 166 &cam_cc_pll1.clkr.hw, 167 }, 168 .num_parents = 1, 169 .flags = CLK_SET_RATE_PARENT, 170 .ops = &clk_alpha_pll_postdiv_taycan_elu_ops, 171 }, 172 }; 173 174 static const struct alpha_pll_config cam_cc_pll2_config = { 175 .l = 0x23, 176 .alpha = 0x4aaa, 177 .config_ctl_val = 0x19660387, 178 .config_ctl_hi_val = 0x098060a0, 179 .config_ctl_hi1_val = 0xb416cb20, 180 .user_ctl_val = 0x00000400, 181 .user_ctl_hi_val = 0x00000002, 182 }; 183 184 static struct clk_alpha_pll cam_cc_pll2 = { 185 .offset = 0x2000, 186 .config = &cam_cc_pll2_config, 187 .vco_table = taycan_elu_vco, 188 .num_vco = ARRAY_SIZE(taycan_elu_vco), 189 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_ELU], 190 .clkr = { 191 .hw.init = &(const struct clk_init_data) { 192 .name = "cam_cc_pll2", 193 .parent_data = &(const struct clk_parent_data) { 194 .index = DT_BI_TCXO, 195 }, 196 .num_parents = 1, 197 .ops = &clk_alpha_pll_taycan_elu_ops, 198 }, 199 }, 200 }; 201 202 static const struct clk_div_table post_div_table_cam_cc_pll2_out_even[] = { 203 { 0x1, 2 }, 204 { } 205 }; 206 207 static struct clk_alpha_pll_postdiv cam_cc_pll2_out_even = { 208 .offset = 0x2000, 209 .post_div_shift = 10, 210 .post_div_table = post_div_table_cam_cc_pll2_out_even, 211 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll2_out_even), 212 .width = 4, 213 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_ELU], 214 .clkr.hw.init = &(const struct clk_init_data) { 215 .name = "cam_cc_pll2_out_even", 216 .parent_hws = (const struct clk_hw*[]) { 217 &cam_cc_pll2.clkr.hw, 218 }, 219 .num_parents = 1, 220 .flags = CLK_SET_RATE_PARENT, 221 .ops = &clk_alpha_pll_postdiv_taycan_elu_ops, 222 }, 223 }; 224 225 static const struct alpha_pll_config cam_cc_pll3_config = { 226 .l = 0x25, 227 .alpha = 0x8777, 228 .config_ctl_val = 0x19660387, 229 .config_ctl_hi_val = 0x098060a0, 230 .config_ctl_hi1_val = 0xb416cb20, 231 .user_ctl_val = 0x00000400, 232 .user_ctl_hi_val = 0x00000002, 233 }; 234 235 static struct clk_alpha_pll cam_cc_pll3 = { 236 .offset = 0x3000, 237 .config = &cam_cc_pll3_config, 238 .vco_table = taycan_elu_vco, 239 .num_vco = ARRAY_SIZE(taycan_elu_vco), 240 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_ELU], 241 .clkr = { 242 .hw.init = &(const struct clk_init_data) { 243 .name = "cam_cc_pll3", 244 .parent_data = &(const struct clk_parent_data) { 245 .index = DT_BI_TCXO, 246 }, 247 .num_parents = 1, 248 .ops = &clk_alpha_pll_taycan_elu_ops, 249 }, 250 }, 251 }; 252 253 static const struct clk_div_table post_div_table_cam_cc_pll3_out_even[] = { 254 { 0x1, 2 }, 255 { } 256 }; 257 258 static struct clk_alpha_pll_postdiv cam_cc_pll3_out_even = { 259 .offset = 0x3000, 260 .post_div_shift = 10, 261 .post_div_table = post_div_table_cam_cc_pll3_out_even, 262 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll3_out_even), 263 .width = 4, 264 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_ELU], 265 .clkr.hw.init = &(const struct clk_init_data) { 266 .name = "cam_cc_pll3_out_even", 267 .parent_hws = (const struct clk_hw*[]) { 268 &cam_cc_pll3.clkr.hw, 269 }, 270 .num_parents = 1, 271 .flags = CLK_SET_RATE_PARENT, 272 .ops = &clk_alpha_pll_postdiv_taycan_elu_ops, 273 }, 274 }; 275 276 static const struct alpha_pll_config cam_cc_pll4_config = { 277 .l = 0x25, 278 .alpha = 0x8777, 279 .config_ctl_val = 0x19660387, 280 .config_ctl_hi_val = 0x098060a0, 281 .config_ctl_hi1_val = 0xb416cb20, 282 .user_ctl_val = 0x00000400, 283 .user_ctl_hi_val = 0x00000002, 284 }; 285 286 static struct clk_alpha_pll cam_cc_pll4 = { 287 .offset = 0x4000, 288 .config = &cam_cc_pll4_config, 289 .vco_table = taycan_elu_vco, 290 .num_vco = ARRAY_SIZE(taycan_elu_vco), 291 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_ELU], 292 .clkr = { 293 .hw.init = &(const struct clk_init_data) { 294 .name = "cam_cc_pll4", 295 .parent_data = &(const struct clk_parent_data) { 296 .index = DT_BI_TCXO, 297 }, 298 .num_parents = 1, 299 .ops = &clk_alpha_pll_taycan_elu_ops, 300 }, 301 }, 302 }; 303 304 static const struct clk_div_table post_div_table_cam_cc_pll4_out_even[] = { 305 { 0x1, 2 }, 306 { } 307 }; 308 309 static struct clk_alpha_pll_postdiv cam_cc_pll4_out_even = { 310 .offset = 0x4000, 311 .post_div_shift = 10, 312 .post_div_table = post_div_table_cam_cc_pll4_out_even, 313 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll4_out_even), 314 .width = 4, 315 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_ELU], 316 .clkr.hw.init = &(const struct clk_init_data) { 317 .name = "cam_cc_pll4_out_even", 318 .parent_hws = (const struct clk_hw*[]) { 319 &cam_cc_pll4.clkr.hw, 320 }, 321 .num_parents = 1, 322 .flags = CLK_SET_RATE_PARENT, 323 .ops = &clk_alpha_pll_postdiv_taycan_elu_ops, 324 }, 325 }; 326 327 static const struct alpha_pll_config cam_cc_pll5_config = { 328 .l = 0x25, 329 .alpha = 0x8777, 330 .config_ctl_val = 0x19660387, 331 .config_ctl_hi_val = 0x098060a0, 332 .config_ctl_hi1_val = 0xb416cb20, 333 .user_ctl_val = 0x00000400, 334 .user_ctl_hi_val = 0x00000002, 335 }; 336 337 static struct clk_alpha_pll cam_cc_pll5 = { 338 .offset = 0x5000, 339 .config = &cam_cc_pll5_config, 340 .vco_table = taycan_elu_vco, 341 .num_vco = ARRAY_SIZE(taycan_elu_vco), 342 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_ELU], 343 .clkr = { 344 .hw.init = &(const struct clk_init_data) { 345 .name = "cam_cc_pll5", 346 .parent_data = &(const struct clk_parent_data) { 347 .index = DT_BI_TCXO, 348 }, 349 .num_parents = 1, 350 .ops = &clk_alpha_pll_taycan_elu_ops, 351 }, 352 }, 353 }; 354 355 static const struct clk_div_table post_div_table_cam_cc_pll5_out_even[] = { 356 { 0x1, 2 }, 357 { } 358 }; 359 360 static struct clk_alpha_pll_postdiv cam_cc_pll5_out_even = { 361 .offset = 0x5000, 362 .post_div_shift = 10, 363 .post_div_table = post_div_table_cam_cc_pll5_out_even, 364 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll5_out_even), 365 .width = 4, 366 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_ELU], 367 .clkr.hw.init = &(const struct clk_init_data) { 368 .name = "cam_cc_pll5_out_even", 369 .parent_hws = (const struct clk_hw*[]) { 370 &cam_cc_pll5.clkr.hw, 371 }, 372 .num_parents = 1, 373 .flags = CLK_SET_RATE_PARENT, 374 .ops = &clk_alpha_pll_postdiv_taycan_elu_ops, 375 }, 376 }; 377 378 static const struct alpha_pll_config cam_cc_pll6_config = { 379 .l = 0x32, 380 .alpha = 0x0, 381 .config_ctl_val = 0x19660387, 382 .config_ctl_hi_val = 0x098060a0, 383 .config_ctl_hi1_val = 0xb416cb20, 384 .user_ctl_val = 0x00008400, 385 .user_ctl_hi_val = 0x00000002, 386 }; 387 388 static struct clk_alpha_pll cam_cc_pll6 = { 389 .offset = 0x6000, 390 .config = &cam_cc_pll6_config, 391 .vco_table = taycan_elu_vco, 392 .num_vco = ARRAY_SIZE(taycan_elu_vco), 393 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_ELU], 394 .clkr = { 395 .hw.init = &(const struct clk_init_data) { 396 .name = "cam_cc_pll6", 397 .parent_data = &(const struct clk_parent_data) { 398 .index = DT_BI_TCXO, 399 }, 400 .num_parents = 1, 401 .ops = &clk_alpha_pll_taycan_elu_ops, 402 }, 403 }, 404 }; 405 406 static const struct clk_div_table post_div_table_cam_cc_pll6_out_even[] = { 407 { 0x1, 2 }, 408 { } 409 }; 410 411 static struct clk_alpha_pll_postdiv cam_cc_pll6_out_even = { 412 .offset = 0x6000, 413 .post_div_shift = 10, 414 .post_div_table = post_div_table_cam_cc_pll6_out_even, 415 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll6_out_even), 416 .width = 4, 417 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_ELU], 418 .clkr.hw.init = &(const struct clk_init_data) { 419 .name = "cam_cc_pll6_out_even", 420 .parent_hws = (const struct clk_hw*[]) { 421 &cam_cc_pll6.clkr.hw, 422 }, 423 .num_parents = 1, 424 .flags = CLK_SET_RATE_PARENT, 425 .ops = &clk_alpha_pll_postdiv_taycan_elu_ops, 426 }, 427 }; 428 429 static const struct clk_div_table post_div_table_cam_cc_pll6_out_odd[] = { 430 { 0x2, 3 }, 431 { } 432 }; 433 434 static struct clk_alpha_pll_postdiv cam_cc_pll6_out_odd = { 435 .offset = 0x6000, 436 .post_div_shift = 14, 437 .post_div_table = post_div_table_cam_cc_pll6_out_odd, 438 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll6_out_odd), 439 .width = 4, 440 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_ELU], 441 .clkr.hw.init = &(const struct clk_init_data) { 442 .name = "cam_cc_pll6_out_odd", 443 .parent_hws = (const struct clk_hw*[]) { 444 &cam_cc_pll6.clkr.hw, 445 }, 446 .num_parents = 1, 447 .flags = CLK_SET_RATE_PARENT, 448 .ops = &clk_alpha_pll_postdiv_taycan_elu_ops, 449 }, 450 }; 451 452 static const struct parent_map cam_cc_parent_map_0[] = { 453 { P_BI_TCXO, 0 }, 454 { P_CAM_CC_PLL0_OUT_MAIN, 1 }, 455 { P_CAM_CC_PLL0_OUT_EVEN, 2 }, 456 { P_CAM_CC_PLL0_OUT_ODD, 3 }, 457 { P_CAM_CC_PLL6_OUT_ODD, 4 }, 458 { P_CAM_CC_PLL6_OUT_EVEN, 5 }, 459 }; 460 461 static const struct clk_parent_data cam_cc_parent_data_0[] = { 462 { .index = DT_BI_TCXO }, 463 { .hw = &cam_cc_pll0.clkr.hw }, 464 { .hw = &cam_cc_pll0_out_even.clkr.hw }, 465 { .hw = &cam_cc_pll0_out_odd.clkr.hw }, 466 { .hw = &cam_cc_pll6_out_odd.clkr.hw }, 467 { .hw = &cam_cc_pll6_out_even.clkr.hw }, 468 }; 469 470 static const struct parent_map cam_cc_parent_map_1[] = { 471 { P_BI_TCXO, 0 }, 472 { P_CAM_CC_PLL0_OUT_MAIN, 1 }, 473 { P_CAM_CC_PLL0_OUT_EVEN, 2 }, 474 { P_CAM_CC_PLL0_OUT_ODD, 3 }, 475 { P_CAM_CC_PLL6_OUT_ODD, 4 }, 476 { P_CAM_CC_PLL6_OUT_EVEN, 5 }, 477 }; 478 479 static const struct clk_parent_data cam_cc_parent_data_1[] = { 480 { .index = DT_BI_TCXO }, 481 { .hw = &cam_cc_pll0.clkr.hw }, 482 { .hw = &cam_cc_pll0_out_even.clkr.hw }, 483 { .hw = &cam_cc_pll0_out_odd.clkr.hw }, 484 { .hw = &cam_cc_pll6_out_odd.clkr.hw }, 485 { .hw = &cam_cc_pll6_out_even.clkr.hw }, 486 }; 487 488 static const struct parent_map cam_cc_parent_map_2[] = { 489 { P_BI_TCXO, 0 }, 490 { P_CAM_CC_PLL1_OUT_EVEN, 4 }, 491 }; 492 493 static const struct clk_parent_data cam_cc_parent_data_2[] = { 494 { .index = DT_BI_TCXO }, 495 { .hw = &cam_cc_pll1_out_even.clkr.hw }, 496 }; 497 498 static const struct parent_map cam_cc_parent_map_3[] = { 499 { P_BI_TCXO, 0 }, 500 { P_CAM_CC_PLL2_OUT_EVEN, 5 }, 501 }; 502 503 static const struct clk_parent_data cam_cc_parent_data_3[] = { 504 { .index = DT_BI_TCXO }, 505 { .hw = &cam_cc_pll2_out_even.clkr.hw }, 506 }; 507 508 static const struct parent_map cam_cc_parent_map_4[] = { 509 { P_SLEEP_CLK, 0 }, 510 }; 511 512 static const struct clk_parent_data cam_cc_parent_data_4[] = { 513 { .index = DT_SLEEP_CLK }, 514 }; 515 516 static const struct parent_map cam_cc_parent_map_5[] = { 517 { P_BI_TCXO, 0 }, 518 { P_CAM_CC_PLL3_OUT_EVEN, 6 }, 519 }; 520 521 static const struct clk_parent_data cam_cc_parent_data_5[] = { 522 { .index = DT_BI_TCXO }, 523 { .hw = &cam_cc_pll3_out_even.clkr.hw }, 524 }; 525 526 static const struct parent_map cam_cc_parent_map_6[] = { 527 { P_BI_TCXO, 0 }, 528 { P_CAM_CC_PLL4_OUT_EVEN, 6 }, 529 }; 530 531 static const struct clk_parent_data cam_cc_parent_data_6[] = { 532 { .index = DT_BI_TCXO }, 533 { .hw = &cam_cc_pll4_out_even.clkr.hw }, 534 }; 535 536 static const struct parent_map cam_cc_parent_map_7[] = { 537 { P_BI_TCXO, 0 }, 538 { P_CAM_CC_PLL5_OUT_EVEN, 6 }, 539 }; 540 541 static const struct clk_parent_data cam_cc_parent_data_7[] = { 542 { .index = DT_BI_TCXO }, 543 { .hw = &cam_cc_pll5_out_even.clkr.hw }, 544 }; 545 546 static const struct parent_map cam_cc_parent_map_8_ao[] = { 547 { P_BI_TCXO_AO, 0 }, 548 }; 549 550 static const struct clk_parent_data cam_cc_parent_data_8_ao[] = { 551 { .index = DT_BI_TCXO_AO }, 552 }; 553 554 static const struct freq_tbl ftbl_cam_cc_camnoc_rt_axi_clk_src[] = { 555 F(19200000, P_BI_TCXO, 1, 0, 0), 556 F(200000000, P_CAM_CC_PLL0_OUT_EVEN, 3, 0, 0), 557 F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0), 558 F(400000000, P_CAM_CC_PLL0_OUT_EVEN, 1.5, 0, 0), 559 { } 560 }; 561 562 static struct clk_rcg2 cam_cc_camnoc_rt_axi_clk_src = { 563 .cmd_rcgr = 0x112e8, 564 .mnd_width = 0, 565 .hid_width = 5, 566 .parent_map = cam_cc_parent_map_0, 567 .freq_tbl = ftbl_cam_cc_camnoc_rt_axi_clk_src, 568 .clkr.hw.init = &(const struct clk_init_data) { 569 .name = "cam_cc_camnoc_rt_axi_clk_src", 570 .parent_data = cam_cc_parent_data_0, 571 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 572 .flags = CLK_SET_RATE_PARENT, 573 .ops = &clk_rcg2_shared_ops, 574 }, 575 }; 576 577 static const struct freq_tbl ftbl_cam_cc_cci_0_clk_src[] = { 578 F(37500000, P_CAM_CC_PLL0_OUT_EVEN, 16, 0, 0), 579 { } 580 }; 581 582 static struct clk_rcg2 cam_cc_cci_0_clk_src = { 583 .cmd_rcgr = 0x1126c, 584 .mnd_width = 8, 585 .hid_width = 5, 586 .parent_map = cam_cc_parent_map_0, 587 .freq_tbl = ftbl_cam_cc_cci_0_clk_src, 588 .clkr.hw.init = &(const struct clk_init_data) { 589 .name = "cam_cc_cci_0_clk_src", 590 .parent_data = cam_cc_parent_data_0, 591 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 592 .flags = CLK_SET_RATE_PARENT, 593 .ops = &clk_rcg2_shared_ops, 594 }, 595 }; 596 597 static struct clk_rcg2 cam_cc_cci_1_clk_src = { 598 .cmd_rcgr = 0x11288, 599 .mnd_width = 8, 600 .hid_width = 5, 601 .parent_map = cam_cc_parent_map_0, 602 .freq_tbl = ftbl_cam_cc_cci_0_clk_src, 603 .clkr.hw.init = &(const struct clk_init_data) { 604 .name = "cam_cc_cci_1_clk_src", 605 .parent_data = cam_cc_parent_data_0, 606 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 607 .flags = CLK_SET_RATE_PARENT, 608 .ops = &clk_rcg2_shared_ops, 609 }, 610 }; 611 612 static struct clk_rcg2 cam_cc_cci_2_clk_src = { 613 .cmd_rcgr = 0x112a4, 614 .mnd_width = 8, 615 .hid_width = 5, 616 .parent_map = cam_cc_parent_map_0, 617 .freq_tbl = ftbl_cam_cc_cci_0_clk_src, 618 .clkr.hw.init = &(const struct clk_init_data) { 619 .name = "cam_cc_cci_2_clk_src", 620 .parent_data = cam_cc_parent_data_0, 621 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 622 .flags = CLK_SET_RATE_PARENT, 623 .ops = &clk_rcg2_shared_ops, 624 }, 625 }; 626 627 static const struct freq_tbl ftbl_cam_cc_cphy_rx_clk_src[] = { 628 F(266666667, P_CAM_CC_PLL0_OUT_MAIN, 4.5, 0, 0), 629 F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0), 630 F(480000000, P_CAM_CC_PLL0_OUT_MAIN, 2.5, 0, 0), 631 { } 632 }; 633 634 static struct clk_rcg2 cam_cc_cphy_rx_clk_src = { 635 .cmd_rcgr = 0x11068, 636 .mnd_width = 0, 637 .hid_width = 5, 638 .parent_map = cam_cc_parent_map_1, 639 .freq_tbl = ftbl_cam_cc_cphy_rx_clk_src, 640 .clkr.hw.init = &(const struct clk_init_data) { 641 .name = "cam_cc_cphy_rx_clk_src", 642 .parent_data = cam_cc_parent_data_1, 643 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 644 .flags = CLK_SET_RATE_PARENT, 645 .ops = &clk_rcg2_shared_ops, 646 }, 647 }; 648 649 static const struct freq_tbl ftbl_cam_cc_cre_clk_src[] = { 650 F(137142857, P_CAM_CC_PLL6_OUT_EVEN, 3.5, 0, 0), 651 F(200000000, P_CAM_CC_PLL0_OUT_ODD, 2, 0, 0), 652 F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), 653 F(480000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0), 654 F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0), 655 { } 656 }; 657 658 static struct clk_rcg2 cam_cc_cre_clk_src = { 659 .cmd_rcgr = 0x111ac, 660 .mnd_width = 0, 661 .hid_width = 5, 662 .parent_map = cam_cc_parent_map_0, 663 .freq_tbl = ftbl_cam_cc_cre_clk_src, 664 .clkr.hw.init = &(const struct clk_init_data) { 665 .name = "cam_cc_cre_clk_src", 666 .parent_data = cam_cc_parent_data_0, 667 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 668 .flags = CLK_SET_RATE_PARENT, 669 .ops = &clk_rcg2_shared_ops, 670 }, 671 }; 672 673 static const struct freq_tbl ftbl_cam_cc_csi0phytimer_clk_src[] = { 674 F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0), 675 { } 676 }; 677 678 static struct clk_rcg2 cam_cc_csi0phytimer_clk_src = { 679 .cmd_rcgr = 0x10000, 680 .mnd_width = 0, 681 .hid_width = 5, 682 .parent_map = cam_cc_parent_map_1, 683 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, 684 .clkr.hw.init = &(const struct clk_init_data) { 685 .name = "cam_cc_csi0phytimer_clk_src", 686 .parent_data = cam_cc_parent_data_1, 687 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 688 .flags = CLK_SET_RATE_PARENT, 689 .ops = &clk_rcg2_shared_ops, 690 }, 691 }; 692 693 static struct clk_rcg2 cam_cc_csi1phytimer_clk_src = { 694 .cmd_rcgr = 0x10024, 695 .mnd_width = 0, 696 .hid_width = 5, 697 .parent_map = cam_cc_parent_map_1, 698 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, 699 .clkr.hw.init = &(const struct clk_init_data) { 700 .name = "cam_cc_csi1phytimer_clk_src", 701 .parent_data = cam_cc_parent_data_1, 702 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 703 .flags = CLK_SET_RATE_PARENT, 704 .ops = &clk_rcg2_shared_ops, 705 }, 706 }; 707 708 static struct clk_rcg2 cam_cc_csi2phytimer_clk_src = { 709 .cmd_rcgr = 0x10044, 710 .mnd_width = 0, 711 .hid_width = 5, 712 .parent_map = cam_cc_parent_map_1, 713 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, 714 .clkr.hw.init = &(const struct clk_init_data) { 715 .name = "cam_cc_csi2phytimer_clk_src", 716 .parent_data = cam_cc_parent_data_1, 717 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 718 .flags = CLK_SET_RATE_PARENT, 719 .ops = &clk_rcg2_shared_ops, 720 }, 721 }; 722 723 static struct clk_rcg2 cam_cc_csi3phytimer_clk_src = { 724 .cmd_rcgr = 0x10064, 725 .mnd_width = 0, 726 .hid_width = 5, 727 .parent_map = cam_cc_parent_map_1, 728 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, 729 .clkr.hw.init = &(const struct clk_init_data) { 730 .name = "cam_cc_csi3phytimer_clk_src", 731 .parent_data = cam_cc_parent_data_1, 732 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 733 .flags = CLK_SET_RATE_PARENT, 734 .ops = &clk_rcg2_shared_ops, 735 }, 736 }; 737 738 static struct clk_rcg2 cam_cc_csi4phytimer_clk_src = { 739 .cmd_rcgr = 0x10084, 740 .mnd_width = 0, 741 .hid_width = 5, 742 .parent_map = cam_cc_parent_map_1, 743 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, 744 .clkr.hw.init = &(const struct clk_init_data) { 745 .name = "cam_cc_csi4phytimer_clk_src", 746 .parent_data = cam_cc_parent_data_1, 747 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 748 .flags = CLK_SET_RATE_PARENT, 749 .ops = &clk_rcg2_shared_ops, 750 }, 751 }; 752 753 static struct clk_rcg2 cam_cc_csi5phytimer_clk_src = { 754 .cmd_rcgr = 0x100a4, 755 .mnd_width = 0, 756 .hid_width = 5, 757 .parent_map = cam_cc_parent_map_1, 758 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, 759 .clkr.hw.init = &(const struct clk_init_data) { 760 .name = "cam_cc_csi5phytimer_clk_src", 761 .parent_data = cam_cc_parent_data_1, 762 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 763 .flags = CLK_SET_RATE_PARENT, 764 .ops = &clk_rcg2_shared_ops, 765 }, 766 }; 767 768 static struct clk_rcg2 cam_cc_csid_clk_src = { 769 .cmd_rcgr = 0x112c0, 770 .mnd_width = 0, 771 .hid_width = 5, 772 .parent_map = cam_cc_parent_map_1, 773 .freq_tbl = ftbl_cam_cc_cphy_rx_clk_src, 774 .clkr.hw.init = &(const struct clk_init_data) { 775 .name = "cam_cc_csid_clk_src", 776 .parent_data = cam_cc_parent_data_1, 777 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 778 .flags = CLK_SET_RATE_PARENT, 779 .ops = &clk_rcg2_shared_ops, 780 }, 781 }; 782 783 static const struct freq_tbl ftbl_cam_cc_fast_ahb_clk_src[] = { 784 F(213333333, P_CAM_CC_PLL6_OUT_ODD, 1.5, 0, 0), 785 F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0), 786 F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0), 787 { } 788 }; 789 790 static struct clk_rcg2 cam_cc_fast_ahb_clk_src = { 791 .cmd_rcgr = 0x100dc, 792 .mnd_width = 0, 793 .hid_width = 5, 794 .parent_map = cam_cc_parent_map_0, 795 .freq_tbl = ftbl_cam_cc_fast_ahb_clk_src, 796 .clkr.hw.init = &(const struct clk_init_data) { 797 .name = "cam_cc_fast_ahb_clk_src", 798 .parent_data = cam_cc_parent_data_0, 799 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 800 .flags = CLK_SET_RATE_PARENT, 801 .ops = &clk_rcg2_shared_ops, 802 }, 803 }; 804 805 static const struct freq_tbl ftbl_cam_cc_icp_0_clk_src[] = { 806 F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0), 807 F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), 808 F(480000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0), 809 F(600000000, P_CAM_CC_PLL0_OUT_MAIN, 2, 0, 0), 810 { } 811 }; 812 813 static struct clk_rcg2 cam_cc_icp_0_clk_src = { 814 .cmd_rcgr = 0x11214, 815 .mnd_width = 0, 816 .hid_width = 5, 817 .parent_map = cam_cc_parent_map_0, 818 .freq_tbl = ftbl_cam_cc_icp_0_clk_src, 819 .clkr.hw.init = &(const struct clk_init_data) { 820 .name = "cam_cc_icp_0_clk_src", 821 .parent_data = cam_cc_parent_data_0, 822 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 823 .flags = CLK_SET_RATE_PARENT, 824 .ops = &clk_rcg2_shared_ops, 825 }, 826 }; 827 828 static struct clk_rcg2 cam_cc_icp_1_clk_src = { 829 .cmd_rcgr = 0x1123c, 830 .mnd_width = 0, 831 .hid_width = 5, 832 .parent_map = cam_cc_parent_map_0, 833 .freq_tbl = ftbl_cam_cc_icp_0_clk_src, 834 .clkr.hw.init = &(const struct clk_init_data) { 835 .name = "cam_cc_icp_1_clk_src", 836 .parent_data = cam_cc_parent_data_0, 837 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 838 .flags = CLK_SET_RATE_PARENT, 839 .ops = &clk_rcg2_shared_ops, 840 }, 841 }; 842 843 static struct clk_rcg2 cam_cc_ife_lite_clk_src = { 844 .cmd_rcgr = 0x11150, 845 .mnd_width = 0, 846 .hid_width = 5, 847 .parent_map = cam_cc_parent_map_1, 848 .freq_tbl = ftbl_cam_cc_cphy_rx_clk_src, 849 .clkr.hw.init = &(const struct clk_init_data) { 850 .name = "cam_cc_ife_lite_clk_src", 851 .parent_data = cam_cc_parent_data_1, 852 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 853 .flags = CLK_SET_RATE_PARENT, 854 .ops = &clk_rcg2_shared_ops, 855 }, 856 }; 857 858 static struct clk_rcg2 cam_cc_ife_lite_csid_clk_src = { 859 .cmd_rcgr = 0x1117c, 860 .mnd_width = 0, 861 .hid_width = 5, 862 .parent_map = cam_cc_parent_map_1, 863 .freq_tbl = ftbl_cam_cc_cphy_rx_clk_src, 864 .clkr.hw.init = &(const struct clk_init_data) { 865 .name = "cam_cc_ife_lite_csid_clk_src", 866 .parent_data = cam_cc_parent_data_1, 867 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 868 .flags = CLK_SET_RATE_PARENT, 869 .ops = &clk_rcg2_shared_ops, 870 }, 871 }; 872 873 static const struct freq_tbl ftbl_cam_cc_ipe_nps_clk_src[] = { 874 F(332500000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), 875 F(475000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), 876 F(575000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), 877 F(675000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), 878 F(825000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), 879 { } 880 }; 881 882 static struct clk_rcg2 cam_cc_ipe_nps_clk_src = { 883 .cmd_rcgr = 0x10190, 884 .mnd_width = 0, 885 .hid_width = 5, 886 .parent_map = cam_cc_parent_map_2, 887 .freq_tbl = ftbl_cam_cc_ipe_nps_clk_src, 888 .clkr.hw.init = &(const struct clk_init_data) { 889 .name = "cam_cc_ipe_nps_clk_src", 890 .parent_data = cam_cc_parent_data_2, 891 .num_parents = ARRAY_SIZE(cam_cc_parent_data_2), 892 .flags = CLK_SET_RATE_PARENT, 893 .ops = &clk_rcg2_shared_ops, 894 }, 895 }; 896 897 static struct clk_rcg2 cam_cc_jpeg_clk_src = { 898 .cmd_rcgr = 0x111d0, 899 .mnd_width = 0, 900 .hid_width = 5, 901 .parent_map = cam_cc_parent_map_0, 902 .freq_tbl = ftbl_cam_cc_cre_clk_src, 903 .clkr.hw.init = &(const struct clk_init_data) { 904 .name = "cam_cc_jpeg_clk_src", 905 .parent_data = cam_cc_parent_data_0, 906 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 907 .flags = CLK_SET_RATE_PARENT, 908 .ops = &clk_rcg2_shared_ops, 909 }, 910 }; 911 912 static const struct freq_tbl ftbl_cam_cc_ofe_clk_src[] = { 913 F(338800000, P_CAM_CC_PLL2_OUT_EVEN, 1, 0, 0), 914 F(484000000, P_CAM_CC_PLL2_OUT_EVEN, 1, 0, 0), 915 F(586000000, P_CAM_CC_PLL2_OUT_EVEN, 1, 0, 0), 916 F(688000000, P_CAM_CC_PLL2_OUT_EVEN, 1, 0, 0), 917 F(841000000, P_CAM_CC_PLL2_OUT_EVEN, 1, 0, 0), 918 { } 919 }; 920 921 static struct clk_rcg2 cam_cc_ofe_clk_src = { 922 .cmd_rcgr = 0x1011c, 923 .mnd_width = 0, 924 .hid_width = 5, 925 .parent_map = cam_cc_parent_map_3, 926 .freq_tbl = ftbl_cam_cc_ofe_clk_src, 927 .clkr.hw.init = &(const struct clk_init_data) { 928 .name = "cam_cc_ofe_clk_src", 929 .parent_data = cam_cc_parent_data_3, 930 .num_parents = ARRAY_SIZE(cam_cc_parent_data_3), 931 .flags = CLK_SET_RATE_PARENT, 932 .ops = &clk_rcg2_shared_ops, 933 }, 934 }; 935 936 static const struct freq_tbl ftbl_cam_cc_qdss_debug_clk_src[] = { 937 F(40000000, P_CAM_CC_PLL6_OUT_ODD, 8, 0, 0), 938 F(60000000, P_CAM_CC_PLL6_OUT_EVEN, 8, 0, 0), 939 F(120000000, P_CAM_CC_PLL0_OUT_EVEN, 5, 0, 0), 940 F(240000000, P_CAM_CC_PLL0_OUT_MAIN, 5, 0, 0), 941 { } 942 }; 943 944 static struct clk_rcg2 cam_cc_qdss_debug_clk_src = { 945 .cmd_rcgr = 0x1132c, 946 .mnd_width = 0, 947 .hid_width = 5, 948 .parent_map = cam_cc_parent_map_0, 949 .freq_tbl = ftbl_cam_cc_qdss_debug_clk_src, 950 .clkr.hw.init = &(const struct clk_init_data) { 951 .name = "cam_cc_qdss_debug_clk_src", 952 .parent_data = cam_cc_parent_data_0, 953 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 954 .flags = CLK_SET_RATE_PARENT, 955 .ops = &clk_rcg2_shared_ops, 956 }, 957 }; 958 959 static const struct freq_tbl ftbl_cam_cc_sleep_clk_src[] = { 960 F(32000, P_SLEEP_CLK, 1, 0, 0), 961 { } 962 }; 963 964 static struct clk_rcg2 cam_cc_sleep_clk_src = { 965 .cmd_rcgr = 0x11380, 966 .mnd_width = 0, 967 .hid_width = 5, 968 .parent_map = cam_cc_parent_map_4, 969 .freq_tbl = ftbl_cam_cc_sleep_clk_src, 970 .clkr.hw.init = &(const struct clk_init_data) { 971 .name = "cam_cc_sleep_clk_src", 972 .parent_data = cam_cc_parent_data_4, 973 .num_parents = ARRAY_SIZE(cam_cc_parent_data_4), 974 .flags = CLK_SET_RATE_PARENT, 975 .ops = &clk_rcg2_shared_ops, 976 }, 977 }; 978 979 static const struct freq_tbl ftbl_cam_cc_slow_ahb_clk_src[] = { 980 F(56470588, P_CAM_CC_PLL6_OUT_EVEN, 8.5, 0, 0), 981 F(80000000, P_CAM_CC_PLL0_OUT_EVEN, 7.5, 0, 0), 982 { } 983 }; 984 985 static struct clk_rcg2 cam_cc_slow_ahb_clk_src = { 986 .cmd_rcgr = 0x10100, 987 .mnd_width = 0, 988 .hid_width = 5, 989 .parent_map = cam_cc_parent_map_0, 990 .freq_tbl = ftbl_cam_cc_slow_ahb_clk_src, 991 .clkr.hw.init = &(const struct clk_init_data) { 992 .name = "cam_cc_slow_ahb_clk_src", 993 .parent_data = cam_cc_parent_data_0, 994 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 995 .flags = CLK_SET_RATE_PARENT, 996 .ops = &clk_rcg2_shared_ops, 997 }, 998 }; 999 1000 static const struct freq_tbl ftbl_cam_cc_tfe_0_clk_src[] = { 1001 F(360280000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), 1002 F(480000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), 1003 F(630000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), 1004 F(716000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), 1005 F(833000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), 1006 { } 1007 }; 1008 1009 static struct clk_rcg2 cam_cc_tfe_0_clk_src = { 1010 .cmd_rcgr = 0x11018, 1011 .mnd_width = 0, 1012 .hid_width = 5, 1013 .parent_map = cam_cc_parent_map_5, 1014 .freq_tbl = ftbl_cam_cc_tfe_0_clk_src, 1015 .clkr.hw.init = &(const struct clk_init_data) { 1016 .name = "cam_cc_tfe_0_clk_src", 1017 .parent_data = cam_cc_parent_data_5, 1018 .num_parents = ARRAY_SIZE(cam_cc_parent_data_5), 1019 .flags = CLK_SET_RATE_PARENT, 1020 .ops = &clk_rcg2_shared_ops, 1021 }, 1022 }; 1023 1024 static const struct freq_tbl ftbl_cam_cc_tfe_1_clk_src[] = { 1025 F(360280000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), 1026 F(480000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), 1027 F(630000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), 1028 F(716000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), 1029 F(833000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), 1030 { } 1031 }; 1032 1033 static struct clk_rcg2 cam_cc_tfe_1_clk_src = { 1034 .cmd_rcgr = 0x11098, 1035 .mnd_width = 0, 1036 .hid_width = 5, 1037 .parent_map = cam_cc_parent_map_6, 1038 .freq_tbl = ftbl_cam_cc_tfe_1_clk_src, 1039 .clkr.hw.init = &(const struct clk_init_data) { 1040 .name = "cam_cc_tfe_1_clk_src", 1041 .parent_data = cam_cc_parent_data_6, 1042 .num_parents = ARRAY_SIZE(cam_cc_parent_data_6), 1043 .flags = CLK_SET_RATE_PARENT, 1044 .ops = &clk_rcg2_shared_ops, 1045 }, 1046 }; 1047 1048 static const struct freq_tbl ftbl_cam_cc_tfe_2_clk_src[] = { 1049 F(360280000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0), 1050 F(480000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0), 1051 F(630000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0), 1052 F(716000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0), 1053 F(833000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0), 1054 { } 1055 }; 1056 1057 static struct clk_rcg2 cam_cc_tfe_2_clk_src = { 1058 .cmd_rcgr = 0x11100, 1059 .mnd_width = 0, 1060 .hid_width = 5, 1061 .parent_map = cam_cc_parent_map_7, 1062 .freq_tbl = ftbl_cam_cc_tfe_2_clk_src, 1063 .clkr.hw.init = &(const struct clk_init_data) { 1064 .name = "cam_cc_tfe_2_clk_src", 1065 .parent_data = cam_cc_parent_data_7, 1066 .num_parents = ARRAY_SIZE(cam_cc_parent_data_7), 1067 .flags = CLK_SET_RATE_PARENT, 1068 .ops = &clk_rcg2_shared_ops, 1069 }, 1070 }; 1071 1072 static const struct freq_tbl ftbl_cam_cc_xo_clk_src[] = { 1073 F(19200000, P_BI_TCXO_AO, 1, 0, 0), 1074 { } 1075 }; 1076 1077 static struct clk_rcg2 cam_cc_xo_clk_src = { 1078 .cmd_rcgr = 0x11364, 1079 .mnd_width = 0, 1080 .hid_width = 5, 1081 .parent_map = cam_cc_parent_map_8_ao, 1082 .freq_tbl = ftbl_cam_cc_xo_clk_src, 1083 .clkr.hw.init = &(const struct clk_init_data) { 1084 .name = "cam_cc_xo_clk_src", 1085 .parent_data = cam_cc_parent_data_8_ao, 1086 .num_parents = ARRAY_SIZE(cam_cc_parent_data_8_ao), 1087 .flags = CLK_SET_RATE_PARENT, 1088 .ops = &clk_rcg2_shared_ops, 1089 }, 1090 }; 1091 1092 static struct clk_branch cam_cc_cam_top_ahb_clk = { 1093 .halt_reg = 0x113ac, 1094 .halt_check = BRANCH_HALT, 1095 .clkr = { 1096 .enable_reg = 0x113ac, 1097 .enable_mask = BIT(0), 1098 .hw.init = &(const struct clk_init_data) { 1099 .name = "cam_cc_cam_top_ahb_clk", 1100 .parent_hws = (const struct clk_hw*[]) { 1101 &cam_cc_slow_ahb_clk_src.clkr.hw, 1102 }, 1103 .num_parents = 1, 1104 .flags = CLK_SET_RATE_PARENT, 1105 .ops = &clk_branch2_ops, 1106 }, 1107 }, 1108 }; 1109 1110 static struct clk_branch cam_cc_cam_top_fast_ahb_clk = { 1111 .halt_reg = 0x1139c, 1112 .halt_check = BRANCH_HALT, 1113 .clkr = { 1114 .enable_reg = 0x1139c, 1115 .enable_mask = BIT(0), 1116 .hw.init = &(const struct clk_init_data) { 1117 .name = "cam_cc_cam_top_fast_ahb_clk", 1118 .parent_hws = (const struct clk_hw*[]) { 1119 &cam_cc_fast_ahb_clk_src.clkr.hw, 1120 }, 1121 .num_parents = 1, 1122 .flags = CLK_SET_RATE_PARENT, 1123 .ops = &clk_branch2_ops, 1124 }, 1125 }, 1126 }; 1127 1128 static struct clk_branch cam_cc_camnoc_dcd_xo_clk = { 1129 .halt_reg = 0x11320, 1130 .halt_check = BRANCH_HALT, 1131 .clkr = { 1132 .enable_reg = 0x11320, 1133 .enable_mask = BIT(0), 1134 .hw.init = &(const struct clk_init_data) { 1135 .name = "cam_cc_camnoc_dcd_xo_clk", 1136 .parent_hws = (const struct clk_hw*[]) { 1137 &cam_cc_xo_clk_src.clkr.hw, 1138 }, 1139 .num_parents = 1, 1140 .flags = CLK_SET_RATE_PARENT, 1141 .ops = &clk_branch2_ops, 1142 }, 1143 }, 1144 }; 1145 1146 static struct clk_branch cam_cc_camnoc_nrt_axi_clk = { 1147 .halt_reg = 0x11310, 1148 .halt_check = BRANCH_HALT_VOTED, 1149 .hwcg_reg = 0x11310, 1150 .hwcg_bit = 1, 1151 .clkr = { 1152 .enable_reg = 0x11310, 1153 .enable_mask = BIT(0), 1154 .hw.init = &(const struct clk_init_data) { 1155 .name = "cam_cc_camnoc_nrt_axi_clk", 1156 .parent_hws = (const struct clk_hw*[]) { 1157 &cam_cc_camnoc_rt_axi_clk_src.clkr.hw, 1158 }, 1159 .num_parents = 1, 1160 .flags = CLK_SET_RATE_PARENT, 1161 .ops = &clk_branch2_ops, 1162 }, 1163 }, 1164 }; 1165 1166 static struct clk_branch cam_cc_camnoc_nrt_cre_clk = { 1167 .halt_reg = 0x111c8, 1168 .halt_check = BRANCH_HALT, 1169 .clkr = { 1170 .enable_reg = 0x111c8, 1171 .enable_mask = BIT(0), 1172 .hw.init = &(const struct clk_init_data) { 1173 .name = "cam_cc_camnoc_nrt_cre_clk", 1174 .parent_hws = (const struct clk_hw*[]) { 1175 &cam_cc_cre_clk_src.clkr.hw, 1176 }, 1177 .num_parents = 1, 1178 .flags = CLK_SET_RATE_PARENT, 1179 .ops = &clk_branch2_ops, 1180 }, 1181 }, 1182 }; 1183 1184 static struct clk_branch cam_cc_camnoc_nrt_ipe_nps_clk = { 1185 .halt_reg = 0x101b8, 1186 .halt_check = BRANCH_HALT, 1187 .clkr = { 1188 .enable_reg = 0x101b8, 1189 .enable_mask = BIT(0), 1190 .hw.init = &(const struct clk_init_data) { 1191 .name = "cam_cc_camnoc_nrt_ipe_nps_clk", 1192 .parent_hws = (const struct clk_hw*[]) { 1193 &cam_cc_ipe_nps_clk_src.clkr.hw, 1194 }, 1195 .num_parents = 1, 1196 .flags = CLK_SET_RATE_PARENT, 1197 .ops = &clk_branch2_ops, 1198 }, 1199 }, 1200 }; 1201 1202 static struct clk_branch cam_cc_camnoc_nrt_ofe_anchor_clk = { 1203 .halt_reg = 0x10158, 1204 .halt_check = BRANCH_HALT, 1205 .clkr = { 1206 .enable_reg = 0x10158, 1207 .enable_mask = BIT(0), 1208 .hw.init = &(const struct clk_init_data) { 1209 .name = "cam_cc_camnoc_nrt_ofe_anchor_clk", 1210 .parent_hws = (const struct clk_hw*[]) { 1211 &cam_cc_ofe_clk_src.clkr.hw, 1212 }, 1213 .num_parents = 1, 1214 .flags = CLK_SET_RATE_PARENT, 1215 .ops = &clk_branch2_ops, 1216 }, 1217 }, 1218 }; 1219 1220 static struct clk_branch cam_cc_camnoc_nrt_ofe_hdr_clk = { 1221 .halt_reg = 0x1016c, 1222 .halt_check = BRANCH_HALT, 1223 .clkr = { 1224 .enable_reg = 0x1016c, 1225 .enable_mask = BIT(0), 1226 .hw.init = &(const struct clk_init_data) { 1227 .name = "cam_cc_camnoc_nrt_ofe_hdr_clk", 1228 .parent_hws = (const struct clk_hw*[]) { 1229 &cam_cc_ofe_clk_src.clkr.hw, 1230 }, 1231 .num_parents = 1, 1232 .flags = CLK_SET_RATE_PARENT, 1233 .ops = &clk_branch2_ops, 1234 }, 1235 }, 1236 }; 1237 1238 static struct clk_branch cam_cc_camnoc_nrt_ofe_main_clk = { 1239 .halt_reg = 0x10144, 1240 .halt_check = BRANCH_HALT, 1241 .clkr = { 1242 .enable_reg = 0x10144, 1243 .enable_mask = BIT(0), 1244 .hw.init = &(const struct clk_init_data) { 1245 .name = "cam_cc_camnoc_nrt_ofe_main_clk", 1246 .parent_hws = (const struct clk_hw*[]) { 1247 &cam_cc_ofe_clk_src.clkr.hw, 1248 }, 1249 .num_parents = 1, 1250 .flags = CLK_SET_RATE_PARENT, 1251 .ops = &clk_branch2_ops, 1252 }, 1253 }, 1254 }; 1255 1256 static struct clk_branch cam_cc_camnoc_rt_axi_clk = { 1257 .halt_reg = 0x11300, 1258 .halt_check = BRANCH_HALT, 1259 .clkr = { 1260 .enable_reg = 0x11300, 1261 .enable_mask = BIT(0), 1262 .hw.init = &(const struct clk_init_data) { 1263 .name = "cam_cc_camnoc_rt_axi_clk", 1264 .parent_hws = (const struct clk_hw*[]) { 1265 &cam_cc_camnoc_rt_axi_clk_src.clkr.hw, 1266 }, 1267 .num_parents = 1, 1268 .flags = CLK_SET_RATE_PARENT, 1269 .ops = &clk_branch2_ops, 1270 }, 1271 }, 1272 }; 1273 1274 static struct clk_branch cam_cc_camnoc_rt_ife_lite_clk = { 1275 .halt_reg = 0x11178, 1276 .halt_check = BRANCH_HALT, 1277 .clkr = { 1278 .enable_reg = 0x11178, 1279 .enable_mask = BIT(0), 1280 .hw.init = &(const struct clk_init_data) { 1281 .name = "cam_cc_camnoc_rt_ife_lite_clk", 1282 .parent_hws = (const struct clk_hw*[]) { 1283 &cam_cc_ife_lite_clk_src.clkr.hw, 1284 }, 1285 .num_parents = 1, 1286 .flags = CLK_SET_RATE_PARENT, 1287 .ops = &clk_branch2_ops, 1288 }, 1289 }, 1290 }; 1291 1292 static struct clk_branch cam_cc_camnoc_rt_tfe_0_bayer_clk = { 1293 .halt_reg = 0x11054, 1294 .halt_check = BRANCH_HALT, 1295 .clkr = { 1296 .enable_reg = 0x11054, 1297 .enable_mask = BIT(0), 1298 .hw.init = &(const struct clk_init_data) { 1299 .name = "cam_cc_camnoc_rt_tfe_0_bayer_clk", 1300 .parent_hws = (const struct clk_hw*[]) { 1301 &cam_cc_tfe_0_clk_src.clkr.hw, 1302 }, 1303 .num_parents = 1, 1304 .flags = CLK_SET_RATE_PARENT, 1305 .ops = &clk_branch2_ops, 1306 }, 1307 }, 1308 }; 1309 1310 static struct clk_branch cam_cc_camnoc_rt_tfe_0_main_clk = { 1311 .halt_reg = 0x11040, 1312 .halt_check = BRANCH_HALT, 1313 .clkr = { 1314 .enable_reg = 0x11040, 1315 .enable_mask = BIT(0), 1316 .hw.init = &(const struct clk_init_data) { 1317 .name = "cam_cc_camnoc_rt_tfe_0_main_clk", 1318 .parent_hws = (const struct clk_hw*[]) { 1319 &cam_cc_tfe_0_clk_src.clkr.hw, 1320 }, 1321 .num_parents = 1, 1322 .flags = CLK_SET_RATE_PARENT, 1323 .ops = &clk_branch2_ops, 1324 }, 1325 }, 1326 }; 1327 1328 static struct clk_branch cam_cc_camnoc_rt_tfe_1_bayer_clk = { 1329 .halt_reg = 0x110d4, 1330 .halt_check = BRANCH_HALT, 1331 .clkr = { 1332 .enable_reg = 0x110d4, 1333 .enable_mask = BIT(0), 1334 .hw.init = &(const struct clk_init_data) { 1335 .name = "cam_cc_camnoc_rt_tfe_1_bayer_clk", 1336 .parent_hws = (const struct clk_hw*[]) { 1337 &cam_cc_tfe_1_clk_src.clkr.hw, 1338 }, 1339 .num_parents = 1, 1340 .flags = CLK_SET_RATE_PARENT, 1341 .ops = &clk_branch2_ops, 1342 }, 1343 }, 1344 }; 1345 1346 static struct clk_branch cam_cc_camnoc_rt_tfe_1_main_clk = { 1347 .halt_reg = 0x110c0, 1348 .halt_check = BRANCH_HALT, 1349 .clkr = { 1350 .enable_reg = 0x110c0, 1351 .enable_mask = BIT(0), 1352 .hw.init = &(const struct clk_init_data) { 1353 .name = "cam_cc_camnoc_rt_tfe_1_main_clk", 1354 .parent_hws = (const struct clk_hw*[]) { 1355 &cam_cc_tfe_1_clk_src.clkr.hw, 1356 }, 1357 .num_parents = 1, 1358 .flags = CLK_SET_RATE_PARENT, 1359 .ops = &clk_branch2_ops, 1360 }, 1361 }, 1362 }; 1363 1364 static struct clk_branch cam_cc_camnoc_rt_tfe_2_bayer_clk = { 1365 .halt_reg = 0x1113c, 1366 .halt_check = BRANCH_HALT, 1367 .clkr = { 1368 .enable_reg = 0x1113c, 1369 .enable_mask = BIT(0), 1370 .hw.init = &(const struct clk_init_data) { 1371 .name = "cam_cc_camnoc_rt_tfe_2_bayer_clk", 1372 .parent_hws = (const struct clk_hw*[]) { 1373 &cam_cc_tfe_2_clk_src.clkr.hw, 1374 }, 1375 .num_parents = 1, 1376 .flags = CLK_SET_RATE_PARENT, 1377 .ops = &clk_branch2_ops, 1378 }, 1379 }, 1380 }; 1381 1382 static struct clk_branch cam_cc_camnoc_rt_tfe_2_main_clk = { 1383 .halt_reg = 0x11128, 1384 .halt_check = BRANCH_HALT, 1385 .clkr = { 1386 .enable_reg = 0x11128, 1387 .enable_mask = BIT(0), 1388 .hw.init = &(const struct clk_init_data) { 1389 .name = "cam_cc_camnoc_rt_tfe_2_main_clk", 1390 .parent_hws = (const struct clk_hw*[]) { 1391 &cam_cc_tfe_2_clk_src.clkr.hw, 1392 }, 1393 .num_parents = 1, 1394 .flags = CLK_SET_RATE_PARENT, 1395 .ops = &clk_branch2_ops, 1396 }, 1397 }, 1398 }; 1399 1400 static struct clk_branch cam_cc_camnoc_xo_clk = { 1401 .halt_reg = 0x11324, 1402 .halt_check = BRANCH_HALT, 1403 .clkr = { 1404 .enable_reg = 0x11324, 1405 .enable_mask = BIT(0), 1406 .hw.init = &(const struct clk_init_data) { 1407 .name = "cam_cc_camnoc_xo_clk", 1408 .parent_hws = (const struct clk_hw*[]) { 1409 &cam_cc_xo_clk_src.clkr.hw, 1410 }, 1411 .num_parents = 1, 1412 .flags = CLK_SET_RATE_PARENT, 1413 .ops = &clk_branch2_ops, 1414 }, 1415 }, 1416 }; 1417 1418 static struct clk_branch cam_cc_cci_0_clk = { 1419 .halt_reg = 0x11284, 1420 .halt_check = BRANCH_HALT, 1421 .clkr = { 1422 .enable_reg = 0x11284, 1423 .enable_mask = BIT(0), 1424 .hw.init = &(const struct clk_init_data) { 1425 .name = "cam_cc_cci_0_clk", 1426 .parent_hws = (const struct clk_hw*[]) { 1427 &cam_cc_cci_0_clk_src.clkr.hw, 1428 }, 1429 .num_parents = 1, 1430 .flags = CLK_SET_RATE_PARENT, 1431 .ops = &clk_branch2_ops, 1432 }, 1433 }, 1434 }; 1435 1436 static struct clk_branch cam_cc_cci_1_clk = { 1437 .halt_reg = 0x112a0, 1438 .halt_check = BRANCH_HALT, 1439 .clkr = { 1440 .enable_reg = 0x112a0, 1441 .enable_mask = BIT(0), 1442 .hw.init = &(const struct clk_init_data) { 1443 .name = "cam_cc_cci_1_clk", 1444 .parent_hws = (const struct clk_hw*[]) { 1445 &cam_cc_cci_1_clk_src.clkr.hw, 1446 }, 1447 .num_parents = 1, 1448 .flags = CLK_SET_RATE_PARENT, 1449 .ops = &clk_branch2_ops, 1450 }, 1451 }, 1452 }; 1453 1454 static struct clk_branch cam_cc_cci_2_clk = { 1455 .halt_reg = 0x112bc, 1456 .halt_check = BRANCH_HALT, 1457 .clkr = { 1458 .enable_reg = 0x112bc, 1459 .enable_mask = BIT(0), 1460 .hw.init = &(const struct clk_init_data) { 1461 .name = "cam_cc_cci_2_clk", 1462 .parent_hws = (const struct clk_hw*[]) { 1463 &cam_cc_cci_2_clk_src.clkr.hw, 1464 }, 1465 .num_parents = 1, 1466 .flags = CLK_SET_RATE_PARENT, 1467 .ops = &clk_branch2_ops, 1468 }, 1469 }, 1470 }; 1471 1472 static struct clk_branch cam_cc_core_ahb_clk = { 1473 .halt_reg = 0x11360, 1474 .halt_check = BRANCH_HALT_DELAY, 1475 .clkr = { 1476 .enable_reg = 0x11360, 1477 .enable_mask = BIT(0), 1478 .hw.init = &(const struct clk_init_data) { 1479 .name = "cam_cc_core_ahb_clk", 1480 .parent_hws = (const struct clk_hw*[]) { 1481 &cam_cc_slow_ahb_clk_src.clkr.hw, 1482 }, 1483 .num_parents = 1, 1484 .flags = CLK_SET_RATE_PARENT, 1485 .ops = &clk_branch2_ops, 1486 }, 1487 }, 1488 }; 1489 1490 static struct clk_branch cam_cc_cre_ahb_clk = { 1491 .halt_reg = 0x111cc, 1492 .halt_check = BRANCH_HALT, 1493 .clkr = { 1494 .enable_reg = 0x111cc, 1495 .enable_mask = BIT(0), 1496 .hw.init = &(const struct clk_init_data) { 1497 .name = "cam_cc_cre_ahb_clk", 1498 .parent_hws = (const struct clk_hw*[]) { 1499 &cam_cc_slow_ahb_clk_src.clkr.hw, 1500 }, 1501 .num_parents = 1, 1502 .flags = CLK_SET_RATE_PARENT, 1503 .ops = &clk_branch2_ops, 1504 }, 1505 }, 1506 }; 1507 1508 static struct clk_branch cam_cc_cre_clk = { 1509 .halt_reg = 0x111c4, 1510 .halt_check = BRANCH_HALT, 1511 .clkr = { 1512 .enable_reg = 0x111c4, 1513 .enable_mask = BIT(0), 1514 .hw.init = &(const struct clk_init_data) { 1515 .name = "cam_cc_cre_clk", 1516 .parent_hws = (const struct clk_hw*[]) { 1517 &cam_cc_cre_clk_src.clkr.hw, 1518 }, 1519 .num_parents = 1, 1520 .flags = CLK_SET_RATE_PARENT, 1521 .ops = &clk_branch2_ops, 1522 }, 1523 }, 1524 }; 1525 1526 static struct clk_branch cam_cc_csi0phytimer_clk = { 1527 .halt_reg = 0x10018, 1528 .halt_check = BRANCH_HALT, 1529 .clkr = { 1530 .enable_reg = 0x10018, 1531 .enable_mask = BIT(0), 1532 .hw.init = &(const struct clk_init_data) { 1533 .name = "cam_cc_csi0phytimer_clk", 1534 .parent_hws = (const struct clk_hw*[]) { 1535 &cam_cc_csi0phytimer_clk_src.clkr.hw, 1536 }, 1537 .num_parents = 1, 1538 .flags = CLK_SET_RATE_PARENT, 1539 .ops = &clk_branch2_ops, 1540 }, 1541 }, 1542 }; 1543 1544 static struct clk_branch cam_cc_csi1phytimer_clk = { 1545 .halt_reg = 0x1003c, 1546 .halt_check = BRANCH_HALT, 1547 .clkr = { 1548 .enable_reg = 0x1003c, 1549 .enable_mask = BIT(0), 1550 .hw.init = &(const struct clk_init_data) { 1551 .name = "cam_cc_csi1phytimer_clk", 1552 .parent_hws = (const struct clk_hw*[]) { 1553 &cam_cc_csi1phytimer_clk_src.clkr.hw, 1554 }, 1555 .num_parents = 1, 1556 .flags = CLK_SET_RATE_PARENT, 1557 .ops = &clk_branch2_ops, 1558 }, 1559 }, 1560 }; 1561 1562 static struct clk_branch cam_cc_csi2phytimer_clk = { 1563 .halt_reg = 0x1005c, 1564 .halt_check = BRANCH_HALT, 1565 .clkr = { 1566 .enable_reg = 0x1005c, 1567 .enable_mask = BIT(0), 1568 .hw.init = &(const struct clk_init_data) { 1569 .name = "cam_cc_csi2phytimer_clk", 1570 .parent_hws = (const struct clk_hw*[]) { 1571 &cam_cc_csi2phytimer_clk_src.clkr.hw, 1572 }, 1573 .num_parents = 1, 1574 .flags = CLK_SET_RATE_PARENT, 1575 .ops = &clk_branch2_ops, 1576 }, 1577 }, 1578 }; 1579 1580 static struct clk_branch cam_cc_csi3phytimer_clk = { 1581 .halt_reg = 0x1007c, 1582 .halt_check = BRANCH_HALT, 1583 .clkr = { 1584 .enable_reg = 0x1007c, 1585 .enable_mask = BIT(0), 1586 .hw.init = &(const struct clk_init_data) { 1587 .name = "cam_cc_csi3phytimer_clk", 1588 .parent_hws = (const struct clk_hw*[]) { 1589 &cam_cc_csi3phytimer_clk_src.clkr.hw, 1590 }, 1591 .num_parents = 1, 1592 .flags = CLK_SET_RATE_PARENT, 1593 .ops = &clk_branch2_ops, 1594 }, 1595 }, 1596 }; 1597 1598 static struct clk_branch cam_cc_csi4phytimer_clk = { 1599 .halt_reg = 0x1009c, 1600 .halt_check = BRANCH_HALT, 1601 .clkr = { 1602 .enable_reg = 0x1009c, 1603 .enable_mask = BIT(0), 1604 .hw.init = &(const struct clk_init_data) { 1605 .name = "cam_cc_csi4phytimer_clk", 1606 .parent_hws = (const struct clk_hw*[]) { 1607 &cam_cc_csi4phytimer_clk_src.clkr.hw, 1608 }, 1609 .num_parents = 1, 1610 .flags = CLK_SET_RATE_PARENT, 1611 .ops = &clk_branch2_ops, 1612 }, 1613 }, 1614 }; 1615 1616 static struct clk_branch cam_cc_csi5phytimer_clk = { 1617 .halt_reg = 0x100bc, 1618 .halt_check = BRANCH_HALT, 1619 .clkr = { 1620 .enable_reg = 0x100bc, 1621 .enable_mask = BIT(0), 1622 .hw.init = &(const struct clk_init_data) { 1623 .name = "cam_cc_csi5phytimer_clk", 1624 .parent_hws = (const struct clk_hw*[]) { 1625 &cam_cc_csi5phytimer_clk_src.clkr.hw, 1626 }, 1627 .num_parents = 1, 1628 .flags = CLK_SET_RATE_PARENT, 1629 .ops = &clk_branch2_ops, 1630 }, 1631 }, 1632 }; 1633 1634 static struct clk_branch cam_cc_csid_clk = { 1635 .halt_reg = 0x112d8, 1636 .halt_check = BRANCH_HALT, 1637 .clkr = { 1638 .enable_reg = 0x112d8, 1639 .enable_mask = BIT(0), 1640 .hw.init = &(const struct clk_init_data) { 1641 .name = "cam_cc_csid_clk", 1642 .parent_hws = (const struct clk_hw*[]) { 1643 &cam_cc_csid_clk_src.clkr.hw, 1644 }, 1645 .num_parents = 1, 1646 .flags = CLK_SET_RATE_PARENT, 1647 .ops = &clk_branch2_ops, 1648 }, 1649 }, 1650 }; 1651 1652 static struct clk_branch cam_cc_csid_csiphy_rx_clk = { 1653 .halt_reg = 0x10020, 1654 .halt_check = BRANCH_HALT, 1655 .clkr = { 1656 .enable_reg = 0x10020, 1657 .enable_mask = BIT(0), 1658 .hw.init = &(const struct clk_init_data) { 1659 .name = "cam_cc_csid_csiphy_rx_clk", 1660 .parent_hws = (const struct clk_hw*[]) { 1661 &cam_cc_cphy_rx_clk_src.clkr.hw, 1662 }, 1663 .num_parents = 1, 1664 .flags = CLK_SET_RATE_PARENT, 1665 .ops = &clk_branch2_ops, 1666 }, 1667 }, 1668 }; 1669 1670 static struct clk_branch cam_cc_csiphy0_clk = { 1671 .halt_reg = 0x1001c, 1672 .halt_check = BRANCH_HALT, 1673 .clkr = { 1674 .enable_reg = 0x1001c, 1675 .enable_mask = BIT(0), 1676 .hw.init = &(const struct clk_init_data) { 1677 .name = "cam_cc_csiphy0_clk", 1678 .parent_hws = (const struct clk_hw*[]) { 1679 &cam_cc_cphy_rx_clk_src.clkr.hw, 1680 }, 1681 .num_parents = 1, 1682 .flags = CLK_SET_RATE_PARENT, 1683 .ops = &clk_branch2_ops, 1684 }, 1685 }, 1686 }; 1687 1688 static struct clk_branch cam_cc_csiphy1_clk = { 1689 .halt_reg = 0x10040, 1690 .halt_check = BRANCH_HALT, 1691 .clkr = { 1692 .enable_reg = 0x10040, 1693 .enable_mask = BIT(0), 1694 .hw.init = &(const struct clk_init_data) { 1695 .name = "cam_cc_csiphy1_clk", 1696 .parent_hws = (const struct clk_hw*[]) { 1697 &cam_cc_cphy_rx_clk_src.clkr.hw, 1698 }, 1699 .num_parents = 1, 1700 .flags = CLK_SET_RATE_PARENT, 1701 .ops = &clk_branch2_ops, 1702 }, 1703 }, 1704 }; 1705 1706 static struct clk_branch cam_cc_csiphy2_clk = { 1707 .halt_reg = 0x10060, 1708 .halt_check = BRANCH_HALT, 1709 .clkr = { 1710 .enable_reg = 0x10060, 1711 .enable_mask = BIT(0), 1712 .hw.init = &(const struct clk_init_data) { 1713 .name = "cam_cc_csiphy2_clk", 1714 .parent_hws = (const struct clk_hw*[]) { 1715 &cam_cc_cphy_rx_clk_src.clkr.hw, 1716 }, 1717 .num_parents = 1, 1718 .flags = CLK_SET_RATE_PARENT, 1719 .ops = &clk_branch2_ops, 1720 }, 1721 }, 1722 }; 1723 1724 static struct clk_branch cam_cc_csiphy3_clk = { 1725 .halt_reg = 0x10080, 1726 .halt_check = BRANCH_HALT, 1727 .clkr = { 1728 .enable_reg = 0x10080, 1729 .enable_mask = BIT(0), 1730 .hw.init = &(const struct clk_init_data) { 1731 .name = "cam_cc_csiphy3_clk", 1732 .parent_hws = (const struct clk_hw*[]) { 1733 &cam_cc_cphy_rx_clk_src.clkr.hw, 1734 }, 1735 .num_parents = 1, 1736 .flags = CLK_SET_RATE_PARENT, 1737 .ops = &clk_branch2_ops, 1738 }, 1739 }, 1740 }; 1741 1742 static struct clk_branch cam_cc_csiphy4_clk = { 1743 .halt_reg = 0x100a0, 1744 .halt_check = BRANCH_HALT, 1745 .clkr = { 1746 .enable_reg = 0x100a0, 1747 .enable_mask = BIT(0), 1748 .hw.init = &(const struct clk_init_data) { 1749 .name = "cam_cc_csiphy4_clk", 1750 .parent_hws = (const struct clk_hw*[]) { 1751 &cam_cc_cphy_rx_clk_src.clkr.hw, 1752 }, 1753 .num_parents = 1, 1754 .flags = CLK_SET_RATE_PARENT, 1755 .ops = &clk_branch2_ops, 1756 }, 1757 }, 1758 }; 1759 1760 static struct clk_branch cam_cc_csiphy5_clk = { 1761 .halt_reg = 0x100c0, 1762 .halt_check = BRANCH_HALT, 1763 .clkr = { 1764 .enable_reg = 0x100c0, 1765 .enable_mask = BIT(0), 1766 .hw.init = &(const struct clk_init_data) { 1767 .name = "cam_cc_csiphy5_clk", 1768 .parent_hws = (const struct clk_hw*[]) { 1769 &cam_cc_cphy_rx_clk_src.clkr.hw, 1770 }, 1771 .num_parents = 1, 1772 .flags = CLK_SET_RATE_PARENT, 1773 .ops = &clk_branch2_ops, 1774 }, 1775 }, 1776 }; 1777 1778 static struct clk_branch cam_cc_icp_0_ahb_clk = { 1779 .halt_reg = 0x11264, 1780 .halt_check = BRANCH_HALT, 1781 .clkr = { 1782 .enable_reg = 0x11264, 1783 .enable_mask = BIT(0), 1784 .hw.init = &(const struct clk_init_data) { 1785 .name = "cam_cc_icp_0_ahb_clk", 1786 .parent_hws = (const struct clk_hw*[]) { 1787 &cam_cc_slow_ahb_clk_src.clkr.hw, 1788 }, 1789 .num_parents = 1, 1790 .flags = CLK_SET_RATE_PARENT, 1791 .ops = &clk_branch2_ops, 1792 }, 1793 }, 1794 }; 1795 1796 static struct clk_branch cam_cc_icp_0_clk = { 1797 .halt_reg = 0x1122c, 1798 .halt_check = BRANCH_HALT, 1799 .clkr = { 1800 .enable_reg = 0x1122c, 1801 .enable_mask = BIT(0), 1802 .hw.init = &(const struct clk_init_data) { 1803 .name = "cam_cc_icp_0_clk", 1804 .parent_hws = (const struct clk_hw*[]) { 1805 &cam_cc_icp_0_clk_src.clkr.hw, 1806 }, 1807 .num_parents = 1, 1808 .flags = CLK_SET_RATE_PARENT, 1809 .ops = &clk_branch2_ops, 1810 }, 1811 }, 1812 }; 1813 1814 static struct clk_branch cam_cc_icp_1_ahb_clk = { 1815 .halt_reg = 0x11268, 1816 .halt_check = BRANCH_HALT, 1817 .clkr = { 1818 .enable_reg = 0x11268, 1819 .enable_mask = BIT(0), 1820 .hw.init = &(const struct clk_init_data) { 1821 .name = "cam_cc_icp_1_ahb_clk", 1822 .parent_hws = (const struct clk_hw*[]) { 1823 &cam_cc_slow_ahb_clk_src.clkr.hw, 1824 }, 1825 .num_parents = 1, 1826 .flags = CLK_SET_RATE_PARENT, 1827 .ops = &clk_branch2_ops, 1828 }, 1829 }, 1830 }; 1831 1832 static struct clk_branch cam_cc_icp_1_clk = { 1833 .halt_reg = 0x11254, 1834 .halt_check = BRANCH_HALT, 1835 .clkr = { 1836 .enable_reg = 0x11254, 1837 .enable_mask = BIT(0), 1838 .hw.init = &(const struct clk_init_data) { 1839 .name = "cam_cc_icp_1_clk", 1840 .parent_hws = (const struct clk_hw*[]) { 1841 &cam_cc_icp_1_clk_src.clkr.hw, 1842 }, 1843 .num_parents = 1, 1844 .flags = CLK_SET_RATE_PARENT, 1845 .ops = &clk_branch2_ops, 1846 }, 1847 }, 1848 }; 1849 1850 static struct clk_branch cam_cc_ife_lite_ahb_clk = { 1851 .halt_reg = 0x111a8, 1852 .halt_check = BRANCH_HALT, 1853 .clkr = { 1854 .enable_reg = 0x111a8, 1855 .enable_mask = BIT(0), 1856 .hw.init = &(const struct clk_init_data) { 1857 .name = "cam_cc_ife_lite_ahb_clk", 1858 .parent_hws = (const struct clk_hw*[]) { 1859 &cam_cc_slow_ahb_clk_src.clkr.hw, 1860 }, 1861 .num_parents = 1, 1862 .flags = CLK_SET_RATE_PARENT, 1863 .ops = &clk_branch2_ops, 1864 }, 1865 }, 1866 }; 1867 1868 static struct clk_branch cam_cc_ife_lite_clk = { 1869 .halt_reg = 0x11168, 1870 .halt_check = BRANCH_HALT, 1871 .clkr = { 1872 .enable_reg = 0x11168, 1873 .enable_mask = BIT(0), 1874 .hw.init = &(const struct clk_init_data) { 1875 .name = "cam_cc_ife_lite_clk", 1876 .parent_hws = (const struct clk_hw*[]) { 1877 &cam_cc_ife_lite_clk_src.clkr.hw, 1878 }, 1879 .num_parents = 1, 1880 .flags = CLK_SET_RATE_PARENT, 1881 .ops = &clk_branch2_ops, 1882 }, 1883 }, 1884 }; 1885 1886 static struct clk_branch cam_cc_ife_lite_cphy_rx_clk = { 1887 .halt_reg = 0x111a4, 1888 .halt_check = BRANCH_HALT, 1889 .clkr = { 1890 .enable_reg = 0x111a4, 1891 .enable_mask = BIT(0), 1892 .hw.init = &(const struct clk_init_data) { 1893 .name = "cam_cc_ife_lite_cphy_rx_clk", 1894 .parent_hws = (const struct clk_hw*[]) { 1895 &cam_cc_cphy_rx_clk_src.clkr.hw, 1896 }, 1897 .num_parents = 1, 1898 .flags = CLK_SET_RATE_PARENT, 1899 .ops = &clk_branch2_ops, 1900 }, 1901 }, 1902 }; 1903 1904 static struct clk_branch cam_cc_ife_lite_csid_clk = { 1905 .halt_reg = 0x11194, 1906 .halt_check = BRANCH_HALT, 1907 .clkr = { 1908 .enable_reg = 0x11194, 1909 .enable_mask = BIT(0), 1910 .hw.init = &(const struct clk_init_data) { 1911 .name = "cam_cc_ife_lite_csid_clk", 1912 .parent_hws = (const struct clk_hw*[]) { 1913 &cam_cc_ife_lite_csid_clk_src.clkr.hw, 1914 }, 1915 .num_parents = 1, 1916 .flags = CLK_SET_RATE_PARENT, 1917 .ops = &clk_branch2_ops, 1918 }, 1919 }, 1920 }; 1921 1922 static struct clk_branch cam_cc_ipe_nps_ahb_clk = { 1923 .halt_reg = 0x101d4, 1924 .halt_check = BRANCH_HALT, 1925 .clkr = { 1926 .enable_reg = 0x101d4, 1927 .enable_mask = BIT(0), 1928 .hw.init = &(const struct clk_init_data) { 1929 .name = "cam_cc_ipe_nps_ahb_clk", 1930 .parent_hws = (const struct clk_hw*[]) { 1931 &cam_cc_slow_ahb_clk_src.clkr.hw, 1932 }, 1933 .num_parents = 1, 1934 .flags = CLK_SET_RATE_PARENT, 1935 .ops = &clk_branch2_ops, 1936 }, 1937 }, 1938 }; 1939 1940 static struct clk_branch cam_cc_ipe_nps_clk = { 1941 .halt_reg = 0x101a8, 1942 .halt_check = BRANCH_HALT, 1943 .clkr = { 1944 .enable_reg = 0x101a8, 1945 .enable_mask = BIT(0), 1946 .hw.init = &(const struct clk_init_data) { 1947 .name = "cam_cc_ipe_nps_clk", 1948 .parent_hws = (const struct clk_hw*[]) { 1949 &cam_cc_ipe_nps_clk_src.clkr.hw, 1950 }, 1951 .num_parents = 1, 1952 .flags = CLK_SET_RATE_PARENT, 1953 .ops = &clk_branch2_ops, 1954 }, 1955 }, 1956 }; 1957 1958 static struct clk_branch cam_cc_ipe_nps_fast_ahb_clk = { 1959 .halt_reg = 0x101d8, 1960 .halt_check = BRANCH_HALT, 1961 .clkr = { 1962 .enable_reg = 0x101d8, 1963 .enable_mask = BIT(0), 1964 .hw.init = &(const struct clk_init_data) { 1965 .name = "cam_cc_ipe_nps_fast_ahb_clk", 1966 .parent_hws = (const struct clk_hw*[]) { 1967 &cam_cc_fast_ahb_clk_src.clkr.hw, 1968 }, 1969 .num_parents = 1, 1970 .flags = CLK_SET_RATE_PARENT, 1971 .ops = &clk_branch2_ops, 1972 }, 1973 }, 1974 }; 1975 1976 static struct clk_branch cam_cc_ipe_pps_clk = { 1977 .halt_reg = 0x101bc, 1978 .halt_check = BRANCH_HALT, 1979 .clkr = { 1980 .enable_reg = 0x101bc, 1981 .enable_mask = BIT(0), 1982 .hw.init = &(const struct clk_init_data) { 1983 .name = "cam_cc_ipe_pps_clk", 1984 .parent_hws = (const struct clk_hw*[]) { 1985 &cam_cc_ipe_nps_clk_src.clkr.hw, 1986 }, 1987 .num_parents = 1, 1988 .flags = CLK_SET_RATE_PARENT, 1989 .ops = &clk_branch2_ops, 1990 }, 1991 }, 1992 }; 1993 1994 static struct clk_branch cam_cc_ipe_pps_fast_ahb_clk = { 1995 .halt_reg = 0x101dc, 1996 .halt_check = BRANCH_HALT, 1997 .clkr = { 1998 .enable_reg = 0x101dc, 1999 .enable_mask = BIT(0), 2000 .hw.init = &(const struct clk_init_data) { 2001 .name = "cam_cc_ipe_pps_fast_ahb_clk", 2002 .parent_hws = (const struct clk_hw*[]) { 2003 &cam_cc_fast_ahb_clk_src.clkr.hw, 2004 }, 2005 .num_parents = 1, 2006 .flags = CLK_SET_RATE_PARENT, 2007 .ops = &clk_branch2_ops, 2008 }, 2009 }, 2010 }; 2011 2012 static struct clk_branch cam_cc_jpeg_0_clk = { 2013 .halt_reg = 0x111e8, 2014 .halt_check = BRANCH_HALT, 2015 .clkr = { 2016 .enable_reg = 0x111e8, 2017 .enable_mask = BIT(0), 2018 .hw.init = &(const struct clk_init_data) { 2019 .name = "cam_cc_jpeg_0_clk", 2020 .parent_hws = (const struct clk_hw*[]) { 2021 &cam_cc_jpeg_clk_src.clkr.hw, 2022 }, 2023 .num_parents = 1, 2024 .flags = CLK_SET_RATE_PARENT, 2025 .ops = &clk_branch2_ops, 2026 }, 2027 }, 2028 }; 2029 2030 static struct clk_branch cam_cc_jpeg_1_clk = { 2031 .halt_reg = 0x111f8, 2032 .halt_check = BRANCH_HALT, 2033 .clkr = { 2034 .enable_reg = 0x111f8, 2035 .enable_mask = BIT(0), 2036 .hw.init = &(const struct clk_init_data) { 2037 .name = "cam_cc_jpeg_1_clk", 2038 .parent_hws = (const struct clk_hw*[]) { 2039 &cam_cc_jpeg_clk_src.clkr.hw, 2040 }, 2041 .num_parents = 1, 2042 .flags = CLK_SET_RATE_PARENT, 2043 .ops = &clk_branch2_ops, 2044 }, 2045 }, 2046 }; 2047 2048 static struct clk_branch cam_cc_ofe_ahb_clk = { 2049 .halt_reg = 0x10118, 2050 .halt_check = BRANCH_HALT, 2051 .clkr = { 2052 .enable_reg = 0x10118, 2053 .enable_mask = BIT(0), 2054 .hw.init = &(const struct clk_init_data) { 2055 .name = "cam_cc_ofe_ahb_clk", 2056 .parent_hws = (const struct clk_hw*[]) { 2057 &cam_cc_slow_ahb_clk_src.clkr.hw, 2058 }, 2059 .num_parents = 1, 2060 .flags = CLK_SET_RATE_PARENT, 2061 .ops = &clk_branch2_ops, 2062 }, 2063 }, 2064 }; 2065 2066 static struct clk_branch cam_cc_ofe_anchor_clk = { 2067 .halt_reg = 0x10148, 2068 .halt_check = BRANCH_HALT, 2069 .clkr = { 2070 .enable_reg = 0x10148, 2071 .enable_mask = BIT(0), 2072 .hw.init = &(const struct clk_init_data) { 2073 .name = "cam_cc_ofe_anchor_clk", 2074 .parent_hws = (const struct clk_hw*[]) { 2075 &cam_cc_ofe_clk_src.clkr.hw, 2076 }, 2077 .num_parents = 1, 2078 .flags = CLK_SET_RATE_PARENT, 2079 .ops = &clk_branch2_ops, 2080 }, 2081 }, 2082 }; 2083 2084 static struct clk_branch cam_cc_ofe_anchor_fast_ahb_clk = { 2085 .halt_reg = 0x100f8, 2086 .halt_check = BRANCH_HALT, 2087 .clkr = { 2088 .enable_reg = 0x100f8, 2089 .enable_mask = BIT(0), 2090 .hw.init = &(const struct clk_init_data) { 2091 .name = "cam_cc_ofe_anchor_fast_ahb_clk", 2092 .parent_hws = (const struct clk_hw*[]) { 2093 &cam_cc_fast_ahb_clk_src.clkr.hw, 2094 }, 2095 .num_parents = 1, 2096 .flags = CLK_SET_RATE_PARENT, 2097 .ops = &clk_branch2_ops, 2098 }, 2099 }, 2100 }; 2101 2102 static struct clk_branch cam_cc_ofe_hdr_clk = { 2103 .halt_reg = 0x1015c, 2104 .halt_check = BRANCH_HALT, 2105 .clkr = { 2106 .enable_reg = 0x1015c, 2107 .enable_mask = BIT(0), 2108 .hw.init = &(const struct clk_init_data) { 2109 .name = "cam_cc_ofe_hdr_clk", 2110 .parent_hws = (const struct clk_hw*[]) { 2111 &cam_cc_ofe_clk_src.clkr.hw, 2112 }, 2113 .num_parents = 1, 2114 .flags = CLK_SET_RATE_PARENT, 2115 .ops = &clk_branch2_ops, 2116 }, 2117 }, 2118 }; 2119 2120 static struct clk_branch cam_cc_ofe_hdr_fast_ahb_clk = { 2121 .halt_reg = 0x100fc, 2122 .halt_check = BRANCH_HALT, 2123 .clkr = { 2124 .enable_reg = 0x100fc, 2125 .enable_mask = BIT(0), 2126 .hw.init = &(const struct clk_init_data) { 2127 .name = "cam_cc_ofe_hdr_fast_ahb_clk", 2128 .parent_hws = (const struct clk_hw*[]) { 2129 &cam_cc_fast_ahb_clk_src.clkr.hw, 2130 }, 2131 .num_parents = 1, 2132 .flags = CLK_SET_RATE_PARENT, 2133 .ops = &clk_branch2_ops, 2134 }, 2135 }, 2136 }; 2137 2138 static struct clk_branch cam_cc_ofe_main_clk = { 2139 .halt_reg = 0x10134, 2140 .halt_check = BRANCH_HALT, 2141 .clkr = { 2142 .enable_reg = 0x10134, 2143 .enable_mask = BIT(0), 2144 .hw.init = &(const struct clk_init_data) { 2145 .name = "cam_cc_ofe_main_clk", 2146 .parent_hws = (const struct clk_hw*[]) { 2147 &cam_cc_ofe_clk_src.clkr.hw, 2148 }, 2149 .num_parents = 1, 2150 .flags = CLK_SET_RATE_PARENT, 2151 .ops = &clk_branch2_ops, 2152 }, 2153 }, 2154 }; 2155 2156 static struct clk_branch cam_cc_ofe_main_fast_ahb_clk = { 2157 .halt_reg = 0x100f4, 2158 .halt_check = BRANCH_HALT, 2159 .clkr = { 2160 .enable_reg = 0x100f4, 2161 .enable_mask = BIT(0), 2162 .hw.init = &(const struct clk_init_data) { 2163 .name = "cam_cc_ofe_main_fast_ahb_clk", 2164 .parent_hws = (const struct clk_hw*[]) { 2165 &cam_cc_fast_ahb_clk_src.clkr.hw, 2166 }, 2167 .num_parents = 1, 2168 .flags = CLK_SET_RATE_PARENT, 2169 .ops = &clk_branch2_ops, 2170 }, 2171 }, 2172 }; 2173 2174 static struct clk_branch cam_cc_qdss_debug_clk = { 2175 .halt_reg = 0x11344, 2176 .halt_check = BRANCH_HALT, 2177 .clkr = { 2178 .enable_reg = 0x11344, 2179 .enable_mask = BIT(0), 2180 .hw.init = &(const struct clk_init_data) { 2181 .name = "cam_cc_qdss_debug_clk", 2182 .parent_hws = (const struct clk_hw*[]) { 2183 &cam_cc_qdss_debug_clk_src.clkr.hw, 2184 }, 2185 .num_parents = 1, 2186 .flags = CLK_SET_RATE_PARENT, 2187 .ops = &clk_branch2_ops, 2188 }, 2189 }, 2190 }; 2191 2192 static struct clk_branch cam_cc_qdss_debug_xo_clk = { 2193 .halt_reg = 0x11348, 2194 .halt_check = BRANCH_HALT, 2195 .clkr = { 2196 .enable_reg = 0x11348, 2197 .enable_mask = BIT(0), 2198 .hw.init = &(const struct clk_init_data) { 2199 .name = "cam_cc_qdss_debug_xo_clk", 2200 .parent_hws = (const struct clk_hw*[]) { 2201 &cam_cc_xo_clk_src.clkr.hw, 2202 }, 2203 .num_parents = 1, 2204 .flags = CLK_SET_RATE_PARENT, 2205 .ops = &clk_branch2_ops, 2206 }, 2207 }, 2208 }; 2209 2210 static struct clk_branch cam_cc_tfe_0_bayer_clk = { 2211 .halt_reg = 0x11044, 2212 .halt_check = BRANCH_HALT, 2213 .clkr = { 2214 .enable_reg = 0x11044, 2215 .enable_mask = BIT(0), 2216 .hw.init = &(const struct clk_init_data) { 2217 .name = "cam_cc_tfe_0_bayer_clk", 2218 .parent_hws = (const struct clk_hw*[]) { 2219 &cam_cc_tfe_0_clk_src.clkr.hw, 2220 }, 2221 .num_parents = 1, 2222 .flags = CLK_SET_RATE_PARENT, 2223 .ops = &clk_branch2_ops, 2224 }, 2225 }, 2226 }; 2227 2228 static struct clk_branch cam_cc_tfe_0_bayer_fast_ahb_clk = { 2229 .halt_reg = 0x11064, 2230 .halt_check = BRANCH_HALT, 2231 .clkr = { 2232 .enable_reg = 0x11064, 2233 .enable_mask = BIT(0), 2234 .hw.init = &(const struct clk_init_data) { 2235 .name = "cam_cc_tfe_0_bayer_fast_ahb_clk", 2236 .parent_hws = (const struct clk_hw*[]) { 2237 &cam_cc_fast_ahb_clk_src.clkr.hw, 2238 }, 2239 .num_parents = 1, 2240 .flags = CLK_SET_RATE_PARENT, 2241 .ops = &clk_branch2_ops, 2242 }, 2243 }, 2244 }; 2245 2246 static struct clk_branch cam_cc_tfe_0_main_clk = { 2247 .halt_reg = 0x11030, 2248 .halt_check = BRANCH_HALT, 2249 .clkr = { 2250 .enable_reg = 0x11030, 2251 .enable_mask = BIT(0), 2252 .hw.init = &(const struct clk_init_data) { 2253 .name = "cam_cc_tfe_0_main_clk", 2254 .parent_hws = (const struct clk_hw*[]) { 2255 &cam_cc_tfe_0_clk_src.clkr.hw, 2256 }, 2257 .num_parents = 1, 2258 .flags = CLK_SET_RATE_PARENT, 2259 .ops = &clk_branch2_ops, 2260 }, 2261 }, 2262 }; 2263 2264 static struct clk_branch cam_cc_tfe_0_main_fast_ahb_clk = { 2265 .halt_reg = 0x11060, 2266 .halt_check = BRANCH_HALT, 2267 .clkr = { 2268 .enable_reg = 0x11060, 2269 .enable_mask = BIT(0), 2270 .hw.init = &(const struct clk_init_data) { 2271 .name = "cam_cc_tfe_0_main_fast_ahb_clk", 2272 .parent_hws = (const struct clk_hw*[]) { 2273 &cam_cc_fast_ahb_clk_src.clkr.hw, 2274 }, 2275 .num_parents = 1, 2276 .flags = CLK_SET_RATE_PARENT, 2277 .ops = &clk_branch2_ops, 2278 }, 2279 }, 2280 }; 2281 2282 static struct clk_branch cam_cc_tfe_1_bayer_clk = { 2283 .halt_reg = 0x110c4, 2284 .halt_check = BRANCH_HALT, 2285 .clkr = { 2286 .enable_reg = 0x110c4, 2287 .enable_mask = BIT(0), 2288 .hw.init = &(const struct clk_init_data) { 2289 .name = "cam_cc_tfe_1_bayer_clk", 2290 .parent_hws = (const struct clk_hw*[]) { 2291 &cam_cc_tfe_1_clk_src.clkr.hw, 2292 }, 2293 .num_parents = 1, 2294 .flags = CLK_SET_RATE_PARENT, 2295 .ops = &clk_branch2_ops, 2296 }, 2297 }, 2298 }; 2299 2300 static struct clk_branch cam_cc_tfe_1_bayer_fast_ahb_clk = { 2301 .halt_reg = 0x110e4, 2302 .halt_check = BRANCH_HALT, 2303 .clkr = { 2304 .enable_reg = 0x110e4, 2305 .enable_mask = BIT(0), 2306 .hw.init = &(const struct clk_init_data) { 2307 .name = "cam_cc_tfe_1_bayer_fast_ahb_clk", 2308 .parent_hws = (const struct clk_hw*[]) { 2309 &cam_cc_fast_ahb_clk_src.clkr.hw, 2310 }, 2311 .num_parents = 1, 2312 .flags = CLK_SET_RATE_PARENT, 2313 .ops = &clk_branch2_ops, 2314 }, 2315 }, 2316 }; 2317 2318 static struct clk_branch cam_cc_tfe_1_main_clk = { 2319 .halt_reg = 0x110b0, 2320 .halt_check = BRANCH_HALT, 2321 .clkr = { 2322 .enable_reg = 0x110b0, 2323 .enable_mask = BIT(0), 2324 .hw.init = &(const struct clk_init_data) { 2325 .name = "cam_cc_tfe_1_main_clk", 2326 .parent_hws = (const struct clk_hw*[]) { 2327 &cam_cc_tfe_1_clk_src.clkr.hw, 2328 }, 2329 .num_parents = 1, 2330 .flags = CLK_SET_RATE_PARENT, 2331 .ops = &clk_branch2_ops, 2332 }, 2333 }, 2334 }; 2335 2336 static struct clk_branch cam_cc_tfe_1_main_fast_ahb_clk = { 2337 .halt_reg = 0x110e0, 2338 .halt_check = BRANCH_HALT, 2339 .clkr = { 2340 .enable_reg = 0x110e0, 2341 .enable_mask = BIT(0), 2342 .hw.init = &(const struct clk_init_data) { 2343 .name = "cam_cc_tfe_1_main_fast_ahb_clk", 2344 .parent_hws = (const struct clk_hw*[]) { 2345 &cam_cc_fast_ahb_clk_src.clkr.hw, 2346 }, 2347 .num_parents = 1, 2348 .flags = CLK_SET_RATE_PARENT, 2349 .ops = &clk_branch2_ops, 2350 }, 2351 }, 2352 }; 2353 2354 static struct clk_branch cam_cc_tfe_2_bayer_clk = { 2355 .halt_reg = 0x1112c, 2356 .halt_check = BRANCH_HALT, 2357 .clkr = { 2358 .enable_reg = 0x1112c, 2359 .enable_mask = BIT(0), 2360 .hw.init = &(const struct clk_init_data) { 2361 .name = "cam_cc_tfe_2_bayer_clk", 2362 .parent_hws = (const struct clk_hw*[]) { 2363 &cam_cc_tfe_2_clk_src.clkr.hw, 2364 }, 2365 .num_parents = 1, 2366 .flags = CLK_SET_RATE_PARENT, 2367 .ops = &clk_branch2_ops, 2368 }, 2369 }, 2370 }; 2371 2372 static struct clk_branch cam_cc_tfe_2_bayer_fast_ahb_clk = { 2373 .halt_reg = 0x1114c, 2374 .halt_check = BRANCH_HALT, 2375 .clkr = { 2376 .enable_reg = 0x1114c, 2377 .enable_mask = BIT(0), 2378 .hw.init = &(const struct clk_init_data) { 2379 .name = "cam_cc_tfe_2_bayer_fast_ahb_clk", 2380 .parent_hws = (const struct clk_hw*[]) { 2381 &cam_cc_fast_ahb_clk_src.clkr.hw, 2382 }, 2383 .num_parents = 1, 2384 .flags = CLK_SET_RATE_PARENT, 2385 .ops = &clk_branch2_ops, 2386 }, 2387 }, 2388 }; 2389 2390 static struct clk_branch cam_cc_tfe_2_main_clk = { 2391 .halt_reg = 0x11118, 2392 .halt_check = BRANCH_HALT, 2393 .clkr = { 2394 .enable_reg = 0x11118, 2395 .enable_mask = BIT(0), 2396 .hw.init = &(const struct clk_init_data) { 2397 .name = "cam_cc_tfe_2_main_clk", 2398 .parent_hws = (const struct clk_hw*[]) { 2399 &cam_cc_tfe_2_clk_src.clkr.hw, 2400 }, 2401 .num_parents = 1, 2402 .flags = CLK_SET_RATE_PARENT, 2403 .ops = &clk_branch2_ops, 2404 }, 2405 }, 2406 }; 2407 2408 static struct clk_branch cam_cc_tfe_2_main_fast_ahb_clk = { 2409 .halt_reg = 0x11148, 2410 .halt_check = BRANCH_HALT, 2411 .clkr = { 2412 .enable_reg = 0x11148, 2413 .enable_mask = BIT(0), 2414 .hw.init = &(const struct clk_init_data) { 2415 .name = "cam_cc_tfe_2_main_fast_ahb_clk", 2416 .parent_hws = (const struct clk_hw*[]) { 2417 &cam_cc_fast_ahb_clk_src.clkr.hw, 2418 }, 2419 .num_parents = 1, 2420 .flags = CLK_SET_RATE_PARENT, 2421 .ops = &clk_branch2_ops, 2422 }, 2423 }, 2424 }; 2425 2426 static struct gdsc cam_cc_titan_top_gdsc = { 2427 .gdscr = 0x1134c, 2428 .en_rest_wait_val = 0x2, 2429 .en_few_wait_val = 0x2, 2430 .clk_dis_wait_val = 0xf, 2431 .pd = { 2432 .name = "cam_cc_titan_top_gdsc", 2433 }, 2434 .pwrsts = PWRSTS_OFF_ON, 2435 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 2436 }; 2437 2438 static struct gdsc cam_cc_ipe_0_gdsc = { 2439 .gdscr = 0x1017c, 2440 .en_rest_wait_val = 0x2, 2441 .en_few_wait_val = 0x2, 2442 .clk_dis_wait_val = 0xf, 2443 .pd = { 2444 .name = "cam_cc_ipe_0_gdsc", 2445 }, 2446 .pwrsts = PWRSTS_OFF_ON, 2447 .parent = &cam_cc_titan_top_gdsc.pd, 2448 .flags = HW_CTRL_TRIGGER | POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 2449 }; 2450 2451 static struct gdsc cam_cc_ofe_gdsc = { 2452 .gdscr = 0x100c8, 2453 .en_rest_wait_val = 0x2, 2454 .en_few_wait_val = 0x2, 2455 .clk_dis_wait_val = 0xf, 2456 .pd = { 2457 .name = "cam_cc_ofe_gdsc", 2458 }, 2459 .pwrsts = PWRSTS_OFF_ON, 2460 .parent = &cam_cc_titan_top_gdsc.pd, 2461 .flags = HW_CTRL_TRIGGER | POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 2462 }; 2463 2464 static struct gdsc cam_cc_tfe_0_gdsc = { 2465 .gdscr = 0x11004, 2466 .en_rest_wait_val = 0x2, 2467 .en_few_wait_val = 0x2, 2468 .clk_dis_wait_val = 0xf, 2469 .pd = { 2470 .name = "cam_cc_tfe_0_gdsc", 2471 }, 2472 .pwrsts = PWRSTS_OFF_ON, 2473 .parent = &cam_cc_titan_top_gdsc.pd, 2474 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 2475 }; 2476 2477 static struct gdsc cam_cc_tfe_1_gdsc = { 2478 .gdscr = 0x11084, 2479 .en_rest_wait_val = 0x2, 2480 .en_few_wait_val = 0x2, 2481 .clk_dis_wait_val = 0xf, 2482 .pd = { 2483 .name = "cam_cc_tfe_1_gdsc", 2484 }, 2485 .pwrsts = PWRSTS_OFF_ON, 2486 .parent = &cam_cc_titan_top_gdsc.pd, 2487 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 2488 }; 2489 2490 static struct gdsc cam_cc_tfe_2_gdsc = { 2491 .gdscr = 0x110ec, 2492 .en_rest_wait_val = 0x2, 2493 .en_few_wait_val = 0x2, 2494 .clk_dis_wait_val = 0xf, 2495 .pd = { 2496 .name = "cam_cc_tfe_2_gdsc", 2497 }, 2498 .pwrsts = PWRSTS_OFF_ON, 2499 .parent = &cam_cc_titan_top_gdsc.pd, 2500 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 2501 }; 2502 2503 static struct clk_regmap *cam_cc_sm8750_clocks[] = { 2504 [CAM_CC_CAM_TOP_AHB_CLK] = &cam_cc_cam_top_ahb_clk.clkr, 2505 [CAM_CC_CAM_TOP_FAST_AHB_CLK] = &cam_cc_cam_top_fast_ahb_clk.clkr, 2506 [CAM_CC_CAMNOC_DCD_XO_CLK] = &cam_cc_camnoc_dcd_xo_clk.clkr, 2507 [CAM_CC_CAMNOC_NRT_AXI_CLK] = &cam_cc_camnoc_nrt_axi_clk.clkr, 2508 [CAM_CC_CAMNOC_NRT_CRE_CLK] = &cam_cc_camnoc_nrt_cre_clk.clkr, 2509 [CAM_CC_CAMNOC_NRT_IPE_NPS_CLK] = &cam_cc_camnoc_nrt_ipe_nps_clk.clkr, 2510 [CAM_CC_CAMNOC_NRT_OFE_ANCHOR_CLK] = &cam_cc_camnoc_nrt_ofe_anchor_clk.clkr, 2511 [CAM_CC_CAMNOC_NRT_OFE_HDR_CLK] = &cam_cc_camnoc_nrt_ofe_hdr_clk.clkr, 2512 [CAM_CC_CAMNOC_NRT_OFE_MAIN_CLK] = &cam_cc_camnoc_nrt_ofe_main_clk.clkr, 2513 [CAM_CC_CAMNOC_RT_AXI_CLK] = &cam_cc_camnoc_rt_axi_clk.clkr, 2514 [CAM_CC_CAMNOC_RT_AXI_CLK_SRC] = &cam_cc_camnoc_rt_axi_clk_src.clkr, 2515 [CAM_CC_CAMNOC_RT_IFE_LITE_CLK] = &cam_cc_camnoc_rt_ife_lite_clk.clkr, 2516 [CAM_CC_CAMNOC_RT_TFE_0_BAYER_CLK] = &cam_cc_camnoc_rt_tfe_0_bayer_clk.clkr, 2517 [CAM_CC_CAMNOC_RT_TFE_0_MAIN_CLK] = &cam_cc_camnoc_rt_tfe_0_main_clk.clkr, 2518 [CAM_CC_CAMNOC_RT_TFE_1_BAYER_CLK] = &cam_cc_camnoc_rt_tfe_1_bayer_clk.clkr, 2519 [CAM_CC_CAMNOC_RT_TFE_1_MAIN_CLK] = &cam_cc_camnoc_rt_tfe_1_main_clk.clkr, 2520 [CAM_CC_CAMNOC_RT_TFE_2_BAYER_CLK] = &cam_cc_camnoc_rt_tfe_2_bayer_clk.clkr, 2521 [CAM_CC_CAMNOC_RT_TFE_2_MAIN_CLK] = &cam_cc_camnoc_rt_tfe_2_main_clk.clkr, 2522 [CAM_CC_CAMNOC_XO_CLK] = &cam_cc_camnoc_xo_clk.clkr, 2523 [CAM_CC_CCI_0_CLK] = &cam_cc_cci_0_clk.clkr, 2524 [CAM_CC_CCI_0_CLK_SRC] = &cam_cc_cci_0_clk_src.clkr, 2525 [CAM_CC_CCI_1_CLK] = &cam_cc_cci_1_clk.clkr, 2526 [CAM_CC_CCI_1_CLK_SRC] = &cam_cc_cci_1_clk_src.clkr, 2527 [CAM_CC_CCI_2_CLK] = &cam_cc_cci_2_clk.clkr, 2528 [CAM_CC_CCI_2_CLK_SRC] = &cam_cc_cci_2_clk_src.clkr, 2529 [CAM_CC_CORE_AHB_CLK] = &cam_cc_core_ahb_clk.clkr, 2530 [CAM_CC_CPHY_RX_CLK_SRC] = &cam_cc_cphy_rx_clk_src.clkr, 2531 [CAM_CC_CRE_AHB_CLK] = &cam_cc_cre_ahb_clk.clkr, 2532 [CAM_CC_CRE_CLK] = &cam_cc_cre_clk.clkr, 2533 [CAM_CC_CRE_CLK_SRC] = &cam_cc_cre_clk_src.clkr, 2534 [CAM_CC_CSI0PHYTIMER_CLK] = &cam_cc_csi0phytimer_clk.clkr, 2535 [CAM_CC_CSI0PHYTIMER_CLK_SRC] = &cam_cc_csi0phytimer_clk_src.clkr, 2536 [CAM_CC_CSI1PHYTIMER_CLK] = &cam_cc_csi1phytimer_clk.clkr, 2537 [CAM_CC_CSI1PHYTIMER_CLK_SRC] = &cam_cc_csi1phytimer_clk_src.clkr, 2538 [CAM_CC_CSI2PHYTIMER_CLK] = &cam_cc_csi2phytimer_clk.clkr, 2539 [CAM_CC_CSI2PHYTIMER_CLK_SRC] = &cam_cc_csi2phytimer_clk_src.clkr, 2540 [CAM_CC_CSI3PHYTIMER_CLK] = &cam_cc_csi3phytimer_clk.clkr, 2541 [CAM_CC_CSI3PHYTIMER_CLK_SRC] = &cam_cc_csi3phytimer_clk_src.clkr, 2542 [CAM_CC_CSI4PHYTIMER_CLK] = &cam_cc_csi4phytimer_clk.clkr, 2543 [CAM_CC_CSI4PHYTIMER_CLK_SRC] = &cam_cc_csi4phytimer_clk_src.clkr, 2544 [CAM_CC_CSI5PHYTIMER_CLK] = &cam_cc_csi5phytimer_clk.clkr, 2545 [CAM_CC_CSI5PHYTIMER_CLK_SRC] = &cam_cc_csi5phytimer_clk_src.clkr, 2546 [CAM_CC_CSID_CLK] = &cam_cc_csid_clk.clkr, 2547 [CAM_CC_CSID_CLK_SRC] = &cam_cc_csid_clk_src.clkr, 2548 [CAM_CC_CSID_CSIPHY_RX_CLK] = &cam_cc_csid_csiphy_rx_clk.clkr, 2549 [CAM_CC_CSIPHY0_CLK] = &cam_cc_csiphy0_clk.clkr, 2550 [CAM_CC_CSIPHY1_CLK] = &cam_cc_csiphy1_clk.clkr, 2551 [CAM_CC_CSIPHY2_CLK] = &cam_cc_csiphy2_clk.clkr, 2552 [CAM_CC_CSIPHY3_CLK] = &cam_cc_csiphy3_clk.clkr, 2553 [CAM_CC_CSIPHY4_CLK] = &cam_cc_csiphy4_clk.clkr, 2554 [CAM_CC_CSIPHY5_CLK] = &cam_cc_csiphy5_clk.clkr, 2555 [CAM_CC_FAST_AHB_CLK_SRC] = &cam_cc_fast_ahb_clk_src.clkr, 2556 [CAM_CC_ICP_0_AHB_CLK] = &cam_cc_icp_0_ahb_clk.clkr, 2557 [CAM_CC_ICP_0_CLK] = &cam_cc_icp_0_clk.clkr, 2558 [CAM_CC_ICP_0_CLK_SRC] = &cam_cc_icp_0_clk_src.clkr, 2559 [CAM_CC_ICP_1_AHB_CLK] = &cam_cc_icp_1_ahb_clk.clkr, 2560 [CAM_CC_ICP_1_CLK] = &cam_cc_icp_1_clk.clkr, 2561 [CAM_CC_ICP_1_CLK_SRC] = &cam_cc_icp_1_clk_src.clkr, 2562 [CAM_CC_IFE_LITE_AHB_CLK] = &cam_cc_ife_lite_ahb_clk.clkr, 2563 [CAM_CC_IFE_LITE_CLK] = &cam_cc_ife_lite_clk.clkr, 2564 [CAM_CC_IFE_LITE_CLK_SRC] = &cam_cc_ife_lite_clk_src.clkr, 2565 [CAM_CC_IFE_LITE_CPHY_RX_CLK] = &cam_cc_ife_lite_cphy_rx_clk.clkr, 2566 [CAM_CC_IFE_LITE_CSID_CLK] = &cam_cc_ife_lite_csid_clk.clkr, 2567 [CAM_CC_IFE_LITE_CSID_CLK_SRC] = &cam_cc_ife_lite_csid_clk_src.clkr, 2568 [CAM_CC_IPE_NPS_AHB_CLK] = &cam_cc_ipe_nps_ahb_clk.clkr, 2569 [CAM_CC_IPE_NPS_CLK] = &cam_cc_ipe_nps_clk.clkr, 2570 [CAM_CC_IPE_NPS_CLK_SRC] = &cam_cc_ipe_nps_clk_src.clkr, 2571 [CAM_CC_IPE_NPS_FAST_AHB_CLK] = &cam_cc_ipe_nps_fast_ahb_clk.clkr, 2572 [CAM_CC_IPE_PPS_CLK] = &cam_cc_ipe_pps_clk.clkr, 2573 [CAM_CC_IPE_PPS_FAST_AHB_CLK] = &cam_cc_ipe_pps_fast_ahb_clk.clkr, 2574 [CAM_CC_JPEG_0_CLK] = &cam_cc_jpeg_0_clk.clkr, 2575 [CAM_CC_JPEG_1_CLK] = &cam_cc_jpeg_1_clk.clkr, 2576 [CAM_CC_JPEG_CLK_SRC] = &cam_cc_jpeg_clk_src.clkr, 2577 [CAM_CC_OFE_AHB_CLK] = &cam_cc_ofe_ahb_clk.clkr, 2578 [CAM_CC_OFE_ANCHOR_CLK] = &cam_cc_ofe_anchor_clk.clkr, 2579 [CAM_CC_OFE_ANCHOR_FAST_AHB_CLK] = &cam_cc_ofe_anchor_fast_ahb_clk.clkr, 2580 [CAM_CC_OFE_CLK_SRC] = &cam_cc_ofe_clk_src.clkr, 2581 [CAM_CC_OFE_HDR_CLK] = &cam_cc_ofe_hdr_clk.clkr, 2582 [CAM_CC_OFE_HDR_FAST_AHB_CLK] = &cam_cc_ofe_hdr_fast_ahb_clk.clkr, 2583 [CAM_CC_OFE_MAIN_CLK] = &cam_cc_ofe_main_clk.clkr, 2584 [CAM_CC_OFE_MAIN_FAST_AHB_CLK] = &cam_cc_ofe_main_fast_ahb_clk.clkr, 2585 [CAM_CC_PLL0] = &cam_cc_pll0.clkr, 2586 [CAM_CC_PLL0_OUT_EVEN] = &cam_cc_pll0_out_even.clkr, 2587 [CAM_CC_PLL0_OUT_ODD] = &cam_cc_pll0_out_odd.clkr, 2588 [CAM_CC_PLL1] = &cam_cc_pll1.clkr, 2589 [CAM_CC_PLL1_OUT_EVEN] = &cam_cc_pll1_out_even.clkr, 2590 [CAM_CC_PLL2] = &cam_cc_pll2.clkr, 2591 [CAM_CC_PLL2_OUT_EVEN] = &cam_cc_pll2_out_even.clkr, 2592 [CAM_CC_PLL3] = &cam_cc_pll3.clkr, 2593 [CAM_CC_PLL3_OUT_EVEN] = &cam_cc_pll3_out_even.clkr, 2594 [CAM_CC_PLL4] = &cam_cc_pll4.clkr, 2595 [CAM_CC_PLL4_OUT_EVEN] = &cam_cc_pll4_out_even.clkr, 2596 [CAM_CC_PLL5] = &cam_cc_pll5.clkr, 2597 [CAM_CC_PLL5_OUT_EVEN] = &cam_cc_pll5_out_even.clkr, 2598 [CAM_CC_PLL6] = &cam_cc_pll6.clkr, 2599 [CAM_CC_PLL6_OUT_EVEN] = &cam_cc_pll6_out_even.clkr, 2600 [CAM_CC_PLL6_OUT_ODD] = &cam_cc_pll6_out_odd.clkr, 2601 [CAM_CC_QDSS_DEBUG_CLK] = &cam_cc_qdss_debug_clk.clkr, 2602 [CAM_CC_QDSS_DEBUG_CLK_SRC] = &cam_cc_qdss_debug_clk_src.clkr, 2603 [CAM_CC_QDSS_DEBUG_XO_CLK] = &cam_cc_qdss_debug_xo_clk.clkr, 2604 [CAM_CC_SLEEP_CLK_SRC] = &cam_cc_sleep_clk_src.clkr, 2605 [CAM_CC_SLOW_AHB_CLK_SRC] = &cam_cc_slow_ahb_clk_src.clkr, 2606 [CAM_CC_TFE_0_BAYER_CLK] = &cam_cc_tfe_0_bayer_clk.clkr, 2607 [CAM_CC_TFE_0_BAYER_FAST_AHB_CLK] = &cam_cc_tfe_0_bayer_fast_ahb_clk.clkr, 2608 [CAM_CC_TFE_0_CLK_SRC] = &cam_cc_tfe_0_clk_src.clkr, 2609 [CAM_CC_TFE_0_MAIN_CLK] = &cam_cc_tfe_0_main_clk.clkr, 2610 [CAM_CC_TFE_0_MAIN_FAST_AHB_CLK] = &cam_cc_tfe_0_main_fast_ahb_clk.clkr, 2611 [CAM_CC_TFE_1_BAYER_CLK] = &cam_cc_tfe_1_bayer_clk.clkr, 2612 [CAM_CC_TFE_1_BAYER_FAST_AHB_CLK] = &cam_cc_tfe_1_bayer_fast_ahb_clk.clkr, 2613 [CAM_CC_TFE_1_CLK_SRC] = &cam_cc_tfe_1_clk_src.clkr, 2614 [CAM_CC_TFE_1_MAIN_CLK] = &cam_cc_tfe_1_main_clk.clkr, 2615 [CAM_CC_TFE_1_MAIN_FAST_AHB_CLK] = &cam_cc_tfe_1_main_fast_ahb_clk.clkr, 2616 [CAM_CC_TFE_2_BAYER_CLK] = &cam_cc_tfe_2_bayer_clk.clkr, 2617 [CAM_CC_TFE_2_BAYER_FAST_AHB_CLK] = &cam_cc_tfe_2_bayer_fast_ahb_clk.clkr, 2618 [CAM_CC_TFE_2_CLK_SRC] = &cam_cc_tfe_2_clk_src.clkr, 2619 [CAM_CC_TFE_2_MAIN_CLK] = &cam_cc_tfe_2_main_clk.clkr, 2620 [CAM_CC_TFE_2_MAIN_FAST_AHB_CLK] = &cam_cc_tfe_2_main_fast_ahb_clk.clkr, 2621 [CAM_CC_XO_CLK_SRC] = &cam_cc_xo_clk_src.clkr, 2622 }; 2623 2624 static struct gdsc *cam_cc_sm8750_gdscs[] = { 2625 [CAM_CC_TITAN_TOP_GDSC] = &cam_cc_titan_top_gdsc, 2626 [CAM_CC_IPE_0_GDSC] = &cam_cc_ipe_0_gdsc, 2627 [CAM_CC_OFE_GDSC] = &cam_cc_ofe_gdsc, 2628 [CAM_CC_TFE_0_GDSC] = &cam_cc_tfe_0_gdsc, 2629 [CAM_CC_TFE_1_GDSC] = &cam_cc_tfe_1_gdsc, 2630 [CAM_CC_TFE_2_GDSC] = &cam_cc_tfe_2_gdsc, 2631 }; 2632 2633 static const struct qcom_reset_map cam_cc_sm8750_resets[] = { 2634 [CAM_CC_DRV_BCR] = { 0x113bc }, 2635 [CAM_CC_ICP_BCR] = { 0x11210 }, 2636 [CAM_CC_IPE_0_BCR] = { 0x10178 }, 2637 [CAM_CC_OFE_BCR] = { 0x100c4 }, 2638 [CAM_CC_QDSS_DEBUG_BCR] = { 0x11328 }, 2639 [CAM_CC_TFE_0_BCR] = { 0x11000 }, 2640 [CAM_CC_TFE_1_BCR] = { 0x11080 }, 2641 [CAM_CC_TFE_2_BCR] = { 0x110e8 }, 2642 }; 2643 2644 static struct clk_alpha_pll *cam_cc_sm8750_plls[] = { 2645 &cam_cc_pll0, 2646 &cam_cc_pll1, 2647 &cam_cc_pll2, 2648 &cam_cc_pll3, 2649 &cam_cc_pll4, 2650 &cam_cc_pll5, 2651 &cam_cc_pll6, 2652 }; 2653 2654 static u32 cam_cc_sm8750_critical_cbcrs[] = { 2655 0x113c4, /* CAM_CC_DRV_AHB_CLK */ 2656 0x113c0, /* CAM_CC_DRV_XO_CLK */ 2657 0x1137c, /* CAM_CC_GDSC_CLK */ 2658 0x11398, /* CAM_CC_SLEEP_CLK */ 2659 }; 2660 2661 static const struct regmap_config cam_cc_sm8750_regmap_config = { 2662 .reg_bits = 32, 2663 .reg_stride = 4, 2664 .val_bits = 32, 2665 .max_register = 0x1601c, 2666 .fast_io = true, 2667 }; 2668 2669 static struct qcom_cc_driver_data cam_cc_sm8750_driver_data = { 2670 .alpha_plls = cam_cc_sm8750_plls, 2671 .num_alpha_plls = ARRAY_SIZE(cam_cc_sm8750_plls), 2672 .clk_cbcrs = cam_cc_sm8750_critical_cbcrs, 2673 .num_clk_cbcrs = ARRAY_SIZE(cam_cc_sm8750_critical_cbcrs), 2674 }; 2675 2676 static const struct qcom_cc_desc cam_cc_sm8750_desc = { 2677 .config = &cam_cc_sm8750_regmap_config, 2678 .clks = cam_cc_sm8750_clocks, 2679 .num_clks = ARRAY_SIZE(cam_cc_sm8750_clocks), 2680 .resets = cam_cc_sm8750_resets, 2681 .num_resets = ARRAY_SIZE(cam_cc_sm8750_resets), 2682 .gdscs = cam_cc_sm8750_gdscs, 2683 .num_gdscs = ARRAY_SIZE(cam_cc_sm8750_gdscs), 2684 .use_rpm = true, 2685 .driver_data = &cam_cc_sm8750_driver_data, 2686 }; 2687 2688 static const struct of_device_id cam_cc_sm8750_match_table[] = { 2689 { .compatible = "qcom,sm8750-camcc" }, 2690 { } 2691 }; 2692 MODULE_DEVICE_TABLE(of, cam_cc_sm8750_match_table); 2693 2694 static int cam_cc_sm8750_probe(struct platform_device *pdev) 2695 { 2696 return qcom_cc_probe(pdev, &cam_cc_sm8750_desc); 2697 } 2698 2699 static struct platform_driver cam_cc_sm8750_driver = { 2700 .probe = cam_cc_sm8750_probe, 2701 .driver = { 2702 .name = "camcc-sm8750", 2703 .of_match_table = cam_cc_sm8750_match_table, 2704 }, 2705 }; 2706 2707 module_platform_driver(cam_cc_sm8750_driver); 2708 2709 MODULE_DESCRIPTION("QTI CAMCC SM8750 Driver"); 2710 MODULE_LICENSE("GPL"); 2711