1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 6 #include <linux/clk-provider.h> 7 #include <linux/module.h> 8 #include <linux/of.h> 9 #include <linux/platform_device.h> 10 #include <linux/regmap.h> 11 12 #include <dt-bindings/clock/qcom,qcs615-camcc.h> 13 14 #include "clk-alpha-pll.h" 15 #include "clk-branch.h" 16 #include "clk-pll.h" 17 #include "clk-rcg.h" 18 #include "clk-regmap.h" 19 #include "clk-regmap-divider.h" 20 #include "clk-regmap-mux.h" 21 #include "common.h" 22 #include "gdsc.h" 23 #include "reset.h" 24 25 enum { 26 DT_BI_TCXO, 27 }; 28 29 enum { 30 P_BI_TCXO, 31 P_CAM_CC_PLL0_OUT_AUX, 32 P_CAM_CC_PLL1_OUT_AUX, 33 P_CAM_CC_PLL2_OUT_AUX2, 34 P_CAM_CC_PLL2_OUT_EARLY, 35 P_CAM_CC_PLL3_OUT_MAIN, 36 }; 37 38 static const struct pll_vco brammo_vco[] = { 39 { 500000000, 1250000000, 0 }, 40 }; 41 42 static const struct pll_vco spark_vco[] = { 43 { 1000000000, 2100000000, 0 }, 44 { 750000000, 1500000000, 1 }, 45 { 500000000, 1000000000, 2 }, 46 { 300000000, 500000000, 3 }, 47 { 550000000, 1100000000, 4 }, 48 }; 49 50 /* 600MHz configuration VCO - 2 */ 51 static const struct alpha_pll_config cam_cc_pll0_config = { 52 .l = 0x1f, 53 .alpha_hi = 0x40, 54 .alpha_en_mask = BIT(24), 55 .vco_val = BIT(21), 56 .vco_mask = GENMASK(21, 20), 57 .aux_output_mask = BIT(1), 58 .config_ctl_val = 0x4001055b, 59 .test_ctl_hi_val = 0x1, 60 .test_ctl_hi_mask = 0x1, 61 }; 62 63 static struct clk_alpha_pll cam_cc_pll0 = { 64 .offset = 0x0, 65 .config = &cam_cc_pll0_config, 66 .vco_table = spark_vco, 67 .num_vco = ARRAY_SIZE(spark_vco), 68 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 69 .clkr = { 70 .hw.init = &(const struct clk_init_data) { 71 .name = "cam_cc_pll0", 72 .parent_data = &(const struct clk_parent_data) { 73 .index = DT_BI_TCXO, 74 }, 75 .num_parents = 1, 76 .ops = &clk_alpha_pll_ops, 77 }, 78 }, 79 }; 80 81 /* 808MHz configuration VCO - 2 */ 82 static struct alpha_pll_config cam_cc_pll1_config = { 83 .l = 0x2a, 84 .alpha_hi = 0x15, 85 .alpha = 0x55555555, 86 .alpha_en_mask = BIT(24), 87 .vco_val = BIT(21), 88 .vco_mask = GENMASK(21, 20), 89 .aux_output_mask = BIT(1), 90 .config_ctl_val = 0x4001055b, 91 .test_ctl_hi_val = 0x1, 92 .test_ctl_hi_mask = 0x1, 93 }; 94 95 static struct clk_alpha_pll cam_cc_pll1 = { 96 .offset = 0x1000, 97 .config = &cam_cc_pll1_config, 98 .vco_table = spark_vco, 99 .num_vco = ARRAY_SIZE(spark_vco), 100 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 101 .clkr = { 102 .hw.init = &(const struct clk_init_data) { 103 .name = "cam_cc_pll1", 104 .parent_data = &(const struct clk_parent_data) { 105 .index = DT_BI_TCXO, 106 }, 107 .num_parents = 1, 108 .ops = &clk_alpha_pll_ops, 109 }, 110 }, 111 }; 112 113 /* 960MHz configuration VCO - 0 */ 114 static struct alpha_pll_config cam_cc_pll2_config = { 115 .l = 0x32, 116 .vco_val = 0x0, 117 .vco_mask = GENMASK(21, 20), 118 .early_output_mask = BIT(3), 119 .aux2_output_mask = BIT(2), 120 .post_div_val = 0x1 << 8, 121 .post_div_mask = 0x3 << 8, 122 .config_ctl_val = 0x04289, 123 .test_ctl_val = 0x08000000, 124 .test_ctl_mask = 0x08000000, 125 }; 126 127 static struct clk_alpha_pll cam_cc_pll2 = { 128 .offset = 0x2000, 129 .config = &cam_cc_pll2_config, 130 .vco_table = brammo_vco, 131 .num_vco = ARRAY_SIZE(brammo_vco), 132 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_BRAMMO], 133 .clkr = { 134 .hw.init = &(const struct clk_init_data) { 135 .name = "cam_cc_pll2", 136 .parent_data = &(const struct clk_parent_data) { 137 .index = DT_BI_TCXO, 138 }, 139 .num_parents = 1, 140 .ops = &clk_alpha_pll_ops, 141 }, 142 }, 143 }; 144 145 static const struct clk_div_table post_div_table_cam_cc_pll2_out_aux2[] = { 146 { 0x1, 2 }, 147 { } 148 }; 149 150 static struct clk_alpha_pll_postdiv cam_cc_pll2_out_aux2 = { 151 .offset = 0x2000, 152 .post_div_shift = 8, 153 .post_div_table = post_div_table_cam_cc_pll2_out_aux2, 154 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll2_out_aux2), 155 .width = 2, 156 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_BRAMMO], 157 .clkr.hw.init = &(const struct clk_init_data) { 158 .name = "cam_cc_pll2_out_aux2", 159 .parent_hws = (const struct clk_hw*[]) { 160 &cam_cc_pll2.clkr.hw, 161 }, 162 .num_parents = 1, 163 .ops = &clk_alpha_pll_postdiv_ops, 164 }, 165 }; 166 167 /* 1080MHz configuration - VCO - 0 */ 168 static struct alpha_pll_config cam_cc_pll3_config = { 169 .l = 0x38, 170 .alpha_hi = 0x40, 171 .alpha_en_mask = BIT(24), 172 .vco_val = 0x0, 173 .vco_mask = GENMASK(21, 20), 174 .main_output_mask = BIT(0), 175 .config_ctl_val = 0x4001055b, 176 .test_ctl_hi_val = 0x1, 177 .test_ctl_hi_mask = 0x1, 178 }; 179 180 static struct clk_alpha_pll cam_cc_pll3 = { 181 .offset = 0x3000, 182 .config = &cam_cc_pll3_config, 183 .vco_table = spark_vco, 184 .num_vco = ARRAY_SIZE(spark_vco), 185 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 186 .clkr = { 187 .hw.init = &(const struct clk_init_data) { 188 .name = "cam_cc_pll3", 189 .parent_data = &(const struct clk_parent_data) { 190 .index = DT_BI_TCXO, 191 }, 192 .num_parents = 1, 193 .ops = &clk_alpha_pll_ops, 194 }, 195 }, 196 }; 197 198 static const struct parent_map cam_cc_parent_map_0[] = { 199 { P_BI_TCXO, 0 }, 200 { P_CAM_CC_PLL1_OUT_AUX, 2 }, 201 { P_CAM_CC_PLL0_OUT_AUX, 6 }, 202 }; 203 204 static const struct clk_parent_data cam_cc_parent_data_0[] = { 205 { .index = DT_BI_TCXO }, 206 { .hw = &cam_cc_pll1.clkr.hw }, 207 { .hw = &cam_cc_pll0.clkr.hw }, 208 }; 209 210 static const struct parent_map cam_cc_parent_map_1[] = { 211 { P_BI_TCXO, 0 }, 212 { P_CAM_CC_PLL2_OUT_EARLY, 4 }, 213 { P_CAM_CC_PLL3_OUT_MAIN, 5 }, 214 { P_CAM_CC_PLL0_OUT_AUX, 6 }, 215 }; 216 217 static const struct clk_parent_data cam_cc_parent_data_1[] = { 218 { .index = DT_BI_TCXO }, 219 { .hw = &cam_cc_pll2.clkr.hw }, 220 { .hw = &cam_cc_pll3.clkr.hw }, 221 { .hw = &cam_cc_pll0.clkr.hw }, 222 }; 223 224 static const struct parent_map cam_cc_parent_map_2[] = { 225 { P_BI_TCXO, 0 }, 226 { P_CAM_CC_PLL1_OUT_AUX, 2 }, 227 { P_CAM_CC_PLL2_OUT_EARLY, 4 }, 228 { P_CAM_CC_PLL3_OUT_MAIN, 5 }, 229 { P_CAM_CC_PLL0_OUT_AUX, 6 }, 230 }; 231 232 static const struct clk_parent_data cam_cc_parent_data_2[] = { 233 { .index = DT_BI_TCXO }, 234 { .hw = &cam_cc_pll1.clkr.hw }, 235 { .hw = &cam_cc_pll2.clkr.hw }, 236 { .hw = &cam_cc_pll3.clkr.hw }, 237 { .hw = &cam_cc_pll0.clkr.hw }, 238 }; 239 240 static const struct parent_map cam_cc_parent_map_3[] = { 241 { P_BI_TCXO, 0 }, 242 { P_CAM_CC_PLL2_OUT_AUX2, 1 }, 243 }; 244 245 static const struct clk_parent_data cam_cc_parent_data_3[] = { 246 { .index = DT_BI_TCXO }, 247 { .hw = &cam_cc_pll2_out_aux2.clkr.hw }, 248 }; 249 250 static const struct parent_map cam_cc_parent_map_4[] = { 251 { P_BI_TCXO, 0 }, 252 { P_CAM_CC_PLL3_OUT_MAIN, 5 }, 253 { P_CAM_CC_PLL0_OUT_AUX, 6 }, 254 }; 255 256 static const struct clk_parent_data cam_cc_parent_data_4[] = { 257 { .index = DT_BI_TCXO }, 258 { .hw = &cam_cc_pll3.clkr.hw }, 259 { .hw = &cam_cc_pll0.clkr.hw }, 260 }; 261 262 static const struct parent_map cam_cc_parent_map_5[] = { 263 { P_BI_TCXO, 0 }, 264 { P_CAM_CC_PLL0_OUT_AUX, 6 }, 265 }; 266 267 static const struct clk_parent_data cam_cc_parent_data_5[] = { 268 { .index = DT_BI_TCXO }, 269 { .hw = &cam_cc_pll0.clkr.hw }, 270 }; 271 272 static const struct parent_map cam_cc_parent_map_6[] = { 273 { P_BI_TCXO, 0 }, 274 { P_CAM_CC_PLL1_OUT_AUX, 2 }, 275 { P_CAM_CC_PLL3_OUT_MAIN, 5 }, 276 { P_CAM_CC_PLL0_OUT_AUX, 6 }, 277 }; 278 279 static const struct clk_parent_data cam_cc_parent_data_6[] = { 280 { .index = DT_BI_TCXO }, 281 { .hw = &cam_cc_pll1.clkr.hw }, 282 { .hw = &cam_cc_pll3.clkr.hw }, 283 { .hw = &cam_cc_pll0.clkr.hw }, 284 }; 285 286 static const struct freq_tbl ftbl_cam_cc_bps_clk_src[] = { 287 F(200000000, P_CAM_CC_PLL0_OUT_AUX, 3, 0, 0), 288 F(360000000, P_CAM_CC_PLL3_OUT_MAIN, 3, 0, 0), 289 F(432000000, P_CAM_CC_PLL3_OUT_MAIN, 2.5, 0, 0), 290 F(480000000, P_CAM_CC_PLL2_OUT_EARLY, 2, 0, 0), 291 F(540000000, P_CAM_CC_PLL3_OUT_MAIN, 2, 0, 0), 292 F(600000000, P_CAM_CC_PLL0_OUT_AUX, 1, 0, 0), 293 { } 294 }; 295 296 static struct clk_rcg2 cam_cc_bps_clk_src = { 297 .cmd_rcgr = 0x6010, 298 .mnd_width = 0, 299 .hid_width = 5, 300 .parent_map = cam_cc_parent_map_1, 301 .freq_tbl = ftbl_cam_cc_bps_clk_src, 302 .clkr.hw.init = &(const struct clk_init_data) { 303 .name = "cam_cc_bps_clk_src", 304 .parent_data = cam_cc_parent_data_1, 305 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 306 .ops = &clk_rcg2_shared_ops, 307 }, 308 }; 309 310 static const struct freq_tbl ftbl_cam_cc_cci_clk_src[] = { 311 F(37500000, P_CAM_CC_PLL0_OUT_AUX, 16, 0, 0), 312 F(50000000, P_CAM_CC_PLL0_OUT_AUX, 12, 0, 0), 313 F(100000000, P_CAM_CC_PLL0_OUT_AUX, 6, 0, 0), 314 { } 315 }; 316 317 static struct clk_rcg2 cam_cc_cci_clk_src = { 318 .cmd_rcgr = 0xb0d8, 319 .mnd_width = 8, 320 .hid_width = 5, 321 .parent_map = cam_cc_parent_map_5, 322 .freq_tbl = ftbl_cam_cc_cci_clk_src, 323 .clkr.hw.init = &(const struct clk_init_data) { 324 .name = "cam_cc_cci_clk_src", 325 .parent_data = cam_cc_parent_data_5, 326 .num_parents = ARRAY_SIZE(cam_cc_parent_data_5), 327 .ops = &clk_rcg2_shared_ops, 328 }, 329 }; 330 331 static const struct freq_tbl ftbl_cam_cc_cphy_rx_clk_src[] = { 332 F(100000000, P_CAM_CC_PLL0_OUT_AUX, 6, 0, 0), 333 F(200000000, P_CAM_CC_PLL0_OUT_AUX, 3, 0, 0), 334 F(269333333, P_CAM_CC_PLL1_OUT_AUX, 3, 0, 0), 335 F(320000000, P_CAM_CC_PLL2_OUT_EARLY, 3, 0, 0), 336 F(384000000, P_CAM_CC_PLL2_OUT_EARLY, 2.5, 0, 0), 337 { } 338 }; 339 340 static struct clk_rcg2 cam_cc_cphy_rx_clk_src = { 341 .cmd_rcgr = 0x9064, 342 .mnd_width = 0, 343 .hid_width = 5, 344 .parent_map = cam_cc_parent_map_2, 345 .freq_tbl = ftbl_cam_cc_cphy_rx_clk_src, 346 .clkr.hw.init = &(const struct clk_init_data) { 347 .name = "cam_cc_cphy_rx_clk_src", 348 .parent_data = cam_cc_parent_data_2, 349 .num_parents = ARRAY_SIZE(cam_cc_parent_data_2), 350 .ops = &clk_rcg2_shared_ops, 351 }, 352 }; 353 354 static const struct freq_tbl ftbl_cam_cc_csi0phytimer_clk_src[] = { 355 F(100000000, P_CAM_CC_PLL0_OUT_AUX, 6, 0, 0), 356 F(200000000, P_CAM_CC_PLL0_OUT_AUX, 3, 0, 0), 357 F(269333333, P_CAM_CC_PLL1_OUT_AUX, 3, 0, 0), 358 { } 359 }; 360 361 static struct clk_rcg2 cam_cc_csi0phytimer_clk_src = { 362 .cmd_rcgr = 0x5004, 363 .mnd_width = 0, 364 .hid_width = 5, 365 .parent_map = cam_cc_parent_map_0, 366 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, 367 .clkr.hw.init = &(const struct clk_init_data) { 368 .name = "cam_cc_csi0phytimer_clk_src", 369 .parent_data = cam_cc_parent_data_0, 370 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 371 .ops = &clk_rcg2_shared_ops, 372 }, 373 }; 374 375 static struct clk_rcg2 cam_cc_csi1phytimer_clk_src = { 376 .cmd_rcgr = 0x5028, 377 .mnd_width = 0, 378 .hid_width = 5, 379 .parent_map = cam_cc_parent_map_0, 380 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, 381 .clkr.hw.init = &(const struct clk_init_data) { 382 .name = "cam_cc_csi1phytimer_clk_src", 383 .parent_data = cam_cc_parent_data_0, 384 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 385 .ops = &clk_rcg2_shared_ops, 386 }, 387 }; 388 389 static struct clk_rcg2 cam_cc_csi2phytimer_clk_src = { 390 .cmd_rcgr = 0x504c, 391 .mnd_width = 0, 392 .hid_width = 5, 393 .parent_map = cam_cc_parent_map_0, 394 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, 395 .clkr.hw.init = &(const struct clk_init_data) { 396 .name = "cam_cc_csi2phytimer_clk_src", 397 .parent_data = cam_cc_parent_data_0, 398 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 399 .ops = &clk_rcg2_shared_ops, 400 }, 401 }; 402 403 static const struct freq_tbl ftbl_cam_cc_fast_ahb_clk_src[] = { 404 F(100000000, P_CAM_CC_PLL0_OUT_AUX, 6, 0, 0), 405 F(200000000, P_CAM_CC_PLL0_OUT_AUX, 3, 0, 0), 406 F(300000000, P_CAM_CC_PLL0_OUT_AUX, 2, 0, 0), 407 F(404000000, P_CAM_CC_PLL1_OUT_AUX, 2, 0, 0), 408 { } 409 }; 410 411 static struct clk_rcg2 cam_cc_fast_ahb_clk_src = { 412 .cmd_rcgr = 0x603c, 413 .mnd_width = 0, 414 .hid_width = 5, 415 .parent_map = cam_cc_parent_map_0, 416 .freq_tbl = ftbl_cam_cc_fast_ahb_clk_src, 417 .clkr.hw.init = &(const struct clk_init_data) { 418 .name = "cam_cc_fast_ahb_clk_src", 419 .parent_data = cam_cc_parent_data_0, 420 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 421 .ops = &clk_rcg2_shared_ops, 422 }, 423 }; 424 425 static const struct freq_tbl ftbl_cam_cc_icp_clk_src[] = { 426 F(240000000, P_CAM_CC_PLL0_OUT_AUX, 2.5, 0, 0), 427 F(360000000, P_CAM_CC_PLL3_OUT_MAIN, 3, 0, 0), 428 F(432000000, P_CAM_CC_PLL3_OUT_MAIN, 2.5, 0, 0), 429 F(480000000, P_CAM_CC_PLL2_OUT_EARLY, 2, 0, 0), 430 F(540000000, P_CAM_CC_PLL3_OUT_MAIN, 2, 0, 0), 431 F(600000000, P_CAM_CC_PLL0_OUT_AUX, 1, 0, 0), 432 { } 433 }; 434 435 static struct clk_rcg2 cam_cc_icp_clk_src = { 436 .cmd_rcgr = 0xb088, 437 .mnd_width = 0, 438 .hid_width = 5, 439 .parent_map = cam_cc_parent_map_1, 440 .freq_tbl = ftbl_cam_cc_icp_clk_src, 441 .clkr.hw.init = &(const struct clk_init_data) { 442 .name = "cam_cc_icp_clk_src", 443 .parent_data = cam_cc_parent_data_1, 444 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 445 .ops = &clk_rcg2_shared_ops, 446 }, 447 }; 448 449 static const struct freq_tbl ftbl_cam_cc_ife_0_clk_src[] = { 450 F(240000000, P_CAM_CC_PLL0_OUT_AUX, 2.5, 0, 0), 451 F(360000000, P_CAM_CC_PLL3_OUT_MAIN, 3, 0, 0), 452 F(432000000, P_CAM_CC_PLL3_OUT_MAIN, 2.5, 0, 0), 453 F(540000000, P_CAM_CC_PLL3_OUT_MAIN, 2, 0, 0), 454 F(600000000, P_CAM_CC_PLL0_OUT_AUX, 1, 0, 0), 455 { } 456 }; 457 458 static struct clk_rcg2 cam_cc_ife_0_clk_src = { 459 .cmd_rcgr = 0x9010, 460 .mnd_width = 0, 461 .hid_width = 5, 462 .parent_map = cam_cc_parent_map_4, 463 .freq_tbl = ftbl_cam_cc_ife_0_clk_src, 464 .clkr.hw.init = &(const struct clk_init_data) { 465 .name = "cam_cc_ife_0_clk_src", 466 .parent_data = cam_cc_parent_data_4, 467 .num_parents = ARRAY_SIZE(cam_cc_parent_data_4), 468 .ops = &clk_rcg2_shared_ops, 469 }, 470 }; 471 472 static const struct freq_tbl ftbl_cam_cc_ife_0_csid_clk_src[] = { 473 F(100000000, P_CAM_CC_PLL0_OUT_AUX, 6, 0, 0), 474 F(200000000, P_CAM_CC_PLL0_OUT_AUX, 3, 0, 0), 475 F(320000000, P_CAM_CC_PLL2_OUT_EARLY, 3, 0, 0), 476 F(404000000, P_CAM_CC_PLL1_OUT_AUX, 2, 0, 0), 477 F(480000000, P_CAM_CC_PLL2_OUT_EARLY, 2, 0, 0), 478 F(540000000, P_CAM_CC_PLL3_OUT_MAIN, 2, 0, 0), 479 { } 480 }; 481 482 static struct clk_rcg2 cam_cc_ife_0_csid_clk_src = { 483 .cmd_rcgr = 0x903c, 484 .mnd_width = 0, 485 .hid_width = 5, 486 .parent_map = cam_cc_parent_map_2, 487 .freq_tbl = ftbl_cam_cc_ife_0_csid_clk_src, 488 .clkr.hw.init = &(const struct clk_init_data) { 489 .name = "cam_cc_ife_0_csid_clk_src", 490 .parent_data = cam_cc_parent_data_2, 491 .num_parents = ARRAY_SIZE(cam_cc_parent_data_2), 492 .ops = &clk_rcg2_shared_ops, 493 }, 494 }; 495 496 static struct clk_rcg2 cam_cc_ife_1_clk_src = { 497 .cmd_rcgr = 0xa010, 498 .mnd_width = 0, 499 .hid_width = 5, 500 .parent_map = cam_cc_parent_map_4, 501 .freq_tbl = ftbl_cam_cc_ife_0_clk_src, 502 .clkr.hw.init = &(const struct clk_init_data) { 503 .name = "cam_cc_ife_1_clk_src", 504 .parent_data = cam_cc_parent_data_4, 505 .num_parents = ARRAY_SIZE(cam_cc_parent_data_4), 506 .ops = &clk_rcg2_shared_ops, 507 }, 508 }; 509 510 static struct clk_rcg2 cam_cc_ife_1_csid_clk_src = { 511 .cmd_rcgr = 0xa034, 512 .mnd_width = 0, 513 .hid_width = 5, 514 .parent_map = cam_cc_parent_map_2, 515 .freq_tbl = ftbl_cam_cc_ife_0_csid_clk_src, 516 .clkr.hw.init = &(const struct clk_init_data) { 517 .name = "cam_cc_ife_1_csid_clk_src", 518 .parent_data = cam_cc_parent_data_2, 519 .num_parents = ARRAY_SIZE(cam_cc_parent_data_2), 520 .ops = &clk_rcg2_shared_ops, 521 }, 522 }; 523 524 static struct clk_rcg2 cam_cc_ife_lite_clk_src = { 525 .cmd_rcgr = 0xb004, 526 .mnd_width = 0, 527 .hid_width = 5, 528 .parent_map = cam_cc_parent_map_4, 529 .freq_tbl = ftbl_cam_cc_ife_0_clk_src, 530 .clkr.hw.init = &(const struct clk_init_data) { 531 .name = "cam_cc_ife_lite_clk_src", 532 .parent_data = cam_cc_parent_data_4, 533 .num_parents = ARRAY_SIZE(cam_cc_parent_data_4), 534 .ops = &clk_rcg2_shared_ops, 535 }, 536 }; 537 538 static struct clk_rcg2 cam_cc_ife_lite_csid_clk_src = { 539 .cmd_rcgr = 0xb024, 540 .mnd_width = 0, 541 .hid_width = 5, 542 .parent_map = cam_cc_parent_map_2, 543 .freq_tbl = ftbl_cam_cc_ife_0_csid_clk_src, 544 .clkr.hw.init = &(const struct clk_init_data) { 545 .name = "cam_cc_ife_lite_csid_clk_src", 546 .parent_data = cam_cc_parent_data_2, 547 .num_parents = ARRAY_SIZE(cam_cc_parent_data_2), 548 .ops = &clk_rcg2_shared_ops, 549 }, 550 }; 551 552 static struct clk_rcg2 cam_cc_ipe_0_clk_src = { 553 .cmd_rcgr = 0x7010, 554 .mnd_width = 0, 555 .hid_width = 5, 556 .parent_map = cam_cc_parent_map_1, 557 .freq_tbl = ftbl_cam_cc_icp_clk_src, 558 .clkr.hw.init = &(const struct clk_init_data) { 559 .name = "cam_cc_ipe_0_clk_src", 560 .parent_data = cam_cc_parent_data_1, 561 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 562 .ops = &clk_rcg2_shared_ops, 563 }, 564 }; 565 566 static const struct freq_tbl ftbl_cam_cc_jpeg_clk_src[] = { 567 F(66666667, P_CAM_CC_PLL0_OUT_AUX, 9, 0, 0), 568 F(133333333, P_CAM_CC_PLL0_OUT_AUX, 4.5, 0, 0), 569 F(216000000, P_CAM_CC_PLL3_OUT_MAIN, 5, 0, 0), 570 F(320000000, P_CAM_CC_PLL2_OUT_EARLY, 3, 0, 0), 571 F(480000000, P_CAM_CC_PLL2_OUT_EARLY, 2, 0, 0), 572 F(600000000, P_CAM_CC_PLL0_OUT_AUX, 1, 0, 0), 573 { } 574 }; 575 576 static struct clk_rcg2 cam_cc_jpeg_clk_src = { 577 .cmd_rcgr = 0xb04c, 578 .mnd_width = 0, 579 .hid_width = 5, 580 .parent_map = cam_cc_parent_map_1, 581 .freq_tbl = ftbl_cam_cc_jpeg_clk_src, 582 .clkr.hw.init = &(const struct clk_init_data) { 583 .name = "cam_cc_jpeg_clk_src", 584 .parent_data = cam_cc_parent_data_1, 585 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 586 .ops = &clk_rcg2_shared_ops, 587 }, 588 }; 589 590 static const struct freq_tbl ftbl_cam_cc_lrme_clk_src[] = { 591 F(200000000, P_CAM_CC_PLL0_OUT_AUX, 3, 0, 0), 592 F(216000000, P_CAM_CC_PLL3_OUT_MAIN, 5, 0, 0), 593 F(300000000, P_CAM_CC_PLL0_OUT_AUX, 2, 0, 0), 594 F(404000000, P_CAM_CC_PLL1_OUT_AUX, 2, 0, 0), 595 { } 596 }; 597 598 static struct clk_rcg2 cam_cc_lrme_clk_src = { 599 .cmd_rcgr = 0xb0f8, 600 .mnd_width = 0, 601 .hid_width = 5, 602 .parent_map = cam_cc_parent_map_6, 603 .freq_tbl = ftbl_cam_cc_lrme_clk_src, 604 .clkr.hw.init = &(const struct clk_init_data) { 605 .name = "cam_cc_lrme_clk_src", 606 .parent_data = cam_cc_parent_data_6, 607 .num_parents = ARRAY_SIZE(cam_cc_parent_data_6), 608 .ops = &clk_rcg2_shared_ops, 609 }, 610 }; 611 612 static const struct freq_tbl ftbl_cam_cc_mclk0_clk_src[] = { 613 F(19200000, P_BI_TCXO, 1, 0, 0), 614 F(24000000, P_CAM_CC_PLL2_OUT_AUX2, 10, 1, 2), 615 F(34285714, P_CAM_CC_PLL2_OUT_AUX2, 14, 0, 0), 616 { } 617 }; 618 619 static struct clk_rcg2 cam_cc_mclk0_clk_src = { 620 .cmd_rcgr = 0x4004, 621 .mnd_width = 8, 622 .hid_width = 5, 623 .parent_map = cam_cc_parent_map_3, 624 .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 625 .clkr.hw.init = &(const struct clk_init_data) { 626 .name = "cam_cc_mclk0_clk_src", 627 .parent_data = cam_cc_parent_data_3, 628 .num_parents = ARRAY_SIZE(cam_cc_parent_data_3), 629 .ops = &clk_rcg2_shared_ops, 630 }, 631 }; 632 633 static struct clk_rcg2 cam_cc_mclk1_clk_src = { 634 .cmd_rcgr = 0x4024, 635 .mnd_width = 8, 636 .hid_width = 5, 637 .parent_map = cam_cc_parent_map_3, 638 .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 639 .clkr.hw.init = &(const struct clk_init_data) { 640 .name = "cam_cc_mclk1_clk_src", 641 .parent_data = cam_cc_parent_data_3, 642 .num_parents = ARRAY_SIZE(cam_cc_parent_data_3), 643 .ops = &clk_rcg2_shared_ops, 644 }, 645 }; 646 647 static struct clk_rcg2 cam_cc_mclk2_clk_src = { 648 .cmd_rcgr = 0x4044, 649 .mnd_width = 8, 650 .hid_width = 5, 651 .parent_map = cam_cc_parent_map_3, 652 .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 653 .clkr.hw.init = &(const struct clk_init_data) { 654 .name = "cam_cc_mclk2_clk_src", 655 .parent_data = cam_cc_parent_data_3, 656 .num_parents = ARRAY_SIZE(cam_cc_parent_data_3), 657 .ops = &clk_rcg2_shared_ops, 658 }, 659 }; 660 661 static struct clk_rcg2 cam_cc_mclk3_clk_src = { 662 .cmd_rcgr = 0x4064, 663 .mnd_width = 8, 664 .hid_width = 5, 665 .parent_map = cam_cc_parent_map_3, 666 .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 667 .clkr.hw.init = &(const struct clk_init_data) { 668 .name = "cam_cc_mclk3_clk_src", 669 .parent_data = cam_cc_parent_data_3, 670 .num_parents = ARRAY_SIZE(cam_cc_parent_data_3), 671 .ops = &clk_rcg2_shared_ops, 672 }, 673 }; 674 675 static const struct freq_tbl ftbl_cam_cc_slow_ahb_clk_src[] = { 676 F(80000000, P_CAM_CC_PLL0_OUT_AUX, 7.5, 0, 0), 677 { } 678 }; 679 680 static struct clk_rcg2 cam_cc_slow_ahb_clk_src = { 681 .cmd_rcgr = 0x6058, 682 .mnd_width = 0, 683 .hid_width = 5, 684 .parent_map = cam_cc_parent_map_0, 685 .freq_tbl = ftbl_cam_cc_slow_ahb_clk_src, 686 .clkr.hw.init = &(const struct clk_init_data) { 687 .name = "cam_cc_slow_ahb_clk_src", 688 .parent_data = cam_cc_parent_data_0, 689 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 690 .ops = &clk_rcg2_shared_ops, 691 }, 692 }; 693 694 static struct clk_branch cam_cc_bps_ahb_clk = { 695 .halt_reg = 0x6070, 696 .halt_check = BRANCH_HALT, 697 .clkr = { 698 .enable_reg = 0x6070, 699 .enable_mask = BIT(0), 700 .hw.init = &(const struct clk_init_data) { 701 .name = "cam_cc_bps_ahb_clk", 702 .parent_hws = (const struct clk_hw*[]) { 703 &cam_cc_slow_ahb_clk_src.clkr.hw, 704 }, 705 .num_parents = 1, 706 .flags = CLK_SET_RATE_PARENT, 707 .ops = &clk_branch2_ops, 708 }, 709 }, 710 }; 711 712 static struct clk_branch cam_cc_bps_areg_clk = { 713 .halt_reg = 0x6054, 714 .halt_check = BRANCH_HALT, 715 .clkr = { 716 .enable_reg = 0x6054, 717 .enable_mask = BIT(0), 718 .hw.init = &(const struct clk_init_data) { 719 .name = "cam_cc_bps_areg_clk", 720 .parent_hws = (const struct clk_hw*[]) { 721 &cam_cc_fast_ahb_clk_src.clkr.hw, 722 }, 723 .num_parents = 1, 724 .flags = CLK_SET_RATE_PARENT, 725 .ops = &clk_branch2_ops, 726 }, 727 }, 728 }; 729 730 static struct clk_branch cam_cc_bps_axi_clk = { 731 .halt_reg = 0x6038, 732 .halt_check = BRANCH_HALT, 733 .clkr = { 734 .enable_reg = 0x6038, 735 .enable_mask = BIT(0), 736 .hw.init = &(const struct clk_init_data) { 737 .name = "cam_cc_bps_axi_clk", 738 .ops = &clk_branch2_ops, 739 }, 740 }, 741 }; 742 743 static struct clk_branch cam_cc_bps_clk = { 744 .halt_reg = 0x6028, 745 .halt_check = BRANCH_HALT, 746 .clkr = { 747 .enable_reg = 0x6028, 748 .enable_mask = BIT(0), 749 .hw.init = &(const struct clk_init_data) { 750 .name = "cam_cc_bps_clk", 751 .parent_hws = (const struct clk_hw*[]) { 752 &cam_cc_bps_clk_src.clkr.hw, 753 }, 754 .num_parents = 1, 755 .flags = CLK_SET_RATE_PARENT, 756 .ops = &clk_branch2_ops, 757 }, 758 }, 759 }; 760 761 static struct clk_branch cam_cc_camnoc_axi_clk = { 762 .halt_reg = 0xb124, 763 .halt_check = BRANCH_HALT, 764 .clkr = { 765 .enable_reg = 0xb124, 766 .enable_mask = BIT(0), 767 .hw.init = &(const struct clk_init_data) { 768 .name = "cam_cc_camnoc_axi_clk", 769 .ops = &clk_branch2_ops, 770 }, 771 }, 772 }; 773 774 static struct clk_branch cam_cc_cci_clk = { 775 .halt_reg = 0xb0f0, 776 .halt_check = BRANCH_HALT, 777 .clkr = { 778 .enable_reg = 0xb0f0, 779 .enable_mask = BIT(0), 780 .hw.init = &(const struct clk_init_data) { 781 .name = "cam_cc_cci_clk", 782 .parent_hws = (const struct clk_hw*[]) { 783 &cam_cc_cci_clk_src.clkr.hw, 784 }, 785 .num_parents = 1, 786 .flags = CLK_SET_RATE_PARENT, 787 .ops = &clk_branch2_ops, 788 }, 789 }, 790 }; 791 792 static struct clk_branch cam_cc_core_ahb_clk = { 793 .halt_reg = 0xb144, 794 .halt_check = BRANCH_HALT_VOTED, 795 .clkr = { 796 .enable_reg = 0xb144, 797 .enable_mask = BIT(0), 798 .hw.init = &(const struct clk_init_data) { 799 .name = "cam_cc_core_ahb_clk", 800 .parent_hws = (const struct clk_hw*[]) { 801 &cam_cc_slow_ahb_clk_src.clkr.hw, 802 }, 803 .num_parents = 1, 804 .flags = CLK_SET_RATE_PARENT, 805 .ops = &clk_branch2_ops, 806 }, 807 }, 808 }; 809 810 static struct clk_branch cam_cc_cpas_ahb_clk = { 811 .halt_reg = 0xb11c, 812 .halt_check = BRANCH_HALT, 813 .clkr = { 814 .enable_reg = 0xb11c, 815 .enable_mask = BIT(0), 816 .hw.init = &(const struct clk_init_data) { 817 .name = "cam_cc_cpas_ahb_clk", 818 .parent_hws = (const struct clk_hw*[]) { 819 &cam_cc_slow_ahb_clk_src.clkr.hw, 820 }, 821 .num_parents = 1, 822 .flags = CLK_SET_RATE_PARENT, 823 .ops = &clk_branch2_ops, 824 }, 825 }, 826 }; 827 828 static struct clk_branch cam_cc_csi0phytimer_clk = { 829 .halt_reg = 0x501c, 830 .halt_check = BRANCH_HALT, 831 .clkr = { 832 .enable_reg = 0x501c, 833 .enable_mask = BIT(0), 834 .hw.init = &(const struct clk_init_data) { 835 .name = "cam_cc_csi0phytimer_clk", 836 .parent_hws = (const struct clk_hw*[]) { 837 &cam_cc_csi0phytimer_clk_src.clkr.hw, 838 }, 839 .num_parents = 1, 840 .flags = CLK_SET_RATE_PARENT, 841 .ops = &clk_branch2_ops, 842 }, 843 }, 844 }; 845 846 static struct clk_branch cam_cc_csi1phytimer_clk = { 847 .halt_reg = 0x5040, 848 .halt_check = BRANCH_HALT, 849 .clkr = { 850 .enable_reg = 0x5040, 851 .enable_mask = BIT(0), 852 .hw.init = &(const struct clk_init_data) { 853 .name = "cam_cc_csi1phytimer_clk", 854 .parent_hws = (const struct clk_hw*[]) { 855 &cam_cc_csi1phytimer_clk_src.clkr.hw, 856 }, 857 .num_parents = 1, 858 .flags = CLK_SET_RATE_PARENT, 859 .ops = &clk_branch2_ops, 860 }, 861 }, 862 }; 863 864 static struct clk_branch cam_cc_csi2phytimer_clk = { 865 .halt_reg = 0x5064, 866 .halt_check = BRANCH_HALT, 867 .clkr = { 868 .enable_reg = 0x5064, 869 .enable_mask = BIT(0), 870 .hw.init = &(const struct clk_init_data) { 871 .name = "cam_cc_csi2phytimer_clk", 872 .parent_hws = (const struct clk_hw*[]) { 873 &cam_cc_csi2phytimer_clk_src.clkr.hw, 874 }, 875 .num_parents = 1, 876 .flags = CLK_SET_RATE_PARENT, 877 .ops = &clk_branch2_ops, 878 }, 879 }, 880 }; 881 882 static struct clk_branch cam_cc_csiphy0_clk = { 883 .halt_reg = 0x5020, 884 .halt_check = BRANCH_HALT, 885 .clkr = { 886 .enable_reg = 0x5020, 887 .enable_mask = BIT(0), 888 .hw.init = &(const struct clk_init_data) { 889 .name = "cam_cc_csiphy0_clk", 890 .parent_hws = (const struct clk_hw*[]) { 891 &cam_cc_cphy_rx_clk_src.clkr.hw, 892 }, 893 .num_parents = 1, 894 .flags = CLK_SET_RATE_PARENT, 895 .ops = &clk_branch2_ops, 896 }, 897 }, 898 }; 899 900 static struct clk_branch cam_cc_csiphy1_clk = { 901 .halt_reg = 0x5044, 902 .halt_check = BRANCH_HALT, 903 .clkr = { 904 .enable_reg = 0x5044, 905 .enable_mask = BIT(0), 906 .hw.init = &(const struct clk_init_data) { 907 .name = "cam_cc_csiphy1_clk", 908 .parent_hws = (const struct clk_hw*[]) { 909 &cam_cc_cphy_rx_clk_src.clkr.hw, 910 }, 911 .num_parents = 1, 912 .flags = CLK_SET_RATE_PARENT, 913 .ops = &clk_branch2_ops, 914 }, 915 }, 916 }; 917 918 static struct clk_branch cam_cc_csiphy2_clk = { 919 .halt_reg = 0x5068, 920 .halt_check = BRANCH_HALT, 921 .clkr = { 922 .enable_reg = 0x5068, 923 .enable_mask = BIT(0), 924 .hw.init = &(const struct clk_init_data) { 925 .name = "cam_cc_csiphy2_clk", 926 .parent_hws = (const struct clk_hw*[]) { 927 &cam_cc_cphy_rx_clk_src.clkr.hw, 928 }, 929 .num_parents = 1, 930 .flags = CLK_SET_RATE_PARENT, 931 .ops = &clk_branch2_ops, 932 }, 933 }, 934 }; 935 936 static struct clk_branch cam_cc_icp_clk = { 937 .halt_reg = 0xb0a0, 938 .halt_check = BRANCH_HALT, 939 .clkr = { 940 .enable_reg = 0xb0a0, 941 .enable_mask = BIT(0), 942 .hw.init = &(const struct clk_init_data) { 943 .name = "cam_cc_icp_clk", 944 .parent_hws = (const struct clk_hw*[]) { 945 &cam_cc_icp_clk_src.clkr.hw, 946 }, 947 .num_parents = 1, 948 .flags = CLK_SET_RATE_PARENT, 949 .ops = &clk_branch2_ops, 950 }, 951 }, 952 }; 953 954 static struct clk_branch cam_cc_ife_0_axi_clk = { 955 .halt_reg = 0x9080, 956 .halt_check = BRANCH_HALT, 957 .clkr = { 958 .enable_reg = 0x9080, 959 .enable_mask = BIT(0), 960 .hw.init = &(const struct clk_init_data) { 961 .name = "cam_cc_ife_0_axi_clk", 962 .ops = &clk_branch2_ops, 963 }, 964 }, 965 }; 966 967 static struct clk_branch cam_cc_ife_0_clk = { 968 .halt_reg = 0x9028, 969 .halt_check = BRANCH_HALT, 970 .clkr = { 971 .enable_reg = 0x9028, 972 .enable_mask = BIT(0), 973 .hw.init = &(const struct clk_init_data) { 974 .name = "cam_cc_ife_0_clk", 975 .parent_hws = (const struct clk_hw*[]) { 976 &cam_cc_ife_0_clk_src.clkr.hw, 977 }, 978 .num_parents = 1, 979 .flags = CLK_SET_RATE_PARENT, 980 .ops = &clk_branch2_ops, 981 }, 982 }, 983 }; 984 985 static struct clk_branch cam_cc_ife_0_cphy_rx_clk = { 986 .halt_reg = 0x907c, 987 .halt_check = BRANCH_HALT, 988 .clkr = { 989 .enable_reg = 0x907c, 990 .enable_mask = BIT(0), 991 .hw.init = &(const struct clk_init_data) { 992 .name = "cam_cc_ife_0_cphy_rx_clk", 993 .parent_hws = (const struct clk_hw*[]) { 994 &cam_cc_cphy_rx_clk_src.clkr.hw, 995 }, 996 .num_parents = 1, 997 .flags = CLK_SET_RATE_PARENT, 998 .ops = &clk_branch2_ops, 999 }, 1000 }, 1001 }; 1002 1003 static struct clk_branch cam_cc_ife_0_csid_clk = { 1004 .halt_reg = 0x9054, 1005 .halt_check = BRANCH_HALT, 1006 .clkr = { 1007 .enable_reg = 0x9054, 1008 .enable_mask = BIT(0), 1009 .hw.init = &(const struct clk_init_data) { 1010 .name = "cam_cc_ife_0_csid_clk", 1011 .parent_hws = (const struct clk_hw*[]) { 1012 &cam_cc_ife_0_csid_clk_src.clkr.hw, 1013 }, 1014 .num_parents = 1, 1015 .flags = CLK_SET_RATE_PARENT, 1016 .ops = &clk_branch2_ops, 1017 }, 1018 }, 1019 }; 1020 1021 static struct clk_branch cam_cc_ife_0_dsp_clk = { 1022 .halt_reg = 0x9038, 1023 .halt_check = BRANCH_HALT, 1024 .clkr = { 1025 .enable_reg = 0x9038, 1026 .enable_mask = BIT(0), 1027 .hw.init = &(const struct clk_init_data) { 1028 .name = "cam_cc_ife_0_dsp_clk", 1029 .parent_hws = (const struct clk_hw*[]) { 1030 &cam_cc_ife_0_clk_src.clkr.hw, 1031 }, 1032 .num_parents = 1, 1033 .flags = CLK_SET_RATE_PARENT, 1034 .ops = &clk_branch2_ops, 1035 }, 1036 }, 1037 }; 1038 1039 static struct clk_branch cam_cc_ife_1_axi_clk = { 1040 .halt_reg = 0xa058, 1041 .halt_check = BRANCH_HALT, 1042 .clkr = { 1043 .enable_reg = 0xa058, 1044 .enable_mask = BIT(0), 1045 .hw.init = &(const struct clk_init_data) { 1046 .name = "cam_cc_ife_1_axi_clk", 1047 .ops = &clk_branch2_ops, 1048 }, 1049 }, 1050 }; 1051 1052 static struct clk_branch cam_cc_ife_1_clk = { 1053 .halt_reg = 0xa028, 1054 .halt_check = BRANCH_HALT, 1055 .clkr = { 1056 .enable_reg = 0xa028, 1057 .enable_mask = BIT(0), 1058 .hw.init = &(const struct clk_init_data) { 1059 .name = "cam_cc_ife_1_clk", 1060 .parent_hws = (const struct clk_hw*[]) { 1061 &cam_cc_ife_1_clk_src.clkr.hw, 1062 }, 1063 .num_parents = 1, 1064 .flags = CLK_SET_RATE_PARENT, 1065 .ops = &clk_branch2_ops, 1066 }, 1067 }, 1068 }; 1069 1070 static struct clk_branch cam_cc_ife_1_cphy_rx_clk = { 1071 .halt_reg = 0xa054, 1072 .halt_check = BRANCH_HALT, 1073 .clkr = { 1074 .enable_reg = 0xa054, 1075 .enable_mask = BIT(0), 1076 .hw.init = &(const struct clk_init_data) { 1077 .name = "cam_cc_ife_1_cphy_rx_clk", 1078 .parent_hws = (const struct clk_hw*[]) { 1079 &cam_cc_cphy_rx_clk_src.clkr.hw, 1080 }, 1081 .num_parents = 1, 1082 .flags = CLK_SET_RATE_PARENT, 1083 .ops = &clk_branch2_ops, 1084 }, 1085 }, 1086 }; 1087 1088 static struct clk_branch cam_cc_ife_1_csid_clk = { 1089 .halt_reg = 0xa04c, 1090 .halt_check = BRANCH_HALT, 1091 .clkr = { 1092 .enable_reg = 0xa04c, 1093 .enable_mask = BIT(0), 1094 .hw.init = &(const struct clk_init_data) { 1095 .name = "cam_cc_ife_1_csid_clk", 1096 .parent_hws = (const struct clk_hw*[]) { 1097 &cam_cc_ife_1_csid_clk_src.clkr.hw, 1098 }, 1099 .num_parents = 1, 1100 .flags = CLK_SET_RATE_PARENT, 1101 .ops = &clk_branch2_ops, 1102 }, 1103 }, 1104 }; 1105 1106 static struct clk_branch cam_cc_ife_1_dsp_clk = { 1107 .halt_reg = 0xa030, 1108 .halt_check = BRANCH_HALT, 1109 .clkr = { 1110 .enable_reg = 0xa030, 1111 .enable_mask = BIT(0), 1112 .hw.init = &(const struct clk_init_data) { 1113 .name = "cam_cc_ife_1_dsp_clk", 1114 .parent_hws = (const struct clk_hw*[]) { 1115 &cam_cc_ife_1_clk_src.clkr.hw, 1116 }, 1117 .num_parents = 1, 1118 .flags = CLK_SET_RATE_PARENT, 1119 .ops = &clk_branch2_ops, 1120 }, 1121 }, 1122 }; 1123 1124 static struct clk_branch cam_cc_ife_lite_clk = { 1125 .halt_reg = 0xb01c, 1126 .halt_check = BRANCH_HALT, 1127 .clkr = { 1128 .enable_reg = 0xb01c, 1129 .enable_mask = BIT(0), 1130 .hw.init = &(const struct clk_init_data) { 1131 .name = "cam_cc_ife_lite_clk", 1132 .parent_hws = (const struct clk_hw*[]) { 1133 &cam_cc_ife_lite_clk_src.clkr.hw, 1134 }, 1135 .num_parents = 1, 1136 .flags = CLK_SET_RATE_PARENT, 1137 .ops = &clk_branch2_ops, 1138 }, 1139 }, 1140 }; 1141 1142 static struct clk_branch cam_cc_ife_lite_cphy_rx_clk = { 1143 .halt_reg = 0xb044, 1144 .halt_check = BRANCH_HALT, 1145 .clkr = { 1146 .enable_reg = 0xb044, 1147 .enable_mask = BIT(0), 1148 .hw.init = &(const struct clk_init_data) { 1149 .name = "cam_cc_ife_lite_cphy_rx_clk", 1150 .parent_hws = (const struct clk_hw*[]) { 1151 &cam_cc_cphy_rx_clk_src.clkr.hw, 1152 }, 1153 .num_parents = 1, 1154 .flags = CLK_SET_RATE_PARENT, 1155 .ops = &clk_branch2_ops, 1156 }, 1157 }, 1158 }; 1159 1160 static struct clk_branch cam_cc_ife_lite_csid_clk = { 1161 .halt_reg = 0xb03c, 1162 .halt_check = BRANCH_HALT, 1163 .clkr = { 1164 .enable_reg = 0xb03c, 1165 .enable_mask = BIT(0), 1166 .hw.init = &(const struct clk_init_data) { 1167 .name = "cam_cc_ife_lite_csid_clk", 1168 .parent_hws = (const struct clk_hw*[]) { 1169 &cam_cc_ife_lite_csid_clk_src.clkr.hw, 1170 }, 1171 .num_parents = 1, 1172 .flags = CLK_SET_RATE_PARENT, 1173 .ops = &clk_branch2_ops, 1174 }, 1175 }, 1176 }; 1177 1178 static struct clk_branch cam_cc_ipe_0_ahb_clk = { 1179 .halt_reg = 0x7040, 1180 .halt_check = BRANCH_HALT, 1181 .clkr = { 1182 .enable_reg = 0x7040, 1183 .enable_mask = BIT(0), 1184 .hw.init = &(const struct clk_init_data) { 1185 .name = "cam_cc_ipe_0_ahb_clk", 1186 .parent_hws = (const struct clk_hw*[]) { 1187 &cam_cc_slow_ahb_clk_src.clkr.hw, 1188 }, 1189 .num_parents = 1, 1190 .flags = CLK_SET_RATE_PARENT, 1191 .ops = &clk_branch2_ops, 1192 }, 1193 }, 1194 }; 1195 1196 static struct clk_branch cam_cc_ipe_0_areg_clk = { 1197 .halt_reg = 0x703c, 1198 .halt_check = BRANCH_HALT, 1199 .clkr = { 1200 .enable_reg = 0x703c, 1201 .enable_mask = BIT(0), 1202 .hw.init = &(const struct clk_init_data) { 1203 .name = "cam_cc_ipe_0_areg_clk", 1204 .parent_hws = (const struct clk_hw*[]) { 1205 &cam_cc_fast_ahb_clk_src.clkr.hw, 1206 }, 1207 .num_parents = 1, 1208 .flags = CLK_SET_RATE_PARENT, 1209 .ops = &clk_branch2_ops, 1210 }, 1211 }, 1212 }; 1213 1214 static struct clk_branch cam_cc_ipe_0_axi_clk = { 1215 .halt_reg = 0x7038, 1216 .halt_check = BRANCH_HALT, 1217 .clkr = { 1218 .enable_reg = 0x7038, 1219 .enable_mask = BIT(0), 1220 .hw.init = &(const struct clk_init_data) { 1221 .name = "cam_cc_ipe_0_axi_clk", 1222 .ops = &clk_branch2_ops, 1223 }, 1224 }, 1225 }; 1226 1227 static struct clk_branch cam_cc_ipe_0_clk = { 1228 .halt_reg = 0x7028, 1229 .halt_check = BRANCH_HALT, 1230 .clkr = { 1231 .enable_reg = 0x7028, 1232 .enable_mask = BIT(0), 1233 .hw.init = &(const struct clk_init_data) { 1234 .name = "cam_cc_ipe_0_clk", 1235 .parent_hws = (const struct clk_hw*[]) { 1236 &cam_cc_ipe_0_clk_src.clkr.hw, 1237 }, 1238 .num_parents = 1, 1239 .flags = CLK_SET_RATE_PARENT, 1240 .ops = &clk_branch2_ops, 1241 }, 1242 }, 1243 }; 1244 1245 static struct clk_branch cam_cc_jpeg_clk = { 1246 .halt_reg = 0xb064, 1247 .halt_check = BRANCH_HALT, 1248 .clkr = { 1249 .enable_reg = 0xb064, 1250 .enable_mask = BIT(0), 1251 .hw.init = &(const struct clk_init_data) { 1252 .name = "cam_cc_jpeg_clk", 1253 .parent_hws = (const struct clk_hw*[]) { 1254 &cam_cc_jpeg_clk_src.clkr.hw, 1255 }, 1256 .num_parents = 1, 1257 .flags = CLK_SET_RATE_PARENT, 1258 .ops = &clk_branch2_ops, 1259 }, 1260 }, 1261 }; 1262 1263 static struct clk_branch cam_cc_lrme_clk = { 1264 .halt_reg = 0xb110, 1265 .halt_check = BRANCH_HALT, 1266 .clkr = { 1267 .enable_reg = 0xb110, 1268 .enable_mask = BIT(0), 1269 .hw.init = &(const struct clk_init_data) { 1270 .name = "cam_cc_lrme_clk", 1271 .parent_hws = (const struct clk_hw*[]) { 1272 &cam_cc_lrme_clk_src.clkr.hw, 1273 }, 1274 .num_parents = 1, 1275 .flags = CLK_SET_RATE_PARENT, 1276 .ops = &clk_branch2_ops, 1277 }, 1278 }, 1279 }; 1280 1281 static struct clk_branch cam_cc_mclk0_clk = { 1282 .halt_reg = 0x401c, 1283 .halt_check = BRANCH_HALT, 1284 .clkr = { 1285 .enable_reg = 0x401c, 1286 .enable_mask = BIT(0), 1287 .hw.init = &(const struct clk_init_data) { 1288 .name = "cam_cc_mclk0_clk", 1289 .parent_hws = (const struct clk_hw*[]) { 1290 &cam_cc_mclk0_clk_src.clkr.hw, 1291 }, 1292 .num_parents = 1, 1293 .flags = CLK_SET_RATE_PARENT, 1294 .ops = &clk_branch2_ops, 1295 }, 1296 }, 1297 }; 1298 1299 static struct clk_branch cam_cc_mclk1_clk = { 1300 .halt_reg = 0x403c, 1301 .halt_check = BRANCH_HALT, 1302 .clkr = { 1303 .enable_reg = 0x403c, 1304 .enable_mask = BIT(0), 1305 .hw.init = &(const struct clk_init_data) { 1306 .name = "cam_cc_mclk1_clk", 1307 .parent_hws = (const struct clk_hw*[]) { 1308 &cam_cc_mclk1_clk_src.clkr.hw, 1309 }, 1310 .num_parents = 1, 1311 .flags = CLK_SET_RATE_PARENT, 1312 .ops = &clk_branch2_ops, 1313 }, 1314 }, 1315 }; 1316 1317 static struct clk_branch cam_cc_mclk2_clk = { 1318 .halt_reg = 0x405c, 1319 .halt_check = BRANCH_HALT, 1320 .clkr = { 1321 .enable_reg = 0x405c, 1322 .enable_mask = BIT(0), 1323 .hw.init = &(const struct clk_init_data) { 1324 .name = "cam_cc_mclk2_clk", 1325 .parent_hws = (const struct clk_hw*[]) { 1326 &cam_cc_mclk2_clk_src.clkr.hw, 1327 }, 1328 .num_parents = 1, 1329 .flags = CLK_SET_RATE_PARENT, 1330 .ops = &clk_branch2_ops, 1331 }, 1332 }, 1333 }; 1334 1335 static struct clk_branch cam_cc_mclk3_clk = { 1336 .halt_reg = 0x407c, 1337 .halt_check = BRANCH_HALT, 1338 .clkr = { 1339 .enable_reg = 0x407c, 1340 .enable_mask = BIT(0), 1341 .hw.init = &(const struct clk_init_data) { 1342 .name = "cam_cc_mclk3_clk", 1343 .parent_hws = (const struct clk_hw*[]) { 1344 &cam_cc_mclk3_clk_src.clkr.hw, 1345 }, 1346 .num_parents = 1, 1347 .flags = CLK_SET_RATE_PARENT, 1348 .ops = &clk_branch2_ops, 1349 }, 1350 }, 1351 }; 1352 1353 static struct clk_branch cam_cc_soc_ahb_clk = { 1354 .halt_reg = 0xb140, 1355 .halt_check = BRANCH_HALT, 1356 .clkr = { 1357 .enable_reg = 0xb140, 1358 .enable_mask = BIT(0), 1359 .hw.init = &(const struct clk_init_data) { 1360 .name = "cam_cc_soc_ahb_clk", 1361 .ops = &clk_branch2_ops, 1362 }, 1363 }, 1364 }; 1365 1366 static struct clk_branch cam_cc_sys_tmr_clk = { 1367 .halt_reg = 0xb0a8, 1368 .halt_check = BRANCH_HALT, 1369 .clkr = { 1370 .enable_reg = 0xb0a8, 1371 .enable_mask = BIT(0), 1372 .hw.init = &(const struct clk_init_data) { 1373 .name = "cam_cc_sys_tmr_clk", 1374 .ops = &clk_branch2_ops, 1375 }, 1376 }, 1377 }; 1378 1379 static struct gdsc titan_top_gdsc = { 1380 .gdscr = 0xb134, 1381 .en_rest_wait_val = 0x2, 1382 .en_few_wait_val = 0x2, 1383 .clk_dis_wait_val = 0xf, 1384 .pd = { 1385 .name = "titan_top_gdsc", 1386 }, 1387 .pwrsts = PWRSTS_OFF_ON, 1388 .flags = POLL_CFG_GDSCR, 1389 }; 1390 1391 static struct gdsc bps_gdsc = { 1392 .gdscr = 0x6004, 1393 .en_rest_wait_val = 0x2, 1394 .en_few_wait_val = 0x2, 1395 .clk_dis_wait_val = 0xf, 1396 .pd = { 1397 .name = "bps_gdsc", 1398 }, 1399 .pwrsts = PWRSTS_OFF_ON, 1400 .parent = &titan_top_gdsc.pd, 1401 .flags = POLL_CFG_GDSCR, 1402 }; 1403 1404 static struct gdsc ife_0_gdsc = { 1405 .gdscr = 0x9004, 1406 .en_rest_wait_val = 0x2, 1407 .en_few_wait_val = 0x2, 1408 .clk_dis_wait_val = 0xf, 1409 .pd = { 1410 .name = "ife_0_gdsc", 1411 }, 1412 .pwrsts = PWRSTS_OFF_ON, 1413 .parent = &titan_top_gdsc.pd, 1414 .flags = POLL_CFG_GDSCR, 1415 }; 1416 1417 static struct gdsc ife_1_gdsc = { 1418 .gdscr = 0xa004, 1419 .en_rest_wait_val = 0x2, 1420 .en_few_wait_val = 0x2, 1421 .clk_dis_wait_val = 0xf, 1422 .pd = { 1423 .name = "ife_1_gdsc", 1424 }, 1425 .pwrsts = PWRSTS_OFF_ON, 1426 .parent = &titan_top_gdsc.pd, 1427 .flags = POLL_CFG_GDSCR, 1428 }; 1429 1430 static struct gdsc ipe_0_gdsc = { 1431 .gdscr = 0x7004, 1432 .en_rest_wait_val = 0x2, 1433 .en_few_wait_val = 0x2, 1434 .clk_dis_wait_val = 0xf, 1435 .pd = { 1436 .name = "ipe_0_gdsc", 1437 }, 1438 .pwrsts = PWRSTS_OFF_ON, 1439 .parent = &titan_top_gdsc.pd, 1440 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 1441 }; 1442 1443 static struct clk_regmap *cam_cc_qcs615_clocks[] = { 1444 [CAM_CC_BPS_AHB_CLK] = &cam_cc_bps_ahb_clk.clkr, 1445 [CAM_CC_BPS_AREG_CLK] = &cam_cc_bps_areg_clk.clkr, 1446 [CAM_CC_BPS_AXI_CLK] = &cam_cc_bps_axi_clk.clkr, 1447 [CAM_CC_BPS_CLK] = &cam_cc_bps_clk.clkr, 1448 [CAM_CC_BPS_CLK_SRC] = &cam_cc_bps_clk_src.clkr, 1449 [CAM_CC_CAMNOC_AXI_CLK] = &cam_cc_camnoc_axi_clk.clkr, 1450 [CAM_CC_CCI_CLK] = &cam_cc_cci_clk.clkr, 1451 [CAM_CC_CCI_CLK_SRC] = &cam_cc_cci_clk_src.clkr, 1452 [CAM_CC_CORE_AHB_CLK] = &cam_cc_core_ahb_clk.clkr, 1453 [CAM_CC_CPAS_AHB_CLK] = &cam_cc_cpas_ahb_clk.clkr, 1454 [CAM_CC_CPHY_RX_CLK_SRC] = &cam_cc_cphy_rx_clk_src.clkr, 1455 [CAM_CC_CSI0PHYTIMER_CLK] = &cam_cc_csi0phytimer_clk.clkr, 1456 [CAM_CC_CSI0PHYTIMER_CLK_SRC] = &cam_cc_csi0phytimer_clk_src.clkr, 1457 [CAM_CC_CSI1PHYTIMER_CLK] = &cam_cc_csi1phytimer_clk.clkr, 1458 [CAM_CC_CSI1PHYTIMER_CLK_SRC] = &cam_cc_csi1phytimer_clk_src.clkr, 1459 [CAM_CC_CSI2PHYTIMER_CLK] = &cam_cc_csi2phytimer_clk.clkr, 1460 [CAM_CC_CSI2PHYTIMER_CLK_SRC] = &cam_cc_csi2phytimer_clk_src.clkr, 1461 [CAM_CC_CSIPHY0_CLK] = &cam_cc_csiphy0_clk.clkr, 1462 [CAM_CC_CSIPHY1_CLK] = &cam_cc_csiphy1_clk.clkr, 1463 [CAM_CC_CSIPHY2_CLK] = &cam_cc_csiphy2_clk.clkr, 1464 [CAM_CC_FAST_AHB_CLK_SRC] = &cam_cc_fast_ahb_clk_src.clkr, 1465 [CAM_CC_ICP_CLK] = &cam_cc_icp_clk.clkr, 1466 [CAM_CC_ICP_CLK_SRC] = &cam_cc_icp_clk_src.clkr, 1467 [CAM_CC_IFE_0_AXI_CLK] = &cam_cc_ife_0_axi_clk.clkr, 1468 [CAM_CC_IFE_0_CLK] = &cam_cc_ife_0_clk.clkr, 1469 [CAM_CC_IFE_0_CLK_SRC] = &cam_cc_ife_0_clk_src.clkr, 1470 [CAM_CC_IFE_0_CPHY_RX_CLK] = &cam_cc_ife_0_cphy_rx_clk.clkr, 1471 [CAM_CC_IFE_0_CSID_CLK] = &cam_cc_ife_0_csid_clk.clkr, 1472 [CAM_CC_IFE_0_CSID_CLK_SRC] = &cam_cc_ife_0_csid_clk_src.clkr, 1473 [CAM_CC_IFE_0_DSP_CLK] = &cam_cc_ife_0_dsp_clk.clkr, 1474 [CAM_CC_IFE_1_AXI_CLK] = &cam_cc_ife_1_axi_clk.clkr, 1475 [CAM_CC_IFE_1_CLK] = &cam_cc_ife_1_clk.clkr, 1476 [CAM_CC_IFE_1_CLK_SRC] = &cam_cc_ife_1_clk_src.clkr, 1477 [CAM_CC_IFE_1_CPHY_RX_CLK] = &cam_cc_ife_1_cphy_rx_clk.clkr, 1478 [CAM_CC_IFE_1_CSID_CLK] = &cam_cc_ife_1_csid_clk.clkr, 1479 [CAM_CC_IFE_1_CSID_CLK_SRC] = &cam_cc_ife_1_csid_clk_src.clkr, 1480 [CAM_CC_IFE_1_DSP_CLK] = &cam_cc_ife_1_dsp_clk.clkr, 1481 [CAM_CC_IFE_LITE_CLK] = &cam_cc_ife_lite_clk.clkr, 1482 [CAM_CC_IFE_LITE_CLK_SRC] = &cam_cc_ife_lite_clk_src.clkr, 1483 [CAM_CC_IFE_LITE_CPHY_RX_CLK] = &cam_cc_ife_lite_cphy_rx_clk.clkr, 1484 [CAM_CC_IFE_LITE_CSID_CLK] = &cam_cc_ife_lite_csid_clk.clkr, 1485 [CAM_CC_IFE_LITE_CSID_CLK_SRC] = &cam_cc_ife_lite_csid_clk_src.clkr, 1486 [CAM_CC_IPE_0_AHB_CLK] = &cam_cc_ipe_0_ahb_clk.clkr, 1487 [CAM_CC_IPE_0_AREG_CLK] = &cam_cc_ipe_0_areg_clk.clkr, 1488 [CAM_CC_IPE_0_AXI_CLK] = &cam_cc_ipe_0_axi_clk.clkr, 1489 [CAM_CC_IPE_0_CLK] = &cam_cc_ipe_0_clk.clkr, 1490 [CAM_CC_IPE_0_CLK_SRC] = &cam_cc_ipe_0_clk_src.clkr, 1491 [CAM_CC_JPEG_CLK] = &cam_cc_jpeg_clk.clkr, 1492 [CAM_CC_JPEG_CLK_SRC] = &cam_cc_jpeg_clk_src.clkr, 1493 [CAM_CC_LRME_CLK] = &cam_cc_lrme_clk.clkr, 1494 [CAM_CC_LRME_CLK_SRC] = &cam_cc_lrme_clk_src.clkr, 1495 [CAM_CC_MCLK0_CLK] = &cam_cc_mclk0_clk.clkr, 1496 [CAM_CC_MCLK0_CLK_SRC] = &cam_cc_mclk0_clk_src.clkr, 1497 [CAM_CC_MCLK1_CLK] = &cam_cc_mclk1_clk.clkr, 1498 [CAM_CC_MCLK1_CLK_SRC] = &cam_cc_mclk1_clk_src.clkr, 1499 [CAM_CC_MCLK2_CLK] = &cam_cc_mclk2_clk.clkr, 1500 [CAM_CC_MCLK2_CLK_SRC] = &cam_cc_mclk2_clk_src.clkr, 1501 [CAM_CC_MCLK3_CLK] = &cam_cc_mclk3_clk.clkr, 1502 [CAM_CC_MCLK3_CLK_SRC] = &cam_cc_mclk3_clk_src.clkr, 1503 [CAM_CC_PLL0] = &cam_cc_pll0.clkr, 1504 [CAM_CC_PLL1] = &cam_cc_pll1.clkr, 1505 [CAM_CC_PLL2] = &cam_cc_pll2.clkr, 1506 [CAM_CC_PLL2_OUT_AUX2] = &cam_cc_pll2_out_aux2.clkr, 1507 [CAM_CC_PLL3] = &cam_cc_pll3.clkr, 1508 [CAM_CC_SLOW_AHB_CLK_SRC] = &cam_cc_slow_ahb_clk_src.clkr, 1509 [CAM_CC_SOC_AHB_CLK] = &cam_cc_soc_ahb_clk.clkr, 1510 [CAM_CC_SYS_TMR_CLK] = &cam_cc_sys_tmr_clk.clkr, 1511 }; 1512 1513 static struct gdsc *cam_cc_qcs615_gdscs[] = { 1514 [BPS_GDSC] = &bps_gdsc, 1515 [IFE_0_GDSC] = &ife_0_gdsc, 1516 [IFE_1_GDSC] = &ife_1_gdsc, 1517 [IPE_0_GDSC] = &ipe_0_gdsc, 1518 [TITAN_TOP_GDSC] = &titan_top_gdsc, 1519 }; 1520 1521 static const struct qcom_reset_map cam_cc_qcs615_resets[] = { 1522 [CAM_CC_BPS_BCR] = { 0x6000 }, 1523 [CAM_CC_CAMNOC_BCR] = { 0xb120 }, 1524 [CAM_CC_CCI_BCR] = { 0xb0d4 }, 1525 [CAM_CC_CPAS_BCR] = { 0xb118 }, 1526 [CAM_CC_CSI0PHY_BCR] = { 0x5000 }, 1527 [CAM_CC_CSI1PHY_BCR] = { 0x5024 }, 1528 [CAM_CC_CSI2PHY_BCR] = { 0x5048 }, 1529 [CAM_CC_ICP_BCR] = { 0xb074 }, 1530 [CAM_CC_IFE_0_BCR] = { 0x9000 }, 1531 [CAM_CC_IFE_1_BCR] = { 0xa000 }, 1532 [CAM_CC_IFE_LITE_BCR] = { 0xb000 }, 1533 [CAM_CC_IPE_0_BCR] = { 0x7000 }, 1534 [CAM_CC_JPEG_BCR] = { 0xb048 }, 1535 [CAM_CC_LRME_BCR] = { 0xb0f4 }, 1536 [CAM_CC_MCLK0_BCR] = { 0x4000 }, 1537 [CAM_CC_MCLK1_BCR] = { 0x4020 }, 1538 [CAM_CC_MCLK2_BCR] = { 0x4040 }, 1539 [CAM_CC_MCLK3_BCR] = { 0x4060 }, 1540 [CAM_CC_TITAN_TOP_BCR] = { 0xb130 }, 1541 }; 1542 1543 static struct clk_alpha_pll *cam_cc_qcs615_plls[] = { 1544 &cam_cc_pll0, 1545 &cam_cc_pll1, 1546 &cam_cc_pll2, 1547 &cam_cc_pll3, 1548 }; 1549 1550 static const struct regmap_config cam_cc_qcs615_regmap_config = { 1551 .reg_bits = 32, 1552 .reg_stride = 4, 1553 .val_bits = 32, 1554 .max_register = 0xd004, 1555 .fast_io = true, 1556 }; 1557 1558 static const struct qcom_cc_driver_data cam_cc_qcs615_driver_data = { 1559 .alpha_plls = cam_cc_qcs615_plls, 1560 .num_alpha_plls = ARRAY_SIZE(cam_cc_qcs615_plls), 1561 }; 1562 1563 static const struct qcom_cc_desc cam_cc_qcs615_desc = { 1564 .config = &cam_cc_qcs615_regmap_config, 1565 .clks = cam_cc_qcs615_clocks, 1566 .num_clks = ARRAY_SIZE(cam_cc_qcs615_clocks), 1567 .resets = cam_cc_qcs615_resets, 1568 .num_resets = ARRAY_SIZE(cam_cc_qcs615_resets), 1569 .gdscs = cam_cc_qcs615_gdscs, 1570 .num_gdscs = ARRAY_SIZE(cam_cc_qcs615_gdscs), 1571 .driver_data = &cam_cc_qcs615_driver_data, 1572 }; 1573 1574 static const struct of_device_id cam_cc_qcs615_match_table[] = { 1575 { .compatible = "qcom,qcs615-camcc" }, 1576 { } 1577 }; 1578 MODULE_DEVICE_TABLE(of, cam_cc_qcs615_match_table); 1579 1580 static int cam_cc_qcs615_probe(struct platform_device *pdev) 1581 { 1582 return qcom_cc_probe(pdev, &cam_cc_qcs615_desc); 1583 } 1584 1585 static struct platform_driver cam_cc_qcs615_driver = { 1586 .probe = cam_cc_qcs615_probe, 1587 .driver = { 1588 .name = "camcc-qcs615", 1589 .of_match_table = cam_cc_qcs615_match_table, 1590 }, 1591 }; 1592 1593 module_platform_driver(cam_cc_qcs615_driver); 1594 1595 MODULE_DESCRIPTION("QTI CAMCC QCS615 Driver"); 1596 MODULE_LICENSE("GPL"); 1597