1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 6 #include <linux/clk-provider.h> 7 #include <linux/module.h> 8 #include <linux/mod_devicetable.h> 9 #include <linux/of.h> 10 #include <linux/platform_device.h> 11 #include <linux/regmap.h> 12 13 #include <dt-bindings/clock/qcom,qcs615-camcc.h> 14 15 #include "clk-alpha-pll.h" 16 #include "clk-branch.h" 17 #include "clk-pll.h" 18 #include "clk-rcg.h" 19 #include "clk-regmap.h" 20 #include "clk-regmap-divider.h" 21 #include "clk-regmap-mux.h" 22 #include "common.h" 23 #include "gdsc.h" 24 #include "reset.h" 25 26 enum { 27 DT_BI_TCXO, 28 }; 29 30 enum { 31 P_BI_TCXO, 32 P_CAM_CC_PLL0_OUT_AUX, 33 P_CAM_CC_PLL1_OUT_AUX, 34 P_CAM_CC_PLL2_OUT_AUX2, 35 P_CAM_CC_PLL2_OUT_EARLY, 36 P_CAM_CC_PLL3_OUT_MAIN, 37 }; 38 39 static const struct pll_vco brammo_vco[] = { 40 { 500000000, 1250000000, 0 }, 41 }; 42 43 static const struct pll_vco spark_vco[] = { 44 { 1000000000, 2100000000, 0 }, 45 { 750000000, 1500000000, 1 }, 46 { 500000000, 1000000000, 2 }, 47 { 300000000, 500000000, 3 }, 48 { 550000000, 1100000000, 4 }, 49 }; 50 51 /* 600MHz configuration VCO - 2 */ 52 static const struct alpha_pll_config cam_cc_pll0_config = { 53 .l = 0x1f, 54 .alpha_hi = 0x40, 55 .alpha_en_mask = BIT(24), 56 .vco_val = BIT(21), 57 .vco_mask = GENMASK(21, 20), 58 .aux_output_mask = BIT(1), 59 .config_ctl_val = 0x4001055b, 60 .test_ctl_hi_val = 0x1, 61 .test_ctl_hi_mask = 0x1, 62 }; 63 64 static struct clk_alpha_pll cam_cc_pll0 = { 65 .offset = 0x0, 66 .config = &cam_cc_pll0_config, 67 .vco_table = spark_vco, 68 .num_vco = ARRAY_SIZE(spark_vco), 69 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 70 .clkr = { 71 .hw.init = &(const struct clk_init_data) { 72 .name = "cam_cc_pll0", 73 .parent_data = &(const struct clk_parent_data) { 74 .index = DT_BI_TCXO, 75 }, 76 .num_parents = 1, 77 .ops = &clk_alpha_pll_ops, 78 }, 79 }, 80 }; 81 82 /* 808MHz configuration VCO - 2 */ 83 static struct alpha_pll_config cam_cc_pll1_config = { 84 .l = 0x2a, 85 .alpha_hi = 0x15, 86 .alpha = 0x55555555, 87 .alpha_en_mask = BIT(24), 88 .vco_val = BIT(21), 89 .vco_mask = GENMASK(21, 20), 90 .aux_output_mask = BIT(1), 91 .config_ctl_val = 0x4001055b, 92 .test_ctl_hi_val = 0x1, 93 .test_ctl_hi_mask = 0x1, 94 }; 95 96 static struct clk_alpha_pll cam_cc_pll1 = { 97 .offset = 0x1000, 98 .config = &cam_cc_pll1_config, 99 .vco_table = spark_vco, 100 .num_vco = ARRAY_SIZE(spark_vco), 101 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 102 .clkr = { 103 .hw.init = &(const struct clk_init_data) { 104 .name = "cam_cc_pll1", 105 .parent_data = &(const struct clk_parent_data) { 106 .index = DT_BI_TCXO, 107 }, 108 .num_parents = 1, 109 .ops = &clk_alpha_pll_ops, 110 }, 111 }, 112 }; 113 114 /* 960MHz configuration VCO - 0 */ 115 static struct alpha_pll_config cam_cc_pll2_config = { 116 .l = 0x32, 117 .vco_val = 0x0, 118 .vco_mask = GENMASK(21, 20), 119 .early_output_mask = BIT(3), 120 .aux2_output_mask = BIT(2), 121 .post_div_val = 0x1 << 8, 122 .post_div_mask = 0x3 << 8, 123 .config_ctl_val = 0x04289, 124 .test_ctl_val = 0x08000000, 125 .test_ctl_mask = 0x08000000, 126 }; 127 128 static struct clk_alpha_pll cam_cc_pll2 = { 129 .offset = 0x2000, 130 .config = &cam_cc_pll2_config, 131 .vco_table = brammo_vco, 132 .num_vco = ARRAY_SIZE(brammo_vco), 133 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_BRAMMO], 134 .clkr = { 135 .hw.init = &(const struct clk_init_data) { 136 .name = "cam_cc_pll2", 137 .parent_data = &(const struct clk_parent_data) { 138 .index = DT_BI_TCXO, 139 }, 140 .num_parents = 1, 141 .ops = &clk_alpha_pll_ops, 142 }, 143 }, 144 }; 145 146 static const struct clk_div_table post_div_table_cam_cc_pll2_out_aux2[] = { 147 { 0x1, 2 }, 148 { } 149 }; 150 151 static struct clk_alpha_pll_postdiv cam_cc_pll2_out_aux2 = { 152 .offset = 0x2000, 153 .post_div_shift = 8, 154 .post_div_table = post_div_table_cam_cc_pll2_out_aux2, 155 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll2_out_aux2), 156 .width = 2, 157 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_BRAMMO], 158 .clkr.hw.init = &(const struct clk_init_data) { 159 .name = "cam_cc_pll2_out_aux2", 160 .parent_hws = (const struct clk_hw*[]) { 161 &cam_cc_pll2.clkr.hw, 162 }, 163 .num_parents = 1, 164 .ops = &clk_alpha_pll_postdiv_ops, 165 }, 166 }; 167 168 /* 1080MHz configuration - VCO - 0 */ 169 static struct alpha_pll_config cam_cc_pll3_config = { 170 .l = 0x38, 171 .alpha_hi = 0x40, 172 .alpha_en_mask = BIT(24), 173 .vco_val = 0x0, 174 .vco_mask = GENMASK(21, 20), 175 .main_output_mask = BIT(0), 176 .config_ctl_val = 0x4001055b, 177 .test_ctl_hi_val = 0x1, 178 .test_ctl_hi_mask = 0x1, 179 }; 180 181 static struct clk_alpha_pll cam_cc_pll3 = { 182 .offset = 0x3000, 183 .config = &cam_cc_pll3_config, 184 .vco_table = spark_vco, 185 .num_vco = ARRAY_SIZE(spark_vco), 186 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 187 .clkr = { 188 .hw.init = &(const struct clk_init_data) { 189 .name = "cam_cc_pll3", 190 .parent_data = &(const struct clk_parent_data) { 191 .index = DT_BI_TCXO, 192 }, 193 .num_parents = 1, 194 .ops = &clk_alpha_pll_ops, 195 }, 196 }, 197 }; 198 199 static const struct parent_map cam_cc_parent_map_0[] = { 200 { P_BI_TCXO, 0 }, 201 { P_CAM_CC_PLL1_OUT_AUX, 2 }, 202 { P_CAM_CC_PLL0_OUT_AUX, 6 }, 203 }; 204 205 static const struct clk_parent_data cam_cc_parent_data_0[] = { 206 { .index = DT_BI_TCXO }, 207 { .hw = &cam_cc_pll1.clkr.hw }, 208 { .hw = &cam_cc_pll0.clkr.hw }, 209 }; 210 211 static const struct parent_map cam_cc_parent_map_1[] = { 212 { P_BI_TCXO, 0 }, 213 { P_CAM_CC_PLL2_OUT_EARLY, 4 }, 214 { P_CAM_CC_PLL3_OUT_MAIN, 5 }, 215 { P_CAM_CC_PLL0_OUT_AUX, 6 }, 216 }; 217 218 static const struct clk_parent_data cam_cc_parent_data_1[] = { 219 { .index = DT_BI_TCXO }, 220 { .hw = &cam_cc_pll2.clkr.hw }, 221 { .hw = &cam_cc_pll3.clkr.hw }, 222 { .hw = &cam_cc_pll0.clkr.hw }, 223 }; 224 225 static const struct parent_map cam_cc_parent_map_2[] = { 226 { P_BI_TCXO, 0 }, 227 { P_CAM_CC_PLL1_OUT_AUX, 2 }, 228 { P_CAM_CC_PLL2_OUT_EARLY, 4 }, 229 { P_CAM_CC_PLL3_OUT_MAIN, 5 }, 230 { P_CAM_CC_PLL0_OUT_AUX, 6 }, 231 }; 232 233 static const struct clk_parent_data cam_cc_parent_data_2[] = { 234 { .index = DT_BI_TCXO }, 235 { .hw = &cam_cc_pll1.clkr.hw }, 236 { .hw = &cam_cc_pll2.clkr.hw }, 237 { .hw = &cam_cc_pll3.clkr.hw }, 238 { .hw = &cam_cc_pll0.clkr.hw }, 239 }; 240 241 static const struct parent_map cam_cc_parent_map_3[] = { 242 { P_BI_TCXO, 0 }, 243 { P_CAM_CC_PLL2_OUT_AUX2, 1 }, 244 }; 245 246 static const struct clk_parent_data cam_cc_parent_data_3[] = { 247 { .index = DT_BI_TCXO }, 248 { .hw = &cam_cc_pll2_out_aux2.clkr.hw }, 249 }; 250 251 static const struct parent_map cam_cc_parent_map_4[] = { 252 { P_BI_TCXO, 0 }, 253 { P_CAM_CC_PLL3_OUT_MAIN, 5 }, 254 { P_CAM_CC_PLL0_OUT_AUX, 6 }, 255 }; 256 257 static const struct clk_parent_data cam_cc_parent_data_4[] = { 258 { .index = DT_BI_TCXO }, 259 { .hw = &cam_cc_pll3.clkr.hw }, 260 { .hw = &cam_cc_pll0.clkr.hw }, 261 }; 262 263 static const struct parent_map cam_cc_parent_map_5[] = { 264 { P_BI_TCXO, 0 }, 265 { P_CAM_CC_PLL0_OUT_AUX, 6 }, 266 }; 267 268 static const struct clk_parent_data cam_cc_parent_data_5[] = { 269 { .index = DT_BI_TCXO }, 270 { .hw = &cam_cc_pll0.clkr.hw }, 271 }; 272 273 static const struct parent_map cam_cc_parent_map_6[] = { 274 { P_BI_TCXO, 0 }, 275 { P_CAM_CC_PLL1_OUT_AUX, 2 }, 276 { P_CAM_CC_PLL3_OUT_MAIN, 5 }, 277 { P_CAM_CC_PLL0_OUT_AUX, 6 }, 278 }; 279 280 static const struct clk_parent_data cam_cc_parent_data_6[] = { 281 { .index = DT_BI_TCXO }, 282 { .hw = &cam_cc_pll1.clkr.hw }, 283 { .hw = &cam_cc_pll3.clkr.hw }, 284 { .hw = &cam_cc_pll0.clkr.hw }, 285 }; 286 287 static const struct freq_tbl ftbl_cam_cc_bps_clk_src[] = { 288 F(200000000, P_CAM_CC_PLL0_OUT_AUX, 3, 0, 0), 289 F(360000000, P_CAM_CC_PLL3_OUT_MAIN, 3, 0, 0), 290 F(432000000, P_CAM_CC_PLL3_OUT_MAIN, 2.5, 0, 0), 291 F(480000000, P_CAM_CC_PLL2_OUT_EARLY, 2, 0, 0), 292 F(540000000, P_CAM_CC_PLL3_OUT_MAIN, 2, 0, 0), 293 F(600000000, P_CAM_CC_PLL0_OUT_AUX, 1, 0, 0), 294 { } 295 }; 296 297 static struct clk_rcg2 cam_cc_bps_clk_src = { 298 .cmd_rcgr = 0x6010, 299 .mnd_width = 0, 300 .hid_width = 5, 301 .parent_map = cam_cc_parent_map_1, 302 .freq_tbl = ftbl_cam_cc_bps_clk_src, 303 .clkr.hw.init = &(const struct clk_init_data) { 304 .name = "cam_cc_bps_clk_src", 305 .parent_data = cam_cc_parent_data_1, 306 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 307 .ops = &clk_rcg2_shared_ops, 308 }, 309 }; 310 311 static const struct freq_tbl ftbl_cam_cc_cci_clk_src[] = { 312 F(37500000, P_CAM_CC_PLL0_OUT_AUX, 16, 0, 0), 313 F(50000000, P_CAM_CC_PLL0_OUT_AUX, 12, 0, 0), 314 F(100000000, P_CAM_CC_PLL0_OUT_AUX, 6, 0, 0), 315 { } 316 }; 317 318 static struct clk_rcg2 cam_cc_cci_clk_src = { 319 .cmd_rcgr = 0xb0d8, 320 .mnd_width = 8, 321 .hid_width = 5, 322 .parent_map = cam_cc_parent_map_5, 323 .freq_tbl = ftbl_cam_cc_cci_clk_src, 324 .clkr.hw.init = &(const struct clk_init_data) { 325 .name = "cam_cc_cci_clk_src", 326 .parent_data = cam_cc_parent_data_5, 327 .num_parents = ARRAY_SIZE(cam_cc_parent_data_5), 328 .ops = &clk_rcg2_shared_ops, 329 }, 330 }; 331 332 static const struct freq_tbl ftbl_cam_cc_cphy_rx_clk_src[] = { 333 F(100000000, P_CAM_CC_PLL0_OUT_AUX, 6, 0, 0), 334 F(200000000, P_CAM_CC_PLL0_OUT_AUX, 3, 0, 0), 335 F(269333333, P_CAM_CC_PLL1_OUT_AUX, 3, 0, 0), 336 F(320000000, P_CAM_CC_PLL2_OUT_EARLY, 3, 0, 0), 337 F(384000000, P_CAM_CC_PLL2_OUT_EARLY, 2.5, 0, 0), 338 { } 339 }; 340 341 static struct clk_rcg2 cam_cc_cphy_rx_clk_src = { 342 .cmd_rcgr = 0x9064, 343 .mnd_width = 0, 344 .hid_width = 5, 345 .parent_map = cam_cc_parent_map_2, 346 .freq_tbl = ftbl_cam_cc_cphy_rx_clk_src, 347 .clkr.hw.init = &(const struct clk_init_data) { 348 .name = "cam_cc_cphy_rx_clk_src", 349 .parent_data = cam_cc_parent_data_2, 350 .num_parents = ARRAY_SIZE(cam_cc_parent_data_2), 351 .ops = &clk_rcg2_shared_ops, 352 }, 353 }; 354 355 static const struct freq_tbl ftbl_cam_cc_csi0phytimer_clk_src[] = { 356 F(100000000, P_CAM_CC_PLL0_OUT_AUX, 6, 0, 0), 357 F(200000000, P_CAM_CC_PLL0_OUT_AUX, 3, 0, 0), 358 F(269333333, P_CAM_CC_PLL1_OUT_AUX, 3, 0, 0), 359 { } 360 }; 361 362 static struct clk_rcg2 cam_cc_csi0phytimer_clk_src = { 363 .cmd_rcgr = 0x5004, 364 .mnd_width = 0, 365 .hid_width = 5, 366 .parent_map = cam_cc_parent_map_0, 367 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, 368 .clkr.hw.init = &(const struct clk_init_data) { 369 .name = "cam_cc_csi0phytimer_clk_src", 370 .parent_data = cam_cc_parent_data_0, 371 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 372 .ops = &clk_rcg2_shared_ops, 373 }, 374 }; 375 376 static struct clk_rcg2 cam_cc_csi1phytimer_clk_src = { 377 .cmd_rcgr = 0x5028, 378 .mnd_width = 0, 379 .hid_width = 5, 380 .parent_map = cam_cc_parent_map_0, 381 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, 382 .clkr.hw.init = &(const struct clk_init_data) { 383 .name = "cam_cc_csi1phytimer_clk_src", 384 .parent_data = cam_cc_parent_data_0, 385 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 386 .ops = &clk_rcg2_shared_ops, 387 }, 388 }; 389 390 static struct clk_rcg2 cam_cc_csi2phytimer_clk_src = { 391 .cmd_rcgr = 0x504c, 392 .mnd_width = 0, 393 .hid_width = 5, 394 .parent_map = cam_cc_parent_map_0, 395 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, 396 .clkr.hw.init = &(const struct clk_init_data) { 397 .name = "cam_cc_csi2phytimer_clk_src", 398 .parent_data = cam_cc_parent_data_0, 399 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 400 .ops = &clk_rcg2_shared_ops, 401 }, 402 }; 403 404 static const struct freq_tbl ftbl_cam_cc_fast_ahb_clk_src[] = { 405 F(100000000, P_CAM_CC_PLL0_OUT_AUX, 6, 0, 0), 406 F(200000000, P_CAM_CC_PLL0_OUT_AUX, 3, 0, 0), 407 F(300000000, P_CAM_CC_PLL0_OUT_AUX, 2, 0, 0), 408 F(404000000, P_CAM_CC_PLL1_OUT_AUX, 2, 0, 0), 409 { } 410 }; 411 412 static struct clk_rcg2 cam_cc_fast_ahb_clk_src = { 413 .cmd_rcgr = 0x603c, 414 .mnd_width = 0, 415 .hid_width = 5, 416 .parent_map = cam_cc_parent_map_0, 417 .freq_tbl = ftbl_cam_cc_fast_ahb_clk_src, 418 .clkr.hw.init = &(const struct clk_init_data) { 419 .name = "cam_cc_fast_ahb_clk_src", 420 .parent_data = cam_cc_parent_data_0, 421 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 422 .ops = &clk_rcg2_shared_ops, 423 }, 424 }; 425 426 static const struct freq_tbl ftbl_cam_cc_icp_clk_src[] = { 427 F(240000000, P_CAM_CC_PLL0_OUT_AUX, 2.5, 0, 0), 428 F(360000000, P_CAM_CC_PLL3_OUT_MAIN, 3, 0, 0), 429 F(432000000, P_CAM_CC_PLL3_OUT_MAIN, 2.5, 0, 0), 430 F(480000000, P_CAM_CC_PLL2_OUT_EARLY, 2, 0, 0), 431 F(540000000, P_CAM_CC_PLL3_OUT_MAIN, 2, 0, 0), 432 F(600000000, P_CAM_CC_PLL0_OUT_AUX, 1, 0, 0), 433 { } 434 }; 435 436 static struct clk_rcg2 cam_cc_icp_clk_src = { 437 .cmd_rcgr = 0xb088, 438 .mnd_width = 0, 439 .hid_width = 5, 440 .parent_map = cam_cc_parent_map_1, 441 .freq_tbl = ftbl_cam_cc_icp_clk_src, 442 .clkr.hw.init = &(const struct clk_init_data) { 443 .name = "cam_cc_icp_clk_src", 444 .parent_data = cam_cc_parent_data_1, 445 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 446 .ops = &clk_rcg2_shared_ops, 447 }, 448 }; 449 450 static const struct freq_tbl ftbl_cam_cc_ife_0_clk_src[] = { 451 F(240000000, P_CAM_CC_PLL0_OUT_AUX, 2.5, 0, 0), 452 F(360000000, P_CAM_CC_PLL3_OUT_MAIN, 3, 0, 0), 453 F(432000000, P_CAM_CC_PLL3_OUT_MAIN, 2.5, 0, 0), 454 F(540000000, P_CAM_CC_PLL3_OUT_MAIN, 2, 0, 0), 455 F(600000000, P_CAM_CC_PLL0_OUT_AUX, 1, 0, 0), 456 { } 457 }; 458 459 static struct clk_rcg2 cam_cc_ife_0_clk_src = { 460 .cmd_rcgr = 0x9010, 461 .mnd_width = 0, 462 .hid_width = 5, 463 .parent_map = cam_cc_parent_map_4, 464 .freq_tbl = ftbl_cam_cc_ife_0_clk_src, 465 .clkr.hw.init = &(const struct clk_init_data) { 466 .name = "cam_cc_ife_0_clk_src", 467 .parent_data = cam_cc_parent_data_4, 468 .num_parents = ARRAY_SIZE(cam_cc_parent_data_4), 469 .ops = &clk_rcg2_shared_ops, 470 }, 471 }; 472 473 static const struct freq_tbl ftbl_cam_cc_ife_0_csid_clk_src[] = { 474 F(100000000, P_CAM_CC_PLL0_OUT_AUX, 6, 0, 0), 475 F(200000000, P_CAM_CC_PLL0_OUT_AUX, 3, 0, 0), 476 F(320000000, P_CAM_CC_PLL2_OUT_EARLY, 3, 0, 0), 477 F(404000000, P_CAM_CC_PLL1_OUT_AUX, 2, 0, 0), 478 F(480000000, P_CAM_CC_PLL2_OUT_EARLY, 2, 0, 0), 479 F(540000000, P_CAM_CC_PLL3_OUT_MAIN, 2, 0, 0), 480 { } 481 }; 482 483 static struct clk_rcg2 cam_cc_ife_0_csid_clk_src = { 484 .cmd_rcgr = 0x903c, 485 .mnd_width = 0, 486 .hid_width = 5, 487 .parent_map = cam_cc_parent_map_2, 488 .freq_tbl = ftbl_cam_cc_ife_0_csid_clk_src, 489 .clkr.hw.init = &(const struct clk_init_data) { 490 .name = "cam_cc_ife_0_csid_clk_src", 491 .parent_data = cam_cc_parent_data_2, 492 .num_parents = ARRAY_SIZE(cam_cc_parent_data_2), 493 .ops = &clk_rcg2_shared_ops, 494 }, 495 }; 496 497 static struct clk_rcg2 cam_cc_ife_1_clk_src = { 498 .cmd_rcgr = 0xa010, 499 .mnd_width = 0, 500 .hid_width = 5, 501 .parent_map = cam_cc_parent_map_4, 502 .freq_tbl = ftbl_cam_cc_ife_0_clk_src, 503 .clkr.hw.init = &(const struct clk_init_data) { 504 .name = "cam_cc_ife_1_clk_src", 505 .parent_data = cam_cc_parent_data_4, 506 .num_parents = ARRAY_SIZE(cam_cc_parent_data_4), 507 .ops = &clk_rcg2_shared_ops, 508 }, 509 }; 510 511 static struct clk_rcg2 cam_cc_ife_1_csid_clk_src = { 512 .cmd_rcgr = 0xa034, 513 .mnd_width = 0, 514 .hid_width = 5, 515 .parent_map = cam_cc_parent_map_2, 516 .freq_tbl = ftbl_cam_cc_ife_0_csid_clk_src, 517 .clkr.hw.init = &(const struct clk_init_data) { 518 .name = "cam_cc_ife_1_csid_clk_src", 519 .parent_data = cam_cc_parent_data_2, 520 .num_parents = ARRAY_SIZE(cam_cc_parent_data_2), 521 .ops = &clk_rcg2_shared_ops, 522 }, 523 }; 524 525 static struct clk_rcg2 cam_cc_ife_lite_clk_src = { 526 .cmd_rcgr = 0xb004, 527 .mnd_width = 0, 528 .hid_width = 5, 529 .parent_map = cam_cc_parent_map_4, 530 .freq_tbl = ftbl_cam_cc_ife_0_clk_src, 531 .clkr.hw.init = &(const struct clk_init_data) { 532 .name = "cam_cc_ife_lite_clk_src", 533 .parent_data = cam_cc_parent_data_4, 534 .num_parents = ARRAY_SIZE(cam_cc_parent_data_4), 535 .ops = &clk_rcg2_shared_ops, 536 }, 537 }; 538 539 static struct clk_rcg2 cam_cc_ife_lite_csid_clk_src = { 540 .cmd_rcgr = 0xb024, 541 .mnd_width = 0, 542 .hid_width = 5, 543 .parent_map = cam_cc_parent_map_2, 544 .freq_tbl = ftbl_cam_cc_ife_0_csid_clk_src, 545 .clkr.hw.init = &(const struct clk_init_data) { 546 .name = "cam_cc_ife_lite_csid_clk_src", 547 .parent_data = cam_cc_parent_data_2, 548 .num_parents = ARRAY_SIZE(cam_cc_parent_data_2), 549 .ops = &clk_rcg2_shared_ops, 550 }, 551 }; 552 553 static struct clk_rcg2 cam_cc_ipe_0_clk_src = { 554 .cmd_rcgr = 0x7010, 555 .mnd_width = 0, 556 .hid_width = 5, 557 .parent_map = cam_cc_parent_map_1, 558 .freq_tbl = ftbl_cam_cc_icp_clk_src, 559 .clkr.hw.init = &(const struct clk_init_data) { 560 .name = "cam_cc_ipe_0_clk_src", 561 .parent_data = cam_cc_parent_data_1, 562 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 563 .ops = &clk_rcg2_shared_ops, 564 }, 565 }; 566 567 static const struct freq_tbl ftbl_cam_cc_jpeg_clk_src[] = { 568 F(66666667, P_CAM_CC_PLL0_OUT_AUX, 9, 0, 0), 569 F(133333333, P_CAM_CC_PLL0_OUT_AUX, 4.5, 0, 0), 570 F(216000000, P_CAM_CC_PLL3_OUT_MAIN, 5, 0, 0), 571 F(320000000, P_CAM_CC_PLL2_OUT_EARLY, 3, 0, 0), 572 F(480000000, P_CAM_CC_PLL2_OUT_EARLY, 2, 0, 0), 573 F(600000000, P_CAM_CC_PLL0_OUT_AUX, 1, 0, 0), 574 { } 575 }; 576 577 static struct clk_rcg2 cam_cc_jpeg_clk_src = { 578 .cmd_rcgr = 0xb04c, 579 .mnd_width = 0, 580 .hid_width = 5, 581 .parent_map = cam_cc_parent_map_1, 582 .freq_tbl = ftbl_cam_cc_jpeg_clk_src, 583 .clkr.hw.init = &(const struct clk_init_data) { 584 .name = "cam_cc_jpeg_clk_src", 585 .parent_data = cam_cc_parent_data_1, 586 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 587 .ops = &clk_rcg2_shared_ops, 588 }, 589 }; 590 591 static const struct freq_tbl ftbl_cam_cc_lrme_clk_src[] = { 592 F(200000000, P_CAM_CC_PLL0_OUT_AUX, 3, 0, 0), 593 F(216000000, P_CAM_CC_PLL3_OUT_MAIN, 5, 0, 0), 594 F(300000000, P_CAM_CC_PLL0_OUT_AUX, 2, 0, 0), 595 F(404000000, P_CAM_CC_PLL1_OUT_AUX, 2, 0, 0), 596 { } 597 }; 598 599 static struct clk_rcg2 cam_cc_lrme_clk_src = { 600 .cmd_rcgr = 0xb0f8, 601 .mnd_width = 0, 602 .hid_width = 5, 603 .parent_map = cam_cc_parent_map_6, 604 .freq_tbl = ftbl_cam_cc_lrme_clk_src, 605 .clkr.hw.init = &(const struct clk_init_data) { 606 .name = "cam_cc_lrme_clk_src", 607 .parent_data = cam_cc_parent_data_6, 608 .num_parents = ARRAY_SIZE(cam_cc_parent_data_6), 609 .ops = &clk_rcg2_shared_ops, 610 }, 611 }; 612 613 static const struct freq_tbl ftbl_cam_cc_mclk0_clk_src[] = { 614 F(19200000, P_BI_TCXO, 1, 0, 0), 615 F(24000000, P_CAM_CC_PLL2_OUT_AUX2, 10, 1, 2), 616 F(34285714, P_CAM_CC_PLL2_OUT_AUX2, 14, 0, 0), 617 { } 618 }; 619 620 static struct clk_rcg2 cam_cc_mclk0_clk_src = { 621 .cmd_rcgr = 0x4004, 622 .mnd_width = 8, 623 .hid_width = 5, 624 .parent_map = cam_cc_parent_map_3, 625 .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 626 .clkr.hw.init = &(const struct clk_init_data) { 627 .name = "cam_cc_mclk0_clk_src", 628 .parent_data = cam_cc_parent_data_3, 629 .num_parents = ARRAY_SIZE(cam_cc_parent_data_3), 630 .ops = &clk_rcg2_shared_ops, 631 }, 632 }; 633 634 static struct clk_rcg2 cam_cc_mclk1_clk_src = { 635 .cmd_rcgr = 0x4024, 636 .mnd_width = 8, 637 .hid_width = 5, 638 .parent_map = cam_cc_parent_map_3, 639 .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 640 .clkr.hw.init = &(const struct clk_init_data) { 641 .name = "cam_cc_mclk1_clk_src", 642 .parent_data = cam_cc_parent_data_3, 643 .num_parents = ARRAY_SIZE(cam_cc_parent_data_3), 644 .ops = &clk_rcg2_shared_ops, 645 }, 646 }; 647 648 static struct clk_rcg2 cam_cc_mclk2_clk_src = { 649 .cmd_rcgr = 0x4044, 650 .mnd_width = 8, 651 .hid_width = 5, 652 .parent_map = cam_cc_parent_map_3, 653 .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 654 .clkr.hw.init = &(const struct clk_init_data) { 655 .name = "cam_cc_mclk2_clk_src", 656 .parent_data = cam_cc_parent_data_3, 657 .num_parents = ARRAY_SIZE(cam_cc_parent_data_3), 658 .ops = &clk_rcg2_shared_ops, 659 }, 660 }; 661 662 static struct clk_rcg2 cam_cc_mclk3_clk_src = { 663 .cmd_rcgr = 0x4064, 664 .mnd_width = 8, 665 .hid_width = 5, 666 .parent_map = cam_cc_parent_map_3, 667 .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 668 .clkr.hw.init = &(const struct clk_init_data) { 669 .name = "cam_cc_mclk3_clk_src", 670 .parent_data = cam_cc_parent_data_3, 671 .num_parents = ARRAY_SIZE(cam_cc_parent_data_3), 672 .ops = &clk_rcg2_shared_ops, 673 }, 674 }; 675 676 static const struct freq_tbl ftbl_cam_cc_slow_ahb_clk_src[] = { 677 F(80000000, P_CAM_CC_PLL0_OUT_AUX, 7.5, 0, 0), 678 { } 679 }; 680 681 static struct clk_rcg2 cam_cc_slow_ahb_clk_src = { 682 .cmd_rcgr = 0x6058, 683 .mnd_width = 0, 684 .hid_width = 5, 685 .parent_map = cam_cc_parent_map_0, 686 .freq_tbl = ftbl_cam_cc_slow_ahb_clk_src, 687 .clkr.hw.init = &(const struct clk_init_data) { 688 .name = "cam_cc_slow_ahb_clk_src", 689 .parent_data = cam_cc_parent_data_0, 690 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 691 .ops = &clk_rcg2_shared_ops, 692 }, 693 }; 694 695 static struct clk_branch cam_cc_bps_ahb_clk = { 696 .halt_reg = 0x6070, 697 .halt_check = BRANCH_HALT, 698 .clkr = { 699 .enable_reg = 0x6070, 700 .enable_mask = BIT(0), 701 .hw.init = &(const struct clk_init_data) { 702 .name = "cam_cc_bps_ahb_clk", 703 .parent_hws = (const struct clk_hw*[]) { 704 &cam_cc_slow_ahb_clk_src.clkr.hw, 705 }, 706 .num_parents = 1, 707 .flags = CLK_SET_RATE_PARENT, 708 .ops = &clk_branch2_ops, 709 }, 710 }, 711 }; 712 713 static struct clk_branch cam_cc_bps_areg_clk = { 714 .halt_reg = 0x6054, 715 .halt_check = BRANCH_HALT, 716 .clkr = { 717 .enable_reg = 0x6054, 718 .enable_mask = BIT(0), 719 .hw.init = &(const struct clk_init_data) { 720 .name = "cam_cc_bps_areg_clk", 721 .parent_hws = (const struct clk_hw*[]) { 722 &cam_cc_fast_ahb_clk_src.clkr.hw, 723 }, 724 .num_parents = 1, 725 .flags = CLK_SET_RATE_PARENT, 726 .ops = &clk_branch2_ops, 727 }, 728 }, 729 }; 730 731 static struct clk_branch cam_cc_bps_axi_clk = { 732 .halt_reg = 0x6038, 733 .halt_check = BRANCH_HALT, 734 .clkr = { 735 .enable_reg = 0x6038, 736 .enable_mask = BIT(0), 737 .hw.init = &(const struct clk_init_data) { 738 .name = "cam_cc_bps_axi_clk", 739 .ops = &clk_branch2_ops, 740 }, 741 }, 742 }; 743 744 static struct clk_branch cam_cc_bps_clk = { 745 .halt_reg = 0x6028, 746 .halt_check = BRANCH_HALT, 747 .clkr = { 748 .enable_reg = 0x6028, 749 .enable_mask = BIT(0), 750 .hw.init = &(const struct clk_init_data) { 751 .name = "cam_cc_bps_clk", 752 .parent_hws = (const struct clk_hw*[]) { 753 &cam_cc_bps_clk_src.clkr.hw, 754 }, 755 .num_parents = 1, 756 .flags = CLK_SET_RATE_PARENT, 757 .ops = &clk_branch2_ops, 758 }, 759 }, 760 }; 761 762 static struct clk_branch cam_cc_camnoc_axi_clk = { 763 .halt_reg = 0xb124, 764 .halt_check = BRANCH_HALT, 765 .clkr = { 766 .enable_reg = 0xb124, 767 .enable_mask = BIT(0), 768 .hw.init = &(const struct clk_init_data) { 769 .name = "cam_cc_camnoc_axi_clk", 770 .ops = &clk_branch2_ops, 771 }, 772 }, 773 }; 774 775 static struct clk_branch cam_cc_cci_clk = { 776 .halt_reg = 0xb0f0, 777 .halt_check = BRANCH_HALT, 778 .clkr = { 779 .enable_reg = 0xb0f0, 780 .enable_mask = BIT(0), 781 .hw.init = &(const struct clk_init_data) { 782 .name = "cam_cc_cci_clk", 783 .parent_hws = (const struct clk_hw*[]) { 784 &cam_cc_cci_clk_src.clkr.hw, 785 }, 786 .num_parents = 1, 787 .flags = CLK_SET_RATE_PARENT, 788 .ops = &clk_branch2_ops, 789 }, 790 }, 791 }; 792 793 static struct clk_branch cam_cc_core_ahb_clk = { 794 .halt_reg = 0xb144, 795 .halt_check = BRANCH_HALT_VOTED, 796 .clkr = { 797 .enable_reg = 0xb144, 798 .enable_mask = BIT(0), 799 .hw.init = &(const struct clk_init_data) { 800 .name = "cam_cc_core_ahb_clk", 801 .parent_hws = (const struct clk_hw*[]) { 802 &cam_cc_slow_ahb_clk_src.clkr.hw, 803 }, 804 .num_parents = 1, 805 .flags = CLK_SET_RATE_PARENT, 806 .ops = &clk_branch2_ops, 807 }, 808 }, 809 }; 810 811 static struct clk_branch cam_cc_cpas_ahb_clk = { 812 .halt_reg = 0xb11c, 813 .halt_check = BRANCH_HALT, 814 .clkr = { 815 .enable_reg = 0xb11c, 816 .enable_mask = BIT(0), 817 .hw.init = &(const struct clk_init_data) { 818 .name = "cam_cc_cpas_ahb_clk", 819 .parent_hws = (const struct clk_hw*[]) { 820 &cam_cc_slow_ahb_clk_src.clkr.hw, 821 }, 822 .num_parents = 1, 823 .flags = CLK_SET_RATE_PARENT, 824 .ops = &clk_branch2_ops, 825 }, 826 }, 827 }; 828 829 static struct clk_branch cam_cc_csi0phytimer_clk = { 830 .halt_reg = 0x501c, 831 .halt_check = BRANCH_HALT, 832 .clkr = { 833 .enable_reg = 0x501c, 834 .enable_mask = BIT(0), 835 .hw.init = &(const struct clk_init_data) { 836 .name = "cam_cc_csi0phytimer_clk", 837 .parent_hws = (const struct clk_hw*[]) { 838 &cam_cc_csi0phytimer_clk_src.clkr.hw, 839 }, 840 .num_parents = 1, 841 .flags = CLK_SET_RATE_PARENT, 842 .ops = &clk_branch2_ops, 843 }, 844 }, 845 }; 846 847 static struct clk_branch cam_cc_csi1phytimer_clk = { 848 .halt_reg = 0x5040, 849 .halt_check = BRANCH_HALT, 850 .clkr = { 851 .enable_reg = 0x5040, 852 .enable_mask = BIT(0), 853 .hw.init = &(const struct clk_init_data) { 854 .name = "cam_cc_csi1phytimer_clk", 855 .parent_hws = (const struct clk_hw*[]) { 856 &cam_cc_csi1phytimer_clk_src.clkr.hw, 857 }, 858 .num_parents = 1, 859 .flags = CLK_SET_RATE_PARENT, 860 .ops = &clk_branch2_ops, 861 }, 862 }, 863 }; 864 865 static struct clk_branch cam_cc_csi2phytimer_clk = { 866 .halt_reg = 0x5064, 867 .halt_check = BRANCH_HALT, 868 .clkr = { 869 .enable_reg = 0x5064, 870 .enable_mask = BIT(0), 871 .hw.init = &(const struct clk_init_data) { 872 .name = "cam_cc_csi2phytimer_clk", 873 .parent_hws = (const struct clk_hw*[]) { 874 &cam_cc_csi2phytimer_clk_src.clkr.hw, 875 }, 876 .num_parents = 1, 877 .flags = CLK_SET_RATE_PARENT, 878 .ops = &clk_branch2_ops, 879 }, 880 }, 881 }; 882 883 static struct clk_branch cam_cc_csiphy0_clk = { 884 .halt_reg = 0x5020, 885 .halt_check = BRANCH_HALT, 886 .clkr = { 887 .enable_reg = 0x5020, 888 .enable_mask = BIT(0), 889 .hw.init = &(const struct clk_init_data) { 890 .name = "cam_cc_csiphy0_clk", 891 .parent_hws = (const struct clk_hw*[]) { 892 &cam_cc_cphy_rx_clk_src.clkr.hw, 893 }, 894 .num_parents = 1, 895 .flags = CLK_SET_RATE_PARENT, 896 .ops = &clk_branch2_ops, 897 }, 898 }, 899 }; 900 901 static struct clk_branch cam_cc_csiphy1_clk = { 902 .halt_reg = 0x5044, 903 .halt_check = BRANCH_HALT, 904 .clkr = { 905 .enable_reg = 0x5044, 906 .enable_mask = BIT(0), 907 .hw.init = &(const struct clk_init_data) { 908 .name = "cam_cc_csiphy1_clk", 909 .parent_hws = (const struct clk_hw*[]) { 910 &cam_cc_cphy_rx_clk_src.clkr.hw, 911 }, 912 .num_parents = 1, 913 .flags = CLK_SET_RATE_PARENT, 914 .ops = &clk_branch2_ops, 915 }, 916 }, 917 }; 918 919 static struct clk_branch cam_cc_csiphy2_clk = { 920 .halt_reg = 0x5068, 921 .halt_check = BRANCH_HALT, 922 .clkr = { 923 .enable_reg = 0x5068, 924 .enable_mask = BIT(0), 925 .hw.init = &(const struct clk_init_data) { 926 .name = "cam_cc_csiphy2_clk", 927 .parent_hws = (const struct clk_hw*[]) { 928 &cam_cc_cphy_rx_clk_src.clkr.hw, 929 }, 930 .num_parents = 1, 931 .flags = CLK_SET_RATE_PARENT, 932 .ops = &clk_branch2_ops, 933 }, 934 }, 935 }; 936 937 static struct clk_branch cam_cc_icp_clk = { 938 .halt_reg = 0xb0a0, 939 .halt_check = BRANCH_HALT, 940 .clkr = { 941 .enable_reg = 0xb0a0, 942 .enable_mask = BIT(0), 943 .hw.init = &(const struct clk_init_data) { 944 .name = "cam_cc_icp_clk", 945 .parent_hws = (const struct clk_hw*[]) { 946 &cam_cc_icp_clk_src.clkr.hw, 947 }, 948 .num_parents = 1, 949 .flags = CLK_SET_RATE_PARENT, 950 .ops = &clk_branch2_ops, 951 }, 952 }, 953 }; 954 955 static struct clk_branch cam_cc_ife_0_axi_clk = { 956 .halt_reg = 0x9080, 957 .halt_check = BRANCH_HALT, 958 .clkr = { 959 .enable_reg = 0x9080, 960 .enable_mask = BIT(0), 961 .hw.init = &(const struct clk_init_data) { 962 .name = "cam_cc_ife_0_axi_clk", 963 .ops = &clk_branch2_ops, 964 }, 965 }, 966 }; 967 968 static struct clk_branch cam_cc_ife_0_clk = { 969 .halt_reg = 0x9028, 970 .halt_check = BRANCH_HALT, 971 .clkr = { 972 .enable_reg = 0x9028, 973 .enable_mask = BIT(0), 974 .hw.init = &(const struct clk_init_data) { 975 .name = "cam_cc_ife_0_clk", 976 .parent_hws = (const struct clk_hw*[]) { 977 &cam_cc_ife_0_clk_src.clkr.hw, 978 }, 979 .num_parents = 1, 980 .flags = CLK_SET_RATE_PARENT, 981 .ops = &clk_branch2_ops, 982 }, 983 }, 984 }; 985 986 static struct clk_branch cam_cc_ife_0_cphy_rx_clk = { 987 .halt_reg = 0x907c, 988 .halt_check = BRANCH_HALT, 989 .clkr = { 990 .enable_reg = 0x907c, 991 .enable_mask = BIT(0), 992 .hw.init = &(const struct clk_init_data) { 993 .name = "cam_cc_ife_0_cphy_rx_clk", 994 .parent_hws = (const struct clk_hw*[]) { 995 &cam_cc_cphy_rx_clk_src.clkr.hw, 996 }, 997 .num_parents = 1, 998 .flags = CLK_SET_RATE_PARENT, 999 .ops = &clk_branch2_ops, 1000 }, 1001 }, 1002 }; 1003 1004 static struct clk_branch cam_cc_ife_0_csid_clk = { 1005 .halt_reg = 0x9054, 1006 .halt_check = BRANCH_HALT, 1007 .clkr = { 1008 .enable_reg = 0x9054, 1009 .enable_mask = BIT(0), 1010 .hw.init = &(const struct clk_init_data) { 1011 .name = "cam_cc_ife_0_csid_clk", 1012 .parent_hws = (const struct clk_hw*[]) { 1013 &cam_cc_ife_0_csid_clk_src.clkr.hw, 1014 }, 1015 .num_parents = 1, 1016 .flags = CLK_SET_RATE_PARENT, 1017 .ops = &clk_branch2_ops, 1018 }, 1019 }, 1020 }; 1021 1022 static struct clk_branch cam_cc_ife_0_dsp_clk = { 1023 .halt_reg = 0x9038, 1024 .halt_check = BRANCH_HALT, 1025 .clkr = { 1026 .enable_reg = 0x9038, 1027 .enable_mask = BIT(0), 1028 .hw.init = &(const struct clk_init_data) { 1029 .name = "cam_cc_ife_0_dsp_clk", 1030 .parent_hws = (const struct clk_hw*[]) { 1031 &cam_cc_ife_0_clk_src.clkr.hw, 1032 }, 1033 .num_parents = 1, 1034 .flags = CLK_SET_RATE_PARENT, 1035 .ops = &clk_branch2_ops, 1036 }, 1037 }, 1038 }; 1039 1040 static struct clk_branch cam_cc_ife_1_axi_clk = { 1041 .halt_reg = 0xa058, 1042 .halt_check = BRANCH_HALT, 1043 .clkr = { 1044 .enable_reg = 0xa058, 1045 .enable_mask = BIT(0), 1046 .hw.init = &(const struct clk_init_data) { 1047 .name = "cam_cc_ife_1_axi_clk", 1048 .ops = &clk_branch2_ops, 1049 }, 1050 }, 1051 }; 1052 1053 static struct clk_branch cam_cc_ife_1_clk = { 1054 .halt_reg = 0xa028, 1055 .halt_check = BRANCH_HALT, 1056 .clkr = { 1057 .enable_reg = 0xa028, 1058 .enable_mask = BIT(0), 1059 .hw.init = &(const struct clk_init_data) { 1060 .name = "cam_cc_ife_1_clk", 1061 .parent_hws = (const struct clk_hw*[]) { 1062 &cam_cc_ife_1_clk_src.clkr.hw, 1063 }, 1064 .num_parents = 1, 1065 .flags = CLK_SET_RATE_PARENT, 1066 .ops = &clk_branch2_ops, 1067 }, 1068 }, 1069 }; 1070 1071 static struct clk_branch cam_cc_ife_1_cphy_rx_clk = { 1072 .halt_reg = 0xa054, 1073 .halt_check = BRANCH_HALT, 1074 .clkr = { 1075 .enable_reg = 0xa054, 1076 .enable_mask = BIT(0), 1077 .hw.init = &(const struct clk_init_data) { 1078 .name = "cam_cc_ife_1_cphy_rx_clk", 1079 .parent_hws = (const struct clk_hw*[]) { 1080 &cam_cc_cphy_rx_clk_src.clkr.hw, 1081 }, 1082 .num_parents = 1, 1083 .flags = CLK_SET_RATE_PARENT, 1084 .ops = &clk_branch2_ops, 1085 }, 1086 }, 1087 }; 1088 1089 static struct clk_branch cam_cc_ife_1_csid_clk = { 1090 .halt_reg = 0xa04c, 1091 .halt_check = BRANCH_HALT, 1092 .clkr = { 1093 .enable_reg = 0xa04c, 1094 .enable_mask = BIT(0), 1095 .hw.init = &(const struct clk_init_data) { 1096 .name = "cam_cc_ife_1_csid_clk", 1097 .parent_hws = (const struct clk_hw*[]) { 1098 &cam_cc_ife_1_csid_clk_src.clkr.hw, 1099 }, 1100 .num_parents = 1, 1101 .flags = CLK_SET_RATE_PARENT, 1102 .ops = &clk_branch2_ops, 1103 }, 1104 }, 1105 }; 1106 1107 static struct clk_branch cam_cc_ife_1_dsp_clk = { 1108 .halt_reg = 0xa030, 1109 .halt_check = BRANCH_HALT, 1110 .clkr = { 1111 .enable_reg = 0xa030, 1112 .enable_mask = BIT(0), 1113 .hw.init = &(const struct clk_init_data) { 1114 .name = "cam_cc_ife_1_dsp_clk", 1115 .parent_hws = (const struct clk_hw*[]) { 1116 &cam_cc_ife_1_clk_src.clkr.hw, 1117 }, 1118 .num_parents = 1, 1119 .flags = CLK_SET_RATE_PARENT, 1120 .ops = &clk_branch2_ops, 1121 }, 1122 }, 1123 }; 1124 1125 static struct clk_branch cam_cc_ife_lite_clk = { 1126 .halt_reg = 0xb01c, 1127 .halt_check = BRANCH_HALT, 1128 .clkr = { 1129 .enable_reg = 0xb01c, 1130 .enable_mask = BIT(0), 1131 .hw.init = &(const struct clk_init_data) { 1132 .name = "cam_cc_ife_lite_clk", 1133 .parent_hws = (const struct clk_hw*[]) { 1134 &cam_cc_ife_lite_clk_src.clkr.hw, 1135 }, 1136 .num_parents = 1, 1137 .flags = CLK_SET_RATE_PARENT, 1138 .ops = &clk_branch2_ops, 1139 }, 1140 }, 1141 }; 1142 1143 static struct clk_branch cam_cc_ife_lite_cphy_rx_clk = { 1144 .halt_reg = 0xb044, 1145 .halt_check = BRANCH_HALT, 1146 .clkr = { 1147 .enable_reg = 0xb044, 1148 .enable_mask = BIT(0), 1149 .hw.init = &(const struct clk_init_data) { 1150 .name = "cam_cc_ife_lite_cphy_rx_clk", 1151 .parent_hws = (const struct clk_hw*[]) { 1152 &cam_cc_cphy_rx_clk_src.clkr.hw, 1153 }, 1154 .num_parents = 1, 1155 .flags = CLK_SET_RATE_PARENT, 1156 .ops = &clk_branch2_ops, 1157 }, 1158 }, 1159 }; 1160 1161 static struct clk_branch cam_cc_ife_lite_csid_clk = { 1162 .halt_reg = 0xb03c, 1163 .halt_check = BRANCH_HALT, 1164 .clkr = { 1165 .enable_reg = 0xb03c, 1166 .enable_mask = BIT(0), 1167 .hw.init = &(const struct clk_init_data) { 1168 .name = "cam_cc_ife_lite_csid_clk", 1169 .parent_hws = (const struct clk_hw*[]) { 1170 &cam_cc_ife_lite_csid_clk_src.clkr.hw, 1171 }, 1172 .num_parents = 1, 1173 .flags = CLK_SET_RATE_PARENT, 1174 .ops = &clk_branch2_ops, 1175 }, 1176 }, 1177 }; 1178 1179 static struct clk_branch cam_cc_ipe_0_ahb_clk = { 1180 .halt_reg = 0x7040, 1181 .halt_check = BRANCH_HALT, 1182 .clkr = { 1183 .enable_reg = 0x7040, 1184 .enable_mask = BIT(0), 1185 .hw.init = &(const struct clk_init_data) { 1186 .name = "cam_cc_ipe_0_ahb_clk", 1187 .parent_hws = (const struct clk_hw*[]) { 1188 &cam_cc_slow_ahb_clk_src.clkr.hw, 1189 }, 1190 .num_parents = 1, 1191 .flags = CLK_SET_RATE_PARENT, 1192 .ops = &clk_branch2_ops, 1193 }, 1194 }, 1195 }; 1196 1197 static struct clk_branch cam_cc_ipe_0_areg_clk = { 1198 .halt_reg = 0x703c, 1199 .halt_check = BRANCH_HALT, 1200 .clkr = { 1201 .enable_reg = 0x703c, 1202 .enable_mask = BIT(0), 1203 .hw.init = &(const struct clk_init_data) { 1204 .name = "cam_cc_ipe_0_areg_clk", 1205 .parent_hws = (const struct clk_hw*[]) { 1206 &cam_cc_fast_ahb_clk_src.clkr.hw, 1207 }, 1208 .num_parents = 1, 1209 .flags = CLK_SET_RATE_PARENT, 1210 .ops = &clk_branch2_ops, 1211 }, 1212 }, 1213 }; 1214 1215 static struct clk_branch cam_cc_ipe_0_axi_clk = { 1216 .halt_reg = 0x7038, 1217 .halt_check = BRANCH_HALT, 1218 .clkr = { 1219 .enable_reg = 0x7038, 1220 .enable_mask = BIT(0), 1221 .hw.init = &(const struct clk_init_data) { 1222 .name = "cam_cc_ipe_0_axi_clk", 1223 .ops = &clk_branch2_ops, 1224 }, 1225 }, 1226 }; 1227 1228 static struct clk_branch cam_cc_ipe_0_clk = { 1229 .halt_reg = 0x7028, 1230 .halt_check = BRANCH_HALT, 1231 .clkr = { 1232 .enable_reg = 0x7028, 1233 .enable_mask = BIT(0), 1234 .hw.init = &(const struct clk_init_data) { 1235 .name = "cam_cc_ipe_0_clk", 1236 .parent_hws = (const struct clk_hw*[]) { 1237 &cam_cc_ipe_0_clk_src.clkr.hw, 1238 }, 1239 .num_parents = 1, 1240 .flags = CLK_SET_RATE_PARENT, 1241 .ops = &clk_branch2_ops, 1242 }, 1243 }, 1244 }; 1245 1246 static struct clk_branch cam_cc_jpeg_clk = { 1247 .halt_reg = 0xb064, 1248 .halt_check = BRANCH_HALT, 1249 .clkr = { 1250 .enable_reg = 0xb064, 1251 .enable_mask = BIT(0), 1252 .hw.init = &(const struct clk_init_data) { 1253 .name = "cam_cc_jpeg_clk", 1254 .parent_hws = (const struct clk_hw*[]) { 1255 &cam_cc_jpeg_clk_src.clkr.hw, 1256 }, 1257 .num_parents = 1, 1258 .flags = CLK_SET_RATE_PARENT, 1259 .ops = &clk_branch2_ops, 1260 }, 1261 }, 1262 }; 1263 1264 static struct clk_branch cam_cc_lrme_clk = { 1265 .halt_reg = 0xb110, 1266 .halt_check = BRANCH_HALT, 1267 .clkr = { 1268 .enable_reg = 0xb110, 1269 .enable_mask = BIT(0), 1270 .hw.init = &(const struct clk_init_data) { 1271 .name = "cam_cc_lrme_clk", 1272 .parent_hws = (const struct clk_hw*[]) { 1273 &cam_cc_lrme_clk_src.clkr.hw, 1274 }, 1275 .num_parents = 1, 1276 .flags = CLK_SET_RATE_PARENT, 1277 .ops = &clk_branch2_ops, 1278 }, 1279 }, 1280 }; 1281 1282 static struct clk_branch cam_cc_mclk0_clk = { 1283 .halt_reg = 0x401c, 1284 .halt_check = BRANCH_HALT, 1285 .clkr = { 1286 .enable_reg = 0x401c, 1287 .enable_mask = BIT(0), 1288 .hw.init = &(const struct clk_init_data) { 1289 .name = "cam_cc_mclk0_clk", 1290 .parent_hws = (const struct clk_hw*[]) { 1291 &cam_cc_mclk0_clk_src.clkr.hw, 1292 }, 1293 .num_parents = 1, 1294 .flags = CLK_SET_RATE_PARENT, 1295 .ops = &clk_branch2_ops, 1296 }, 1297 }, 1298 }; 1299 1300 static struct clk_branch cam_cc_mclk1_clk = { 1301 .halt_reg = 0x403c, 1302 .halt_check = BRANCH_HALT, 1303 .clkr = { 1304 .enable_reg = 0x403c, 1305 .enable_mask = BIT(0), 1306 .hw.init = &(const struct clk_init_data) { 1307 .name = "cam_cc_mclk1_clk", 1308 .parent_hws = (const struct clk_hw*[]) { 1309 &cam_cc_mclk1_clk_src.clkr.hw, 1310 }, 1311 .num_parents = 1, 1312 .flags = CLK_SET_RATE_PARENT, 1313 .ops = &clk_branch2_ops, 1314 }, 1315 }, 1316 }; 1317 1318 static struct clk_branch cam_cc_mclk2_clk = { 1319 .halt_reg = 0x405c, 1320 .halt_check = BRANCH_HALT, 1321 .clkr = { 1322 .enable_reg = 0x405c, 1323 .enable_mask = BIT(0), 1324 .hw.init = &(const struct clk_init_data) { 1325 .name = "cam_cc_mclk2_clk", 1326 .parent_hws = (const struct clk_hw*[]) { 1327 &cam_cc_mclk2_clk_src.clkr.hw, 1328 }, 1329 .num_parents = 1, 1330 .flags = CLK_SET_RATE_PARENT, 1331 .ops = &clk_branch2_ops, 1332 }, 1333 }, 1334 }; 1335 1336 static struct clk_branch cam_cc_mclk3_clk = { 1337 .halt_reg = 0x407c, 1338 .halt_check = BRANCH_HALT, 1339 .clkr = { 1340 .enable_reg = 0x407c, 1341 .enable_mask = BIT(0), 1342 .hw.init = &(const struct clk_init_data) { 1343 .name = "cam_cc_mclk3_clk", 1344 .parent_hws = (const struct clk_hw*[]) { 1345 &cam_cc_mclk3_clk_src.clkr.hw, 1346 }, 1347 .num_parents = 1, 1348 .flags = CLK_SET_RATE_PARENT, 1349 .ops = &clk_branch2_ops, 1350 }, 1351 }, 1352 }; 1353 1354 static struct clk_branch cam_cc_soc_ahb_clk = { 1355 .halt_reg = 0xb140, 1356 .halt_check = BRANCH_HALT, 1357 .clkr = { 1358 .enable_reg = 0xb140, 1359 .enable_mask = BIT(0), 1360 .hw.init = &(const struct clk_init_data) { 1361 .name = "cam_cc_soc_ahb_clk", 1362 .ops = &clk_branch2_ops, 1363 }, 1364 }, 1365 }; 1366 1367 static struct clk_branch cam_cc_sys_tmr_clk = { 1368 .halt_reg = 0xb0a8, 1369 .halt_check = BRANCH_HALT, 1370 .clkr = { 1371 .enable_reg = 0xb0a8, 1372 .enable_mask = BIT(0), 1373 .hw.init = &(const struct clk_init_data) { 1374 .name = "cam_cc_sys_tmr_clk", 1375 .ops = &clk_branch2_ops, 1376 }, 1377 }, 1378 }; 1379 1380 static struct gdsc titan_top_gdsc = { 1381 .gdscr = 0xb134, 1382 .en_rest_wait_val = 0x2, 1383 .en_few_wait_val = 0x2, 1384 .clk_dis_wait_val = 0xf, 1385 .pd = { 1386 .name = "titan_top_gdsc", 1387 }, 1388 .pwrsts = PWRSTS_OFF_ON, 1389 .flags = POLL_CFG_GDSCR, 1390 }; 1391 1392 static struct gdsc bps_gdsc = { 1393 .gdscr = 0x6004, 1394 .en_rest_wait_val = 0x2, 1395 .en_few_wait_val = 0x2, 1396 .clk_dis_wait_val = 0xf, 1397 .pd = { 1398 .name = "bps_gdsc", 1399 }, 1400 .pwrsts = PWRSTS_OFF_ON, 1401 .parent = &titan_top_gdsc.pd, 1402 .flags = POLL_CFG_GDSCR, 1403 }; 1404 1405 static struct gdsc ife_0_gdsc = { 1406 .gdscr = 0x9004, 1407 .en_rest_wait_val = 0x2, 1408 .en_few_wait_val = 0x2, 1409 .clk_dis_wait_val = 0xf, 1410 .pd = { 1411 .name = "ife_0_gdsc", 1412 }, 1413 .pwrsts = PWRSTS_OFF_ON, 1414 .parent = &titan_top_gdsc.pd, 1415 .flags = POLL_CFG_GDSCR, 1416 }; 1417 1418 static struct gdsc ife_1_gdsc = { 1419 .gdscr = 0xa004, 1420 .en_rest_wait_val = 0x2, 1421 .en_few_wait_val = 0x2, 1422 .clk_dis_wait_val = 0xf, 1423 .pd = { 1424 .name = "ife_1_gdsc", 1425 }, 1426 .pwrsts = PWRSTS_OFF_ON, 1427 .parent = &titan_top_gdsc.pd, 1428 .flags = POLL_CFG_GDSCR, 1429 }; 1430 1431 static struct gdsc ipe_0_gdsc = { 1432 .gdscr = 0x7004, 1433 .en_rest_wait_val = 0x2, 1434 .en_few_wait_val = 0x2, 1435 .clk_dis_wait_val = 0xf, 1436 .pd = { 1437 .name = "ipe_0_gdsc", 1438 }, 1439 .pwrsts = PWRSTS_OFF_ON, 1440 .parent = &titan_top_gdsc.pd, 1441 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 1442 }; 1443 1444 static struct clk_regmap *cam_cc_qcs615_clocks[] = { 1445 [CAM_CC_BPS_AHB_CLK] = &cam_cc_bps_ahb_clk.clkr, 1446 [CAM_CC_BPS_AREG_CLK] = &cam_cc_bps_areg_clk.clkr, 1447 [CAM_CC_BPS_AXI_CLK] = &cam_cc_bps_axi_clk.clkr, 1448 [CAM_CC_BPS_CLK] = &cam_cc_bps_clk.clkr, 1449 [CAM_CC_BPS_CLK_SRC] = &cam_cc_bps_clk_src.clkr, 1450 [CAM_CC_CAMNOC_AXI_CLK] = &cam_cc_camnoc_axi_clk.clkr, 1451 [CAM_CC_CCI_CLK] = &cam_cc_cci_clk.clkr, 1452 [CAM_CC_CCI_CLK_SRC] = &cam_cc_cci_clk_src.clkr, 1453 [CAM_CC_CORE_AHB_CLK] = &cam_cc_core_ahb_clk.clkr, 1454 [CAM_CC_CPAS_AHB_CLK] = &cam_cc_cpas_ahb_clk.clkr, 1455 [CAM_CC_CPHY_RX_CLK_SRC] = &cam_cc_cphy_rx_clk_src.clkr, 1456 [CAM_CC_CSI0PHYTIMER_CLK] = &cam_cc_csi0phytimer_clk.clkr, 1457 [CAM_CC_CSI0PHYTIMER_CLK_SRC] = &cam_cc_csi0phytimer_clk_src.clkr, 1458 [CAM_CC_CSI1PHYTIMER_CLK] = &cam_cc_csi1phytimer_clk.clkr, 1459 [CAM_CC_CSI1PHYTIMER_CLK_SRC] = &cam_cc_csi1phytimer_clk_src.clkr, 1460 [CAM_CC_CSI2PHYTIMER_CLK] = &cam_cc_csi2phytimer_clk.clkr, 1461 [CAM_CC_CSI2PHYTIMER_CLK_SRC] = &cam_cc_csi2phytimer_clk_src.clkr, 1462 [CAM_CC_CSIPHY0_CLK] = &cam_cc_csiphy0_clk.clkr, 1463 [CAM_CC_CSIPHY1_CLK] = &cam_cc_csiphy1_clk.clkr, 1464 [CAM_CC_CSIPHY2_CLK] = &cam_cc_csiphy2_clk.clkr, 1465 [CAM_CC_FAST_AHB_CLK_SRC] = &cam_cc_fast_ahb_clk_src.clkr, 1466 [CAM_CC_ICP_CLK] = &cam_cc_icp_clk.clkr, 1467 [CAM_CC_ICP_CLK_SRC] = &cam_cc_icp_clk_src.clkr, 1468 [CAM_CC_IFE_0_AXI_CLK] = &cam_cc_ife_0_axi_clk.clkr, 1469 [CAM_CC_IFE_0_CLK] = &cam_cc_ife_0_clk.clkr, 1470 [CAM_CC_IFE_0_CLK_SRC] = &cam_cc_ife_0_clk_src.clkr, 1471 [CAM_CC_IFE_0_CPHY_RX_CLK] = &cam_cc_ife_0_cphy_rx_clk.clkr, 1472 [CAM_CC_IFE_0_CSID_CLK] = &cam_cc_ife_0_csid_clk.clkr, 1473 [CAM_CC_IFE_0_CSID_CLK_SRC] = &cam_cc_ife_0_csid_clk_src.clkr, 1474 [CAM_CC_IFE_0_DSP_CLK] = &cam_cc_ife_0_dsp_clk.clkr, 1475 [CAM_CC_IFE_1_AXI_CLK] = &cam_cc_ife_1_axi_clk.clkr, 1476 [CAM_CC_IFE_1_CLK] = &cam_cc_ife_1_clk.clkr, 1477 [CAM_CC_IFE_1_CLK_SRC] = &cam_cc_ife_1_clk_src.clkr, 1478 [CAM_CC_IFE_1_CPHY_RX_CLK] = &cam_cc_ife_1_cphy_rx_clk.clkr, 1479 [CAM_CC_IFE_1_CSID_CLK] = &cam_cc_ife_1_csid_clk.clkr, 1480 [CAM_CC_IFE_1_CSID_CLK_SRC] = &cam_cc_ife_1_csid_clk_src.clkr, 1481 [CAM_CC_IFE_1_DSP_CLK] = &cam_cc_ife_1_dsp_clk.clkr, 1482 [CAM_CC_IFE_LITE_CLK] = &cam_cc_ife_lite_clk.clkr, 1483 [CAM_CC_IFE_LITE_CLK_SRC] = &cam_cc_ife_lite_clk_src.clkr, 1484 [CAM_CC_IFE_LITE_CPHY_RX_CLK] = &cam_cc_ife_lite_cphy_rx_clk.clkr, 1485 [CAM_CC_IFE_LITE_CSID_CLK] = &cam_cc_ife_lite_csid_clk.clkr, 1486 [CAM_CC_IFE_LITE_CSID_CLK_SRC] = &cam_cc_ife_lite_csid_clk_src.clkr, 1487 [CAM_CC_IPE_0_AHB_CLK] = &cam_cc_ipe_0_ahb_clk.clkr, 1488 [CAM_CC_IPE_0_AREG_CLK] = &cam_cc_ipe_0_areg_clk.clkr, 1489 [CAM_CC_IPE_0_AXI_CLK] = &cam_cc_ipe_0_axi_clk.clkr, 1490 [CAM_CC_IPE_0_CLK] = &cam_cc_ipe_0_clk.clkr, 1491 [CAM_CC_IPE_0_CLK_SRC] = &cam_cc_ipe_0_clk_src.clkr, 1492 [CAM_CC_JPEG_CLK] = &cam_cc_jpeg_clk.clkr, 1493 [CAM_CC_JPEG_CLK_SRC] = &cam_cc_jpeg_clk_src.clkr, 1494 [CAM_CC_LRME_CLK] = &cam_cc_lrme_clk.clkr, 1495 [CAM_CC_LRME_CLK_SRC] = &cam_cc_lrme_clk_src.clkr, 1496 [CAM_CC_MCLK0_CLK] = &cam_cc_mclk0_clk.clkr, 1497 [CAM_CC_MCLK0_CLK_SRC] = &cam_cc_mclk0_clk_src.clkr, 1498 [CAM_CC_MCLK1_CLK] = &cam_cc_mclk1_clk.clkr, 1499 [CAM_CC_MCLK1_CLK_SRC] = &cam_cc_mclk1_clk_src.clkr, 1500 [CAM_CC_MCLK2_CLK] = &cam_cc_mclk2_clk.clkr, 1501 [CAM_CC_MCLK2_CLK_SRC] = &cam_cc_mclk2_clk_src.clkr, 1502 [CAM_CC_MCLK3_CLK] = &cam_cc_mclk3_clk.clkr, 1503 [CAM_CC_MCLK3_CLK_SRC] = &cam_cc_mclk3_clk_src.clkr, 1504 [CAM_CC_PLL0] = &cam_cc_pll0.clkr, 1505 [CAM_CC_PLL1] = &cam_cc_pll1.clkr, 1506 [CAM_CC_PLL2] = &cam_cc_pll2.clkr, 1507 [CAM_CC_PLL2_OUT_AUX2] = &cam_cc_pll2_out_aux2.clkr, 1508 [CAM_CC_PLL3] = &cam_cc_pll3.clkr, 1509 [CAM_CC_SLOW_AHB_CLK_SRC] = &cam_cc_slow_ahb_clk_src.clkr, 1510 [CAM_CC_SOC_AHB_CLK] = &cam_cc_soc_ahb_clk.clkr, 1511 [CAM_CC_SYS_TMR_CLK] = &cam_cc_sys_tmr_clk.clkr, 1512 }; 1513 1514 static struct gdsc *cam_cc_qcs615_gdscs[] = { 1515 [BPS_GDSC] = &bps_gdsc, 1516 [IFE_0_GDSC] = &ife_0_gdsc, 1517 [IFE_1_GDSC] = &ife_1_gdsc, 1518 [IPE_0_GDSC] = &ipe_0_gdsc, 1519 [TITAN_TOP_GDSC] = &titan_top_gdsc, 1520 }; 1521 1522 static const struct qcom_reset_map cam_cc_qcs615_resets[] = { 1523 [CAM_CC_BPS_BCR] = { 0x6000 }, 1524 [CAM_CC_CAMNOC_BCR] = { 0xb120 }, 1525 [CAM_CC_CCI_BCR] = { 0xb0d4 }, 1526 [CAM_CC_CPAS_BCR] = { 0xb118 }, 1527 [CAM_CC_CSI0PHY_BCR] = { 0x5000 }, 1528 [CAM_CC_CSI1PHY_BCR] = { 0x5024 }, 1529 [CAM_CC_CSI2PHY_BCR] = { 0x5048 }, 1530 [CAM_CC_ICP_BCR] = { 0xb074 }, 1531 [CAM_CC_IFE_0_BCR] = { 0x9000 }, 1532 [CAM_CC_IFE_1_BCR] = { 0xa000 }, 1533 [CAM_CC_IFE_LITE_BCR] = { 0xb000 }, 1534 [CAM_CC_IPE_0_BCR] = { 0x7000 }, 1535 [CAM_CC_JPEG_BCR] = { 0xb048 }, 1536 [CAM_CC_LRME_BCR] = { 0xb0f4 }, 1537 [CAM_CC_MCLK0_BCR] = { 0x4000 }, 1538 [CAM_CC_MCLK1_BCR] = { 0x4020 }, 1539 [CAM_CC_MCLK2_BCR] = { 0x4040 }, 1540 [CAM_CC_MCLK3_BCR] = { 0x4060 }, 1541 [CAM_CC_TITAN_TOP_BCR] = { 0xb130 }, 1542 }; 1543 1544 static struct clk_alpha_pll *cam_cc_qcs615_plls[] = { 1545 &cam_cc_pll0, 1546 &cam_cc_pll1, 1547 &cam_cc_pll2, 1548 &cam_cc_pll3, 1549 }; 1550 1551 static const struct regmap_config cam_cc_qcs615_regmap_config = { 1552 .reg_bits = 32, 1553 .reg_stride = 4, 1554 .val_bits = 32, 1555 .max_register = 0xd004, 1556 .fast_io = true, 1557 }; 1558 1559 static struct qcom_cc_driver_data cam_cc_qcs615_driver_data = { 1560 .alpha_plls = cam_cc_qcs615_plls, 1561 .num_alpha_plls = ARRAY_SIZE(cam_cc_qcs615_plls), 1562 }; 1563 1564 static const struct qcom_cc_desc cam_cc_qcs615_desc = { 1565 .config = &cam_cc_qcs615_regmap_config, 1566 .clks = cam_cc_qcs615_clocks, 1567 .num_clks = ARRAY_SIZE(cam_cc_qcs615_clocks), 1568 .resets = cam_cc_qcs615_resets, 1569 .num_resets = ARRAY_SIZE(cam_cc_qcs615_resets), 1570 .gdscs = cam_cc_qcs615_gdscs, 1571 .num_gdscs = ARRAY_SIZE(cam_cc_qcs615_gdscs), 1572 .driver_data = &cam_cc_qcs615_driver_data, 1573 }; 1574 1575 static const struct of_device_id cam_cc_qcs615_match_table[] = { 1576 { .compatible = "qcom,qcs615-camcc" }, 1577 { } 1578 }; 1579 MODULE_DEVICE_TABLE(of, cam_cc_qcs615_match_table); 1580 1581 static int cam_cc_qcs615_probe(struct platform_device *pdev) 1582 { 1583 return qcom_cc_probe(pdev, &cam_cc_qcs615_desc); 1584 } 1585 1586 static struct platform_driver cam_cc_qcs615_driver = { 1587 .probe = cam_cc_qcs615_probe, 1588 .driver = { 1589 .name = "camcc-qcs615", 1590 .of_match_table = cam_cc_qcs615_match_table, 1591 }, 1592 }; 1593 1594 module_platform_driver(cam_cc_qcs615_driver); 1595 1596 MODULE_DESCRIPTION("QTI CAMCC QCS615 Driver"); 1597 MODULE_LICENSE("GPL"); 1598