1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. 4 * Copyright (c) 2025, Luca Weiss <luca.weiss@fairphone.com> 5 */ 6 7 #include <linux/clk-provider.h> 8 #include <linux/module.h> 9 #include <linux/platform_device.h> 10 #include <linux/regmap.h> 11 12 #include <dt-bindings/clock/qcom,milos-camcc.h> 13 14 #include "clk-alpha-pll.h" 15 #include "clk-branch.h" 16 #include "clk-pll.h" 17 #include "clk-rcg.h" 18 #include "clk-regmap.h" 19 #include "clk-regmap-divider.h" 20 #include "clk-regmap-mux.h" 21 #include "common.h" 22 #include "gdsc.h" 23 #include "reset.h" 24 25 /* Need to match the order of clocks in DT binding */ 26 enum { 27 DT_BI_TCXO, 28 DT_SLEEP_CLK, 29 DT_IFACE, 30 }; 31 32 /* Need to match the order of interconnects in DT binding */ 33 enum { 34 DT_ICC_TOP_GDSC, 35 }; 36 37 enum { 38 P_BI_TCXO, 39 P_CAM_CC_PLL0_OUT_EVEN, 40 P_CAM_CC_PLL0_OUT_MAIN, 41 P_CAM_CC_PLL0_OUT_ODD, 42 P_CAM_CC_PLL1_OUT_EVEN, 43 P_CAM_CC_PLL1_OUT_MAIN, 44 P_CAM_CC_PLL2_OUT_MAIN, 45 P_CAM_CC_PLL3_OUT_EVEN, 46 P_CAM_CC_PLL4_OUT_EVEN, 47 P_CAM_CC_PLL4_OUT_MAIN, 48 P_CAM_CC_PLL5_OUT_EVEN, 49 P_CAM_CC_PLL5_OUT_MAIN, 50 P_CAM_CC_PLL6_OUT_EVEN, 51 P_CAM_CC_PLL6_OUT_MAIN, 52 P_SLEEP_CLK, 53 }; 54 55 static const struct pll_vco lucid_ole_vco[] = { 56 { 249600000, 2300000000, 0 }, 57 }; 58 59 static const struct pll_vco rivian_ole_vco[] = { 60 { 777000000, 1285000000, 0 }, 61 }; 62 63 /* 1200.0 MHz Configuration */ 64 static const struct alpha_pll_config cam_cc_pll0_config = { 65 .l = 0x3e, 66 .alpha = 0x8000, 67 .config_ctl_val = 0x20485699, 68 .config_ctl_hi_val = 0x00182261, 69 .config_ctl_hi1_val = 0x82aa299c, 70 .test_ctl_val = 0x00000000, 71 .test_ctl_hi_val = 0x00000003, 72 .test_ctl_hi1_val = 0x00009000, 73 .test_ctl_hi2_val = 0x00000034, 74 .user_ctl_val = 0x00008400, 75 .user_ctl_hi_val = 0x00000005, 76 }; 77 78 static struct clk_alpha_pll cam_cc_pll0 = { 79 .offset = 0x0, 80 .config = &cam_cc_pll0_config, 81 .vco_table = lucid_ole_vco, 82 .num_vco = ARRAY_SIZE(lucid_ole_vco), 83 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 84 .clkr = { 85 .hw.init = &(const struct clk_init_data) { 86 .name = "cam_cc_pll0", 87 .parent_data = &(const struct clk_parent_data) { 88 .index = DT_BI_TCXO, 89 }, 90 .num_parents = 1, 91 .ops = &clk_alpha_pll_lucid_evo_ops, 92 }, 93 }, 94 }; 95 96 static const struct clk_div_table post_div_table_cam_cc_pll0_out_even[] = { 97 { 0x1, 2 }, 98 { } 99 }; 100 101 static struct clk_alpha_pll_postdiv cam_cc_pll0_out_even = { 102 .offset = 0x0, 103 .post_div_shift = 10, 104 .post_div_table = post_div_table_cam_cc_pll0_out_even, 105 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll0_out_even), 106 .width = 4, 107 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 108 .clkr.hw.init = &(const struct clk_init_data) { 109 .name = "cam_cc_pll0_out_even", 110 .parent_hws = (const struct clk_hw*[]) { 111 &cam_cc_pll0.clkr.hw, 112 }, 113 .num_parents = 1, 114 .flags = CLK_SET_RATE_PARENT, 115 .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, 116 }, 117 }; 118 119 static const struct clk_div_table post_div_table_cam_cc_pll0_out_odd[] = { 120 { 0x2, 3 }, 121 { } 122 }; 123 124 static struct clk_alpha_pll_postdiv cam_cc_pll0_out_odd = { 125 .offset = 0x0, 126 .post_div_shift = 14, 127 .post_div_table = post_div_table_cam_cc_pll0_out_odd, 128 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll0_out_odd), 129 .width = 4, 130 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 131 .clkr.hw.init = &(const struct clk_init_data) { 132 .name = "cam_cc_pll0_out_odd", 133 .parent_hws = (const struct clk_hw*[]) { 134 &cam_cc_pll0.clkr.hw, 135 }, 136 .num_parents = 1, 137 .flags = CLK_SET_RATE_PARENT, 138 .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, 139 }, 140 }; 141 142 /* 600.0 MHz Configuration */ 143 static const struct alpha_pll_config cam_cc_pll1_config = { 144 .l = 0x1f, 145 .alpha = 0x4000, 146 .config_ctl_val = 0x20485699, 147 .config_ctl_hi_val = 0x00182261, 148 .config_ctl_hi1_val = 0x82aa299c, 149 .test_ctl_val = 0x00000000, 150 .test_ctl_hi_val = 0x00000003, 151 .test_ctl_hi1_val = 0x00009000, 152 .test_ctl_hi2_val = 0x00000034, 153 .user_ctl_val = 0x00000400, 154 .user_ctl_hi_val = 0x00000005, 155 }; 156 157 static struct clk_alpha_pll cam_cc_pll1 = { 158 .offset = 0x1000, 159 .config = &cam_cc_pll1_config, 160 .vco_table = lucid_ole_vco, 161 .num_vco = ARRAY_SIZE(lucid_ole_vco), 162 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 163 .clkr = { 164 .hw.init = &(const struct clk_init_data) { 165 .name = "cam_cc_pll1", 166 .parent_data = &(const struct clk_parent_data) { 167 .index = DT_BI_TCXO, 168 }, 169 .num_parents = 1, 170 .ops = &clk_alpha_pll_lucid_evo_ops, 171 }, 172 }, 173 }; 174 175 static const struct clk_div_table post_div_table_cam_cc_pll1_out_even[] = { 176 { 0x1, 2 }, 177 { } 178 }; 179 180 static struct clk_alpha_pll_postdiv cam_cc_pll1_out_even = { 181 .offset = 0x1000, 182 .post_div_shift = 10, 183 .post_div_table = post_div_table_cam_cc_pll1_out_even, 184 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll1_out_even), 185 .width = 4, 186 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 187 .clkr.hw.init = &(const struct clk_init_data) { 188 .name = "cam_cc_pll1_out_even", 189 .parent_hws = (const struct clk_hw*[]) { 190 &cam_cc_pll1.clkr.hw, 191 }, 192 .num_parents = 1, 193 .flags = CLK_SET_RATE_PARENT, 194 .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, 195 }, 196 }; 197 198 /* 960.0 MHz Configuration */ 199 static const struct alpha_pll_config cam_cc_pll2_config = { 200 .l = 0x32, 201 .alpha = 0x0, 202 .config_ctl_val = 0x10000030, 203 .config_ctl_hi_val = 0x80890263, 204 .config_ctl_hi1_val = 0x00000217, 205 .user_ctl_val = 0x00000001, 206 .user_ctl_hi_val = 0x00100000, 207 }; 208 209 static struct clk_alpha_pll cam_cc_pll2 = { 210 .offset = 0x2000, 211 .config = &cam_cc_pll2_config, 212 .vco_table = rivian_ole_vco, 213 .num_vco = ARRAY_SIZE(rivian_ole_vco), 214 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_RIVIAN_EVO], 215 .clkr = { 216 .hw.init = &(const struct clk_init_data) { 217 .name = "cam_cc_pll2", 218 .parent_data = &(const struct clk_parent_data) { 219 .index = DT_BI_TCXO, 220 }, 221 .num_parents = 1, 222 .ops = &clk_alpha_pll_rivian_evo_ops, 223 }, 224 }, 225 }; 226 227 /* 600.0 MHz Configuration */ 228 static const struct alpha_pll_config cam_cc_pll3_config = { 229 .l = 0x1f, 230 .alpha = 0x4000, 231 .config_ctl_val = 0x20485699, 232 .config_ctl_hi_val = 0x00182261, 233 .config_ctl_hi1_val = 0x82aa299c, 234 .test_ctl_val = 0x00000000, 235 .test_ctl_hi_val = 0x00000003, 236 .test_ctl_hi1_val = 0x00009000, 237 .test_ctl_hi2_val = 0x00000034, 238 .user_ctl_val = 0x00000400, 239 .user_ctl_hi_val = 0x00000005, 240 }; 241 242 static struct clk_alpha_pll cam_cc_pll3 = { 243 .offset = 0x3000, 244 .config = &cam_cc_pll3_config, 245 .vco_table = lucid_ole_vco, 246 .num_vco = ARRAY_SIZE(lucid_ole_vco), 247 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 248 .clkr = { 249 .hw.init = &(const struct clk_init_data) { 250 .name = "cam_cc_pll3", 251 .parent_data = &(const struct clk_parent_data) { 252 .index = DT_BI_TCXO, 253 }, 254 .num_parents = 1, 255 .ops = &clk_alpha_pll_lucid_evo_ops, 256 }, 257 }, 258 }; 259 260 static const struct clk_div_table post_div_table_cam_cc_pll3_out_even[] = { 261 { 0x1, 2 }, 262 { } 263 }; 264 265 static struct clk_alpha_pll_postdiv cam_cc_pll3_out_even = { 266 .offset = 0x3000, 267 .post_div_shift = 10, 268 .post_div_table = post_div_table_cam_cc_pll3_out_even, 269 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll3_out_even), 270 .width = 4, 271 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 272 .clkr.hw.init = &(const struct clk_init_data) { 273 .name = "cam_cc_pll3_out_even", 274 .parent_hws = (const struct clk_hw*[]) { 275 &cam_cc_pll3.clkr.hw, 276 }, 277 .num_parents = 1, 278 .flags = CLK_SET_RATE_PARENT, 279 .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, 280 }, 281 }; 282 283 /* 700.0 MHz Configuration */ 284 static const struct alpha_pll_config cam_cc_pll4_config = { 285 .l = 0x24, 286 .alpha = 0x7555, 287 .config_ctl_val = 0x20485699, 288 .config_ctl_hi_val = 0x00182261, 289 .config_ctl_hi1_val = 0x82aa299c, 290 .test_ctl_val = 0x00000000, 291 .test_ctl_hi_val = 0x00000003, 292 .test_ctl_hi1_val = 0x00009000, 293 .test_ctl_hi2_val = 0x00000034, 294 .user_ctl_val = 0x00000400, 295 .user_ctl_hi_val = 0x00000005, 296 }; 297 298 static struct clk_alpha_pll cam_cc_pll4 = { 299 .offset = 0x4000, 300 .config = &cam_cc_pll4_config, 301 .vco_table = lucid_ole_vco, 302 .num_vco = ARRAY_SIZE(lucid_ole_vco), 303 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 304 .clkr = { 305 .hw.init = &(const struct clk_init_data) { 306 .name = "cam_cc_pll4", 307 .parent_data = &(const struct clk_parent_data) { 308 .index = DT_BI_TCXO, 309 }, 310 .num_parents = 1, 311 .ops = &clk_alpha_pll_lucid_evo_ops, 312 }, 313 }, 314 }; 315 316 static const struct clk_div_table post_div_table_cam_cc_pll4_out_even[] = { 317 { 0x1, 2 }, 318 { } 319 }; 320 321 static struct clk_alpha_pll_postdiv cam_cc_pll4_out_even = { 322 .offset = 0x4000, 323 .post_div_shift = 10, 324 .post_div_table = post_div_table_cam_cc_pll4_out_even, 325 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll4_out_even), 326 .width = 4, 327 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 328 .clkr.hw.init = &(const struct clk_init_data) { 329 .name = "cam_cc_pll4_out_even", 330 .parent_hws = (const struct clk_hw*[]) { 331 &cam_cc_pll4.clkr.hw, 332 }, 333 .num_parents = 1, 334 .flags = CLK_SET_RATE_PARENT, 335 .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, 336 }, 337 }; 338 339 /* 700.0 MHz Configuration */ 340 static const struct alpha_pll_config cam_cc_pll5_config = { 341 .l = 0x24, 342 .alpha = 0x7555, 343 .config_ctl_val = 0x20485699, 344 .config_ctl_hi_val = 0x00182261, 345 .config_ctl_hi1_val = 0x82aa299c, 346 .test_ctl_val = 0x00000000, 347 .test_ctl_hi_val = 0x00000003, 348 .test_ctl_hi1_val = 0x00009000, 349 .test_ctl_hi2_val = 0x00000034, 350 .user_ctl_val = 0x00000400, 351 .user_ctl_hi_val = 0x00000005, 352 }; 353 354 static struct clk_alpha_pll cam_cc_pll5 = { 355 .offset = 0x5000, 356 .config = &cam_cc_pll5_config, 357 .vco_table = lucid_ole_vco, 358 .num_vco = ARRAY_SIZE(lucid_ole_vco), 359 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 360 .clkr = { 361 .hw.init = &(const struct clk_init_data) { 362 .name = "cam_cc_pll5", 363 .parent_data = &(const struct clk_parent_data) { 364 .index = DT_BI_TCXO, 365 }, 366 .num_parents = 1, 367 .ops = &clk_alpha_pll_lucid_evo_ops, 368 }, 369 }, 370 }; 371 372 static const struct clk_div_table post_div_table_cam_cc_pll5_out_even[] = { 373 { 0x1, 2 }, 374 { } 375 }; 376 377 static struct clk_alpha_pll_postdiv cam_cc_pll5_out_even = { 378 .offset = 0x5000, 379 .post_div_shift = 10, 380 .post_div_table = post_div_table_cam_cc_pll5_out_even, 381 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll5_out_even), 382 .width = 4, 383 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 384 .clkr.hw.init = &(const struct clk_init_data) { 385 .name = "cam_cc_pll5_out_even", 386 .parent_hws = (const struct clk_hw*[]) { 387 &cam_cc_pll5.clkr.hw, 388 }, 389 .num_parents = 1, 390 .flags = CLK_SET_RATE_PARENT, 391 .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, 392 }, 393 }; 394 395 /* 700.0 MHz Configuration */ 396 static const struct alpha_pll_config cam_cc_pll6_config = { 397 .l = 0x24, 398 .alpha = 0x7555, 399 .config_ctl_val = 0x20485699, 400 .config_ctl_hi_val = 0x00182261, 401 .config_ctl_hi1_val = 0x82aa299c, 402 .test_ctl_val = 0x00000000, 403 .test_ctl_hi_val = 0x00000003, 404 .test_ctl_hi1_val = 0x00009000, 405 .test_ctl_hi2_val = 0x00000034, 406 .user_ctl_val = 0x00000400, 407 .user_ctl_hi_val = 0x00000005, 408 }; 409 410 static struct clk_alpha_pll cam_cc_pll6 = { 411 .offset = 0x6000, 412 .config = &cam_cc_pll6_config, 413 .vco_table = lucid_ole_vco, 414 .num_vco = ARRAY_SIZE(lucid_ole_vco), 415 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 416 .clkr = { 417 .hw.init = &(const struct clk_init_data) { 418 .name = "cam_cc_pll6", 419 .parent_data = &(const struct clk_parent_data) { 420 .index = DT_BI_TCXO, 421 }, 422 .num_parents = 1, 423 .ops = &clk_alpha_pll_lucid_evo_ops, 424 }, 425 }, 426 }; 427 428 static const struct clk_div_table post_div_table_cam_cc_pll6_out_even[] = { 429 { 0x1, 2 }, 430 { } 431 }; 432 433 static struct clk_alpha_pll_postdiv cam_cc_pll6_out_even = { 434 .offset = 0x6000, 435 .post_div_shift = 10, 436 .post_div_table = post_div_table_cam_cc_pll6_out_even, 437 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll6_out_even), 438 .width = 4, 439 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 440 .clkr.hw.init = &(const struct clk_init_data) { 441 .name = "cam_cc_pll6_out_even", 442 .parent_hws = (const struct clk_hw*[]) { 443 &cam_cc_pll6.clkr.hw, 444 }, 445 .num_parents = 1, 446 .flags = CLK_SET_RATE_PARENT, 447 .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, 448 }, 449 }; 450 451 static const struct parent_map cam_cc_parent_map_0[] = { 452 { P_BI_TCXO, 0 }, 453 { P_CAM_CC_PLL0_OUT_MAIN, 1 }, 454 { P_CAM_CC_PLL0_OUT_ODD, 5 }, 455 { P_CAM_CC_PLL0_OUT_EVEN, 6 }, 456 }; 457 458 static const struct clk_parent_data cam_cc_parent_data_0[] = { 459 { .index = DT_BI_TCXO }, 460 { .hw = &cam_cc_pll0.clkr.hw }, 461 { .hw = &cam_cc_pll0_out_odd.clkr.hw }, 462 { .hw = &cam_cc_pll0_out_even.clkr.hw }, 463 }; 464 465 static const struct parent_map cam_cc_parent_map_1[] = { 466 { P_BI_TCXO, 0 }, 467 { P_CAM_CC_PLL2_OUT_MAIN, 4 }, 468 }; 469 470 static const struct clk_parent_data cam_cc_parent_data_1[] = { 471 { .index = DT_BI_TCXO }, 472 { .hw = &cam_cc_pll2.clkr.hw }, 473 }; 474 475 static const struct parent_map cam_cc_parent_map_2[] = { 476 { P_BI_TCXO, 0 }, 477 { P_CAM_CC_PLL0_OUT_MAIN, 1 }, 478 { P_CAM_CC_PLL1_OUT_MAIN, 2 }, 479 { P_CAM_CC_PLL1_OUT_EVEN, 3 }, 480 { P_CAM_CC_PLL0_OUT_ODD, 5 }, 481 { P_CAM_CC_PLL0_OUT_EVEN, 6 }, 482 }; 483 484 static const struct clk_parent_data cam_cc_parent_data_2[] = { 485 { .index = DT_BI_TCXO }, 486 { .hw = &cam_cc_pll0.clkr.hw }, 487 { .hw = &cam_cc_pll1.clkr.hw }, 488 { .hw = &cam_cc_pll1_out_even.clkr.hw }, 489 { .hw = &cam_cc_pll0_out_odd.clkr.hw }, 490 { .hw = &cam_cc_pll0_out_even.clkr.hw }, 491 }; 492 493 static const struct parent_map cam_cc_parent_map_3[] = { 494 { P_BI_TCXO, 0 }, 495 { P_CAM_CC_PLL0_OUT_ODD, 5 }, 496 { P_CAM_CC_PLL0_OUT_EVEN, 6 }, 497 }; 498 499 static const struct clk_parent_data cam_cc_parent_data_3[] = { 500 { .index = DT_BI_TCXO }, 501 { .hw = &cam_cc_pll0_out_odd.clkr.hw }, 502 { .hw = &cam_cc_pll0_out_even.clkr.hw }, 503 }; 504 505 static const struct parent_map cam_cc_parent_map_4[] = { 506 { P_BI_TCXO, 0 }, 507 { P_CAM_CC_PLL0_OUT_MAIN, 1 }, 508 { P_CAM_CC_PLL0_OUT_EVEN, 6 }, 509 }; 510 511 static const struct clk_parent_data cam_cc_parent_data_4[] = { 512 { .index = DT_BI_TCXO }, 513 { .hw = &cam_cc_pll0.clkr.hw }, 514 { .hw = &cam_cc_pll0_out_even.clkr.hw }, 515 }; 516 517 static const struct parent_map cam_cc_parent_map_5[] = { 518 { P_BI_TCXO, 0 }, 519 { P_CAM_CC_PLL0_OUT_MAIN, 1 }, 520 { P_CAM_CC_PLL3_OUT_EVEN, 5 }, 521 { P_CAM_CC_PLL0_OUT_EVEN, 6 }, 522 }; 523 524 static const struct clk_parent_data cam_cc_parent_data_5[] = { 525 { .index = DT_BI_TCXO }, 526 { .hw = &cam_cc_pll0.clkr.hw }, 527 { .hw = &cam_cc_pll3_out_even.clkr.hw }, 528 { .hw = &cam_cc_pll0_out_even.clkr.hw }, 529 }; 530 531 static const struct parent_map cam_cc_parent_map_6[] = { 532 { P_SLEEP_CLK, 0 }, 533 }; 534 535 static const struct clk_parent_data cam_cc_parent_data_6_ao[] = { 536 { .index = DT_SLEEP_CLK }, 537 }; 538 539 static const struct parent_map cam_cc_parent_map_7[] = { 540 { P_BI_TCXO, 0 }, 541 { P_CAM_CC_PLL0_OUT_MAIN, 1 }, 542 { P_CAM_CC_PLL4_OUT_EVEN, 2 }, 543 { P_CAM_CC_PLL4_OUT_MAIN, 3 }, 544 { P_CAM_CC_PLL0_OUT_ODD, 5 }, 545 { P_CAM_CC_PLL0_OUT_EVEN, 6 }, 546 }; 547 548 static const struct clk_parent_data cam_cc_parent_data_7[] = { 549 { .index = DT_BI_TCXO }, 550 { .hw = &cam_cc_pll0.clkr.hw }, 551 { .hw = &cam_cc_pll4_out_even.clkr.hw }, 552 { .hw = &cam_cc_pll4.clkr.hw }, 553 { .hw = &cam_cc_pll0_out_odd.clkr.hw }, 554 { .hw = &cam_cc_pll0_out_even.clkr.hw }, 555 }; 556 557 static const struct parent_map cam_cc_parent_map_8[] = { 558 { P_BI_TCXO, 0 }, 559 { P_CAM_CC_PLL0_OUT_MAIN, 1 }, 560 { P_CAM_CC_PLL5_OUT_EVEN, 2 }, 561 { P_CAM_CC_PLL5_OUT_MAIN, 3 }, 562 { P_CAM_CC_PLL0_OUT_ODD, 5 }, 563 { P_CAM_CC_PLL0_OUT_EVEN, 6 }, 564 }; 565 566 static const struct clk_parent_data cam_cc_parent_data_8[] = { 567 { .index = DT_BI_TCXO }, 568 { .hw = &cam_cc_pll0.clkr.hw }, 569 { .hw = &cam_cc_pll5_out_even.clkr.hw }, 570 { .hw = &cam_cc_pll5.clkr.hw }, 571 { .hw = &cam_cc_pll0_out_odd.clkr.hw }, 572 { .hw = &cam_cc_pll0_out_even.clkr.hw }, 573 }; 574 575 static const struct parent_map cam_cc_parent_map_9[] = { 576 { P_BI_TCXO, 0 }, 577 { P_CAM_CC_PLL0_OUT_MAIN, 1 }, 578 { P_CAM_CC_PLL6_OUT_EVEN, 2 }, 579 { P_CAM_CC_PLL6_OUT_MAIN, 3 }, 580 { P_CAM_CC_PLL0_OUT_ODD, 5 }, 581 { P_CAM_CC_PLL0_OUT_EVEN, 6 }, 582 }; 583 584 static const struct clk_parent_data cam_cc_parent_data_9[] = { 585 { .index = DT_BI_TCXO }, 586 { .hw = &cam_cc_pll0.clkr.hw }, 587 { .hw = &cam_cc_pll6_out_even.clkr.hw }, 588 { .hw = &cam_cc_pll6.clkr.hw }, 589 { .hw = &cam_cc_pll0_out_odd.clkr.hw }, 590 { .hw = &cam_cc_pll0_out_even.clkr.hw }, 591 }; 592 593 static const struct parent_map cam_cc_parent_map_10[] = { 594 { P_BI_TCXO, 0 }, 595 }; 596 597 static const struct clk_parent_data cam_cc_parent_data_10[] = { 598 { .index = DT_BI_TCXO }, 599 }; 600 601 static const struct freq_tbl ftbl_cam_cc_bps_clk_src[] = { 602 F(300000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), 603 F(410000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), 604 F(460000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), 605 F(600000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), 606 F(700000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), 607 { } 608 }; 609 610 static struct clk_rcg2 cam_cc_bps_clk_src = { 611 .cmd_rcgr = 0x1a004, 612 .mnd_width = 0, 613 .hid_width = 5, 614 .parent_map = cam_cc_parent_map_2, 615 .freq_tbl = ftbl_cam_cc_bps_clk_src, 616 .clkr.hw.init = &(const struct clk_init_data) { 617 .name = "cam_cc_bps_clk_src", 618 .parent_data = cam_cc_parent_data_2, 619 .num_parents = ARRAY_SIZE(cam_cc_parent_data_2), 620 .flags = CLK_SET_RATE_PARENT, 621 .ops = &clk_rcg2_shared_ops, 622 }, 623 }; 624 625 static const struct freq_tbl ftbl_cam_cc_camnoc_axi_clk_src[] = { 626 F(150000000, P_CAM_CC_PLL0_OUT_EVEN, 4, 0, 0), 627 F(240000000, P_CAM_CC_PLL0_OUT_EVEN, 2.5, 0, 0), 628 F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0), 629 F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), 630 { } 631 }; 632 633 static struct clk_rcg2 cam_cc_camnoc_axi_clk_src = { 634 .cmd_rcgr = 0x2401c, 635 .mnd_width = 0, 636 .hid_width = 5, 637 .parent_map = cam_cc_parent_map_0, 638 .freq_tbl = ftbl_cam_cc_camnoc_axi_clk_src, 639 .clkr.hw.init = &(const struct clk_init_data) { 640 .name = "cam_cc_camnoc_axi_clk_src", 641 .parent_data = cam_cc_parent_data_0, 642 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 643 .flags = CLK_SET_RATE_PARENT, 644 .ops = &clk_rcg2_shared_ops, 645 }, 646 }; 647 648 static const struct freq_tbl ftbl_cam_cc_cci_0_clk_src[] = { 649 F(37500000, P_CAM_CC_PLL0_OUT_EVEN, 16, 0, 0), 650 F(50000000, P_CAM_CC_PLL0_OUT_EVEN, 12, 0, 0), 651 F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0), 652 { } 653 }; 654 655 static struct clk_rcg2 cam_cc_cci_0_clk_src = { 656 .cmd_rcgr = 0x21004, 657 .mnd_width = 8, 658 .hid_width = 5, 659 .parent_map = cam_cc_parent_map_3, 660 .freq_tbl = ftbl_cam_cc_cci_0_clk_src, 661 .clkr.hw.init = &(const struct clk_init_data) { 662 .name = "cam_cc_cci_0_clk_src", 663 .parent_data = cam_cc_parent_data_3, 664 .num_parents = ARRAY_SIZE(cam_cc_parent_data_3), 665 .flags = CLK_SET_RATE_PARENT, 666 .ops = &clk_rcg2_shared_ops, 667 }, 668 }; 669 670 static struct clk_rcg2 cam_cc_cci_1_clk_src = { 671 .cmd_rcgr = 0x22004, 672 .mnd_width = 8, 673 .hid_width = 5, 674 .parent_map = cam_cc_parent_map_3, 675 .freq_tbl = ftbl_cam_cc_cci_0_clk_src, 676 .clkr.hw.init = &(const struct clk_init_data) { 677 .name = "cam_cc_cci_1_clk_src", 678 .parent_data = cam_cc_parent_data_3, 679 .num_parents = ARRAY_SIZE(cam_cc_parent_data_3), 680 .flags = CLK_SET_RATE_PARENT, 681 .ops = &clk_rcg2_shared_ops, 682 }, 683 }; 684 685 static const struct freq_tbl ftbl_cam_cc_cphy_rx_clk_src[] = { 686 F(200000000, P_CAM_CC_PLL0_OUT_EVEN, 3, 0, 0), 687 F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0), 688 F(400000000, P_CAM_CC_PLL0_OUT_EVEN, 1.5, 0, 0), 689 { } 690 }; 691 692 static struct clk_rcg2 cam_cc_cphy_rx_clk_src = { 693 .cmd_rcgr = 0x1c05c, 694 .mnd_width = 0, 695 .hid_width = 5, 696 .parent_map = cam_cc_parent_map_0, 697 .freq_tbl = ftbl_cam_cc_cphy_rx_clk_src, 698 .clkr.hw.init = &(const struct clk_init_data) { 699 .name = "cam_cc_cphy_rx_clk_src", 700 .parent_data = cam_cc_parent_data_0, 701 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 702 .flags = CLK_SET_RATE_PARENT, 703 .ops = &clk_rcg2_shared_ops, 704 }, 705 }; 706 707 static const struct freq_tbl ftbl_cam_cc_cre_clk_src[] = { 708 F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0), 709 F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), 710 F(600000000, P_CAM_CC_PLL0_OUT_MAIN, 2, 0, 0), 711 { } 712 }; 713 714 static struct clk_rcg2 cam_cc_cre_clk_src = { 715 .cmd_rcgr = 0x27004, 716 .mnd_width = 0, 717 .hid_width = 5, 718 .parent_map = cam_cc_parent_map_2, 719 .freq_tbl = ftbl_cam_cc_cre_clk_src, 720 .clkr.hw.init = &(const struct clk_init_data) { 721 .name = "cam_cc_cre_clk_src", 722 .parent_data = cam_cc_parent_data_2, 723 .num_parents = ARRAY_SIZE(cam_cc_parent_data_2), 724 .flags = CLK_SET_RATE_PARENT, 725 .ops = &clk_rcg2_shared_ops, 726 }, 727 }; 728 729 static const struct freq_tbl ftbl_cam_cc_csi0phytimer_clk_src[] = { 730 F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0), 731 { } 732 }; 733 734 static struct clk_rcg2 cam_cc_csi0phytimer_clk_src = { 735 .cmd_rcgr = 0x19004, 736 .mnd_width = 0, 737 .hid_width = 5, 738 .parent_map = cam_cc_parent_map_0, 739 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, 740 .clkr.hw.init = &(const struct clk_init_data) { 741 .name = "cam_cc_csi0phytimer_clk_src", 742 .parent_data = cam_cc_parent_data_0, 743 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 744 .flags = CLK_SET_RATE_PARENT, 745 .ops = &clk_rcg2_shared_ops, 746 }, 747 }; 748 749 static struct clk_rcg2 cam_cc_csi1phytimer_clk_src = { 750 .cmd_rcgr = 0x19028, 751 .mnd_width = 0, 752 .hid_width = 5, 753 .parent_map = cam_cc_parent_map_0, 754 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, 755 .clkr.hw.init = &(const struct clk_init_data) { 756 .name = "cam_cc_csi1phytimer_clk_src", 757 .parent_data = cam_cc_parent_data_0, 758 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 759 .flags = CLK_SET_RATE_PARENT, 760 .ops = &clk_rcg2_shared_ops, 761 }, 762 }; 763 764 static struct clk_rcg2 cam_cc_csi2phytimer_clk_src = { 765 .cmd_rcgr = 0x1904c, 766 .mnd_width = 0, 767 .hid_width = 5, 768 .parent_map = cam_cc_parent_map_0, 769 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, 770 .clkr.hw.init = &(const struct clk_init_data) { 771 .name = "cam_cc_csi2phytimer_clk_src", 772 .parent_data = cam_cc_parent_data_0, 773 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 774 .flags = CLK_SET_RATE_PARENT, 775 .ops = &clk_rcg2_shared_ops, 776 }, 777 }; 778 779 static struct clk_rcg2 cam_cc_csi3phytimer_clk_src = { 780 .cmd_rcgr = 0x19070, 781 .mnd_width = 0, 782 .hid_width = 5, 783 .parent_map = cam_cc_parent_map_0, 784 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, 785 .clkr.hw.init = &(const struct clk_init_data) { 786 .name = "cam_cc_csi3phytimer_clk_src", 787 .parent_data = cam_cc_parent_data_0, 788 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 789 .flags = CLK_SET_RATE_PARENT, 790 .ops = &clk_rcg2_shared_ops, 791 }, 792 }; 793 794 static const struct freq_tbl ftbl_cam_cc_fast_ahb_clk_src[] = { 795 F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0), 796 F(150000000, P_CAM_CC_PLL0_OUT_EVEN, 4, 0, 0), 797 F(200000000, P_CAM_CC_PLL0_OUT_MAIN, 6, 0, 0), 798 F(240000000, P_CAM_CC_PLL0_OUT_MAIN, 5, 0, 0), 799 { } 800 }; 801 802 static struct clk_rcg2 cam_cc_fast_ahb_clk_src = { 803 .cmd_rcgr = 0x1a030, 804 .mnd_width = 0, 805 .hid_width = 5, 806 .parent_map = cam_cc_parent_map_0, 807 .freq_tbl = ftbl_cam_cc_fast_ahb_clk_src, 808 .clkr.hw.init = &(const struct clk_init_data) { 809 .name = "cam_cc_fast_ahb_clk_src", 810 .parent_data = cam_cc_parent_data_0, 811 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 812 .flags = CLK_SET_RATE_PARENT, 813 .ops = &clk_rcg2_shared_ops, 814 }, 815 }; 816 817 static const struct freq_tbl ftbl_cam_cc_icp_clk_src[] = { 818 F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0), 819 F(480000000, P_CAM_CC_PLL0_OUT_MAIN, 2.5, 0, 0), 820 F(600000000, P_CAM_CC_PLL0_OUT_MAIN, 2, 0, 0), 821 { } 822 }; 823 824 static struct clk_rcg2 cam_cc_icp_clk_src = { 825 .cmd_rcgr = 0x20014, 826 .mnd_width = 0, 827 .hid_width = 5, 828 .parent_map = cam_cc_parent_map_4, 829 .freq_tbl = ftbl_cam_cc_icp_clk_src, 830 .clkr.hw.init = &(const struct clk_init_data) { 831 .name = "cam_cc_icp_clk_src", 832 .parent_data = cam_cc_parent_data_4, 833 .num_parents = ARRAY_SIZE(cam_cc_parent_data_4), 834 .flags = CLK_SET_RATE_PARENT, 835 .ops = &clk_rcg2_shared_ops, 836 }, 837 }; 838 839 static const struct freq_tbl ftbl_cam_cc_mclk0_clk_src[] = { 840 F(19200000, P_CAM_CC_PLL2_OUT_MAIN, 1, 1, 50), 841 F(24000000, P_CAM_CC_PLL2_OUT_MAIN, 10, 1, 4), 842 F(64000000, P_CAM_CC_PLL2_OUT_MAIN, 15, 0, 0), 843 { } 844 }; 845 846 static struct clk_rcg2 cam_cc_mclk0_clk_src = { 847 .cmd_rcgr = 0x18004, 848 .mnd_width = 8, 849 .hid_width = 5, 850 .parent_map = cam_cc_parent_map_1, 851 .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 852 .clkr.hw.init = &(const struct clk_init_data) { 853 .name = "cam_cc_mclk0_clk_src", 854 .parent_data = cam_cc_parent_data_1, 855 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 856 .flags = CLK_SET_RATE_PARENT, 857 .ops = &clk_rcg2_shared_ops, 858 }, 859 }; 860 861 static struct clk_rcg2 cam_cc_mclk1_clk_src = { 862 .cmd_rcgr = 0x18024, 863 .mnd_width = 8, 864 .hid_width = 5, 865 .parent_map = cam_cc_parent_map_1, 866 .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 867 .clkr.hw.init = &(const struct clk_init_data) { 868 .name = "cam_cc_mclk1_clk_src", 869 .parent_data = cam_cc_parent_data_1, 870 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 871 .flags = CLK_SET_RATE_PARENT, 872 .ops = &clk_rcg2_shared_ops, 873 }, 874 }; 875 876 static struct clk_rcg2 cam_cc_mclk2_clk_src = { 877 .cmd_rcgr = 0x18044, 878 .mnd_width = 8, 879 .hid_width = 5, 880 .parent_map = cam_cc_parent_map_1, 881 .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 882 .clkr.hw.init = &(const struct clk_init_data) { 883 .name = "cam_cc_mclk2_clk_src", 884 .parent_data = cam_cc_parent_data_1, 885 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 886 .flags = CLK_SET_RATE_PARENT, 887 .ops = &clk_rcg2_shared_ops, 888 }, 889 }; 890 891 static struct clk_rcg2 cam_cc_mclk3_clk_src = { 892 .cmd_rcgr = 0x18064, 893 .mnd_width = 8, 894 .hid_width = 5, 895 .parent_map = cam_cc_parent_map_1, 896 .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 897 .clkr.hw.init = &(const struct clk_init_data) { 898 .name = "cam_cc_mclk3_clk_src", 899 .parent_data = cam_cc_parent_data_1, 900 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 901 .flags = CLK_SET_RATE_PARENT, 902 .ops = &clk_rcg2_shared_ops, 903 }, 904 }; 905 906 static struct clk_rcg2 cam_cc_mclk4_clk_src = { 907 .cmd_rcgr = 0x18084, 908 .mnd_width = 8, 909 .hid_width = 5, 910 .parent_map = cam_cc_parent_map_1, 911 .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 912 .clkr.hw.init = &(const struct clk_init_data) { 913 .name = "cam_cc_mclk4_clk_src", 914 .parent_data = cam_cc_parent_data_1, 915 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 916 .flags = CLK_SET_RATE_PARENT, 917 .ops = &clk_rcg2_shared_ops, 918 }, 919 }; 920 921 static const struct freq_tbl ftbl_cam_cc_ope_0_clk_src[] = { 922 F(300000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), 923 F(410000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), 924 F(520000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), 925 F(645000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), 926 F(700000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), 927 { } 928 }; 929 930 static struct clk_rcg2 cam_cc_ope_0_clk_src = { 931 .cmd_rcgr = 0x1b004, 932 .mnd_width = 0, 933 .hid_width = 5, 934 .parent_map = cam_cc_parent_map_5, 935 .freq_tbl = ftbl_cam_cc_ope_0_clk_src, 936 .clkr.hw.init = &(const struct clk_init_data) { 937 .name = "cam_cc_ope_0_clk_src", 938 .parent_data = cam_cc_parent_data_5, 939 .num_parents = ARRAY_SIZE(cam_cc_parent_data_5), 940 .flags = CLK_SET_RATE_PARENT, 941 .ops = &clk_rcg2_shared_ops, 942 }, 943 }; 944 945 static const struct freq_tbl ftbl_cam_cc_sleep_clk_src[] = { 946 F(32000, P_SLEEP_CLK, 1, 0, 0), 947 { } 948 }; 949 950 static struct clk_rcg2 cam_cc_sleep_clk_src = { 951 .cmd_rcgr = 0x25044, 952 .mnd_width = 0, 953 .hid_width = 5, 954 .parent_map = cam_cc_parent_map_6, 955 .freq_tbl = ftbl_cam_cc_sleep_clk_src, 956 .clkr.hw.init = &(const struct clk_init_data) { 957 .name = "cam_cc_sleep_clk_src", 958 .parent_data = cam_cc_parent_data_6_ao, 959 .num_parents = ARRAY_SIZE(cam_cc_parent_data_6_ao), 960 .flags = CLK_SET_RATE_PARENT, 961 .ops = &clk_rcg2_ops, 962 }, 963 }; 964 965 static const struct freq_tbl ftbl_cam_cc_slow_ahb_clk_src[] = { 966 F(80000000, P_CAM_CC_PLL0_OUT_EVEN, 7.5, 0, 0), 967 { } 968 }; 969 970 static struct clk_rcg2 cam_cc_slow_ahb_clk_src = { 971 .cmd_rcgr = 0x1a04c, 972 .mnd_width = 0, 973 .hid_width = 5, 974 .parent_map = cam_cc_parent_map_0, 975 .freq_tbl = ftbl_cam_cc_slow_ahb_clk_src, 976 .clkr.hw.init = &(const struct clk_init_data) { 977 .name = "cam_cc_slow_ahb_clk_src", 978 .parent_data = cam_cc_parent_data_0, 979 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 980 .flags = CLK_SET_RATE_PARENT, 981 .ops = &clk_rcg2_shared_ops, 982 }, 983 }; 984 985 static const struct freq_tbl ftbl_cam_cc_tfe_0_clk_src[] = { 986 F(350000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), 987 F(570000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), 988 F(600000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), 989 F(725000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), 990 { } 991 }; 992 993 static struct clk_rcg2 cam_cc_tfe_0_clk_src = { 994 .cmd_rcgr = 0x1c004, 995 .mnd_width = 0, 996 .hid_width = 5, 997 .parent_map = cam_cc_parent_map_7, 998 .freq_tbl = ftbl_cam_cc_tfe_0_clk_src, 999 .clkr.hw.init = &(const struct clk_init_data) { 1000 .name = "cam_cc_tfe_0_clk_src", 1001 .parent_data = cam_cc_parent_data_7, 1002 .num_parents = ARRAY_SIZE(cam_cc_parent_data_7), 1003 .flags = CLK_SET_RATE_PARENT, 1004 .ops = &clk_rcg2_shared_ops, 1005 }, 1006 }; 1007 1008 static struct clk_rcg2 cam_cc_tfe_0_csid_clk_src = { 1009 .cmd_rcgr = 0x1c030, 1010 .mnd_width = 0, 1011 .hid_width = 5, 1012 .parent_map = cam_cc_parent_map_0, 1013 .freq_tbl = ftbl_cam_cc_cphy_rx_clk_src, 1014 .clkr.hw.init = &(const struct clk_init_data) { 1015 .name = "cam_cc_tfe_0_csid_clk_src", 1016 .parent_data = cam_cc_parent_data_0, 1017 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 1018 .flags = CLK_SET_RATE_PARENT, 1019 .ops = &clk_rcg2_shared_ops, 1020 }, 1021 }; 1022 1023 static const struct freq_tbl ftbl_cam_cc_tfe_1_clk_src[] = { 1024 F(350000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0), 1025 F(570000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0), 1026 F(600000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0), 1027 F(725000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0), 1028 { } 1029 }; 1030 1031 static struct clk_rcg2 cam_cc_tfe_1_clk_src = { 1032 .cmd_rcgr = 0x1d004, 1033 .mnd_width = 0, 1034 .hid_width = 5, 1035 .parent_map = cam_cc_parent_map_8, 1036 .freq_tbl = ftbl_cam_cc_tfe_1_clk_src, 1037 .clkr.hw.init = &(const struct clk_init_data) { 1038 .name = "cam_cc_tfe_1_clk_src", 1039 .parent_data = cam_cc_parent_data_8, 1040 .num_parents = ARRAY_SIZE(cam_cc_parent_data_8), 1041 .flags = CLK_SET_RATE_PARENT, 1042 .ops = &clk_rcg2_shared_ops, 1043 }, 1044 }; 1045 1046 static struct clk_rcg2 cam_cc_tfe_1_csid_clk_src = { 1047 .cmd_rcgr = 0x1d030, 1048 .mnd_width = 0, 1049 .hid_width = 5, 1050 .parent_map = cam_cc_parent_map_0, 1051 .freq_tbl = ftbl_cam_cc_cphy_rx_clk_src, 1052 .clkr.hw.init = &(const struct clk_init_data) { 1053 .name = "cam_cc_tfe_1_csid_clk_src", 1054 .parent_data = cam_cc_parent_data_0, 1055 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 1056 .flags = CLK_SET_RATE_PARENT, 1057 .ops = &clk_rcg2_shared_ops, 1058 }, 1059 }; 1060 1061 static const struct freq_tbl ftbl_cam_cc_tfe_2_clk_src[] = { 1062 F(350000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0), 1063 F(570000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0), 1064 F(600000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0), 1065 F(725000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0), 1066 { } 1067 }; 1068 1069 static struct clk_rcg2 cam_cc_tfe_2_clk_src = { 1070 .cmd_rcgr = 0x1e004, 1071 .mnd_width = 0, 1072 .hid_width = 5, 1073 .parent_map = cam_cc_parent_map_9, 1074 .freq_tbl = ftbl_cam_cc_tfe_2_clk_src, 1075 .clkr.hw.init = &(const struct clk_init_data) { 1076 .name = "cam_cc_tfe_2_clk_src", 1077 .parent_data = cam_cc_parent_data_9, 1078 .num_parents = ARRAY_SIZE(cam_cc_parent_data_9), 1079 .flags = CLK_SET_RATE_PARENT, 1080 .ops = &clk_rcg2_shared_ops, 1081 }, 1082 }; 1083 1084 static struct clk_rcg2 cam_cc_tfe_2_csid_clk_src = { 1085 .cmd_rcgr = 0x1e030, 1086 .mnd_width = 0, 1087 .hid_width = 5, 1088 .parent_map = cam_cc_parent_map_0, 1089 .freq_tbl = ftbl_cam_cc_cphy_rx_clk_src, 1090 .clkr.hw.init = &(const struct clk_init_data) { 1091 .name = "cam_cc_tfe_2_csid_clk_src", 1092 .parent_data = cam_cc_parent_data_0, 1093 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 1094 .flags = CLK_SET_RATE_PARENT, 1095 .ops = &clk_rcg2_shared_ops, 1096 }, 1097 }; 1098 1099 static const struct freq_tbl ftbl_cam_cc_xo_clk_src[] = { 1100 F(19200000, P_BI_TCXO, 1, 0, 0), 1101 { } 1102 }; 1103 1104 static struct clk_rcg2 cam_cc_xo_clk_src = { 1105 .cmd_rcgr = 0x25020, 1106 .mnd_width = 0, 1107 .hid_width = 5, 1108 .parent_map = cam_cc_parent_map_10, 1109 .freq_tbl = ftbl_cam_cc_xo_clk_src, 1110 .clkr.hw.init = &(const struct clk_init_data) { 1111 .name = "cam_cc_xo_clk_src", 1112 .parent_data = cam_cc_parent_data_10, 1113 .num_parents = ARRAY_SIZE(cam_cc_parent_data_10), 1114 .flags = CLK_SET_RATE_PARENT, 1115 .ops = &clk_rcg2_ops, 1116 }, 1117 }; 1118 1119 static struct clk_branch cam_cc_bps_ahb_clk = { 1120 .halt_reg = 0x1a064, 1121 .halt_check = BRANCH_HALT, 1122 .clkr = { 1123 .enable_reg = 0x1a064, 1124 .enable_mask = BIT(0), 1125 .hw.init = &(const struct clk_init_data) { 1126 .name = "cam_cc_bps_ahb_clk", 1127 .parent_hws = (const struct clk_hw*[]) { 1128 &cam_cc_slow_ahb_clk_src.clkr.hw, 1129 }, 1130 .num_parents = 1, 1131 .flags = CLK_SET_RATE_PARENT, 1132 .ops = &clk_branch2_ops, 1133 }, 1134 }, 1135 }; 1136 1137 static struct clk_branch cam_cc_bps_areg_clk = { 1138 .halt_reg = 0x1a048, 1139 .halt_check = BRANCH_HALT, 1140 .clkr = { 1141 .enable_reg = 0x1a048, 1142 .enable_mask = BIT(0), 1143 .hw.init = &(const struct clk_init_data) { 1144 .name = "cam_cc_bps_areg_clk", 1145 .parent_hws = (const struct clk_hw*[]) { 1146 &cam_cc_fast_ahb_clk_src.clkr.hw, 1147 }, 1148 .num_parents = 1, 1149 .flags = CLK_SET_RATE_PARENT, 1150 .ops = &clk_branch2_ops, 1151 }, 1152 }, 1153 }; 1154 1155 static struct clk_branch cam_cc_bps_clk = { 1156 .halt_reg = 0x1a01c, 1157 .halt_check = BRANCH_HALT, 1158 .clkr = { 1159 .enable_reg = 0x1a01c, 1160 .enable_mask = BIT(0), 1161 .hw.init = &(const struct clk_init_data) { 1162 .name = "cam_cc_bps_clk", 1163 .parent_hws = (const struct clk_hw*[]) { 1164 &cam_cc_bps_clk_src.clkr.hw, 1165 }, 1166 .num_parents = 1, 1167 .flags = CLK_SET_RATE_PARENT, 1168 .ops = &clk_branch2_ops, 1169 }, 1170 }, 1171 }; 1172 1173 static struct clk_branch cam_cc_camnoc_atb_clk = { 1174 .halt_reg = 0x24040, 1175 .halt_check = BRANCH_HALT, 1176 .clkr = { 1177 .enable_reg = 0x24040, 1178 .enable_mask = BIT(0), 1179 .hw.init = &(const struct clk_init_data) { 1180 .name = "cam_cc_camnoc_atb_clk", 1181 .ops = &clk_branch2_ops, 1182 }, 1183 }, 1184 }; 1185 1186 static struct clk_branch cam_cc_camnoc_axi_hf_clk = { 1187 .halt_reg = 0x24010, 1188 .halt_check = BRANCH_HALT, 1189 .clkr = { 1190 .enable_reg = 0x24010, 1191 .enable_mask = BIT(0), 1192 .hw.init = &(const struct clk_init_data) { 1193 .name = "cam_cc_camnoc_axi_hf_clk", 1194 .ops = &clk_branch2_ops, 1195 }, 1196 }, 1197 }; 1198 1199 static struct clk_branch cam_cc_camnoc_axi_sf_clk = { 1200 .halt_reg = 0x24004, 1201 .halt_check = BRANCH_HALT, 1202 .clkr = { 1203 .enable_reg = 0x24004, 1204 .enable_mask = BIT(0), 1205 .hw.init = &(const struct clk_init_data) { 1206 .name = "cam_cc_camnoc_axi_sf_clk", 1207 .ops = &clk_branch2_ops, 1208 }, 1209 }, 1210 }; 1211 1212 static struct clk_branch cam_cc_camnoc_nrt_axi_clk = { 1213 .halt_reg = 0x2404c, 1214 .halt_check = BRANCH_HALT_VOTED, 1215 .hwcg_reg = 0x2404c, 1216 .hwcg_bit = 1, 1217 .clkr = { 1218 .enable_reg = 0x2404c, 1219 .enable_mask = BIT(0), 1220 .hw.init = &(const struct clk_init_data) { 1221 .name = "cam_cc_camnoc_nrt_axi_clk", 1222 .parent_hws = (const struct clk_hw*[]) { 1223 &cam_cc_camnoc_axi_clk_src.clkr.hw, 1224 }, 1225 .num_parents = 1, 1226 .flags = CLK_SET_RATE_PARENT, 1227 .ops = &clk_branch2_ops, 1228 }, 1229 }, 1230 }; 1231 1232 static struct clk_branch cam_cc_camnoc_rt_axi_clk = { 1233 .halt_reg = 0x24034, 1234 .halt_check = BRANCH_HALT, 1235 .clkr = { 1236 .enable_reg = 0x24034, 1237 .enable_mask = BIT(0), 1238 .hw.init = &(const struct clk_init_data) { 1239 .name = "cam_cc_camnoc_rt_axi_clk", 1240 .parent_hws = (const struct clk_hw*[]) { 1241 &cam_cc_camnoc_axi_clk_src.clkr.hw, 1242 }, 1243 .num_parents = 1, 1244 .flags = CLK_SET_RATE_PARENT, 1245 .ops = &clk_branch2_ops, 1246 }, 1247 }, 1248 }; 1249 1250 static struct clk_branch cam_cc_cci_0_clk = { 1251 .halt_reg = 0x2101c, 1252 .halt_check = BRANCH_HALT, 1253 .clkr = { 1254 .enable_reg = 0x2101c, 1255 .enable_mask = BIT(0), 1256 .hw.init = &(const struct clk_init_data) { 1257 .name = "cam_cc_cci_0_clk", 1258 .parent_hws = (const struct clk_hw*[]) { 1259 &cam_cc_cci_0_clk_src.clkr.hw, 1260 }, 1261 .num_parents = 1, 1262 .flags = CLK_SET_RATE_PARENT, 1263 .ops = &clk_branch2_ops, 1264 }, 1265 }, 1266 }; 1267 1268 static struct clk_branch cam_cc_cci_1_clk = { 1269 .halt_reg = 0x2201c, 1270 .halt_check = BRANCH_HALT, 1271 .clkr = { 1272 .enable_reg = 0x2201c, 1273 .enable_mask = BIT(0), 1274 .hw.init = &(const struct clk_init_data) { 1275 .name = "cam_cc_cci_1_clk", 1276 .parent_hws = (const struct clk_hw*[]) { 1277 &cam_cc_cci_1_clk_src.clkr.hw, 1278 }, 1279 .num_parents = 1, 1280 .flags = CLK_SET_RATE_PARENT, 1281 .ops = &clk_branch2_ops, 1282 }, 1283 }, 1284 }; 1285 1286 static struct clk_branch cam_cc_core_ahb_clk = { 1287 .halt_reg = 0x2501c, 1288 .halt_check = BRANCH_HALT_DELAY, 1289 .clkr = { 1290 .enable_reg = 0x2501c, 1291 .enable_mask = BIT(0), 1292 .hw.init = &(const struct clk_init_data) { 1293 .name = "cam_cc_core_ahb_clk", 1294 .parent_hws = (const struct clk_hw*[]) { 1295 &cam_cc_slow_ahb_clk_src.clkr.hw, 1296 }, 1297 .num_parents = 1, 1298 .flags = CLK_SET_RATE_PARENT, 1299 .ops = &clk_branch2_ops, 1300 }, 1301 }, 1302 }; 1303 1304 static struct clk_branch cam_cc_cpas_ahb_clk = { 1305 .halt_reg = 0x23004, 1306 .halt_check = BRANCH_HALT, 1307 .clkr = { 1308 .enable_reg = 0x23004, 1309 .enable_mask = BIT(0), 1310 .hw.init = &(const struct clk_init_data) { 1311 .name = "cam_cc_cpas_ahb_clk", 1312 .parent_hws = (const struct clk_hw*[]) { 1313 &cam_cc_slow_ahb_clk_src.clkr.hw, 1314 }, 1315 .num_parents = 1, 1316 .flags = CLK_SET_RATE_PARENT, 1317 .ops = &clk_branch2_ops, 1318 }, 1319 }, 1320 }; 1321 1322 static struct clk_branch cam_cc_cre_ahb_clk = { 1323 .halt_reg = 0x27020, 1324 .halt_check = BRANCH_HALT, 1325 .clkr = { 1326 .enable_reg = 0x27020, 1327 .enable_mask = BIT(0), 1328 .hw.init = &(const struct clk_init_data) { 1329 .name = "cam_cc_cre_ahb_clk", 1330 .parent_hws = (const struct clk_hw*[]) { 1331 &cam_cc_slow_ahb_clk_src.clkr.hw, 1332 }, 1333 .num_parents = 1, 1334 .flags = CLK_SET_RATE_PARENT, 1335 .ops = &clk_branch2_ops, 1336 }, 1337 }, 1338 }; 1339 1340 static struct clk_branch cam_cc_cre_clk = { 1341 .halt_reg = 0x2701c, 1342 .halt_check = BRANCH_HALT, 1343 .clkr = { 1344 .enable_reg = 0x2701c, 1345 .enable_mask = BIT(0), 1346 .hw.init = &(const struct clk_init_data) { 1347 .name = "cam_cc_cre_clk", 1348 .parent_hws = (const struct clk_hw*[]) { 1349 &cam_cc_cre_clk_src.clkr.hw, 1350 }, 1351 .num_parents = 1, 1352 .flags = CLK_SET_RATE_PARENT, 1353 .ops = &clk_branch2_ops, 1354 }, 1355 }, 1356 }; 1357 1358 static struct clk_branch cam_cc_csi0phytimer_clk = { 1359 .halt_reg = 0x1901c, 1360 .halt_check = BRANCH_HALT, 1361 .clkr = { 1362 .enable_reg = 0x1901c, 1363 .enable_mask = BIT(0), 1364 .hw.init = &(const struct clk_init_data) { 1365 .name = "cam_cc_csi0phytimer_clk", 1366 .parent_hws = (const struct clk_hw*[]) { 1367 &cam_cc_csi0phytimer_clk_src.clkr.hw, 1368 }, 1369 .num_parents = 1, 1370 .flags = CLK_SET_RATE_PARENT, 1371 .ops = &clk_branch2_ops, 1372 }, 1373 }, 1374 }; 1375 1376 static struct clk_branch cam_cc_csi1phytimer_clk = { 1377 .halt_reg = 0x19040, 1378 .halt_check = BRANCH_HALT, 1379 .clkr = { 1380 .enable_reg = 0x19040, 1381 .enable_mask = BIT(0), 1382 .hw.init = &(const struct clk_init_data) { 1383 .name = "cam_cc_csi1phytimer_clk", 1384 .parent_hws = (const struct clk_hw*[]) { 1385 &cam_cc_csi1phytimer_clk_src.clkr.hw, 1386 }, 1387 .num_parents = 1, 1388 .flags = CLK_SET_RATE_PARENT, 1389 .ops = &clk_branch2_ops, 1390 }, 1391 }, 1392 }; 1393 1394 static struct clk_branch cam_cc_csi2phytimer_clk = { 1395 .halt_reg = 0x19064, 1396 .halt_check = BRANCH_HALT, 1397 .clkr = { 1398 .enable_reg = 0x19064, 1399 .enable_mask = BIT(0), 1400 .hw.init = &(const struct clk_init_data) { 1401 .name = "cam_cc_csi2phytimer_clk", 1402 .parent_hws = (const struct clk_hw*[]) { 1403 &cam_cc_csi2phytimer_clk_src.clkr.hw, 1404 }, 1405 .num_parents = 1, 1406 .flags = CLK_SET_RATE_PARENT, 1407 .ops = &clk_branch2_ops, 1408 }, 1409 }, 1410 }; 1411 1412 static struct clk_branch cam_cc_csi3phytimer_clk = { 1413 .halt_reg = 0x19088, 1414 .halt_check = BRANCH_HALT, 1415 .clkr = { 1416 .enable_reg = 0x19088, 1417 .enable_mask = BIT(0), 1418 .hw.init = &(const struct clk_init_data) { 1419 .name = "cam_cc_csi3phytimer_clk", 1420 .parent_hws = (const struct clk_hw*[]) { 1421 &cam_cc_csi3phytimer_clk_src.clkr.hw, 1422 }, 1423 .num_parents = 1, 1424 .flags = CLK_SET_RATE_PARENT, 1425 .ops = &clk_branch2_ops, 1426 }, 1427 }, 1428 }; 1429 1430 static struct clk_branch cam_cc_csiphy0_clk = { 1431 .halt_reg = 0x19020, 1432 .halt_check = BRANCH_HALT, 1433 .clkr = { 1434 .enable_reg = 0x19020, 1435 .enable_mask = BIT(0), 1436 .hw.init = &(const struct clk_init_data) { 1437 .name = "cam_cc_csiphy0_clk", 1438 .parent_hws = (const struct clk_hw*[]) { 1439 &cam_cc_cphy_rx_clk_src.clkr.hw, 1440 }, 1441 .num_parents = 1, 1442 .flags = CLK_SET_RATE_PARENT, 1443 .ops = &clk_branch2_ops, 1444 }, 1445 }, 1446 }; 1447 1448 static struct clk_branch cam_cc_csiphy1_clk = { 1449 .halt_reg = 0x19044, 1450 .halt_check = BRANCH_HALT, 1451 .clkr = { 1452 .enable_reg = 0x19044, 1453 .enable_mask = BIT(0), 1454 .hw.init = &(const struct clk_init_data) { 1455 .name = "cam_cc_csiphy1_clk", 1456 .parent_hws = (const struct clk_hw*[]) { 1457 &cam_cc_cphy_rx_clk_src.clkr.hw, 1458 }, 1459 .num_parents = 1, 1460 .flags = CLK_SET_RATE_PARENT, 1461 .ops = &clk_branch2_ops, 1462 }, 1463 }, 1464 }; 1465 1466 static struct clk_branch cam_cc_csiphy2_clk = { 1467 .halt_reg = 0x19068, 1468 .halt_check = BRANCH_HALT, 1469 .clkr = { 1470 .enable_reg = 0x19068, 1471 .enable_mask = BIT(0), 1472 .hw.init = &(const struct clk_init_data) { 1473 .name = "cam_cc_csiphy2_clk", 1474 .parent_hws = (const struct clk_hw*[]) { 1475 &cam_cc_cphy_rx_clk_src.clkr.hw, 1476 }, 1477 .num_parents = 1, 1478 .flags = CLK_SET_RATE_PARENT, 1479 .ops = &clk_branch2_ops, 1480 }, 1481 }, 1482 }; 1483 1484 static struct clk_branch cam_cc_csiphy3_clk = { 1485 .halt_reg = 0x1908c, 1486 .halt_check = BRANCH_HALT, 1487 .clkr = { 1488 .enable_reg = 0x1908c, 1489 .enable_mask = BIT(0), 1490 .hw.init = &(const struct clk_init_data) { 1491 .name = "cam_cc_csiphy3_clk", 1492 .parent_hws = (const struct clk_hw*[]) { 1493 &cam_cc_cphy_rx_clk_src.clkr.hw, 1494 }, 1495 .num_parents = 1, 1496 .flags = CLK_SET_RATE_PARENT, 1497 .ops = &clk_branch2_ops, 1498 }, 1499 }, 1500 }; 1501 1502 static struct clk_branch cam_cc_icp_atb_clk = { 1503 .halt_reg = 0x20004, 1504 .halt_check = BRANCH_HALT, 1505 .clkr = { 1506 .enable_reg = 0x20004, 1507 .enable_mask = BIT(0), 1508 .hw.init = &(const struct clk_init_data) { 1509 .name = "cam_cc_icp_atb_clk", 1510 .ops = &clk_branch2_ops, 1511 }, 1512 }, 1513 }; 1514 1515 static struct clk_branch cam_cc_icp_clk = { 1516 .halt_reg = 0x2002c, 1517 .halt_check = BRANCH_HALT, 1518 .clkr = { 1519 .enable_reg = 0x2002c, 1520 .enable_mask = BIT(0), 1521 .hw.init = &(const struct clk_init_data) { 1522 .name = "cam_cc_icp_clk", 1523 .parent_hws = (const struct clk_hw*[]) { 1524 &cam_cc_icp_clk_src.clkr.hw, 1525 }, 1526 .num_parents = 1, 1527 .flags = CLK_SET_RATE_PARENT, 1528 .ops = &clk_branch2_ops, 1529 }, 1530 }, 1531 }; 1532 1533 static struct clk_branch cam_cc_icp_cti_clk = { 1534 .halt_reg = 0x20008, 1535 .halt_check = BRANCH_HALT, 1536 .clkr = { 1537 .enable_reg = 0x20008, 1538 .enable_mask = BIT(0), 1539 .hw.init = &(const struct clk_init_data) { 1540 .name = "cam_cc_icp_cti_clk", 1541 .ops = &clk_branch2_ops, 1542 }, 1543 }, 1544 }; 1545 1546 static struct clk_branch cam_cc_icp_ts_clk = { 1547 .halt_reg = 0x2000c, 1548 .halt_check = BRANCH_HALT, 1549 .clkr = { 1550 .enable_reg = 0x2000c, 1551 .enable_mask = BIT(0), 1552 .hw.init = &(const struct clk_init_data) { 1553 .name = "cam_cc_icp_ts_clk", 1554 .ops = &clk_branch2_ops, 1555 }, 1556 }, 1557 }; 1558 1559 static struct clk_branch cam_cc_mclk0_clk = { 1560 .halt_reg = 0x1801c, 1561 .halt_check = BRANCH_HALT, 1562 .clkr = { 1563 .enable_reg = 0x1801c, 1564 .enable_mask = BIT(0), 1565 .hw.init = &(const struct clk_init_data) { 1566 .name = "cam_cc_mclk0_clk", 1567 .parent_hws = (const struct clk_hw*[]) { 1568 &cam_cc_mclk0_clk_src.clkr.hw, 1569 }, 1570 .num_parents = 1, 1571 .flags = CLK_SET_RATE_PARENT, 1572 .ops = &clk_branch2_ops, 1573 }, 1574 }, 1575 }; 1576 1577 static struct clk_branch cam_cc_mclk1_clk = { 1578 .halt_reg = 0x1803c, 1579 .halt_check = BRANCH_HALT, 1580 .clkr = { 1581 .enable_reg = 0x1803c, 1582 .enable_mask = BIT(0), 1583 .hw.init = &(const struct clk_init_data) { 1584 .name = "cam_cc_mclk1_clk", 1585 .parent_hws = (const struct clk_hw*[]) { 1586 &cam_cc_mclk1_clk_src.clkr.hw, 1587 }, 1588 .num_parents = 1, 1589 .flags = CLK_SET_RATE_PARENT, 1590 .ops = &clk_branch2_ops, 1591 }, 1592 }, 1593 }; 1594 1595 static struct clk_branch cam_cc_mclk2_clk = { 1596 .halt_reg = 0x1805c, 1597 .halt_check = BRANCH_HALT, 1598 .clkr = { 1599 .enable_reg = 0x1805c, 1600 .enable_mask = BIT(0), 1601 .hw.init = &(const struct clk_init_data) { 1602 .name = "cam_cc_mclk2_clk", 1603 .parent_hws = (const struct clk_hw*[]) { 1604 &cam_cc_mclk2_clk_src.clkr.hw, 1605 }, 1606 .num_parents = 1, 1607 .flags = CLK_SET_RATE_PARENT, 1608 .ops = &clk_branch2_ops, 1609 }, 1610 }, 1611 }; 1612 1613 static struct clk_branch cam_cc_mclk3_clk = { 1614 .halt_reg = 0x1807c, 1615 .halt_check = BRANCH_HALT, 1616 .clkr = { 1617 .enable_reg = 0x1807c, 1618 .enable_mask = BIT(0), 1619 .hw.init = &(const struct clk_init_data) { 1620 .name = "cam_cc_mclk3_clk", 1621 .parent_hws = (const struct clk_hw*[]) { 1622 &cam_cc_mclk3_clk_src.clkr.hw, 1623 }, 1624 .num_parents = 1, 1625 .flags = CLK_SET_RATE_PARENT, 1626 .ops = &clk_branch2_ops, 1627 }, 1628 }, 1629 }; 1630 1631 static struct clk_branch cam_cc_mclk4_clk = { 1632 .halt_reg = 0x1809c, 1633 .halt_check = BRANCH_HALT, 1634 .clkr = { 1635 .enable_reg = 0x1809c, 1636 .enable_mask = BIT(0), 1637 .hw.init = &(const struct clk_init_data) { 1638 .name = "cam_cc_mclk4_clk", 1639 .parent_hws = (const struct clk_hw*[]) { 1640 &cam_cc_mclk4_clk_src.clkr.hw, 1641 }, 1642 .num_parents = 1, 1643 .flags = CLK_SET_RATE_PARENT, 1644 .ops = &clk_branch2_ops, 1645 }, 1646 }, 1647 }; 1648 1649 static struct clk_branch cam_cc_ope_0_ahb_clk = { 1650 .halt_reg = 0x1b034, 1651 .halt_check = BRANCH_HALT, 1652 .clkr = { 1653 .enable_reg = 0x1b034, 1654 .enable_mask = BIT(0), 1655 .hw.init = &(const struct clk_init_data) { 1656 .name = "cam_cc_ope_0_ahb_clk", 1657 .parent_hws = (const struct clk_hw*[]) { 1658 &cam_cc_slow_ahb_clk_src.clkr.hw, 1659 }, 1660 .num_parents = 1, 1661 .flags = CLK_SET_RATE_PARENT, 1662 .ops = &clk_branch2_ops, 1663 }, 1664 }, 1665 }; 1666 1667 static struct clk_branch cam_cc_ope_0_areg_clk = { 1668 .halt_reg = 0x1b030, 1669 .halt_check = BRANCH_HALT, 1670 .clkr = { 1671 .enable_reg = 0x1b030, 1672 .enable_mask = BIT(0), 1673 .hw.init = &(const struct clk_init_data) { 1674 .name = "cam_cc_ope_0_areg_clk", 1675 .parent_hws = (const struct clk_hw*[]) { 1676 &cam_cc_fast_ahb_clk_src.clkr.hw, 1677 }, 1678 .num_parents = 1, 1679 .flags = CLK_SET_RATE_PARENT, 1680 .ops = &clk_branch2_ops, 1681 }, 1682 }, 1683 }; 1684 1685 static struct clk_branch cam_cc_ope_0_clk = { 1686 .halt_reg = 0x1b01c, 1687 .halt_check = BRANCH_HALT, 1688 .clkr = { 1689 .enable_reg = 0x1b01c, 1690 .enable_mask = BIT(0), 1691 .hw.init = &(const struct clk_init_data) { 1692 .name = "cam_cc_ope_0_clk", 1693 .parent_hws = (const struct clk_hw*[]) { 1694 &cam_cc_ope_0_clk_src.clkr.hw, 1695 }, 1696 .num_parents = 1, 1697 .flags = CLK_SET_RATE_PARENT, 1698 .ops = &clk_branch2_ops, 1699 }, 1700 }, 1701 }; 1702 1703 static struct clk_branch cam_cc_soc_ahb_clk = { 1704 .halt_reg = 0x25018, 1705 .halt_check = BRANCH_HALT, 1706 .clkr = { 1707 .enable_reg = 0x25018, 1708 .enable_mask = BIT(0), 1709 .hw.init = &(const struct clk_init_data) { 1710 .name = "cam_cc_soc_ahb_clk", 1711 .ops = &clk_branch2_ops, 1712 }, 1713 }, 1714 }; 1715 1716 static struct clk_branch cam_cc_sys_tmr_clk = { 1717 .halt_reg = 0x20038, 1718 .halt_check = BRANCH_HALT, 1719 .clkr = { 1720 .enable_reg = 0x20038, 1721 .enable_mask = BIT(0), 1722 .hw.init = &(const struct clk_init_data) { 1723 .name = "cam_cc_sys_tmr_clk", 1724 .parent_hws = (const struct clk_hw*[]) { 1725 &cam_cc_xo_clk_src.clkr.hw, 1726 }, 1727 .num_parents = 1, 1728 .flags = CLK_SET_RATE_PARENT, 1729 .ops = &clk_branch2_ops, 1730 }, 1731 }, 1732 }; 1733 1734 static struct clk_branch cam_cc_tfe_0_ahb_clk = { 1735 .halt_reg = 0x1c078, 1736 .halt_check = BRANCH_HALT, 1737 .clkr = { 1738 .enable_reg = 0x1c078, 1739 .enable_mask = BIT(0), 1740 .hw.init = &(const struct clk_init_data) { 1741 .name = "cam_cc_tfe_0_ahb_clk", 1742 .parent_hws = (const struct clk_hw*[]) { 1743 &cam_cc_slow_ahb_clk_src.clkr.hw, 1744 }, 1745 .num_parents = 1, 1746 .flags = CLK_SET_RATE_PARENT, 1747 .ops = &clk_branch2_ops, 1748 }, 1749 }, 1750 }; 1751 1752 static struct clk_branch cam_cc_tfe_0_clk = { 1753 .halt_reg = 0x1c01c, 1754 .halt_check = BRANCH_HALT, 1755 .clkr = { 1756 .enable_reg = 0x1c01c, 1757 .enable_mask = BIT(0), 1758 .hw.init = &(const struct clk_init_data) { 1759 .name = "cam_cc_tfe_0_clk", 1760 .parent_hws = (const struct clk_hw*[]) { 1761 &cam_cc_tfe_0_clk_src.clkr.hw, 1762 }, 1763 .num_parents = 1, 1764 .flags = CLK_SET_RATE_PARENT, 1765 .ops = &clk_branch2_ops, 1766 }, 1767 }, 1768 }; 1769 1770 static struct clk_branch cam_cc_tfe_0_cphy_rx_clk = { 1771 .halt_reg = 0x1c074, 1772 .halt_check = BRANCH_HALT, 1773 .clkr = { 1774 .enable_reg = 0x1c074, 1775 .enable_mask = BIT(0), 1776 .hw.init = &(const struct clk_init_data) { 1777 .name = "cam_cc_tfe_0_cphy_rx_clk", 1778 .parent_hws = (const struct clk_hw*[]) { 1779 &cam_cc_cphy_rx_clk_src.clkr.hw, 1780 }, 1781 .num_parents = 1, 1782 .flags = CLK_SET_RATE_PARENT, 1783 .ops = &clk_branch2_ops, 1784 }, 1785 }, 1786 }; 1787 1788 static struct clk_branch cam_cc_tfe_0_csid_clk = { 1789 .halt_reg = 0x1c048, 1790 .halt_check = BRANCH_HALT, 1791 .clkr = { 1792 .enable_reg = 0x1c048, 1793 .enable_mask = BIT(0), 1794 .hw.init = &(const struct clk_init_data) { 1795 .name = "cam_cc_tfe_0_csid_clk", 1796 .parent_hws = (const struct clk_hw*[]) { 1797 &cam_cc_tfe_0_csid_clk_src.clkr.hw, 1798 }, 1799 .num_parents = 1, 1800 .flags = CLK_SET_RATE_PARENT, 1801 .ops = &clk_branch2_ops, 1802 }, 1803 }, 1804 }; 1805 1806 static struct clk_branch cam_cc_tfe_1_ahb_clk = { 1807 .halt_reg = 0x1d058, 1808 .halt_check = BRANCH_HALT, 1809 .clkr = { 1810 .enable_reg = 0x1d058, 1811 .enable_mask = BIT(0), 1812 .hw.init = &(const struct clk_init_data) { 1813 .name = "cam_cc_tfe_1_ahb_clk", 1814 .parent_hws = (const struct clk_hw*[]) { 1815 &cam_cc_slow_ahb_clk_src.clkr.hw, 1816 }, 1817 .num_parents = 1, 1818 .flags = CLK_SET_RATE_PARENT, 1819 .ops = &clk_branch2_ops, 1820 }, 1821 }, 1822 }; 1823 1824 static struct clk_branch cam_cc_tfe_1_clk = { 1825 .halt_reg = 0x1d01c, 1826 .halt_check = BRANCH_HALT, 1827 .clkr = { 1828 .enable_reg = 0x1d01c, 1829 .enable_mask = BIT(0), 1830 .hw.init = &(const struct clk_init_data) { 1831 .name = "cam_cc_tfe_1_clk", 1832 .parent_hws = (const struct clk_hw*[]) { 1833 &cam_cc_tfe_1_clk_src.clkr.hw, 1834 }, 1835 .num_parents = 1, 1836 .flags = CLK_SET_RATE_PARENT, 1837 .ops = &clk_branch2_ops, 1838 }, 1839 }, 1840 }; 1841 1842 static struct clk_branch cam_cc_tfe_1_cphy_rx_clk = { 1843 .halt_reg = 0x1d054, 1844 .halt_check = BRANCH_HALT, 1845 .clkr = { 1846 .enable_reg = 0x1d054, 1847 .enable_mask = BIT(0), 1848 .hw.init = &(const struct clk_init_data) { 1849 .name = "cam_cc_tfe_1_cphy_rx_clk", 1850 .parent_hws = (const struct clk_hw*[]) { 1851 &cam_cc_cphy_rx_clk_src.clkr.hw, 1852 }, 1853 .num_parents = 1, 1854 .flags = CLK_SET_RATE_PARENT, 1855 .ops = &clk_branch2_ops, 1856 }, 1857 }, 1858 }; 1859 1860 static struct clk_branch cam_cc_tfe_1_csid_clk = { 1861 .halt_reg = 0x1d048, 1862 .halt_check = BRANCH_HALT, 1863 .clkr = { 1864 .enable_reg = 0x1d048, 1865 .enable_mask = BIT(0), 1866 .hw.init = &(const struct clk_init_data) { 1867 .name = "cam_cc_tfe_1_csid_clk", 1868 .parent_hws = (const struct clk_hw*[]) { 1869 &cam_cc_tfe_1_csid_clk_src.clkr.hw, 1870 }, 1871 .num_parents = 1, 1872 .flags = CLK_SET_RATE_PARENT, 1873 .ops = &clk_branch2_ops, 1874 }, 1875 }, 1876 }; 1877 1878 static struct clk_branch cam_cc_tfe_2_ahb_clk = { 1879 .halt_reg = 0x1e058, 1880 .halt_check = BRANCH_HALT, 1881 .clkr = { 1882 .enable_reg = 0x1e058, 1883 .enable_mask = BIT(0), 1884 .hw.init = &(const struct clk_init_data) { 1885 .name = "cam_cc_tfe_2_ahb_clk", 1886 .parent_hws = (const struct clk_hw*[]) { 1887 &cam_cc_slow_ahb_clk_src.clkr.hw, 1888 }, 1889 .num_parents = 1, 1890 .flags = CLK_SET_RATE_PARENT, 1891 .ops = &clk_branch2_ops, 1892 }, 1893 }, 1894 }; 1895 1896 static struct clk_branch cam_cc_tfe_2_clk = { 1897 .halt_reg = 0x1e01c, 1898 .halt_check = BRANCH_HALT, 1899 .clkr = { 1900 .enable_reg = 0x1e01c, 1901 .enable_mask = BIT(0), 1902 .hw.init = &(const struct clk_init_data) { 1903 .name = "cam_cc_tfe_2_clk", 1904 .parent_hws = (const struct clk_hw*[]) { 1905 &cam_cc_tfe_2_clk_src.clkr.hw, 1906 }, 1907 .num_parents = 1, 1908 .flags = CLK_SET_RATE_PARENT, 1909 .ops = &clk_branch2_ops, 1910 }, 1911 }, 1912 }; 1913 1914 static struct clk_branch cam_cc_tfe_2_cphy_rx_clk = { 1915 .halt_reg = 0x1e054, 1916 .halt_check = BRANCH_HALT, 1917 .clkr = { 1918 .enable_reg = 0x1e054, 1919 .enable_mask = BIT(0), 1920 .hw.init = &(const struct clk_init_data) { 1921 .name = "cam_cc_tfe_2_cphy_rx_clk", 1922 .parent_hws = (const struct clk_hw*[]) { 1923 &cam_cc_cphy_rx_clk_src.clkr.hw, 1924 }, 1925 .num_parents = 1, 1926 .flags = CLK_SET_RATE_PARENT, 1927 .ops = &clk_branch2_ops, 1928 }, 1929 }, 1930 }; 1931 1932 static struct clk_branch cam_cc_tfe_2_csid_clk = { 1933 .halt_reg = 0x1e048, 1934 .halt_check = BRANCH_HALT, 1935 .clkr = { 1936 .enable_reg = 0x1e048, 1937 .enable_mask = BIT(0), 1938 .hw.init = &(const struct clk_init_data) { 1939 .name = "cam_cc_tfe_2_csid_clk", 1940 .parent_hws = (const struct clk_hw*[]) { 1941 &cam_cc_tfe_2_csid_clk_src.clkr.hw, 1942 }, 1943 .num_parents = 1, 1944 .flags = CLK_SET_RATE_PARENT, 1945 .ops = &clk_branch2_ops, 1946 }, 1947 }, 1948 }; 1949 1950 static struct clk_branch cam_cc_top_shift_clk = { 1951 .halt_reg = 0x25040, 1952 .halt_check = BRANCH_HALT_VOTED, 1953 .clkr = { 1954 .enable_reg = 0x25040, 1955 .enable_mask = BIT(0), 1956 .hw.init = &(const struct clk_init_data) { 1957 .name = "cam_cc_top_shift_clk", 1958 .parent_hws = (const struct clk_hw*[]) { 1959 &cam_cc_xo_clk_src.clkr.hw, 1960 }, 1961 .num_parents = 1, 1962 .flags = CLK_SET_RATE_PARENT, 1963 .ops = &clk_branch2_ops, 1964 }, 1965 }, 1966 }; 1967 1968 static struct gdsc cam_cc_camss_top_gdsc = { 1969 .gdscr = 0x25004, 1970 .en_rest_wait_val = 0x2, 1971 .en_few_wait_val = 0x2, 1972 .clk_dis_wait_val = 0xf, 1973 .pd = { 1974 .name = "cam_cc_camss_top_gdsc", 1975 }, 1976 .pwrsts = PWRSTS_OFF_ON, 1977 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 1978 .needs_icc = true, 1979 .icc_path_index = DT_ICC_TOP_GDSC, 1980 }; 1981 1982 static struct clk_regmap *cam_cc_milos_clocks[] = { 1983 [CAM_CC_BPS_AHB_CLK] = &cam_cc_bps_ahb_clk.clkr, 1984 [CAM_CC_BPS_AREG_CLK] = &cam_cc_bps_areg_clk.clkr, 1985 [CAM_CC_BPS_CLK] = &cam_cc_bps_clk.clkr, 1986 [CAM_CC_BPS_CLK_SRC] = &cam_cc_bps_clk_src.clkr, 1987 [CAM_CC_CAMNOC_ATB_CLK] = &cam_cc_camnoc_atb_clk.clkr, 1988 [CAM_CC_CAMNOC_AXI_CLK_SRC] = &cam_cc_camnoc_axi_clk_src.clkr, 1989 [CAM_CC_CAMNOC_AXI_HF_CLK] = &cam_cc_camnoc_axi_hf_clk.clkr, 1990 [CAM_CC_CAMNOC_AXI_SF_CLK] = &cam_cc_camnoc_axi_sf_clk.clkr, 1991 [CAM_CC_CAMNOC_NRT_AXI_CLK] = &cam_cc_camnoc_nrt_axi_clk.clkr, 1992 [CAM_CC_CAMNOC_RT_AXI_CLK] = &cam_cc_camnoc_rt_axi_clk.clkr, 1993 [CAM_CC_CCI_0_CLK] = &cam_cc_cci_0_clk.clkr, 1994 [CAM_CC_CCI_0_CLK_SRC] = &cam_cc_cci_0_clk_src.clkr, 1995 [CAM_CC_CCI_1_CLK] = &cam_cc_cci_1_clk.clkr, 1996 [CAM_CC_CCI_1_CLK_SRC] = &cam_cc_cci_1_clk_src.clkr, 1997 [CAM_CC_CORE_AHB_CLK] = &cam_cc_core_ahb_clk.clkr, 1998 [CAM_CC_CPAS_AHB_CLK] = &cam_cc_cpas_ahb_clk.clkr, 1999 [CAM_CC_CPHY_RX_CLK_SRC] = &cam_cc_cphy_rx_clk_src.clkr, 2000 [CAM_CC_CRE_AHB_CLK] = &cam_cc_cre_ahb_clk.clkr, 2001 [CAM_CC_CRE_CLK] = &cam_cc_cre_clk.clkr, 2002 [CAM_CC_CRE_CLK_SRC] = &cam_cc_cre_clk_src.clkr, 2003 [CAM_CC_CSI0PHYTIMER_CLK] = &cam_cc_csi0phytimer_clk.clkr, 2004 [CAM_CC_CSI0PHYTIMER_CLK_SRC] = &cam_cc_csi0phytimer_clk_src.clkr, 2005 [CAM_CC_CSI1PHYTIMER_CLK] = &cam_cc_csi1phytimer_clk.clkr, 2006 [CAM_CC_CSI1PHYTIMER_CLK_SRC] = &cam_cc_csi1phytimer_clk_src.clkr, 2007 [CAM_CC_CSI2PHYTIMER_CLK] = &cam_cc_csi2phytimer_clk.clkr, 2008 [CAM_CC_CSI2PHYTIMER_CLK_SRC] = &cam_cc_csi2phytimer_clk_src.clkr, 2009 [CAM_CC_CSI3PHYTIMER_CLK] = &cam_cc_csi3phytimer_clk.clkr, 2010 [CAM_CC_CSI3PHYTIMER_CLK_SRC] = &cam_cc_csi3phytimer_clk_src.clkr, 2011 [CAM_CC_CSIPHY0_CLK] = &cam_cc_csiphy0_clk.clkr, 2012 [CAM_CC_CSIPHY1_CLK] = &cam_cc_csiphy1_clk.clkr, 2013 [CAM_CC_CSIPHY2_CLK] = &cam_cc_csiphy2_clk.clkr, 2014 [CAM_CC_CSIPHY3_CLK] = &cam_cc_csiphy3_clk.clkr, 2015 [CAM_CC_FAST_AHB_CLK_SRC] = &cam_cc_fast_ahb_clk_src.clkr, 2016 [CAM_CC_ICP_ATB_CLK] = &cam_cc_icp_atb_clk.clkr, 2017 [CAM_CC_ICP_CLK] = &cam_cc_icp_clk.clkr, 2018 [CAM_CC_ICP_CLK_SRC] = &cam_cc_icp_clk_src.clkr, 2019 [CAM_CC_ICP_CTI_CLK] = &cam_cc_icp_cti_clk.clkr, 2020 [CAM_CC_ICP_TS_CLK] = &cam_cc_icp_ts_clk.clkr, 2021 [CAM_CC_MCLK0_CLK] = &cam_cc_mclk0_clk.clkr, 2022 [CAM_CC_MCLK0_CLK_SRC] = &cam_cc_mclk0_clk_src.clkr, 2023 [CAM_CC_MCLK1_CLK] = &cam_cc_mclk1_clk.clkr, 2024 [CAM_CC_MCLK1_CLK_SRC] = &cam_cc_mclk1_clk_src.clkr, 2025 [CAM_CC_MCLK2_CLK] = &cam_cc_mclk2_clk.clkr, 2026 [CAM_CC_MCLK2_CLK_SRC] = &cam_cc_mclk2_clk_src.clkr, 2027 [CAM_CC_MCLK3_CLK] = &cam_cc_mclk3_clk.clkr, 2028 [CAM_CC_MCLK3_CLK_SRC] = &cam_cc_mclk3_clk_src.clkr, 2029 [CAM_CC_MCLK4_CLK] = &cam_cc_mclk4_clk.clkr, 2030 [CAM_CC_MCLK4_CLK_SRC] = &cam_cc_mclk4_clk_src.clkr, 2031 [CAM_CC_OPE_0_AHB_CLK] = &cam_cc_ope_0_ahb_clk.clkr, 2032 [CAM_CC_OPE_0_AREG_CLK] = &cam_cc_ope_0_areg_clk.clkr, 2033 [CAM_CC_OPE_0_CLK] = &cam_cc_ope_0_clk.clkr, 2034 [CAM_CC_OPE_0_CLK_SRC] = &cam_cc_ope_0_clk_src.clkr, 2035 [CAM_CC_PLL0] = &cam_cc_pll0.clkr, 2036 [CAM_CC_PLL0_OUT_EVEN] = &cam_cc_pll0_out_even.clkr, 2037 [CAM_CC_PLL0_OUT_ODD] = &cam_cc_pll0_out_odd.clkr, 2038 [CAM_CC_PLL1] = &cam_cc_pll1.clkr, 2039 [CAM_CC_PLL1_OUT_EVEN] = &cam_cc_pll1_out_even.clkr, 2040 [CAM_CC_PLL2] = &cam_cc_pll2.clkr, 2041 [CAM_CC_PLL3] = &cam_cc_pll3.clkr, 2042 [CAM_CC_PLL3_OUT_EVEN] = &cam_cc_pll3_out_even.clkr, 2043 [CAM_CC_PLL4] = &cam_cc_pll4.clkr, 2044 [CAM_CC_PLL4_OUT_EVEN] = &cam_cc_pll4_out_even.clkr, 2045 [CAM_CC_PLL5] = &cam_cc_pll5.clkr, 2046 [CAM_CC_PLL5_OUT_EVEN] = &cam_cc_pll5_out_even.clkr, 2047 [CAM_CC_PLL6] = &cam_cc_pll6.clkr, 2048 [CAM_CC_PLL6_OUT_EVEN] = &cam_cc_pll6_out_even.clkr, 2049 [CAM_CC_SLEEP_CLK_SRC] = &cam_cc_sleep_clk_src.clkr, 2050 [CAM_CC_SLOW_AHB_CLK_SRC] = &cam_cc_slow_ahb_clk_src.clkr, 2051 [CAM_CC_SOC_AHB_CLK] = &cam_cc_soc_ahb_clk.clkr, 2052 [CAM_CC_SYS_TMR_CLK] = &cam_cc_sys_tmr_clk.clkr, 2053 [CAM_CC_TFE_0_AHB_CLK] = &cam_cc_tfe_0_ahb_clk.clkr, 2054 [CAM_CC_TFE_0_CLK] = &cam_cc_tfe_0_clk.clkr, 2055 [CAM_CC_TFE_0_CLK_SRC] = &cam_cc_tfe_0_clk_src.clkr, 2056 [CAM_CC_TFE_0_CPHY_RX_CLK] = &cam_cc_tfe_0_cphy_rx_clk.clkr, 2057 [CAM_CC_TFE_0_CSID_CLK] = &cam_cc_tfe_0_csid_clk.clkr, 2058 [CAM_CC_TFE_0_CSID_CLK_SRC] = &cam_cc_tfe_0_csid_clk_src.clkr, 2059 [CAM_CC_TFE_1_AHB_CLK] = &cam_cc_tfe_1_ahb_clk.clkr, 2060 [CAM_CC_TFE_1_CLK] = &cam_cc_tfe_1_clk.clkr, 2061 [CAM_CC_TFE_1_CLK_SRC] = &cam_cc_tfe_1_clk_src.clkr, 2062 [CAM_CC_TFE_1_CPHY_RX_CLK] = &cam_cc_tfe_1_cphy_rx_clk.clkr, 2063 [CAM_CC_TFE_1_CSID_CLK] = &cam_cc_tfe_1_csid_clk.clkr, 2064 [CAM_CC_TFE_1_CSID_CLK_SRC] = &cam_cc_tfe_1_csid_clk_src.clkr, 2065 [CAM_CC_TFE_2_AHB_CLK] = &cam_cc_tfe_2_ahb_clk.clkr, 2066 [CAM_CC_TFE_2_CLK] = &cam_cc_tfe_2_clk.clkr, 2067 [CAM_CC_TFE_2_CLK_SRC] = &cam_cc_tfe_2_clk_src.clkr, 2068 [CAM_CC_TFE_2_CPHY_RX_CLK] = &cam_cc_tfe_2_cphy_rx_clk.clkr, 2069 [CAM_CC_TFE_2_CSID_CLK] = &cam_cc_tfe_2_csid_clk.clkr, 2070 [CAM_CC_TFE_2_CSID_CLK_SRC] = &cam_cc_tfe_2_csid_clk_src.clkr, 2071 [CAM_CC_TOP_SHIFT_CLK] = &cam_cc_top_shift_clk.clkr, 2072 [CAM_CC_XO_CLK_SRC] = &cam_cc_xo_clk_src.clkr, 2073 }; 2074 2075 static const struct qcom_reset_map cam_cc_milos_resets[] = { 2076 [CAM_CC_BPS_BCR] = { 0x1a000 }, 2077 [CAM_CC_CAMNOC_BCR] = { 0x24000 }, 2078 [CAM_CC_CAMSS_TOP_BCR] = { 0x25000 }, 2079 [CAM_CC_CCI_0_BCR] = { 0x21000 }, 2080 [CAM_CC_CCI_1_BCR] = { 0x22000 }, 2081 [CAM_CC_CPAS_BCR] = { 0x23000 }, 2082 [CAM_CC_CRE_BCR] = { 0x27000 }, 2083 [CAM_CC_CSI0PHY_BCR] = { 0x19000 }, 2084 [CAM_CC_CSI1PHY_BCR] = { 0x19024 }, 2085 [CAM_CC_CSI2PHY_BCR] = { 0x19048 }, 2086 [CAM_CC_CSI3PHY_BCR] = { 0x1906c }, 2087 [CAM_CC_ICP_BCR] = { 0x20000 }, 2088 [CAM_CC_MCLK0_BCR] = { 0x18000 }, 2089 [CAM_CC_MCLK1_BCR] = { 0x18020 }, 2090 [CAM_CC_MCLK2_BCR] = { 0x18040 }, 2091 [CAM_CC_MCLK3_BCR] = { 0x18060 }, 2092 [CAM_CC_MCLK4_BCR] = { 0x18080 }, 2093 [CAM_CC_OPE_0_BCR] = { 0x1b000 }, 2094 [CAM_CC_TFE_0_BCR] = { 0x1c000 }, 2095 [CAM_CC_TFE_1_BCR] = { 0x1d000 }, 2096 [CAM_CC_TFE_2_BCR] = { 0x1e000 }, 2097 }; 2098 2099 static struct gdsc *cam_cc_milos_gdscs[] = { 2100 [CAM_CC_CAMSS_TOP_GDSC] = &cam_cc_camss_top_gdsc, 2101 }; 2102 2103 static struct clk_alpha_pll *cam_cc_milos_plls[] = { 2104 &cam_cc_pll0, 2105 &cam_cc_pll1, 2106 &cam_cc_pll2, 2107 &cam_cc_pll3, 2108 &cam_cc_pll4, 2109 &cam_cc_pll5, 2110 &cam_cc_pll6, 2111 }; 2112 2113 static const u32 cam_cc_milos_critical_cbcrs[] = { 2114 0x25038, /* CAM_CC_GDSC_CLK */ 2115 0x2505c, /* CAM_CC_SLEEP_CLK */ 2116 }; 2117 2118 static const struct regmap_config cam_cc_milos_regmap_config = { 2119 .reg_bits = 32, 2120 .reg_stride = 4, 2121 .val_bits = 32, 2122 .max_register = 0x30728, 2123 .fast_io = true, 2124 }; 2125 2126 static const struct qcom_cc_driver_data cam_cc_milos_driver_data = { 2127 .alpha_plls = cam_cc_milos_plls, 2128 .num_alpha_plls = ARRAY_SIZE(cam_cc_milos_plls), 2129 .clk_cbcrs = cam_cc_milos_critical_cbcrs, 2130 .num_clk_cbcrs = ARRAY_SIZE(cam_cc_milos_critical_cbcrs), 2131 }; 2132 2133 static const struct qcom_cc_desc cam_cc_milos_desc = { 2134 .config = &cam_cc_milos_regmap_config, 2135 .clks = cam_cc_milos_clocks, 2136 .num_clks = ARRAY_SIZE(cam_cc_milos_clocks), 2137 .resets = cam_cc_milos_resets, 2138 .num_resets = ARRAY_SIZE(cam_cc_milos_resets), 2139 .gdscs = cam_cc_milos_gdscs, 2140 .num_gdscs = ARRAY_SIZE(cam_cc_milos_gdscs), 2141 .use_rpm = true, 2142 .driver_data = &cam_cc_milos_driver_data, 2143 }; 2144 2145 static const struct of_device_id cam_cc_milos_match_table[] = { 2146 { .compatible = "qcom,milos-camcc" }, 2147 { } 2148 }; 2149 MODULE_DEVICE_TABLE(of, cam_cc_milos_match_table); 2150 2151 static int cam_cc_milos_probe(struct platform_device *pdev) 2152 { 2153 return qcom_cc_probe(pdev, &cam_cc_milos_desc); 2154 } 2155 2156 static struct platform_driver cam_cc_milos_driver = { 2157 .probe = cam_cc_milos_probe, 2158 .driver = { 2159 .name = "cam_cc-milos", 2160 .of_match_table = cam_cc_milos_match_table, 2161 }, 2162 }; 2163 2164 module_platform_driver(cam_cc_milos_driver); 2165 2166 MODULE_DESCRIPTION("QTI CAM_CC Milos Driver"); 2167 MODULE_LICENSE("GPL"); 2168