1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. 4 * Copyright (c) 2025, Luca Weiss <luca.weiss@fairphone.com> 5 */ 6 7 #include <linux/clk-provider.h> 8 #include <linux/mod_devicetable.h> 9 #include <linux/module.h> 10 #include <linux/platform_device.h> 11 #include <linux/regmap.h> 12 13 #include <dt-bindings/clock/qcom,milos-camcc.h> 14 15 #include "clk-alpha-pll.h" 16 #include "clk-branch.h" 17 #include "clk-pll.h" 18 #include "clk-rcg.h" 19 #include "clk-regmap.h" 20 #include "clk-regmap-divider.h" 21 #include "clk-regmap-mux.h" 22 #include "common.h" 23 #include "gdsc.h" 24 #include "reset.h" 25 26 /* Need to match the order of clocks in DT binding */ 27 enum { 28 DT_BI_TCXO, 29 DT_SLEEP_CLK, 30 DT_IFACE, 31 }; 32 33 /* Need to match the order of interconnects in DT binding */ 34 enum { 35 DT_ICC_TOP_GDSC, 36 }; 37 38 enum { 39 P_BI_TCXO, 40 P_CAM_CC_PLL0_OUT_EVEN, 41 P_CAM_CC_PLL0_OUT_MAIN, 42 P_CAM_CC_PLL0_OUT_ODD, 43 P_CAM_CC_PLL1_OUT_EVEN, 44 P_CAM_CC_PLL1_OUT_MAIN, 45 P_CAM_CC_PLL2_OUT_MAIN, 46 P_CAM_CC_PLL3_OUT_EVEN, 47 P_CAM_CC_PLL4_OUT_EVEN, 48 P_CAM_CC_PLL4_OUT_MAIN, 49 P_CAM_CC_PLL5_OUT_EVEN, 50 P_CAM_CC_PLL5_OUT_MAIN, 51 P_CAM_CC_PLL6_OUT_EVEN, 52 P_CAM_CC_PLL6_OUT_MAIN, 53 P_SLEEP_CLK, 54 }; 55 56 static const struct pll_vco lucid_ole_vco[] = { 57 { 249600000, 2300000000, 0 }, 58 }; 59 60 static const struct pll_vco rivian_ole_vco[] = { 61 { 777000000, 1285000000, 0 }, 62 }; 63 64 /* 1200.0 MHz Configuration */ 65 static const struct alpha_pll_config cam_cc_pll0_config = { 66 .l = 0x3e, 67 .alpha = 0x8000, 68 .config_ctl_val = 0x20485699, 69 .config_ctl_hi_val = 0x00182261, 70 .config_ctl_hi1_val = 0x82aa299c, 71 .test_ctl_val = 0x00000000, 72 .test_ctl_hi_val = 0x00000003, 73 .test_ctl_hi1_val = 0x00009000, 74 .test_ctl_hi2_val = 0x00000034, 75 .user_ctl_val = 0x00008400, 76 .user_ctl_hi_val = 0x00000005, 77 }; 78 79 static struct clk_alpha_pll cam_cc_pll0 = { 80 .offset = 0x0, 81 .config = &cam_cc_pll0_config, 82 .vco_table = lucid_ole_vco, 83 .num_vco = ARRAY_SIZE(lucid_ole_vco), 84 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 85 .clkr = { 86 .hw.init = &(const struct clk_init_data) { 87 .name = "cam_cc_pll0", 88 .parent_data = &(const struct clk_parent_data) { 89 .index = DT_BI_TCXO, 90 }, 91 .num_parents = 1, 92 .ops = &clk_alpha_pll_lucid_evo_ops, 93 }, 94 }, 95 }; 96 97 static const struct clk_div_table post_div_table_cam_cc_pll0_out_even[] = { 98 { 0x1, 2 }, 99 { } 100 }; 101 102 static struct clk_alpha_pll_postdiv cam_cc_pll0_out_even = { 103 .offset = 0x0, 104 .post_div_shift = 10, 105 .post_div_table = post_div_table_cam_cc_pll0_out_even, 106 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll0_out_even), 107 .width = 4, 108 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 109 .clkr.hw.init = &(const struct clk_init_data) { 110 .name = "cam_cc_pll0_out_even", 111 .parent_hws = (const struct clk_hw*[]) { 112 &cam_cc_pll0.clkr.hw, 113 }, 114 .num_parents = 1, 115 .flags = CLK_SET_RATE_PARENT, 116 .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, 117 }, 118 }; 119 120 static const struct clk_div_table post_div_table_cam_cc_pll0_out_odd[] = { 121 { 0x2, 3 }, 122 { } 123 }; 124 125 static struct clk_alpha_pll_postdiv cam_cc_pll0_out_odd = { 126 .offset = 0x0, 127 .post_div_shift = 14, 128 .post_div_table = post_div_table_cam_cc_pll0_out_odd, 129 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll0_out_odd), 130 .width = 4, 131 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 132 .clkr.hw.init = &(const struct clk_init_data) { 133 .name = "cam_cc_pll0_out_odd", 134 .parent_hws = (const struct clk_hw*[]) { 135 &cam_cc_pll0.clkr.hw, 136 }, 137 .num_parents = 1, 138 .flags = CLK_SET_RATE_PARENT, 139 .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, 140 }, 141 }; 142 143 /* 600.0 MHz Configuration */ 144 static const struct alpha_pll_config cam_cc_pll1_config = { 145 .l = 0x1f, 146 .alpha = 0x4000, 147 .config_ctl_val = 0x20485699, 148 .config_ctl_hi_val = 0x00182261, 149 .config_ctl_hi1_val = 0x82aa299c, 150 .test_ctl_val = 0x00000000, 151 .test_ctl_hi_val = 0x00000003, 152 .test_ctl_hi1_val = 0x00009000, 153 .test_ctl_hi2_val = 0x00000034, 154 .user_ctl_val = 0x00000400, 155 .user_ctl_hi_val = 0x00000005, 156 }; 157 158 static struct clk_alpha_pll cam_cc_pll1 = { 159 .offset = 0x1000, 160 .config = &cam_cc_pll1_config, 161 .vco_table = lucid_ole_vco, 162 .num_vco = ARRAY_SIZE(lucid_ole_vco), 163 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 164 .clkr = { 165 .hw.init = &(const struct clk_init_data) { 166 .name = "cam_cc_pll1", 167 .parent_data = &(const struct clk_parent_data) { 168 .index = DT_BI_TCXO, 169 }, 170 .num_parents = 1, 171 .ops = &clk_alpha_pll_lucid_evo_ops, 172 }, 173 }, 174 }; 175 176 static const struct clk_div_table post_div_table_cam_cc_pll1_out_even[] = { 177 { 0x1, 2 }, 178 { } 179 }; 180 181 static struct clk_alpha_pll_postdiv cam_cc_pll1_out_even = { 182 .offset = 0x1000, 183 .post_div_shift = 10, 184 .post_div_table = post_div_table_cam_cc_pll1_out_even, 185 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll1_out_even), 186 .width = 4, 187 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 188 .clkr.hw.init = &(const struct clk_init_data) { 189 .name = "cam_cc_pll1_out_even", 190 .parent_hws = (const struct clk_hw*[]) { 191 &cam_cc_pll1.clkr.hw, 192 }, 193 .num_parents = 1, 194 .flags = CLK_SET_RATE_PARENT, 195 .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, 196 }, 197 }; 198 199 /* 960.0 MHz Configuration */ 200 static const struct alpha_pll_config cam_cc_pll2_config = { 201 .l = 0x32, 202 .alpha = 0x0, 203 .config_ctl_val = 0x10000030, 204 .config_ctl_hi_val = 0x80890263, 205 .config_ctl_hi1_val = 0x00000217, 206 .user_ctl_val = 0x00000001, 207 .user_ctl_hi_val = 0x00100000, 208 }; 209 210 static struct clk_alpha_pll cam_cc_pll2 = { 211 .offset = 0x2000, 212 .config = &cam_cc_pll2_config, 213 .vco_table = rivian_ole_vco, 214 .num_vco = ARRAY_SIZE(rivian_ole_vco), 215 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_RIVIAN_EVO], 216 .clkr = { 217 .hw.init = &(const struct clk_init_data) { 218 .name = "cam_cc_pll2", 219 .parent_data = &(const struct clk_parent_data) { 220 .index = DT_BI_TCXO, 221 }, 222 .num_parents = 1, 223 .ops = &clk_alpha_pll_rivian_evo_ops, 224 }, 225 }, 226 }; 227 228 /* 600.0 MHz Configuration */ 229 static const struct alpha_pll_config cam_cc_pll3_config = { 230 .l = 0x1f, 231 .alpha = 0x4000, 232 .config_ctl_val = 0x20485699, 233 .config_ctl_hi_val = 0x00182261, 234 .config_ctl_hi1_val = 0x82aa299c, 235 .test_ctl_val = 0x00000000, 236 .test_ctl_hi_val = 0x00000003, 237 .test_ctl_hi1_val = 0x00009000, 238 .test_ctl_hi2_val = 0x00000034, 239 .user_ctl_val = 0x00000400, 240 .user_ctl_hi_val = 0x00000005, 241 }; 242 243 static struct clk_alpha_pll cam_cc_pll3 = { 244 .offset = 0x3000, 245 .config = &cam_cc_pll3_config, 246 .vco_table = lucid_ole_vco, 247 .num_vco = ARRAY_SIZE(lucid_ole_vco), 248 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 249 .clkr = { 250 .hw.init = &(const struct clk_init_data) { 251 .name = "cam_cc_pll3", 252 .parent_data = &(const struct clk_parent_data) { 253 .index = DT_BI_TCXO, 254 }, 255 .num_parents = 1, 256 .ops = &clk_alpha_pll_lucid_evo_ops, 257 }, 258 }, 259 }; 260 261 static const struct clk_div_table post_div_table_cam_cc_pll3_out_even[] = { 262 { 0x1, 2 }, 263 { } 264 }; 265 266 static struct clk_alpha_pll_postdiv cam_cc_pll3_out_even = { 267 .offset = 0x3000, 268 .post_div_shift = 10, 269 .post_div_table = post_div_table_cam_cc_pll3_out_even, 270 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll3_out_even), 271 .width = 4, 272 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 273 .clkr.hw.init = &(const struct clk_init_data) { 274 .name = "cam_cc_pll3_out_even", 275 .parent_hws = (const struct clk_hw*[]) { 276 &cam_cc_pll3.clkr.hw, 277 }, 278 .num_parents = 1, 279 .flags = CLK_SET_RATE_PARENT, 280 .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, 281 }, 282 }; 283 284 /* 700.0 MHz Configuration */ 285 static const struct alpha_pll_config cam_cc_pll4_config = { 286 .l = 0x24, 287 .alpha = 0x7555, 288 .config_ctl_val = 0x20485699, 289 .config_ctl_hi_val = 0x00182261, 290 .config_ctl_hi1_val = 0x82aa299c, 291 .test_ctl_val = 0x00000000, 292 .test_ctl_hi_val = 0x00000003, 293 .test_ctl_hi1_val = 0x00009000, 294 .test_ctl_hi2_val = 0x00000034, 295 .user_ctl_val = 0x00000400, 296 .user_ctl_hi_val = 0x00000005, 297 }; 298 299 static struct clk_alpha_pll cam_cc_pll4 = { 300 .offset = 0x4000, 301 .config = &cam_cc_pll4_config, 302 .vco_table = lucid_ole_vco, 303 .num_vco = ARRAY_SIZE(lucid_ole_vco), 304 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 305 .clkr = { 306 .hw.init = &(const struct clk_init_data) { 307 .name = "cam_cc_pll4", 308 .parent_data = &(const struct clk_parent_data) { 309 .index = DT_BI_TCXO, 310 }, 311 .num_parents = 1, 312 .ops = &clk_alpha_pll_lucid_evo_ops, 313 }, 314 }, 315 }; 316 317 static const struct clk_div_table post_div_table_cam_cc_pll4_out_even[] = { 318 { 0x1, 2 }, 319 { } 320 }; 321 322 static struct clk_alpha_pll_postdiv cam_cc_pll4_out_even = { 323 .offset = 0x4000, 324 .post_div_shift = 10, 325 .post_div_table = post_div_table_cam_cc_pll4_out_even, 326 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll4_out_even), 327 .width = 4, 328 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 329 .clkr.hw.init = &(const struct clk_init_data) { 330 .name = "cam_cc_pll4_out_even", 331 .parent_hws = (const struct clk_hw*[]) { 332 &cam_cc_pll4.clkr.hw, 333 }, 334 .num_parents = 1, 335 .flags = CLK_SET_RATE_PARENT, 336 .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, 337 }, 338 }; 339 340 /* 700.0 MHz Configuration */ 341 static const struct alpha_pll_config cam_cc_pll5_config = { 342 .l = 0x24, 343 .alpha = 0x7555, 344 .config_ctl_val = 0x20485699, 345 .config_ctl_hi_val = 0x00182261, 346 .config_ctl_hi1_val = 0x82aa299c, 347 .test_ctl_val = 0x00000000, 348 .test_ctl_hi_val = 0x00000003, 349 .test_ctl_hi1_val = 0x00009000, 350 .test_ctl_hi2_val = 0x00000034, 351 .user_ctl_val = 0x00000400, 352 .user_ctl_hi_val = 0x00000005, 353 }; 354 355 static struct clk_alpha_pll cam_cc_pll5 = { 356 .offset = 0x5000, 357 .config = &cam_cc_pll5_config, 358 .vco_table = lucid_ole_vco, 359 .num_vco = ARRAY_SIZE(lucid_ole_vco), 360 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 361 .clkr = { 362 .hw.init = &(const struct clk_init_data) { 363 .name = "cam_cc_pll5", 364 .parent_data = &(const struct clk_parent_data) { 365 .index = DT_BI_TCXO, 366 }, 367 .num_parents = 1, 368 .ops = &clk_alpha_pll_lucid_evo_ops, 369 }, 370 }, 371 }; 372 373 static const struct clk_div_table post_div_table_cam_cc_pll5_out_even[] = { 374 { 0x1, 2 }, 375 { } 376 }; 377 378 static struct clk_alpha_pll_postdiv cam_cc_pll5_out_even = { 379 .offset = 0x5000, 380 .post_div_shift = 10, 381 .post_div_table = post_div_table_cam_cc_pll5_out_even, 382 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll5_out_even), 383 .width = 4, 384 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 385 .clkr.hw.init = &(const struct clk_init_data) { 386 .name = "cam_cc_pll5_out_even", 387 .parent_hws = (const struct clk_hw*[]) { 388 &cam_cc_pll5.clkr.hw, 389 }, 390 .num_parents = 1, 391 .flags = CLK_SET_RATE_PARENT, 392 .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, 393 }, 394 }; 395 396 /* 700.0 MHz Configuration */ 397 static const struct alpha_pll_config cam_cc_pll6_config = { 398 .l = 0x24, 399 .alpha = 0x7555, 400 .config_ctl_val = 0x20485699, 401 .config_ctl_hi_val = 0x00182261, 402 .config_ctl_hi1_val = 0x82aa299c, 403 .test_ctl_val = 0x00000000, 404 .test_ctl_hi_val = 0x00000003, 405 .test_ctl_hi1_val = 0x00009000, 406 .test_ctl_hi2_val = 0x00000034, 407 .user_ctl_val = 0x00000400, 408 .user_ctl_hi_val = 0x00000005, 409 }; 410 411 static struct clk_alpha_pll cam_cc_pll6 = { 412 .offset = 0x6000, 413 .config = &cam_cc_pll6_config, 414 .vco_table = lucid_ole_vco, 415 .num_vco = ARRAY_SIZE(lucid_ole_vco), 416 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 417 .clkr = { 418 .hw.init = &(const struct clk_init_data) { 419 .name = "cam_cc_pll6", 420 .parent_data = &(const struct clk_parent_data) { 421 .index = DT_BI_TCXO, 422 }, 423 .num_parents = 1, 424 .ops = &clk_alpha_pll_lucid_evo_ops, 425 }, 426 }, 427 }; 428 429 static const struct clk_div_table post_div_table_cam_cc_pll6_out_even[] = { 430 { 0x1, 2 }, 431 { } 432 }; 433 434 static struct clk_alpha_pll_postdiv cam_cc_pll6_out_even = { 435 .offset = 0x6000, 436 .post_div_shift = 10, 437 .post_div_table = post_div_table_cam_cc_pll6_out_even, 438 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll6_out_even), 439 .width = 4, 440 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 441 .clkr.hw.init = &(const struct clk_init_data) { 442 .name = "cam_cc_pll6_out_even", 443 .parent_hws = (const struct clk_hw*[]) { 444 &cam_cc_pll6.clkr.hw, 445 }, 446 .num_parents = 1, 447 .flags = CLK_SET_RATE_PARENT, 448 .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, 449 }, 450 }; 451 452 static const struct parent_map cam_cc_parent_map_0[] = { 453 { P_BI_TCXO, 0 }, 454 { P_CAM_CC_PLL0_OUT_MAIN, 1 }, 455 { P_CAM_CC_PLL0_OUT_ODD, 5 }, 456 { P_CAM_CC_PLL0_OUT_EVEN, 6 }, 457 }; 458 459 static const struct clk_parent_data cam_cc_parent_data_0[] = { 460 { .index = DT_BI_TCXO }, 461 { .hw = &cam_cc_pll0.clkr.hw }, 462 { .hw = &cam_cc_pll0_out_odd.clkr.hw }, 463 { .hw = &cam_cc_pll0_out_even.clkr.hw }, 464 }; 465 466 static const struct parent_map cam_cc_parent_map_1[] = { 467 { P_BI_TCXO, 0 }, 468 { P_CAM_CC_PLL2_OUT_MAIN, 4 }, 469 }; 470 471 static const struct clk_parent_data cam_cc_parent_data_1[] = { 472 { .index = DT_BI_TCXO }, 473 { .hw = &cam_cc_pll2.clkr.hw }, 474 }; 475 476 static const struct parent_map cam_cc_parent_map_2[] = { 477 { P_BI_TCXO, 0 }, 478 { P_CAM_CC_PLL0_OUT_MAIN, 1 }, 479 { P_CAM_CC_PLL1_OUT_MAIN, 2 }, 480 { P_CAM_CC_PLL1_OUT_EVEN, 3 }, 481 { P_CAM_CC_PLL0_OUT_ODD, 5 }, 482 { P_CAM_CC_PLL0_OUT_EVEN, 6 }, 483 }; 484 485 static const struct clk_parent_data cam_cc_parent_data_2[] = { 486 { .index = DT_BI_TCXO }, 487 { .hw = &cam_cc_pll0.clkr.hw }, 488 { .hw = &cam_cc_pll1.clkr.hw }, 489 { .hw = &cam_cc_pll1_out_even.clkr.hw }, 490 { .hw = &cam_cc_pll0_out_odd.clkr.hw }, 491 { .hw = &cam_cc_pll0_out_even.clkr.hw }, 492 }; 493 494 static const struct parent_map cam_cc_parent_map_3[] = { 495 { P_BI_TCXO, 0 }, 496 { P_CAM_CC_PLL0_OUT_ODD, 5 }, 497 { P_CAM_CC_PLL0_OUT_EVEN, 6 }, 498 }; 499 500 static const struct clk_parent_data cam_cc_parent_data_3[] = { 501 { .index = DT_BI_TCXO }, 502 { .hw = &cam_cc_pll0_out_odd.clkr.hw }, 503 { .hw = &cam_cc_pll0_out_even.clkr.hw }, 504 }; 505 506 static const struct parent_map cam_cc_parent_map_4[] = { 507 { P_BI_TCXO, 0 }, 508 { P_CAM_CC_PLL0_OUT_MAIN, 1 }, 509 { P_CAM_CC_PLL0_OUT_EVEN, 6 }, 510 }; 511 512 static const struct clk_parent_data cam_cc_parent_data_4[] = { 513 { .index = DT_BI_TCXO }, 514 { .hw = &cam_cc_pll0.clkr.hw }, 515 { .hw = &cam_cc_pll0_out_even.clkr.hw }, 516 }; 517 518 static const struct parent_map cam_cc_parent_map_5[] = { 519 { P_BI_TCXO, 0 }, 520 { P_CAM_CC_PLL0_OUT_MAIN, 1 }, 521 { P_CAM_CC_PLL3_OUT_EVEN, 5 }, 522 { P_CAM_CC_PLL0_OUT_EVEN, 6 }, 523 }; 524 525 static const struct clk_parent_data cam_cc_parent_data_5[] = { 526 { .index = DT_BI_TCXO }, 527 { .hw = &cam_cc_pll0.clkr.hw }, 528 { .hw = &cam_cc_pll3_out_even.clkr.hw }, 529 { .hw = &cam_cc_pll0_out_even.clkr.hw }, 530 }; 531 532 static const struct parent_map cam_cc_parent_map_6[] = { 533 { P_SLEEP_CLK, 0 }, 534 }; 535 536 static const struct clk_parent_data cam_cc_parent_data_6_ao[] = { 537 { .index = DT_SLEEP_CLK }, 538 }; 539 540 static const struct parent_map cam_cc_parent_map_7[] = { 541 { P_BI_TCXO, 0 }, 542 { P_CAM_CC_PLL0_OUT_MAIN, 1 }, 543 { P_CAM_CC_PLL4_OUT_EVEN, 2 }, 544 { P_CAM_CC_PLL4_OUT_MAIN, 3 }, 545 { P_CAM_CC_PLL0_OUT_ODD, 5 }, 546 { P_CAM_CC_PLL0_OUT_EVEN, 6 }, 547 }; 548 549 static const struct clk_parent_data cam_cc_parent_data_7[] = { 550 { .index = DT_BI_TCXO }, 551 { .hw = &cam_cc_pll0.clkr.hw }, 552 { .hw = &cam_cc_pll4_out_even.clkr.hw }, 553 { .hw = &cam_cc_pll4.clkr.hw }, 554 { .hw = &cam_cc_pll0_out_odd.clkr.hw }, 555 { .hw = &cam_cc_pll0_out_even.clkr.hw }, 556 }; 557 558 static const struct parent_map cam_cc_parent_map_8[] = { 559 { P_BI_TCXO, 0 }, 560 { P_CAM_CC_PLL0_OUT_MAIN, 1 }, 561 { P_CAM_CC_PLL5_OUT_EVEN, 2 }, 562 { P_CAM_CC_PLL5_OUT_MAIN, 3 }, 563 { P_CAM_CC_PLL0_OUT_ODD, 5 }, 564 { P_CAM_CC_PLL0_OUT_EVEN, 6 }, 565 }; 566 567 static const struct clk_parent_data cam_cc_parent_data_8[] = { 568 { .index = DT_BI_TCXO }, 569 { .hw = &cam_cc_pll0.clkr.hw }, 570 { .hw = &cam_cc_pll5_out_even.clkr.hw }, 571 { .hw = &cam_cc_pll5.clkr.hw }, 572 { .hw = &cam_cc_pll0_out_odd.clkr.hw }, 573 { .hw = &cam_cc_pll0_out_even.clkr.hw }, 574 }; 575 576 static const struct parent_map cam_cc_parent_map_9[] = { 577 { P_BI_TCXO, 0 }, 578 { P_CAM_CC_PLL0_OUT_MAIN, 1 }, 579 { P_CAM_CC_PLL6_OUT_EVEN, 2 }, 580 { P_CAM_CC_PLL6_OUT_MAIN, 3 }, 581 { P_CAM_CC_PLL0_OUT_ODD, 5 }, 582 { P_CAM_CC_PLL0_OUT_EVEN, 6 }, 583 }; 584 585 static const struct clk_parent_data cam_cc_parent_data_9[] = { 586 { .index = DT_BI_TCXO }, 587 { .hw = &cam_cc_pll0.clkr.hw }, 588 { .hw = &cam_cc_pll6_out_even.clkr.hw }, 589 { .hw = &cam_cc_pll6.clkr.hw }, 590 { .hw = &cam_cc_pll0_out_odd.clkr.hw }, 591 { .hw = &cam_cc_pll0_out_even.clkr.hw }, 592 }; 593 594 static const struct parent_map cam_cc_parent_map_10[] = { 595 { P_BI_TCXO, 0 }, 596 }; 597 598 static const struct clk_parent_data cam_cc_parent_data_10[] = { 599 { .index = DT_BI_TCXO }, 600 }; 601 602 static const struct freq_tbl ftbl_cam_cc_bps_clk_src[] = { 603 F(300000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), 604 F(410000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), 605 F(460000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), 606 F(600000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), 607 F(700000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), 608 { } 609 }; 610 611 static struct clk_rcg2 cam_cc_bps_clk_src = { 612 .cmd_rcgr = 0x1a004, 613 .mnd_width = 0, 614 .hid_width = 5, 615 .parent_map = cam_cc_parent_map_2, 616 .freq_tbl = ftbl_cam_cc_bps_clk_src, 617 .clkr.hw.init = &(const struct clk_init_data) { 618 .name = "cam_cc_bps_clk_src", 619 .parent_data = cam_cc_parent_data_2, 620 .num_parents = ARRAY_SIZE(cam_cc_parent_data_2), 621 .flags = CLK_SET_RATE_PARENT, 622 .ops = &clk_rcg2_shared_ops, 623 }, 624 }; 625 626 static const struct freq_tbl ftbl_cam_cc_camnoc_axi_clk_src[] = { 627 F(150000000, P_CAM_CC_PLL0_OUT_EVEN, 4, 0, 0), 628 F(240000000, P_CAM_CC_PLL0_OUT_EVEN, 2.5, 0, 0), 629 F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0), 630 F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), 631 { } 632 }; 633 634 static struct clk_rcg2 cam_cc_camnoc_axi_clk_src = { 635 .cmd_rcgr = 0x2401c, 636 .mnd_width = 0, 637 .hid_width = 5, 638 .parent_map = cam_cc_parent_map_0, 639 .freq_tbl = ftbl_cam_cc_camnoc_axi_clk_src, 640 .clkr.hw.init = &(const struct clk_init_data) { 641 .name = "cam_cc_camnoc_axi_clk_src", 642 .parent_data = cam_cc_parent_data_0, 643 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 644 .flags = CLK_SET_RATE_PARENT, 645 .ops = &clk_rcg2_shared_ops, 646 }, 647 }; 648 649 static const struct freq_tbl ftbl_cam_cc_cci_0_clk_src[] = { 650 F(37500000, P_CAM_CC_PLL0_OUT_EVEN, 16, 0, 0), 651 F(50000000, P_CAM_CC_PLL0_OUT_EVEN, 12, 0, 0), 652 F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0), 653 { } 654 }; 655 656 static struct clk_rcg2 cam_cc_cci_0_clk_src = { 657 .cmd_rcgr = 0x21004, 658 .mnd_width = 8, 659 .hid_width = 5, 660 .parent_map = cam_cc_parent_map_3, 661 .freq_tbl = ftbl_cam_cc_cci_0_clk_src, 662 .clkr.hw.init = &(const struct clk_init_data) { 663 .name = "cam_cc_cci_0_clk_src", 664 .parent_data = cam_cc_parent_data_3, 665 .num_parents = ARRAY_SIZE(cam_cc_parent_data_3), 666 .flags = CLK_SET_RATE_PARENT, 667 .ops = &clk_rcg2_shared_ops, 668 }, 669 }; 670 671 static struct clk_rcg2 cam_cc_cci_1_clk_src = { 672 .cmd_rcgr = 0x22004, 673 .mnd_width = 8, 674 .hid_width = 5, 675 .parent_map = cam_cc_parent_map_3, 676 .freq_tbl = ftbl_cam_cc_cci_0_clk_src, 677 .clkr.hw.init = &(const struct clk_init_data) { 678 .name = "cam_cc_cci_1_clk_src", 679 .parent_data = cam_cc_parent_data_3, 680 .num_parents = ARRAY_SIZE(cam_cc_parent_data_3), 681 .flags = CLK_SET_RATE_PARENT, 682 .ops = &clk_rcg2_shared_ops, 683 }, 684 }; 685 686 static const struct freq_tbl ftbl_cam_cc_cphy_rx_clk_src[] = { 687 F(200000000, P_CAM_CC_PLL0_OUT_EVEN, 3, 0, 0), 688 F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0), 689 F(400000000, P_CAM_CC_PLL0_OUT_EVEN, 1.5, 0, 0), 690 { } 691 }; 692 693 static struct clk_rcg2 cam_cc_cphy_rx_clk_src = { 694 .cmd_rcgr = 0x1c05c, 695 .mnd_width = 0, 696 .hid_width = 5, 697 .parent_map = cam_cc_parent_map_0, 698 .freq_tbl = ftbl_cam_cc_cphy_rx_clk_src, 699 .clkr.hw.init = &(const struct clk_init_data) { 700 .name = "cam_cc_cphy_rx_clk_src", 701 .parent_data = cam_cc_parent_data_0, 702 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 703 .flags = CLK_SET_RATE_PARENT, 704 .ops = &clk_rcg2_shared_ops, 705 }, 706 }; 707 708 static const struct freq_tbl ftbl_cam_cc_cre_clk_src[] = { 709 F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0), 710 F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), 711 F(600000000, P_CAM_CC_PLL0_OUT_MAIN, 2, 0, 0), 712 { } 713 }; 714 715 static struct clk_rcg2 cam_cc_cre_clk_src = { 716 .cmd_rcgr = 0x27004, 717 .mnd_width = 0, 718 .hid_width = 5, 719 .parent_map = cam_cc_parent_map_2, 720 .freq_tbl = ftbl_cam_cc_cre_clk_src, 721 .clkr.hw.init = &(const struct clk_init_data) { 722 .name = "cam_cc_cre_clk_src", 723 .parent_data = cam_cc_parent_data_2, 724 .num_parents = ARRAY_SIZE(cam_cc_parent_data_2), 725 .flags = CLK_SET_RATE_PARENT, 726 .ops = &clk_rcg2_shared_ops, 727 }, 728 }; 729 730 static const struct freq_tbl ftbl_cam_cc_csi0phytimer_clk_src[] = { 731 F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0), 732 { } 733 }; 734 735 static struct clk_rcg2 cam_cc_csi0phytimer_clk_src = { 736 .cmd_rcgr = 0x19004, 737 .mnd_width = 0, 738 .hid_width = 5, 739 .parent_map = cam_cc_parent_map_0, 740 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, 741 .clkr.hw.init = &(const struct clk_init_data) { 742 .name = "cam_cc_csi0phytimer_clk_src", 743 .parent_data = cam_cc_parent_data_0, 744 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 745 .flags = CLK_SET_RATE_PARENT, 746 .ops = &clk_rcg2_shared_ops, 747 }, 748 }; 749 750 static struct clk_rcg2 cam_cc_csi1phytimer_clk_src = { 751 .cmd_rcgr = 0x19028, 752 .mnd_width = 0, 753 .hid_width = 5, 754 .parent_map = cam_cc_parent_map_0, 755 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, 756 .clkr.hw.init = &(const struct clk_init_data) { 757 .name = "cam_cc_csi1phytimer_clk_src", 758 .parent_data = cam_cc_parent_data_0, 759 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 760 .flags = CLK_SET_RATE_PARENT, 761 .ops = &clk_rcg2_shared_ops, 762 }, 763 }; 764 765 static struct clk_rcg2 cam_cc_csi2phytimer_clk_src = { 766 .cmd_rcgr = 0x1904c, 767 .mnd_width = 0, 768 .hid_width = 5, 769 .parent_map = cam_cc_parent_map_0, 770 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, 771 .clkr.hw.init = &(const struct clk_init_data) { 772 .name = "cam_cc_csi2phytimer_clk_src", 773 .parent_data = cam_cc_parent_data_0, 774 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 775 .flags = CLK_SET_RATE_PARENT, 776 .ops = &clk_rcg2_shared_ops, 777 }, 778 }; 779 780 static struct clk_rcg2 cam_cc_csi3phytimer_clk_src = { 781 .cmd_rcgr = 0x19070, 782 .mnd_width = 0, 783 .hid_width = 5, 784 .parent_map = cam_cc_parent_map_0, 785 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, 786 .clkr.hw.init = &(const struct clk_init_data) { 787 .name = "cam_cc_csi3phytimer_clk_src", 788 .parent_data = cam_cc_parent_data_0, 789 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 790 .flags = CLK_SET_RATE_PARENT, 791 .ops = &clk_rcg2_shared_ops, 792 }, 793 }; 794 795 static const struct freq_tbl ftbl_cam_cc_fast_ahb_clk_src[] = { 796 F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0), 797 F(150000000, P_CAM_CC_PLL0_OUT_EVEN, 4, 0, 0), 798 F(200000000, P_CAM_CC_PLL0_OUT_MAIN, 6, 0, 0), 799 F(240000000, P_CAM_CC_PLL0_OUT_MAIN, 5, 0, 0), 800 { } 801 }; 802 803 static struct clk_rcg2 cam_cc_fast_ahb_clk_src = { 804 .cmd_rcgr = 0x1a030, 805 .mnd_width = 0, 806 .hid_width = 5, 807 .parent_map = cam_cc_parent_map_0, 808 .freq_tbl = ftbl_cam_cc_fast_ahb_clk_src, 809 .clkr.hw.init = &(const struct clk_init_data) { 810 .name = "cam_cc_fast_ahb_clk_src", 811 .parent_data = cam_cc_parent_data_0, 812 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 813 .flags = CLK_SET_RATE_PARENT, 814 .ops = &clk_rcg2_shared_ops, 815 }, 816 }; 817 818 static const struct freq_tbl ftbl_cam_cc_icp_clk_src[] = { 819 F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0), 820 F(480000000, P_CAM_CC_PLL0_OUT_MAIN, 2.5, 0, 0), 821 F(600000000, P_CAM_CC_PLL0_OUT_MAIN, 2, 0, 0), 822 { } 823 }; 824 825 static struct clk_rcg2 cam_cc_icp_clk_src = { 826 .cmd_rcgr = 0x20014, 827 .mnd_width = 0, 828 .hid_width = 5, 829 .parent_map = cam_cc_parent_map_4, 830 .freq_tbl = ftbl_cam_cc_icp_clk_src, 831 .clkr.hw.init = &(const struct clk_init_data) { 832 .name = "cam_cc_icp_clk_src", 833 .parent_data = cam_cc_parent_data_4, 834 .num_parents = ARRAY_SIZE(cam_cc_parent_data_4), 835 .flags = CLK_SET_RATE_PARENT, 836 .ops = &clk_rcg2_shared_ops, 837 }, 838 }; 839 840 static const struct freq_tbl ftbl_cam_cc_mclk0_clk_src[] = { 841 F(19200000, P_CAM_CC_PLL2_OUT_MAIN, 1, 1, 50), 842 F(24000000, P_CAM_CC_PLL2_OUT_MAIN, 10, 1, 4), 843 F(64000000, P_CAM_CC_PLL2_OUT_MAIN, 15, 0, 0), 844 { } 845 }; 846 847 static struct clk_rcg2 cam_cc_mclk0_clk_src = { 848 .cmd_rcgr = 0x18004, 849 .mnd_width = 8, 850 .hid_width = 5, 851 .parent_map = cam_cc_parent_map_1, 852 .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 853 .clkr.hw.init = &(const struct clk_init_data) { 854 .name = "cam_cc_mclk0_clk_src", 855 .parent_data = cam_cc_parent_data_1, 856 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 857 .flags = CLK_SET_RATE_PARENT, 858 .ops = &clk_rcg2_shared_ops, 859 }, 860 }; 861 862 static struct clk_rcg2 cam_cc_mclk1_clk_src = { 863 .cmd_rcgr = 0x18024, 864 .mnd_width = 8, 865 .hid_width = 5, 866 .parent_map = cam_cc_parent_map_1, 867 .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 868 .clkr.hw.init = &(const struct clk_init_data) { 869 .name = "cam_cc_mclk1_clk_src", 870 .parent_data = cam_cc_parent_data_1, 871 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 872 .flags = CLK_SET_RATE_PARENT, 873 .ops = &clk_rcg2_shared_ops, 874 }, 875 }; 876 877 static struct clk_rcg2 cam_cc_mclk2_clk_src = { 878 .cmd_rcgr = 0x18044, 879 .mnd_width = 8, 880 .hid_width = 5, 881 .parent_map = cam_cc_parent_map_1, 882 .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 883 .clkr.hw.init = &(const struct clk_init_data) { 884 .name = "cam_cc_mclk2_clk_src", 885 .parent_data = cam_cc_parent_data_1, 886 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 887 .flags = CLK_SET_RATE_PARENT, 888 .ops = &clk_rcg2_shared_ops, 889 }, 890 }; 891 892 static struct clk_rcg2 cam_cc_mclk3_clk_src = { 893 .cmd_rcgr = 0x18064, 894 .mnd_width = 8, 895 .hid_width = 5, 896 .parent_map = cam_cc_parent_map_1, 897 .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 898 .clkr.hw.init = &(const struct clk_init_data) { 899 .name = "cam_cc_mclk3_clk_src", 900 .parent_data = cam_cc_parent_data_1, 901 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 902 .flags = CLK_SET_RATE_PARENT, 903 .ops = &clk_rcg2_shared_ops, 904 }, 905 }; 906 907 static struct clk_rcg2 cam_cc_mclk4_clk_src = { 908 .cmd_rcgr = 0x18084, 909 .mnd_width = 8, 910 .hid_width = 5, 911 .parent_map = cam_cc_parent_map_1, 912 .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 913 .clkr.hw.init = &(const struct clk_init_data) { 914 .name = "cam_cc_mclk4_clk_src", 915 .parent_data = cam_cc_parent_data_1, 916 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 917 .flags = CLK_SET_RATE_PARENT, 918 .ops = &clk_rcg2_shared_ops, 919 }, 920 }; 921 922 static const struct freq_tbl ftbl_cam_cc_ope_0_clk_src[] = { 923 F(300000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), 924 F(410000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), 925 F(520000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), 926 F(645000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), 927 F(700000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), 928 { } 929 }; 930 931 static struct clk_rcg2 cam_cc_ope_0_clk_src = { 932 .cmd_rcgr = 0x1b004, 933 .mnd_width = 0, 934 .hid_width = 5, 935 .parent_map = cam_cc_parent_map_5, 936 .freq_tbl = ftbl_cam_cc_ope_0_clk_src, 937 .clkr.hw.init = &(const struct clk_init_data) { 938 .name = "cam_cc_ope_0_clk_src", 939 .parent_data = cam_cc_parent_data_5, 940 .num_parents = ARRAY_SIZE(cam_cc_parent_data_5), 941 .flags = CLK_SET_RATE_PARENT, 942 .ops = &clk_rcg2_shared_ops, 943 }, 944 }; 945 946 static const struct freq_tbl ftbl_cam_cc_sleep_clk_src[] = { 947 F(32000, P_SLEEP_CLK, 1, 0, 0), 948 { } 949 }; 950 951 static struct clk_rcg2 cam_cc_sleep_clk_src = { 952 .cmd_rcgr = 0x25044, 953 .mnd_width = 0, 954 .hid_width = 5, 955 .parent_map = cam_cc_parent_map_6, 956 .freq_tbl = ftbl_cam_cc_sleep_clk_src, 957 .clkr.hw.init = &(const struct clk_init_data) { 958 .name = "cam_cc_sleep_clk_src", 959 .parent_data = cam_cc_parent_data_6_ao, 960 .num_parents = ARRAY_SIZE(cam_cc_parent_data_6_ao), 961 .flags = CLK_SET_RATE_PARENT, 962 .ops = &clk_rcg2_ops, 963 }, 964 }; 965 966 static const struct freq_tbl ftbl_cam_cc_slow_ahb_clk_src[] = { 967 F(80000000, P_CAM_CC_PLL0_OUT_EVEN, 7.5, 0, 0), 968 { } 969 }; 970 971 static struct clk_rcg2 cam_cc_slow_ahb_clk_src = { 972 .cmd_rcgr = 0x1a04c, 973 .mnd_width = 0, 974 .hid_width = 5, 975 .parent_map = cam_cc_parent_map_0, 976 .freq_tbl = ftbl_cam_cc_slow_ahb_clk_src, 977 .clkr.hw.init = &(const struct clk_init_data) { 978 .name = "cam_cc_slow_ahb_clk_src", 979 .parent_data = cam_cc_parent_data_0, 980 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 981 .flags = CLK_SET_RATE_PARENT, 982 .ops = &clk_rcg2_shared_ops, 983 }, 984 }; 985 986 static const struct freq_tbl ftbl_cam_cc_tfe_0_clk_src[] = { 987 F(350000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), 988 F(570000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), 989 F(600000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), 990 F(725000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), 991 { } 992 }; 993 994 static struct clk_rcg2 cam_cc_tfe_0_clk_src = { 995 .cmd_rcgr = 0x1c004, 996 .mnd_width = 0, 997 .hid_width = 5, 998 .parent_map = cam_cc_parent_map_7, 999 .freq_tbl = ftbl_cam_cc_tfe_0_clk_src, 1000 .clkr.hw.init = &(const struct clk_init_data) { 1001 .name = "cam_cc_tfe_0_clk_src", 1002 .parent_data = cam_cc_parent_data_7, 1003 .num_parents = ARRAY_SIZE(cam_cc_parent_data_7), 1004 .flags = CLK_SET_RATE_PARENT, 1005 .ops = &clk_rcg2_shared_ops, 1006 }, 1007 }; 1008 1009 static struct clk_rcg2 cam_cc_tfe_0_csid_clk_src = { 1010 .cmd_rcgr = 0x1c030, 1011 .mnd_width = 0, 1012 .hid_width = 5, 1013 .parent_map = cam_cc_parent_map_0, 1014 .freq_tbl = ftbl_cam_cc_cphy_rx_clk_src, 1015 .clkr.hw.init = &(const struct clk_init_data) { 1016 .name = "cam_cc_tfe_0_csid_clk_src", 1017 .parent_data = cam_cc_parent_data_0, 1018 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 1019 .flags = CLK_SET_RATE_PARENT, 1020 .ops = &clk_rcg2_shared_ops, 1021 }, 1022 }; 1023 1024 static const struct freq_tbl ftbl_cam_cc_tfe_1_clk_src[] = { 1025 F(350000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0), 1026 F(570000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0), 1027 F(600000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0), 1028 F(725000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0), 1029 { } 1030 }; 1031 1032 static struct clk_rcg2 cam_cc_tfe_1_clk_src = { 1033 .cmd_rcgr = 0x1d004, 1034 .mnd_width = 0, 1035 .hid_width = 5, 1036 .parent_map = cam_cc_parent_map_8, 1037 .freq_tbl = ftbl_cam_cc_tfe_1_clk_src, 1038 .clkr.hw.init = &(const struct clk_init_data) { 1039 .name = "cam_cc_tfe_1_clk_src", 1040 .parent_data = cam_cc_parent_data_8, 1041 .num_parents = ARRAY_SIZE(cam_cc_parent_data_8), 1042 .flags = CLK_SET_RATE_PARENT, 1043 .ops = &clk_rcg2_shared_ops, 1044 }, 1045 }; 1046 1047 static struct clk_rcg2 cam_cc_tfe_1_csid_clk_src = { 1048 .cmd_rcgr = 0x1d030, 1049 .mnd_width = 0, 1050 .hid_width = 5, 1051 .parent_map = cam_cc_parent_map_0, 1052 .freq_tbl = ftbl_cam_cc_cphy_rx_clk_src, 1053 .clkr.hw.init = &(const struct clk_init_data) { 1054 .name = "cam_cc_tfe_1_csid_clk_src", 1055 .parent_data = cam_cc_parent_data_0, 1056 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 1057 .flags = CLK_SET_RATE_PARENT, 1058 .ops = &clk_rcg2_shared_ops, 1059 }, 1060 }; 1061 1062 static const struct freq_tbl ftbl_cam_cc_tfe_2_clk_src[] = { 1063 F(350000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0), 1064 F(570000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0), 1065 F(600000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0), 1066 F(725000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0), 1067 { } 1068 }; 1069 1070 static struct clk_rcg2 cam_cc_tfe_2_clk_src = { 1071 .cmd_rcgr = 0x1e004, 1072 .mnd_width = 0, 1073 .hid_width = 5, 1074 .parent_map = cam_cc_parent_map_9, 1075 .freq_tbl = ftbl_cam_cc_tfe_2_clk_src, 1076 .clkr.hw.init = &(const struct clk_init_data) { 1077 .name = "cam_cc_tfe_2_clk_src", 1078 .parent_data = cam_cc_parent_data_9, 1079 .num_parents = ARRAY_SIZE(cam_cc_parent_data_9), 1080 .flags = CLK_SET_RATE_PARENT, 1081 .ops = &clk_rcg2_shared_ops, 1082 }, 1083 }; 1084 1085 static struct clk_rcg2 cam_cc_tfe_2_csid_clk_src = { 1086 .cmd_rcgr = 0x1e030, 1087 .mnd_width = 0, 1088 .hid_width = 5, 1089 .parent_map = cam_cc_parent_map_0, 1090 .freq_tbl = ftbl_cam_cc_cphy_rx_clk_src, 1091 .clkr.hw.init = &(const struct clk_init_data) { 1092 .name = "cam_cc_tfe_2_csid_clk_src", 1093 .parent_data = cam_cc_parent_data_0, 1094 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 1095 .flags = CLK_SET_RATE_PARENT, 1096 .ops = &clk_rcg2_shared_ops, 1097 }, 1098 }; 1099 1100 static const struct freq_tbl ftbl_cam_cc_xo_clk_src[] = { 1101 F(19200000, P_BI_TCXO, 1, 0, 0), 1102 { } 1103 }; 1104 1105 static struct clk_rcg2 cam_cc_xo_clk_src = { 1106 .cmd_rcgr = 0x25020, 1107 .mnd_width = 0, 1108 .hid_width = 5, 1109 .parent_map = cam_cc_parent_map_10, 1110 .freq_tbl = ftbl_cam_cc_xo_clk_src, 1111 .clkr.hw.init = &(const struct clk_init_data) { 1112 .name = "cam_cc_xo_clk_src", 1113 .parent_data = cam_cc_parent_data_10, 1114 .num_parents = ARRAY_SIZE(cam_cc_parent_data_10), 1115 .flags = CLK_SET_RATE_PARENT, 1116 .ops = &clk_rcg2_ops, 1117 }, 1118 }; 1119 1120 static struct clk_branch cam_cc_bps_ahb_clk = { 1121 .halt_reg = 0x1a064, 1122 .halt_check = BRANCH_HALT, 1123 .clkr = { 1124 .enable_reg = 0x1a064, 1125 .enable_mask = BIT(0), 1126 .hw.init = &(const struct clk_init_data) { 1127 .name = "cam_cc_bps_ahb_clk", 1128 .parent_hws = (const struct clk_hw*[]) { 1129 &cam_cc_slow_ahb_clk_src.clkr.hw, 1130 }, 1131 .num_parents = 1, 1132 .flags = CLK_SET_RATE_PARENT, 1133 .ops = &clk_branch2_ops, 1134 }, 1135 }, 1136 }; 1137 1138 static struct clk_branch cam_cc_bps_areg_clk = { 1139 .halt_reg = 0x1a048, 1140 .halt_check = BRANCH_HALT, 1141 .clkr = { 1142 .enable_reg = 0x1a048, 1143 .enable_mask = BIT(0), 1144 .hw.init = &(const struct clk_init_data) { 1145 .name = "cam_cc_bps_areg_clk", 1146 .parent_hws = (const struct clk_hw*[]) { 1147 &cam_cc_fast_ahb_clk_src.clkr.hw, 1148 }, 1149 .num_parents = 1, 1150 .flags = CLK_SET_RATE_PARENT, 1151 .ops = &clk_branch2_ops, 1152 }, 1153 }, 1154 }; 1155 1156 static struct clk_branch cam_cc_bps_clk = { 1157 .halt_reg = 0x1a01c, 1158 .halt_check = BRANCH_HALT, 1159 .clkr = { 1160 .enable_reg = 0x1a01c, 1161 .enable_mask = BIT(0), 1162 .hw.init = &(const struct clk_init_data) { 1163 .name = "cam_cc_bps_clk", 1164 .parent_hws = (const struct clk_hw*[]) { 1165 &cam_cc_bps_clk_src.clkr.hw, 1166 }, 1167 .num_parents = 1, 1168 .flags = CLK_SET_RATE_PARENT, 1169 .ops = &clk_branch2_ops, 1170 }, 1171 }, 1172 }; 1173 1174 static struct clk_branch cam_cc_camnoc_atb_clk = { 1175 .halt_reg = 0x24040, 1176 .halt_check = BRANCH_HALT, 1177 .clkr = { 1178 .enable_reg = 0x24040, 1179 .enable_mask = BIT(0), 1180 .hw.init = &(const struct clk_init_data) { 1181 .name = "cam_cc_camnoc_atb_clk", 1182 .ops = &clk_branch2_ops, 1183 }, 1184 }, 1185 }; 1186 1187 static struct clk_branch cam_cc_camnoc_axi_hf_clk = { 1188 .halt_reg = 0x24010, 1189 .halt_check = BRANCH_HALT, 1190 .clkr = { 1191 .enable_reg = 0x24010, 1192 .enable_mask = BIT(0), 1193 .hw.init = &(const struct clk_init_data) { 1194 .name = "cam_cc_camnoc_axi_hf_clk", 1195 .ops = &clk_branch2_ops, 1196 }, 1197 }, 1198 }; 1199 1200 static struct clk_branch cam_cc_camnoc_axi_sf_clk = { 1201 .halt_reg = 0x24004, 1202 .halt_check = BRANCH_HALT, 1203 .clkr = { 1204 .enable_reg = 0x24004, 1205 .enable_mask = BIT(0), 1206 .hw.init = &(const struct clk_init_data) { 1207 .name = "cam_cc_camnoc_axi_sf_clk", 1208 .ops = &clk_branch2_ops, 1209 }, 1210 }, 1211 }; 1212 1213 static struct clk_branch cam_cc_camnoc_nrt_axi_clk = { 1214 .halt_reg = 0x2404c, 1215 .halt_check = BRANCH_HALT_VOTED, 1216 .hwcg_reg = 0x2404c, 1217 .hwcg_bit = 1, 1218 .clkr = { 1219 .enable_reg = 0x2404c, 1220 .enable_mask = BIT(0), 1221 .hw.init = &(const struct clk_init_data) { 1222 .name = "cam_cc_camnoc_nrt_axi_clk", 1223 .parent_hws = (const struct clk_hw*[]) { 1224 &cam_cc_camnoc_axi_clk_src.clkr.hw, 1225 }, 1226 .num_parents = 1, 1227 .flags = CLK_SET_RATE_PARENT, 1228 .ops = &clk_branch2_ops, 1229 }, 1230 }, 1231 }; 1232 1233 static struct clk_branch cam_cc_camnoc_rt_axi_clk = { 1234 .halt_reg = 0x24034, 1235 .halt_check = BRANCH_HALT, 1236 .clkr = { 1237 .enable_reg = 0x24034, 1238 .enable_mask = BIT(0), 1239 .hw.init = &(const struct clk_init_data) { 1240 .name = "cam_cc_camnoc_rt_axi_clk", 1241 .parent_hws = (const struct clk_hw*[]) { 1242 &cam_cc_camnoc_axi_clk_src.clkr.hw, 1243 }, 1244 .num_parents = 1, 1245 .flags = CLK_SET_RATE_PARENT, 1246 .ops = &clk_branch2_ops, 1247 }, 1248 }, 1249 }; 1250 1251 static struct clk_branch cam_cc_cci_0_clk = { 1252 .halt_reg = 0x2101c, 1253 .halt_check = BRANCH_HALT, 1254 .clkr = { 1255 .enable_reg = 0x2101c, 1256 .enable_mask = BIT(0), 1257 .hw.init = &(const struct clk_init_data) { 1258 .name = "cam_cc_cci_0_clk", 1259 .parent_hws = (const struct clk_hw*[]) { 1260 &cam_cc_cci_0_clk_src.clkr.hw, 1261 }, 1262 .num_parents = 1, 1263 .flags = CLK_SET_RATE_PARENT, 1264 .ops = &clk_branch2_ops, 1265 }, 1266 }, 1267 }; 1268 1269 static struct clk_branch cam_cc_cci_1_clk = { 1270 .halt_reg = 0x2201c, 1271 .halt_check = BRANCH_HALT, 1272 .clkr = { 1273 .enable_reg = 0x2201c, 1274 .enable_mask = BIT(0), 1275 .hw.init = &(const struct clk_init_data) { 1276 .name = "cam_cc_cci_1_clk", 1277 .parent_hws = (const struct clk_hw*[]) { 1278 &cam_cc_cci_1_clk_src.clkr.hw, 1279 }, 1280 .num_parents = 1, 1281 .flags = CLK_SET_RATE_PARENT, 1282 .ops = &clk_branch2_ops, 1283 }, 1284 }, 1285 }; 1286 1287 static struct clk_branch cam_cc_core_ahb_clk = { 1288 .halt_reg = 0x2501c, 1289 .halt_check = BRANCH_HALT_DELAY, 1290 .clkr = { 1291 .enable_reg = 0x2501c, 1292 .enable_mask = BIT(0), 1293 .hw.init = &(const struct clk_init_data) { 1294 .name = "cam_cc_core_ahb_clk", 1295 .parent_hws = (const struct clk_hw*[]) { 1296 &cam_cc_slow_ahb_clk_src.clkr.hw, 1297 }, 1298 .num_parents = 1, 1299 .flags = CLK_SET_RATE_PARENT, 1300 .ops = &clk_branch2_ops, 1301 }, 1302 }, 1303 }; 1304 1305 static struct clk_branch cam_cc_cpas_ahb_clk = { 1306 .halt_reg = 0x23004, 1307 .halt_check = BRANCH_HALT, 1308 .clkr = { 1309 .enable_reg = 0x23004, 1310 .enable_mask = BIT(0), 1311 .hw.init = &(const struct clk_init_data) { 1312 .name = "cam_cc_cpas_ahb_clk", 1313 .parent_hws = (const struct clk_hw*[]) { 1314 &cam_cc_slow_ahb_clk_src.clkr.hw, 1315 }, 1316 .num_parents = 1, 1317 .flags = CLK_SET_RATE_PARENT, 1318 .ops = &clk_branch2_ops, 1319 }, 1320 }, 1321 }; 1322 1323 static struct clk_branch cam_cc_cre_ahb_clk = { 1324 .halt_reg = 0x27020, 1325 .halt_check = BRANCH_HALT, 1326 .clkr = { 1327 .enable_reg = 0x27020, 1328 .enable_mask = BIT(0), 1329 .hw.init = &(const struct clk_init_data) { 1330 .name = "cam_cc_cre_ahb_clk", 1331 .parent_hws = (const struct clk_hw*[]) { 1332 &cam_cc_slow_ahb_clk_src.clkr.hw, 1333 }, 1334 .num_parents = 1, 1335 .flags = CLK_SET_RATE_PARENT, 1336 .ops = &clk_branch2_ops, 1337 }, 1338 }, 1339 }; 1340 1341 static struct clk_branch cam_cc_cre_clk = { 1342 .halt_reg = 0x2701c, 1343 .halt_check = BRANCH_HALT, 1344 .clkr = { 1345 .enable_reg = 0x2701c, 1346 .enable_mask = BIT(0), 1347 .hw.init = &(const struct clk_init_data) { 1348 .name = "cam_cc_cre_clk", 1349 .parent_hws = (const struct clk_hw*[]) { 1350 &cam_cc_cre_clk_src.clkr.hw, 1351 }, 1352 .num_parents = 1, 1353 .flags = CLK_SET_RATE_PARENT, 1354 .ops = &clk_branch2_ops, 1355 }, 1356 }, 1357 }; 1358 1359 static struct clk_branch cam_cc_csi0phytimer_clk = { 1360 .halt_reg = 0x1901c, 1361 .halt_check = BRANCH_HALT, 1362 .clkr = { 1363 .enable_reg = 0x1901c, 1364 .enable_mask = BIT(0), 1365 .hw.init = &(const struct clk_init_data) { 1366 .name = "cam_cc_csi0phytimer_clk", 1367 .parent_hws = (const struct clk_hw*[]) { 1368 &cam_cc_csi0phytimer_clk_src.clkr.hw, 1369 }, 1370 .num_parents = 1, 1371 .flags = CLK_SET_RATE_PARENT, 1372 .ops = &clk_branch2_ops, 1373 }, 1374 }, 1375 }; 1376 1377 static struct clk_branch cam_cc_csi1phytimer_clk = { 1378 .halt_reg = 0x19040, 1379 .halt_check = BRANCH_HALT, 1380 .clkr = { 1381 .enable_reg = 0x19040, 1382 .enable_mask = BIT(0), 1383 .hw.init = &(const struct clk_init_data) { 1384 .name = "cam_cc_csi1phytimer_clk", 1385 .parent_hws = (const struct clk_hw*[]) { 1386 &cam_cc_csi1phytimer_clk_src.clkr.hw, 1387 }, 1388 .num_parents = 1, 1389 .flags = CLK_SET_RATE_PARENT, 1390 .ops = &clk_branch2_ops, 1391 }, 1392 }, 1393 }; 1394 1395 static struct clk_branch cam_cc_csi2phytimer_clk = { 1396 .halt_reg = 0x19064, 1397 .halt_check = BRANCH_HALT, 1398 .clkr = { 1399 .enable_reg = 0x19064, 1400 .enable_mask = BIT(0), 1401 .hw.init = &(const struct clk_init_data) { 1402 .name = "cam_cc_csi2phytimer_clk", 1403 .parent_hws = (const struct clk_hw*[]) { 1404 &cam_cc_csi2phytimer_clk_src.clkr.hw, 1405 }, 1406 .num_parents = 1, 1407 .flags = CLK_SET_RATE_PARENT, 1408 .ops = &clk_branch2_ops, 1409 }, 1410 }, 1411 }; 1412 1413 static struct clk_branch cam_cc_csi3phytimer_clk = { 1414 .halt_reg = 0x19088, 1415 .halt_check = BRANCH_HALT, 1416 .clkr = { 1417 .enable_reg = 0x19088, 1418 .enable_mask = BIT(0), 1419 .hw.init = &(const struct clk_init_data) { 1420 .name = "cam_cc_csi3phytimer_clk", 1421 .parent_hws = (const struct clk_hw*[]) { 1422 &cam_cc_csi3phytimer_clk_src.clkr.hw, 1423 }, 1424 .num_parents = 1, 1425 .flags = CLK_SET_RATE_PARENT, 1426 .ops = &clk_branch2_ops, 1427 }, 1428 }, 1429 }; 1430 1431 static struct clk_branch cam_cc_csiphy0_clk = { 1432 .halt_reg = 0x19020, 1433 .halt_check = BRANCH_HALT, 1434 .clkr = { 1435 .enable_reg = 0x19020, 1436 .enable_mask = BIT(0), 1437 .hw.init = &(const struct clk_init_data) { 1438 .name = "cam_cc_csiphy0_clk", 1439 .parent_hws = (const struct clk_hw*[]) { 1440 &cam_cc_cphy_rx_clk_src.clkr.hw, 1441 }, 1442 .num_parents = 1, 1443 .flags = CLK_SET_RATE_PARENT, 1444 .ops = &clk_branch2_ops, 1445 }, 1446 }, 1447 }; 1448 1449 static struct clk_branch cam_cc_csiphy1_clk = { 1450 .halt_reg = 0x19044, 1451 .halt_check = BRANCH_HALT, 1452 .clkr = { 1453 .enable_reg = 0x19044, 1454 .enable_mask = BIT(0), 1455 .hw.init = &(const struct clk_init_data) { 1456 .name = "cam_cc_csiphy1_clk", 1457 .parent_hws = (const struct clk_hw*[]) { 1458 &cam_cc_cphy_rx_clk_src.clkr.hw, 1459 }, 1460 .num_parents = 1, 1461 .flags = CLK_SET_RATE_PARENT, 1462 .ops = &clk_branch2_ops, 1463 }, 1464 }, 1465 }; 1466 1467 static struct clk_branch cam_cc_csiphy2_clk = { 1468 .halt_reg = 0x19068, 1469 .halt_check = BRANCH_HALT, 1470 .clkr = { 1471 .enable_reg = 0x19068, 1472 .enable_mask = BIT(0), 1473 .hw.init = &(const struct clk_init_data) { 1474 .name = "cam_cc_csiphy2_clk", 1475 .parent_hws = (const struct clk_hw*[]) { 1476 &cam_cc_cphy_rx_clk_src.clkr.hw, 1477 }, 1478 .num_parents = 1, 1479 .flags = CLK_SET_RATE_PARENT, 1480 .ops = &clk_branch2_ops, 1481 }, 1482 }, 1483 }; 1484 1485 static struct clk_branch cam_cc_csiphy3_clk = { 1486 .halt_reg = 0x1908c, 1487 .halt_check = BRANCH_HALT, 1488 .clkr = { 1489 .enable_reg = 0x1908c, 1490 .enable_mask = BIT(0), 1491 .hw.init = &(const struct clk_init_data) { 1492 .name = "cam_cc_csiphy3_clk", 1493 .parent_hws = (const struct clk_hw*[]) { 1494 &cam_cc_cphy_rx_clk_src.clkr.hw, 1495 }, 1496 .num_parents = 1, 1497 .flags = CLK_SET_RATE_PARENT, 1498 .ops = &clk_branch2_ops, 1499 }, 1500 }, 1501 }; 1502 1503 static struct clk_branch cam_cc_icp_atb_clk = { 1504 .halt_reg = 0x20004, 1505 .halt_check = BRANCH_HALT, 1506 .clkr = { 1507 .enable_reg = 0x20004, 1508 .enable_mask = BIT(0), 1509 .hw.init = &(const struct clk_init_data) { 1510 .name = "cam_cc_icp_atb_clk", 1511 .ops = &clk_branch2_ops, 1512 }, 1513 }, 1514 }; 1515 1516 static struct clk_branch cam_cc_icp_clk = { 1517 .halt_reg = 0x2002c, 1518 .halt_check = BRANCH_HALT, 1519 .clkr = { 1520 .enable_reg = 0x2002c, 1521 .enable_mask = BIT(0), 1522 .hw.init = &(const struct clk_init_data) { 1523 .name = "cam_cc_icp_clk", 1524 .parent_hws = (const struct clk_hw*[]) { 1525 &cam_cc_icp_clk_src.clkr.hw, 1526 }, 1527 .num_parents = 1, 1528 .flags = CLK_SET_RATE_PARENT, 1529 .ops = &clk_branch2_ops, 1530 }, 1531 }, 1532 }; 1533 1534 static struct clk_branch cam_cc_icp_cti_clk = { 1535 .halt_reg = 0x20008, 1536 .halt_check = BRANCH_HALT, 1537 .clkr = { 1538 .enable_reg = 0x20008, 1539 .enable_mask = BIT(0), 1540 .hw.init = &(const struct clk_init_data) { 1541 .name = "cam_cc_icp_cti_clk", 1542 .ops = &clk_branch2_ops, 1543 }, 1544 }, 1545 }; 1546 1547 static struct clk_branch cam_cc_icp_ts_clk = { 1548 .halt_reg = 0x2000c, 1549 .halt_check = BRANCH_HALT, 1550 .clkr = { 1551 .enable_reg = 0x2000c, 1552 .enable_mask = BIT(0), 1553 .hw.init = &(const struct clk_init_data) { 1554 .name = "cam_cc_icp_ts_clk", 1555 .ops = &clk_branch2_ops, 1556 }, 1557 }, 1558 }; 1559 1560 static struct clk_branch cam_cc_mclk0_clk = { 1561 .halt_reg = 0x1801c, 1562 .halt_check = BRANCH_HALT, 1563 .clkr = { 1564 .enable_reg = 0x1801c, 1565 .enable_mask = BIT(0), 1566 .hw.init = &(const struct clk_init_data) { 1567 .name = "cam_cc_mclk0_clk", 1568 .parent_hws = (const struct clk_hw*[]) { 1569 &cam_cc_mclk0_clk_src.clkr.hw, 1570 }, 1571 .num_parents = 1, 1572 .flags = CLK_SET_RATE_PARENT, 1573 .ops = &clk_branch2_ops, 1574 }, 1575 }, 1576 }; 1577 1578 static struct clk_branch cam_cc_mclk1_clk = { 1579 .halt_reg = 0x1803c, 1580 .halt_check = BRANCH_HALT, 1581 .clkr = { 1582 .enable_reg = 0x1803c, 1583 .enable_mask = BIT(0), 1584 .hw.init = &(const struct clk_init_data) { 1585 .name = "cam_cc_mclk1_clk", 1586 .parent_hws = (const struct clk_hw*[]) { 1587 &cam_cc_mclk1_clk_src.clkr.hw, 1588 }, 1589 .num_parents = 1, 1590 .flags = CLK_SET_RATE_PARENT, 1591 .ops = &clk_branch2_ops, 1592 }, 1593 }, 1594 }; 1595 1596 static struct clk_branch cam_cc_mclk2_clk = { 1597 .halt_reg = 0x1805c, 1598 .halt_check = BRANCH_HALT, 1599 .clkr = { 1600 .enable_reg = 0x1805c, 1601 .enable_mask = BIT(0), 1602 .hw.init = &(const struct clk_init_data) { 1603 .name = "cam_cc_mclk2_clk", 1604 .parent_hws = (const struct clk_hw*[]) { 1605 &cam_cc_mclk2_clk_src.clkr.hw, 1606 }, 1607 .num_parents = 1, 1608 .flags = CLK_SET_RATE_PARENT, 1609 .ops = &clk_branch2_ops, 1610 }, 1611 }, 1612 }; 1613 1614 static struct clk_branch cam_cc_mclk3_clk = { 1615 .halt_reg = 0x1807c, 1616 .halt_check = BRANCH_HALT, 1617 .clkr = { 1618 .enable_reg = 0x1807c, 1619 .enable_mask = BIT(0), 1620 .hw.init = &(const struct clk_init_data) { 1621 .name = "cam_cc_mclk3_clk", 1622 .parent_hws = (const struct clk_hw*[]) { 1623 &cam_cc_mclk3_clk_src.clkr.hw, 1624 }, 1625 .num_parents = 1, 1626 .flags = CLK_SET_RATE_PARENT, 1627 .ops = &clk_branch2_ops, 1628 }, 1629 }, 1630 }; 1631 1632 static struct clk_branch cam_cc_mclk4_clk = { 1633 .halt_reg = 0x1809c, 1634 .halt_check = BRANCH_HALT, 1635 .clkr = { 1636 .enable_reg = 0x1809c, 1637 .enable_mask = BIT(0), 1638 .hw.init = &(const struct clk_init_data) { 1639 .name = "cam_cc_mclk4_clk", 1640 .parent_hws = (const struct clk_hw*[]) { 1641 &cam_cc_mclk4_clk_src.clkr.hw, 1642 }, 1643 .num_parents = 1, 1644 .flags = CLK_SET_RATE_PARENT, 1645 .ops = &clk_branch2_ops, 1646 }, 1647 }, 1648 }; 1649 1650 static struct clk_branch cam_cc_ope_0_ahb_clk = { 1651 .halt_reg = 0x1b034, 1652 .halt_check = BRANCH_HALT, 1653 .clkr = { 1654 .enable_reg = 0x1b034, 1655 .enable_mask = BIT(0), 1656 .hw.init = &(const struct clk_init_data) { 1657 .name = "cam_cc_ope_0_ahb_clk", 1658 .parent_hws = (const struct clk_hw*[]) { 1659 &cam_cc_slow_ahb_clk_src.clkr.hw, 1660 }, 1661 .num_parents = 1, 1662 .flags = CLK_SET_RATE_PARENT, 1663 .ops = &clk_branch2_ops, 1664 }, 1665 }, 1666 }; 1667 1668 static struct clk_branch cam_cc_ope_0_areg_clk = { 1669 .halt_reg = 0x1b030, 1670 .halt_check = BRANCH_HALT, 1671 .clkr = { 1672 .enable_reg = 0x1b030, 1673 .enable_mask = BIT(0), 1674 .hw.init = &(const struct clk_init_data) { 1675 .name = "cam_cc_ope_0_areg_clk", 1676 .parent_hws = (const struct clk_hw*[]) { 1677 &cam_cc_fast_ahb_clk_src.clkr.hw, 1678 }, 1679 .num_parents = 1, 1680 .flags = CLK_SET_RATE_PARENT, 1681 .ops = &clk_branch2_ops, 1682 }, 1683 }, 1684 }; 1685 1686 static struct clk_branch cam_cc_ope_0_clk = { 1687 .halt_reg = 0x1b01c, 1688 .halt_check = BRANCH_HALT, 1689 .clkr = { 1690 .enable_reg = 0x1b01c, 1691 .enable_mask = BIT(0), 1692 .hw.init = &(const struct clk_init_data) { 1693 .name = "cam_cc_ope_0_clk", 1694 .parent_hws = (const struct clk_hw*[]) { 1695 &cam_cc_ope_0_clk_src.clkr.hw, 1696 }, 1697 .num_parents = 1, 1698 .flags = CLK_SET_RATE_PARENT, 1699 .ops = &clk_branch2_ops, 1700 }, 1701 }, 1702 }; 1703 1704 static struct clk_branch cam_cc_soc_ahb_clk = { 1705 .halt_reg = 0x25018, 1706 .halt_check = BRANCH_HALT, 1707 .clkr = { 1708 .enable_reg = 0x25018, 1709 .enable_mask = BIT(0), 1710 .hw.init = &(const struct clk_init_data) { 1711 .name = "cam_cc_soc_ahb_clk", 1712 .ops = &clk_branch2_ops, 1713 }, 1714 }, 1715 }; 1716 1717 static struct clk_branch cam_cc_sys_tmr_clk = { 1718 .halt_reg = 0x20038, 1719 .halt_check = BRANCH_HALT, 1720 .clkr = { 1721 .enable_reg = 0x20038, 1722 .enable_mask = BIT(0), 1723 .hw.init = &(const struct clk_init_data) { 1724 .name = "cam_cc_sys_tmr_clk", 1725 .parent_hws = (const struct clk_hw*[]) { 1726 &cam_cc_xo_clk_src.clkr.hw, 1727 }, 1728 .num_parents = 1, 1729 .flags = CLK_SET_RATE_PARENT, 1730 .ops = &clk_branch2_ops, 1731 }, 1732 }, 1733 }; 1734 1735 static struct clk_branch cam_cc_tfe_0_ahb_clk = { 1736 .halt_reg = 0x1c078, 1737 .halt_check = BRANCH_HALT, 1738 .clkr = { 1739 .enable_reg = 0x1c078, 1740 .enable_mask = BIT(0), 1741 .hw.init = &(const struct clk_init_data) { 1742 .name = "cam_cc_tfe_0_ahb_clk", 1743 .parent_hws = (const struct clk_hw*[]) { 1744 &cam_cc_slow_ahb_clk_src.clkr.hw, 1745 }, 1746 .num_parents = 1, 1747 .flags = CLK_SET_RATE_PARENT, 1748 .ops = &clk_branch2_ops, 1749 }, 1750 }, 1751 }; 1752 1753 static struct clk_branch cam_cc_tfe_0_clk = { 1754 .halt_reg = 0x1c01c, 1755 .halt_check = BRANCH_HALT, 1756 .clkr = { 1757 .enable_reg = 0x1c01c, 1758 .enable_mask = BIT(0), 1759 .hw.init = &(const struct clk_init_data) { 1760 .name = "cam_cc_tfe_0_clk", 1761 .parent_hws = (const struct clk_hw*[]) { 1762 &cam_cc_tfe_0_clk_src.clkr.hw, 1763 }, 1764 .num_parents = 1, 1765 .flags = CLK_SET_RATE_PARENT, 1766 .ops = &clk_branch2_ops, 1767 }, 1768 }, 1769 }; 1770 1771 static struct clk_branch cam_cc_tfe_0_cphy_rx_clk = { 1772 .halt_reg = 0x1c074, 1773 .halt_check = BRANCH_HALT, 1774 .clkr = { 1775 .enable_reg = 0x1c074, 1776 .enable_mask = BIT(0), 1777 .hw.init = &(const struct clk_init_data) { 1778 .name = "cam_cc_tfe_0_cphy_rx_clk", 1779 .parent_hws = (const struct clk_hw*[]) { 1780 &cam_cc_cphy_rx_clk_src.clkr.hw, 1781 }, 1782 .num_parents = 1, 1783 .flags = CLK_SET_RATE_PARENT, 1784 .ops = &clk_branch2_ops, 1785 }, 1786 }, 1787 }; 1788 1789 static struct clk_branch cam_cc_tfe_0_csid_clk = { 1790 .halt_reg = 0x1c048, 1791 .halt_check = BRANCH_HALT, 1792 .clkr = { 1793 .enable_reg = 0x1c048, 1794 .enable_mask = BIT(0), 1795 .hw.init = &(const struct clk_init_data) { 1796 .name = "cam_cc_tfe_0_csid_clk", 1797 .parent_hws = (const struct clk_hw*[]) { 1798 &cam_cc_tfe_0_csid_clk_src.clkr.hw, 1799 }, 1800 .num_parents = 1, 1801 .flags = CLK_SET_RATE_PARENT, 1802 .ops = &clk_branch2_ops, 1803 }, 1804 }, 1805 }; 1806 1807 static struct clk_branch cam_cc_tfe_1_ahb_clk = { 1808 .halt_reg = 0x1d058, 1809 .halt_check = BRANCH_HALT, 1810 .clkr = { 1811 .enable_reg = 0x1d058, 1812 .enable_mask = BIT(0), 1813 .hw.init = &(const struct clk_init_data) { 1814 .name = "cam_cc_tfe_1_ahb_clk", 1815 .parent_hws = (const struct clk_hw*[]) { 1816 &cam_cc_slow_ahb_clk_src.clkr.hw, 1817 }, 1818 .num_parents = 1, 1819 .flags = CLK_SET_RATE_PARENT, 1820 .ops = &clk_branch2_ops, 1821 }, 1822 }, 1823 }; 1824 1825 static struct clk_branch cam_cc_tfe_1_clk = { 1826 .halt_reg = 0x1d01c, 1827 .halt_check = BRANCH_HALT, 1828 .clkr = { 1829 .enable_reg = 0x1d01c, 1830 .enable_mask = BIT(0), 1831 .hw.init = &(const struct clk_init_data) { 1832 .name = "cam_cc_tfe_1_clk", 1833 .parent_hws = (const struct clk_hw*[]) { 1834 &cam_cc_tfe_1_clk_src.clkr.hw, 1835 }, 1836 .num_parents = 1, 1837 .flags = CLK_SET_RATE_PARENT, 1838 .ops = &clk_branch2_ops, 1839 }, 1840 }, 1841 }; 1842 1843 static struct clk_branch cam_cc_tfe_1_cphy_rx_clk = { 1844 .halt_reg = 0x1d054, 1845 .halt_check = BRANCH_HALT, 1846 .clkr = { 1847 .enable_reg = 0x1d054, 1848 .enable_mask = BIT(0), 1849 .hw.init = &(const struct clk_init_data) { 1850 .name = "cam_cc_tfe_1_cphy_rx_clk", 1851 .parent_hws = (const struct clk_hw*[]) { 1852 &cam_cc_cphy_rx_clk_src.clkr.hw, 1853 }, 1854 .num_parents = 1, 1855 .flags = CLK_SET_RATE_PARENT, 1856 .ops = &clk_branch2_ops, 1857 }, 1858 }, 1859 }; 1860 1861 static struct clk_branch cam_cc_tfe_1_csid_clk = { 1862 .halt_reg = 0x1d048, 1863 .halt_check = BRANCH_HALT, 1864 .clkr = { 1865 .enable_reg = 0x1d048, 1866 .enable_mask = BIT(0), 1867 .hw.init = &(const struct clk_init_data) { 1868 .name = "cam_cc_tfe_1_csid_clk", 1869 .parent_hws = (const struct clk_hw*[]) { 1870 &cam_cc_tfe_1_csid_clk_src.clkr.hw, 1871 }, 1872 .num_parents = 1, 1873 .flags = CLK_SET_RATE_PARENT, 1874 .ops = &clk_branch2_ops, 1875 }, 1876 }, 1877 }; 1878 1879 static struct clk_branch cam_cc_tfe_2_ahb_clk = { 1880 .halt_reg = 0x1e058, 1881 .halt_check = BRANCH_HALT, 1882 .clkr = { 1883 .enable_reg = 0x1e058, 1884 .enable_mask = BIT(0), 1885 .hw.init = &(const struct clk_init_data) { 1886 .name = "cam_cc_tfe_2_ahb_clk", 1887 .parent_hws = (const struct clk_hw*[]) { 1888 &cam_cc_slow_ahb_clk_src.clkr.hw, 1889 }, 1890 .num_parents = 1, 1891 .flags = CLK_SET_RATE_PARENT, 1892 .ops = &clk_branch2_ops, 1893 }, 1894 }, 1895 }; 1896 1897 static struct clk_branch cam_cc_tfe_2_clk = { 1898 .halt_reg = 0x1e01c, 1899 .halt_check = BRANCH_HALT, 1900 .clkr = { 1901 .enable_reg = 0x1e01c, 1902 .enable_mask = BIT(0), 1903 .hw.init = &(const struct clk_init_data) { 1904 .name = "cam_cc_tfe_2_clk", 1905 .parent_hws = (const struct clk_hw*[]) { 1906 &cam_cc_tfe_2_clk_src.clkr.hw, 1907 }, 1908 .num_parents = 1, 1909 .flags = CLK_SET_RATE_PARENT, 1910 .ops = &clk_branch2_ops, 1911 }, 1912 }, 1913 }; 1914 1915 static struct clk_branch cam_cc_tfe_2_cphy_rx_clk = { 1916 .halt_reg = 0x1e054, 1917 .halt_check = BRANCH_HALT, 1918 .clkr = { 1919 .enable_reg = 0x1e054, 1920 .enable_mask = BIT(0), 1921 .hw.init = &(const struct clk_init_data) { 1922 .name = "cam_cc_tfe_2_cphy_rx_clk", 1923 .parent_hws = (const struct clk_hw*[]) { 1924 &cam_cc_cphy_rx_clk_src.clkr.hw, 1925 }, 1926 .num_parents = 1, 1927 .flags = CLK_SET_RATE_PARENT, 1928 .ops = &clk_branch2_ops, 1929 }, 1930 }, 1931 }; 1932 1933 static struct clk_branch cam_cc_tfe_2_csid_clk = { 1934 .halt_reg = 0x1e048, 1935 .halt_check = BRANCH_HALT, 1936 .clkr = { 1937 .enable_reg = 0x1e048, 1938 .enable_mask = BIT(0), 1939 .hw.init = &(const struct clk_init_data) { 1940 .name = "cam_cc_tfe_2_csid_clk", 1941 .parent_hws = (const struct clk_hw*[]) { 1942 &cam_cc_tfe_2_csid_clk_src.clkr.hw, 1943 }, 1944 .num_parents = 1, 1945 .flags = CLK_SET_RATE_PARENT, 1946 .ops = &clk_branch2_ops, 1947 }, 1948 }, 1949 }; 1950 1951 static struct clk_branch cam_cc_top_shift_clk = { 1952 .halt_reg = 0x25040, 1953 .halt_check = BRANCH_HALT_VOTED, 1954 .clkr = { 1955 .enable_reg = 0x25040, 1956 .enable_mask = BIT(0), 1957 .hw.init = &(const struct clk_init_data) { 1958 .name = "cam_cc_top_shift_clk", 1959 .parent_hws = (const struct clk_hw*[]) { 1960 &cam_cc_xo_clk_src.clkr.hw, 1961 }, 1962 .num_parents = 1, 1963 .flags = CLK_SET_RATE_PARENT, 1964 .ops = &clk_branch2_ops, 1965 }, 1966 }, 1967 }; 1968 1969 static struct gdsc cam_cc_camss_top_gdsc = { 1970 .gdscr = 0x25004, 1971 .en_rest_wait_val = 0x2, 1972 .en_few_wait_val = 0x2, 1973 .clk_dis_wait_val = 0xf, 1974 .pd = { 1975 .name = "cam_cc_camss_top_gdsc", 1976 }, 1977 .pwrsts = PWRSTS_OFF_ON, 1978 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 1979 .needs_icc = true, 1980 .icc_path_index = DT_ICC_TOP_GDSC, 1981 }; 1982 1983 static struct clk_regmap *cam_cc_milos_clocks[] = { 1984 [CAM_CC_BPS_AHB_CLK] = &cam_cc_bps_ahb_clk.clkr, 1985 [CAM_CC_BPS_AREG_CLK] = &cam_cc_bps_areg_clk.clkr, 1986 [CAM_CC_BPS_CLK] = &cam_cc_bps_clk.clkr, 1987 [CAM_CC_BPS_CLK_SRC] = &cam_cc_bps_clk_src.clkr, 1988 [CAM_CC_CAMNOC_ATB_CLK] = &cam_cc_camnoc_atb_clk.clkr, 1989 [CAM_CC_CAMNOC_AXI_CLK_SRC] = &cam_cc_camnoc_axi_clk_src.clkr, 1990 [CAM_CC_CAMNOC_AXI_HF_CLK] = &cam_cc_camnoc_axi_hf_clk.clkr, 1991 [CAM_CC_CAMNOC_AXI_SF_CLK] = &cam_cc_camnoc_axi_sf_clk.clkr, 1992 [CAM_CC_CAMNOC_NRT_AXI_CLK] = &cam_cc_camnoc_nrt_axi_clk.clkr, 1993 [CAM_CC_CAMNOC_RT_AXI_CLK] = &cam_cc_camnoc_rt_axi_clk.clkr, 1994 [CAM_CC_CCI_0_CLK] = &cam_cc_cci_0_clk.clkr, 1995 [CAM_CC_CCI_0_CLK_SRC] = &cam_cc_cci_0_clk_src.clkr, 1996 [CAM_CC_CCI_1_CLK] = &cam_cc_cci_1_clk.clkr, 1997 [CAM_CC_CCI_1_CLK_SRC] = &cam_cc_cci_1_clk_src.clkr, 1998 [CAM_CC_CORE_AHB_CLK] = &cam_cc_core_ahb_clk.clkr, 1999 [CAM_CC_CPAS_AHB_CLK] = &cam_cc_cpas_ahb_clk.clkr, 2000 [CAM_CC_CPHY_RX_CLK_SRC] = &cam_cc_cphy_rx_clk_src.clkr, 2001 [CAM_CC_CRE_AHB_CLK] = &cam_cc_cre_ahb_clk.clkr, 2002 [CAM_CC_CRE_CLK] = &cam_cc_cre_clk.clkr, 2003 [CAM_CC_CRE_CLK_SRC] = &cam_cc_cre_clk_src.clkr, 2004 [CAM_CC_CSI0PHYTIMER_CLK] = &cam_cc_csi0phytimer_clk.clkr, 2005 [CAM_CC_CSI0PHYTIMER_CLK_SRC] = &cam_cc_csi0phytimer_clk_src.clkr, 2006 [CAM_CC_CSI1PHYTIMER_CLK] = &cam_cc_csi1phytimer_clk.clkr, 2007 [CAM_CC_CSI1PHYTIMER_CLK_SRC] = &cam_cc_csi1phytimer_clk_src.clkr, 2008 [CAM_CC_CSI2PHYTIMER_CLK] = &cam_cc_csi2phytimer_clk.clkr, 2009 [CAM_CC_CSI2PHYTIMER_CLK_SRC] = &cam_cc_csi2phytimer_clk_src.clkr, 2010 [CAM_CC_CSI3PHYTIMER_CLK] = &cam_cc_csi3phytimer_clk.clkr, 2011 [CAM_CC_CSI3PHYTIMER_CLK_SRC] = &cam_cc_csi3phytimer_clk_src.clkr, 2012 [CAM_CC_CSIPHY0_CLK] = &cam_cc_csiphy0_clk.clkr, 2013 [CAM_CC_CSIPHY1_CLK] = &cam_cc_csiphy1_clk.clkr, 2014 [CAM_CC_CSIPHY2_CLK] = &cam_cc_csiphy2_clk.clkr, 2015 [CAM_CC_CSIPHY3_CLK] = &cam_cc_csiphy3_clk.clkr, 2016 [CAM_CC_FAST_AHB_CLK_SRC] = &cam_cc_fast_ahb_clk_src.clkr, 2017 [CAM_CC_ICP_ATB_CLK] = &cam_cc_icp_atb_clk.clkr, 2018 [CAM_CC_ICP_CLK] = &cam_cc_icp_clk.clkr, 2019 [CAM_CC_ICP_CLK_SRC] = &cam_cc_icp_clk_src.clkr, 2020 [CAM_CC_ICP_CTI_CLK] = &cam_cc_icp_cti_clk.clkr, 2021 [CAM_CC_ICP_TS_CLK] = &cam_cc_icp_ts_clk.clkr, 2022 [CAM_CC_MCLK0_CLK] = &cam_cc_mclk0_clk.clkr, 2023 [CAM_CC_MCLK0_CLK_SRC] = &cam_cc_mclk0_clk_src.clkr, 2024 [CAM_CC_MCLK1_CLK] = &cam_cc_mclk1_clk.clkr, 2025 [CAM_CC_MCLK1_CLK_SRC] = &cam_cc_mclk1_clk_src.clkr, 2026 [CAM_CC_MCLK2_CLK] = &cam_cc_mclk2_clk.clkr, 2027 [CAM_CC_MCLK2_CLK_SRC] = &cam_cc_mclk2_clk_src.clkr, 2028 [CAM_CC_MCLK3_CLK] = &cam_cc_mclk3_clk.clkr, 2029 [CAM_CC_MCLK3_CLK_SRC] = &cam_cc_mclk3_clk_src.clkr, 2030 [CAM_CC_MCLK4_CLK] = &cam_cc_mclk4_clk.clkr, 2031 [CAM_CC_MCLK4_CLK_SRC] = &cam_cc_mclk4_clk_src.clkr, 2032 [CAM_CC_OPE_0_AHB_CLK] = &cam_cc_ope_0_ahb_clk.clkr, 2033 [CAM_CC_OPE_0_AREG_CLK] = &cam_cc_ope_0_areg_clk.clkr, 2034 [CAM_CC_OPE_0_CLK] = &cam_cc_ope_0_clk.clkr, 2035 [CAM_CC_OPE_0_CLK_SRC] = &cam_cc_ope_0_clk_src.clkr, 2036 [CAM_CC_PLL0] = &cam_cc_pll0.clkr, 2037 [CAM_CC_PLL0_OUT_EVEN] = &cam_cc_pll0_out_even.clkr, 2038 [CAM_CC_PLL0_OUT_ODD] = &cam_cc_pll0_out_odd.clkr, 2039 [CAM_CC_PLL1] = &cam_cc_pll1.clkr, 2040 [CAM_CC_PLL1_OUT_EVEN] = &cam_cc_pll1_out_even.clkr, 2041 [CAM_CC_PLL2] = &cam_cc_pll2.clkr, 2042 [CAM_CC_PLL3] = &cam_cc_pll3.clkr, 2043 [CAM_CC_PLL3_OUT_EVEN] = &cam_cc_pll3_out_even.clkr, 2044 [CAM_CC_PLL4] = &cam_cc_pll4.clkr, 2045 [CAM_CC_PLL4_OUT_EVEN] = &cam_cc_pll4_out_even.clkr, 2046 [CAM_CC_PLL5] = &cam_cc_pll5.clkr, 2047 [CAM_CC_PLL5_OUT_EVEN] = &cam_cc_pll5_out_even.clkr, 2048 [CAM_CC_PLL6] = &cam_cc_pll6.clkr, 2049 [CAM_CC_PLL6_OUT_EVEN] = &cam_cc_pll6_out_even.clkr, 2050 [CAM_CC_SLEEP_CLK_SRC] = &cam_cc_sleep_clk_src.clkr, 2051 [CAM_CC_SLOW_AHB_CLK_SRC] = &cam_cc_slow_ahb_clk_src.clkr, 2052 [CAM_CC_SOC_AHB_CLK] = &cam_cc_soc_ahb_clk.clkr, 2053 [CAM_CC_SYS_TMR_CLK] = &cam_cc_sys_tmr_clk.clkr, 2054 [CAM_CC_TFE_0_AHB_CLK] = &cam_cc_tfe_0_ahb_clk.clkr, 2055 [CAM_CC_TFE_0_CLK] = &cam_cc_tfe_0_clk.clkr, 2056 [CAM_CC_TFE_0_CLK_SRC] = &cam_cc_tfe_0_clk_src.clkr, 2057 [CAM_CC_TFE_0_CPHY_RX_CLK] = &cam_cc_tfe_0_cphy_rx_clk.clkr, 2058 [CAM_CC_TFE_0_CSID_CLK] = &cam_cc_tfe_0_csid_clk.clkr, 2059 [CAM_CC_TFE_0_CSID_CLK_SRC] = &cam_cc_tfe_0_csid_clk_src.clkr, 2060 [CAM_CC_TFE_1_AHB_CLK] = &cam_cc_tfe_1_ahb_clk.clkr, 2061 [CAM_CC_TFE_1_CLK] = &cam_cc_tfe_1_clk.clkr, 2062 [CAM_CC_TFE_1_CLK_SRC] = &cam_cc_tfe_1_clk_src.clkr, 2063 [CAM_CC_TFE_1_CPHY_RX_CLK] = &cam_cc_tfe_1_cphy_rx_clk.clkr, 2064 [CAM_CC_TFE_1_CSID_CLK] = &cam_cc_tfe_1_csid_clk.clkr, 2065 [CAM_CC_TFE_1_CSID_CLK_SRC] = &cam_cc_tfe_1_csid_clk_src.clkr, 2066 [CAM_CC_TFE_2_AHB_CLK] = &cam_cc_tfe_2_ahb_clk.clkr, 2067 [CAM_CC_TFE_2_CLK] = &cam_cc_tfe_2_clk.clkr, 2068 [CAM_CC_TFE_2_CLK_SRC] = &cam_cc_tfe_2_clk_src.clkr, 2069 [CAM_CC_TFE_2_CPHY_RX_CLK] = &cam_cc_tfe_2_cphy_rx_clk.clkr, 2070 [CAM_CC_TFE_2_CSID_CLK] = &cam_cc_tfe_2_csid_clk.clkr, 2071 [CAM_CC_TFE_2_CSID_CLK_SRC] = &cam_cc_tfe_2_csid_clk_src.clkr, 2072 [CAM_CC_TOP_SHIFT_CLK] = &cam_cc_top_shift_clk.clkr, 2073 [CAM_CC_XO_CLK_SRC] = &cam_cc_xo_clk_src.clkr, 2074 }; 2075 2076 static const struct qcom_reset_map cam_cc_milos_resets[] = { 2077 [CAM_CC_BPS_BCR] = { 0x1a000 }, 2078 [CAM_CC_CAMNOC_BCR] = { 0x24000 }, 2079 [CAM_CC_CAMSS_TOP_BCR] = { 0x25000 }, 2080 [CAM_CC_CCI_0_BCR] = { 0x21000 }, 2081 [CAM_CC_CCI_1_BCR] = { 0x22000 }, 2082 [CAM_CC_CPAS_BCR] = { 0x23000 }, 2083 [CAM_CC_CRE_BCR] = { 0x27000 }, 2084 [CAM_CC_CSI0PHY_BCR] = { 0x19000 }, 2085 [CAM_CC_CSI1PHY_BCR] = { 0x19024 }, 2086 [CAM_CC_CSI2PHY_BCR] = { 0x19048 }, 2087 [CAM_CC_CSI3PHY_BCR] = { 0x1906c }, 2088 [CAM_CC_ICP_BCR] = { 0x20000 }, 2089 [CAM_CC_MCLK0_BCR] = { 0x18000 }, 2090 [CAM_CC_MCLK1_BCR] = { 0x18020 }, 2091 [CAM_CC_MCLK2_BCR] = { 0x18040 }, 2092 [CAM_CC_MCLK3_BCR] = { 0x18060 }, 2093 [CAM_CC_MCLK4_BCR] = { 0x18080 }, 2094 [CAM_CC_OPE_0_BCR] = { 0x1b000 }, 2095 [CAM_CC_TFE_0_BCR] = { 0x1c000 }, 2096 [CAM_CC_TFE_1_BCR] = { 0x1d000 }, 2097 [CAM_CC_TFE_2_BCR] = { 0x1e000 }, 2098 }; 2099 2100 static struct gdsc *cam_cc_milos_gdscs[] = { 2101 [CAM_CC_CAMSS_TOP_GDSC] = &cam_cc_camss_top_gdsc, 2102 }; 2103 2104 static struct clk_alpha_pll *cam_cc_milos_plls[] = { 2105 &cam_cc_pll0, 2106 &cam_cc_pll1, 2107 &cam_cc_pll2, 2108 &cam_cc_pll3, 2109 &cam_cc_pll4, 2110 &cam_cc_pll5, 2111 &cam_cc_pll6, 2112 }; 2113 2114 static const u32 cam_cc_milos_critical_cbcrs[] = { 2115 0x25038, /* CAM_CC_GDSC_CLK */ 2116 0x2505c, /* CAM_CC_SLEEP_CLK */ 2117 }; 2118 2119 static const struct regmap_config cam_cc_milos_regmap_config = { 2120 .reg_bits = 32, 2121 .reg_stride = 4, 2122 .val_bits = 32, 2123 .max_register = 0x30728, 2124 .fast_io = true, 2125 }; 2126 2127 static const struct qcom_cc_driver_data cam_cc_milos_driver_data = { 2128 .alpha_plls = cam_cc_milos_plls, 2129 .num_alpha_plls = ARRAY_SIZE(cam_cc_milos_plls), 2130 .clk_cbcrs = cam_cc_milos_critical_cbcrs, 2131 .num_clk_cbcrs = ARRAY_SIZE(cam_cc_milos_critical_cbcrs), 2132 }; 2133 2134 static const struct qcom_cc_desc cam_cc_milos_desc = { 2135 .config = &cam_cc_milos_regmap_config, 2136 .clks = cam_cc_milos_clocks, 2137 .num_clks = ARRAY_SIZE(cam_cc_milos_clocks), 2138 .resets = cam_cc_milos_resets, 2139 .num_resets = ARRAY_SIZE(cam_cc_milos_resets), 2140 .gdscs = cam_cc_milos_gdscs, 2141 .num_gdscs = ARRAY_SIZE(cam_cc_milos_gdscs), 2142 .use_rpm = true, 2143 .driver_data = &cam_cc_milos_driver_data, 2144 }; 2145 2146 static const struct of_device_id cam_cc_milos_match_table[] = { 2147 { .compatible = "qcom,milos-camcc" }, 2148 { } 2149 }; 2150 MODULE_DEVICE_TABLE(of, cam_cc_milos_match_table); 2151 2152 static int cam_cc_milos_probe(struct platform_device *pdev) 2153 { 2154 return qcom_cc_probe(pdev, &cam_cc_milos_desc); 2155 } 2156 2157 static struct platform_driver cam_cc_milos_driver = { 2158 .probe = cam_cc_milos_probe, 2159 .driver = { 2160 .name = "cam_cc-milos", 2161 .of_match_table = cam_cc_milos_match_table, 2162 }, 2163 }; 2164 2165 module_platform_driver(cam_cc_milos_driver); 2166 2167 MODULE_DESCRIPTION("QTI CAM_CC Milos Driver"); 2168 MODULE_LICENSE("GPL"); 2169