1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 4 */ 5 6 #include <linux/clk-provider.h> 7 #include <linux/mod_devicetable.h> 8 #include <linux/module.h> 9 #include <linux/platform_device.h> 10 #include <linux/regmap.h> 11 12 #include <dt-bindings/clock/qcom,kaanapali-camcc.h> 13 14 #include "clk-alpha-pll.h" 15 #include "clk-branch.h" 16 #include "clk-pll.h" 17 #include "clk-rcg.h" 18 #include "clk-regmap.h" 19 #include "clk-regmap-divider.h" 20 #include "clk-regmap-mux.h" 21 #include "common.h" 22 #include "gdsc.h" 23 #include "reset.h" 24 25 enum { 26 DT_AHB_CLK, 27 DT_BI_TCXO, 28 DT_BI_TCXO_AO, 29 DT_SLEEP_CLK, 30 }; 31 32 enum { 33 P_BI_TCXO, 34 P_CAM_CC_PLL0_OUT_EVEN, 35 P_CAM_CC_PLL0_OUT_MAIN, 36 P_CAM_CC_PLL0_OUT_ODD, 37 P_CAM_CC_PLL1_OUT_EVEN, 38 P_CAM_CC_PLL2_OUT_EVEN, 39 P_CAM_CC_PLL3_OUT_EVEN, 40 P_CAM_CC_PLL4_OUT_EVEN, 41 P_CAM_CC_PLL5_OUT_EVEN, 42 P_CAM_CC_PLL6_OUT_EVEN, 43 P_CAM_CC_PLL6_OUT_ODD, 44 P_CAM_CC_PLL7_OUT_EVEN, 45 }; 46 47 static const struct pll_vco taycan_eko_t_vco[] = { 48 { 249600000, 2500000000, 0 }, 49 }; 50 51 /* 1200.0 MHz Configuration */ 52 static const struct alpha_pll_config cam_cc_pll0_config = { 53 .l = 0x3e, 54 .cal_l = 0x48, 55 .alpha = 0x8000, 56 .config_ctl_val = 0x25c400e7, 57 .config_ctl_hi_val = 0x0a8062e0, 58 .config_ctl_hi1_val = 0xf51dea20, 59 .user_ctl_val = 0x00008408, 60 .user_ctl_hi_val = 0x00000002, 61 }; 62 63 static struct clk_alpha_pll cam_cc_pll0 = { 64 .offset = 0x0, 65 .config = &cam_cc_pll0_config, 66 .vco_table = taycan_eko_t_vco, 67 .num_vco = ARRAY_SIZE(taycan_eko_t_vco), 68 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], 69 .clkr = { 70 .hw.init = &(const struct clk_init_data) { 71 .name = "cam_cc_pll0", 72 .parent_data = &(const struct clk_parent_data) { 73 .index = DT_BI_TCXO, 74 }, 75 .num_parents = 1, 76 .ops = &clk_alpha_pll_taycan_eko_t_ops, 77 }, 78 }, 79 }; 80 81 static const struct clk_div_table post_div_table_cam_cc_pll0_out_even[] = { 82 { 0x1, 2 }, 83 { } 84 }; 85 86 static struct clk_alpha_pll_postdiv cam_cc_pll0_out_even = { 87 .offset = 0x0, 88 .post_div_shift = 10, 89 .post_div_table = post_div_table_cam_cc_pll0_out_even, 90 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll0_out_even), 91 .width = 4, 92 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], 93 .clkr.hw.init = &(const struct clk_init_data) { 94 .name = "cam_cc_pll0_out_even", 95 .parent_hws = (const struct clk_hw*[]) { 96 &cam_cc_pll0.clkr.hw, 97 }, 98 .num_parents = 1, 99 .flags = CLK_SET_RATE_PARENT, 100 .ops = &clk_alpha_pll_postdiv_taycan_eko_t_ops, 101 }, 102 }; 103 104 static const struct clk_div_table post_div_table_cam_cc_pll0_out_odd[] = { 105 { 0x2, 3 }, 106 { } 107 }; 108 109 static struct clk_alpha_pll_postdiv cam_cc_pll0_out_odd = { 110 .offset = 0x0, 111 .post_div_shift = 14, 112 .post_div_table = post_div_table_cam_cc_pll0_out_odd, 113 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll0_out_odd), 114 .width = 4, 115 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], 116 .clkr.hw.init = &(const struct clk_init_data) { 117 .name = "cam_cc_pll0_out_odd", 118 .parent_hws = (const struct clk_hw*[]) { 119 &cam_cc_pll0.clkr.hw, 120 }, 121 .num_parents = 1, 122 .flags = CLK_SET_RATE_PARENT, 123 .ops = &clk_alpha_pll_postdiv_taycan_eko_t_ops, 124 }, 125 }; 126 127 /* 665.0 MHz Configuration */ 128 static const struct alpha_pll_config cam_cc_pll1_config = { 129 .l = 0x22, 130 .cal_l = 0x48, 131 .alpha = 0xa2aa, 132 .config_ctl_val = 0x25c400e7, 133 .config_ctl_hi_val = 0x0a8062e0, 134 .config_ctl_hi1_val = 0xf51dea20, 135 .user_ctl_val = 0x00000408, 136 .user_ctl_hi_val = 0x00000002, 137 }; 138 139 static struct clk_alpha_pll cam_cc_pll1 = { 140 .offset = 0x1000, 141 .config = &cam_cc_pll1_config, 142 .vco_table = taycan_eko_t_vco, 143 .num_vco = ARRAY_SIZE(taycan_eko_t_vco), 144 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], 145 .clkr = { 146 .hw.init = &(const struct clk_init_data) { 147 .name = "cam_cc_pll1", 148 .parent_data = &(const struct clk_parent_data) { 149 .index = DT_BI_TCXO, 150 }, 151 .num_parents = 1, 152 .ops = &clk_alpha_pll_taycan_eko_t_ops, 153 }, 154 }, 155 }; 156 157 static const struct clk_div_table post_div_table_cam_cc_pll1_out_even[] = { 158 { 0x1, 2 }, 159 { } 160 }; 161 162 static struct clk_alpha_pll_postdiv cam_cc_pll1_out_even = { 163 .offset = 0x1000, 164 .post_div_shift = 10, 165 .post_div_table = post_div_table_cam_cc_pll1_out_even, 166 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll1_out_even), 167 .width = 4, 168 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], 169 .clkr.hw.init = &(const struct clk_init_data) { 170 .name = "cam_cc_pll1_out_even", 171 .parent_hws = (const struct clk_hw*[]) { 172 &cam_cc_pll1.clkr.hw, 173 }, 174 .num_parents = 1, 175 .flags = CLK_SET_RATE_PARENT, 176 .ops = &clk_alpha_pll_postdiv_taycan_eko_t_ops, 177 }, 178 }; 179 180 /* 677.6 MHz Configuration */ 181 static const struct alpha_pll_config cam_cc_pll2_config = { 182 .l = 0x23, 183 .cal_l = 0x48, 184 .alpha = 0x4aaa, 185 .config_ctl_val = 0x25c400e7, 186 .config_ctl_hi_val = 0x0a8062e0, 187 .config_ctl_hi1_val = 0xf51dea20, 188 .user_ctl_val = 0x00000408, 189 .user_ctl_hi_val = 0x00000002, 190 }; 191 192 static struct clk_alpha_pll cam_cc_pll2 = { 193 .offset = 0x2000, 194 .config = &cam_cc_pll2_config, 195 .vco_table = taycan_eko_t_vco, 196 .num_vco = ARRAY_SIZE(taycan_eko_t_vco), 197 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], 198 .clkr = { 199 .hw.init = &(const struct clk_init_data) { 200 .name = "cam_cc_pll2", 201 .parent_data = &(const struct clk_parent_data) { 202 .index = DT_BI_TCXO, 203 }, 204 .num_parents = 1, 205 .ops = &clk_alpha_pll_taycan_eko_t_ops, 206 }, 207 }, 208 }; 209 210 static const struct clk_div_table post_div_table_cam_cc_pll2_out_even[] = { 211 { 0x1, 2 }, 212 { } 213 }; 214 215 static struct clk_alpha_pll_postdiv cam_cc_pll2_out_even = { 216 .offset = 0x2000, 217 .post_div_shift = 10, 218 .post_div_table = post_div_table_cam_cc_pll2_out_even, 219 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll2_out_even), 220 .width = 4, 221 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], 222 .clkr.hw.init = &(const struct clk_init_data) { 223 .name = "cam_cc_pll2_out_even", 224 .parent_hws = (const struct clk_hw*[]) { 225 &cam_cc_pll2.clkr.hw, 226 }, 227 .num_parents = 1, 228 .flags = CLK_SET_RATE_PARENT, 229 .ops = &clk_alpha_pll_postdiv_taycan_eko_t_ops, 230 }, 231 }; 232 233 /* 720.56 MHz Configuration */ 234 static const struct alpha_pll_config cam_cc_pll3_config = { 235 .l = 0x25, 236 .cal_l = 0x48, 237 .alpha = 0x8777, 238 .config_ctl_val = 0x25c400e7, 239 .config_ctl_hi_val = 0x0a8062e0, 240 .config_ctl_hi1_val = 0xf51dea20, 241 .user_ctl_val = 0x00000408, 242 .user_ctl_hi_val = 0x00000002, 243 }; 244 245 static struct clk_alpha_pll cam_cc_pll3 = { 246 .offset = 0x3000, 247 .config = &cam_cc_pll3_config, 248 .vco_table = taycan_eko_t_vco, 249 .num_vco = ARRAY_SIZE(taycan_eko_t_vco), 250 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], 251 .clkr = { 252 .hw.init = &(const struct clk_init_data) { 253 .name = "cam_cc_pll3", 254 .parent_data = &(const struct clk_parent_data) { 255 .index = DT_BI_TCXO, 256 }, 257 .num_parents = 1, 258 .ops = &clk_alpha_pll_taycan_eko_t_ops, 259 }, 260 }, 261 }; 262 263 static const struct clk_div_table post_div_table_cam_cc_pll3_out_even[] = { 264 { 0x1, 2 }, 265 { } 266 }; 267 268 static struct clk_alpha_pll_postdiv cam_cc_pll3_out_even = { 269 .offset = 0x3000, 270 .post_div_shift = 10, 271 .post_div_table = post_div_table_cam_cc_pll3_out_even, 272 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll3_out_even), 273 .width = 4, 274 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], 275 .clkr.hw.init = &(const struct clk_init_data) { 276 .name = "cam_cc_pll3_out_even", 277 .parent_hws = (const struct clk_hw*[]) { 278 &cam_cc_pll3.clkr.hw, 279 }, 280 .num_parents = 1, 281 .flags = CLK_SET_RATE_PARENT, 282 .ops = &clk_alpha_pll_postdiv_taycan_eko_t_ops, 283 }, 284 }; 285 286 /* 720.56 MHz Configuration */ 287 static const struct alpha_pll_config cam_cc_pll4_config = { 288 .l = 0x25, 289 .cal_l = 0x48, 290 .alpha = 0x8777, 291 .config_ctl_val = 0x25c400e7, 292 .config_ctl_hi_val = 0x0a8062e0, 293 .config_ctl_hi1_val = 0xf51dea20, 294 .user_ctl_val = 0x00000408, 295 .user_ctl_hi_val = 0x00000002, 296 }; 297 298 static struct clk_alpha_pll cam_cc_pll4 = { 299 .offset = 0x4000, 300 .config = &cam_cc_pll4_config, 301 .vco_table = taycan_eko_t_vco, 302 .num_vco = ARRAY_SIZE(taycan_eko_t_vco), 303 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], 304 .clkr = { 305 .hw.init = &(const struct clk_init_data) { 306 .name = "cam_cc_pll4", 307 .parent_data = &(const struct clk_parent_data) { 308 .index = DT_BI_TCXO, 309 }, 310 .num_parents = 1, 311 .ops = &clk_alpha_pll_taycan_eko_t_ops, 312 }, 313 }, 314 }; 315 316 static const struct clk_div_table post_div_table_cam_cc_pll4_out_even[] = { 317 { 0x1, 2 }, 318 { } 319 }; 320 321 static struct clk_alpha_pll_postdiv cam_cc_pll4_out_even = { 322 .offset = 0x4000, 323 .post_div_shift = 10, 324 .post_div_table = post_div_table_cam_cc_pll4_out_even, 325 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll4_out_even), 326 .width = 4, 327 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], 328 .clkr.hw.init = &(const struct clk_init_data) { 329 .name = "cam_cc_pll4_out_even", 330 .parent_hws = (const struct clk_hw*[]) { 331 &cam_cc_pll4.clkr.hw, 332 }, 333 .num_parents = 1, 334 .flags = CLK_SET_RATE_PARENT, 335 .ops = &clk_alpha_pll_postdiv_taycan_eko_t_ops, 336 }, 337 }; 338 339 /* 720.56 MHz Configuration */ 340 static const struct alpha_pll_config cam_cc_pll5_config = { 341 .l = 0x25, 342 .cal_l = 0x48, 343 .alpha = 0x8777, 344 .config_ctl_val = 0x25c400e7, 345 .config_ctl_hi_val = 0x0a8062e0, 346 .config_ctl_hi1_val = 0xf51dea20, 347 .user_ctl_val = 0x00000408, 348 .user_ctl_hi_val = 0x00000002, 349 }; 350 351 static struct clk_alpha_pll cam_cc_pll5 = { 352 .offset = 0x5000, 353 .config = &cam_cc_pll5_config, 354 .vco_table = taycan_eko_t_vco, 355 .num_vco = ARRAY_SIZE(taycan_eko_t_vco), 356 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], 357 .clkr = { 358 .hw.init = &(const struct clk_init_data) { 359 .name = "cam_cc_pll5", 360 .parent_data = &(const struct clk_parent_data) { 361 .index = DT_BI_TCXO, 362 }, 363 .num_parents = 1, 364 .ops = &clk_alpha_pll_taycan_eko_t_ops, 365 }, 366 }, 367 }; 368 369 static const struct clk_div_table post_div_table_cam_cc_pll5_out_even[] = { 370 { 0x1, 2 }, 371 { } 372 }; 373 374 static struct clk_alpha_pll_postdiv cam_cc_pll5_out_even = { 375 .offset = 0x5000, 376 .post_div_shift = 10, 377 .post_div_table = post_div_table_cam_cc_pll5_out_even, 378 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll5_out_even), 379 .width = 4, 380 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], 381 .clkr.hw.init = &(const struct clk_init_data) { 382 .name = "cam_cc_pll5_out_even", 383 .parent_hws = (const struct clk_hw*[]) { 384 &cam_cc_pll5.clkr.hw, 385 }, 386 .num_parents = 1, 387 .flags = CLK_SET_RATE_PARENT, 388 .ops = &clk_alpha_pll_postdiv_taycan_eko_t_ops, 389 }, 390 }; 391 392 /* 960.0 MHz Configuration */ 393 static const struct alpha_pll_config cam_cc_pll6_config = { 394 .l = 0x32, 395 .cal_l = 0x48, 396 .alpha = 0x0, 397 .config_ctl_val = 0x25c400e7, 398 .config_ctl_hi_val = 0x0a8062e0, 399 .config_ctl_hi1_val = 0xf51dea20, 400 .user_ctl_val = 0x00008408, 401 .user_ctl_hi_val = 0x00000002, 402 }; 403 404 static struct clk_alpha_pll cam_cc_pll6 = { 405 .offset = 0x6000, 406 .config = &cam_cc_pll6_config, 407 .vco_table = taycan_eko_t_vco, 408 .num_vco = ARRAY_SIZE(taycan_eko_t_vco), 409 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], 410 .clkr = { 411 .hw.init = &(const struct clk_init_data) { 412 .name = "cam_cc_pll6", 413 .parent_data = &(const struct clk_parent_data) { 414 .index = DT_BI_TCXO, 415 }, 416 .num_parents = 1, 417 .ops = &clk_alpha_pll_taycan_eko_t_ops, 418 }, 419 }, 420 }; 421 422 static const struct clk_div_table post_div_table_cam_cc_pll6_out_even[] = { 423 { 0x1, 2 }, 424 { } 425 }; 426 427 static struct clk_alpha_pll_postdiv cam_cc_pll6_out_even = { 428 .offset = 0x6000, 429 .post_div_shift = 10, 430 .post_div_table = post_div_table_cam_cc_pll6_out_even, 431 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll6_out_even), 432 .width = 4, 433 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], 434 .clkr.hw.init = &(const struct clk_init_data) { 435 .name = "cam_cc_pll6_out_even", 436 .parent_hws = (const struct clk_hw*[]) { 437 &cam_cc_pll6.clkr.hw, 438 }, 439 .num_parents = 1, 440 .flags = CLK_SET_RATE_PARENT, 441 .ops = &clk_alpha_pll_postdiv_taycan_eko_t_ops, 442 }, 443 }; 444 445 static const struct clk_div_table post_div_table_cam_cc_pll6_out_odd[] = { 446 { 0x2, 3 }, 447 { } 448 }; 449 450 static struct clk_alpha_pll_postdiv cam_cc_pll6_out_odd = { 451 .offset = 0x6000, 452 .post_div_shift = 14, 453 .post_div_table = post_div_table_cam_cc_pll6_out_odd, 454 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll6_out_odd), 455 .width = 4, 456 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], 457 .clkr.hw.init = &(const struct clk_init_data) { 458 .name = "cam_cc_pll6_out_odd", 459 .parent_hws = (const struct clk_hw*[]) { 460 &cam_cc_pll6.clkr.hw, 461 }, 462 .num_parents = 1, 463 .flags = CLK_SET_RATE_PARENT, 464 .ops = &clk_alpha_pll_postdiv_taycan_eko_t_ops, 465 }, 466 }; 467 468 /* 1000.0 MHz Configuration */ 469 static const struct alpha_pll_config cam_cc_pll7_config = { 470 .l = 0x34, 471 .cal_l = 0x48, 472 .alpha = 0x1555, 473 .config_ctl_val = 0x25c400e7, 474 .config_ctl_hi_val = 0x0a8062e0, 475 .config_ctl_hi1_val = 0xf51dea20, 476 .user_ctl_val = 0x00000408, 477 .user_ctl_hi_val = 0x00000002, 478 }; 479 480 static struct clk_alpha_pll cam_cc_pll7 = { 481 .offset = 0x7000, 482 .config = &cam_cc_pll7_config, 483 .vco_table = taycan_eko_t_vco, 484 .num_vco = ARRAY_SIZE(taycan_eko_t_vco), 485 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], 486 .clkr = { 487 .hw.init = &(const struct clk_init_data) { 488 .name = "cam_cc_pll7", 489 .parent_data = &(const struct clk_parent_data) { 490 .index = DT_BI_TCXO, 491 }, 492 .num_parents = 1, 493 .ops = &clk_alpha_pll_taycan_eko_t_ops, 494 }, 495 }, 496 }; 497 498 static const struct clk_div_table post_div_table_cam_cc_pll7_out_even[] = { 499 { 0x1, 2 }, 500 { } 501 }; 502 503 static struct clk_alpha_pll_postdiv cam_cc_pll7_out_even = { 504 .offset = 0x7000, 505 .post_div_shift = 10, 506 .post_div_table = post_div_table_cam_cc_pll7_out_even, 507 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll7_out_even), 508 .width = 4, 509 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], 510 .clkr.hw.init = &(const struct clk_init_data) { 511 .name = "cam_cc_pll7_out_even", 512 .parent_hws = (const struct clk_hw*[]) { 513 &cam_cc_pll7.clkr.hw, 514 }, 515 .num_parents = 1, 516 .flags = CLK_SET_RATE_PARENT, 517 .ops = &clk_alpha_pll_postdiv_taycan_eko_t_ops, 518 }, 519 }; 520 521 static const struct parent_map cam_cc_parent_map_0[] = { 522 { P_BI_TCXO, 0 }, 523 { P_CAM_CC_PLL0_OUT_MAIN, 1 }, 524 { P_CAM_CC_PLL0_OUT_EVEN, 2 }, 525 { P_CAM_CC_PLL0_OUT_ODD, 3 }, 526 { P_CAM_CC_PLL6_OUT_ODD, 4 }, 527 { P_CAM_CC_PLL6_OUT_EVEN, 5 }, 528 }; 529 530 static const struct clk_parent_data cam_cc_parent_data_0[] = { 531 { .index = DT_BI_TCXO }, 532 { .hw = &cam_cc_pll0.clkr.hw }, 533 { .hw = &cam_cc_pll0_out_even.clkr.hw }, 534 { .hw = &cam_cc_pll0_out_odd.clkr.hw }, 535 { .hw = &cam_cc_pll6_out_odd.clkr.hw }, 536 { .hw = &cam_cc_pll6_out_even.clkr.hw }, 537 }; 538 539 static const struct parent_map cam_cc_parent_map_1[] = { 540 { P_BI_TCXO, 0 }, 541 { P_CAM_CC_PLL0_OUT_MAIN, 1 }, 542 { P_CAM_CC_PLL0_OUT_EVEN, 2 }, 543 { P_CAM_CC_PLL0_OUT_ODD, 3 }, 544 { P_CAM_CC_PLL6_OUT_ODD, 4 }, 545 { P_CAM_CC_PLL6_OUT_EVEN, 5 }, 546 }; 547 548 static const struct clk_parent_data cam_cc_parent_data_1[] = { 549 { .index = DT_BI_TCXO }, 550 { .hw = &cam_cc_pll0.clkr.hw }, 551 { .hw = &cam_cc_pll0_out_even.clkr.hw }, 552 { .hw = &cam_cc_pll0_out_odd.clkr.hw }, 553 { .hw = &cam_cc_pll6_out_odd.clkr.hw }, 554 { .hw = &cam_cc_pll6_out_even.clkr.hw }, 555 }; 556 557 static const struct parent_map cam_cc_parent_map_2[] = { 558 { P_BI_TCXO, 0 }, 559 { P_CAM_CC_PLL0_OUT_MAIN, 1 }, 560 { P_CAM_CC_PLL0_OUT_EVEN, 2 }, 561 { P_CAM_CC_PLL0_OUT_ODD, 3 }, 562 { P_CAM_CC_PLL7_OUT_EVEN, 6 }, 563 }; 564 565 static const struct clk_parent_data cam_cc_parent_data_2[] = { 566 { .index = DT_BI_TCXO }, 567 { .hw = &cam_cc_pll0.clkr.hw }, 568 { .hw = &cam_cc_pll0_out_even.clkr.hw }, 569 { .hw = &cam_cc_pll0_out_odd.clkr.hw }, 570 { .hw = &cam_cc_pll7_out_even.clkr.hw }, 571 }; 572 573 static const struct parent_map cam_cc_parent_map_3[] = { 574 { P_BI_TCXO, 0 }, 575 { P_CAM_CC_PLL1_OUT_EVEN, 4 }, 576 }; 577 578 static const struct clk_parent_data cam_cc_parent_data_3[] = { 579 { .index = DT_BI_TCXO }, 580 { .hw = &cam_cc_pll1_out_even.clkr.hw }, 581 }; 582 583 static const struct parent_map cam_cc_parent_map_4[] = { 584 { P_BI_TCXO, 0 }, 585 { P_CAM_CC_PLL2_OUT_EVEN, 5 }, 586 }; 587 588 static const struct clk_parent_data cam_cc_parent_data_4[] = { 589 { .index = DT_BI_TCXO }, 590 { .hw = &cam_cc_pll2_out_even.clkr.hw }, 591 }; 592 593 static const struct parent_map cam_cc_parent_map_5[] = { 594 { P_BI_TCXO, 0 }, 595 { P_CAM_CC_PLL3_OUT_EVEN, 6 }, 596 }; 597 598 static const struct clk_parent_data cam_cc_parent_data_5[] = { 599 { .index = DT_BI_TCXO }, 600 { .hw = &cam_cc_pll3_out_even.clkr.hw }, 601 }; 602 603 static const struct parent_map cam_cc_parent_map_6[] = { 604 { P_BI_TCXO, 0 }, 605 { P_CAM_CC_PLL4_OUT_EVEN, 6 }, 606 }; 607 608 static const struct clk_parent_data cam_cc_parent_data_6[] = { 609 { .index = DT_BI_TCXO }, 610 { .hw = &cam_cc_pll4_out_even.clkr.hw }, 611 }; 612 613 static const struct parent_map cam_cc_parent_map_7[] = { 614 { P_BI_TCXO, 0 }, 615 { P_CAM_CC_PLL5_OUT_EVEN, 6 }, 616 }; 617 618 static const struct clk_parent_data cam_cc_parent_data_7[] = { 619 { .index = DT_BI_TCXO }, 620 { .hw = &cam_cc_pll5_out_even.clkr.hw }, 621 }; 622 623 static const struct parent_map cam_cc_parent_map_8[] = { 624 { P_BI_TCXO, 0 }, 625 }; 626 627 static const struct clk_parent_data cam_cc_parent_data_8[] = { 628 { .index = DT_BI_TCXO }, 629 }; 630 631 static const struct freq_tbl ftbl_cam_cc_camnoc_rt_axi_clk_src[] = { 632 F(19200000, P_BI_TCXO, 1, 0, 0), 633 F(200000000, P_CAM_CC_PLL0_OUT_EVEN, 3, 0, 0), 634 F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0), 635 F(400000000, P_CAM_CC_PLL0_OUT_EVEN, 1.5, 0, 0), 636 F(480000000, P_CAM_CC_PLL0_OUT_MAIN, 2.5, 0, 0), 637 { } 638 }; 639 640 static struct clk_rcg2 cam_cc_camnoc_rt_axi_clk_src = { 641 .cmd_rcgr = 0x212cc, 642 .mnd_width = 0, 643 .hid_width = 5, 644 .parent_map = cam_cc_parent_map_1, 645 .freq_tbl = ftbl_cam_cc_camnoc_rt_axi_clk_src, 646 .hw_clk_ctrl = true, 647 .clkr.hw.init = &(const struct clk_init_data) { 648 .name = "cam_cc_camnoc_rt_axi_clk_src", 649 .parent_data = cam_cc_parent_data_1, 650 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 651 .flags = CLK_SET_RATE_PARENT, 652 .ops = &clk_rcg2_shared_ops, 653 }, 654 }; 655 656 static const struct freq_tbl ftbl_cam_cc_cci_0_clk_src[] = { 657 F(37500000, P_CAM_CC_PLL0_OUT_EVEN, 16, 0, 0), 658 { } 659 }; 660 661 static struct clk_rcg2 cam_cc_cci_0_clk_src = { 662 .cmd_rcgr = 0x21250, 663 .mnd_width = 8, 664 .hid_width = 5, 665 .parent_map = cam_cc_parent_map_1, 666 .freq_tbl = ftbl_cam_cc_cci_0_clk_src, 667 .hw_clk_ctrl = true, 668 .clkr.hw.init = &(const struct clk_init_data) { 669 .name = "cam_cc_cci_0_clk_src", 670 .parent_data = cam_cc_parent_data_1, 671 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 672 .flags = CLK_SET_RATE_PARENT, 673 .ops = &clk_rcg2_shared_ops, 674 }, 675 }; 676 677 static struct clk_rcg2 cam_cc_cci_1_clk_src = { 678 .cmd_rcgr = 0x2126c, 679 .mnd_width = 8, 680 .hid_width = 5, 681 .parent_map = cam_cc_parent_map_1, 682 .freq_tbl = ftbl_cam_cc_cci_0_clk_src, 683 .hw_clk_ctrl = true, 684 .clkr.hw.init = &(const struct clk_init_data) { 685 .name = "cam_cc_cci_1_clk_src", 686 .parent_data = cam_cc_parent_data_1, 687 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 688 .flags = CLK_SET_RATE_PARENT, 689 .ops = &clk_rcg2_shared_ops, 690 }, 691 }; 692 693 static struct clk_rcg2 cam_cc_cci_2_clk_src = { 694 .cmd_rcgr = 0x21288, 695 .mnd_width = 8, 696 .hid_width = 5, 697 .parent_map = cam_cc_parent_map_1, 698 .freq_tbl = ftbl_cam_cc_cci_0_clk_src, 699 .hw_clk_ctrl = true, 700 .clkr.hw.init = &(const struct clk_init_data) { 701 .name = "cam_cc_cci_2_clk_src", 702 .parent_data = cam_cc_parent_data_1, 703 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 704 .flags = CLK_SET_RATE_PARENT, 705 .ops = &clk_rcg2_shared_ops, 706 }, 707 }; 708 709 static const struct freq_tbl ftbl_cam_cc_cphy_rx_clk_src[] = { 710 F(266666667, P_CAM_CC_PLL0_OUT_MAIN, 4.5, 0, 0), 711 F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0), 712 F(480000000, P_CAM_CC_PLL0_OUT_MAIN, 2.5, 0, 0), 713 { } 714 }; 715 716 static struct clk_rcg2 cam_cc_cphy_rx_clk_src = { 717 .cmd_rcgr = 0x21064, 718 .mnd_width = 0, 719 .hid_width = 5, 720 .parent_map = cam_cc_parent_map_0, 721 .freq_tbl = ftbl_cam_cc_cphy_rx_clk_src, 722 .clkr.hw.init = &(const struct clk_init_data) { 723 .name = "cam_cc_cphy_rx_clk_src", 724 .parent_data = cam_cc_parent_data_0, 725 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 726 .flags = CLK_SET_RATE_PARENT, 727 .ops = &clk_rcg2_shared_ops, 728 }, 729 }; 730 731 static const struct freq_tbl ftbl_cam_cc_cre_clk_src[] = { 732 F(137142857, P_CAM_CC_PLL6_OUT_EVEN, 3.5, 0, 0), 733 F(200000000, P_CAM_CC_PLL0_OUT_ODD, 2, 0, 0), 734 F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), 735 F(480000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0), 736 F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0), 737 { } 738 }; 739 740 static struct clk_rcg2 cam_cc_cre_clk_src = { 741 .cmd_rcgr = 0x211a0, 742 .mnd_width = 0, 743 .hid_width = 5, 744 .parent_map = cam_cc_parent_map_1, 745 .freq_tbl = ftbl_cam_cc_cre_clk_src, 746 .clkr.hw.init = &(const struct clk_init_data) { 747 .name = "cam_cc_cre_clk_src", 748 .parent_data = cam_cc_parent_data_1, 749 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 750 .flags = CLK_SET_RATE_PARENT, 751 .ops = &clk_rcg2_shared_ops, 752 }, 753 }; 754 755 static const struct freq_tbl ftbl_cam_cc_csi0phytimer_clk_src[] = { 756 F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), 757 { } 758 }; 759 760 static struct clk_rcg2 cam_cc_csi0phytimer_clk_src = { 761 .cmd_rcgr = 0x20000, 762 .mnd_width = 0, 763 .hid_width = 5, 764 .parent_map = cam_cc_parent_map_0, 765 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, 766 .clkr.hw.init = &(const struct clk_init_data) { 767 .name = "cam_cc_csi0phytimer_clk_src", 768 .parent_data = cam_cc_parent_data_0, 769 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 770 .flags = CLK_SET_RATE_PARENT, 771 .ops = &clk_rcg2_shared_ops, 772 }, 773 }; 774 775 static struct clk_rcg2 cam_cc_csi1phytimer_clk_src = { 776 .cmd_rcgr = 0x20024, 777 .mnd_width = 0, 778 .hid_width = 5, 779 .parent_map = cam_cc_parent_map_0, 780 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, 781 .clkr.hw.init = &(const struct clk_init_data) { 782 .name = "cam_cc_csi1phytimer_clk_src", 783 .parent_data = cam_cc_parent_data_0, 784 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 785 .flags = CLK_SET_RATE_PARENT, 786 .ops = &clk_rcg2_shared_ops, 787 }, 788 }; 789 790 static struct clk_rcg2 cam_cc_csi2phytimer_clk_src = { 791 .cmd_rcgr = 0x20044, 792 .mnd_width = 0, 793 .hid_width = 5, 794 .parent_map = cam_cc_parent_map_0, 795 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, 796 .clkr.hw.init = &(const struct clk_init_data) { 797 .name = "cam_cc_csi2phytimer_clk_src", 798 .parent_data = cam_cc_parent_data_0, 799 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 800 .flags = CLK_SET_RATE_PARENT, 801 .ops = &clk_rcg2_shared_ops, 802 }, 803 }; 804 805 static struct clk_rcg2 cam_cc_csi3phytimer_clk_src = { 806 .cmd_rcgr = 0x20064, 807 .mnd_width = 0, 808 .hid_width = 5, 809 .parent_map = cam_cc_parent_map_0, 810 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, 811 .clkr.hw.init = &(const struct clk_init_data) { 812 .name = "cam_cc_csi3phytimer_clk_src", 813 .parent_data = cam_cc_parent_data_0, 814 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 815 .flags = CLK_SET_RATE_PARENT, 816 .ops = &clk_rcg2_shared_ops, 817 }, 818 }; 819 820 static struct clk_rcg2 cam_cc_csi4phytimer_clk_src = { 821 .cmd_rcgr = 0x20084, 822 .mnd_width = 0, 823 .hid_width = 5, 824 .parent_map = cam_cc_parent_map_0, 825 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, 826 .clkr.hw.init = &(const struct clk_init_data) { 827 .name = "cam_cc_csi4phytimer_clk_src", 828 .parent_data = cam_cc_parent_data_0, 829 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 830 .flags = CLK_SET_RATE_PARENT, 831 .ops = &clk_rcg2_shared_ops, 832 }, 833 }; 834 835 static struct clk_rcg2 cam_cc_csi5phytimer_clk_src = { 836 .cmd_rcgr = 0x200a4, 837 .mnd_width = 0, 838 .hid_width = 5, 839 .parent_map = cam_cc_parent_map_0, 840 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, 841 .clkr.hw.init = &(const struct clk_init_data) { 842 .name = "cam_cc_csi5phytimer_clk_src", 843 .parent_data = cam_cc_parent_data_0, 844 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 845 .flags = CLK_SET_RATE_PARENT, 846 .ops = &clk_rcg2_shared_ops, 847 }, 848 }; 849 850 static struct clk_rcg2 cam_cc_csid_clk_src = { 851 .cmd_rcgr = 0x212a4, 852 .mnd_width = 0, 853 .hid_width = 5, 854 .parent_map = cam_cc_parent_map_0, 855 .freq_tbl = ftbl_cam_cc_cphy_rx_clk_src, 856 .clkr.hw.init = &(const struct clk_init_data) { 857 .name = "cam_cc_csid_clk_src", 858 .parent_data = cam_cc_parent_data_0, 859 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 860 .flags = CLK_SET_RATE_PARENT, 861 .ops = &clk_rcg2_shared_ops, 862 }, 863 }; 864 865 static const struct freq_tbl ftbl_cam_cc_fast_ahb_clk_src[] = { 866 F(213333333, P_CAM_CC_PLL6_OUT_ODD, 1.5, 0, 0), 867 F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0), 868 F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0), 869 { } 870 }; 871 872 static struct clk_rcg2 cam_cc_fast_ahb_clk_src = { 873 .cmd_rcgr = 0x200dc, 874 .mnd_width = 0, 875 .hid_width = 5, 876 .parent_map = cam_cc_parent_map_1, 877 .freq_tbl = ftbl_cam_cc_fast_ahb_clk_src, 878 .clkr.hw.init = &(const struct clk_init_data) { 879 .name = "cam_cc_fast_ahb_clk_src", 880 .parent_data = cam_cc_parent_data_1, 881 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 882 .flags = CLK_SET_RATE_PARENT, 883 .ops = &clk_rcg2_shared_ops, 884 }, 885 }; 886 887 static const struct freq_tbl ftbl_cam_cc_icp_0_clk_src[] = { 888 F(500000000, P_CAM_CC_PLL7_OUT_EVEN, 1, 0, 0), 889 F(600000000, P_CAM_CC_PLL7_OUT_EVEN, 1, 0, 0), 890 F(740000000, P_CAM_CC_PLL7_OUT_EVEN, 1, 0, 0), 891 F(875000000, P_CAM_CC_PLL7_OUT_EVEN, 1, 0, 0), 892 F(1000000000, P_CAM_CC_PLL7_OUT_EVEN, 1, 0, 0), 893 { } 894 }; 895 896 static struct clk_rcg2 cam_cc_icp_0_clk_src = { 897 .cmd_rcgr = 0x211f8, 898 .mnd_width = 0, 899 .hid_width = 5, 900 .parent_map = cam_cc_parent_map_2, 901 .freq_tbl = ftbl_cam_cc_icp_0_clk_src, 902 .clkr.hw.init = &(const struct clk_init_data) { 903 .name = "cam_cc_icp_0_clk_src", 904 .parent_data = cam_cc_parent_data_2, 905 .num_parents = ARRAY_SIZE(cam_cc_parent_data_2), 906 .flags = CLK_SET_RATE_PARENT, 907 .ops = &clk_rcg2_shared_ops, 908 }, 909 }; 910 911 static struct clk_rcg2 cam_cc_icp_1_clk_src = { 912 .cmd_rcgr = 0x21220, 913 .mnd_width = 0, 914 .hid_width = 5, 915 .parent_map = cam_cc_parent_map_2, 916 .freq_tbl = ftbl_cam_cc_icp_0_clk_src, 917 .clkr.hw.init = &(const struct clk_init_data) { 918 .name = "cam_cc_icp_1_clk_src", 919 .parent_data = cam_cc_parent_data_2, 920 .num_parents = ARRAY_SIZE(cam_cc_parent_data_2), 921 .flags = CLK_SET_RATE_PARENT, 922 .ops = &clk_rcg2_shared_ops, 923 }, 924 }; 925 926 static struct clk_rcg2 cam_cc_ife_lite_clk_src = { 927 .cmd_rcgr = 0x21144, 928 .mnd_width = 0, 929 .hid_width = 5, 930 .parent_map = cam_cc_parent_map_0, 931 .freq_tbl = ftbl_cam_cc_cphy_rx_clk_src, 932 .clkr.hw.init = &(const struct clk_init_data) { 933 .name = "cam_cc_ife_lite_clk_src", 934 .parent_data = cam_cc_parent_data_0, 935 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 936 .flags = CLK_SET_RATE_PARENT, 937 .ops = &clk_rcg2_shared_ops, 938 }, 939 }; 940 941 static struct clk_rcg2 cam_cc_ife_lite_csid_clk_src = { 942 .cmd_rcgr = 0x21170, 943 .mnd_width = 0, 944 .hid_width = 5, 945 .parent_map = cam_cc_parent_map_0, 946 .freq_tbl = ftbl_cam_cc_cphy_rx_clk_src, 947 .clkr.hw.init = &(const struct clk_init_data) { 948 .name = "cam_cc_ife_lite_csid_clk_src", 949 .parent_data = cam_cc_parent_data_0, 950 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 951 .flags = CLK_SET_RATE_PARENT, 952 .ops = &clk_rcg2_shared_ops, 953 }, 954 }; 955 956 static const struct freq_tbl ftbl_cam_cc_ipe_nps_clk_src[] = { 957 F(332500000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), 958 F(475000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), 959 F(575000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), 960 F(675000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), 961 F(825000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), 962 { } 963 }; 964 965 static struct clk_rcg2 cam_cc_ipe_nps_clk_src = { 966 .cmd_rcgr = 0x20188, 967 .mnd_width = 0, 968 .hid_width = 5, 969 .parent_map = cam_cc_parent_map_3, 970 .freq_tbl = ftbl_cam_cc_ipe_nps_clk_src, 971 .clkr.hw.init = &(const struct clk_init_data) { 972 .name = "cam_cc_ipe_nps_clk_src", 973 .parent_data = cam_cc_parent_data_3, 974 .num_parents = ARRAY_SIZE(cam_cc_parent_data_3), 975 .flags = CLK_SET_RATE_PARENT, 976 .ops = &clk_rcg2_shared_ops, 977 }, 978 }; 979 980 static struct clk_rcg2 cam_cc_jpeg_clk_src = { 981 .cmd_rcgr = 0x211c4, 982 .mnd_width = 0, 983 .hid_width = 5, 984 .parent_map = cam_cc_parent_map_1, 985 .freq_tbl = ftbl_cam_cc_cre_clk_src, 986 .clkr.hw.init = &(const struct clk_init_data) { 987 .name = "cam_cc_jpeg_clk_src", 988 .parent_data = cam_cc_parent_data_1, 989 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 990 .flags = CLK_SET_RATE_PARENT, 991 .ops = &clk_rcg2_shared_ops, 992 }, 993 }; 994 995 static const struct freq_tbl ftbl_cam_cc_ofe_clk_src[] = { 996 F(338800000, P_CAM_CC_PLL2_OUT_EVEN, 1, 0, 0), 997 F(484000000, P_CAM_CC_PLL2_OUT_EVEN, 1, 0, 0), 998 F(586000000, P_CAM_CC_PLL2_OUT_EVEN, 1, 0, 0), 999 F(688000000, P_CAM_CC_PLL2_OUT_EVEN, 1, 0, 0), 1000 F(841000000, P_CAM_CC_PLL2_OUT_EVEN, 1, 0, 0), 1001 { } 1002 }; 1003 1004 static struct clk_rcg2 cam_cc_ofe_clk_src = { 1005 .cmd_rcgr = 0x2011c, 1006 .mnd_width = 0, 1007 .hid_width = 5, 1008 .parent_map = cam_cc_parent_map_4, 1009 .freq_tbl = ftbl_cam_cc_ofe_clk_src, 1010 .clkr.hw.init = &(const struct clk_init_data) { 1011 .name = "cam_cc_ofe_clk_src", 1012 .parent_data = cam_cc_parent_data_4, 1013 .num_parents = ARRAY_SIZE(cam_cc_parent_data_4), 1014 .flags = CLK_SET_RATE_PARENT, 1015 .ops = &clk_rcg2_shared_ops, 1016 }, 1017 }; 1018 1019 static const struct freq_tbl ftbl_cam_cc_qdss_debug_clk_src[] = { 1020 F(40000000, P_CAM_CC_PLL6_OUT_ODD, 8, 0, 0), 1021 F(60000000, P_CAM_CC_PLL6_OUT_EVEN, 8, 0, 0), 1022 F(120000000, P_CAM_CC_PLL0_OUT_EVEN, 5, 0, 0), 1023 F(240000000, P_CAM_CC_PLL0_OUT_MAIN, 5, 0, 0), 1024 { } 1025 }; 1026 1027 static struct clk_rcg2 cam_cc_qdss_debug_clk_src = { 1028 .cmd_rcgr = 0x21314, 1029 .mnd_width = 0, 1030 .hid_width = 5, 1031 .parent_map = cam_cc_parent_map_1, 1032 .freq_tbl = ftbl_cam_cc_qdss_debug_clk_src, 1033 .clkr.hw.init = &(const struct clk_init_data) { 1034 .name = "cam_cc_qdss_debug_clk_src", 1035 .parent_data = cam_cc_parent_data_1, 1036 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 1037 .flags = CLK_SET_RATE_PARENT, 1038 .ops = &clk_rcg2_shared_ops, 1039 }, 1040 }; 1041 1042 static const struct freq_tbl ftbl_cam_cc_slow_ahb_clk_src[] = { 1043 F(56470588, P_CAM_CC_PLL6_OUT_EVEN, 8.5, 0, 0), 1044 F(80000000, P_CAM_CC_PLL0_OUT_EVEN, 7.5, 0, 0), 1045 { } 1046 }; 1047 1048 static struct clk_rcg2 cam_cc_slow_ahb_clk_src = { 1049 .cmd_rcgr = 0x20100, 1050 .mnd_width = 0, 1051 .hid_width = 5, 1052 .parent_map = cam_cc_parent_map_1, 1053 .freq_tbl = ftbl_cam_cc_slow_ahb_clk_src, 1054 .clkr.hw.init = &(const struct clk_init_data) { 1055 .name = "cam_cc_slow_ahb_clk_src", 1056 .parent_data = cam_cc_parent_data_1, 1057 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 1058 .flags = CLK_SET_RATE_PARENT, 1059 .ops = &clk_rcg2_shared_ops, 1060 }, 1061 }; 1062 1063 static const struct freq_tbl ftbl_cam_cc_tfe_0_clk_src[] = { 1064 F(360280000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), 1065 F(480000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), 1066 F(630000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), 1067 F(716000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), 1068 F(833000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), 1069 { } 1070 }; 1071 1072 static struct clk_rcg2 cam_cc_tfe_0_clk_src = { 1073 .cmd_rcgr = 0x21018, 1074 .mnd_width = 0, 1075 .hid_width = 5, 1076 .parent_map = cam_cc_parent_map_5, 1077 .freq_tbl = ftbl_cam_cc_tfe_0_clk_src, 1078 .clkr.hw.init = &(const struct clk_init_data) { 1079 .name = "cam_cc_tfe_0_clk_src", 1080 .parent_data = cam_cc_parent_data_5, 1081 .num_parents = ARRAY_SIZE(cam_cc_parent_data_5), 1082 .flags = CLK_SET_RATE_PARENT, 1083 .ops = &clk_rcg2_shared_ops, 1084 }, 1085 }; 1086 1087 static const struct freq_tbl ftbl_cam_cc_tfe_1_clk_src[] = { 1088 F(360280000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), 1089 F(480000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), 1090 F(630000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), 1091 F(716000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), 1092 F(833000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), 1093 { } 1094 }; 1095 1096 static struct clk_rcg2 cam_cc_tfe_1_clk_src = { 1097 .cmd_rcgr = 0x21094, 1098 .mnd_width = 0, 1099 .hid_width = 5, 1100 .parent_map = cam_cc_parent_map_6, 1101 .freq_tbl = ftbl_cam_cc_tfe_1_clk_src, 1102 .clkr.hw.init = &(const struct clk_init_data) { 1103 .name = "cam_cc_tfe_1_clk_src", 1104 .parent_data = cam_cc_parent_data_6, 1105 .num_parents = ARRAY_SIZE(cam_cc_parent_data_6), 1106 .flags = CLK_SET_RATE_PARENT, 1107 .ops = &clk_rcg2_shared_ops, 1108 }, 1109 }; 1110 1111 static const struct freq_tbl ftbl_cam_cc_tfe_2_clk_src[] = { 1112 F(360280000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0), 1113 F(480000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0), 1114 F(630000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0), 1115 F(716000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0), 1116 F(833000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0), 1117 { } 1118 }; 1119 1120 static struct clk_rcg2 cam_cc_tfe_2_clk_src = { 1121 .cmd_rcgr = 0x210f8, 1122 .mnd_width = 0, 1123 .hid_width = 5, 1124 .parent_map = cam_cc_parent_map_7, 1125 .freq_tbl = ftbl_cam_cc_tfe_2_clk_src, 1126 .clkr.hw.init = &(const struct clk_init_data) { 1127 .name = "cam_cc_tfe_2_clk_src", 1128 .parent_data = cam_cc_parent_data_7, 1129 .num_parents = ARRAY_SIZE(cam_cc_parent_data_7), 1130 .flags = CLK_SET_RATE_PARENT, 1131 .ops = &clk_rcg2_shared_ops, 1132 }, 1133 }; 1134 1135 static const struct freq_tbl ftbl_cam_cc_xo_clk_src[] = { 1136 F(19200000, P_BI_TCXO, 1, 0, 0), 1137 { } 1138 }; 1139 1140 static struct clk_rcg2 cam_cc_xo_clk_src = { 1141 .cmd_rcgr = 0x2134c, 1142 .mnd_width = 0, 1143 .hid_width = 5, 1144 .parent_map = cam_cc_parent_map_8, 1145 .freq_tbl = ftbl_cam_cc_xo_clk_src, 1146 .clkr.hw.init = &(const struct clk_init_data) { 1147 .name = "cam_cc_xo_clk_src", 1148 .parent_data = cam_cc_parent_data_8, 1149 .num_parents = ARRAY_SIZE(cam_cc_parent_data_8), 1150 .flags = CLK_SET_RATE_PARENT, 1151 .ops = &clk_rcg2_ops, 1152 }, 1153 }; 1154 1155 static struct clk_branch cam_cc_cam_top_ahb_clk = { 1156 .halt_reg = 0x2137c, 1157 .halt_check = BRANCH_HALT, 1158 .clkr = { 1159 .enable_reg = 0x2137c, 1160 .enable_mask = BIT(0), 1161 .hw.init = &(const struct clk_init_data) { 1162 .name = "cam_cc_cam_top_ahb_clk", 1163 .parent_hws = (const struct clk_hw*[]) { 1164 &cam_cc_slow_ahb_clk_src.clkr.hw, 1165 }, 1166 .num_parents = 1, 1167 .flags = CLK_SET_RATE_PARENT, 1168 .ops = &clk_branch2_ops, 1169 }, 1170 }, 1171 }; 1172 1173 static struct clk_branch cam_cc_cam_top_fast_ahb_clk = { 1174 .halt_reg = 0x2136c, 1175 .halt_check = BRANCH_HALT, 1176 .clkr = { 1177 .enable_reg = 0x2136c, 1178 .enable_mask = BIT(0), 1179 .hw.init = &(const struct clk_init_data) { 1180 .name = "cam_cc_cam_top_fast_ahb_clk", 1181 .parent_hws = (const struct clk_hw*[]) { 1182 &cam_cc_fast_ahb_clk_src.clkr.hw, 1183 }, 1184 .num_parents = 1, 1185 .flags = CLK_SET_RATE_PARENT, 1186 .ops = &clk_branch2_ops, 1187 }, 1188 }, 1189 }; 1190 1191 static struct clk_branch cam_cc_camnoc_nrt_axi_clk = { 1192 .halt_reg = 0x212f8, 1193 .halt_check = BRANCH_HALT, 1194 .clkr = { 1195 .enable_reg = 0x212f8, 1196 .enable_mask = BIT(0), 1197 .hw.init = &(const struct clk_init_data) { 1198 .name = "cam_cc_camnoc_nrt_axi_clk", 1199 .parent_hws = (const struct clk_hw*[]) { 1200 &cam_cc_camnoc_rt_axi_clk_src.clkr.hw, 1201 }, 1202 .num_parents = 1, 1203 .flags = CLK_SET_RATE_PARENT, 1204 .ops = &clk_branch2_ops, 1205 }, 1206 }, 1207 }; 1208 1209 static struct clk_branch cam_cc_camnoc_nrt_cre_clk = { 1210 .halt_reg = 0x211bc, 1211 .halt_check = BRANCH_HALT, 1212 .clkr = { 1213 .enable_reg = 0x211bc, 1214 .enable_mask = BIT(0), 1215 .hw.init = &(const struct clk_init_data) { 1216 .name = "cam_cc_camnoc_nrt_cre_clk", 1217 .parent_hws = (const struct clk_hw*[]) { 1218 &cam_cc_cre_clk_src.clkr.hw, 1219 }, 1220 .num_parents = 1, 1221 .flags = CLK_SET_RATE_PARENT, 1222 .ops = &clk_branch2_ops, 1223 }, 1224 }, 1225 }; 1226 1227 static struct clk_branch cam_cc_camnoc_nrt_ipe_nps_clk = { 1228 .halt_reg = 0x201b0, 1229 .halt_check = BRANCH_HALT, 1230 .clkr = { 1231 .enable_reg = 0x201b0, 1232 .enable_mask = BIT(0), 1233 .hw.init = &(const struct clk_init_data) { 1234 .name = "cam_cc_camnoc_nrt_ipe_nps_clk", 1235 .parent_hws = (const struct clk_hw*[]) { 1236 &cam_cc_ipe_nps_clk_src.clkr.hw, 1237 }, 1238 .num_parents = 1, 1239 .flags = CLK_SET_RATE_PARENT, 1240 .ops = &clk_branch2_ops, 1241 }, 1242 }, 1243 }; 1244 1245 static struct clk_branch cam_cc_camnoc_nrt_ofe_main_clk = { 1246 .halt_reg = 0x20144, 1247 .halt_check = BRANCH_HALT, 1248 .clkr = { 1249 .enable_reg = 0x20144, 1250 .enable_mask = BIT(0), 1251 .hw.init = &(const struct clk_init_data) { 1252 .name = "cam_cc_camnoc_nrt_ofe_main_clk", 1253 .parent_hws = (const struct clk_hw*[]) { 1254 &cam_cc_ofe_clk_src.clkr.hw, 1255 }, 1256 .num_parents = 1, 1257 .flags = CLK_SET_RATE_PARENT, 1258 .ops = &clk_branch2_ops, 1259 }, 1260 }, 1261 }; 1262 1263 static struct clk_branch cam_cc_camnoc_rt_axi_clk = { 1264 .halt_reg = 0x212e4, 1265 .halt_check = BRANCH_HALT, 1266 .clkr = { 1267 .enable_reg = 0x212e4, 1268 .enable_mask = BIT(0), 1269 .hw.init = &(const struct clk_init_data) { 1270 .name = "cam_cc_camnoc_rt_axi_clk", 1271 .parent_hws = (const struct clk_hw*[]) { 1272 &cam_cc_camnoc_rt_axi_clk_src.clkr.hw, 1273 }, 1274 .num_parents = 1, 1275 .flags = CLK_SET_RATE_PARENT, 1276 .ops = &clk_branch2_ops, 1277 }, 1278 }, 1279 }; 1280 1281 static struct clk_branch cam_cc_camnoc_rt_ife_lite_clk = { 1282 .halt_reg = 0x2116c, 1283 .halt_check = BRANCH_HALT, 1284 .clkr = { 1285 .enable_reg = 0x2116c, 1286 .enable_mask = BIT(0), 1287 .hw.init = &(const struct clk_init_data) { 1288 .name = "cam_cc_camnoc_rt_ife_lite_clk", 1289 .parent_hws = (const struct clk_hw*[]) { 1290 &cam_cc_ife_lite_clk_src.clkr.hw, 1291 }, 1292 .num_parents = 1, 1293 .flags = CLK_SET_RATE_PARENT, 1294 .ops = &clk_branch2_ops, 1295 }, 1296 }, 1297 }; 1298 1299 static struct clk_branch cam_cc_camnoc_rt_tfe_0_main_clk = { 1300 .halt_reg = 0x21040, 1301 .halt_check = BRANCH_HALT, 1302 .clkr = { 1303 .enable_reg = 0x21040, 1304 .enable_mask = BIT(0), 1305 .hw.init = &(const struct clk_init_data) { 1306 .name = "cam_cc_camnoc_rt_tfe_0_main_clk", 1307 .parent_hws = (const struct clk_hw*[]) { 1308 &cam_cc_tfe_0_clk_src.clkr.hw, 1309 }, 1310 .num_parents = 1, 1311 .flags = CLK_SET_RATE_PARENT, 1312 .ops = &clk_branch2_ops, 1313 }, 1314 }, 1315 }; 1316 1317 static struct clk_branch cam_cc_camnoc_rt_tfe_1_main_clk = { 1318 .halt_reg = 0x210bc, 1319 .halt_check = BRANCH_HALT, 1320 .clkr = { 1321 .enable_reg = 0x210bc, 1322 .enable_mask = BIT(0), 1323 .hw.init = &(const struct clk_init_data) { 1324 .name = "cam_cc_camnoc_rt_tfe_1_main_clk", 1325 .parent_hws = (const struct clk_hw*[]) { 1326 &cam_cc_tfe_1_clk_src.clkr.hw, 1327 }, 1328 .num_parents = 1, 1329 .flags = CLK_SET_RATE_PARENT, 1330 .ops = &clk_branch2_ops, 1331 }, 1332 }, 1333 }; 1334 1335 static struct clk_branch cam_cc_camnoc_rt_tfe_2_main_clk = { 1336 .halt_reg = 0x21120, 1337 .halt_check = BRANCH_HALT, 1338 .clkr = { 1339 .enable_reg = 0x21120, 1340 .enable_mask = BIT(0), 1341 .hw.init = &(const struct clk_init_data) { 1342 .name = "cam_cc_camnoc_rt_tfe_2_main_clk", 1343 .parent_hws = (const struct clk_hw*[]) { 1344 &cam_cc_tfe_2_clk_src.clkr.hw, 1345 }, 1346 .num_parents = 1, 1347 .flags = CLK_SET_RATE_PARENT, 1348 .ops = &clk_branch2_ops, 1349 }, 1350 }, 1351 }; 1352 1353 static struct clk_branch cam_cc_camnoc_xo_clk = { 1354 .halt_reg = 0x2130c, 1355 .halt_check = BRANCH_HALT, 1356 .clkr = { 1357 .enable_reg = 0x2130c, 1358 .enable_mask = BIT(0), 1359 .hw.init = &(const struct clk_init_data) { 1360 .name = "cam_cc_camnoc_xo_clk", 1361 .parent_hws = (const struct clk_hw*[]) { 1362 &cam_cc_xo_clk_src.clkr.hw, 1363 }, 1364 .num_parents = 1, 1365 .flags = CLK_SET_RATE_PARENT, 1366 .ops = &clk_branch2_ops, 1367 }, 1368 }, 1369 }; 1370 1371 static struct clk_branch cam_cc_cci_0_clk = { 1372 .halt_reg = 0x21268, 1373 .halt_check = BRANCH_HALT, 1374 .clkr = { 1375 .enable_reg = 0x21268, 1376 .enable_mask = BIT(0), 1377 .hw.init = &(const struct clk_init_data) { 1378 .name = "cam_cc_cci_0_clk", 1379 .parent_hws = (const struct clk_hw*[]) { 1380 &cam_cc_cci_0_clk_src.clkr.hw, 1381 }, 1382 .num_parents = 1, 1383 .flags = CLK_SET_RATE_PARENT, 1384 .ops = &clk_branch2_ops, 1385 }, 1386 }, 1387 }; 1388 1389 static struct clk_branch cam_cc_cci_1_clk = { 1390 .halt_reg = 0x21284, 1391 .halt_check = BRANCH_HALT, 1392 .clkr = { 1393 .enable_reg = 0x21284, 1394 .enable_mask = BIT(0), 1395 .hw.init = &(const struct clk_init_data) { 1396 .name = "cam_cc_cci_1_clk", 1397 .parent_hws = (const struct clk_hw*[]) { 1398 &cam_cc_cci_1_clk_src.clkr.hw, 1399 }, 1400 .num_parents = 1, 1401 .flags = CLK_SET_RATE_PARENT, 1402 .ops = &clk_branch2_ops, 1403 }, 1404 }, 1405 }; 1406 1407 static struct clk_branch cam_cc_cci_2_clk = { 1408 .halt_reg = 0x212a0, 1409 .halt_check = BRANCH_HALT, 1410 .clkr = { 1411 .enable_reg = 0x212a0, 1412 .enable_mask = BIT(0), 1413 .hw.init = &(const struct clk_init_data) { 1414 .name = "cam_cc_cci_2_clk", 1415 .parent_hws = (const struct clk_hw*[]) { 1416 &cam_cc_cci_2_clk_src.clkr.hw, 1417 }, 1418 .num_parents = 1, 1419 .flags = CLK_SET_RATE_PARENT, 1420 .ops = &clk_branch2_ops, 1421 }, 1422 }, 1423 }; 1424 1425 static struct clk_branch cam_cc_core_ahb_clk = { 1426 .halt_reg = 0x21348, 1427 .halt_check = BRANCH_HALT_DELAY, 1428 .clkr = { 1429 .enable_reg = 0x21348, 1430 .enable_mask = BIT(0), 1431 .hw.init = &(const struct clk_init_data) { 1432 .name = "cam_cc_core_ahb_clk", 1433 .parent_hws = (const struct clk_hw*[]) { 1434 &cam_cc_slow_ahb_clk_src.clkr.hw, 1435 }, 1436 .num_parents = 1, 1437 .flags = CLK_SET_RATE_PARENT, 1438 .ops = &clk_branch2_ops, 1439 }, 1440 }, 1441 }; 1442 1443 static struct clk_branch cam_cc_cre_ahb_clk = { 1444 .halt_reg = 0x211c0, 1445 .halt_check = BRANCH_HALT, 1446 .clkr = { 1447 .enable_reg = 0x211c0, 1448 .enable_mask = BIT(0), 1449 .hw.init = &(const struct clk_init_data) { 1450 .name = "cam_cc_cre_ahb_clk", 1451 .parent_hws = (const struct clk_hw*[]) { 1452 &cam_cc_slow_ahb_clk_src.clkr.hw, 1453 }, 1454 .num_parents = 1, 1455 .flags = CLK_SET_RATE_PARENT, 1456 .ops = &clk_branch2_ops, 1457 }, 1458 }, 1459 }; 1460 1461 static struct clk_branch cam_cc_cre_clk = { 1462 .halt_reg = 0x211b8, 1463 .halt_check = BRANCH_HALT, 1464 .clkr = { 1465 .enable_reg = 0x211b8, 1466 .enable_mask = BIT(0), 1467 .hw.init = &(const struct clk_init_data) { 1468 .name = "cam_cc_cre_clk", 1469 .parent_hws = (const struct clk_hw*[]) { 1470 &cam_cc_cre_clk_src.clkr.hw, 1471 }, 1472 .num_parents = 1, 1473 .flags = CLK_SET_RATE_PARENT, 1474 .ops = &clk_branch2_ops, 1475 }, 1476 }, 1477 }; 1478 1479 static struct clk_branch cam_cc_csi0phytimer_clk = { 1480 .halt_reg = 0x20018, 1481 .halt_check = BRANCH_HALT, 1482 .clkr = { 1483 .enable_reg = 0x20018, 1484 .enable_mask = BIT(0), 1485 .hw.init = &(const struct clk_init_data) { 1486 .name = "cam_cc_csi0phytimer_clk", 1487 .parent_hws = (const struct clk_hw*[]) { 1488 &cam_cc_csi0phytimer_clk_src.clkr.hw, 1489 }, 1490 .num_parents = 1, 1491 .flags = CLK_SET_RATE_PARENT, 1492 .ops = &clk_branch2_ops, 1493 }, 1494 }, 1495 }; 1496 1497 static struct clk_branch cam_cc_csi1phytimer_clk = { 1498 .halt_reg = 0x2003c, 1499 .halt_check = BRANCH_HALT, 1500 .clkr = { 1501 .enable_reg = 0x2003c, 1502 .enable_mask = BIT(0), 1503 .hw.init = &(const struct clk_init_data) { 1504 .name = "cam_cc_csi1phytimer_clk", 1505 .parent_hws = (const struct clk_hw*[]) { 1506 &cam_cc_csi1phytimer_clk_src.clkr.hw, 1507 }, 1508 .num_parents = 1, 1509 .flags = CLK_SET_RATE_PARENT, 1510 .ops = &clk_branch2_ops, 1511 }, 1512 }, 1513 }; 1514 1515 static struct clk_branch cam_cc_csi2phytimer_clk = { 1516 .halt_reg = 0x2005c, 1517 .halt_check = BRANCH_HALT, 1518 .clkr = { 1519 .enable_reg = 0x2005c, 1520 .enable_mask = BIT(0), 1521 .hw.init = &(const struct clk_init_data) { 1522 .name = "cam_cc_csi2phytimer_clk", 1523 .parent_hws = (const struct clk_hw*[]) { 1524 &cam_cc_csi2phytimer_clk_src.clkr.hw, 1525 }, 1526 .num_parents = 1, 1527 .flags = CLK_SET_RATE_PARENT, 1528 .ops = &clk_branch2_ops, 1529 }, 1530 }, 1531 }; 1532 1533 static struct clk_branch cam_cc_csi3phytimer_clk = { 1534 .halt_reg = 0x2007c, 1535 .halt_check = BRANCH_HALT, 1536 .clkr = { 1537 .enable_reg = 0x2007c, 1538 .enable_mask = BIT(0), 1539 .hw.init = &(const struct clk_init_data) { 1540 .name = "cam_cc_csi3phytimer_clk", 1541 .parent_hws = (const struct clk_hw*[]) { 1542 &cam_cc_csi3phytimer_clk_src.clkr.hw, 1543 }, 1544 .num_parents = 1, 1545 .flags = CLK_SET_RATE_PARENT, 1546 .ops = &clk_branch2_ops, 1547 }, 1548 }, 1549 }; 1550 1551 static struct clk_branch cam_cc_csi4phytimer_clk = { 1552 .halt_reg = 0x2009c, 1553 .halt_check = BRANCH_HALT, 1554 .clkr = { 1555 .enable_reg = 0x2009c, 1556 .enable_mask = BIT(0), 1557 .hw.init = &(const struct clk_init_data) { 1558 .name = "cam_cc_csi4phytimer_clk", 1559 .parent_hws = (const struct clk_hw*[]) { 1560 &cam_cc_csi4phytimer_clk_src.clkr.hw, 1561 }, 1562 .num_parents = 1, 1563 .flags = CLK_SET_RATE_PARENT, 1564 .ops = &clk_branch2_ops, 1565 }, 1566 }, 1567 }; 1568 1569 static struct clk_branch cam_cc_csi5phytimer_clk = { 1570 .halt_reg = 0x200bc, 1571 .halt_check = BRANCH_HALT, 1572 .clkr = { 1573 .enable_reg = 0x200bc, 1574 .enable_mask = BIT(0), 1575 .hw.init = &(const struct clk_init_data) { 1576 .name = "cam_cc_csi5phytimer_clk", 1577 .parent_hws = (const struct clk_hw*[]) { 1578 &cam_cc_csi5phytimer_clk_src.clkr.hw, 1579 }, 1580 .num_parents = 1, 1581 .flags = CLK_SET_RATE_PARENT, 1582 .ops = &clk_branch2_ops, 1583 }, 1584 }, 1585 }; 1586 1587 static struct clk_branch cam_cc_csid_clk = { 1588 .halt_reg = 0x212bc, 1589 .halt_check = BRANCH_HALT, 1590 .clkr = { 1591 .enable_reg = 0x212bc, 1592 .enable_mask = BIT(0), 1593 .hw.init = &(const struct clk_init_data) { 1594 .name = "cam_cc_csid_clk", 1595 .parent_hws = (const struct clk_hw*[]) { 1596 &cam_cc_csid_clk_src.clkr.hw, 1597 }, 1598 .num_parents = 1, 1599 .flags = CLK_SET_RATE_PARENT, 1600 .ops = &clk_branch2_ops, 1601 }, 1602 }, 1603 }; 1604 1605 static struct clk_branch cam_cc_csid_csiphy_rx_clk = { 1606 .halt_reg = 0x20020, 1607 .halt_check = BRANCH_HALT, 1608 .clkr = { 1609 .enable_reg = 0x20020, 1610 .enable_mask = BIT(0), 1611 .hw.init = &(const struct clk_init_data) { 1612 .name = "cam_cc_csid_csiphy_rx_clk", 1613 .parent_hws = (const struct clk_hw*[]) { 1614 &cam_cc_cphy_rx_clk_src.clkr.hw, 1615 }, 1616 .num_parents = 1, 1617 .flags = CLK_SET_RATE_PARENT, 1618 .ops = &clk_branch2_ops, 1619 }, 1620 }, 1621 }; 1622 1623 static struct clk_branch cam_cc_csiphy0_clk = { 1624 .halt_reg = 0x2001c, 1625 .halt_check = BRANCH_HALT, 1626 .clkr = { 1627 .enable_reg = 0x2001c, 1628 .enable_mask = BIT(0), 1629 .hw.init = &(const struct clk_init_data) { 1630 .name = "cam_cc_csiphy0_clk", 1631 .parent_hws = (const struct clk_hw*[]) { 1632 &cam_cc_cphy_rx_clk_src.clkr.hw, 1633 }, 1634 .num_parents = 1, 1635 .flags = CLK_SET_RATE_PARENT, 1636 .ops = &clk_branch2_ops, 1637 }, 1638 }, 1639 }; 1640 1641 static struct clk_branch cam_cc_csiphy1_clk = { 1642 .halt_reg = 0x20040, 1643 .halt_check = BRANCH_HALT, 1644 .clkr = { 1645 .enable_reg = 0x20040, 1646 .enable_mask = BIT(0), 1647 .hw.init = &(const struct clk_init_data) { 1648 .name = "cam_cc_csiphy1_clk", 1649 .parent_hws = (const struct clk_hw*[]) { 1650 &cam_cc_cphy_rx_clk_src.clkr.hw, 1651 }, 1652 .num_parents = 1, 1653 .flags = CLK_SET_RATE_PARENT, 1654 .ops = &clk_branch2_ops, 1655 }, 1656 }, 1657 }; 1658 1659 static struct clk_branch cam_cc_csiphy2_clk = { 1660 .halt_reg = 0x20060, 1661 .halt_check = BRANCH_HALT, 1662 .clkr = { 1663 .enable_reg = 0x20060, 1664 .enable_mask = BIT(0), 1665 .hw.init = &(const struct clk_init_data) { 1666 .name = "cam_cc_csiphy2_clk", 1667 .parent_hws = (const struct clk_hw*[]) { 1668 &cam_cc_cphy_rx_clk_src.clkr.hw, 1669 }, 1670 .num_parents = 1, 1671 .flags = CLK_SET_RATE_PARENT, 1672 .ops = &clk_branch2_ops, 1673 }, 1674 }, 1675 }; 1676 1677 static struct clk_branch cam_cc_csiphy3_clk = { 1678 .halt_reg = 0x20080, 1679 .halt_check = BRANCH_HALT, 1680 .clkr = { 1681 .enable_reg = 0x20080, 1682 .enable_mask = BIT(0), 1683 .hw.init = &(const struct clk_init_data) { 1684 .name = "cam_cc_csiphy3_clk", 1685 .parent_hws = (const struct clk_hw*[]) { 1686 &cam_cc_cphy_rx_clk_src.clkr.hw, 1687 }, 1688 .num_parents = 1, 1689 .flags = CLK_SET_RATE_PARENT, 1690 .ops = &clk_branch2_ops, 1691 }, 1692 }, 1693 }; 1694 1695 static struct clk_branch cam_cc_csiphy4_clk = { 1696 .halt_reg = 0x200a0, 1697 .halt_check = BRANCH_HALT, 1698 .clkr = { 1699 .enable_reg = 0x200a0, 1700 .enable_mask = BIT(0), 1701 .hw.init = &(const struct clk_init_data) { 1702 .name = "cam_cc_csiphy4_clk", 1703 .parent_hws = (const struct clk_hw*[]) { 1704 &cam_cc_cphy_rx_clk_src.clkr.hw, 1705 }, 1706 .num_parents = 1, 1707 .flags = CLK_SET_RATE_PARENT, 1708 .ops = &clk_branch2_ops, 1709 }, 1710 }, 1711 }; 1712 1713 static struct clk_branch cam_cc_csiphy5_clk = { 1714 .halt_reg = 0x200c0, 1715 .halt_check = BRANCH_HALT, 1716 .clkr = { 1717 .enable_reg = 0x200c0, 1718 .enable_mask = BIT(0), 1719 .hw.init = &(const struct clk_init_data) { 1720 .name = "cam_cc_csiphy5_clk", 1721 .parent_hws = (const struct clk_hw*[]) { 1722 &cam_cc_cphy_rx_clk_src.clkr.hw, 1723 }, 1724 .num_parents = 1, 1725 .flags = CLK_SET_RATE_PARENT, 1726 .ops = &clk_branch2_ops, 1727 }, 1728 }, 1729 }; 1730 1731 static struct clk_branch cam_cc_icp_0_ahb_clk = { 1732 .halt_reg = 0x21248, 1733 .halt_check = BRANCH_HALT, 1734 .clkr = { 1735 .enable_reg = 0x21248, 1736 .enable_mask = BIT(0), 1737 .hw.init = &(const struct clk_init_data) { 1738 .name = "cam_cc_icp_0_ahb_clk", 1739 .parent_hws = (const struct clk_hw*[]) { 1740 &cam_cc_slow_ahb_clk_src.clkr.hw, 1741 }, 1742 .num_parents = 1, 1743 .flags = CLK_SET_RATE_PARENT, 1744 .ops = &clk_branch2_ops, 1745 }, 1746 }, 1747 }; 1748 1749 static struct clk_branch cam_cc_icp_0_clk = { 1750 .halt_reg = 0x21210, 1751 .halt_check = BRANCH_HALT, 1752 .clkr = { 1753 .enable_reg = 0x21210, 1754 .enable_mask = BIT(0), 1755 .hw.init = &(const struct clk_init_data) { 1756 .name = "cam_cc_icp_0_clk", 1757 .parent_hws = (const struct clk_hw*[]) { 1758 &cam_cc_icp_0_clk_src.clkr.hw, 1759 }, 1760 .num_parents = 1, 1761 .flags = CLK_SET_RATE_PARENT, 1762 .ops = &clk_branch2_ops, 1763 }, 1764 }, 1765 }; 1766 1767 static struct clk_branch cam_cc_icp_1_ahb_clk = { 1768 .halt_reg = 0x2124c, 1769 .halt_check = BRANCH_HALT, 1770 .clkr = { 1771 .enable_reg = 0x2124c, 1772 .enable_mask = BIT(0), 1773 .hw.init = &(const struct clk_init_data) { 1774 .name = "cam_cc_icp_1_ahb_clk", 1775 .parent_hws = (const struct clk_hw*[]) { 1776 &cam_cc_slow_ahb_clk_src.clkr.hw, 1777 }, 1778 .num_parents = 1, 1779 .flags = CLK_SET_RATE_PARENT, 1780 .ops = &clk_branch2_ops, 1781 }, 1782 }, 1783 }; 1784 1785 static struct clk_branch cam_cc_icp_1_clk = { 1786 .halt_reg = 0x21238, 1787 .halt_check = BRANCH_HALT, 1788 .clkr = { 1789 .enable_reg = 0x21238, 1790 .enable_mask = BIT(0), 1791 .hw.init = &(const struct clk_init_data) { 1792 .name = "cam_cc_icp_1_clk", 1793 .parent_hws = (const struct clk_hw*[]) { 1794 &cam_cc_icp_1_clk_src.clkr.hw, 1795 }, 1796 .num_parents = 1, 1797 .flags = CLK_SET_RATE_PARENT, 1798 .ops = &clk_branch2_ops, 1799 }, 1800 }, 1801 }; 1802 1803 static struct clk_branch cam_cc_ife_lite_ahb_clk = { 1804 .halt_reg = 0x2119c, 1805 .halt_check = BRANCH_HALT, 1806 .clkr = { 1807 .enable_reg = 0x2119c, 1808 .enable_mask = BIT(0), 1809 .hw.init = &(const struct clk_init_data) { 1810 .name = "cam_cc_ife_lite_ahb_clk", 1811 .parent_hws = (const struct clk_hw*[]) { 1812 &cam_cc_slow_ahb_clk_src.clkr.hw, 1813 }, 1814 .num_parents = 1, 1815 .flags = CLK_SET_RATE_PARENT, 1816 .ops = &clk_branch2_ops, 1817 }, 1818 }, 1819 }; 1820 1821 static struct clk_branch cam_cc_ife_lite_clk = { 1822 .halt_reg = 0x2115c, 1823 .halt_check = BRANCH_HALT, 1824 .clkr = { 1825 .enable_reg = 0x2115c, 1826 .enable_mask = BIT(0), 1827 .hw.init = &(const struct clk_init_data) { 1828 .name = "cam_cc_ife_lite_clk", 1829 .parent_hws = (const struct clk_hw*[]) { 1830 &cam_cc_ife_lite_clk_src.clkr.hw, 1831 }, 1832 .num_parents = 1, 1833 .flags = CLK_SET_RATE_PARENT, 1834 .ops = &clk_branch2_ops, 1835 }, 1836 }, 1837 }; 1838 1839 static struct clk_branch cam_cc_ife_lite_cphy_rx_clk = { 1840 .halt_reg = 0x21198, 1841 .halt_check = BRANCH_HALT, 1842 .clkr = { 1843 .enable_reg = 0x21198, 1844 .enable_mask = BIT(0), 1845 .hw.init = &(const struct clk_init_data) { 1846 .name = "cam_cc_ife_lite_cphy_rx_clk", 1847 .parent_hws = (const struct clk_hw*[]) { 1848 &cam_cc_cphy_rx_clk_src.clkr.hw, 1849 }, 1850 .num_parents = 1, 1851 .flags = CLK_SET_RATE_PARENT, 1852 .ops = &clk_branch2_ops, 1853 }, 1854 }, 1855 }; 1856 1857 static struct clk_branch cam_cc_ife_lite_csid_clk = { 1858 .halt_reg = 0x21188, 1859 .halt_check = BRANCH_HALT, 1860 .clkr = { 1861 .enable_reg = 0x21188, 1862 .enable_mask = BIT(0), 1863 .hw.init = &(const struct clk_init_data) { 1864 .name = "cam_cc_ife_lite_csid_clk", 1865 .parent_hws = (const struct clk_hw*[]) { 1866 &cam_cc_ife_lite_csid_clk_src.clkr.hw, 1867 }, 1868 .num_parents = 1, 1869 .flags = CLK_SET_RATE_PARENT, 1870 .ops = &clk_branch2_ops, 1871 }, 1872 }, 1873 }; 1874 1875 static struct clk_branch cam_cc_ipe_nps_ahb_clk = { 1876 .halt_reg = 0x201cc, 1877 .halt_check = BRANCH_HALT, 1878 .clkr = { 1879 .enable_reg = 0x201cc, 1880 .enable_mask = BIT(0), 1881 .hw.init = &(const struct clk_init_data) { 1882 .name = "cam_cc_ipe_nps_ahb_clk", 1883 .parent_hws = (const struct clk_hw*[]) { 1884 &cam_cc_slow_ahb_clk_src.clkr.hw, 1885 }, 1886 .num_parents = 1, 1887 .flags = CLK_SET_RATE_PARENT, 1888 .ops = &clk_branch2_ops, 1889 }, 1890 }, 1891 }; 1892 1893 static struct clk_branch cam_cc_ipe_nps_clk = { 1894 .halt_reg = 0x201a0, 1895 .halt_check = BRANCH_HALT, 1896 .clkr = { 1897 .enable_reg = 0x201a0, 1898 .enable_mask = BIT(0), 1899 .hw.init = &(const struct clk_init_data) { 1900 .name = "cam_cc_ipe_nps_clk", 1901 .parent_hws = (const struct clk_hw*[]) { 1902 &cam_cc_ipe_nps_clk_src.clkr.hw, 1903 }, 1904 .num_parents = 1, 1905 .flags = CLK_SET_RATE_PARENT, 1906 .ops = &clk_branch2_ops, 1907 }, 1908 }, 1909 }; 1910 1911 static struct clk_branch cam_cc_ipe_nps_fast_ahb_clk = { 1912 .halt_reg = 0x201d0, 1913 .halt_check = BRANCH_HALT, 1914 .clkr = { 1915 .enable_reg = 0x201d0, 1916 .enable_mask = BIT(0), 1917 .hw.init = &(const struct clk_init_data) { 1918 .name = "cam_cc_ipe_nps_fast_ahb_clk", 1919 .parent_hws = (const struct clk_hw*[]) { 1920 &cam_cc_fast_ahb_clk_src.clkr.hw, 1921 }, 1922 .num_parents = 1, 1923 .flags = CLK_SET_RATE_PARENT, 1924 .ops = &clk_branch2_ops, 1925 }, 1926 }, 1927 }; 1928 1929 static struct clk_branch cam_cc_ipe_pps_clk = { 1930 .halt_reg = 0x201b4, 1931 .halt_check = BRANCH_HALT, 1932 .clkr = { 1933 .enable_reg = 0x201b4, 1934 .enable_mask = BIT(0), 1935 .hw.init = &(const struct clk_init_data) { 1936 .name = "cam_cc_ipe_pps_clk", 1937 .parent_hws = (const struct clk_hw*[]) { 1938 &cam_cc_ipe_nps_clk_src.clkr.hw, 1939 }, 1940 .num_parents = 1, 1941 .flags = CLK_SET_RATE_PARENT, 1942 .ops = &clk_branch2_ops, 1943 }, 1944 }, 1945 }; 1946 1947 static struct clk_branch cam_cc_ipe_pps_fast_ahb_clk = { 1948 .halt_reg = 0x201d4, 1949 .halt_check = BRANCH_HALT, 1950 .clkr = { 1951 .enable_reg = 0x201d4, 1952 .enable_mask = BIT(0), 1953 .hw.init = &(const struct clk_init_data) { 1954 .name = "cam_cc_ipe_pps_fast_ahb_clk", 1955 .parent_hws = (const struct clk_hw*[]) { 1956 &cam_cc_fast_ahb_clk_src.clkr.hw, 1957 }, 1958 .num_parents = 1, 1959 .flags = CLK_SET_RATE_PARENT, 1960 .ops = &clk_branch2_ops, 1961 }, 1962 }, 1963 }; 1964 1965 static struct clk_branch cam_cc_jpeg_clk = { 1966 .halt_reg = 0x211dc, 1967 .halt_check = BRANCH_HALT, 1968 .clkr = { 1969 .enable_reg = 0x211dc, 1970 .enable_mask = BIT(0), 1971 .hw.init = &(const struct clk_init_data) { 1972 .name = "cam_cc_jpeg_clk", 1973 .parent_hws = (const struct clk_hw*[]) { 1974 &cam_cc_jpeg_clk_src.clkr.hw, 1975 }, 1976 .num_parents = 1, 1977 .flags = CLK_SET_RATE_PARENT, 1978 .ops = &clk_branch2_ops, 1979 }, 1980 }, 1981 }; 1982 1983 static struct clk_branch cam_cc_ofe_ahb_clk = { 1984 .halt_reg = 0x20118, 1985 .halt_check = BRANCH_HALT, 1986 .clkr = { 1987 .enable_reg = 0x20118, 1988 .enable_mask = BIT(0), 1989 .hw.init = &(const struct clk_init_data) { 1990 .name = "cam_cc_ofe_ahb_clk", 1991 .parent_hws = (const struct clk_hw*[]) { 1992 &cam_cc_slow_ahb_clk_src.clkr.hw, 1993 }, 1994 .num_parents = 1, 1995 .flags = CLK_SET_RATE_PARENT, 1996 .ops = &clk_branch2_ops, 1997 }, 1998 }, 1999 }; 2000 2001 static struct clk_branch cam_cc_ofe_anchor_clk = { 2002 .halt_reg = 0x20148, 2003 .halt_check = BRANCH_HALT, 2004 .clkr = { 2005 .enable_reg = 0x20148, 2006 .enable_mask = BIT(0), 2007 .hw.init = &(const struct clk_init_data) { 2008 .name = "cam_cc_ofe_anchor_clk", 2009 .parent_hws = (const struct clk_hw*[]) { 2010 &cam_cc_ofe_clk_src.clkr.hw, 2011 }, 2012 .num_parents = 1, 2013 .flags = CLK_SET_RATE_PARENT, 2014 .ops = &clk_branch2_ops, 2015 }, 2016 }, 2017 }; 2018 2019 static struct clk_branch cam_cc_ofe_anchor_fast_ahb_clk = { 2020 .halt_reg = 0x200f8, 2021 .halt_check = BRANCH_HALT, 2022 .clkr = { 2023 .enable_reg = 0x200f8, 2024 .enable_mask = BIT(0), 2025 .hw.init = &(const struct clk_init_data) { 2026 .name = "cam_cc_ofe_anchor_fast_ahb_clk", 2027 .parent_hws = (const struct clk_hw*[]) { 2028 &cam_cc_fast_ahb_clk_src.clkr.hw, 2029 }, 2030 .num_parents = 1, 2031 .flags = CLK_SET_RATE_PARENT, 2032 .ops = &clk_branch2_ops, 2033 }, 2034 }, 2035 }; 2036 2037 static struct clk_branch cam_cc_ofe_hdr_clk = { 2038 .halt_reg = 0x20158, 2039 .halt_check = BRANCH_HALT, 2040 .clkr = { 2041 .enable_reg = 0x20158, 2042 .enable_mask = BIT(0), 2043 .hw.init = &(const struct clk_init_data) { 2044 .name = "cam_cc_ofe_hdr_clk", 2045 .parent_hws = (const struct clk_hw*[]) { 2046 &cam_cc_ofe_clk_src.clkr.hw, 2047 }, 2048 .num_parents = 1, 2049 .flags = CLK_SET_RATE_PARENT, 2050 .ops = &clk_branch2_ops, 2051 }, 2052 }, 2053 }; 2054 2055 static struct clk_branch cam_cc_ofe_hdr_fast_ahb_clk = { 2056 .halt_reg = 0x200fc, 2057 .halt_check = BRANCH_HALT, 2058 .clkr = { 2059 .enable_reg = 0x200fc, 2060 .enable_mask = BIT(0), 2061 .hw.init = &(const struct clk_init_data) { 2062 .name = "cam_cc_ofe_hdr_fast_ahb_clk", 2063 .parent_hws = (const struct clk_hw*[]) { 2064 &cam_cc_fast_ahb_clk_src.clkr.hw, 2065 }, 2066 .num_parents = 1, 2067 .flags = CLK_SET_RATE_PARENT, 2068 .ops = &clk_branch2_ops, 2069 }, 2070 }, 2071 }; 2072 2073 static struct clk_branch cam_cc_ofe_main_clk = { 2074 .halt_reg = 0x20134, 2075 .halt_check = BRANCH_HALT, 2076 .clkr = { 2077 .enable_reg = 0x20134, 2078 .enable_mask = BIT(0), 2079 .hw.init = &(const struct clk_init_data) { 2080 .name = "cam_cc_ofe_main_clk", 2081 .parent_hws = (const struct clk_hw*[]) { 2082 &cam_cc_ofe_clk_src.clkr.hw, 2083 }, 2084 .num_parents = 1, 2085 .flags = CLK_SET_RATE_PARENT, 2086 .ops = &clk_branch2_ops, 2087 }, 2088 }, 2089 }; 2090 2091 static struct clk_branch cam_cc_ofe_main_fast_ahb_clk = { 2092 .halt_reg = 0x200f4, 2093 .halt_check = BRANCH_HALT, 2094 .clkr = { 2095 .enable_reg = 0x200f4, 2096 .enable_mask = BIT(0), 2097 .hw.init = &(const struct clk_init_data) { 2098 .name = "cam_cc_ofe_main_fast_ahb_clk", 2099 .parent_hws = (const struct clk_hw*[]) { 2100 &cam_cc_fast_ahb_clk_src.clkr.hw, 2101 }, 2102 .num_parents = 1, 2103 .flags = CLK_SET_RATE_PARENT, 2104 .ops = &clk_branch2_ops, 2105 }, 2106 }, 2107 }; 2108 2109 static struct clk_branch cam_cc_qdss_debug_clk = { 2110 .halt_reg = 0x2132c, 2111 .halt_check = BRANCH_HALT, 2112 .clkr = { 2113 .enable_reg = 0x2132c, 2114 .enable_mask = BIT(0), 2115 .hw.init = &(const struct clk_init_data) { 2116 .name = "cam_cc_qdss_debug_clk", 2117 .parent_hws = (const struct clk_hw*[]) { 2118 &cam_cc_qdss_debug_clk_src.clkr.hw, 2119 }, 2120 .num_parents = 1, 2121 .flags = CLK_SET_RATE_PARENT, 2122 .ops = &clk_branch2_ops, 2123 }, 2124 }, 2125 }; 2126 2127 static struct clk_branch cam_cc_qdss_debug_xo_clk = { 2128 .halt_reg = 0x21330, 2129 .halt_check = BRANCH_HALT, 2130 .clkr = { 2131 .enable_reg = 0x21330, 2132 .enable_mask = BIT(0), 2133 .hw.init = &(const struct clk_init_data) { 2134 .name = "cam_cc_qdss_debug_xo_clk", 2135 .parent_hws = (const struct clk_hw*[]) { 2136 &cam_cc_xo_clk_src.clkr.hw, 2137 }, 2138 .num_parents = 1, 2139 .flags = CLK_SET_RATE_PARENT, 2140 .ops = &clk_branch2_ops, 2141 }, 2142 }, 2143 }; 2144 2145 static struct clk_branch cam_cc_tfe_0_bayer_clk = { 2146 .halt_reg = 0x21044, 2147 .halt_check = BRANCH_HALT, 2148 .clkr = { 2149 .enable_reg = 0x21044, 2150 .enable_mask = BIT(0), 2151 .hw.init = &(const struct clk_init_data) { 2152 .name = "cam_cc_tfe_0_bayer_clk", 2153 .parent_hws = (const struct clk_hw*[]) { 2154 &cam_cc_tfe_0_clk_src.clkr.hw, 2155 }, 2156 .num_parents = 1, 2157 .flags = CLK_SET_RATE_PARENT, 2158 .ops = &clk_branch2_ops, 2159 }, 2160 }, 2161 }; 2162 2163 static struct clk_branch cam_cc_tfe_0_bayer_fast_ahb_clk = { 2164 .halt_reg = 0x21060, 2165 .halt_check = BRANCH_HALT, 2166 .clkr = { 2167 .enable_reg = 0x21060, 2168 .enable_mask = BIT(0), 2169 .hw.init = &(const struct clk_init_data) { 2170 .name = "cam_cc_tfe_0_bayer_fast_ahb_clk", 2171 .parent_hws = (const struct clk_hw*[]) { 2172 &cam_cc_fast_ahb_clk_src.clkr.hw, 2173 }, 2174 .num_parents = 1, 2175 .flags = CLK_SET_RATE_PARENT, 2176 .ops = &clk_branch2_ops, 2177 }, 2178 }, 2179 }; 2180 2181 static struct clk_branch cam_cc_tfe_0_main_clk = { 2182 .halt_reg = 0x21030, 2183 .halt_check = BRANCH_HALT, 2184 .clkr = { 2185 .enable_reg = 0x21030, 2186 .enable_mask = BIT(0), 2187 .hw.init = &(const struct clk_init_data) { 2188 .name = "cam_cc_tfe_0_main_clk", 2189 .parent_hws = (const struct clk_hw*[]) { 2190 &cam_cc_tfe_0_clk_src.clkr.hw, 2191 }, 2192 .num_parents = 1, 2193 .flags = CLK_SET_RATE_PARENT, 2194 .ops = &clk_branch2_ops, 2195 }, 2196 }, 2197 }; 2198 2199 static struct clk_branch cam_cc_tfe_0_main_fast_ahb_clk = { 2200 .halt_reg = 0x2105c, 2201 .halt_check = BRANCH_HALT, 2202 .clkr = { 2203 .enable_reg = 0x2105c, 2204 .enable_mask = BIT(0), 2205 .hw.init = &(const struct clk_init_data) { 2206 .name = "cam_cc_tfe_0_main_fast_ahb_clk", 2207 .parent_hws = (const struct clk_hw*[]) { 2208 &cam_cc_fast_ahb_clk_src.clkr.hw, 2209 }, 2210 .num_parents = 1, 2211 .flags = CLK_SET_RATE_PARENT, 2212 .ops = &clk_branch2_ops, 2213 }, 2214 }, 2215 }; 2216 2217 static struct clk_branch cam_cc_tfe_1_bayer_clk = { 2218 .halt_reg = 0x210c0, 2219 .halt_check = BRANCH_HALT, 2220 .clkr = { 2221 .enable_reg = 0x210c0, 2222 .enable_mask = BIT(0), 2223 .hw.init = &(const struct clk_init_data) { 2224 .name = "cam_cc_tfe_1_bayer_clk", 2225 .parent_hws = (const struct clk_hw*[]) { 2226 &cam_cc_tfe_1_clk_src.clkr.hw, 2227 }, 2228 .num_parents = 1, 2229 .flags = CLK_SET_RATE_PARENT, 2230 .ops = &clk_branch2_ops, 2231 }, 2232 }, 2233 }; 2234 2235 static struct clk_branch cam_cc_tfe_1_bayer_fast_ahb_clk = { 2236 .halt_reg = 0x210dc, 2237 .halt_check = BRANCH_HALT, 2238 .clkr = { 2239 .enable_reg = 0x210dc, 2240 .enable_mask = BIT(0), 2241 .hw.init = &(const struct clk_init_data) { 2242 .name = "cam_cc_tfe_1_bayer_fast_ahb_clk", 2243 .parent_hws = (const struct clk_hw*[]) { 2244 &cam_cc_fast_ahb_clk_src.clkr.hw, 2245 }, 2246 .num_parents = 1, 2247 .flags = CLK_SET_RATE_PARENT, 2248 .ops = &clk_branch2_ops, 2249 }, 2250 }, 2251 }; 2252 2253 static struct clk_branch cam_cc_tfe_1_main_clk = { 2254 .halt_reg = 0x210ac, 2255 .halt_check = BRANCH_HALT, 2256 .clkr = { 2257 .enable_reg = 0x210ac, 2258 .enable_mask = BIT(0), 2259 .hw.init = &(const struct clk_init_data) { 2260 .name = "cam_cc_tfe_1_main_clk", 2261 .parent_hws = (const struct clk_hw*[]) { 2262 &cam_cc_tfe_1_clk_src.clkr.hw, 2263 }, 2264 .num_parents = 1, 2265 .flags = CLK_SET_RATE_PARENT, 2266 .ops = &clk_branch2_ops, 2267 }, 2268 }, 2269 }; 2270 2271 static struct clk_branch cam_cc_tfe_1_main_fast_ahb_clk = { 2272 .halt_reg = 0x210d8, 2273 .halt_check = BRANCH_HALT, 2274 .clkr = { 2275 .enable_reg = 0x210d8, 2276 .enable_mask = BIT(0), 2277 .hw.init = &(const struct clk_init_data) { 2278 .name = "cam_cc_tfe_1_main_fast_ahb_clk", 2279 .parent_hws = (const struct clk_hw*[]) { 2280 &cam_cc_fast_ahb_clk_src.clkr.hw, 2281 }, 2282 .num_parents = 1, 2283 .flags = CLK_SET_RATE_PARENT, 2284 .ops = &clk_branch2_ops, 2285 }, 2286 }, 2287 }; 2288 2289 static struct clk_branch cam_cc_tfe_2_bayer_clk = { 2290 .halt_reg = 0x21124, 2291 .halt_check = BRANCH_HALT, 2292 .clkr = { 2293 .enable_reg = 0x21124, 2294 .enable_mask = BIT(0), 2295 .hw.init = &(const struct clk_init_data) { 2296 .name = "cam_cc_tfe_2_bayer_clk", 2297 .parent_hws = (const struct clk_hw*[]) { 2298 &cam_cc_tfe_2_clk_src.clkr.hw, 2299 }, 2300 .num_parents = 1, 2301 .flags = CLK_SET_RATE_PARENT, 2302 .ops = &clk_branch2_ops, 2303 }, 2304 }, 2305 }; 2306 2307 static struct clk_branch cam_cc_tfe_2_bayer_fast_ahb_clk = { 2308 .halt_reg = 0x21140, 2309 .halt_check = BRANCH_HALT, 2310 .clkr = { 2311 .enable_reg = 0x21140, 2312 .enable_mask = BIT(0), 2313 .hw.init = &(const struct clk_init_data) { 2314 .name = "cam_cc_tfe_2_bayer_fast_ahb_clk", 2315 .parent_hws = (const struct clk_hw*[]) { 2316 &cam_cc_fast_ahb_clk_src.clkr.hw, 2317 }, 2318 .num_parents = 1, 2319 .flags = CLK_SET_RATE_PARENT, 2320 .ops = &clk_branch2_ops, 2321 }, 2322 }, 2323 }; 2324 2325 static struct clk_branch cam_cc_tfe_2_main_clk = { 2326 .halt_reg = 0x21110, 2327 .halt_check = BRANCH_HALT, 2328 .clkr = { 2329 .enable_reg = 0x21110, 2330 .enable_mask = BIT(0), 2331 .hw.init = &(const struct clk_init_data) { 2332 .name = "cam_cc_tfe_2_main_clk", 2333 .parent_hws = (const struct clk_hw*[]) { 2334 &cam_cc_tfe_2_clk_src.clkr.hw, 2335 }, 2336 .num_parents = 1, 2337 .flags = CLK_SET_RATE_PARENT, 2338 .ops = &clk_branch2_ops, 2339 }, 2340 }, 2341 }; 2342 2343 static struct clk_branch cam_cc_tfe_2_main_fast_ahb_clk = { 2344 .halt_reg = 0x2113c, 2345 .halt_check = BRANCH_HALT, 2346 .clkr = { 2347 .enable_reg = 0x2113c, 2348 .enable_mask = BIT(0), 2349 .hw.init = &(const struct clk_init_data) { 2350 .name = "cam_cc_tfe_2_main_fast_ahb_clk", 2351 .parent_hws = (const struct clk_hw*[]) { 2352 &cam_cc_fast_ahb_clk_src.clkr.hw, 2353 }, 2354 .num_parents = 1, 2355 .flags = CLK_SET_RATE_PARENT, 2356 .ops = &clk_branch2_ops, 2357 }, 2358 }, 2359 }; 2360 2361 static struct clk_branch cam_cc_tracenoc_tpdm_1_cmb_clk = { 2362 .halt_reg = 0x21394, 2363 .halt_check = BRANCH_HALT, 2364 .clkr = { 2365 .enable_reg = 0x21394, 2366 .enable_mask = BIT(0), 2367 .hw.init = &(const struct clk_init_data) { 2368 .name = "cam_cc_tracenoc_tpdm_1_cmb_clk", 2369 .parent_hws = (const struct clk_hw*[]) { 2370 &cam_cc_xo_clk_src.clkr.hw, 2371 }, 2372 .num_parents = 1, 2373 .flags = CLK_SET_RATE_PARENT, 2374 .ops = &clk_branch2_ops, 2375 }, 2376 }, 2377 }; 2378 2379 static struct gdsc cam_cc_titan_top_gdsc = { 2380 .gdscr = 0x21334, 2381 .en_rest_wait_val = 0x2, 2382 .en_few_wait_val = 0x2, 2383 .clk_dis_wait_val = 0xf, 2384 .pd = { 2385 .name = "cam_cc_titan_top_gdsc", 2386 }, 2387 .pwrsts = PWRSTS_OFF_ON, 2388 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 2389 }; 2390 2391 static struct gdsc cam_cc_ipe_0_gdsc = { 2392 .gdscr = 0x20174, 2393 .en_rest_wait_val = 0x2, 2394 .en_few_wait_val = 0x2, 2395 .clk_dis_wait_val = 0xf, 2396 .pd = { 2397 .name = "cam_cc_ipe_0_gdsc", 2398 }, 2399 .parent = &cam_cc_titan_top_gdsc.pd, 2400 .pwrsts = PWRSTS_OFF_ON, 2401 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | HW_CTRL_TRIGGER, 2402 }; 2403 2404 static struct gdsc cam_cc_ofe_gdsc = { 2405 .gdscr = 0x200c8, 2406 .en_rest_wait_val = 0x2, 2407 .en_few_wait_val = 0x2, 2408 .clk_dis_wait_val = 0xf, 2409 .pd = { 2410 .name = "cam_cc_ofe_gdsc", 2411 }, 2412 .pwrsts = PWRSTS_OFF_ON, 2413 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | HW_CTRL_TRIGGER, 2414 .parent = &cam_cc_titan_top_gdsc.pd, 2415 }; 2416 2417 static struct gdsc cam_cc_tfe_0_gdsc = { 2418 .gdscr = 0x21004, 2419 .en_rest_wait_val = 0x2, 2420 .en_few_wait_val = 0x2, 2421 .clk_dis_wait_val = 0xf, 2422 .pd = { 2423 .name = "cam_cc_tfe_0_gdsc", 2424 }, 2425 .pwrsts = PWRSTS_OFF_ON, 2426 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 2427 .parent = &cam_cc_titan_top_gdsc.pd, 2428 }; 2429 2430 static struct gdsc cam_cc_tfe_1_gdsc = { 2431 .gdscr = 0x21080, 2432 .en_rest_wait_val = 0x2, 2433 .en_few_wait_val = 0x2, 2434 .clk_dis_wait_val = 0xf, 2435 .pd = { 2436 .name = "cam_cc_tfe_1_gdsc", 2437 }, 2438 .pwrsts = PWRSTS_OFF_ON, 2439 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 2440 .parent = &cam_cc_titan_top_gdsc.pd, 2441 }; 2442 2443 static struct gdsc cam_cc_tfe_2_gdsc = { 2444 .gdscr = 0x210e4, 2445 .en_rest_wait_val = 0x2, 2446 .en_few_wait_val = 0x2, 2447 .clk_dis_wait_val = 0xf, 2448 .pd = { 2449 .name = "cam_cc_tfe_2_gdsc", 2450 }, 2451 .pwrsts = PWRSTS_OFF_ON, 2452 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 2453 .parent = &cam_cc_titan_top_gdsc.pd, 2454 }; 2455 2456 static struct clk_regmap *cam_cc_kaanapali_clocks[] = { 2457 [CAM_CC_CAM_TOP_AHB_CLK] = &cam_cc_cam_top_ahb_clk.clkr, 2458 [CAM_CC_CAM_TOP_FAST_AHB_CLK] = &cam_cc_cam_top_fast_ahb_clk.clkr, 2459 [CAM_CC_CAMNOC_NRT_AXI_CLK] = &cam_cc_camnoc_nrt_axi_clk.clkr, 2460 [CAM_CC_CAMNOC_NRT_CRE_CLK] = &cam_cc_camnoc_nrt_cre_clk.clkr, 2461 [CAM_CC_CAMNOC_NRT_IPE_NPS_CLK] = &cam_cc_camnoc_nrt_ipe_nps_clk.clkr, 2462 [CAM_CC_CAMNOC_NRT_OFE_MAIN_CLK] = &cam_cc_camnoc_nrt_ofe_main_clk.clkr, 2463 [CAM_CC_CAMNOC_RT_AXI_CLK] = &cam_cc_camnoc_rt_axi_clk.clkr, 2464 [CAM_CC_CAMNOC_RT_AXI_CLK_SRC] = &cam_cc_camnoc_rt_axi_clk_src.clkr, 2465 [CAM_CC_CAMNOC_RT_IFE_LITE_CLK] = &cam_cc_camnoc_rt_ife_lite_clk.clkr, 2466 [CAM_CC_CAMNOC_RT_TFE_0_MAIN_CLK] = &cam_cc_camnoc_rt_tfe_0_main_clk.clkr, 2467 [CAM_CC_CAMNOC_RT_TFE_1_MAIN_CLK] = &cam_cc_camnoc_rt_tfe_1_main_clk.clkr, 2468 [CAM_CC_CAMNOC_RT_TFE_2_MAIN_CLK] = &cam_cc_camnoc_rt_tfe_2_main_clk.clkr, 2469 [CAM_CC_CAMNOC_XO_CLK] = &cam_cc_camnoc_xo_clk.clkr, 2470 [CAM_CC_CCI_0_CLK] = &cam_cc_cci_0_clk.clkr, 2471 [CAM_CC_CCI_0_CLK_SRC] = &cam_cc_cci_0_clk_src.clkr, 2472 [CAM_CC_CCI_1_CLK] = &cam_cc_cci_1_clk.clkr, 2473 [CAM_CC_CCI_1_CLK_SRC] = &cam_cc_cci_1_clk_src.clkr, 2474 [CAM_CC_CCI_2_CLK] = &cam_cc_cci_2_clk.clkr, 2475 [CAM_CC_CCI_2_CLK_SRC] = &cam_cc_cci_2_clk_src.clkr, 2476 [CAM_CC_CORE_AHB_CLK] = &cam_cc_core_ahb_clk.clkr, 2477 [CAM_CC_CPHY_RX_CLK_SRC] = &cam_cc_cphy_rx_clk_src.clkr, 2478 [CAM_CC_CRE_AHB_CLK] = &cam_cc_cre_ahb_clk.clkr, 2479 [CAM_CC_CRE_CLK] = &cam_cc_cre_clk.clkr, 2480 [CAM_CC_CRE_CLK_SRC] = &cam_cc_cre_clk_src.clkr, 2481 [CAM_CC_CSI0PHYTIMER_CLK] = &cam_cc_csi0phytimer_clk.clkr, 2482 [CAM_CC_CSI0PHYTIMER_CLK_SRC] = &cam_cc_csi0phytimer_clk_src.clkr, 2483 [CAM_CC_CSI1PHYTIMER_CLK] = &cam_cc_csi1phytimer_clk.clkr, 2484 [CAM_CC_CSI1PHYTIMER_CLK_SRC] = &cam_cc_csi1phytimer_clk_src.clkr, 2485 [CAM_CC_CSI2PHYTIMER_CLK] = &cam_cc_csi2phytimer_clk.clkr, 2486 [CAM_CC_CSI2PHYTIMER_CLK_SRC] = &cam_cc_csi2phytimer_clk_src.clkr, 2487 [CAM_CC_CSI3PHYTIMER_CLK] = &cam_cc_csi3phytimer_clk.clkr, 2488 [CAM_CC_CSI3PHYTIMER_CLK_SRC] = &cam_cc_csi3phytimer_clk_src.clkr, 2489 [CAM_CC_CSI4PHYTIMER_CLK] = &cam_cc_csi4phytimer_clk.clkr, 2490 [CAM_CC_CSI4PHYTIMER_CLK_SRC] = &cam_cc_csi4phytimer_clk_src.clkr, 2491 [CAM_CC_CSI5PHYTIMER_CLK] = &cam_cc_csi5phytimer_clk.clkr, 2492 [CAM_CC_CSI5PHYTIMER_CLK_SRC] = &cam_cc_csi5phytimer_clk_src.clkr, 2493 [CAM_CC_CSID_CLK] = &cam_cc_csid_clk.clkr, 2494 [CAM_CC_CSID_CLK_SRC] = &cam_cc_csid_clk_src.clkr, 2495 [CAM_CC_CSID_CSIPHY_RX_CLK] = &cam_cc_csid_csiphy_rx_clk.clkr, 2496 [CAM_CC_CSIPHY0_CLK] = &cam_cc_csiphy0_clk.clkr, 2497 [CAM_CC_CSIPHY1_CLK] = &cam_cc_csiphy1_clk.clkr, 2498 [CAM_CC_CSIPHY2_CLK] = &cam_cc_csiphy2_clk.clkr, 2499 [CAM_CC_CSIPHY3_CLK] = &cam_cc_csiphy3_clk.clkr, 2500 [CAM_CC_CSIPHY4_CLK] = &cam_cc_csiphy4_clk.clkr, 2501 [CAM_CC_CSIPHY5_CLK] = &cam_cc_csiphy5_clk.clkr, 2502 [CAM_CC_FAST_AHB_CLK_SRC] = &cam_cc_fast_ahb_clk_src.clkr, 2503 [CAM_CC_ICP_0_AHB_CLK] = &cam_cc_icp_0_ahb_clk.clkr, 2504 [CAM_CC_ICP_0_CLK] = &cam_cc_icp_0_clk.clkr, 2505 [CAM_CC_ICP_0_CLK_SRC] = &cam_cc_icp_0_clk_src.clkr, 2506 [CAM_CC_ICP_1_AHB_CLK] = &cam_cc_icp_1_ahb_clk.clkr, 2507 [CAM_CC_ICP_1_CLK] = &cam_cc_icp_1_clk.clkr, 2508 [CAM_CC_ICP_1_CLK_SRC] = &cam_cc_icp_1_clk_src.clkr, 2509 [CAM_CC_IFE_LITE_AHB_CLK] = &cam_cc_ife_lite_ahb_clk.clkr, 2510 [CAM_CC_IFE_LITE_CLK] = &cam_cc_ife_lite_clk.clkr, 2511 [CAM_CC_IFE_LITE_CLK_SRC] = &cam_cc_ife_lite_clk_src.clkr, 2512 [CAM_CC_IFE_LITE_CPHY_RX_CLK] = &cam_cc_ife_lite_cphy_rx_clk.clkr, 2513 [CAM_CC_IFE_LITE_CSID_CLK] = &cam_cc_ife_lite_csid_clk.clkr, 2514 [CAM_CC_IFE_LITE_CSID_CLK_SRC] = &cam_cc_ife_lite_csid_clk_src.clkr, 2515 [CAM_CC_IPE_NPS_AHB_CLK] = &cam_cc_ipe_nps_ahb_clk.clkr, 2516 [CAM_CC_IPE_NPS_CLK] = &cam_cc_ipe_nps_clk.clkr, 2517 [CAM_CC_IPE_NPS_CLK_SRC] = &cam_cc_ipe_nps_clk_src.clkr, 2518 [CAM_CC_IPE_NPS_FAST_AHB_CLK] = &cam_cc_ipe_nps_fast_ahb_clk.clkr, 2519 [CAM_CC_IPE_PPS_CLK] = &cam_cc_ipe_pps_clk.clkr, 2520 [CAM_CC_IPE_PPS_FAST_AHB_CLK] = &cam_cc_ipe_pps_fast_ahb_clk.clkr, 2521 [CAM_CC_JPEG_CLK] = &cam_cc_jpeg_clk.clkr, 2522 [CAM_CC_JPEG_CLK_SRC] = &cam_cc_jpeg_clk_src.clkr, 2523 [CAM_CC_OFE_AHB_CLK] = &cam_cc_ofe_ahb_clk.clkr, 2524 [CAM_CC_OFE_ANCHOR_CLK] = &cam_cc_ofe_anchor_clk.clkr, 2525 [CAM_CC_OFE_ANCHOR_FAST_AHB_CLK] = &cam_cc_ofe_anchor_fast_ahb_clk.clkr, 2526 [CAM_CC_OFE_CLK_SRC] = &cam_cc_ofe_clk_src.clkr, 2527 [CAM_CC_OFE_HDR_CLK] = &cam_cc_ofe_hdr_clk.clkr, 2528 [CAM_CC_OFE_HDR_FAST_AHB_CLK] = &cam_cc_ofe_hdr_fast_ahb_clk.clkr, 2529 [CAM_CC_OFE_MAIN_CLK] = &cam_cc_ofe_main_clk.clkr, 2530 [CAM_CC_OFE_MAIN_FAST_AHB_CLK] = &cam_cc_ofe_main_fast_ahb_clk.clkr, 2531 [CAM_CC_PLL0] = &cam_cc_pll0.clkr, 2532 [CAM_CC_PLL0_OUT_EVEN] = &cam_cc_pll0_out_even.clkr, 2533 [CAM_CC_PLL0_OUT_ODD] = &cam_cc_pll0_out_odd.clkr, 2534 [CAM_CC_PLL1] = &cam_cc_pll1.clkr, 2535 [CAM_CC_PLL1_OUT_EVEN] = &cam_cc_pll1_out_even.clkr, 2536 [CAM_CC_PLL2] = &cam_cc_pll2.clkr, 2537 [CAM_CC_PLL2_OUT_EVEN] = &cam_cc_pll2_out_even.clkr, 2538 [CAM_CC_PLL3] = &cam_cc_pll3.clkr, 2539 [CAM_CC_PLL3_OUT_EVEN] = &cam_cc_pll3_out_even.clkr, 2540 [CAM_CC_PLL4] = &cam_cc_pll4.clkr, 2541 [CAM_CC_PLL4_OUT_EVEN] = &cam_cc_pll4_out_even.clkr, 2542 [CAM_CC_PLL5] = &cam_cc_pll5.clkr, 2543 [CAM_CC_PLL5_OUT_EVEN] = &cam_cc_pll5_out_even.clkr, 2544 [CAM_CC_PLL6] = &cam_cc_pll6.clkr, 2545 [CAM_CC_PLL6_OUT_EVEN] = &cam_cc_pll6_out_even.clkr, 2546 [CAM_CC_PLL6_OUT_ODD] = &cam_cc_pll6_out_odd.clkr, 2547 [CAM_CC_PLL7] = &cam_cc_pll7.clkr, 2548 [CAM_CC_PLL7_OUT_EVEN] = &cam_cc_pll7_out_even.clkr, 2549 [CAM_CC_QDSS_DEBUG_CLK] = &cam_cc_qdss_debug_clk.clkr, 2550 [CAM_CC_QDSS_DEBUG_CLK_SRC] = &cam_cc_qdss_debug_clk_src.clkr, 2551 [CAM_CC_QDSS_DEBUG_XO_CLK] = &cam_cc_qdss_debug_xo_clk.clkr, 2552 [CAM_CC_SLOW_AHB_CLK_SRC] = &cam_cc_slow_ahb_clk_src.clkr, 2553 [CAM_CC_TFE_0_BAYER_CLK] = &cam_cc_tfe_0_bayer_clk.clkr, 2554 [CAM_CC_TFE_0_BAYER_FAST_AHB_CLK] = &cam_cc_tfe_0_bayer_fast_ahb_clk.clkr, 2555 [CAM_CC_TFE_0_CLK_SRC] = &cam_cc_tfe_0_clk_src.clkr, 2556 [CAM_CC_TFE_0_MAIN_CLK] = &cam_cc_tfe_0_main_clk.clkr, 2557 [CAM_CC_TFE_0_MAIN_FAST_AHB_CLK] = &cam_cc_tfe_0_main_fast_ahb_clk.clkr, 2558 [CAM_CC_TFE_1_BAYER_CLK] = &cam_cc_tfe_1_bayer_clk.clkr, 2559 [CAM_CC_TFE_1_BAYER_FAST_AHB_CLK] = &cam_cc_tfe_1_bayer_fast_ahb_clk.clkr, 2560 [CAM_CC_TFE_1_CLK_SRC] = &cam_cc_tfe_1_clk_src.clkr, 2561 [CAM_CC_TFE_1_MAIN_CLK] = &cam_cc_tfe_1_main_clk.clkr, 2562 [CAM_CC_TFE_1_MAIN_FAST_AHB_CLK] = &cam_cc_tfe_1_main_fast_ahb_clk.clkr, 2563 [CAM_CC_TFE_2_BAYER_CLK] = &cam_cc_tfe_2_bayer_clk.clkr, 2564 [CAM_CC_TFE_2_BAYER_FAST_AHB_CLK] = &cam_cc_tfe_2_bayer_fast_ahb_clk.clkr, 2565 [CAM_CC_TFE_2_CLK_SRC] = &cam_cc_tfe_2_clk_src.clkr, 2566 [CAM_CC_TFE_2_MAIN_CLK] = &cam_cc_tfe_2_main_clk.clkr, 2567 [CAM_CC_TFE_2_MAIN_FAST_AHB_CLK] = &cam_cc_tfe_2_main_fast_ahb_clk.clkr, 2568 [CAM_CC_TRACENOC_TPDM_1_CMB_CLK] = &cam_cc_tracenoc_tpdm_1_cmb_clk.clkr, 2569 [CAM_CC_XO_CLK_SRC] = &cam_cc_xo_clk_src.clkr, 2570 }; 2571 2572 static struct gdsc *cam_cc_kaanapali_gdscs[] = { 2573 [CAM_CC_IPE_0_GDSC] = &cam_cc_ipe_0_gdsc, 2574 [CAM_CC_OFE_GDSC] = &cam_cc_ofe_gdsc, 2575 [CAM_CC_TFE_0_GDSC] = &cam_cc_tfe_0_gdsc, 2576 [CAM_CC_TFE_1_GDSC] = &cam_cc_tfe_1_gdsc, 2577 [CAM_CC_TFE_2_GDSC] = &cam_cc_tfe_2_gdsc, 2578 [CAM_CC_TITAN_TOP_GDSC] = &cam_cc_titan_top_gdsc, 2579 }; 2580 2581 static const struct qcom_reset_map cam_cc_kaanapali_resets[] = { 2582 [CAM_CC_DRV_BCR] = { 0x2138c }, 2583 [CAM_CC_ICP_BCR] = { 0x211f4 }, 2584 [CAM_CC_IPE_0_BCR] = { 0x20170 }, 2585 [CAM_CC_OFE_BCR] = { 0x200c4 }, 2586 [CAM_CC_QDSS_DEBUG_BCR] = { 0x21310 }, 2587 [CAM_CC_TFE_0_BCR] = { 0x21000 }, 2588 [CAM_CC_TFE_1_BCR] = { 0x2107c }, 2589 [CAM_CC_TFE_2_BCR] = { 0x210e0 }, 2590 }; 2591 2592 static struct clk_alpha_pll *cam_cc_kaanapali_plls[] = { 2593 &cam_cc_pll0, 2594 &cam_cc_pll1, 2595 &cam_cc_pll2, 2596 &cam_cc_pll3, 2597 &cam_cc_pll4, 2598 &cam_cc_pll5, 2599 &cam_cc_pll6, 2600 &cam_cc_pll7, 2601 }; 2602 2603 static const u32 cam_cc_kaanapali_critical_cbcrs[] = { 2604 0x21398, /* CAM_CC_DRV_AHB_CLK */ 2605 0x21390, /* CAM_CC_DRV_XO_CLK */ 2606 0x21364, /* CAM_CC_GDSC_CLK */ 2607 0x21368, /* CAM_CC_SLEEP_CLK */ 2608 }; 2609 2610 static const struct regmap_config cam_cc_kaanapali_regmap_config = { 2611 .reg_bits = 32, 2612 .reg_stride = 4, 2613 .val_bits = 32, 2614 .max_register = 0x2601c, 2615 .fast_io = true, 2616 }; 2617 2618 static const struct qcom_cc_driver_data cam_cc_kaanapali_driver_data = { 2619 .alpha_plls = cam_cc_kaanapali_plls, 2620 .num_alpha_plls = ARRAY_SIZE(cam_cc_kaanapali_plls), 2621 .clk_cbcrs = cam_cc_kaanapali_critical_cbcrs, 2622 .num_clk_cbcrs = ARRAY_SIZE(cam_cc_kaanapali_critical_cbcrs), 2623 }; 2624 2625 static const struct qcom_cc_desc cam_cc_kaanapali_desc = { 2626 .config = &cam_cc_kaanapali_regmap_config, 2627 .clks = cam_cc_kaanapali_clocks, 2628 .num_clks = ARRAY_SIZE(cam_cc_kaanapali_clocks), 2629 .resets = cam_cc_kaanapali_resets, 2630 .num_resets = ARRAY_SIZE(cam_cc_kaanapali_resets), 2631 .gdscs = cam_cc_kaanapali_gdscs, 2632 .num_gdscs = ARRAY_SIZE(cam_cc_kaanapali_gdscs), 2633 .use_rpm = true, 2634 .driver_data = &cam_cc_kaanapali_driver_data, 2635 }; 2636 2637 static const struct of_device_id cam_cc_kaanapali_match_table[] = { 2638 { .compatible = "qcom,kaanapali-camcc" }, 2639 { } 2640 }; 2641 MODULE_DEVICE_TABLE(of, cam_cc_kaanapali_match_table); 2642 2643 static int cam_cc_kaanapali_probe(struct platform_device *pdev) 2644 { 2645 return qcom_cc_probe(pdev, &cam_cc_kaanapali_desc); 2646 } 2647 2648 static struct platform_driver cam_cc_kaanapali_driver = { 2649 .probe = cam_cc_kaanapali_probe, 2650 .driver = { 2651 .name = "camcc-kaanapali", 2652 .of_match_table = cam_cc_kaanapali_match_table, 2653 }, 2654 }; 2655 2656 module_platform_driver(cam_cc_kaanapali_driver); 2657 2658 MODULE_DESCRIPTION("QTI CAMCC Kaanapali Driver"); 2659 MODULE_LICENSE("GPL"); 2660