1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 4 */ 5 6 #include <linux/clk-provider.h> 7 #include <linux/mod_devicetable.h> 8 #include <linux/module.h> 9 #include <linux/of.h> 10 #include <linux/platform_device.h> 11 #include <linux/pm_runtime.h> 12 #include <linux/regmap.h> 13 14 #include <dt-bindings/clock/qcom,kaanapali-camcc.h> 15 16 #include "clk-alpha-pll.h" 17 #include "clk-branch.h" 18 #include "clk-pll.h" 19 #include "clk-rcg.h" 20 #include "clk-regmap.h" 21 #include "clk-regmap-divider.h" 22 #include "clk-regmap-mux.h" 23 #include "common.h" 24 #include "gdsc.h" 25 #include "reset.h" 26 27 enum { 28 DT_AHB_CLK, 29 DT_BI_TCXO, 30 DT_BI_TCXO_AO, 31 DT_SLEEP_CLK, 32 }; 33 34 enum { 35 P_BI_TCXO, 36 P_CAM_CC_PLL0_OUT_EVEN, 37 P_CAM_CC_PLL0_OUT_MAIN, 38 P_CAM_CC_PLL0_OUT_ODD, 39 P_CAM_CC_PLL1_OUT_EVEN, 40 P_CAM_CC_PLL2_OUT_EVEN, 41 P_CAM_CC_PLL3_OUT_EVEN, 42 P_CAM_CC_PLL4_OUT_EVEN, 43 P_CAM_CC_PLL5_OUT_EVEN, 44 P_CAM_CC_PLL6_OUT_EVEN, 45 P_CAM_CC_PLL6_OUT_ODD, 46 P_CAM_CC_PLL7_OUT_EVEN, 47 }; 48 49 static const struct pll_vco taycan_eko_t_vco[] = { 50 { 249600000, 2500000000, 0 }, 51 }; 52 53 /* 1200.0 MHz Configuration */ 54 static const struct alpha_pll_config cam_cc_pll0_config = { 55 .l = 0x3e, 56 .cal_l = 0x48, 57 .alpha = 0x8000, 58 .config_ctl_val = 0x25c400e7, 59 .config_ctl_hi_val = 0x0a8062e0, 60 .config_ctl_hi1_val = 0xf51dea20, 61 .user_ctl_val = 0x00008408, 62 .user_ctl_hi_val = 0x00000002, 63 }; 64 65 static struct clk_alpha_pll cam_cc_pll0 = { 66 .offset = 0x0, 67 .config = &cam_cc_pll0_config, 68 .vco_table = taycan_eko_t_vco, 69 .num_vco = ARRAY_SIZE(taycan_eko_t_vco), 70 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], 71 .clkr = { 72 .hw.init = &(const struct clk_init_data) { 73 .name = "cam_cc_pll0", 74 .parent_data = &(const struct clk_parent_data) { 75 .index = DT_BI_TCXO, 76 }, 77 .num_parents = 1, 78 .ops = &clk_alpha_pll_taycan_eko_t_ops, 79 }, 80 }, 81 }; 82 83 static const struct clk_div_table post_div_table_cam_cc_pll0_out_even[] = { 84 { 0x1, 2 }, 85 { } 86 }; 87 88 static struct clk_alpha_pll_postdiv cam_cc_pll0_out_even = { 89 .offset = 0x0, 90 .post_div_shift = 10, 91 .post_div_table = post_div_table_cam_cc_pll0_out_even, 92 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll0_out_even), 93 .width = 4, 94 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], 95 .clkr.hw.init = &(const struct clk_init_data) { 96 .name = "cam_cc_pll0_out_even", 97 .parent_hws = (const struct clk_hw*[]) { 98 &cam_cc_pll0.clkr.hw, 99 }, 100 .num_parents = 1, 101 .flags = CLK_SET_RATE_PARENT, 102 .ops = &clk_alpha_pll_postdiv_taycan_eko_t_ops, 103 }, 104 }; 105 106 static const struct clk_div_table post_div_table_cam_cc_pll0_out_odd[] = { 107 { 0x2, 3 }, 108 { } 109 }; 110 111 static struct clk_alpha_pll_postdiv cam_cc_pll0_out_odd = { 112 .offset = 0x0, 113 .post_div_shift = 14, 114 .post_div_table = post_div_table_cam_cc_pll0_out_odd, 115 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll0_out_odd), 116 .width = 4, 117 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], 118 .clkr.hw.init = &(const struct clk_init_data) { 119 .name = "cam_cc_pll0_out_odd", 120 .parent_hws = (const struct clk_hw*[]) { 121 &cam_cc_pll0.clkr.hw, 122 }, 123 .num_parents = 1, 124 .flags = CLK_SET_RATE_PARENT, 125 .ops = &clk_alpha_pll_postdiv_taycan_eko_t_ops, 126 }, 127 }; 128 129 /* 665.0 MHz Configuration */ 130 static const struct alpha_pll_config cam_cc_pll1_config = { 131 .l = 0x22, 132 .cal_l = 0x48, 133 .alpha = 0xa2aa, 134 .config_ctl_val = 0x25c400e7, 135 .config_ctl_hi_val = 0x0a8062e0, 136 .config_ctl_hi1_val = 0xf51dea20, 137 .user_ctl_val = 0x00000408, 138 .user_ctl_hi_val = 0x00000002, 139 }; 140 141 static struct clk_alpha_pll cam_cc_pll1 = { 142 .offset = 0x1000, 143 .config = &cam_cc_pll1_config, 144 .vco_table = taycan_eko_t_vco, 145 .num_vco = ARRAY_SIZE(taycan_eko_t_vco), 146 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], 147 .clkr = { 148 .hw.init = &(const struct clk_init_data) { 149 .name = "cam_cc_pll1", 150 .parent_data = &(const struct clk_parent_data) { 151 .index = DT_BI_TCXO, 152 }, 153 .num_parents = 1, 154 .ops = &clk_alpha_pll_taycan_eko_t_ops, 155 }, 156 }, 157 }; 158 159 static const struct clk_div_table post_div_table_cam_cc_pll1_out_even[] = { 160 { 0x1, 2 }, 161 { } 162 }; 163 164 static struct clk_alpha_pll_postdiv cam_cc_pll1_out_even = { 165 .offset = 0x1000, 166 .post_div_shift = 10, 167 .post_div_table = post_div_table_cam_cc_pll1_out_even, 168 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll1_out_even), 169 .width = 4, 170 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], 171 .clkr.hw.init = &(const struct clk_init_data) { 172 .name = "cam_cc_pll1_out_even", 173 .parent_hws = (const struct clk_hw*[]) { 174 &cam_cc_pll1.clkr.hw, 175 }, 176 .num_parents = 1, 177 .flags = CLK_SET_RATE_PARENT, 178 .ops = &clk_alpha_pll_postdiv_taycan_eko_t_ops, 179 }, 180 }; 181 182 /* 677.6 MHz Configuration */ 183 static const struct alpha_pll_config cam_cc_pll2_config = { 184 .l = 0x23, 185 .cal_l = 0x48, 186 .alpha = 0x4aaa, 187 .config_ctl_val = 0x25c400e7, 188 .config_ctl_hi_val = 0x0a8062e0, 189 .config_ctl_hi1_val = 0xf51dea20, 190 .user_ctl_val = 0x00000408, 191 .user_ctl_hi_val = 0x00000002, 192 }; 193 194 static struct clk_alpha_pll cam_cc_pll2 = { 195 .offset = 0x2000, 196 .config = &cam_cc_pll2_config, 197 .vco_table = taycan_eko_t_vco, 198 .num_vco = ARRAY_SIZE(taycan_eko_t_vco), 199 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], 200 .clkr = { 201 .hw.init = &(const struct clk_init_data) { 202 .name = "cam_cc_pll2", 203 .parent_data = &(const struct clk_parent_data) { 204 .index = DT_BI_TCXO, 205 }, 206 .num_parents = 1, 207 .ops = &clk_alpha_pll_taycan_eko_t_ops, 208 }, 209 }, 210 }; 211 212 static const struct clk_div_table post_div_table_cam_cc_pll2_out_even[] = { 213 { 0x1, 2 }, 214 { } 215 }; 216 217 static struct clk_alpha_pll_postdiv cam_cc_pll2_out_even = { 218 .offset = 0x2000, 219 .post_div_shift = 10, 220 .post_div_table = post_div_table_cam_cc_pll2_out_even, 221 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll2_out_even), 222 .width = 4, 223 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], 224 .clkr.hw.init = &(const struct clk_init_data) { 225 .name = "cam_cc_pll2_out_even", 226 .parent_hws = (const struct clk_hw*[]) { 227 &cam_cc_pll2.clkr.hw, 228 }, 229 .num_parents = 1, 230 .flags = CLK_SET_RATE_PARENT, 231 .ops = &clk_alpha_pll_postdiv_taycan_eko_t_ops, 232 }, 233 }; 234 235 /* 720.56 MHz Configuration */ 236 static const struct alpha_pll_config cam_cc_pll3_config = { 237 .l = 0x25, 238 .cal_l = 0x48, 239 .alpha = 0x8777, 240 .config_ctl_val = 0x25c400e7, 241 .config_ctl_hi_val = 0x0a8062e0, 242 .config_ctl_hi1_val = 0xf51dea20, 243 .user_ctl_val = 0x00000408, 244 .user_ctl_hi_val = 0x00000002, 245 }; 246 247 static struct clk_alpha_pll cam_cc_pll3 = { 248 .offset = 0x3000, 249 .config = &cam_cc_pll3_config, 250 .vco_table = taycan_eko_t_vco, 251 .num_vco = ARRAY_SIZE(taycan_eko_t_vco), 252 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], 253 .clkr = { 254 .hw.init = &(const struct clk_init_data) { 255 .name = "cam_cc_pll3", 256 .parent_data = &(const struct clk_parent_data) { 257 .index = DT_BI_TCXO, 258 }, 259 .num_parents = 1, 260 .ops = &clk_alpha_pll_taycan_eko_t_ops, 261 }, 262 }, 263 }; 264 265 static const struct clk_div_table post_div_table_cam_cc_pll3_out_even[] = { 266 { 0x1, 2 }, 267 { } 268 }; 269 270 static struct clk_alpha_pll_postdiv cam_cc_pll3_out_even = { 271 .offset = 0x3000, 272 .post_div_shift = 10, 273 .post_div_table = post_div_table_cam_cc_pll3_out_even, 274 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll3_out_even), 275 .width = 4, 276 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], 277 .clkr.hw.init = &(const struct clk_init_data) { 278 .name = "cam_cc_pll3_out_even", 279 .parent_hws = (const struct clk_hw*[]) { 280 &cam_cc_pll3.clkr.hw, 281 }, 282 .num_parents = 1, 283 .flags = CLK_SET_RATE_PARENT, 284 .ops = &clk_alpha_pll_postdiv_taycan_eko_t_ops, 285 }, 286 }; 287 288 /* 720.56 MHz Configuration */ 289 static const struct alpha_pll_config cam_cc_pll4_config = { 290 .l = 0x25, 291 .cal_l = 0x48, 292 .alpha = 0x8777, 293 .config_ctl_val = 0x25c400e7, 294 .config_ctl_hi_val = 0x0a8062e0, 295 .config_ctl_hi1_val = 0xf51dea20, 296 .user_ctl_val = 0x00000408, 297 .user_ctl_hi_val = 0x00000002, 298 }; 299 300 static struct clk_alpha_pll cam_cc_pll4 = { 301 .offset = 0x4000, 302 .config = &cam_cc_pll4_config, 303 .vco_table = taycan_eko_t_vco, 304 .num_vco = ARRAY_SIZE(taycan_eko_t_vco), 305 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], 306 .clkr = { 307 .hw.init = &(const struct clk_init_data) { 308 .name = "cam_cc_pll4", 309 .parent_data = &(const struct clk_parent_data) { 310 .index = DT_BI_TCXO, 311 }, 312 .num_parents = 1, 313 .ops = &clk_alpha_pll_taycan_eko_t_ops, 314 }, 315 }, 316 }; 317 318 static const struct clk_div_table post_div_table_cam_cc_pll4_out_even[] = { 319 { 0x1, 2 }, 320 { } 321 }; 322 323 static struct clk_alpha_pll_postdiv cam_cc_pll4_out_even = { 324 .offset = 0x4000, 325 .post_div_shift = 10, 326 .post_div_table = post_div_table_cam_cc_pll4_out_even, 327 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll4_out_even), 328 .width = 4, 329 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], 330 .clkr.hw.init = &(const struct clk_init_data) { 331 .name = "cam_cc_pll4_out_even", 332 .parent_hws = (const struct clk_hw*[]) { 333 &cam_cc_pll4.clkr.hw, 334 }, 335 .num_parents = 1, 336 .flags = CLK_SET_RATE_PARENT, 337 .ops = &clk_alpha_pll_postdiv_taycan_eko_t_ops, 338 }, 339 }; 340 341 /* 720.56 MHz Configuration */ 342 static const struct alpha_pll_config cam_cc_pll5_config = { 343 .l = 0x25, 344 .cal_l = 0x48, 345 .alpha = 0x8777, 346 .config_ctl_val = 0x25c400e7, 347 .config_ctl_hi_val = 0x0a8062e0, 348 .config_ctl_hi1_val = 0xf51dea20, 349 .user_ctl_val = 0x00000408, 350 .user_ctl_hi_val = 0x00000002, 351 }; 352 353 static struct clk_alpha_pll cam_cc_pll5 = { 354 .offset = 0x5000, 355 .config = &cam_cc_pll5_config, 356 .vco_table = taycan_eko_t_vco, 357 .num_vco = ARRAY_SIZE(taycan_eko_t_vco), 358 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], 359 .clkr = { 360 .hw.init = &(const struct clk_init_data) { 361 .name = "cam_cc_pll5", 362 .parent_data = &(const struct clk_parent_data) { 363 .index = DT_BI_TCXO, 364 }, 365 .num_parents = 1, 366 .ops = &clk_alpha_pll_taycan_eko_t_ops, 367 }, 368 }, 369 }; 370 371 static const struct clk_div_table post_div_table_cam_cc_pll5_out_even[] = { 372 { 0x1, 2 }, 373 { } 374 }; 375 376 static struct clk_alpha_pll_postdiv cam_cc_pll5_out_even = { 377 .offset = 0x5000, 378 .post_div_shift = 10, 379 .post_div_table = post_div_table_cam_cc_pll5_out_even, 380 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll5_out_even), 381 .width = 4, 382 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], 383 .clkr.hw.init = &(const struct clk_init_data) { 384 .name = "cam_cc_pll5_out_even", 385 .parent_hws = (const struct clk_hw*[]) { 386 &cam_cc_pll5.clkr.hw, 387 }, 388 .num_parents = 1, 389 .flags = CLK_SET_RATE_PARENT, 390 .ops = &clk_alpha_pll_postdiv_taycan_eko_t_ops, 391 }, 392 }; 393 394 /* 960.0 MHz Configuration */ 395 static const struct alpha_pll_config cam_cc_pll6_config = { 396 .l = 0x32, 397 .cal_l = 0x48, 398 .alpha = 0x0, 399 .config_ctl_val = 0x25c400e7, 400 .config_ctl_hi_val = 0x0a8062e0, 401 .config_ctl_hi1_val = 0xf51dea20, 402 .user_ctl_val = 0x00008408, 403 .user_ctl_hi_val = 0x00000002, 404 }; 405 406 static struct clk_alpha_pll cam_cc_pll6 = { 407 .offset = 0x6000, 408 .config = &cam_cc_pll6_config, 409 .vco_table = taycan_eko_t_vco, 410 .num_vco = ARRAY_SIZE(taycan_eko_t_vco), 411 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], 412 .clkr = { 413 .hw.init = &(const struct clk_init_data) { 414 .name = "cam_cc_pll6", 415 .parent_data = &(const struct clk_parent_data) { 416 .index = DT_BI_TCXO, 417 }, 418 .num_parents = 1, 419 .ops = &clk_alpha_pll_taycan_eko_t_ops, 420 }, 421 }, 422 }; 423 424 static const struct clk_div_table post_div_table_cam_cc_pll6_out_even[] = { 425 { 0x1, 2 }, 426 { } 427 }; 428 429 static struct clk_alpha_pll_postdiv cam_cc_pll6_out_even = { 430 .offset = 0x6000, 431 .post_div_shift = 10, 432 .post_div_table = post_div_table_cam_cc_pll6_out_even, 433 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll6_out_even), 434 .width = 4, 435 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], 436 .clkr.hw.init = &(const struct clk_init_data) { 437 .name = "cam_cc_pll6_out_even", 438 .parent_hws = (const struct clk_hw*[]) { 439 &cam_cc_pll6.clkr.hw, 440 }, 441 .num_parents = 1, 442 .flags = CLK_SET_RATE_PARENT, 443 .ops = &clk_alpha_pll_postdiv_taycan_eko_t_ops, 444 }, 445 }; 446 447 static const struct clk_div_table post_div_table_cam_cc_pll6_out_odd[] = { 448 { 0x2, 3 }, 449 { } 450 }; 451 452 static struct clk_alpha_pll_postdiv cam_cc_pll6_out_odd = { 453 .offset = 0x6000, 454 .post_div_shift = 14, 455 .post_div_table = post_div_table_cam_cc_pll6_out_odd, 456 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll6_out_odd), 457 .width = 4, 458 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], 459 .clkr.hw.init = &(const struct clk_init_data) { 460 .name = "cam_cc_pll6_out_odd", 461 .parent_hws = (const struct clk_hw*[]) { 462 &cam_cc_pll6.clkr.hw, 463 }, 464 .num_parents = 1, 465 .flags = CLK_SET_RATE_PARENT, 466 .ops = &clk_alpha_pll_postdiv_taycan_eko_t_ops, 467 }, 468 }; 469 470 /* 1000.0 MHz Configuration */ 471 static const struct alpha_pll_config cam_cc_pll7_config = { 472 .l = 0x34, 473 .cal_l = 0x48, 474 .alpha = 0x1555, 475 .config_ctl_val = 0x25c400e7, 476 .config_ctl_hi_val = 0x0a8062e0, 477 .config_ctl_hi1_val = 0xf51dea20, 478 .user_ctl_val = 0x00000408, 479 .user_ctl_hi_val = 0x00000002, 480 }; 481 482 static struct clk_alpha_pll cam_cc_pll7 = { 483 .offset = 0x7000, 484 .config = &cam_cc_pll7_config, 485 .vco_table = taycan_eko_t_vco, 486 .num_vco = ARRAY_SIZE(taycan_eko_t_vco), 487 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], 488 .clkr = { 489 .hw.init = &(const struct clk_init_data) { 490 .name = "cam_cc_pll7", 491 .parent_data = &(const struct clk_parent_data) { 492 .index = DT_BI_TCXO, 493 }, 494 .num_parents = 1, 495 .ops = &clk_alpha_pll_taycan_eko_t_ops, 496 }, 497 }, 498 }; 499 500 static const struct clk_div_table post_div_table_cam_cc_pll7_out_even[] = { 501 { 0x1, 2 }, 502 { } 503 }; 504 505 static struct clk_alpha_pll_postdiv cam_cc_pll7_out_even = { 506 .offset = 0x7000, 507 .post_div_shift = 10, 508 .post_div_table = post_div_table_cam_cc_pll7_out_even, 509 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll7_out_even), 510 .width = 4, 511 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], 512 .clkr.hw.init = &(const struct clk_init_data) { 513 .name = "cam_cc_pll7_out_even", 514 .parent_hws = (const struct clk_hw*[]) { 515 &cam_cc_pll7.clkr.hw, 516 }, 517 .num_parents = 1, 518 .flags = CLK_SET_RATE_PARENT, 519 .ops = &clk_alpha_pll_postdiv_taycan_eko_t_ops, 520 }, 521 }; 522 523 static const struct parent_map cam_cc_parent_map_0[] = { 524 { P_BI_TCXO, 0 }, 525 { P_CAM_CC_PLL0_OUT_MAIN, 1 }, 526 { P_CAM_CC_PLL0_OUT_EVEN, 2 }, 527 { P_CAM_CC_PLL0_OUT_ODD, 3 }, 528 { P_CAM_CC_PLL6_OUT_ODD, 4 }, 529 { P_CAM_CC_PLL6_OUT_EVEN, 5 }, 530 }; 531 532 static const struct clk_parent_data cam_cc_parent_data_0[] = { 533 { .index = DT_BI_TCXO }, 534 { .hw = &cam_cc_pll0.clkr.hw }, 535 { .hw = &cam_cc_pll0_out_even.clkr.hw }, 536 { .hw = &cam_cc_pll0_out_odd.clkr.hw }, 537 { .hw = &cam_cc_pll6_out_odd.clkr.hw }, 538 { .hw = &cam_cc_pll6_out_even.clkr.hw }, 539 }; 540 541 static const struct parent_map cam_cc_parent_map_1[] = { 542 { P_BI_TCXO, 0 }, 543 { P_CAM_CC_PLL0_OUT_MAIN, 1 }, 544 { P_CAM_CC_PLL0_OUT_EVEN, 2 }, 545 { P_CAM_CC_PLL0_OUT_ODD, 3 }, 546 { P_CAM_CC_PLL6_OUT_ODD, 4 }, 547 { P_CAM_CC_PLL6_OUT_EVEN, 5 }, 548 }; 549 550 static const struct clk_parent_data cam_cc_parent_data_1[] = { 551 { .index = DT_BI_TCXO }, 552 { .hw = &cam_cc_pll0.clkr.hw }, 553 { .hw = &cam_cc_pll0_out_even.clkr.hw }, 554 { .hw = &cam_cc_pll0_out_odd.clkr.hw }, 555 { .hw = &cam_cc_pll6_out_odd.clkr.hw }, 556 { .hw = &cam_cc_pll6_out_even.clkr.hw }, 557 }; 558 559 static const struct parent_map cam_cc_parent_map_2[] = { 560 { P_BI_TCXO, 0 }, 561 { P_CAM_CC_PLL0_OUT_MAIN, 1 }, 562 { P_CAM_CC_PLL0_OUT_EVEN, 2 }, 563 { P_CAM_CC_PLL0_OUT_ODD, 3 }, 564 { P_CAM_CC_PLL7_OUT_EVEN, 6 }, 565 }; 566 567 static const struct clk_parent_data cam_cc_parent_data_2[] = { 568 { .index = DT_BI_TCXO }, 569 { .hw = &cam_cc_pll0.clkr.hw }, 570 { .hw = &cam_cc_pll0_out_even.clkr.hw }, 571 { .hw = &cam_cc_pll0_out_odd.clkr.hw }, 572 { .hw = &cam_cc_pll7_out_even.clkr.hw }, 573 }; 574 575 static const struct parent_map cam_cc_parent_map_3[] = { 576 { P_BI_TCXO, 0 }, 577 { P_CAM_CC_PLL1_OUT_EVEN, 4 }, 578 }; 579 580 static const struct clk_parent_data cam_cc_parent_data_3[] = { 581 { .index = DT_BI_TCXO }, 582 { .hw = &cam_cc_pll1_out_even.clkr.hw }, 583 }; 584 585 static const struct parent_map cam_cc_parent_map_4[] = { 586 { P_BI_TCXO, 0 }, 587 { P_CAM_CC_PLL2_OUT_EVEN, 5 }, 588 }; 589 590 static const struct clk_parent_data cam_cc_parent_data_4[] = { 591 { .index = DT_BI_TCXO }, 592 { .hw = &cam_cc_pll2_out_even.clkr.hw }, 593 }; 594 595 static const struct parent_map cam_cc_parent_map_5[] = { 596 { P_BI_TCXO, 0 }, 597 { P_CAM_CC_PLL3_OUT_EVEN, 6 }, 598 }; 599 600 static const struct clk_parent_data cam_cc_parent_data_5[] = { 601 { .index = DT_BI_TCXO }, 602 { .hw = &cam_cc_pll3_out_even.clkr.hw }, 603 }; 604 605 static const struct parent_map cam_cc_parent_map_6[] = { 606 { P_BI_TCXO, 0 }, 607 { P_CAM_CC_PLL4_OUT_EVEN, 6 }, 608 }; 609 610 static const struct clk_parent_data cam_cc_parent_data_6[] = { 611 { .index = DT_BI_TCXO }, 612 { .hw = &cam_cc_pll4_out_even.clkr.hw }, 613 }; 614 615 static const struct parent_map cam_cc_parent_map_7[] = { 616 { P_BI_TCXO, 0 }, 617 { P_CAM_CC_PLL5_OUT_EVEN, 6 }, 618 }; 619 620 static const struct clk_parent_data cam_cc_parent_data_7[] = { 621 { .index = DT_BI_TCXO }, 622 { .hw = &cam_cc_pll5_out_even.clkr.hw }, 623 }; 624 625 static const struct parent_map cam_cc_parent_map_8[] = { 626 { P_BI_TCXO, 0 }, 627 }; 628 629 static const struct clk_parent_data cam_cc_parent_data_8[] = { 630 { .index = DT_BI_TCXO }, 631 }; 632 633 static const struct freq_tbl ftbl_cam_cc_camnoc_rt_axi_clk_src[] = { 634 F(19200000, P_BI_TCXO, 1, 0, 0), 635 F(200000000, P_CAM_CC_PLL0_OUT_EVEN, 3, 0, 0), 636 F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0), 637 F(400000000, P_CAM_CC_PLL0_OUT_EVEN, 1.5, 0, 0), 638 F(480000000, P_CAM_CC_PLL0_OUT_MAIN, 2.5, 0, 0), 639 { } 640 }; 641 642 static struct clk_rcg2 cam_cc_camnoc_rt_axi_clk_src = { 643 .cmd_rcgr = 0x212cc, 644 .mnd_width = 0, 645 .hid_width = 5, 646 .parent_map = cam_cc_parent_map_1, 647 .freq_tbl = ftbl_cam_cc_camnoc_rt_axi_clk_src, 648 .hw_clk_ctrl = true, 649 .clkr.hw.init = &(const struct clk_init_data) { 650 .name = "cam_cc_camnoc_rt_axi_clk_src", 651 .parent_data = cam_cc_parent_data_1, 652 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 653 .flags = CLK_SET_RATE_PARENT, 654 .ops = &clk_rcg2_shared_ops, 655 }, 656 }; 657 658 static const struct freq_tbl ftbl_cam_cc_cci_0_clk_src[] = { 659 F(37500000, P_CAM_CC_PLL0_OUT_EVEN, 16, 0, 0), 660 { } 661 }; 662 663 static struct clk_rcg2 cam_cc_cci_0_clk_src = { 664 .cmd_rcgr = 0x21250, 665 .mnd_width = 8, 666 .hid_width = 5, 667 .parent_map = cam_cc_parent_map_1, 668 .freq_tbl = ftbl_cam_cc_cci_0_clk_src, 669 .hw_clk_ctrl = true, 670 .clkr.hw.init = &(const struct clk_init_data) { 671 .name = "cam_cc_cci_0_clk_src", 672 .parent_data = cam_cc_parent_data_1, 673 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 674 .flags = CLK_SET_RATE_PARENT, 675 .ops = &clk_rcg2_shared_ops, 676 }, 677 }; 678 679 static struct clk_rcg2 cam_cc_cci_1_clk_src = { 680 .cmd_rcgr = 0x2126c, 681 .mnd_width = 8, 682 .hid_width = 5, 683 .parent_map = cam_cc_parent_map_1, 684 .freq_tbl = ftbl_cam_cc_cci_0_clk_src, 685 .hw_clk_ctrl = true, 686 .clkr.hw.init = &(const struct clk_init_data) { 687 .name = "cam_cc_cci_1_clk_src", 688 .parent_data = cam_cc_parent_data_1, 689 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 690 .flags = CLK_SET_RATE_PARENT, 691 .ops = &clk_rcg2_shared_ops, 692 }, 693 }; 694 695 static struct clk_rcg2 cam_cc_cci_2_clk_src = { 696 .cmd_rcgr = 0x21288, 697 .mnd_width = 8, 698 .hid_width = 5, 699 .parent_map = cam_cc_parent_map_1, 700 .freq_tbl = ftbl_cam_cc_cci_0_clk_src, 701 .hw_clk_ctrl = true, 702 .clkr.hw.init = &(const struct clk_init_data) { 703 .name = "cam_cc_cci_2_clk_src", 704 .parent_data = cam_cc_parent_data_1, 705 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 706 .flags = CLK_SET_RATE_PARENT, 707 .ops = &clk_rcg2_shared_ops, 708 }, 709 }; 710 711 static const struct freq_tbl ftbl_cam_cc_cphy_rx_clk_src[] = { 712 F(266666667, P_CAM_CC_PLL0_OUT_MAIN, 4.5, 0, 0), 713 F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0), 714 F(480000000, P_CAM_CC_PLL0_OUT_MAIN, 2.5, 0, 0), 715 { } 716 }; 717 718 static struct clk_rcg2 cam_cc_cphy_rx_clk_src = { 719 .cmd_rcgr = 0x21064, 720 .mnd_width = 0, 721 .hid_width = 5, 722 .parent_map = cam_cc_parent_map_0, 723 .freq_tbl = ftbl_cam_cc_cphy_rx_clk_src, 724 .clkr.hw.init = &(const struct clk_init_data) { 725 .name = "cam_cc_cphy_rx_clk_src", 726 .parent_data = cam_cc_parent_data_0, 727 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 728 .flags = CLK_SET_RATE_PARENT, 729 .ops = &clk_rcg2_shared_ops, 730 }, 731 }; 732 733 static const struct freq_tbl ftbl_cam_cc_cre_clk_src[] = { 734 F(137142857, P_CAM_CC_PLL6_OUT_EVEN, 3.5, 0, 0), 735 F(200000000, P_CAM_CC_PLL0_OUT_ODD, 2, 0, 0), 736 F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), 737 F(480000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0), 738 F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0), 739 { } 740 }; 741 742 static struct clk_rcg2 cam_cc_cre_clk_src = { 743 .cmd_rcgr = 0x211a0, 744 .mnd_width = 0, 745 .hid_width = 5, 746 .parent_map = cam_cc_parent_map_1, 747 .freq_tbl = ftbl_cam_cc_cre_clk_src, 748 .clkr.hw.init = &(const struct clk_init_data) { 749 .name = "cam_cc_cre_clk_src", 750 .parent_data = cam_cc_parent_data_1, 751 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 752 .flags = CLK_SET_RATE_PARENT, 753 .ops = &clk_rcg2_shared_ops, 754 }, 755 }; 756 757 static const struct freq_tbl ftbl_cam_cc_csi0phytimer_clk_src[] = { 758 F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), 759 { } 760 }; 761 762 static struct clk_rcg2 cam_cc_csi0phytimer_clk_src = { 763 .cmd_rcgr = 0x20000, 764 .mnd_width = 0, 765 .hid_width = 5, 766 .parent_map = cam_cc_parent_map_0, 767 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, 768 .clkr.hw.init = &(const struct clk_init_data) { 769 .name = "cam_cc_csi0phytimer_clk_src", 770 .parent_data = cam_cc_parent_data_0, 771 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 772 .flags = CLK_SET_RATE_PARENT, 773 .ops = &clk_rcg2_shared_ops, 774 }, 775 }; 776 777 static struct clk_rcg2 cam_cc_csi1phytimer_clk_src = { 778 .cmd_rcgr = 0x20024, 779 .mnd_width = 0, 780 .hid_width = 5, 781 .parent_map = cam_cc_parent_map_0, 782 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, 783 .clkr.hw.init = &(const struct clk_init_data) { 784 .name = "cam_cc_csi1phytimer_clk_src", 785 .parent_data = cam_cc_parent_data_0, 786 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 787 .flags = CLK_SET_RATE_PARENT, 788 .ops = &clk_rcg2_shared_ops, 789 }, 790 }; 791 792 static struct clk_rcg2 cam_cc_csi2phytimer_clk_src = { 793 .cmd_rcgr = 0x20044, 794 .mnd_width = 0, 795 .hid_width = 5, 796 .parent_map = cam_cc_parent_map_0, 797 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, 798 .clkr.hw.init = &(const struct clk_init_data) { 799 .name = "cam_cc_csi2phytimer_clk_src", 800 .parent_data = cam_cc_parent_data_0, 801 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 802 .flags = CLK_SET_RATE_PARENT, 803 .ops = &clk_rcg2_shared_ops, 804 }, 805 }; 806 807 static struct clk_rcg2 cam_cc_csi3phytimer_clk_src = { 808 .cmd_rcgr = 0x20064, 809 .mnd_width = 0, 810 .hid_width = 5, 811 .parent_map = cam_cc_parent_map_0, 812 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, 813 .clkr.hw.init = &(const struct clk_init_data) { 814 .name = "cam_cc_csi3phytimer_clk_src", 815 .parent_data = cam_cc_parent_data_0, 816 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 817 .flags = CLK_SET_RATE_PARENT, 818 .ops = &clk_rcg2_shared_ops, 819 }, 820 }; 821 822 static struct clk_rcg2 cam_cc_csi4phytimer_clk_src = { 823 .cmd_rcgr = 0x20084, 824 .mnd_width = 0, 825 .hid_width = 5, 826 .parent_map = cam_cc_parent_map_0, 827 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, 828 .clkr.hw.init = &(const struct clk_init_data) { 829 .name = "cam_cc_csi4phytimer_clk_src", 830 .parent_data = cam_cc_parent_data_0, 831 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 832 .flags = CLK_SET_RATE_PARENT, 833 .ops = &clk_rcg2_shared_ops, 834 }, 835 }; 836 837 static struct clk_rcg2 cam_cc_csi5phytimer_clk_src = { 838 .cmd_rcgr = 0x200a4, 839 .mnd_width = 0, 840 .hid_width = 5, 841 .parent_map = cam_cc_parent_map_0, 842 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, 843 .clkr.hw.init = &(const struct clk_init_data) { 844 .name = "cam_cc_csi5phytimer_clk_src", 845 .parent_data = cam_cc_parent_data_0, 846 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 847 .flags = CLK_SET_RATE_PARENT, 848 .ops = &clk_rcg2_shared_ops, 849 }, 850 }; 851 852 static struct clk_rcg2 cam_cc_csid_clk_src = { 853 .cmd_rcgr = 0x212a4, 854 .mnd_width = 0, 855 .hid_width = 5, 856 .parent_map = cam_cc_parent_map_0, 857 .freq_tbl = ftbl_cam_cc_cphy_rx_clk_src, 858 .clkr.hw.init = &(const struct clk_init_data) { 859 .name = "cam_cc_csid_clk_src", 860 .parent_data = cam_cc_parent_data_0, 861 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 862 .flags = CLK_SET_RATE_PARENT, 863 .ops = &clk_rcg2_shared_ops, 864 }, 865 }; 866 867 static const struct freq_tbl ftbl_cam_cc_fast_ahb_clk_src[] = { 868 F(213333333, P_CAM_CC_PLL6_OUT_ODD, 1.5, 0, 0), 869 F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0), 870 F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0), 871 { } 872 }; 873 874 static struct clk_rcg2 cam_cc_fast_ahb_clk_src = { 875 .cmd_rcgr = 0x200dc, 876 .mnd_width = 0, 877 .hid_width = 5, 878 .parent_map = cam_cc_parent_map_1, 879 .freq_tbl = ftbl_cam_cc_fast_ahb_clk_src, 880 .clkr.hw.init = &(const struct clk_init_data) { 881 .name = "cam_cc_fast_ahb_clk_src", 882 .parent_data = cam_cc_parent_data_1, 883 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 884 .flags = CLK_SET_RATE_PARENT, 885 .ops = &clk_rcg2_shared_ops, 886 }, 887 }; 888 889 static const struct freq_tbl ftbl_cam_cc_icp_0_clk_src[] = { 890 F(500000000, P_CAM_CC_PLL7_OUT_EVEN, 1, 0, 0), 891 F(600000000, P_CAM_CC_PLL7_OUT_EVEN, 1, 0, 0), 892 F(740000000, P_CAM_CC_PLL7_OUT_EVEN, 1, 0, 0), 893 F(875000000, P_CAM_CC_PLL7_OUT_EVEN, 1, 0, 0), 894 F(1000000000, P_CAM_CC_PLL7_OUT_EVEN, 1, 0, 0), 895 { } 896 }; 897 898 static struct clk_rcg2 cam_cc_icp_0_clk_src = { 899 .cmd_rcgr = 0x211f8, 900 .mnd_width = 0, 901 .hid_width = 5, 902 .parent_map = cam_cc_parent_map_2, 903 .freq_tbl = ftbl_cam_cc_icp_0_clk_src, 904 .clkr.hw.init = &(const struct clk_init_data) { 905 .name = "cam_cc_icp_0_clk_src", 906 .parent_data = cam_cc_parent_data_2, 907 .num_parents = ARRAY_SIZE(cam_cc_parent_data_2), 908 .flags = CLK_SET_RATE_PARENT, 909 .ops = &clk_rcg2_shared_ops, 910 }, 911 }; 912 913 static struct clk_rcg2 cam_cc_icp_1_clk_src = { 914 .cmd_rcgr = 0x21220, 915 .mnd_width = 0, 916 .hid_width = 5, 917 .parent_map = cam_cc_parent_map_2, 918 .freq_tbl = ftbl_cam_cc_icp_0_clk_src, 919 .clkr.hw.init = &(const struct clk_init_data) { 920 .name = "cam_cc_icp_1_clk_src", 921 .parent_data = cam_cc_parent_data_2, 922 .num_parents = ARRAY_SIZE(cam_cc_parent_data_2), 923 .flags = CLK_SET_RATE_PARENT, 924 .ops = &clk_rcg2_shared_ops, 925 }, 926 }; 927 928 static struct clk_rcg2 cam_cc_ife_lite_clk_src = { 929 .cmd_rcgr = 0x21144, 930 .mnd_width = 0, 931 .hid_width = 5, 932 .parent_map = cam_cc_parent_map_0, 933 .freq_tbl = ftbl_cam_cc_cphy_rx_clk_src, 934 .clkr.hw.init = &(const struct clk_init_data) { 935 .name = "cam_cc_ife_lite_clk_src", 936 .parent_data = cam_cc_parent_data_0, 937 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 938 .flags = CLK_SET_RATE_PARENT, 939 .ops = &clk_rcg2_shared_ops, 940 }, 941 }; 942 943 static struct clk_rcg2 cam_cc_ife_lite_csid_clk_src = { 944 .cmd_rcgr = 0x21170, 945 .mnd_width = 0, 946 .hid_width = 5, 947 .parent_map = cam_cc_parent_map_0, 948 .freq_tbl = ftbl_cam_cc_cphy_rx_clk_src, 949 .clkr.hw.init = &(const struct clk_init_data) { 950 .name = "cam_cc_ife_lite_csid_clk_src", 951 .parent_data = cam_cc_parent_data_0, 952 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 953 .flags = CLK_SET_RATE_PARENT, 954 .ops = &clk_rcg2_shared_ops, 955 }, 956 }; 957 958 static const struct freq_tbl ftbl_cam_cc_ipe_nps_clk_src[] = { 959 F(332500000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), 960 F(475000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), 961 F(575000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), 962 F(675000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), 963 F(825000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), 964 { } 965 }; 966 967 static struct clk_rcg2 cam_cc_ipe_nps_clk_src = { 968 .cmd_rcgr = 0x20188, 969 .mnd_width = 0, 970 .hid_width = 5, 971 .parent_map = cam_cc_parent_map_3, 972 .freq_tbl = ftbl_cam_cc_ipe_nps_clk_src, 973 .clkr.hw.init = &(const struct clk_init_data) { 974 .name = "cam_cc_ipe_nps_clk_src", 975 .parent_data = cam_cc_parent_data_3, 976 .num_parents = ARRAY_SIZE(cam_cc_parent_data_3), 977 .flags = CLK_SET_RATE_PARENT, 978 .ops = &clk_rcg2_shared_ops, 979 }, 980 }; 981 982 static struct clk_rcg2 cam_cc_jpeg_clk_src = { 983 .cmd_rcgr = 0x211c4, 984 .mnd_width = 0, 985 .hid_width = 5, 986 .parent_map = cam_cc_parent_map_1, 987 .freq_tbl = ftbl_cam_cc_cre_clk_src, 988 .clkr.hw.init = &(const struct clk_init_data) { 989 .name = "cam_cc_jpeg_clk_src", 990 .parent_data = cam_cc_parent_data_1, 991 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 992 .flags = CLK_SET_RATE_PARENT, 993 .ops = &clk_rcg2_shared_ops, 994 }, 995 }; 996 997 static const struct freq_tbl ftbl_cam_cc_ofe_clk_src[] = { 998 F(338800000, P_CAM_CC_PLL2_OUT_EVEN, 1, 0, 0), 999 F(484000000, P_CAM_CC_PLL2_OUT_EVEN, 1, 0, 0), 1000 F(586000000, P_CAM_CC_PLL2_OUT_EVEN, 1, 0, 0), 1001 F(688000000, P_CAM_CC_PLL2_OUT_EVEN, 1, 0, 0), 1002 F(841000000, P_CAM_CC_PLL2_OUT_EVEN, 1, 0, 0), 1003 { } 1004 }; 1005 1006 static struct clk_rcg2 cam_cc_ofe_clk_src = { 1007 .cmd_rcgr = 0x2011c, 1008 .mnd_width = 0, 1009 .hid_width = 5, 1010 .parent_map = cam_cc_parent_map_4, 1011 .freq_tbl = ftbl_cam_cc_ofe_clk_src, 1012 .clkr.hw.init = &(const struct clk_init_data) { 1013 .name = "cam_cc_ofe_clk_src", 1014 .parent_data = cam_cc_parent_data_4, 1015 .num_parents = ARRAY_SIZE(cam_cc_parent_data_4), 1016 .flags = CLK_SET_RATE_PARENT, 1017 .ops = &clk_rcg2_shared_ops, 1018 }, 1019 }; 1020 1021 static const struct freq_tbl ftbl_cam_cc_qdss_debug_clk_src[] = { 1022 F(40000000, P_CAM_CC_PLL6_OUT_ODD, 8, 0, 0), 1023 F(60000000, P_CAM_CC_PLL6_OUT_EVEN, 8, 0, 0), 1024 F(120000000, P_CAM_CC_PLL0_OUT_EVEN, 5, 0, 0), 1025 F(240000000, P_CAM_CC_PLL0_OUT_MAIN, 5, 0, 0), 1026 { } 1027 }; 1028 1029 static struct clk_rcg2 cam_cc_qdss_debug_clk_src = { 1030 .cmd_rcgr = 0x21314, 1031 .mnd_width = 0, 1032 .hid_width = 5, 1033 .parent_map = cam_cc_parent_map_1, 1034 .freq_tbl = ftbl_cam_cc_qdss_debug_clk_src, 1035 .clkr.hw.init = &(const struct clk_init_data) { 1036 .name = "cam_cc_qdss_debug_clk_src", 1037 .parent_data = cam_cc_parent_data_1, 1038 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 1039 .flags = CLK_SET_RATE_PARENT, 1040 .ops = &clk_rcg2_shared_ops, 1041 }, 1042 }; 1043 1044 static const struct freq_tbl ftbl_cam_cc_slow_ahb_clk_src[] = { 1045 F(56470588, P_CAM_CC_PLL6_OUT_EVEN, 8.5, 0, 0), 1046 F(80000000, P_CAM_CC_PLL0_OUT_EVEN, 7.5, 0, 0), 1047 { } 1048 }; 1049 1050 static struct clk_rcg2 cam_cc_slow_ahb_clk_src = { 1051 .cmd_rcgr = 0x20100, 1052 .mnd_width = 0, 1053 .hid_width = 5, 1054 .parent_map = cam_cc_parent_map_1, 1055 .freq_tbl = ftbl_cam_cc_slow_ahb_clk_src, 1056 .clkr.hw.init = &(const struct clk_init_data) { 1057 .name = "cam_cc_slow_ahb_clk_src", 1058 .parent_data = cam_cc_parent_data_1, 1059 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 1060 .flags = CLK_SET_RATE_PARENT, 1061 .ops = &clk_rcg2_shared_ops, 1062 }, 1063 }; 1064 1065 static const struct freq_tbl ftbl_cam_cc_tfe_0_clk_src[] = { 1066 F(360280000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), 1067 F(480000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), 1068 F(630000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), 1069 F(716000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), 1070 F(833000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), 1071 { } 1072 }; 1073 1074 static struct clk_rcg2 cam_cc_tfe_0_clk_src = { 1075 .cmd_rcgr = 0x21018, 1076 .mnd_width = 0, 1077 .hid_width = 5, 1078 .parent_map = cam_cc_parent_map_5, 1079 .freq_tbl = ftbl_cam_cc_tfe_0_clk_src, 1080 .clkr.hw.init = &(const struct clk_init_data) { 1081 .name = "cam_cc_tfe_0_clk_src", 1082 .parent_data = cam_cc_parent_data_5, 1083 .num_parents = ARRAY_SIZE(cam_cc_parent_data_5), 1084 .flags = CLK_SET_RATE_PARENT, 1085 .ops = &clk_rcg2_shared_ops, 1086 }, 1087 }; 1088 1089 static const struct freq_tbl ftbl_cam_cc_tfe_1_clk_src[] = { 1090 F(360280000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), 1091 F(480000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), 1092 F(630000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), 1093 F(716000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), 1094 F(833000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), 1095 { } 1096 }; 1097 1098 static struct clk_rcg2 cam_cc_tfe_1_clk_src = { 1099 .cmd_rcgr = 0x21094, 1100 .mnd_width = 0, 1101 .hid_width = 5, 1102 .parent_map = cam_cc_parent_map_6, 1103 .freq_tbl = ftbl_cam_cc_tfe_1_clk_src, 1104 .clkr.hw.init = &(const struct clk_init_data) { 1105 .name = "cam_cc_tfe_1_clk_src", 1106 .parent_data = cam_cc_parent_data_6, 1107 .num_parents = ARRAY_SIZE(cam_cc_parent_data_6), 1108 .flags = CLK_SET_RATE_PARENT, 1109 .ops = &clk_rcg2_shared_ops, 1110 }, 1111 }; 1112 1113 static const struct freq_tbl ftbl_cam_cc_tfe_2_clk_src[] = { 1114 F(360280000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0), 1115 F(480000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0), 1116 F(630000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0), 1117 F(716000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0), 1118 F(833000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0), 1119 { } 1120 }; 1121 1122 static struct clk_rcg2 cam_cc_tfe_2_clk_src = { 1123 .cmd_rcgr = 0x210f8, 1124 .mnd_width = 0, 1125 .hid_width = 5, 1126 .parent_map = cam_cc_parent_map_7, 1127 .freq_tbl = ftbl_cam_cc_tfe_2_clk_src, 1128 .clkr.hw.init = &(const struct clk_init_data) { 1129 .name = "cam_cc_tfe_2_clk_src", 1130 .parent_data = cam_cc_parent_data_7, 1131 .num_parents = ARRAY_SIZE(cam_cc_parent_data_7), 1132 .flags = CLK_SET_RATE_PARENT, 1133 .ops = &clk_rcg2_shared_ops, 1134 }, 1135 }; 1136 1137 static const struct freq_tbl ftbl_cam_cc_xo_clk_src[] = { 1138 F(19200000, P_BI_TCXO, 1, 0, 0), 1139 { } 1140 }; 1141 1142 static struct clk_rcg2 cam_cc_xo_clk_src = { 1143 .cmd_rcgr = 0x2134c, 1144 .mnd_width = 0, 1145 .hid_width = 5, 1146 .parent_map = cam_cc_parent_map_8, 1147 .freq_tbl = ftbl_cam_cc_xo_clk_src, 1148 .clkr.hw.init = &(const struct clk_init_data) { 1149 .name = "cam_cc_xo_clk_src", 1150 .parent_data = cam_cc_parent_data_8, 1151 .num_parents = ARRAY_SIZE(cam_cc_parent_data_8), 1152 .flags = CLK_SET_RATE_PARENT, 1153 .ops = &clk_rcg2_ops, 1154 }, 1155 }; 1156 1157 static struct clk_branch cam_cc_cam_top_ahb_clk = { 1158 .halt_reg = 0x2137c, 1159 .halt_check = BRANCH_HALT, 1160 .clkr = { 1161 .enable_reg = 0x2137c, 1162 .enable_mask = BIT(0), 1163 .hw.init = &(const struct clk_init_data) { 1164 .name = "cam_cc_cam_top_ahb_clk", 1165 .parent_hws = (const struct clk_hw*[]) { 1166 &cam_cc_slow_ahb_clk_src.clkr.hw, 1167 }, 1168 .num_parents = 1, 1169 .flags = CLK_SET_RATE_PARENT, 1170 .ops = &clk_branch2_ops, 1171 }, 1172 }, 1173 }; 1174 1175 static struct clk_branch cam_cc_cam_top_fast_ahb_clk = { 1176 .halt_reg = 0x2136c, 1177 .halt_check = BRANCH_HALT, 1178 .clkr = { 1179 .enable_reg = 0x2136c, 1180 .enable_mask = BIT(0), 1181 .hw.init = &(const struct clk_init_data) { 1182 .name = "cam_cc_cam_top_fast_ahb_clk", 1183 .parent_hws = (const struct clk_hw*[]) { 1184 &cam_cc_fast_ahb_clk_src.clkr.hw, 1185 }, 1186 .num_parents = 1, 1187 .flags = CLK_SET_RATE_PARENT, 1188 .ops = &clk_branch2_ops, 1189 }, 1190 }, 1191 }; 1192 1193 static struct clk_branch cam_cc_camnoc_nrt_axi_clk = { 1194 .halt_reg = 0x212f8, 1195 .halt_check = BRANCH_HALT, 1196 .clkr = { 1197 .enable_reg = 0x212f8, 1198 .enable_mask = BIT(0), 1199 .hw.init = &(const struct clk_init_data) { 1200 .name = "cam_cc_camnoc_nrt_axi_clk", 1201 .parent_hws = (const struct clk_hw*[]) { 1202 &cam_cc_camnoc_rt_axi_clk_src.clkr.hw, 1203 }, 1204 .num_parents = 1, 1205 .flags = CLK_SET_RATE_PARENT, 1206 .ops = &clk_branch2_ops, 1207 }, 1208 }, 1209 }; 1210 1211 static struct clk_branch cam_cc_camnoc_nrt_cre_clk = { 1212 .halt_reg = 0x211bc, 1213 .halt_check = BRANCH_HALT, 1214 .clkr = { 1215 .enable_reg = 0x211bc, 1216 .enable_mask = BIT(0), 1217 .hw.init = &(const struct clk_init_data) { 1218 .name = "cam_cc_camnoc_nrt_cre_clk", 1219 .parent_hws = (const struct clk_hw*[]) { 1220 &cam_cc_cre_clk_src.clkr.hw, 1221 }, 1222 .num_parents = 1, 1223 .flags = CLK_SET_RATE_PARENT, 1224 .ops = &clk_branch2_ops, 1225 }, 1226 }, 1227 }; 1228 1229 static struct clk_branch cam_cc_camnoc_nrt_ipe_nps_clk = { 1230 .halt_reg = 0x201b0, 1231 .halt_check = BRANCH_HALT, 1232 .clkr = { 1233 .enable_reg = 0x201b0, 1234 .enable_mask = BIT(0), 1235 .hw.init = &(const struct clk_init_data) { 1236 .name = "cam_cc_camnoc_nrt_ipe_nps_clk", 1237 .parent_hws = (const struct clk_hw*[]) { 1238 &cam_cc_ipe_nps_clk_src.clkr.hw, 1239 }, 1240 .num_parents = 1, 1241 .flags = CLK_SET_RATE_PARENT, 1242 .ops = &clk_branch2_ops, 1243 }, 1244 }, 1245 }; 1246 1247 static struct clk_branch cam_cc_camnoc_nrt_ofe_main_clk = { 1248 .halt_reg = 0x20144, 1249 .halt_check = BRANCH_HALT, 1250 .clkr = { 1251 .enable_reg = 0x20144, 1252 .enable_mask = BIT(0), 1253 .hw.init = &(const struct clk_init_data) { 1254 .name = "cam_cc_camnoc_nrt_ofe_main_clk", 1255 .parent_hws = (const struct clk_hw*[]) { 1256 &cam_cc_ofe_clk_src.clkr.hw, 1257 }, 1258 .num_parents = 1, 1259 .flags = CLK_SET_RATE_PARENT, 1260 .ops = &clk_branch2_ops, 1261 }, 1262 }, 1263 }; 1264 1265 static struct clk_branch cam_cc_camnoc_rt_axi_clk = { 1266 .halt_reg = 0x212e4, 1267 .halt_check = BRANCH_HALT, 1268 .clkr = { 1269 .enable_reg = 0x212e4, 1270 .enable_mask = BIT(0), 1271 .hw.init = &(const struct clk_init_data) { 1272 .name = "cam_cc_camnoc_rt_axi_clk", 1273 .parent_hws = (const struct clk_hw*[]) { 1274 &cam_cc_camnoc_rt_axi_clk_src.clkr.hw, 1275 }, 1276 .num_parents = 1, 1277 .flags = CLK_SET_RATE_PARENT, 1278 .ops = &clk_branch2_ops, 1279 }, 1280 }, 1281 }; 1282 1283 static struct clk_branch cam_cc_camnoc_rt_ife_lite_clk = { 1284 .halt_reg = 0x2116c, 1285 .halt_check = BRANCH_HALT, 1286 .clkr = { 1287 .enable_reg = 0x2116c, 1288 .enable_mask = BIT(0), 1289 .hw.init = &(const struct clk_init_data) { 1290 .name = "cam_cc_camnoc_rt_ife_lite_clk", 1291 .parent_hws = (const struct clk_hw*[]) { 1292 &cam_cc_ife_lite_clk_src.clkr.hw, 1293 }, 1294 .num_parents = 1, 1295 .flags = CLK_SET_RATE_PARENT, 1296 .ops = &clk_branch2_ops, 1297 }, 1298 }, 1299 }; 1300 1301 static struct clk_branch cam_cc_camnoc_rt_tfe_0_main_clk = { 1302 .halt_reg = 0x21040, 1303 .halt_check = BRANCH_HALT, 1304 .clkr = { 1305 .enable_reg = 0x21040, 1306 .enable_mask = BIT(0), 1307 .hw.init = &(const struct clk_init_data) { 1308 .name = "cam_cc_camnoc_rt_tfe_0_main_clk", 1309 .parent_hws = (const struct clk_hw*[]) { 1310 &cam_cc_tfe_0_clk_src.clkr.hw, 1311 }, 1312 .num_parents = 1, 1313 .flags = CLK_SET_RATE_PARENT, 1314 .ops = &clk_branch2_ops, 1315 }, 1316 }, 1317 }; 1318 1319 static struct clk_branch cam_cc_camnoc_rt_tfe_1_main_clk = { 1320 .halt_reg = 0x210bc, 1321 .halt_check = BRANCH_HALT, 1322 .clkr = { 1323 .enable_reg = 0x210bc, 1324 .enable_mask = BIT(0), 1325 .hw.init = &(const struct clk_init_data) { 1326 .name = "cam_cc_camnoc_rt_tfe_1_main_clk", 1327 .parent_hws = (const struct clk_hw*[]) { 1328 &cam_cc_tfe_1_clk_src.clkr.hw, 1329 }, 1330 .num_parents = 1, 1331 .flags = CLK_SET_RATE_PARENT, 1332 .ops = &clk_branch2_ops, 1333 }, 1334 }, 1335 }; 1336 1337 static struct clk_branch cam_cc_camnoc_rt_tfe_2_main_clk = { 1338 .halt_reg = 0x21120, 1339 .halt_check = BRANCH_HALT, 1340 .clkr = { 1341 .enable_reg = 0x21120, 1342 .enable_mask = BIT(0), 1343 .hw.init = &(const struct clk_init_data) { 1344 .name = "cam_cc_camnoc_rt_tfe_2_main_clk", 1345 .parent_hws = (const struct clk_hw*[]) { 1346 &cam_cc_tfe_2_clk_src.clkr.hw, 1347 }, 1348 .num_parents = 1, 1349 .flags = CLK_SET_RATE_PARENT, 1350 .ops = &clk_branch2_ops, 1351 }, 1352 }, 1353 }; 1354 1355 static struct clk_branch cam_cc_camnoc_xo_clk = { 1356 .halt_reg = 0x2130c, 1357 .halt_check = BRANCH_HALT, 1358 .clkr = { 1359 .enable_reg = 0x2130c, 1360 .enable_mask = BIT(0), 1361 .hw.init = &(const struct clk_init_data) { 1362 .name = "cam_cc_camnoc_xo_clk", 1363 .parent_hws = (const struct clk_hw*[]) { 1364 &cam_cc_xo_clk_src.clkr.hw, 1365 }, 1366 .num_parents = 1, 1367 .flags = CLK_SET_RATE_PARENT, 1368 .ops = &clk_branch2_ops, 1369 }, 1370 }, 1371 }; 1372 1373 static struct clk_branch cam_cc_cci_0_clk = { 1374 .halt_reg = 0x21268, 1375 .halt_check = BRANCH_HALT, 1376 .clkr = { 1377 .enable_reg = 0x21268, 1378 .enable_mask = BIT(0), 1379 .hw.init = &(const struct clk_init_data) { 1380 .name = "cam_cc_cci_0_clk", 1381 .parent_hws = (const struct clk_hw*[]) { 1382 &cam_cc_cci_0_clk_src.clkr.hw, 1383 }, 1384 .num_parents = 1, 1385 .flags = CLK_SET_RATE_PARENT, 1386 .ops = &clk_branch2_ops, 1387 }, 1388 }, 1389 }; 1390 1391 static struct clk_branch cam_cc_cci_1_clk = { 1392 .halt_reg = 0x21284, 1393 .halt_check = BRANCH_HALT, 1394 .clkr = { 1395 .enable_reg = 0x21284, 1396 .enable_mask = BIT(0), 1397 .hw.init = &(const struct clk_init_data) { 1398 .name = "cam_cc_cci_1_clk", 1399 .parent_hws = (const struct clk_hw*[]) { 1400 &cam_cc_cci_1_clk_src.clkr.hw, 1401 }, 1402 .num_parents = 1, 1403 .flags = CLK_SET_RATE_PARENT, 1404 .ops = &clk_branch2_ops, 1405 }, 1406 }, 1407 }; 1408 1409 static struct clk_branch cam_cc_cci_2_clk = { 1410 .halt_reg = 0x212a0, 1411 .halt_check = BRANCH_HALT, 1412 .clkr = { 1413 .enable_reg = 0x212a0, 1414 .enable_mask = BIT(0), 1415 .hw.init = &(const struct clk_init_data) { 1416 .name = "cam_cc_cci_2_clk", 1417 .parent_hws = (const struct clk_hw*[]) { 1418 &cam_cc_cci_2_clk_src.clkr.hw, 1419 }, 1420 .num_parents = 1, 1421 .flags = CLK_SET_RATE_PARENT, 1422 .ops = &clk_branch2_ops, 1423 }, 1424 }, 1425 }; 1426 1427 static struct clk_branch cam_cc_core_ahb_clk = { 1428 .halt_reg = 0x21348, 1429 .halt_check = BRANCH_HALT_DELAY, 1430 .clkr = { 1431 .enable_reg = 0x21348, 1432 .enable_mask = BIT(0), 1433 .hw.init = &(const struct clk_init_data) { 1434 .name = "cam_cc_core_ahb_clk", 1435 .parent_hws = (const struct clk_hw*[]) { 1436 &cam_cc_slow_ahb_clk_src.clkr.hw, 1437 }, 1438 .num_parents = 1, 1439 .flags = CLK_SET_RATE_PARENT, 1440 .ops = &clk_branch2_ops, 1441 }, 1442 }, 1443 }; 1444 1445 static struct clk_branch cam_cc_cre_ahb_clk = { 1446 .halt_reg = 0x211c0, 1447 .halt_check = BRANCH_HALT, 1448 .clkr = { 1449 .enable_reg = 0x211c0, 1450 .enable_mask = BIT(0), 1451 .hw.init = &(const struct clk_init_data) { 1452 .name = "cam_cc_cre_ahb_clk", 1453 .parent_hws = (const struct clk_hw*[]) { 1454 &cam_cc_slow_ahb_clk_src.clkr.hw, 1455 }, 1456 .num_parents = 1, 1457 .flags = CLK_SET_RATE_PARENT, 1458 .ops = &clk_branch2_ops, 1459 }, 1460 }, 1461 }; 1462 1463 static struct clk_branch cam_cc_cre_clk = { 1464 .halt_reg = 0x211b8, 1465 .halt_check = BRANCH_HALT, 1466 .clkr = { 1467 .enable_reg = 0x211b8, 1468 .enable_mask = BIT(0), 1469 .hw.init = &(const struct clk_init_data) { 1470 .name = "cam_cc_cre_clk", 1471 .parent_hws = (const struct clk_hw*[]) { 1472 &cam_cc_cre_clk_src.clkr.hw, 1473 }, 1474 .num_parents = 1, 1475 .flags = CLK_SET_RATE_PARENT, 1476 .ops = &clk_branch2_ops, 1477 }, 1478 }, 1479 }; 1480 1481 static struct clk_branch cam_cc_csi0phytimer_clk = { 1482 .halt_reg = 0x20018, 1483 .halt_check = BRANCH_HALT, 1484 .clkr = { 1485 .enable_reg = 0x20018, 1486 .enable_mask = BIT(0), 1487 .hw.init = &(const struct clk_init_data) { 1488 .name = "cam_cc_csi0phytimer_clk", 1489 .parent_hws = (const struct clk_hw*[]) { 1490 &cam_cc_csi0phytimer_clk_src.clkr.hw, 1491 }, 1492 .num_parents = 1, 1493 .flags = CLK_SET_RATE_PARENT, 1494 .ops = &clk_branch2_ops, 1495 }, 1496 }, 1497 }; 1498 1499 static struct clk_branch cam_cc_csi1phytimer_clk = { 1500 .halt_reg = 0x2003c, 1501 .halt_check = BRANCH_HALT, 1502 .clkr = { 1503 .enable_reg = 0x2003c, 1504 .enable_mask = BIT(0), 1505 .hw.init = &(const struct clk_init_data) { 1506 .name = "cam_cc_csi1phytimer_clk", 1507 .parent_hws = (const struct clk_hw*[]) { 1508 &cam_cc_csi1phytimer_clk_src.clkr.hw, 1509 }, 1510 .num_parents = 1, 1511 .flags = CLK_SET_RATE_PARENT, 1512 .ops = &clk_branch2_ops, 1513 }, 1514 }, 1515 }; 1516 1517 static struct clk_branch cam_cc_csi2phytimer_clk = { 1518 .halt_reg = 0x2005c, 1519 .halt_check = BRANCH_HALT, 1520 .clkr = { 1521 .enable_reg = 0x2005c, 1522 .enable_mask = BIT(0), 1523 .hw.init = &(const struct clk_init_data) { 1524 .name = "cam_cc_csi2phytimer_clk", 1525 .parent_hws = (const struct clk_hw*[]) { 1526 &cam_cc_csi2phytimer_clk_src.clkr.hw, 1527 }, 1528 .num_parents = 1, 1529 .flags = CLK_SET_RATE_PARENT, 1530 .ops = &clk_branch2_ops, 1531 }, 1532 }, 1533 }; 1534 1535 static struct clk_branch cam_cc_csi3phytimer_clk = { 1536 .halt_reg = 0x2007c, 1537 .halt_check = BRANCH_HALT, 1538 .clkr = { 1539 .enable_reg = 0x2007c, 1540 .enable_mask = BIT(0), 1541 .hw.init = &(const struct clk_init_data) { 1542 .name = "cam_cc_csi3phytimer_clk", 1543 .parent_hws = (const struct clk_hw*[]) { 1544 &cam_cc_csi3phytimer_clk_src.clkr.hw, 1545 }, 1546 .num_parents = 1, 1547 .flags = CLK_SET_RATE_PARENT, 1548 .ops = &clk_branch2_ops, 1549 }, 1550 }, 1551 }; 1552 1553 static struct clk_branch cam_cc_csi4phytimer_clk = { 1554 .halt_reg = 0x2009c, 1555 .halt_check = BRANCH_HALT, 1556 .clkr = { 1557 .enable_reg = 0x2009c, 1558 .enable_mask = BIT(0), 1559 .hw.init = &(const struct clk_init_data) { 1560 .name = "cam_cc_csi4phytimer_clk", 1561 .parent_hws = (const struct clk_hw*[]) { 1562 &cam_cc_csi4phytimer_clk_src.clkr.hw, 1563 }, 1564 .num_parents = 1, 1565 .flags = CLK_SET_RATE_PARENT, 1566 .ops = &clk_branch2_ops, 1567 }, 1568 }, 1569 }; 1570 1571 static struct clk_branch cam_cc_csi5phytimer_clk = { 1572 .halt_reg = 0x200bc, 1573 .halt_check = BRANCH_HALT, 1574 .clkr = { 1575 .enable_reg = 0x200bc, 1576 .enable_mask = BIT(0), 1577 .hw.init = &(const struct clk_init_data) { 1578 .name = "cam_cc_csi5phytimer_clk", 1579 .parent_hws = (const struct clk_hw*[]) { 1580 &cam_cc_csi5phytimer_clk_src.clkr.hw, 1581 }, 1582 .num_parents = 1, 1583 .flags = CLK_SET_RATE_PARENT, 1584 .ops = &clk_branch2_ops, 1585 }, 1586 }, 1587 }; 1588 1589 static struct clk_branch cam_cc_csid_clk = { 1590 .halt_reg = 0x212bc, 1591 .halt_check = BRANCH_HALT, 1592 .clkr = { 1593 .enable_reg = 0x212bc, 1594 .enable_mask = BIT(0), 1595 .hw.init = &(const struct clk_init_data) { 1596 .name = "cam_cc_csid_clk", 1597 .parent_hws = (const struct clk_hw*[]) { 1598 &cam_cc_csid_clk_src.clkr.hw, 1599 }, 1600 .num_parents = 1, 1601 .flags = CLK_SET_RATE_PARENT, 1602 .ops = &clk_branch2_ops, 1603 }, 1604 }, 1605 }; 1606 1607 static struct clk_branch cam_cc_csid_csiphy_rx_clk = { 1608 .halt_reg = 0x20020, 1609 .halt_check = BRANCH_HALT, 1610 .clkr = { 1611 .enable_reg = 0x20020, 1612 .enable_mask = BIT(0), 1613 .hw.init = &(const struct clk_init_data) { 1614 .name = "cam_cc_csid_csiphy_rx_clk", 1615 .parent_hws = (const struct clk_hw*[]) { 1616 &cam_cc_cphy_rx_clk_src.clkr.hw, 1617 }, 1618 .num_parents = 1, 1619 .flags = CLK_SET_RATE_PARENT, 1620 .ops = &clk_branch2_ops, 1621 }, 1622 }, 1623 }; 1624 1625 static struct clk_branch cam_cc_csiphy0_clk = { 1626 .halt_reg = 0x2001c, 1627 .halt_check = BRANCH_HALT, 1628 .clkr = { 1629 .enable_reg = 0x2001c, 1630 .enable_mask = BIT(0), 1631 .hw.init = &(const struct clk_init_data) { 1632 .name = "cam_cc_csiphy0_clk", 1633 .parent_hws = (const struct clk_hw*[]) { 1634 &cam_cc_cphy_rx_clk_src.clkr.hw, 1635 }, 1636 .num_parents = 1, 1637 .flags = CLK_SET_RATE_PARENT, 1638 .ops = &clk_branch2_ops, 1639 }, 1640 }, 1641 }; 1642 1643 static struct clk_branch cam_cc_csiphy1_clk = { 1644 .halt_reg = 0x20040, 1645 .halt_check = BRANCH_HALT, 1646 .clkr = { 1647 .enable_reg = 0x20040, 1648 .enable_mask = BIT(0), 1649 .hw.init = &(const struct clk_init_data) { 1650 .name = "cam_cc_csiphy1_clk", 1651 .parent_hws = (const struct clk_hw*[]) { 1652 &cam_cc_cphy_rx_clk_src.clkr.hw, 1653 }, 1654 .num_parents = 1, 1655 .flags = CLK_SET_RATE_PARENT, 1656 .ops = &clk_branch2_ops, 1657 }, 1658 }, 1659 }; 1660 1661 static struct clk_branch cam_cc_csiphy2_clk = { 1662 .halt_reg = 0x20060, 1663 .halt_check = BRANCH_HALT, 1664 .clkr = { 1665 .enable_reg = 0x20060, 1666 .enable_mask = BIT(0), 1667 .hw.init = &(const struct clk_init_data) { 1668 .name = "cam_cc_csiphy2_clk", 1669 .parent_hws = (const struct clk_hw*[]) { 1670 &cam_cc_cphy_rx_clk_src.clkr.hw, 1671 }, 1672 .num_parents = 1, 1673 .flags = CLK_SET_RATE_PARENT, 1674 .ops = &clk_branch2_ops, 1675 }, 1676 }, 1677 }; 1678 1679 static struct clk_branch cam_cc_csiphy3_clk = { 1680 .halt_reg = 0x20080, 1681 .halt_check = BRANCH_HALT, 1682 .clkr = { 1683 .enable_reg = 0x20080, 1684 .enable_mask = BIT(0), 1685 .hw.init = &(const struct clk_init_data) { 1686 .name = "cam_cc_csiphy3_clk", 1687 .parent_hws = (const struct clk_hw*[]) { 1688 &cam_cc_cphy_rx_clk_src.clkr.hw, 1689 }, 1690 .num_parents = 1, 1691 .flags = CLK_SET_RATE_PARENT, 1692 .ops = &clk_branch2_ops, 1693 }, 1694 }, 1695 }; 1696 1697 static struct clk_branch cam_cc_csiphy4_clk = { 1698 .halt_reg = 0x200a0, 1699 .halt_check = BRANCH_HALT, 1700 .clkr = { 1701 .enable_reg = 0x200a0, 1702 .enable_mask = BIT(0), 1703 .hw.init = &(const struct clk_init_data) { 1704 .name = "cam_cc_csiphy4_clk", 1705 .parent_hws = (const struct clk_hw*[]) { 1706 &cam_cc_cphy_rx_clk_src.clkr.hw, 1707 }, 1708 .num_parents = 1, 1709 .flags = CLK_SET_RATE_PARENT, 1710 .ops = &clk_branch2_ops, 1711 }, 1712 }, 1713 }; 1714 1715 static struct clk_branch cam_cc_csiphy5_clk = { 1716 .halt_reg = 0x200c0, 1717 .halt_check = BRANCH_HALT, 1718 .clkr = { 1719 .enable_reg = 0x200c0, 1720 .enable_mask = BIT(0), 1721 .hw.init = &(const struct clk_init_data) { 1722 .name = "cam_cc_csiphy5_clk", 1723 .parent_hws = (const struct clk_hw*[]) { 1724 &cam_cc_cphy_rx_clk_src.clkr.hw, 1725 }, 1726 .num_parents = 1, 1727 .flags = CLK_SET_RATE_PARENT, 1728 .ops = &clk_branch2_ops, 1729 }, 1730 }, 1731 }; 1732 1733 static struct clk_branch cam_cc_icp_0_ahb_clk = { 1734 .halt_reg = 0x21248, 1735 .halt_check = BRANCH_HALT, 1736 .clkr = { 1737 .enable_reg = 0x21248, 1738 .enable_mask = BIT(0), 1739 .hw.init = &(const struct clk_init_data) { 1740 .name = "cam_cc_icp_0_ahb_clk", 1741 .parent_hws = (const struct clk_hw*[]) { 1742 &cam_cc_slow_ahb_clk_src.clkr.hw, 1743 }, 1744 .num_parents = 1, 1745 .flags = CLK_SET_RATE_PARENT, 1746 .ops = &clk_branch2_ops, 1747 }, 1748 }, 1749 }; 1750 1751 static struct clk_branch cam_cc_icp_0_clk = { 1752 .halt_reg = 0x21210, 1753 .halt_check = BRANCH_HALT, 1754 .clkr = { 1755 .enable_reg = 0x21210, 1756 .enable_mask = BIT(0), 1757 .hw.init = &(const struct clk_init_data) { 1758 .name = "cam_cc_icp_0_clk", 1759 .parent_hws = (const struct clk_hw*[]) { 1760 &cam_cc_icp_0_clk_src.clkr.hw, 1761 }, 1762 .num_parents = 1, 1763 .flags = CLK_SET_RATE_PARENT, 1764 .ops = &clk_branch2_ops, 1765 }, 1766 }, 1767 }; 1768 1769 static struct clk_branch cam_cc_icp_1_ahb_clk = { 1770 .halt_reg = 0x2124c, 1771 .halt_check = BRANCH_HALT, 1772 .clkr = { 1773 .enable_reg = 0x2124c, 1774 .enable_mask = BIT(0), 1775 .hw.init = &(const struct clk_init_data) { 1776 .name = "cam_cc_icp_1_ahb_clk", 1777 .parent_hws = (const struct clk_hw*[]) { 1778 &cam_cc_slow_ahb_clk_src.clkr.hw, 1779 }, 1780 .num_parents = 1, 1781 .flags = CLK_SET_RATE_PARENT, 1782 .ops = &clk_branch2_ops, 1783 }, 1784 }, 1785 }; 1786 1787 static struct clk_branch cam_cc_icp_1_clk = { 1788 .halt_reg = 0x21238, 1789 .halt_check = BRANCH_HALT, 1790 .clkr = { 1791 .enable_reg = 0x21238, 1792 .enable_mask = BIT(0), 1793 .hw.init = &(const struct clk_init_data) { 1794 .name = "cam_cc_icp_1_clk", 1795 .parent_hws = (const struct clk_hw*[]) { 1796 &cam_cc_icp_1_clk_src.clkr.hw, 1797 }, 1798 .num_parents = 1, 1799 .flags = CLK_SET_RATE_PARENT, 1800 .ops = &clk_branch2_ops, 1801 }, 1802 }, 1803 }; 1804 1805 static struct clk_branch cam_cc_ife_lite_ahb_clk = { 1806 .halt_reg = 0x2119c, 1807 .halt_check = BRANCH_HALT, 1808 .clkr = { 1809 .enable_reg = 0x2119c, 1810 .enable_mask = BIT(0), 1811 .hw.init = &(const struct clk_init_data) { 1812 .name = "cam_cc_ife_lite_ahb_clk", 1813 .parent_hws = (const struct clk_hw*[]) { 1814 &cam_cc_slow_ahb_clk_src.clkr.hw, 1815 }, 1816 .num_parents = 1, 1817 .flags = CLK_SET_RATE_PARENT, 1818 .ops = &clk_branch2_ops, 1819 }, 1820 }, 1821 }; 1822 1823 static struct clk_branch cam_cc_ife_lite_clk = { 1824 .halt_reg = 0x2115c, 1825 .halt_check = BRANCH_HALT, 1826 .clkr = { 1827 .enable_reg = 0x2115c, 1828 .enable_mask = BIT(0), 1829 .hw.init = &(const struct clk_init_data) { 1830 .name = "cam_cc_ife_lite_clk", 1831 .parent_hws = (const struct clk_hw*[]) { 1832 &cam_cc_ife_lite_clk_src.clkr.hw, 1833 }, 1834 .num_parents = 1, 1835 .flags = CLK_SET_RATE_PARENT, 1836 .ops = &clk_branch2_ops, 1837 }, 1838 }, 1839 }; 1840 1841 static struct clk_branch cam_cc_ife_lite_cphy_rx_clk = { 1842 .halt_reg = 0x21198, 1843 .halt_check = BRANCH_HALT, 1844 .clkr = { 1845 .enable_reg = 0x21198, 1846 .enable_mask = BIT(0), 1847 .hw.init = &(const struct clk_init_data) { 1848 .name = "cam_cc_ife_lite_cphy_rx_clk", 1849 .parent_hws = (const struct clk_hw*[]) { 1850 &cam_cc_cphy_rx_clk_src.clkr.hw, 1851 }, 1852 .num_parents = 1, 1853 .flags = CLK_SET_RATE_PARENT, 1854 .ops = &clk_branch2_ops, 1855 }, 1856 }, 1857 }; 1858 1859 static struct clk_branch cam_cc_ife_lite_csid_clk = { 1860 .halt_reg = 0x21188, 1861 .halt_check = BRANCH_HALT, 1862 .clkr = { 1863 .enable_reg = 0x21188, 1864 .enable_mask = BIT(0), 1865 .hw.init = &(const struct clk_init_data) { 1866 .name = "cam_cc_ife_lite_csid_clk", 1867 .parent_hws = (const struct clk_hw*[]) { 1868 &cam_cc_ife_lite_csid_clk_src.clkr.hw, 1869 }, 1870 .num_parents = 1, 1871 .flags = CLK_SET_RATE_PARENT, 1872 .ops = &clk_branch2_ops, 1873 }, 1874 }, 1875 }; 1876 1877 static struct clk_branch cam_cc_ipe_nps_ahb_clk = { 1878 .halt_reg = 0x201cc, 1879 .halt_check = BRANCH_HALT, 1880 .clkr = { 1881 .enable_reg = 0x201cc, 1882 .enable_mask = BIT(0), 1883 .hw.init = &(const struct clk_init_data) { 1884 .name = "cam_cc_ipe_nps_ahb_clk", 1885 .parent_hws = (const struct clk_hw*[]) { 1886 &cam_cc_slow_ahb_clk_src.clkr.hw, 1887 }, 1888 .num_parents = 1, 1889 .flags = CLK_SET_RATE_PARENT, 1890 .ops = &clk_branch2_ops, 1891 }, 1892 }, 1893 }; 1894 1895 static struct clk_branch cam_cc_ipe_nps_clk = { 1896 .halt_reg = 0x201a0, 1897 .halt_check = BRANCH_HALT, 1898 .clkr = { 1899 .enable_reg = 0x201a0, 1900 .enable_mask = BIT(0), 1901 .hw.init = &(const struct clk_init_data) { 1902 .name = "cam_cc_ipe_nps_clk", 1903 .parent_hws = (const struct clk_hw*[]) { 1904 &cam_cc_ipe_nps_clk_src.clkr.hw, 1905 }, 1906 .num_parents = 1, 1907 .flags = CLK_SET_RATE_PARENT, 1908 .ops = &clk_branch2_ops, 1909 }, 1910 }, 1911 }; 1912 1913 static struct clk_branch cam_cc_ipe_nps_fast_ahb_clk = { 1914 .halt_reg = 0x201d0, 1915 .halt_check = BRANCH_HALT, 1916 .clkr = { 1917 .enable_reg = 0x201d0, 1918 .enable_mask = BIT(0), 1919 .hw.init = &(const struct clk_init_data) { 1920 .name = "cam_cc_ipe_nps_fast_ahb_clk", 1921 .parent_hws = (const struct clk_hw*[]) { 1922 &cam_cc_fast_ahb_clk_src.clkr.hw, 1923 }, 1924 .num_parents = 1, 1925 .flags = CLK_SET_RATE_PARENT, 1926 .ops = &clk_branch2_ops, 1927 }, 1928 }, 1929 }; 1930 1931 static struct clk_branch cam_cc_ipe_pps_clk = { 1932 .halt_reg = 0x201b4, 1933 .halt_check = BRANCH_HALT, 1934 .clkr = { 1935 .enable_reg = 0x201b4, 1936 .enable_mask = BIT(0), 1937 .hw.init = &(const struct clk_init_data) { 1938 .name = "cam_cc_ipe_pps_clk", 1939 .parent_hws = (const struct clk_hw*[]) { 1940 &cam_cc_ipe_nps_clk_src.clkr.hw, 1941 }, 1942 .num_parents = 1, 1943 .flags = CLK_SET_RATE_PARENT, 1944 .ops = &clk_branch2_ops, 1945 }, 1946 }, 1947 }; 1948 1949 static struct clk_branch cam_cc_ipe_pps_fast_ahb_clk = { 1950 .halt_reg = 0x201d4, 1951 .halt_check = BRANCH_HALT, 1952 .clkr = { 1953 .enable_reg = 0x201d4, 1954 .enable_mask = BIT(0), 1955 .hw.init = &(const struct clk_init_data) { 1956 .name = "cam_cc_ipe_pps_fast_ahb_clk", 1957 .parent_hws = (const struct clk_hw*[]) { 1958 &cam_cc_fast_ahb_clk_src.clkr.hw, 1959 }, 1960 .num_parents = 1, 1961 .flags = CLK_SET_RATE_PARENT, 1962 .ops = &clk_branch2_ops, 1963 }, 1964 }, 1965 }; 1966 1967 static struct clk_branch cam_cc_jpeg_clk = { 1968 .halt_reg = 0x211dc, 1969 .halt_check = BRANCH_HALT, 1970 .clkr = { 1971 .enable_reg = 0x211dc, 1972 .enable_mask = BIT(0), 1973 .hw.init = &(const struct clk_init_data) { 1974 .name = "cam_cc_jpeg_clk", 1975 .parent_hws = (const struct clk_hw*[]) { 1976 &cam_cc_jpeg_clk_src.clkr.hw, 1977 }, 1978 .num_parents = 1, 1979 .flags = CLK_SET_RATE_PARENT, 1980 .ops = &clk_branch2_ops, 1981 }, 1982 }, 1983 }; 1984 1985 static struct clk_branch cam_cc_ofe_ahb_clk = { 1986 .halt_reg = 0x20118, 1987 .halt_check = BRANCH_HALT, 1988 .clkr = { 1989 .enable_reg = 0x20118, 1990 .enable_mask = BIT(0), 1991 .hw.init = &(const struct clk_init_data) { 1992 .name = "cam_cc_ofe_ahb_clk", 1993 .parent_hws = (const struct clk_hw*[]) { 1994 &cam_cc_slow_ahb_clk_src.clkr.hw, 1995 }, 1996 .num_parents = 1, 1997 .flags = CLK_SET_RATE_PARENT, 1998 .ops = &clk_branch2_ops, 1999 }, 2000 }, 2001 }; 2002 2003 static struct clk_branch cam_cc_ofe_anchor_clk = { 2004 .halt_reg = 0x20148, 2005 .halt_check = BRANCH_HALT, 2006 .clkr = { 2007 .enable_reg = 0x20148, 2008 .enable_mask = BIT(0), 2009 .hw.init = &(const struct clk_init_data) { 2010 .name = "cam_cc_ofe_anchor_clk", 2011 .parent_hws = (const struct clk_hw*[]) { 2012 &cam_cc_ofe_clk_src.clkr.hw, 2013 }, 2014 .num_parents = 1, 2015 .flags = CLK_SET_RATE_PARENT, 2016 .ops = &clk_branch2_ops, 2017 }, 2018 }, 2019 }; 2020 2021 static struct clk_branch cam_cc_ofe_anchor_fast_ahb_clk = { 2022 .halt_reg = 0x200f8, 2023 .halt_check = BRANCH_HALT, 2024 .clkr = { 2025 .enable_reg = 0x200f8, 2026 .enable_mask = BIT(0), 2027 .hw.init = &(const struct clk_init_data) { 2028 .name = "cam_cc_ofe_anchor_fast_ahb_clk", 2029 .parent_hws = (const struct clk_hw*[]) { 2030 &cam_cc_fast_ahb_clk_src.clkr.hw, 2031 }, 2032 .num_parents = 1, 2033 .flags = CLK_SET_RATE_PARENT, 2034 .ops = &clk_branch2_ops, 2035 }, 2036 }, 2037 }; 2038 2039 static struct clk_branch cam_cc_ofe_hdr_clk = { 2040 .halt_reg = 0x20158, 2041 .halt_check = BRANCH_HALT, 2042 .clkr = { 2043 .enable_reg = 0x20158, 2044 .enable_mask = BIT(0), 2045 .hw.init = &(const struct clk_init_data) { 2046 .name = "cam_cc_ofe_hdr_clk", 2047 .parent_hws = (const struct clk_hw*[]) { 2048 &cam_cc_ofe_clk_src.clkr.hw, 2049 }, 2050 .num_parents = 1, 2051 .flags = CLK_SET_RATE_PARENT, 2052 .ops = &clk_branch2_ops, 2053 }, 2054 }, 2055 }; 2056 2057 static struct clk_branch cam_cc_ofe_hdr_fast_ahb_clk = { 2058 .halt_reg = 0x200fc, 2059 .halt_check = BRANCH_HALT, 2060 .clkr = { 2061 .enable_reg = 0x200fc, 2062 .enable_mask = BIT(0), 2063 .hw.init = &(const struct clk_init_data) { 2064 .name = "cam_cc_ofe_hdr_fast_ahb_clk", 2065 .parent_hws = (const struct clk_hw*[]) { 2066 &cam_cc_fast_ahb_clk_src.clkr.hw, 2067 }, 2068 .num_parents = 1, 2069 .flags = CLK_SET_RATE_PARENT, 2070 .ops = &clk_branch2_ops, 2071 }, 2072 }, 2073 }; 2074 2075 static struct clk_branch cam_cc_ofe_main_clk = { 2076 .halt_reg = 0x20134, 2077 .halt_check = BRANCH_HALT, 2078 .clkr = { 2079 .enable_reg = 0x20134, 2080 .enable_mask = BIT(0), 2081 .hw.init = &(const struct clk_init_data) { 2082 .name = "cam_cc_ofe_main_clk", 2083 .parent_hws = (const struct clk_hw*[]) { 2084 &cam_cc_ofe_clk_src.clkr.hw, 2085 }, 2086 .num_parents = 1, 2087 .flags = CLK_SET_RATE_PARENT, 2088 .ops = &clk_branch2_ops, 2089 }, 2090 }, 2091 }; 2092 2093 static struct clk_branch cam_cc_ofe_main_fast_ahb_clk = { 2094 .halt_reg = 0x200f4, 2095 .halt_check = BRANCH_HALT, 2096 .clkr = { 2097 .enable_reg = 0x200f4, 2098 .enable_mask = BIT(0), 2099 .hw.init = &(const struct clk_init_data) { 2100 .name = "cam_cc_ofe_main_fast_ahb_clk", 2101 .parent_hws = (const struct clk_hw*[]) { 2102 &cam_cc_fast_ahb_clk_src.clkr.hw, 2103 }, 2104 .num_parents = 1, 2105 .flags = CLK_SET_RATE_PARENT, 2106 .ops = &clk_branch2_ops, 2107 }, 2108 }, 2109 }; 2110 2111 static struct clk_branch cam_cc_qdss_debug_clk = { 2112 .halt_reg = 0x2132c, 2113 .halt_check = BRANCH_HALT, 2114 .clkr = { 2115 .enable_reg = 0x2132c, 2116 .enable_mask = BIT(0), 2117 .hw.init = &(const struct clk_init_data) { 2118 .name = "cam_cc_qdss_debug_clk", 2119 .parent_hws = (const struct clk_hw*[]) { 2120 &cam_cc_qdss_debug_clk_src.clkr.hw, 2121 }, 2122 .num_parents = 1, 2123 .flags = CLK_SET_RATE_PARENT, 2124 .ops = &clk_branch2_ops, 2125 }, 2126 }, 2127 }; 2128 2129 static struct clk_branch cam_cc_qdss_debug_xo_clk = { 2130 .halt_reg = 0x21330, 2131 .halt_check = BRANCH_HALT, 2132 .clkr = { 2133 .enable_reg = 0x21330, 2134 .enable_mask = BIT(0), 2135 .hw.init = &(const struct clk_init_data) { 2136 .name = "cam_cc_qdss_debug_xo_clk", 2137 .parent_hws = (const struct clk_hw*[]) { 2138 &cam_cc_xo_clk_src.clkr.hw, 2139 }, 2140 .num_parents = 1, 2141 .flags = CLK_SET_RATE_PARENT, 2142 .ops = &clk_branch2_ops, 2143 }, 2144 }, 2145 }; 2146 2147 static struct clk_branch cam_cc_tfe_0_bayer_clk = { 2148 .halt_reg = 0x21044, 2149 .halt_check = BRANCH_HALT, 2150 .clkr = { 2151 .enable_reg = 0x21044, 2152 .enable_mask = BIT(0), 2153 .hw.init = &(const struct clk_init_data) { 2154 .name = "cam_cc_tfe_0_bayer_clk", 2155 .parent_hws = (const struct clk_hw*[]) { 2156 &cam_cc_tfe_0_clk_src.clkr.hw, 2157 }, 2158 .num_parents = 1, 2159 .flags = CLK_SET_RATE_PARENT, 2160 .ops = &clk_branch2_ops, 2161 }, 2162 }, 2163 }; 2164 2165 static struct clk_branch cam_cc_tfe_0_bayer_fast_ahb_clk = { 2166 .halt_reg = 0x21060, 2167 .halt_check = BRANCH_HALT, 2168 .clkr = { 2169 .enable_reg = 0x21060, 2170 .enable_mask = BIT(0), 2171 .hw.init = &(const struct clk_init_data) { 2172 .name = "cam_cc_tfe_0_bayer_fast_ahb_clk", 2173 .parent_hws = (const struct clk_hw*[]) { 2174 &cam_cc_fast_ahb_clk_src.clkr.hw, 2175 }, 2176 .num_parents = 1, 2177 .flags = CLK_SET_RATE_PARENT, 2178 .ops = &clk_branch2_ops, 2179 }, 2180 }, 2181 }; 2182 2183 static struct clk_branch cam_cc_tfe_0_main_clk = { 2184 .halt_reg = 0x21030, 2185 .halt_check = BRANCH_HALT, 2186 .clkr = { 2187 .enable_reg = 0x21030, 2188 .enable_mask = BIT(0), 2189 .hw.init = &(const struct clk_init_data) { 2190 .name = "cam_cc_tfe_0_main_clk", 2191 .parent_hws = (const struct clk_hw*[]) { 2192 &cam_cc_tfe_0_clk_src.clkr.hw, 2193 }, 2194 .num_parents = 1, 2195 .flags = CLK_SET_RATE_PARENT, 2196 .ops = &clk_branch2_ops, 2197 }, 2198 }, 2199 }; 2200 2201 static struct clk_branch cam_cc_tfe_0_main_fast_ahb_clk = { 2202 .halt_reg = 0x2105c, 2203 .halt_check = BRANCH_HALT, 2204 .clkr = { 2205 .enable_reg = 0x2105c, 2206 .enable_mask = BIT(0), 2207 .hw.init = &(const struct clk_init_data) { 2208 .name = "cam_cc_tfe_0_main_fast_ahb_clk", 2209 .parent_hws = (const struct clk_hw*[]) { 2210 &cam_cc_fast_ahb_clk_src.clkr.hw, 2211 }, 2212 .num_parents = 1, 2213 .flags = CLK_SET_RATE_PARENT, 2214 .ops = &clk_branch2_ops, 2215 }, 2216 }, 2217 }; 2218 2219 static struct clk_branch cam_cc_tfe_1_bayer_clk = { 2220 .halt_reg = 0x210c0, 2221 .halt_check = BRANCH_HALT, 2222 .clkr = { 2223 .enable_reg = 0x210c0, 2224 .enable_mask = BIT(0), 2225 .hw.init = &(const struct clk_init_data) { 2226 .name = "cam_cc_tfe_1_bayer_clk", 2227 .parent_hws = (const struct clk_hw*[]) { 2228 &cam_cc_tfe_1_clk_src.clkr.hw, 2229 }, 2230 .num_parents = 1, 2231 .flags = CLK_SET_RATE_PARENT, 2232 .ops = &clk_branch2_ops, 2233 }, 2234 }, 2235 }; 2236 2237 static struct clk_branch cam_cc_tfe_1_bayer_fast_ahb_clk = { 2238 .halt_reg = 0x210dc, 2239 .halt_check = BRANCH_HALT, 2240 .clkr = { 2241 .enable_reg = 0x210dc, 2242 .enable_mask = BIT(0), 2243 .hw.init = &(const struct clk_init_data) { 2244 .name = "cam_cc_tfe_1_bayer_fast_ahb_clk", 2245 .parent_hws = (const struct clk_hw*[]) { 2246 &cam_cc_fast_ahb_clk_src.clkr.hw, 2247 }, 2248 .num_parents = 1, 2249 .flags = CLK_SET_RATE_PARENT, 2250 .ops = &clk_branch2_ops, 2251 }, 2252 }, 2253 }; 2254 2255 static struct clk_branch cam_cc_tfe_1_main_clk = { 2256 .halt_reg = 0x210ac, 2257 .halt_check = BRANCH_HALT, 2258 .clkr = { 2259 .enable_reg = 0x210ac, 2260 .enable_mask = BIT(0), 2261 .hw.init = &(const struct clk_init_data) { 2262 .name = "cam_cc_tfe_1_main_clk", 2263 .parent_hws = (const struct clk_hw*[]) { 2264 &cam_cc_tfe_1_clk_src.clkr.hw, 2265 }, 2266 .num_parents = 1, 2267 .flags = CLK_SET_RATE_PARENT, 2268 .ops = &clk_branch2_ops, 2269 }, 2270 }, 2271 }; 2272 2273 static struct clk_branch cam_cc_tfe_1_main_fast_ahb_clk = { 2274 .halt_reg = 0x210d8, 2275 .halt_check = BRANCH_HALT, 2276 .clkr = { 2277 .enable_reg = 0x210d8, 2278 .enable_mask = BIT(0), 2279 .hw.init = &(const struct clk_init_data) { 2280 .name = "cam_cc_tfe_1_main_fast_ahb_clk", 2281 .parent_hws = (const struct clk_hw*[]) { 2282 &cam_cc_fast_ahb_clk_src.clkr.hw, 2283 }, 2284 .num_parents = 1, 2285 .flags = CLK_SET_RATE_PARENT, 2286 .ops = &clk_branch2_ops, 2287 }, 2288 }, 2289 }; 2290 2291 static struct clk_branch cam_cc_tfe_2_bayer_clk = { 2292 .halt_reg = 0x21124, 2293 .halt_check = BRANCH_HALT, 2294 .clkr = { 2295 .enable_reg = 0x21124, 2296 .enable_mask = BIT(0), 2297 .hw.init = &(const struct clk_init_data) { 2298 .name = "cam_cc_tfe_2_bayer_clk", 2299 .parent_hws = (const struct clk_hw*[]) { 2300 &cam_cc_tfe_2_clk_src.clkr.hw, 2301 }, 2302 .num_parents = 1, 2303 .flags = CLK_SET_RATE_PARENT, 2304 .ops = &clk_branch2_ops, 2305 }, 2306 }, 2307 }; 2308 2309 static struct clk_branch cam_cc_tfe_2_bayer_fast_ahb_clk = { 2310 .halt_reg = 0x21140, 2311 .halt_check = BRANCH_HALT, 2312 .clkr = { 2313 .enable_reg = 0x21140, 2314 .enable_mask = BIT(0), 2315 .hw.init = &(const struct clk_init_data) { 2316 .name = "cam_cc_tfe_2_bayer_fast_ahb_clk", 2317 .parent_hws = (const struct clk_hw*[]) { 2318 &cam_cc_fast_ahb_clk_src.clkr.hw, 2319 }, 2320 .num_parents = 1, 2321 .flags = CLK_SET_RATE_PARENT, 2322 .ops = &clk_branch2_ops, 2323 }, 2324 }, 2325 }; 2326 2327 static struct clk_branch cam_cc_tfe_2_main_clk = { 2328 .halt_reg = 0x21110, 2329 .halt_check = BRANCH_HALT, 2330 .clkr = { 2331 .enable_reg = 0x21110, 2332 .enable_mask = BIT(0), 2333 .hw.init = &(const struct clk_init_data) { 2334 .name = "cam_cc_tfe_2_main_clk", 2335 .parent_hws = (const struct clk_hw*[]) { 2336 &cam_cc_tfe_2_clk_src.clkr.hw, 2337 }, 2338 .num_parents = 1, 2339 .flags = CLK_SET_RATE_PARENT, 2340 .ops = &clk_branch2_ops, 2341 }, 2342 }, 2343 }; 2344 2345 static struct clk_branch cam_cc_tfe_2_main_fast_ahb_clk = { 2346 .halt_reg = 0x2113c, 2347 .halt_check = BRANCH_HALT, 2348 .clkr = { 2349 .enable_reg = 0x2113c, 2350 .enable_mask = BIT(0), 2351 .hw.init = &(const struct clk_init_data) { 2352 .name = "cam_cc_tfe_2_main_fast_ahb_clk", 2353 .parent_hws = (const struct clk_hw*[]) { 2354 &cam_cc_fast_ahb_clk_src.clkr.hw, 2355 }, 2356 .num_parents = 1, 2357 .flags = CLK_SET_RATE_PARENT, 2358 .ops = &clk_branch2_ops, 2359 }, 2360 }, 2361 }; 2362 2363 static struct clk_branch cam_cc_tracenoc_tpdm_1_cmb_clk = { 2364 .halt_reg = 0x21394, 2365 .halt_check = BRANCH_HALT, 2366 .clkr = { 2367 .enable_reg = 0x21394, 2368 .enable_mask = BIT(0), 2369 .hw.init = &(const struct clk_init_data) { 2370 .name = "cam_cc_tracenoc_tpdm_1_cmb_clk", 2371 .parent_hws = (const struct clk_hw*[]) { 2372 &cam_cc_xo_clk_src.clkr.hw, 2373 }, 2374 .num_parents = 1, 2375 .flags = CLK_SET_RATE_PARENT, 2376 .ops = &clk_branch2_ops, 2377 }, 2378 }, 2379 }; 2380 2381 static struct gdsc cam_cc_titan_top_gdsc = { 2382 .gdscr = 0x21334, 2383 .en_rest_wait_val = 0x2, 2384 .en_few_wait_val = 0x2, 2385 .clk_dis_wait_val = 0xf, 2386 .pd = { 2387 .name = "cam_cc_titan_top_gdsc", 2388 }, 2389 .pwrsts = PWRSTS_OFF_ON, 2390 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 2391 }; 2392 2393 static struct gdsc cam_cc_ipe_0_gdsc = { 2394 .gdscr = 0x20174, 2395 .en_rest_wait_val = 0x2, 2396 .en_few_wait_val = 0x2, 2397 .clk_dis_wait_val = 0xf, 2398 .pd = { 2399 .name = "cam_cc_ipe_0_gdsc", 2400 }, 2401 .parent = &cam_cc_titan_top_gdsc.pd, 2402 .pwrsts = PWRSTS_OFF_ON, 2403 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | HW_CTRL_TRIGGER, 2404 }; 2405 2406 static struct gdsc cam_cc_ofe_gdsc = { 2407 .gdscr = 0x200c8, 2408 .en_rest_wait_val = 0x2, 2409 .en_few_wait_val = 0x2, 2410 .clk_dis_wait_val = 0xf, 2411 .pd = { 2412 .name = "cam_cc_ofe_gdsc", 2413 }, 2414 .pwrsts = PWRSTS_OFF_ON, 2415 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | HW_CTRL_TRIGGER, 2416 .parent = &cam_cc_titan_top_gdsc.pd, 2417 }; 2418 2419 static struct gdsc cam_cc_tfe_0_gdsc = { 2420 .gdscr = 0x21004, 2421 .en_rest_wait_val = 0x2, 2422 .en_few_wait_val = 0x2, 2423 .clk_dis_wait_val = 0xf, 2424 .pd = { 2425 .name = "cam_cc_tfe_0_gdsc", 2426 }, 2427 .pwrsts = PWRSTS_OFF_ON, 2428 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 2429 .parent = &cam_cc_titan_top_gdsc.pd, 2430 }; 2431 2432 static struct gdsc cam_cc_tfe_1_gdsc = { 2433 .gdscr = 0x21080, 2434 .en_rest_wait_val = 0x2, 2435 .en_few_wait_val = 0x2, 2436 .clk_dis_wait_val = 0xf, 2437 .pd = { 2438 .name = "cam_cc_tfe_1_gdsc", 2439 }, 2440 .pwrsts = PWRSTS_OFF_ON, 2441 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 2442 .parent = &cam_cc_titan_top_gdsc.pd, 2443 }; 2444 2445 static struct gdsc cam_cc_tfe_2_gdsc = { 2446 .gdscr = 0x210e4, 2447 .en_rest_wait_val = 0x2, 2448 .en_few_wait_val = 0x2, 2449 .clk_dis_wait_val = 0xf, 2450 .pd = { 2451 .name = "cam_cc_tfe_2_gdsc", 2452 }, 2453 .pwrsts = PWRSTS_OFF_ON, 2454 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 2455 .parent = &cam_cc_titan_top_gdsc.pd, 2456 }; 2457 2458 static struct clk_regmap *cam_cc_kaanapali_clocks[] = { 2459 [CAM_CC_CAM_TOP_AHB_CLK] = &cam_cc_cam_top_ahb_clk.clkr, 2460 [CAM_CC_CAM_TOP_FAST_AHB_CLK] = &cam_cc_cam_top_fast_ahb_clk.clkr, 2461 [CAM_CC_CAMNOC_NRT_AXI_CLK] = &cam_cc_camnoc_nrt_axi_clk.clkr, 2462 [CAM_CC_CAMNOC_NRT_CRE_CLK] = &cam_cc_camnoc_nrt_cre_clk.clkr, 2463 [CAM_CC_CAMNOC_NRT_IPE_NPS_CLK] = &cam_cc_camnoc_nrt_ipe_nps_clk.clkr, 2464 [CAM_CC_CAMNOC_NRT_OFE_MAIN_CLK] = &cam_cc_camnoc_nrt_ofe_main_clk.clkr, 2465 [CAM_CC_CAMNOC_RT_AXI_CLK] = &cam_cc_camnoc_rt_axi_clk.clkr, 2466 [CAM_CC_CAMNOC_RT_AXI_CLK_SRC] = &cam_cc_camnoc_rt_axi_clk_src.clkr, 2467 [CAM_CC_CAMNOC_RT_IFE_LITE_CLK] = &cam_cc_camnoc_rt_ife_lite_clk.clkr, 2468 [CAM_CC_CAMNOC_RT_TFE_0_MAIN_CLK] = &cam_cc_camnoc_rt_tfe_0_main_clk.clkr, 2469 [CAM_CC_CAMNOC_RT_TFE_1_MAIN_CLK] = &cam_cc_camnoc_rt_tfe_1_main_clk.clkr, 2470 [CAM_CC_CAMNOC_RT_TFE_2_MAIN_CLK] = &cam_cc_camnoc_rt_tfe_2_main_clk.clkr, 2471 [CAM_CC_CAMNOC_XO_CLK] = &cam_cc_camnoc_xo_clk.clkr, 2472 [CAM_CC_CCI_0_CLK] = &cam_cc_cci_0_clk.clkr, 2473 [CAM_CC_CCI_0_CLK_SRC] = &cam_cc_cci_0_clk_src.clkr, 2474 [CAM_CC_CCI_1_CLK] = &cam_cc_cci_1_clk.clkr, 2475 [CAM_CC_CCI_1_CLK_SRC] = &cam_cc_cci_1_clk_src.clkr, 2476 [CAM_CC_CCI_2_CLK] = &cam_cc_cci_2_clk.clkr, 2477 [CAM_CC_CCI_2_CLK_SRC] = &cam_cc_cci_2_clk_src.clkr, 2478 [CAM_CC_CORE_AHB_CLK] = &cam_cc_core_ahb_clk.clkr, 2479 [CAM_CC_CPHY_RX_CLK_SRC] = &cam_cc_cphy_rx_clk_src.clkr, 2480 [CAM_CC_CRE_AHB_CLK] = &cam_cc_cre_ahb_clk.clkr, 2481 [CAM_CC_CRE_CLK] = &cam_cc_cre_clk.clkr, 2482 [CAM_CC_CRE_CLK_SRC] = &cam_cc_cre_clk_src.clkr, 2483 [CAM_CC_CSI0PHYTIMER_CLK] = &cam_cc_csi0phytimer_clk.clkr, 2484 [CAM_CC_CSI0PHYTIMER_CLK_SRC] = &cam_cc_csi0phytimer_clk_src.clkr, 2485 [CAM_CC_CSI1PHYTIMER_CLK] = &cam_cc_csi1phytimer_clk.clkr, 2486 [CAM_CC_CSI1PHYTIMER_CLK_SRC] = &cam_cc_csi1phytimer_clk_src.clkr, 2487 [CAM_CC_CSI2PHYTIMER_CLK] = &cam_cc_csi2phytimer_clk.clkr, 2488 [CAM_CC_CSI2PHYTIMER_CLK_SRC] = &cam_cc_csi2phytimer_clk_src.clkr, 2489 [CAM_CC_CSI3PHYTIMER_CLK] = &cam_cc_csi3phytimer_clk.clkr, 2490 [CAM_CC_CSI3PHYTIMER_CLK_SRC] = &cam_cc_csi3phytimer_clk_src.clkr, 2491 [CAM_CC_CSI4PHYTIMER_CLK] = &cam_cc_csi4phytimer_clk.clkr, 2492 [CAM_CC_CSI4PHYTIMER_CLK_SRC] = &cam_cc_csi4phytimer_clk_src.clkr, 2493 [CAM_CC_CSI5PHYTIMER_CLK] = &cam_cc_csi5phytimer_clk.clkr, 2494 [CAM_CC_CSI5PHYTIMER_CLK_SRC] = &cam_cc_csi5phytimer_clk_src.clkr, 2495 [CAM_CC_CSID_CLK] = &cam_cc_csid_clk.clkr, 2496 [CAM_CC_CSID_CLK_SRC] = &cam_cc_csid_clk_src.clkr, 2497 [CAM_CC_CSID_CSIPHY_RX_CLK] = &cam_cc_csid_csiphy_rx_clk.clkr, 2498 [CAM_CC_CSIPHY0_CLK] = &cam_cc_csiphy0_clk.clkr, 2499 [CAM_CC_CSIPHY1_CLK] = &cam_cc_csiphy1_clk.clkr, 2500 [CAM_CC_CSIPHY2_CLK] = &cam_cc_csiphy2_clk.clkr, 2501 [CAM_CC_CSIPHY3_CLK] = &cam_cc_csiphy3_clk.clkr, 2502 [CAM_CC_CSIPHY4_CLK] = &cam_cc_csiphy4_clk.clkr, 2503 [CAM_CC_CSIPHY5_CLK] = &cam_cc_csiphy5_clk.clkr, 2504 [CAM_CC_FAST_AHB_CLK_SRC] = &cam_cc_fast_ahb_clk_src.clkr, 2505 [CAM_CC_ICP_0_AHB_CLK] = &cam_cc_icp_0_ahb_clk.clkr, 2506 [CAM_CC_ICP_0_CLK] = &cam_cc_icp_0_clk.clkr, 2507 [CAM_CC_ICP_0_CLK_SRC] = &cam_cc_icp_0_clk_src.clkr, 2508 [CAM_CC_ICP_1_AHB_CLK] = &cam_cc_icp_1_ahb_clk.clkr, 2509 [CAM_CC_ICP_1_CLK] = &cam_cc_icp_1_clk.clkr, 2510 [CAM_CC_ICP_1_CLK_SRC] = &cam_cc_icp_1_clk_src.clkr, 2511 [CAM_CC_IFE_LITE_AHB_CLK] = &cam_cc_ife_lite_ahb_clk.clkr, 2512 [CAM_CC_IFE_LITE_CLK] = &cam_cc_ife_lite_clk.clkr, 2513 [CAM_CC_IFE_LITE_CLK_SRC] = &cam_cc_ife_lite_clk_src.clkr, 2514 [CAM_CC_IFE_LITE_CPHY_RX_CLK] = &cam_cc_ife_lite_cphy_rx_clk.clkr, 2515 [CAM_CC_IFE_LITE_CSID_CLK] = &cam_cc_ife_lite_csid_clk.clkr, 2516 [CAM_CC_IFE_LITE_CSID_CLK_SRC] = &cam_cc_ife_lite_csid_clk_src.clkr, 2517 [CAM_CC_IPE_NPS_AHB_CLK] = &cam_cc_ipe_nps_ahb_clk.clkr, 2518 [CAM_CC_IPE_NPS_CLK] = &cam_cc_ipe_nps_clk.clkr, 2519 [CAM_CC_IPE_NPS_CLK_SRC] = &cam_cc_ipe_nps_clk_src.clkr, 2520 [CAM_CC_IPE_NPS_FAST_AHB_CLK] = &cam_cc_ipe_nps_fast_ahb_clk.clkr, 2521 [CAM_CC_IPE_PPS_CLK] = &cam_cc_ipe_pps_clk.clkr, 2522 [CAM_CC_IPE_PPS_FAST_AHB_CLK] = &cam_cc_ipe_pps_fast_ahb_clk.clkr, 2523 [CAM_CC_JPEG_CLK] = &cam_cc_jpeg_clk.clkr, 2524 [CAM_CC_JPEG_CLK_SRC] = &cam_cc_jpeg_clk_src.clkr, 2525 [CAM_CC_OFE_AHB_CLK] = &cam_cc_ofe_ahb_clk.clkr, 2526 [CAM_CC_OFE_ANCHOR_CLK] = &cam_cc_ofe_anchor_clk.clkr, 2527 [CAM_CC_OFE_ANCHOR_FAST_AHB_CLK] = &cam_cc_ofe_anchor_fast_ahb_clk.clkr, 2528 [CAM_CC_OFE_CLK_SRC] = &cam_cc_ofe_clk_src.clkr, 2529 [CAM_CC_OFE_HDR_CLK] = &cam_cc_ofe_hdr_clk.clkr, 2530 [CAM_CC_OFE_HDR_FAST_AHB_CLK] = &cam_cc_ofe_hdr_fast_ahb_clk.clkr, 2531 [CAM_CC_OFE_MAIN_CLK] = &cam_cc_ofe_main_clk.clkr, 2532 [CAM_CC_OFE_MAIN_FAST_AHB_CLK] = &cam_cc_ofe_main_fast_ahb_clk.clkr, 2533 [CAM_CC_PLL0] = &cam_cc_pll0.clkr, 2534 [CAM_CC_PLL0_OUT_EVEN] = &cam_cc_pll0_out_even.clkr, 2535 [CAM_CC_PLL0_OUT_ODD] = &cam_cc_pll0_out_odd.clkr, 2536 [CAM_CC_PLL1] = &cam_cc_pll1.clkr, 2537 [CAM_CC_PLL1_OUT_EVEN] = &cam_cc_pll1_out_even.clkr, 2538 [CAM_CC_PLL2] = &cam_cc_pll2.clkr, 2539 [CAM_CC_PLL2_OUT_EVEN] = &cam_cc_pll2_out_even.clkr, 2540 [CAM_CC_PLL3] = &cam_cc_pll3.clkr, 2541 [CAM_CC_PLL3_OUT_EVEN] = &cam_cc_pll3_out_even.clkr, 2542 [CAM_CC_PLL4] = &cam_cc_pll4.clkr, 2543 [CAM_CC_PLL4_OUT_EVEN] = &cam_cc_pll4_out_even.clkr, 2544 [CAM_CC_PLL5] = &cam_cc_pll5.clkr, 2545 [CAM_CC_PLL5_OUT_EVEN] = &cam_cc_pll5_out_even.clkr, 2546 [CAM_CC_PLL6] = &cam_cc_pll6.clkr, 2547 [CAM_CC_PLL6_OUT_EVEN] = &cam_cc_pll6_out_even.clkr, 2548 [CAM_CC_PLL6_OUT_ODD] = &cam_cc_pll6_out_odd.clkr, 2549 [CAM_CC_PLL7] = &cam_cc_pll7.clkr, 2550 [CAM_CC_PLL7_OUT_EVEN] = &cam_cc_pll7_out_even.clkr, 2551 [CAM_CC_QDSS_DEBUG_CLK] = &cam_cc_qdss_debug_clk.clkr, 2552 [CAM_CC_QDSS_DEBUG_CLK_SRC] = &cam_cc_qdss_debug_clk_src.clkr, 2553 [CAM_CC_QDSS_DEBUG_XO_CLK] = &cam_cc_qdss_debug_xo_clk.clkr, 2554 [CAM_CC_SLOW_AHB_CLK_SRC] = &cam_cc_slow_ahb_clk_src.clkr, 2555 [CAM_CC_TFE_0_BAYER_CLK] = &cam_cc_tfe_0_bayer_clk.clkr, 2556 [CAM_CC_TFE_0_BAYER_FAST_AHB_CLK] = &cam_cc_tfe_0_bayer_fast_ahb_clk.clkr, 2557 [CAM_CC_TFE_0_CLK_SRC] = &cam_cc_tfe_0_clk_src.clkr, 2558 [CAM_CC_TFE_0_MAIN_CLK] = &cam_cc_tfe_0_main_clk.clkr, 2559 [CAM_CC_TFE_0_MAIN_FAST_AHB_CLK] = &cam_cc_tfe_0_main_fast_ahb_clk.clkr, 2560 [CAM_CC_TFE_1_BAYER_CLK] = &cam_cc_tfe_1_bayer_clk.clkr, 2561 [CAM_CC_TFE_1_BAYER_FAST_AHB_CLK] = &cam_cc_tfe_1_bayer_fast_ahb_clk.clkr, 2562 [CAM_CC_TFE_1_CLK_SRC] = &cam_cc_tfe_1_clk_src.clkr, 2563 [CAM_CC_TFE_1_MAIN_CLK] = &cam_cc_tfe_1_main_clk.clkr, 2564 [CAM_CC_TFE_1_MAIN_FAST_AHB_CLK] = &cam_cc_tfe_1_main_fast_ahb_clk.clkr, 2565 [CAM_CC_TFE_2_BAYER_CLK] = &cam_cc_tfe_2_bayer_clk.clkr, 2566 [CAM_CC_TFE_2_BAYER_FAST_AHB_CLK] = &cam_cc_tfe_2_bayer_fast_ahb_clk.clkr, 2567 [CAM_CC_TFE_2_CLK_SRC] = &cam_cc_tfe_2_clk_src.clkr, 2568 [CAM_CC_TFE_2_MAIN_CLK] = &cam_cc_tfe_2_main_clk.clkr, 2569 [CAM_CC_TFE_2_MAIN_FAST_AHB_CLK] = &cam_cc_tfe_2_main_fast_ahb_clk.clkr, 2570 [CAM_CC_TRACENOC_TPDM_1_CMB_CLK] = &cam_cc_tracenoc_tpdm_1_cmb_clk.clkr, 2571 [CAM_CC_XO_CLK_SRC] = &cam_cc_xo_clk_src.clkr, 2572 }; 2573 2574 static struct gdsc *cam_cc_kaanapali_gdscs[] = { 2575 [CAM_CC_IPE_0_GDSC] = &cam_cc_ipe_0_gdsc, 2576 [CAM_CC_OFE_GDSC] = &cam_cc_ofe_gdsc, 2577 [CAM_CC_TFE_0_GDSC] = &cam_cc_tfe_0_gdsc, 2578 [CAM_CC_TFE_1_GDSC] = &cam_cc_tfe_1_gdsc, 2579 [CAM_CC_TFE_2_GDSC] = &cam_cc_tfe_2_gdsc, 2580 [CAM_CC_TITAN_TOP_GDSC] = &cam_cc_titan_top_gdsc, 2581 }; 2582 2583 static const struct qcom_reset_map cam_cc_kaanapali_resets[] = { 2584 [CAM_CC_DRV_BCR] = { 0x2138c }, 2585 [CAM_CC_ICP_BCR] = { 0x211f4 }, 2586 [CAM_CC_IPE_0_BCR] = { 0x20170 }, 2587 [CAM_CC_OFE_BCR] = { 0x200c4 }, 2588 [CAM_CC_QDSS_DEBUG_BCR] = { 0x21310 }, 2589 [CAM_CC_TFE_0_BCR] = { 0x21000 }, 2590 [CAM_CC_TFE_1_BCR] = { 0x2107c }, 2591 [CAM_CC_TFE_2_BCR] = { 0x210e0 }, 2592 }; 2593 2594 static struct clk_alpha_pll *cam_cc_kaanapali_plls[] = { 2595 &cam_cc_pll0, 2596 &cam_cc_pll1, 2597 &cam_cc_pll2, 2598 &cam_cc_pll3, 2599 &cam_cc_pll4, 2600 &cam_cc_pll5, 2601 &cam_cc_pll6, 2602 &cam_cc_pll7, 2603 }; 2604 2605 static u32 cam_cc_kaanapali_critical_cbcrs[] = { 2606 0x21398, /* CAM_CC_DRV_AHB_CLK */ 2607 0x21390, /* CAM_CC_DRV_XO_CLK */ 2608 0x21364, /* CAM_CC_GDSC_CLK */ 2609 0x21368, /* CAM_CC_SLEEP_CLK */ 2610 }; 2611 2612 static const struct regmap_config cam_cc_kaanapali_regmap_config = { 2613 .reg_bits = 32, 2614 .reg_stride = 4, 2615 .val_bits = 32, 2616 .max_register = 0x2601c, 2617 .fast_io = true, 2618 }; 2619 2620 static struct qcom_cc_driver_data cam_cc_kaanapali_driver_data = { 2621 .alpha_plls = cam_cc_kaanapali_plls, 2622 .num_alpha_plls = ARRAY_SIZE(cam_cc_kaanapali_plls), 2623 .clk_cbcrs = cam_cc_kaanapali_critical_cbcrs, 2624 .num_clk_cbcrs = ARRAY_SIZE(cam_cc_kaanapali_critical_cbcrs), 2625 }; 2626 2627 static const struct qcom_cc_desc cam_cc_kaanapali_desc = { 2628 .config = &cam_cc_kaanapali_regmap_config, 2629 .clks = cam_cc_kaanapali_clocks, 2630 .num_clks = ARRAY_SIZE(cam_cc_kaanapali_clocks), 2631 .resets = cam_cc_kaanapali_resets, 2632 .num_resets = ARRAY_SIZE(cam_cc_kaanapali_resets), 2633 .gdscs = cam_cc_kaanapali_gdscs, 2634 .num_gdscs = ARRAY_SIZE(cam_cc_kaanapali_gdscs), 2635 .use_rpm = true, 2636 .driver_data = &cam_cc_kaanapali_driver_data, 2637 }; 2638 2639 static const struct of_device_id cam_cc_kaanapali_match_table[] = { 2640 { .compatible = "qcom,kaanapali-camcc" }, 2641 { } 2642 }; 2643 MODULE_DEVICE_TABLE(of, cam_cc_kaanapali_match_table); 2644 2645 static int cam_cc_kaanapali_probe(struct platform_device *pdev) 2646 { 2647 return qcom_cc_probe(pdev, &cam_cc_kaanapali_desc); 2648 } 2649 2650 static struct platform_driver cam_cc_kaanapali_driver = { 2651 .probe = cam_cc_kaanapali_probe, 2652 .driver = { 2653 .name = "camcc-kaanapali", 2654 .of_match_table = cam_cc_kaanapali_match_table, 2655 }, 2656 }; 2657 2658 module_platform_driver(cam_cc_kaanapali_driver); 2659 2660 MODULE_DESCRIPTION("QTI CAMCC Kaanapali Driver"); 2661 MODULE_LICENSE("GPL"); 2662