1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 4 */ 5 6 #include <linux/clk-provider.h> 7 #include <linux/mod_devicetable.h> 8 #include <linux/module.h> 9 #include <linux/of.h> 10 #include <linux/platform_device.h> 11 #include <linux/pm_runtime.h> 12 #include <linux/regmap.h> 13 14 #include <dt-bindings/clock/qcom,kaanapali-cambistmclkcc.h> 15 16 #include "clk-alpha-pll.h" 17 #include "clk-branch.h" 18 #include "clk-pll.h" 19 #include "clk-rcg.h" 20 #include "clk-regmap.h" 21 #include "clk-regmap-divider.h" 22 #include "clk-regmap-mux.h" 23 #include "common.h" 24 #include "gdsc.h" 25 #include "reset.h" 26 27 enum { 28 DT_AHB_CLK, 29 DT_BI_TCXO, 30 DT_BI_TCXO_AO, 31 DT_SLEEP_CLK, 32 }; 33 34 enum { 35 P_BI_TCXO, 36 P_CAM_BIST_MCLK_CC_PLL0_OUT_EVEN, 37 P_CAM_BIST_MCLK_CC_PLL0_OUT_MAIN, 38 }; 39 40 static const struct pll_vco rivian_eko_t_vco[] = { 41 { 883200000, 1171200000, 0 }, 42 }; 43 44 /* 960.0 MHz Configuration */ 45 static const struct alpha_pll_config cam_bist_mclk_cc_pll0_config = { 46 .l = 0x32, 47 .cal_l = 0x32, 48 .alpha = 0x0, 49 .config_ctl_val = 0x12000000, 50 .config_ctl_hi_val = 0x00890263, 51 .config_ctl_hi1_val = 0x1af04237, 52 .config_ctl_hi2_val = 0x00000000, 53 }; 54 55 static struct clk_alpha_pll cam_bist_mclk_cc_pll0 = { 56 .offset = 0x0, 57 .config = &cam_bist_mclk_cc_pll0_config, 58 .vco_table = rivian_eko_t_vco, 59 .num_vco = ARRAY_SIZE(rivian_eko_t_vco), 60 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_RIVIAN_EKO_T], 61 .clkr = { 62 .hw.init = &(const struct clk_init_data) { 63 .name = "cam_bist_mclk_cc_pll0", 64 .parent_data = &(const struct clk_parent_data) { 65 .index = DT_BI_TCXO, 66 }, 67 .num_parents = 1, 68 .ops = &clk_alpha_pll_rivian_eko_t_ops, 69 }, 70 }, 71 }; 72 73 static const struct parent_map cam_bist_mclk_cc_parent_map_0[] = { 74 { P_BI_TCXO, 0 }, 75 { P_CAM_BIST_MCLK_CC_PLL0_OUT_EVEN, 3 }, 76 { P_CAM_BIST_MCLK_CC_PLL0_OUT_MAIN, 5 }, 77 }; 78 79 static const struct clk_parent_data cam_bist_mclk_cc_parent_data_0[] = { 80 { .index = DT_BI_TCXO }, 81 { .hw = &cam_bist_mclk_cc_pll0.clkr.hw }, 82 { .hw = &cam_bist_mclk_cc_pll0.clkr.hw }, 83 }; 84 85 static const struct freq_tbl ftbl_cam_bist_mclk_cc_mclk0_clk_src[] = { 86 F(19200000, P_BI_TCXO, 1, 0, 0), 87 F(24000000, P_CAM_BIST_MCLK_CC_PLL0_OUT_EVEN, 10, 1, 4), 88 F(68571429, P_CAM_BIST_MCLK_CC_PLL0_OUT_MAIN, 14, 0, 0), 89 { } 90 }; 91 92 static struct clk_rcg2 cam_bist_mclk_cc_mclk0_clk_src = { 93 .cmd_rcgr = 0x4000, 94 .mnd_width = 8, 95 .hid_width = 5, 96 .parent_map = cam_bist_mclk_cc_parent_map_0, 97 .hw_clk_ctrl = true, 98 .freq_tbl = ftbl_cam_bist_mclk_cc_mclk0_clk_src, 99 .clkr.hw.init = &(const struct clk_init_data) { 100 .name = "cam_bist_mclk_cc_mclk0_clk_src", 101 .parent_data = cam_bist_mclk_cc_parent_data_0, 102 .num_parents = ARRAY_SIZE(cam_bist_mclk_cc_parent_data_0), 103 .flags = CLK_SET_RATE_PARENT, 104 .ops = &clk_rcg2_shared_ops, 105 }, 106 }; 107 108 static struct clk_rcg2 cam_bist_mclk_cc_mclk1_clk_src = { 109 .cmd_rcgr = 0x401c, 110 .mnd_width = 8, 111 .hid_width = 5, 112 .parent_map = cam_bist_mclk_cc_parent_map_0, 113 .hw_clk_ctrl = true, 114 .freq_tbl = ftbl_cam_bist_mclk_cc_mclk0_clk_src, 115 .clkr.hw.init = &(const struct clk_init_data) { 116 .name = "cam_bist_mclk_cc_mclk1_clk_src", 117 .parent_data = cam_bist_mclk_cc_parent_data_0, 118 .num_parents = ARRAY_SIZE(cam_bist_mclk_cc_parent_data_0), 119 .flags = CLK_SET_RATE_PARENT, 120 .ops = &clk_rcg2_shared_ops, 121 }, 122 }; 123 124 static struct clk_rcg2 cam_bist_mclk_cc_mclk2_clk_src = { 125 .cmd_rcgr = 0x4038, 126 .mnd_width = 8, 127 .hid_width = 5, 128 .parent_map = cam_bist_mclk_cc_parent_map_0, 129 .hw_clk_ctrl = true, 130 .freq_tbl = ftbl_cam_bist_mclk_cc_mclk0_clk_src, 131 .clkr.hw.init = &(const struct clk_init_data) { 132 .name = "cam_bist_mclk_cc_mclk2_clk_src", 133 .parent_data = cam_bist_mclk_cc_parent_data_0, 134 .num_parents = ARRAY_SIZE(cam_bist_mclk_cc_parent_data_0), 135 .flags = CLK_SET_RATE_PARENT, 136 .ops = &clk_rcg2_shared_ops, 137 }, 138 }; 139 140 static struct clk_rcg2 cam_bist_mclk_cc_mclk3_clk_src = { 141 .cmd_rcgr = 0x4054, 142 .mnd_width = 8, 143 .hid_width = 5, 144 .parent_map = cam_bist_mclk_cc_parent_map_0, 145 .hw_clk_ctrl = true, 146 .freq_tbl = ftbl_cam_bist_mclk_cc_mclk0_clk_src, 147 .clkr.hw.init = &(const struct clk_init_data) { 148 .name = "cam_bist_mclk_cc_mclk3_clk_src", 149 .parent_data = cam_bist_mclk_cc_parent_data_0, 150 .num_parents = ARRAY_SIZE(cam_bist_mclk_cc_parent_data_0), 151 .flags = CLK_SET_RATE_PARENT, 152 .ops = &clk_rcg2_shared_ops, 153 }, 154 }; 155 156 static struct clk_rcg2 cam_bist_mclk_cc_mclk4_clk_src = { 157 .cmd_rcgr = 0x4070, 158 .mnd_width = 8, 159 .hid_width = 5, 160 .parent_map = cam_bist_mclk_cc_parent_map_0, 161 .hw_clk_ctrl = true, 162 .freq_tbl = ftbl_cam_bist_mclk_cc_mclk0_clk_src, 163 .clkr.hw.init = &(const struct clk_init_data) { 164 .name = "cam_bist_mclk_cc_mclk4_clk_src", 165 .parent_data = cam_bist_mclk_cc_parent_data_0, 166 .num_parents = ARRAY_SIZE(cam_bist_mclk_cc_parent_data_0), 167 .flags = CLK_SET_RATE_PARENT, 168 .ops = &clk_rcg2_shared_ops, 169 }, 170 }; 171 172 static struct clk_rcg2 cam_bist_mclk_cc_mclk5_clk_src = { 173 .cmd_rcgr = 0x408c, 174 .mnd_width = 8, 175 .hid_width = 5, 176 .parent_map = cam_bist_mclk_cc_parent_map_0, 177 .hw_clk_ctrl = true, 178 .freq_tbl = ftbl_cam_bist_mclk_cc_mclk0_clk_src, 179 .clkr.hw.init = &(const struct clk_init_data) { 180 .name = "cam_bist_mclk_cc_mclk5_clk_src", 181 .parent_data = cam_bist_mclk_cc_parent_data_0, 182 .num_parents = ARRAY_SIZE(cam_bist_mclk_cc_parent_data_0), 183 .flags = CLK_SET_RATE_PARENT, 184 .ops = &clk_rcg2_shared_ops, 185 }, 186 }; 187 188 static struct clk_rcg2 cam_bist_mclk_cc_mclk6_clk_src = { 189 .cmd_rcgr = 0x40a8, 190 .mnd_width = 8, 191 .hid_width = 5, 192 .parent_map = cam_bist_mclk_cc_parent_map_0, 193 .hw_clk_ctrl = true, 194 .freq_tbl = ftbl_cam_bist_mclk_cc_mclk0_clk_src, 195 .clkr.hw.init = &(const struct clk_init_data) { 196 .name = "cam_bist_mclk_cc_mclk6_clk_src", 197 .parent_data = cam_bist_mclk_cc_parent_data_0, 198 .num_parents = ARRAY_SIZE(cam_bist_mclk_cc_parent_data_0), 199 .flags = CLK_SET_RATE_PARENT, 200 .ops = &clk_rcg2_shared_ops, 201 }, 202 }; 203 204 static struct clk_rcg2 cam_bist_mclk_cc_mclk7_clk_src = { 205 .cmd_rcgr = 0x40c4, 206 .mnd_width = 8, 207 .hid_width = 5, 208 .parent_map = cam_bist_mclk_cc_parent_map_0, 209 .hw_clk_ctrl = true, 210 .freq_tbl = ftbl_cam_bist_mclk_cc_mclk0_clk_src, 211 .clkr.hw.init = &(const struct clk_init_data) { 212 .name = "cam_bist_mclk_cc_mclk7_clk_src", 213 .parent_data = cam_bist_mclk_cc_parent_data_0, 214 .num_parents = ARRAY_SIZE(cam_bist_mclk_cc_parent_data_0), 215 .flags = CLK_SET_RATE_PARENT, 216 .ops = &clk_rcg2_shared_ops, 217 }, 218 }; 219 220 static struct clk_branch cam_bist_mclk_cc_mclk0_clk = { 221 .halt_reg = 0x4018, 222 .halt_check = BRANCH_HALT, 223 .clkr = { 224 .enable_reg = 0x4018, 225 .enable_mask = BIT(0), 226 .hw.init = &(const struct clk_init_data) { 227 .name = "cam_bist_mclk_cc_mclk0_clk", 228 .parent_hws = (const struct clk_hw*[]) { 229 &cam_bist_mclk_cc_mclk0_clk_src.clkr.hw, 230 }, 231 .num_parents = 1, 232 .flags = CLK_SET_RATE_PARENT, 233 .ops = &clk_branch2_ops, 234 }, 235 }, 236 }; 237 238 static struct clk_branch cam_bist_mclk_cc_mclk1_clk = { 239 .halt_reg = 0x4034, 240 .halt_check = BRANCH_HALT, 241 .clkr = { 242 .enable_reg = 0x4034, 243 .enable_mask = BIT(0), 244 .hw.init = &(const struct clk_init_data) { 245 .name = "cam_bist_mclk_cc_mclk1_clk", 246 .parent_hws = (const struct clk_hw*[]) { 247 &cam_bist_mclk_cc_mclk1_clk_src.clkr.hw, 248 }, 249 .num_parents = 1, 250 .flags = CLK_SET_RATE_PARENT, 251 .ops = &clk_branch2_ops, 252 }, 253 }, 254 }; 255 256 static struct clk_branch cam_bist_mclk_cc_mclk2_clk = { 257 .halt_reg = 0x4050, 258 .halt_check = BRANCH_HALT, 259 .clkr = { 260 .enable_reg = 0x4050, 261 .enable_mask = BIT(0), 262 .hw.init = &(const struct clk_init_data) { 263 .name = "cam_bist_mclk_cc_mclk2_clk", 264 .parent_hws = (const struct clk_hw*[]) { 265 &cam_bist_mclk_cc_mclk2_clk_src.clkr.hw, 266 }, 267 .num_parents = 1, 268 .flags = CLK_SET_RATE_PARENT, 269 .ops = &clk_branch2_ops, 270 }, 271 }, 272 }; 273 274 static struct clk_branch cam_bist_mclk_cc_mclk3_clk = { 275 .halt_reg = 0x406c, 276 .halt_check = BRANCH_HALT, 277 .clkr = { 278 .enable_reg = 0x406c, 279 .enable_mask = BIT(0), 280 .hw.init = &(const struct clk_init_data) { 281 .name = "cam_bist_mclk_cc_mclk3_clk", 282 .parent_hws = (const struct clk_hw*[]) { 283 &cam_bist_mclk_cc_mclk3_clk_src.clkr.hw, 284 }, 285 .num_parents = 1, 286 .flags = CLK_SET_RATE_PARENT, 287 .ops = &clk_branch2_ops, 288 }, 289 }, 290 }; 291 292 static struct clk_branch cam_bist_mclk_cc_mclk4_clk = { 293 .halt_reg = 0x4088, 294 .halt_check = BRANCH_HALT, 295 .clkr = { 296 .enable_reg = 0x4088, 297 .enable_mask = BIT(0), 298 .hw.init = &(const struct clk_init_data) { 299 .name = "cam_bist_mclk_cc_mclk4_clk", 300 .parent_hws = (const struct clk_hw*[]) { 301 &cam_bist_mclk_cc_mclk4_clk_src.clkr.hw, 302 }, 303 .num_parents = 1, 304 .flags = CLK_SET_RATE_PARENT, 305 .ops = &clk_branch2_ops, 306 }, 307 }, 308 }; 309 310 static struct clk_branch cam_bist_mclk_cc_mclk5_clk = { 311 .halt_reg = 0x40a4, 312 .halt_check = BRANCH_HALT, 313 .clkr = { 314 .enable_reg = 0x40a4, 315 .enable_mask = BIT(0), 316 .hw.init = &(const struct clk_init_data) { 317 .name = "cam_bist_mclk_cc_mclk5_clk", 318 .parent_hws = (const struct clk_hw*[]) { 319 &cam_bist_mclk_cc_mclk5_clk_src.clkr.hw, 320 }, 321 .num_parents = 1, 322 .flags = CLK_SET_RATE_PARENT, 323 .ops = &clk_branch2_ops, 324 }, 325 }, 326 }; 327 328 static struct clk_branch cam_bist_mclk_cc_mclk6_clk = { 329 .halt_reg = 0x40c0, 330 .halt_check = BRANCH_HALT, 331 .clkr = { 332 .enable_reg = 0x40c0, 333 .enable_mask = BIT(0), 334 .hw.init = &(const struct clk_init_data) { 335 .name = "cam_bist_mclk_cc_mclk6_clk", 336 .parent_hws = (const struct clk_hw*[]) { 337 &cam_bist_mclk_cc_mclk6_clk_src.clkr.hw, 338 }, 339 .num_parents = 1, 340 .flags = CLK_SET_RATE_PARENT, 341 .ops = &clk_branch2_ops, 342 }, 343 }, 344 }; 345 346 static struct clk_branch cam_bist_mclk_cc_mclk7_clk = { 347 .halt_reg = 0x40dc, 348 .halt_check = BRANCH_HALT, 349 .clkr = { 350 .enable_reg = 0x40dc, 351 .enable_mask = BIT(0), 352 .hw.init = &(const struct clk_init_data) { 353 .name = "cam_bist_mclk_cc_mclk7_clk", 354 .parent_hws = (const struct clk_hw*[]) { 355 &cam_bist_mclk_cc_mclk7_clk_src.clkr.hw, 356 }, 357 .num_parents = 1, 358 .flags = CLK_SET_RATE_PARENT, 359 .ops = &clk_branch2_ops, 360 }, 361 }, 362 }; 363 364 static struct clk_regmap *cam_bist_mclk_cc_kaanapali_clocks[] = { 365 [CAM_BIST_MCLK_CC_MCLK0_CLK] = &cam_bist_mclk_cc_mclk0_clk.clkr, 366 [CAM_BIST_MCLK_CC_MCLK0_CLK_SRC] = &cam_bist_mclk_cc_mclk0_clk_src.clkr, 367 [CAM_BIST_MCLK_CC_MCLK1_CLK] = &cam_bist_mclk_cc_mclk1_clk.clkr, 368 [CAM_BIST_MCLK_CC_MCLK1_CLK_SRC] = &cam_bist_mclk_cc_mclk1_clk_src.clkr, 369 [CAM_BIST_MCLK_CC_MCLK2_CLK] = &cam_bist_mclk_cc_mclk2_clk.clkr, 370 [CAM_BIST_MCLK_CC_MCLK2_CLK_SRC] = &cam_bist_mclk_cc_mclk2_clk_src.clkr, 371 [CAM_BIST_MCLK_CC_MCLK3_CLK] = &cam_bist_mclk_cc_mclk3_clk.clkr, 372 [CAM_BIST_MCLK_CC_MCLK3_CLK_SRC] = &cam_bist_mclk_cc_mclk3_clk_src.clkr, 373 [CAM_BIST_MCLK_CC_MCLK4_CLK] = &cam_bist_mclk_cc_mclk4_clk.clkr, 374 [CAM_BIST_MCLK_CC_MCLK4_CLK_SRC] = &cam_bist_mclk_cc_mclk4_clk_src.clkr, 375 [CAM_BIST_MCLK_CC_MCLK5_CLK] = &cam_bist_mclk_cc_mclk5_clk.clkr, 376 [CAM_BIST_MCLK_CC_MCLK5_CLK_SRC] = &cam_bist_mclk_cc_mclk5_clk_src.clkr, 377 [CAM_BIST_MCLK_CC_MCLK6_CLK] = &cam_bist_mclk_cc_mclk6_clk.clkr, 378 [CAM_BIST_MCLK_CC_MCLK6_CLK_SRC] = &cam_bist_mclk_cc_mclk6_clk_src.clkr, 379 [CAM_BIST_MCLK_CC_MCLK7_CLK] = &cam_bist_mclk_cc_mclk7_clk.clkr, 380 [CAM_BIST_MCLK_CC_MCLK7_CLK_SRC] = &cam_bist_mclk_cc_mclk7_clk_src.clkr, 381 [CAM_BIST_MCLK_CC_PLL0] = &cam_bist_mclk_cc_pll0.clkr, 382 }; 383 384 static struct clk_alpha_pll *cam_bist_mclk_cc_kaanapali_plls[] = { 385 &cam_bist_mclk_cc_pll0, 386 }; 387 388 static u32 cam_bist_mclk_cc_kaanapali_critical_cbcrs[] = { 389 0x40e0, /* CAM_BIST_MCLK_CC_SLEEP_CLK */ 390 }; 391 392 static const struct regmap_config cam_bist_mclk_cc_kaanapali_regmap_config = { 393 .reg_bits = 32, 394 .reg_stride = 4, 395 .val_bits = 32, 396 .max_register = 0x5010, 397 .fast_io = true, 398 }; 399 400 static struct qcom_cc_driver_data cam_bist_mclk_cc_kaanapali_driver_data = { 401 .alpha_plls = cam_bist_mclk_cc_kaanapali_plls, 402 .num_alpha_plls = ARRAY_SIZE(cam_bist_mclk_cc_kaanapali_plls), 403 .clk_cbcrs = cam_bist_mclk_cc_kaanapali_critical_cbcrs, 404 .num_clk_cbcrs = ARRAY_SIZE(cam_bist_mclk_cc_kaanapali_critical_cbcrs), 405 }; 406 407 static const struct qcom_cc_desc cam_bist_mclk_cc_kaanapali_desc = { 408 .config = &cam_bist_mclk_cc_kaanapali_regmap_config, 409 .clks = cam_bist_mclk_cc_kaanapali_clocks, 410 .num_clks = ARRAY_SIZE(cam_bist_mclk_cc_kaanapali_clocks), 411 .use_rpm = true, 412 .driver_data = &cam_bist_mclk_cc_kaanapali_driver_data, 413 }; 414 415 static const struct of_device_id cam_bist_mclk_cc_kaanapali_match_table[] = { 416 { .compatible = "qcom,kaanapali-cambistmclkcc" }, 417 { } 418 }; 419 MODULE_DEVICE_TABLE(of, cam_bist_mclk_cc_kaanapali_match_table); 420 421 static int cam_bist_mclk_cc_kaanapali_probe(struct platform_device *pdev) 422 { 423 return qcom_cc_probe(pdev, &cam_bist_mclk_cc_kaanapali_desc); 424 } 425 426 static struct platform_driver cam_bist_mclk_cc_kaanapali_driver = { 427 .probe = cam_bist_mclk_cc_kaanapali_probe, 428 .driver = { 429 .name = "cambistmclkcc-kaanapali", 430 .of_match_table = cam_bist_mclk_cc_kaanapali_match_table, 431 }, 432 }; 433 434 module_platform_driver(cam_bist_mclk_cc_kaanapali_driver); 435 436 MODULE_DESCRIPTION("QTI CAMBISTMCLKCC Kaanapali Driver"); 437 MODULE_LICENSE("GPL"); 438