1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
4 */
5
6 #include <linux/clk-provider.h>
7 #include <linux/module.h>
8 #include <linux/platform_device.h>
9 #include <linux/regmap.h>
10
11 #include <dt-bindings/clock/qcom,shikra-audiocorecc.h>
12
13 #include "clk-alpha-pll.h"
14 #include "clk-branch.h"
15 #include "clk-pll.h"
16 #include "clk-rcg.h"
17 #include "clk-regmap.h"
18 #include "clk-regmap-divider.h"
19 #include "clk-regmap-mux.h"
20 #include "common.h"
21 #include "reset.h"
22
23 enum {
24 DT_BI_TCXO,
25 DT_SLEEP_CLK,
26 DT_AUD_REF_CLK_SRC,
27 };
28
29 enum {
30 P_AUD_REF_CLK_SRC,
31 P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX,
32 P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX2,
33 P_BI_TCXO,
34 P_SLEEP_CLK,
35 };
36
37 static const struct pll_vco spark_vco[] = {
38 { 500000000, 1000000000, 2 },
39 };
40
41 /* 614.4 MHz Configuration */
42 static const struct alpha_pll_config audio_core_cc_dig_pll_config = {
43 .l = 0x20,
44 .alpha = 0x0,
45 .vco_val = BIT(21),
46 .post_div_val = 0x28100,
47 .post_div_mask = GENMASK(17, 8),
48 .vco_mask = GENMASK(21, 20),
49 .main_output_mask = BIT(0),
50 .aux_output_mask = BIT(1),
51 .aux2_output_mask = BIT(2),
52 .config_ctl_val = 0x4001055b,
53 .test_ctl_hi_val = 0x1,
54 .test_ctl_hi_mask = 0x1,
55 };
56
57 static struct clk_alpha_pll audio_core_cc_dig_pll = {
58 .offset = 0x0,
59 .config = &audio_core_cc_dig_pll_config,
60 .vco_table = spark_vco,
61 .num_vco = ARRAY_SIZE(spark_vco),
62 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
63 .clkr = {
64 .hw.init = &(const struct clk_init_data) {
65 .name = "audio_core_cc_dig_pll",
66 .parent_data = &(const struct clk_parent_data) {
67 .index = DT_BI_TCXO,
68 },
69 .num_parents = 1,
70 .ops = &clk_alpha_pll_fixed_ops,
71 },
72 },
73 };
74
75 static struct clk_fixed_factor audio_core_cc_dig_pll_out_aux = {
76 .mult = 1,
77 .div = 5,
78 .hw.init = &(struct clk_init_data) {
79 .name = "audio_core_cc_dig_pll_out_aux",
80 .parent_data = &(const struct clk_parent_data) {
81 .hw = &audio_core_cc_dig_pll.clkr.hw,
82 },
83 .num_parents = 1,
84 .flags = CLK_SET_RATE_PARENT,
85 .ops = &clk_fixed_factor_ops,
86 },
87 };
88
89 static struct clk_fixed_factor audio_core_cc_dig_pll_out_aux2 = {
90 .mult = 1,
91 .div = 2,
92 .hw.init = &(struct clk_init_data) {
93 .name = "audio_core_cc_dig_pll_out_aux2",
94 .parent_data = &(const struct clk_parent_data) {
95 .hw = &audio_core_cc_dig_pll.clkr.hw,
96 },
97 .num_parents = 1,
98 .flags = CLK_SET_RATE_PARENT,
99 .ops = &clk_fixed_factor_ops,
100 },
101 };
102
103 static const struct parent_map audio_core_cc_parent_map_0[] = {
104 { P_BI_TCXO, 0 },
105 { P_AUD_REF_CLK_SRC, 1 },
106 { P_SLEEP_CLK, 2 },
107 { P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 4 },
108 { P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX2, 6 },
109 };
110
111 static const struct clk_parent_data audio_core_cc_parent_data_0[] = {
112 { .index = DT_BI_TCXO },
113 { .index = DT_AUD_REF_CLK_SRC },
114 { .index = DT_SLEEP_CLK },
115 { .hw = &audio_core_cc_dig_pll_out_aux.hw },
116 { .hw = &audio_core_cc_dig_pll_out_aux2.hw },
117 };
118
119 static const struct freq_tbl ftbl_audio_core_cc_aif_if0_clk_src[] = {
120 F(240000, P_BI_TCXO, 10, 1, 8),
121 F(256000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 15, 1, 32),
122 F(512000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 15, 1, 16),
123 F(768000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 10, 1, 16),
124 F(1024000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 15, 1, 8),
125 F(1536000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 10, 1, 8),
126 F(2048000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 15, 1, 4),
127 F(3072000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 10, 1, 4),
128 F(4096000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 15, 1, 2),
129 F(6144000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 10, 1, 2),
130 F(8192000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 15, 0, 0),
131 F(9600000, P_BI_TCXO, 2, 0, 0),
132 F(12288000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 10, 0, 0),
133 F(19200000, P_BI_TCXO, 1, 0, 0),
134 F(24576000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 5, 0, 0),
135 { }
136 };
137
138 static struct clk_rcg2 audio_core_cc_aif_if0_clk_src = {
139 .cmd_rcgr = 0x104c,
140 .mnd_width = 16,
141 .hid_width = 5,
142 .parent_map = audio_core_cc_parent_map_0,
143 .freq_tbl = ftbl_audio_core_cc_aif_if0_clk_src,
144 .hw_clk_ctrl = true,
145 .clkr.hw.init = &(const struct clk_init_data) {
146 .name = "audio_core_cc_aif_if0_clk_src",
147 .parent_data = audio_core_cc_parent_data_0,
148 .num_parents = ARRAY_SIZE(audio_core_cc_parent_data_0),
149 .flags = CLK_SET_RATE_PARENT,
150 .ops = &clk_rcg2_shared_ops,
151 },
152 };
153
154 static struct clk_rcg2 audio_core_cc_aif_if1_clk_src = {
155 .cmd_rcgr = 0x10b0,
156 .mnd_width = 16,
157 .hid_width = 5,
158 .parent_map = audio_core_cc_parent_map_0,
159 .freq_tbl = ftbl_audio_core_cc_aif_if0_clk_src,
160 .hw_clk_ctrl = true,
161 .clkr.hw.init = &(const struct clk_init_data) {
162 .name = "audio_core_cc_aif_if1_clk_src",
163 .parent_data = audio_core_cc_parent_data_0,
164 .num_parents = ARRAY_SIZE(audio_core_cc_parent_data_0),
165 .flags = CLK_SET_RATE_PARENT,
166 .ops = &clk_rcg2_shared_ops,
167 },
168 };
169
170 static struct clk_rcg2 audio_core_cc_aif_if2_clk_src = {
171 .cmd_rcgr = 0x1114,
172 .mnd_width = 16,
173 .hid_width = 5,
174 .parent_map = audio_core_cc_parent_map_0,
175 .freq_tbl = ftbl_audio_core_cc_aif_if0_clk_src,
176 .hw_clk_ctrl = true,
177 .clkr.hw.init = &(const struct clk_init_data) {
178 .name = "audio_core_cc_aif_if2_clk_src",
179 .parent_data = audio_core_cc_parent_data_0,
180 .num_parents = ARRAY_SIZE(audio_core_cc_parent_data_0),
181 .flags = CLK_SET_RATE_PARENT,
182 .ops = &clk_rcg2_shared_ops,
183 },
184 };
185
186 static const struct freq_tbl ftbl_audio_core_cc_aif_if3_clk_src[] = {
187 F(240000, P_BI_TCXO, 10, 1, 8),
188 F(256000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 15, 1, 32),
189 F(512000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 15, 1, 16),
190 F(768000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 10, 1, 16),
191 F(1024000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 15, 1, 8),
192 F(1536000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 10, 1, 8),
193 F(2048000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 15, 1, 4),
194 F(3072000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 10, 1, 4),
195 F(4096000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 15, 1, 2),
196 F(6144000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 10, 1, 2),
197 F(8192000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 15, 0, 0),
198 F(9600000, P_BI_TCXO, 2, 0, 0),
199 F(12288000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 10, 0, 0),
200 F(19200000, P_BI_TCXO, 1, 0, 0),
201 F(24576000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 5, 0, 0),
202 F(49152000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 2.5, 0, 0),
203 { }
204 };
205
206 static struct clk_rcg2 audio_core_cc_aif_if3_clk_src = {
207 .cmd_rcgr = 0x1178,
208 .mnd_width = 16,
209 .hid_width = 5,
210 .parent_map = audio_core_cc_parent_map_0,
211 .freq_tbl = ftbl_audio_core_cc_aif_if3_clk_src,
212 .hw_clk_ctrl = true,
213 .clkr.hw.init = &(const struct clk_init_data) {
214 .name = "audio_core_cc_aif_if3_clk_src",
215 .parent_data = audio_core_cc_parent_data_0,
216 .num_parents = ARRAY_SIZE(audio_core_cc_parent_data_0),
217 .flags = CLK_SET_RATE_PARENT,
218 .ops = &clk_rcg2_shared_ops,
219 },
220 };
221
222 static const struct freq_tbl ftbl_audio_core_cc_aud_dma_clk_src[] = {
223 F(38400000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX2, 8, 0, 0),
224 F(102400000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX2, 3, 0, 0),
225 F(153600000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX2, 2, 0, 0),
226 F(307200000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX2, 1, 0, 0),
227 { }
228 };
229
230 static struct clk_rcg2 audio_core_cc_aud_dma_clk_src = {
231 .cmd_rcgr = 0x1028,
232 .mnd_width = 0,
233 .hid_width = 5,
234 .parent_map = audio_core_cc_parent_map_0,
235 .freq_tbl = ftbl_audio_core_cc_aud_dma_clk_src,
236 .hw_clk_ctrl = true,
237 .clkr.hw.init = &(const struct clk_init_data) {
238 .name = "audio_core_cc_aud_dma_clk_src",
239 .parent_data = audio_core_cc_parent_data_0,
240 .num_parents = ARRAY_SIZE(audio_core_cc_parent_data_0),
241 .flags = CLK_SET_RATE_PARENT,
242 .ops = &clk_rcg2_shared_ops,
243 },
244 };
245
246 static const struct freq_tbl ftbl_audio_core_cc_bus_clk_src[] = {
247 F(38400000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX2, 8, 0, 0),
248 F(76800000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX2, 4, 0, 0),
249 { }
250 };
251
252 static struct clk_rcg2 audio_core_cc_bus_clk_src = {
253 .cmd_rcgr = 0x1008,
254 .mnd_width = 0,
255 .hid_width = 5,
256 .parent_map = audio_core_cc_parent_map_0,
257 .freq_tbl = ftbl_audio_core_cc_bus_clk_src,
258 .hw_clk_ctrl = true,
259 .clkr.hw.init = &(const struct clk_init_data) {
260 .name = "audio_core_cc_bus_clk_src",
261 .parent_data = audio_core_cc_parent_data_0,
262 .num_parents = ARRAY_SIZE(audio_core_cc_parent_data_0),
263 .flags = CLK_SET_RATE_PARENT,
264 .ops = &clk_rcg2_shared_ops,
265 },
266 };
267
268 static struct clk_rcg2 audio_core_cc_ext_mclka_clk_src = {
269 .cmd_rcgr = 0x123c,
270 .mnd_width = 8,
271 .hid_width = 5,
272 .parent_map = audio_core_cc_parent_map_0,
273 .freq_tbl = ftbl_audio_core_cc_aif_if0_clk_src,
274 .hw_clk_ctrl = true,
275 .clkr.hw.init = &(const struct clk_init_data) {
276 .name = "audio_core_cc_ext_mclka_clk_src",
277 .parent_data = audio_core_cc_parent_data_0,
278 .num_parents = ARRAY_SIZE(audio_core_cc_parent_data_0),
279 .flags = CLK_SET_RATE_PARENT,
280 .ops = &clk_rcg2_shared_ops,
281 },
282 };
283
284 static struct clk_rcg2 audio_core_cc_ext_mclkb_clk_src = {
285 .cmd_rcgr = 0x125c,
286 .mnd_width = 8,
287 .hid_width = 5,
288 .parent_map = audio_core_cc_parent_map_0,
289 .freq_tbl = ftbl_audio_core_cc_aif_if0_clk_src,
290 .hw_clk_ctrl = true,
291 .clkr.hw.init = &(const struct clk_init_data) {
292 .name = "audio_core_cc_ext_mclkb_clk_src",
293 .parent_data = audio_core_cc_parent_data_0,
294 .num_parents = ARRAY_SIZE(audio_core_cc_parent_data_0),
295 .flags = CLK_SET_RATE_PARENT,
296 .ops = &clk_rcg2_shared_ops,
297 },
298 };
299
300 static const struct freq_tbl ftbl_audio_core_cc_lpaif_pcmoe_clk_src[] = {
301 F(9600000, P_BI_TCXO, 2, 0, 0),
302 F(15360000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 8, 0, 0),
303 F(30720000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 4, 0, 0),
304 F(61440000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 2, 0, 0),
305 { }
306 };
307
308 static struct clk_rcg2 audio_core_cc_lpaif_pcmoe_clk_src = {
309 .cmd_rcgr = 0x12ac,
310 .mnd_width = 8,
311 .hid_width = 5,
312 .parent_map = audio_core_cc_parent_map_0,
313 .freq_tbl = ftbl_audio_core_cc_lpaif_pcmoe_clk_src,
314 .hw_clk_ctrl = true,
315 .clkr.hw.init = &(const struct clk_init_data) {
316 .name = "audio_core_cc_lpaif_pcmoe_clk_src",
317 .parent_data = audio_core_cc_parent_data_0,
318 .num_parents = ARRAY_SIZE(audio_core_cc_parent_data_0),
319 .flags = CLK_SET_RATE_PARENT,
320 .ops = &clk_rcg2_shared_ops,
321 },
322 };
323
324 static const struct freq_tbl ftbl_audio_core_cc_tx_mclk_rcg_clk_src[] = {
325 F(19200000, P_BI_TCXO, 1, 0, 0),
326 F(24576000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 5, 0, 0),
327 { }
328 };
329
330 static struct clk_rcg2 audio_core_cc_tx_mclk_rcg_clk_src = {
331 .cmd_rcgr = 0x127c,
332 .mnd_width = 8,
333 .hid_width = 5,
334 .parent_map = audio_core_cc_parent_map_0,
335 .freq_tbl = ftbl_audio_core_cc_tx_mclk_rcg_clk_src,
336 .hw_clk_ctrl = true,
337 .clkr.hw.init = &(const struct clk_init_data) {
338 .name = "audio_core_cc_tx_mclk_rcg_clk_src",
339 .parent_data = audio_core_cc_parent_data_0,
340 .num_parents = ARRAY_SIZE(audio_core_cc_parent_data_0),
341 .flags = CLK_SET_RATE_PARENT,
342 .ops = &clk_rcg2_shared_ops,
343 },
344 };
345
346 static struct clk_regmap_div audio_core_cc_cdiv_tx_mclk_div_clk_src = {
347 .reg = 0x129c,
348 .shift = 0,
349 .width = 4,
350 .clkr.hw.init = &(const struct clk_init_data) {
351 .name = "audio_core_cc_cdiv_tx_mclk_div_clk_src",
352 .parent_hws = (const struct clk_hw*[]) {
353 &audio_core_cc_tx_mclk_rcg_clk_src.clkr.hw,
354 },
355 .num_parents = 1,
356 .flags = CLK_SET_RATE_PARENT,
357 .ops = &clk_regmap_div_ro_ops,
358 },
359 };
360
361 static struct clk_branch audio_core_cc_aif_if0_ebit_clk = {
362 .halt_reg = 0x1068,
363 .halt_check = BRANCH_HALT_DELAY,
364 .clkr = {
365 .enable_reg = 0x1068,
366 .enable_mask = BIT(0),
367 .hw.init = &(const struct clk_init_data) {
368 .name = "audio_core_cc_aif_if0_ebit_clk",
369 .ops = &clk_branch2_ops,
370 },
371 },
372 };
373
374 static struct clk_branch audio_core_cc_aif_if0_ibit_clk = {
375 .halt_reg = 0x1064,
376 .halt_check = BRANCH_HALT,
377 .clkr = {
378 .enable_reg = 0x1064,
379 .enable_mask = BIT(0),
380 .hw.init = &(const struct clk_init_data) {
381 .name = "audio_core_cc_aif_if0_ibit_clk",
382 .parent_hws = (const struct clk_hw*[]) {
383 &audio_core_cc_aif_if0_clk_src.clkr.hw,
384 },
385 .num_parents = 1,
386 .flags = CLK_SET_RATE_PARENT,
387 .ops = &clk_branch2_ops,
388 },
389 },
390 };
391
392 static struct clk_branch audio_core_cc_aif_if1_ebit_clk = {
393 .halt_reg = 0x10cc,
394 .halt_check = BRANCH_HALT_DELAY,
395 .clkr = {
396 .enable_reg = 0x10cc,
397 .enable_mask = BIT(0),
398 .hw.init = &(const struct clk_init_data) {
399 .name = "audio_core_cc_aif_if1_ebit_clk",
400 .ops = &clk_branch2_ops,
401 },
402 },
403 };
404
405 static struct clk_branch audio_core_cc_aif_if1_ibit_clk = {
406 .halt_reg = 0x10c8,
407 .halt_check = BRANCH_HALT,
408 .clkr = {
409 .enable_reg = 0x10c8,
410 .enable_mask = BIT(0),
411 .hw.init = &(const struct clk_init_data) {
412 .name = "audio_core_cc_aif_if1_ibit_clk",
413 .parent_hws = (const struct clk_hw*[]) {
414 &audio_core_cc_aif_if1_clk_src.clkr.hw,
415 },
416 .num_parents = 1,
417 .flags = CLK_SET_RATE_PARENT,
418 .ops = &clk_branch2_ops,
419 },
420 },
421 };
422
423 static struct clk_branch audio_core_cc_aif_if2_ebit_clk = {
424 .halt_reg = 0x1130,
425 .halt_check = BRANCH_HALT_DELAY,
426 .clkr = {
427 .enable_reg = 0x1130,
428 .enable_mask = BIT(0),
429 .hw.init = &(const struct clk_init_data) {
430 .name = "audio_core_cc_aif_if2_ebit_clk",
431 .ops = &clk_branch2_ops,
432 },
433 },
434 };
435
436 static struct clk_branch audio_core_cc_aif_if2_ibit_clk = {
437 .halt_reg = 0x112c,
438 .halt_check = BRANCH_HALT,
439 .clkr = {
440 .enable_reg = 0x112c,
441 .enable_mask = BIT(0),
442 .hw.init = &(const struct clk_init_data) {
443 .name = "audio_core_cc_aif_if2_ibit_clk",
444 .parent_hws = (const struct clk_hw*[]) {
445 &audio_core_cc_aif_if2_clk_src.clkr.hw,
446 },
447 .num_parents = 1,
448 .flags = CLK_SET_RATE_PARENT,
449 .ops = &clk_branch2_ops,
450 },
451 },
452 };
453
454 static struct clk_branch audio_core_cc_aif_if3_ebit_clk = {
455 .halt_reg = 0x1194,
456 .halt_check = BRANCH_HALT_DELAY,
457 .clkr = {
458 .enable_reg = 0x1194,
459 .enable_mask = BIT(0),
460 .hw.init = &(const struct clk_init_data) {
461 .name = "audio_core_cc_aif_if3_ebit_clk",
462 .ops = &clk_branch2_ops,
463 },
464 },
465 };
466
467 static struct clk_branch audio_core_cc_aif_if3_ibit_clk = {
468 .halt_reg = 0x1190,
469 .halt_check = BRANCH_HALT,
470 .clkr = {
471 .enable_reg = 0x1190,
472 .enable_mask = BIT(0),
473 .hw.init = &(const struct clk_init_data) {
474 .name = "audio_core_cc_aif_if3_ibit_clk",
475 .parent_hws = (const struct clk_hw*[]) {
476 &audio_core_cc_aif_if3_clk_src.clkr.hw,
477 },
478 .num_parents = 1,
479 .flags = CLK_SET_RATE_PARENT,
480 .ops = &clk_branch2_ops,
481 },
482 },
483 };
484
485 static struct clk_branch audio_core_cc_aud_dma_clk = {
486 .halt_reg = 0x1040,
487 .halt_check = BRANCH_HALT,
488 .hwcg_reg = 0x1040,
489 .hwcg_bit = 1,
490 .clkr = {
491 .enable_reg = 0x1040,
492 .enable_mask = BIT(0),
493 .hw.init = &(const struct clk_init_data) {
494 .name = "audio_core_cc_aud_dma_clk",
495 .parent_hws = (const struct clk_hw*[]) {
496 &audio_core_cc_aud_dma_clk_src.clkr.hw,
497 },
498 .num_parents = 1,
499 .flags = CLK_SET_RATE_PARENT,
500 .ops = &clk_branch2_ops,
501 },
502 },
503 };
504
505 static struct clk_branch audio_core_cc_aud_dma_mem_clk = {
506 .halt_reg = 0x1044,
507 .halt_check = BRANCH_HALT,
508 .hwcg_reg = 0x1044,
509 .hwcg_bit = 1,
510 .clkr = {
511 .enable_reg = 0x1044,
512 .enable_mask = BIT(0),
513 .hw.init = &(const struct clk_init_data) {
514 .name = "audio_core_cc_aud_dma_mem_clk",
515 .parent_hws = (const struct clk_hw*[]) {
516 &audio_core_cc_aud_dma_clk_src.clkr.hw,
517 },
518 .num_parents = 1,
519 .flags = CLK_SET_RATE_PARENT,
520 .ops = &clk_branch2_ops,
521 },
522 },
523 };
524
525 static struct clk_branch audio_core_cc_bus_clk = {
526 .halt_reg = 0x1020,
527 .halt_check = BRANCH_HALT_VOTED,
528 .clkr = {
529 .enable_reg = 0x1020,
530 .enable_mask = BIT(0),
531 .hw.init = &(const struct clk_init_data) {
532 .name = "audio_core_cc_bus_clk",
533 .parent_hws = (const struct clk_hw*[]) {
534 &audio_core_cc_bus_clk_src.clkr.hw,
535 },
536 .num_parents = 1,
537 .flags = CLK_SET_RATE_PARENT,
538 .ops = &clk_branch2_aon_ops,
539 },
540 },
541 };
542
543 static struct clk_branch audio_core_cc_ext_mclka_out_clk = {
544 .halt_reg = 0x1254,
545 .halt_check = BRANCH_HALT,
546 .clkr = {
547 .enable_reg = 0x1254,
548 .enable_mask = BIT(0),
549 .hw.init = &(const struct clk_init_data) {
550 .name = "audio_core_cc_ext_mclka_out_clk",
551 .parent_hws = (const struct clk_hw*[]) {
552 &audio_core_cc_ext_mclka_clk_src.clkr.hw,
553 },
554 .num_parents = 1,
555 .flags = CLK_SET_RATE_PARENT,
556 .ops = &clk_branch2_ops,
557 },
558 },
559 };
560
561 static struct clk_branch audio_core_cc_ext_mclkb_out_clk = {
562 .halt_reg = 0x1274,
563 .halt_check = BRANCH_HALT,
564 .clkr = {
565 .enable_reg = 0x1274,
566 .enable_mask = BIT(0),
567 .hw.init = &(const struct clk_init_data) {
568 .name = "audio_core_cc_ext_mclkb_out_clk",
569 .parent_hws = (const struct clk_hw*[]) {
570 &audio_core_cc_ext_mclkb_clk_src.clkr.hw,
571 },
572 .num_parents = 1,
573 .flags = CLK_SET_RATE_PARENT,
574 .ops = &clk_branch2_ops,
575 },
576 },
577 };
578
579 static struct clk_branch audio_core_cc_im_sleep_clk = {
580 .halt_reg = 0x12cc,
581 .halt_check = BRANCH_HALT,
582 .clkr = {
583 .enable_reg = 0x12cc,
584 .enable_mask = BIT(0),
585 .hw.init = &(const struct clk_init_data) {
586 .name = "audio_core_cc_im_sleep_clk",
587 .ops = &clk_branch2_ops,
588 },
589 },
590 };
591
592 static struct clk_branch audio_core_cc_lpaif_pcmoe_clk = {
593 .halt_reg = 0x12c4,
594 .halt_check = BRANCH_HALT,
595 .clkr = {
596 .enable_reg = 0x12c4,
597 .enable_mask = BIT(0),
598 .hw.init = &(const struct clk_init_data) {
599 .name = "audio_core_cc_lpaif_pcmoe_clk",
600 .parent_hws = (const struct clk_hw*[]) {
601 &audio_core_cc_lpaif_pcmoe_clk_src.clkr.hw,
602 },
603 .num_parents = 1,
604 .flags = CLK_SET_RATE_PARENT,
605 .ops = &clk_branch2_ops,
606 },
607 },
608 };
609
610 static struct clk_branch audio_core_cc_rx_mclk_2x_clk = {
611 .halt_reg = 0x1298,
612 .halt_check = BRANCH_HALT,
613 .clkr = {
614 .enable_reg = 0x1298,
615 .enable_mask = BIT(0),
616 .hw.init = &(const struct clk_init_data) {
617 .name = "audio_core_cc_rx_mclk_2x_clk",
618 .parent_hws = (const struct clk_hw*[]) {
619 &audio_core_cc_tx_mclk_rcg_clk_src.clkr.hw,
620 },
621 .num_parents = 1,
622 .flags = CLK_SET_RATE_PARENT,
623 .ops = &clk_branch2_ops,
624 },
625 },
626 };
627
628 static struct clk_branch audio_core_cc_rx_mclk_clk = {
629 .halt_reg = 0x12a4,
630 .halt_check = BRANCH_HALT,
631 .clkr = {
632 .enable_reg = 0x12a4,
633 .enable_mask = BIT(0),
634 .hw.init = &(const struct clk_init_data) {
635 .name = "audio_core_cc_rx_mclk_clk",
636 .parent_hws = (const struct clk_hw*[]) {
637 &audio_core_cc_cdiv_tx_mclk_div_clk_src.clkr.hw,
638 },
639 .num_parents = 1,
640 .flags = CLK_SET_RATE_PARENT,
641 .ops = &clk_branch2_ops,
642 },
643 },
644 };
645
646 static struct clk_branch audio_core_cc_sampling_clk = {
647 .halt_reg = 0x1000,
648 .halt_check = BRANCH_HALT,
649 .clkr = {
650 .enable_reg = 0x1000,
651 .enable_mask = BIT(0),
652 .hw.init = &(const struct clk_init_data) {
653 .name = "audio_core_cc_sampling_clk",
654 .ops = &clk_branch2_ops,
655 },
656 },
657 };
658
659 static struct clk_branch audio_core_cc_tx_mclk_2x_clk = {
660 .halt_reg = 0x1294,
661 .halt_check = BRANCH_HALT,
662 .clkr = {
663 .enable_reg = 0x1294,
664 .enable_mask = BIT(0),
665 .hw.init = &(const struct clk_init_data) {
666 .name = "audio_core_cc_tx_mclk_2x_clk",
667 .parent_hws = (const struct clk_hw*[]) {
668 &audio_core_cc_tx_mclk_rcg_clk_src.clkr.hw,
669 },
670 .num_parents = 1,
671 .flags = CLK_SET_RATE_PARENT,
672 .ops = &clk_branch2_ops,
673 },
674 },
675 };
676
677 static struct clk_branch audio_core_cc_tx_mclk_clk = {
678 .halt_reg = 0x12a0,
679 .halt_check = BRANCH_HALT,
680 .clkr = {
681 .enable_reg = 0x12a0,
682 .enable_mask = BIT(0),
683 .hw.init = &(const struct clk_init_data) {
684 .name = "audio_core_cc_tx_mclk_clk",
685 .parent_hws = (const struct clk_hw*[]) {
686 &audio_core_cc_cdiv_tx_mclk_div_clk_src.clkr.hw,
687 },
688 .num_parents = 1,
689 .flags = CLK_SET_RATE_PARENT,
690 .ops = &clk_branch2_ops,
691 },
692 },
693 };
694
695 static struct clk_hw *audio_core_cc_shikra_hws[] = {
696 [AUDIO_CORE_CC_DIG_PLL_OUT_AUX] = &audio_core_cc_dig_pll_out_aux.hw,
697 [AUDIO_CORE_CC_DIG_PLL_OUT_AUX2] = &audio_core_cc_dig_pll_out_aux2.hw,
698 };
699
700 static struct clk_regmap *audio_core_cc_shikra_clocks[] = {
701 [AUDIO_CORE_CC_AIF_IF0_CLK_SRC] = &audio_core_cc_aif_if0_clk_src.clkr,
702 [AUDIO_CORE_CC_AIF_IF0_EBIT_CLK] = &audio_core_cc_aif_if0_ebit_clk.clkr,
703 [AUDIO_CORE_CC_AIF_IF0_IBIT_CLK] = &audio_core_cc_aif_if0_ibit_clk.clkr,
704 [AUDIO_CORE_CC_AIF_IF1_CLK_SRC] = &audio_core_cc_aif_if1_clk_src.clkr,
705 [AUDIO_CORE_CC_AIF_IF1_EBIT_CLK] = &audio_core_cc_aif_if1_ebit_clk.clkr,
706 [AUDIO_CORE_CC_AIF_IF1_IBIT_CLK] = &audio_core_cc_aif_if1_ibit_clk.clkr,
707 [AUDIO_CORE_CC_AIF_IF2_CLK_SRC] = &audio_core_cc_aif_if2_clk_src.clkr,
708 [AUDIO_CORE_CC_AIF_IF2_EBIT_CLK] = &audio_core_cc_aif_if2_ebit_clk.clkr,
709 [AUDIO_CORE_CC_AIF_IF2_IBIT_CLK] = &audio_core_cc_aif_if2_ibit_clk.clkr,
710 [AUDIO_CORE_CC_AIF_IF3_CLK_SRC] = &audio_core_cc_aif_if3_clk_src.clkr,
711 [AUDIO_CORE_CC_AIF_IF3_EBIT_CLK] = &audio_core_cc_aif_if3_ebit_clk.clkr,
712 [AUDIO_CORE_CC_AIF_IF3_IBIT_CLK] = &audio_core_cc_aif_if3_ibit_clk.clkr,
713 [AUDIO_CORE_CC_AUD_DMA_CLK] = &audio_core_cc_aud_dma_clk.clkr,
714 [AUDIO_CORE_CC_AUD_DMA_CLK_SRC] = &audio_core_cc_aud_dma_clk_src.clkr,
715 [AUDIO_CORE_CC_AUD_DMA_MEM_CLK] = &audio_core_cc_aud_dma_mem_clk.clkr,
716 [AUDIO_CORE_CC_BUS_CLK] = &audio_core_cc_bus_clk.clkr,
717 [AUDIO_CORE_CC_BUS_CLK_SRC] = &audio_core_cc_bus_clk_src.clkr,
718 [AUDIO_CORE_CC_CDIV_TX_MCLK_DIV_CLK_SRC] = &audio_core_cc_cdiv_tx_mclk_div_clk_src.clkr,
719 [AUDIO_CORE_CC_DIG_PLL] = &audio_core_cc_dig_pll.clkr,
720 [AUDIO_CORE_CC_EXT_MCLKA_CLK_SRC] = &audio_core_cc_ext_mclka_clk_src.clkr,
721 [AUDIO_CORE_CC_EXT_MCLKA_OUT_CLK] = &audio_core_cc_ext_mclka_out_clk.clkr,
722 [AUDIO_CORE_CC_EXT_MCLKB_CLK_SRC] = &audio_core_cc_ext_mclkb_clk_src.clkr,
723 [AUDIO_CORE_CC_EXT_MCLKB_OUT_CLK] = &audio_core_cc_ext_mclkb_out_clk.clkr,
724 [AUDIO_CORE_CC_IM_SLEEP_CLK] = &audio_core_cc_im_sleep_clk.clkr,
725 [AUDIO_CORE_CC_LPAIF_PCMOE_CLK] = &audio_core_cc_lpaif_pcmoe_clk.clkr,
726 [AUDIO_CORE_CC_LPAIF_PCMOE_CLK_SRC] = &audio_core_cc_lpaif_pcmoe_clk_src.clkr,
727 [AUDIO_CORE_CC_RX_MCLK_2X_CLK] = &audio_core_cc_rx_mclk_2x_clk.clkr,
728 [AUDIO_CORE_CC_RX_MCLK_CLK] = &audio_core_cc_rx_mclk_clk.clkr,
729 [AUDIO_CORE_CC_SAMPLING_CLK] = &audio_core_cc_sampling_clk.clkr,
730 [AUDIO_CORE_CC_TX_MCLK_2X_CLK] = &audio_core_cc_tx_mclk_2x_clk.clkr,
731 [AUDIO_CORE_CC_TX_MCLK_CLK] = &audio_core_cc_tx_mclk_clk.clkr,
732 [AUDIO_CORE_CC_TX_MCLK_RCG_CLK_SRC] = &audio_core_cc_tx_mclk_rcg_clk_src.clkr,
733 };
734
735 static struct clk_alpha_pll *audio_core_cc_shikra_plls[] = {
736 &audio_core_cc_dig_pll,
737 };
738
739 static const struct qcom_cc_driver_data audio_core_cc_shikra_driver_data = {
740 .alpha_plls = audio_core_cc_shikra_plls,
741 .num_alpha_plls = ARRAY_SIZE(audio_core_cc_shikra_plls),
742 };
743
744 static const struct regmap_config audio_core_cc_shikra_regmap_config = {
745 .reg_bits = 32,
746 .reg_stride = 4,
747 .val_bits = 32,
748 .max_register = 0x305c,
749 .fast_io = true,
750 };
751
752 static const struct qcom_reset_map audio_core_csr_shikra_resets[] = {
753 [AUDIO_CORE_CSR_RX_SWR_CGCR] = { 0x1c, 1 },
754 [AUDIO_CORE_CSR_TX_SWR_CGCR] = { 0x30, 1 },
755 };
756
757 static const struct regmap_config audio_core_csr_shikra_regmap_config = {
758 .name = "audio_core_cc_shikra_reset",
759 .reg_bits = 32,
760 .reg_stride = 4,
761 .val_bits = 32,
762 .fast_io = true,
763 .max_register = 0x34,
764 };
765
766 static const struct qcom_cc_desc audio_core_csr_shikra_desc = {
767 .config = &audio_core_csr_shikra_regmap_config,
768 .resets = audio_core_csr_shikra_resets,
769 .num_resets = ARRAY_SIZE(audio_core_csr_shikra_resets),
770 };
771
772 static const struct qcom_cc_desc audio_core_cc_shikra_desc = {
773 .config = &audio_core_cc_shikra_regmap_config,
774 .clk_hws = audio_core_cc_shikra_hws,
775 .num_clk_hws = ARRAY_SIZE(audio_core_cc_shikra_hws),
776 .clks = audio_core_cc_shikra_clocks,
777 .num_clks = ARRAY_SIZE(audio_core_cc_shikra_clocks),
778 .driver_data = &audio_core_cc_shikra_driver_data,
779 };
780
781 static const struct of_device_id audio_core_cc_shikra_match_table[] = {
782 { .compatible = "qcom,shikra-audiocorecc", .data = &audio_core_cc_shikra_desc },
783 { .compatible = "qcom,shikra-audiocore-csr", .data = &audio_core_csr_shikra_desc },
784 { }
785 };
786 MODULE_DEVICE_TABLE(of, audio_core_cc_shikra_match_table);
787
audio_core_cc_shikra_probe(struct platform_device * pdev)788 static int audio_core_cc_shikra_probe(struct platform_device *pdev)
789 {
790 const struct qcom_cc_desc *desc;
791
792 desc = device_get_match_data(&pdev->dev);
793 if (!desc)
794 return -EINVAL;
795
796 return qcom_cc_probe(pdev, desc);
797 }
798
799 static struct platform_driver audio_core_cc_shikra_driver = {
800 .probe = audio_core_cc_shikra_probe,
801 .driver = {
802 .name = "audiocorecc-shikra",
803 .of_match_table = audio_core_cc_shikra_match_table,
804 },
805 };
806
807 module_platform_driver(audio_core_cc_shikra_driver);
808
809 MODULE_DESCRIPTION("QTI AUDIOCORECC Shikra Driver");
810 MODULE_LICENSE("GPL");
811