1 // SPDX-License-Identifier: (GPL-2.0-only OR MIT) 2 /* 3 * Copyright (C) 2024-2025 Amlogic, Inc. All rights reserved. 4 * Author: Jian Hu <jian.hu@amlogic.com> 5 */ 6 7 #include <linux/clk-provider.h> 8 #include <linux/platform_device.h> 9 #include "clk-dualdiv.h" 10 #include "clk-regmap.h" 11 #include "meson-clkc-utils.h" 12 #include <dt-bindings/clock/amlogic,t7-peripherals-clkc.h> 13 14 #define RTC_BY_OSCIN_CTRL0 0x8 15 #define RTC_BY_OSCIN_CTRL1 0xc 16 #define RTC_CTRL 0x10 17 #define SYS_CLK_CTRL0 0x40 18 #define SYS_CLK_EN0_REG0 0x44 19 #define SYS_CLK_EN0_REG1 0x48 20 #define SYS_CLK_EN0_REG2 0x4c 21 #define SYS_CLK_EN0_REG3 0x50 22 #define CECA_CTRL0 0x88 23 #define CECA_CTRL1 0x8c 24 #define CECB_CTRL0 0x90 25 #define CECB_CTRL1 0x94 26 #define SC_CLK_CTRL 0x98 27 #define DSPA_CLK_CTRL0 0x9c 28 #define DSPB_CLK_CTRL0 0xa0 29 #define CLK12_24_CTRL 0xa8 30 #define ANAKIN_CLK_CTRL 0xac 31 #define MIPI_CSI_PHY_CLK_CTRL 0x10c 32 #define MIPI_ISP_CLK_CTRL 0x110 33 #define TS_CLK_CTRL 0x158 34 #define MALI_CLK_CTRL 0x15c 35 #define ETH_CLK_CTRL 0x164 36 #define NAND_CLK_CTRL 0x168 37 #define SD_EMMC_CLK_CTRL 0x16c 38 #define SPICC_CLK_CTRL 0x174 39 #define SAR_CLK_CTRL0 0x17c 40 #define PWM_CLK_AB_CTRL 0x180 41 #define PWM_CLK_CD_CTRL 0x184 42 #define PWM_CLK_EF_CTRL 0x188 43 #define PWM_CLK_AO_AB_CTRL 0x1a0 44 #define PWM_CLK_AO_CD_CTRL 0x1a4 45 #define PWM_CLK_AO_EF_CTRL 0x1a8 46 #define PWM_CLK_AO_GH_CTRL 0x1ac 47 #define SPICC_CLK_CTRL1 0x1c0 48 #define SPICC_CLK_CTRL2 0x1c4 49 50 #define T7_COMP_SEL(_name, _reg, _shift, _mask, _pdata) \ 51 MESON_COMP_SEL(t7_, _name, _reg, _shift, _mask, _pdata, NULL, 0, 0) 52 53 #define T7_COMP_DIV(_name, _reg, _shift, _width) \ 54 MESON_COMP_DIV(t7_, _name, _reg, _shift, _width, 0, CLK_SET_RATE_PARENT) 55 56 #define T7_COMP_GATE(_name, _reg, _bit, _iflags) \ 57 MESON_COMP_GATE(t7_, _name, _reg, _bit, CLK_SET_RATE_PARENT | (_iflags)) 58 59 static struct clk_regmap t7_rtc_dualdiv_in = { 60 .data = &(struct clk_regmap_gate_data){ 61 .offset = RTC_BY_OSCIN_CTRL0, 62 .bit_idx = 31, 63 }, 64 .hw.init = &(struct clk_init_data) { 65 .name = "rtc_duandiv_in", 66 .ops = &clk_regmap_gate_ops, 67 .parent_data = &(const struct clk_parent_data) { 68 .fw_name = "xtal", 69 }, 70 .num_parents = 1, 71 }, 72 }; 73 74 static const struct meson_clk_dualdiv_param t7_dualdiv_table[] = { 75 { 76 .n1 = 733, .m1 = 8, 77 .n2 = 732, .m2 = 11, 78 .dual = 1, 79 }, 80 {} 81 }; 82 83 static struct clk_regmap t7_rtc_dualdiv_div = { 84 .data = &(struct meson_clk_dualdiv_data){ 85 .n1 = { 86 .reg_off = RTC_BY_OSCIN_CTRL0, 87 .shift = 0, 88 .width = 12, 89 }, 90 .n2 = { 91 .reg_off = RTC_BY_OSCIN_CTRL0, 92 .shift = 12, 93 .width = 12, 94 }, 95 .m1 = { 96 .reg_off = RTC_BY_OSCIN_CTRL1, 97 .shift = 0, 98 .width = 12, 99 }, 100 .m2 = { 101 .reg_off = RTC_BY_OSCIN_CTRL1, 102 .shift = 12, 103 .width = 12, 104 }, 105 .dual = { 106 .reg_off = RTC_BY_OSCIN_CTRL0, 107 .shift = 28, 108 .width = 1, 109 }, 110 .table = t7_dualdiv_table, 111 }, 112 .hw.init = &(struct clk_init_data){ 113 .name = "rtc_dualdiv_div", 114 .ops = &meson_clk_dualdiv_ops, 115 .parent_hws = (const struct clk_hw *[]) { 116 &t7_rtc_dualdiv_in.hw 117 }, 118 .num_parents = 1, 119 }, 120 }; 121 122 static struct clk_regmap t7_rtc_dualdiv_sel = { 123 .data = &(struct clk_regmap_mux_data) { 124 .offset = RTC_BY_OSCIN_CTRL1, 125 .mask = 0x1, 126 .shift = 24, 127 }, 128 .hw.init = &(struct clk_init_data){ 129 .name = "rtc_dualdiv_sel", 130 .ops = &clk_regmap_mux_ops, 131 .parent_hws = (const struct clk_hw *[]) { 132 &t7_rtc_dualdiv_div.hw, 133 &t7_rtc_dualdiv_in.hw, 134 }, 135 .num_parents = 2, 136 .flags = CLK_SET_RATE_PARENT, 137 }, 138 }; 139 140 static struct clk_regmap t7_rtc_dualdiv = { 141 .data = &(struct clk_regmap_gate_data){ 142 .offset = RTC_BY_OSCIN_CTRL0, 143 .bit_idx = 30, 144 }, 145 .hw.init = &(struct clk_init_data) { 146 .name = "rtc_dualdiv", 147 .ops = &clk_regmap_gate_ops, 148 .parent_hws = (const struct clk_hw *[]) { 149 &t7_rtc_dualdiv_sel.hw 150 }, 151 .num_parents = 1, 152 .flags = CLK_SET_RATE_PARENT, 153 }, 154 }; 155 156 static struct clk_regmap t7_rtc = { 157 .data = &(struct clk_regmap_mux_data) { 158 .offset = RTC_CTRL, 159 .mask = 0x3, 160 .shift = 0, 161 }, 162 .hw.init = &(struct clk_init_data){ 163 .name = "rtc", 164 .ops = &clk_regmap_mux_ops, 165 /* 166 * xtal is also on parent input #3 but that it is not useful to CCF since 167 * the same parent is available with parent input #0 168 */ 169 .parent_data = (const struct clk_parent_data []) { 170 { .fw_name = "xtal", }, 171 { .hw = &t7_rtc_dualdiv.hw }, 172 { .fw_name = "ext_rtc", }, 173 }, 174 .num_parents = 2, 175 .flags = CLK_SET_RATE_NO_REPARENT, 176 }, 177 }; 178 179 static struct clk_regmap t7_ceca_dualdiv_in = { 180 .data = &(struct clk_regmap_gate_data){ 181 .offset = CECA_CTRL0, 182 .bit_idx = 31, 183 }, 184 .hw.init = &(struct clk_init_data) { 185 .name = "ceca_dualdiv_in", 186 .ops = &clk_regmap_gate_ops, 187 .parent_data = &(const struct clk_parent_data) { 188 .fw_name = "xtal", 189 }, 190 .num_parents = 1, 191 }, 192 }; 193 194 static struct clk_regmap t7_ceca_dualdiv_div = { 195 .data = &(struct meson_clk_dualdiv_data){ 196 .n1 = { 197 .reg_off = CECA_CTRL0, 198 .shift = 0, 199 .width = 12, 200 }, 201 .n2 = { 202 .reg_off = CECA_CTRL0, 203 .shift = 12, 204 .width = 12, 205 }, 206 .m1 = { 207 .reg_off = CECA_CTRL1, 208 .shift = 0, 209 .width = 12, 210 }, 211 .m2 = { 212 .reg_off = CECA_CTRL1, 213 .shift = 12, 214 .width = 12, 215 }, 216 .dual = { 217 .reg_off = CECA_CTRL0, 218 .shift = 28, 219 .width = 1, 220 }, 221 .table = t7_dualdiv_table, 222 }, 223 .hw.init = &(struct clk_init_data){ 224 .name = "ceca_dualdiv_div", 225 .ops = &meson_clk_dualdiv_ops, 226 .parent_hws = (const struct clk_hw *[]) { 227 &t7_ceca_dualdiv_in.hw 228 }, 229 .num_parents = 1, 230 }, 231 }; 232 233 static struct clk_regmap t7_ceca_dualdiv_sel = { 234 .data = &(struct clk_regmap_mux_data) { 235 .offset = CECA_CTRL1, 236 .mask = 0x1, 237 .shift = 24, 238 }, 239 .hw.init = &(struct clk_init_data){ 240 .name = "ceca_dualdiv_sel", 241 .ops = &clk_regmap_mux_ops, 242 .parent_hws = (const struct clk_hw *[]) { 243 &t7_ceca_dualdiv_div.hw, 244 &t7_ceca_dualdiv_in.hw, 245 }, 246 .num_parents = 2, 247 .flags = CLK_SET_RATE_PARENT, 248 }, 249 }; 250 251 static struct clk_regmap t7_ceca_dualdiv = { 252 .data = &(struct clk_regmap_gate_data){ 253 .offset = CECA_CTRL0, 254 .bit_idx = 30, 255 }, 256 .hw.init = &(struct clk_init_data){ 257 .name = "ceca_dualdiv", 258 .ops = &clk_regmap_gate_ops, 259 .parent_hws = (const struct clk_hw *[]) { 260 &t7_ceca_dualdiv_sel.hw 261 }, 262 .num_parents = 1, 263 .flags = CLK_SET_RATE_PARENT, 264 }, 265 }; 266 267 static struct clk_regmap t7_ceca = { 268 .data = &(struct clk_regmap_mux_data) { 269 .offset = CECA_CTRL1, 270 .mask = 0x1, 271 .shift = 31, 272 }, 273 .hw.init = &(struct clk_init_data){ 274 .name = "ceca", 275 .ops = &clk_regmap_mux_ops, 276 .parent_hws = (const struct clk_hw *[]) { 277 &t7_ceca_dualdiv.hw, 278 &t7_rtc.hw, 279 }, 280 .num_parents = 2, 281 .flags = CLK_SET_RATE_PARENT, 282 }, 283 }; 284 285 static struct clk_regmap t7_cecb_dualdiv_in = { 286 .data = &(struct clk_regmap_gate_data){ 287 .offset = CECB_CTRL0, 288 .bit_idx = 31, 289 }, 290 .hw.init = &(struct clk_init_data) { 291 .name = "cecb_dualdiv_in", 292 .ops = &clk_regmap_gate_ops, 293 .parent_data = &(const struct clk_parent_data) { 294 .fw_name = "xtal", 295 }, 296 .num_parents = 1, 297 }, 298 }; 299 300 static struct clk_regmap t7_cecb_dualdiv_div = { 301 .data = &(struct meson_clk_dualdiv_data){ 302 .n1 = { 303 .reg_off = CECB_CTRL0, 304 .shift = 0, 305 .width = 12, 306 }, 307 .n2 = { 308 .reg_off = CECB_CTRL0, 309 .shift = 12, 310 .width = 12, 311 }, 312 .m1 = { 313 .reg_off = CECB_CTRL1, 314 .shift = 0, 315 .width = 12, 316 }, 317 .m2 = { 318 .reg_off = CECB_CTRL1, 319 .shift = 12, 320 .width = 12, 321 }, 322 .dual = { 323 .reg_off = CECB_CTRL0, 324 .shift = 28, 325 .width = 1, 326 }, 327 .table = t7_dualdiv_table, 328 }, 329 .hw.init = &(struct clk_init_data){ 330 .name = "cecb_dualdiv_div", 331 .ops = &meson_clk_dualdiv_ops, 332 .parent_hws = (const struct clk_hw *[]) { 333 &t7_cecb_dualdiv_in.hw 334 }, 335 .num_parents = 1, 336 }, 337 }; 338 339 static struct clk_regmap t7_cecb_dualdiv_sel = { 340 .data = &(struct clk_regmap_mux_data) { 341 .offset = CECB_CTRL1, 342 .mask = 0x1, 343 .shift = 24, 344 }, 345 .hw.init = &(struct clk_init_data){ 346 .name = "cecb_dualdiv_sel", 347 .ops = &clk_regmap_mux_ops, 348 .parent_hws = (const struct clk_hw *[]) { 349 &t7_cecb_dualdiv_div.hw, 350 &t7_cecb_dualdiv_in.hw, 351 }, 352 .num_parents = 2, 353 .flags = CLK_SET_RATE_PARENT, 354 }, 355 }; 356 357 static struct clk_regmap t7_cecb_dualdiv = { 358 .data = &(struct clk_regmap_gate_data){ 359 .offset = CECB_CTRL0, 360 .bit_idx = 30, 361 }, 362 .hw.init = &(struct clk_init_data){ 363 .name = "cecb_dualdiv", 364 .ops = &clk_regmap_gate_ops, 365 .parent_hws = (const struct clk_hw *[]) { 366 &t7_cecb_dualdiv_sel.hw 367 }, 368 .num_parents = 1, 369 .flags = CLK_SET_RATE_PARENT, 370 }, 371 }; 372 373 static struct clk_regmap t7_cecb = { 374 .data = &(struct clk_regmap_mux_data) { 375 .offset = CECB_CTRL1, 376 .mask = 0x1, 377 .shift = 31, 378 }, 379 .hw.init = &(struct clk_init_data){ 380 .name = "cecb", 381 .ops = &clk_regmap_mux_ops, 382 .parent_hws = (const struct clk_hw *[]) { 383 &t7_cecb_dualdiv.hw, 384 &t7_rtc.hw, 385 }, 386 .num_parents = 2, 387 .flags = CLK_SET_RATE_PARENT, 388 }, 389 }; 390 391 static const struct clk_parent_data t7_sc_parents[] = { 392 { .fw_name = "fdiv4", }, 393 { .fw_name = "fdiv3", }, 394 { .fw_name = "fdiv5", }, 395 { .fw_name = "xtal", }, 396 }; 397 398 static T7_COMP_SEL(sc, SC_CLK_CTRL, 9, 0x3, t7_sc_parents); 399 static T7_COMP_DIV(sc, SC_CLK_CTRL, 0, 8); 400 static T7_COMP_GATE(sc, SC_CLK_CTRL, 8, 0); 401 402 static const struct clk_parent_data t7_dsp_parents[] = { 403 { .fw_name = "xtal", }, 404 { .fw_name = "fdiv2p5", }, 405 { .fw_name = "fdiv3", }, 406 { .fw_name = "fdiv5", }, 407 { .fw_name = "hifi", }, 408 { .fw_name = "fdiv4", }, 409 { .fw_name = "fdiv7", }, 410 { .hw = &t7_rtc.hw }, 411 }; 412 413 static T7_COMP_SEL(dspa_0, DSPA_CLK_CTRL0, 10, 0x7, t7_dsp_parents); 414 static T7_COMP_DIV(dspa_0, DSPA_CLK_CTRL0, 0, 10); 415 static T7_COMP_GATE(dspa_0, DSPA_CLK_CTRL0, 13, CLK_SET_RATE_GATE); 416 417 static T7_COMP_SEL(dspa_1, DSPA_CLK_CTRL0, 26, 0x7, t7_dsp_parents); 418 static T7_COMP_DIV(dspa_1, DSPA_CLK_CTRL0, 16, 10); 419 static T7_COMP_GATE(dspa_1, DSPA_CLK_CTRL0, 29, CLK_SET_RATE_GATE); 420 421 static struct clk_regmap t7_dspa = { 422 .data = &(struct clk_regmap_mux_data){ 423 .offset = DSPA_CLK_CTRL0, 424 .mask = 0x1, 425 .shift = 15, 426 }, 427 .hw.init = &(struct clk_init_data){ 428 .name = "dspa", 429 .ops = &clk_regmap_mux_ops, 430 .parent_hws = (const struct clk_hw *[]) { 431 &t7_dspa_0.hw, 432 &t7_dspa_1.hw, 433 }, 434 .num_parents = 2, 435 .flags = CLK_SET_RATE_PARENT, 436 }, 437 }; 438 439 static T7_COMP_SEL(dspb_0, DSPB_CLK_CTRL0, 10, 0x7, t7_dsp_parents); 440 static T7_COMP_DIV(dspb_0, DSPB_CLK_CTRL0, 0, 10); 441 static T7_COMP_GATE(dspb_0, DSPB_CLK_CTRL0, 13, CLK_SET_RATE_GATE); 442 443 static T7_COMP_SEL(dspb_1, DSPB_CLK_CTRL0, 26, 0x7, t7_dsp_parents); 444 static T7_COMP_DIV(dspb_1, DSPB_CLK_CTRL0, 16, 10); 445 static T7_COMP_GATE(dspb_1, DSPB_CLK_CTRL0, 29, CLK_SET_RATE_GATE); 446 447 static struct clk_regmap t7_dspb = { 448 .data = &(struct clk_regmap_mux_data){ 449 .offset = DSPB_CLK_CTRL0, 450 .mask = 0x1, 451 .shift = 15, 452 }, 453 .hw.init = &(struct clk_init_data){ 454 .name = "dspb", 455 .ops = &clk_regmap_mux_ops, 456 .parent_hws = (const struct clk_hw *[]) { 457 &t7_dspb_0.hw, 458 &t7_dspb_1.hw, 459 }, 460 .num_parents = 2, 461 .flags = CLK_SET_RATE_PARENT, 462 }, 463 }; 464 465 static struct clk_regmap t7_24m = { 466 .data = &(struct clk_regmap_gate_data){ 467 .offset = CLK12_24_CTRL, 468 .bit_idx = 11, 469 }, 470 .hw.init = &(struct clk_init_data) { 471 .name = "24m", 472 .ops = &clk_regmap_gate_ops, 473 .parent_data = &(const struct clk_parent_data) { 474 .fw_name = "xtal", 475 }, 476 .num_parents = 1, 477 }, 478 }; 479 480 static struct clk_fixed_factor t7_24m_div2 = { 481 .mult = 1, 482 .div = 2, 483 .hw.init = &(struct clk_init_data){ 484 .name = "24m_div2", 485 .ops = &clk_fixed_factor_ops, 486 .parent_hws = (const struct clk_hw *[]) { 487 &t7_24m.hw 488 }, 489 .num_parents = 1, 490 }, 491 }; 492 493 static struct clk_regmap t7_12m = { 494 .data = &(struct clk_regmap_gate_data){ 495 .offset = CLK12_24_CTRL, 496 .bit_idx = 10, 497 }, 498 .hw.init = &(struct clk_init_data) { 499 .name = "12m", 500 .ops = &clk_regmap_gate_ops, 501 .parent_hws = (const struct clk_hw *[]) { 502 &t7_24m_div2.hw 503 }, 504 .num_parents = 1, 505 }, 506 }; 507 508 static struct clk_regmap t7_25m_div = { 509 .data = &(struct clk_regmap_div_data){ 510 .offset = CLK12_24_CTRL, 511 .shift = 0, 512 .width = 8, 513 }, 514 .hw.init = &(struct clk_init_data){ 515 .name = "25m_div", 516 .ops = &clk_regmap_divider_ops, 517 .parent_data = &(const struct clk_parent_data) { 518 .fw_name = "fix", 519 }, 520 .num_parents = 1, 521 }, 522 }; 523 524 static struct clk_regmap t7_25m = { 525 .data = &(struct clk_regmap_gate_data){ 526 .offset = CLK12_24_CTRL, 527 .bit_idx = 12, 528 }, 529 .hw.init = &(struct clk_init_data){ 530 .name = "25m", 531 .ops = &clk_regmap_gate_ops, 532 .parent_hws = (const struct clk_hw *[]) { 533 &t7_25m_div.hw 534 }, 535 .num_parents = 1, 536 .flags = CLK_SET_RATE_PARENT, 537 }, 538 }; 539 540 static const struct clk_parent_data t7_anakin_parents[] = { 541 { .fw_name = "fdiv4", }, 542 { .fw_name = "fdiv3", }, 543 { .fw_name = "fdiv5", }, 544 { .fw_name = "fdiv2", }, 545 { .fw_name = "vid_pll0", }, 546 { .fw_name = "mpll1", }, 547 { .fw_name = "mpll2", }, 548 { .fw_name = "fdiv2p5", }, 549 }; 550 551 static T7_COMP_SEL(anakin_0, ANAKIN_CLK_CTRL, 9, 0x7, t7_anakin_parents); 552 static T7_COMP_DIV(anakin_0, ANAKIN_CLK_CTRL, 0, 7); 553 static T7_COMP_GATE(anakin_0, ANAKIN_CLK_CTRL, 8, CLK_SET_RATE_GATE); 554 555 static T7_COMP_SEL(anakin_1, ANAKIN_CLK_CTRL, 25, 0x7, t7_anakin_parents); 556 static T7_COMP_DIV(anakin_1, ANAKIN_CLK_CTRL, 16, 7); 557 static T7_COMP_GATE(anakin_1, ANAKIN_CLK_CTRL, 24, CLK_SET_RATE_GATE); 558 559 static struct clk_regmap t7_anakin_01_sel = { 560 .data = &(struct clk_regmap_mux_data){ 561 .offset = ANAKIN_CLK_CTRL, 562 .mask = 1, 563 .shift = 31, 564 }, 565 .hw.init = &(struct clk_init_data){ 566 .name = "anakin_01_sel", 567 .ops = &clk_regmap_mux_ops, 568 .parent_hws = (const struct clk_hw *[]) { 569 &t7_anakin_0.hw, 570 &t7_anakin_1.hw 571 }, 572 .num_parents = 2, 573 .flags = CLK_SET_RATE_PARENT 574 }, 575 }; 576 577 static struct clk_regmap t7_anakin = { 578 .data = &(struct clk_regmap_gate_data){ 579 .offset = ANAKIN_CLK_CTRL, 580 .bit_idx = 30, 581 }, 582 .hw.init = &(struct clk_init_data) { 583 .name = "anakin", 584 .ops = &clk_regmap_gate_ops, 585 .parent_hws = (const struct clk_hw *[]) { 586 &t7_anakin_01_sel.hw 587 }, 588 .num_parents = 1, 589 .flags = CLK_SET_RATE_PARENT 590 }, 591 }; 592 593 static const struct clk_parent_data t7_mipi_csi_phy_parents[] = { 594 { .fw_name = "xtal", }, 595 { .fw_name = "gp1", }, 596 { .fw_name = "mpll1", }, 597 { .fw_name = "mpll2", }, 598 { .fw_name = "fdiv3", }, 599 { .fw_name = "fdiv4", }, 600 { .fw_name = "fdiv5", }, 601 { .fw_name = "fdiv7", }, 602 }; 603 604 static T7_COMP_SEL(mipi_csi_phy_0, MIPI_CSI_PHY_CLK_CTRL, 9, 0x7, t7_mipi_csi_phy_parents); 605 static T7_COMP_DIV(mipi_csi_phy_0, MIPI_CSI_PHY_CLK_CTRL, 0, 7); 606 static T7_COMP_GATE(mipi_csi_phy_0, MIPI_CSI_PHY_CLK_CTRL, 8, CLK_SET_RATE_GATE); 607 608 static T7_COMP_SEL(mipi_csi_phy_1, MIPI_CSI_PHY_CLK_CTRL, 25, 0x7, t7_mipi_csi_phy_parents); 609 static T7_COMP_DIV(mipi_csi_phy_1, MIPI_CSI_PHY_CLK_CTRL, 16, 7); 610 static T7_COMP_GATE(mipi_csi_phy_1, MIPI_CSI_PHY_CLK_CTRL, 24, CLK_SET_RATE_GATE); 611 612 static struct clk_regmap t7_mipi_csi_phy = { 613 .data = &(struct clk_regmap_mux_data){ 614 .offset = MIPI_CSI_PHY_CLK_CTRL, 615 .mask = 0x1, 616 .shift = 31, 617 }, 618 .hw.init = &(struct clk_init_data){ 619 .name = "mipi_csi_phy", 620 .ops = &clk_regmap_mux_ops, 621 .parent_hws = (const struct clk_hw *[]) { 622 &t7_mipi_csi_phy_0.hw, 623 &t7_mipi_csi_phy_1.hw 624 }, 625 .num_parents = 2, 626 .flags = CLK_SET_RATE_PARENT, 627 }, 628 }; 629 630 static const struct clk_parent_data t7_mipi_isp_parents[] = { 631 { .fw_name = "xtal", }, 632 { .fw_name = "fdiv4", }, 633 { .fw_name = "fdiv3", }, 634 { .fw_name = "fdiv5", }, 635 { .fw_name = "fdiv7", }, 636 { .fw_name = "mpll2", }, 637 { .fw_name = "mpll3", }, 638 { .fw_name = "gp1", }, 639 }; 640 641 static T7_COMP_SEL(mipi_isp, MIPI_ISP_CLK_CTRL, 9, 0x7, t7_mipi_isp_parents); 642 static T7_COMP_DIV(mipi_isp, MIPI_ISP_CLK_CTRL, 0, 7); 643 static T7_COMP_GATE(mipi_isp, MIPI_ISP_CLK_CTRL, 8, 0); 644 645 static struct clk_regmap t7_ts_div = { 646 .data = &(struct clk_regmap_div_data){ 647 .offset = TS_CLK_CTRL, 648 .shift = 0, 649 .width = 8, 650 }, 651 .hw.init = &(struct clk_init_data){ 652 .name = "ts_div", 653 .ops = &clk_regmap_divider_ops, 654 .parent_data = &(const struct clk_parent_data) { 655 .fw_name = "xtal", 656 }, 657 .num_parents = 1, 658 }, 659 }; 660 661 static struct clk_regmap t7_ts = { 662 .data = &(struct clk_regmap_gate_data){ 663 .offset = TS_CLK_CTRL, 664 .bit_idx = 8, 665 }, 666 .hw.init = &(struct clk_init_data){ 667 .name = "ts", 668 .ops = &clk_regmap_gate_ops, 669 .parent_hws = (const struct clk_hw *[]) { 670 &t7_ts_div.hw 671 }, 672 .num_parents = 1, 673 .flags = CLK_SET_RATE_PARENT, 674 }, 675 }; 676 677 static const struct clk_parent_data t7_mali_parents[] = { 678 { .fw_name = "xtal", }, 679 { .fw_name = "gp0", }, 680 { .fw_name = "gp1", }, 681 { .fw_name = "fdiv2p5", }, 682 { .fw_name = "fdiv3", }, 683 { .fw_name = "fdiv4", }, 684 { .fw_name = "fdiv5", }, 685 { .fw_name = "fdiv7", }, 686 }; 687 688 static T7_COMP_SEL(mali_0, MALI_CLK_CTRL, 9, 0x7, t7_mali_parents); 689 static T7_COMP_DIV(mali_0, MALI_CLK_CTRL, 0, 7); 690 static T7_COMP_GATE(mali_0, MALI_CLK_CTRL, 8, CLK_SET_RATE_GATE); 691 692 static T7_COMP_SEL(mali_1, MALI_CLK_CTRL, 25, 0x7, t7_mali_parents); 693 static T7_COMP_DIV(mali_1, MALI_CLK_CTRL, 16, 7); 694 static T7_COMP_GATE(mali_1, MALI_CLK_CTRL, 24, CLK_SET_RATE_GATE); 695 696 static struct clk_regmap t7_mali = { 697 .data = &(struct clk_regmap_mux_data){ 698 .offset = MALI_CLK_CTRL, 699 .mask = 1, 700 .shift = 31, 701 }, 702 .hw.init = &(struct clk_init_data){ 703 .name = "mali", 704 .ops = &clk_regmap_mux_ops, 705 .parent_hws = (const struct clk_hw *[]) { 706 &t7_mali_0.hw, 707 &t7_mali_1.hw, 708 }, 709 .num_parents = 2, 710 .flags = CLK_SET_RATE_PARENT, 711 }, 712 }; 713 714 /* 715 * parent index 2, 3, 4, 5, 6 not connect any clock signal, 716 * the last parent connect external PAD 717 */ 718 static u32 t7_eth_rmii_parents_val_table[] = { 0, 1, 7 }; 719 static const struct clk_parent_data t7_eth_rmii_parents[] = { 720 { .fw_name = "fdiv2", }, 721 { .fw_name = "gp1", }, 722 { .fw_name = "ext_rmii", }, 723 }; 724 725 static struct clk_regmap t7_eth_rmii_sel = { 726 .data = &(struct clk_regmap_mux_data) { 727 .offset = ETH_CLK_CTRL, 728 .mask = 0x7, 729 .shift = 9, 730 .table = t7_eth_rmii_parents_val_table, 731 }, 732 .hw.init = &(struct clk_init_data){ 733 .name = "eth_rmii_sel", 734 .ops = &clk_regmap_mux_ops, 735 .parent_data = t7_eth_rmii_parents, 736 .num_parents = ARRAY_SIZE(t7_eth_rmii_parents), 737 .flags = CLK_SET_RATE_NO_REPARENT, 738 }, 739 }; 740 741 static struct clk_regmap t7_eth_rmii_div = { 742 .data = &(struct clk_regmap_div_data) { 743 .offset = ETH_CLK_CTRL, 744 .shift = 0, 745 .width = 7, 746 }, 747 .hw.init = &(struct clk_init_data){ 748 .name = "eth_rmii_div", 749 .ops = &clk_regmap_divider_ops, 750 .parent_hws = (const struct clk_hw *[]) { 751 &t7_eth_rmii_sel.hw 752 }, 753 .num_parents = 1, 754 .flags = CLK_SET_RATE_PARENT, 755 }, 756 }; 757 758 static struct clk_regmap t7_eth_rmii = { 759 .data = &(struct clk_regmap_gate_data) { 760 .offset = ETH_CLK_CTRL, 761 .bit_idx = 8, 762 }, 763 .hw.init = &(struct clk_init_data){ 764 .name = "eth_rmii", 765 .ops = &clk_regmap_gate_ops, 766 .parent_hws = (const struct clk_hw *[]) { 767 &t7_eth_rmii_div.hw 768 }, 769 .num_parents = 1, 770 .flags = CLK_SET_RATE_PARENT, 771 }, 772 }; 773 774 static struct clk_fixed_factor t7_fdiv2_div8 = { 775 .mult = 1, 776 .div = 8, 777 .hw.init = &(struct clk_init_data){ 778 .name = "fdiv2_div8", 779 .ops = &clk_fixed_factor_ops, 780 .parent_data = &(const struct clk_parent_data) { 781 .fw_name = "fdiv2", 782 }, 783 .num_parents = 1, 784 }, 785 }; 786 787 static struct clk_regmap t7_eth_125m = { 788 .data = &(struct clk_regmap_gate_data) { 789 .offset = ETH_CLK_CTRL, 790 .bit_idx = 7, 791 }, 792 .hw.init = &(struct clk_init_data){ 793 .name = "eth_125m", 794 .ops = &clk_regmap_gate_ops, 795 .parent_hws = (const struct clk_hw *[]) { 796 &t7_fdiv2_div8.hw 797 }, 798 .num_parents = 1, 799 }, 800 }; 801 802 static const struct clk_parent_data t7_sd_emmc_parents[] = { 803 { .fw_name = "xtal", }, 804 { .fw_name = "fdiv2", }, 805 { .fw_name = "fdiv3", }, 806 { .fw_name = "hifi", }, 807 { .fw_name = "fdiv2p5", }, 808 { .fw_name = "mpll2", }, 809 { .fw_name = "mpll3", }, 810 { .fw_name = "gp0", }, 811 }; 812 813 static T7_COMP_SEL(sd_emmc_a, SD_EMMC_CLK_CTRL, 9, 0x7, t7_sd_emmc_parents); 814 static T7_COMP_DIV(sd_emmc_a, SD_EMMC_CLK_CTRL, 0, 7); 815 static T7_COMP_GATE(sd_emmc_a, SD_EMMC_CLK_CTRL, 7, 0); 816 817 static T7_COMP_SEL(sd_emmc_b, SD_EMMC_CLK_CTRL, 25, 0x7, t7_sd_emmc_parents); 818 static T7_COMP_DIV(sd_emmc_b, SD_EMMC_CLK_CTRL, 16, 7); 819 static T7_COMP_GATE(sd_emmc_b, SD_EMMC_CLK_CTRL, 23, 0); 820 821 static T7_COMP_SEL(sd_emmc_c, NAND_CLK_CTRL, 9, 0x7, t7_sd_emmc_parents); 822 static T7_COMP_DIV(sd_emmc_c, NAND_CLK_CTRL, 0, 7); 823 static T7_COMP_GATE(sd_emmc_c, NAND_CLK_CTRL, 7, 0); 824 825 static const struct clk_parent_data t7_spicc_parents[] = { 826 { .fw_name = "xtal", }, 827 { .fw_name = "sys", }, 828 { .fw_name = "fdiv4", }, 829 { .fw_name = "fdiv3", }, 830 { .fw_name = "fdiv2", }, 831 { .fw_name = "fdiv5", }, 832 { .fw_name = "fdiv7", }, 833 { .fw_name = "gp1", }, 834 }; 835 836 static T7_COMP_SEL(spicc0, SPICC_CLK_CTRL, 7, 0x7, t7_spicc_parents); 837 static T7_COMP_DIV(spicc0, SPICC_CLK_CTRL, 0, 6); 838 static T7_COMP_GATE(spicc0, SPICC_CLK_CTRL, 6, 0); 839 840 static T7_COMP_SEL(spicc1, SPICC_CLK_CTRL, 23, 0x7, t7_spicc_parents); 841 static T7_COMP_DIV(spicc1, SPICC_CLK_CTRL, 16, 6); 842 static T7_COMP_GATE(spicc1, SPICC_CLK_CTRL, 22, 0); 843 844 static T7_COMP_SEL(spicc2, SPICC_CLK_CTRL1, 7, 0x7, t7_spicc_parents); 845 static T7_COMP_DIV(spicc2, SPICC_CLK_CTRL1, 0, 6); 846 static T7_COMP_GATE(spicc2, SPICC_CLK_CTRL1, 6, 0); 847 848 static T7_COMP_SEL(spicc3, SPICC_CLK_CTRL1, 23, 0x7, t7_spicc_parents); 849 static T7_COMP_DIV(spicc3, SPICC_CLK_CTRL1, 16, 6); 850 static T7_COMP_GATE(spicc3, SPICC_CLK_CTRL1, 22, 0); 851 852 static T7_COMP_SEL(spicc4, SPICC_CLK_CTRL2, 7, 0x7, t7_spicc_parents); 853 static T7_COMP_DIV(spicc4, SPICC_CLK_CTRL2, 0, 6); 854 static T7_COMP_GATE(spicc4, SPICC_CLK_CTRL2, 6, 0); 855 856 static T7_COMP_SEL(spicc5, SPICC_CLK_CTRL2, 23, 0x7, t7_spicc_parents); 857 static T7_COMP_DIV(spicc5, SPICC_CLK_CTRL2, 16, 6); 858 static T7_COMP_GATE(spicc5, SPICC_CLK_CTRL2, 22, 0); 859 860 static const struct clk_parent_data t7_saradc_parents[] = { 861 { .fw_name = "xtal" }, 862 { .fw_name = "sys" }, 863 }; 864 865 static T7_COMP_SEL(saradc, SAR_CLK_CTRL0, 9, 0x1, t7_saradc_parents); 866 static T7_COMP_DIV(saradc, SAR_CLK_CTRL0, 0, 8); 867 static T7_COMP_GATE(saradc, SAR_CLK_CTRL0, 8, 0); 868 869 static const struct clk_parent_data t7_pwm_parents[] = { 870 { .fw_name = "xtal", }, 871 { .fw_name = "vid_pll0", }, 872 { .fw_name = "fdiv4", }, 873 { .fw_name = "fdiv3", }, 874 }; 875 876 static T7_COMP_SEL(pwm_a, PWM_CLK_AB_CTRL, 9, 0x3, t7_pwm_parents); 877 static T7_COMP_DIV(pwm_a, PWM_CLK_AB_CTRL, 0, 8); 878 static T7_COMP_GATE(pwm_a, PWM_CLK_AB_CTRL, 8, 0); 879 880 static T7_COMP_SEL(pwm_b, PWM_CLK_AB_CTRL, 25, 0x3, t7_pwm_parents); 881 static T7_COMP_DIV(pwm_b, PWM_CLK_AB_CTRL, 16, 8); 882 static T7_COMP_GATE(pwm_b, PWM_CLK_AB_CTRL, 24, 0); 883 884 static T7_COMP_SEL(pwm_c, PWM_CLK_CD_CTRL, 9, 0x3, t7_pwm_parents); 885 static T7_COMP_DIV(pwm_c, PWM_CLK_CD_CTRL, 0, 8); 886 static T7_COMP_GATE(pwm_c, PWM_CLK_CD_CTRL, 8, 0); 887 888 static T7_COMP_SEL(pwm_d, PWM_CLK_CD_CTRL, 25, 0x3, t7_pwm_parents); 889 static T7_COMP_DIV(pwm_d, PWM_CLK_CD_CTRL, 16, 8); 890 static T7_COMP_GATE(pwm_d, PWM_CLK_CD_CTRL, 24, 0); 891 892 static T7_COMP_SEL(pwm_e, PWM_CLK_EF_CTRL, 9, 0x3, t7_pwm_parents); 893 static T7_COMP_DIV(pwm_e, PWM_CLK_EF_CTRL, 0, 8); 894 static T7_COMP_GATE(pwm_e, PWM_CLK_EF_CTRL, 8, 0); 895 896 static T7_COMP_SEL(pwm_f, PWM_CLK_EF_CTRL, 25, 0x3, t7_pwm_parents); 897 static T7_COMP_DIV(pwm_f, PWM_CLK_EF_CTRL, 16, 8); 898 static T7_COMP_GATE(pwm_f, PWM_CLK_EF_CTRL, 24, 0); 899 900 static T7_COMP_SEL(pwm_ao_a, PWM_CLK_AO_AB_CTRL, 9, 0x3, t7_pwm_parents); 901 static T7_COMP_DIV(pwm_ao_a, PWM_CLK_AO_AB_CTRL, 0, 8); 902 static T7_COMP_GATE(pwm_ao_a, PWM_CLK_AO_AB_CTRL, 8, 0); 903 904 static T7_COMP_SEL(pwm_ao_b, PWM_CLK_AO_AB_CTRL, 25, 0x3, t7_pwm_parents); 905 static T7_COMP_DIV(pwm_ao_b, PWM_CLK_AO_AB_CTRL, 16, 8); 906 static T7_COMP_GATE(pwm_ao_b, PWM_CLK_AO_AB_CTRL, 24, 0); 907 908 static T7_COMP_SEL(pwm_ao_c, PWM_CLK_AO_CD_CTRL, 9, 0x3, t7_pwm_parents); 909 static T7_COMP_DIV(pwm_ao_c, PWM_CLK_AO_CD_CTRL, 0, 8); 910 static T7_COMP_GATE(pwm_ao_c, PWM_CLK_AO_CD_CTRL, 8, 0); 911 912 static T7_COMP_SEL(pwm_ao_d, PWM_CLK_AO_CD_CTRL, 25, 0x3, t7_pwm_parents); 913 static T7_COMP_DIV(pwm_ao_d, PWM_CLK_AO_CD_CTRL, 16, 8); 914 static T7_COMP_GATE(pwm_ao_d, PWM_CLK_AO_CD_CTRL, 24, 0); 915 916 static T7_COMP_SEL(pwm_ao_e, PWM_CLK_AO_EF_CTRL, 9, 0x3, t7_pwm_parents); 917 static T7_COMP_DIV(pwm_ao_e, PWM_CLK_AO_EF_CTRL, 0, 8); 918 static T7_COMP_GATE(pwm_ao_e, PWM_CLK_AO_EF_CTRL, 8, 0); 919 920 static T7_COMP_SEL(pwm_ao_f, PWM_CLK_AO_EF_CTRL, 25, 0x3, t7_pwm_parents); 921 static T7_COMP_DIV(pwm_ao_f, PWM_CLK_AO_EF_CTRL, 16, 8); 922 static T7_COMP_GATE(pwm_ao_f, PWM_CLK_AO_EF_CTRL, 24, 0); 923 924 static T7_COMP_SEL(pwm_ao_g, PWM_CLK_AO_GH_CTRL, 9, 0x3, t7_pwm_parents); 925 static T7_COMP_DIV(pwm_ao_g, PWM_CLK_AO_GH_CTRL, 0, 8); 926 static T7_COMP_GATE(pwm_ao_g, PWM_CLK_AO_GH_CTRL, 8, 0); 927 928 static T7_COMP_SEL(pwm_ao_h, PWM_CLK_AO_GH_CTRL, 25, 0x3, t7_pwm_parents); 929 static T7_COMP_DIV(pwm_ao_h, PWM_CLK_AO_GH_CTRL, 16, 8); 930 static T7_COMP_GATE(pwm_ao_h, PWM_CLK_AO_GH_CTRL, 24, 0); 931 932 static const struct clk_parent_data t7_sys_pclk_parents = { .fw_name = "sys" }; 933 934 #define T7_SYS_PCLK(_name, _reg, _bit, _flags) \ 935 MESON_PCLK(t7_##_name, _reg, _bit, &t7_sys_pclk_parents, _flags) 936 937 static T7_SYS_PCLK(sys_ddr, SYS_CLK_EN0_REG0, 0, 0); 938 static T7_SYS_PCLK(sys_dos, SYS_CLK_EN0_REG0, 1, 0); 939 static T7_SYS_PCLK(sys_mipi_dsi_a, SYS_CLK_EN0_REG0, 2, 0); 940 static T7_SYS_PCLK(sys_mipi_dsi_b, SYS_CLK_EN0_REG0, 3, 0); 941 static T7_SYS_PCLK(sys_ethphy, SYS_CLK_EN0_REG0, 4, 0); 942 static T7_SYS_PCLK(sys_mali, SYS_CLK_EN0_REG0, 6, 0); 943 static T7_SYS_PCLK(sys_aocpu, SYS_CLK_EN0_REG0, 13, 0); 944 static T7_SYS_PCLK(sys_aucpu, SYS_CLK_EN0_REG0, 14, 0); 945 static T7_SYS_PCLK(sys_cec, SYS_CLK_EN0_REG0, 16, 0); 946 static T7_SYS_PCLK(sys_gdc, SYS_CLK_EN0_REG0, 17, 0); 947 static T7_SYS_PCLK(sys_deswarp, SYS_CLK_EN0_REG0, 18, 0); 948 static T7_SYS_PCLK(sys_ampipe_nand, SYS_CLK_EN0_REG0, 19, 0); 949 static T7_SYS_PCLK(sys_ampipe_eth, SYS_CLK_EN0_REG0, 20, 0); 950 static T7_SYS_PCLK(sys_am2axi0, SYS_CLK_EN0_REG0, 21, 0); 951 static T7_SYS_PCLK(sys_am2axi1, SYS_CLK_EN0_REG0, 22, 0); 952 static T7_SYS_PCLK(sys_am2axi2, SYS_CLK_EN0_REG0, 23, 0); 953 static T7_SYS_PCLK(sys_sd_emmc_a, SYS_CLK_EN0_REG0, 24, 0); 954 static T7_SYS_PCLK(sys_sd_emmc_b, SYS_CLK_EN0_REG0, 25, 0); 955 static T7_SYS_PCLK(sys_sd_emmc_c, SYS_CLK_EN0_REG0, 26, 0); 956 static T7_SYS_PCLK(sys_smartcard, SYS_CLK_EN0_REG0, 27, 0); 957 static T7_SYS_PCLK(sys_acodec, SYS_CLK_EN0_REG0, 28, 0); 958 static T7_SYS_PCLK(sys_spifc, SYS_CLK_EN0_REG0, 29, 0); 959 static T7_SYS_PCLK(sys_msr_clk, SYS_CLK_EN0_REG0, 30, 0); 960 static T7_SYS_PCLK(sys_ir_ctrl, SYS_CLK_EN0_REG0, 31, 0); 961 static T7_SYS_PCLK(sys_audio, SYS_CLK_EN0_REG1, 0, 0); 962 static T7_SYS_PCLK(sys_eth, SYS_CLK_EN0_REG1, 3, 0); 963 static T7_SYS_PCLK(sys_uart_a, SYS_CLK_EN0_REG1, 5, 0); 964 static T7_SYS_PCLK(sys_uart_b, SYS_CLK_EN0_REG1, 6, 0); 965 static T7_SYS_PCLK(sys_uart_c, SYS_CLK_EN0_REG1, 7, 0); 966 static T7_SYS_PCLK(sys_uart_d, SYS_CLK_EN0_REG1, 8, 0); 967 static T7_SYS_PCLK(sys_uart_e, SYS_CLK_EN0_REG1, 9, 0); 968 static T7_SYS_PCLK(sys_uart_f, SYS_CLK_EN0_REG1, 10, 0); 969 static T7_SYS_PCLK(sys_aififo, SYS_CLK_EN0_REG1, 11, 0); 970 static T7_SYS_PCLK(sys_spicc2, SYS_CLK_EN0_REG1, 12, 0); 971 static T7_SYS_PCLK(sys_spicc3, SYS_CLK_EN0_REG1, 13, 0); 972 static T7_SYS_PCLK(sys_spicc4, SYS_CLK_EN0_REG1, 14, 0); 973 static T7_SYS_PCLK(sys_ts_a73, SYS_CLK_EN0_REG1, 15, 0); 974 static T7_SYS_PCLK(sys_ts_a53, SYS_CLK_EN0_REG1, 16, 0); 975 static T7_SYS_PCLK(sys_spicc5, SYS_CLK_EN0_REG1, 17, 0); 976 static T7_SYS_PCLK(sys_g2d, SYS_CLK_EN0_REG1, 20, 0); 977 static T7_SYS_PCLK(sys_spicc0, SYS_CLK_EN0_REG1, 21, 0); 978 static T7_SYS_PCLK(sys_spicc1, SYS_CLK_EN0_REG1, 22, 0); 979 static T7_SYS_PCLK(sys_pcie, SYS_CLK_EN0_REG1, 24, 0); 980 static T7_SYS_PCLK(sys_usb, SYS_CLK_EN0_REG1, 26, 0); 981 static T7_SYS_PCLK(sys_pcie_phy, SYS_CLK_EN0_REG1, 27, 0); 982 static T7_SYS_PCLK(sys_i2c_ao_a, SYS_CLK_EN0_REG1, 28, 0); 983 static T7_SYS_PCLK(sys_i2c_ao_b, SYS_CLK_EN0_REG1, 29, 0); 984 static T7_SYS_PCLK(sys_i2c_m_a, SYS_CLK_EN0_REG1, 30, 0); 985 static T7_SYS_PCLK(sys_i2c_m_b, SYS_CLK_EN0_REG1, 31, 0); 986 static T7_SYS_PCLK(sys_i2c_m_c, SYS_CLK_EN0_REG2, 0, 0); 987 static T7_SYS_PCLK(sys_i2c_m_d, SYS_CLK_EN0_REG2, 1, 0); 988 static T7_SYS_PCLK(sys_i2c_m_e, SYS_CLK_EN0_REG2, 2, 0); 989 static T7_SYS_PCLK(sys_i2c_m_f, SYS_CLK_EN0_REG2, 3, 0); 990 static T7_SYS_PCLK(sys_hdmitx_apb, SYS_CLK_EN0_REG2, 4, 0); 991 static T7_SYS_PCLK(sys_i2c_s_a, SYS_CLK_EN0_REG2, 5, 0); 992 static T7_SYS_PCLK(sys_hdmirx_pclk, SYS_CLK_EN0_REG2, 8, 0); 993 static T7_SYS_PCLK(sys_mmc_apb, SYS_CLK_EN0_REG2, 11, 0); 994 static T7_SYS_PCLK(sys_mipi_isp_pclk, SYS_CLK_EN0_REG2, 17, 0); 995 static T7_SYS_PCLK(sys_rsa, SYS_CLK_EN0_REG2, 18, 0); 996 static T7_SYS_PCLK(sys_pclk_sys_apb, SYS_CLK_EN0_REG2, 19, 0); 997 static T7_SYS_PCLK(sys_a73pclk_apb, SYS_CLK_EN0_REG2, 20, 0); 998 static T7_SYS_PCLK(sys_dspa, SYS_CLK_EN0_REG2, 21, 0); 999 static T7_SYS_PCLK(sys_dspb, SYS_CLK_EN0_REG2, 22, 0); 1000 static T7_SYS_PCLK(sys_vpu_intr, SYS_CLK_EN0_REG2, 25, 0); 1001 static T7_SYS_PCLK(sys_sar_adc, SYS_CLK_EN0_REG2, 28, 0); 1002 /* 1003 * sys_gic provides the clock for GIC(Generic Interrupt Controller). 1004 * After clock is disabled, The GIC cannot work properly. At present, the driver 1005 * used by our GIC is the public driver in kernel, and there is no management 1006 * clock in the driver. 1007 */ 1008 static T7_SYS_PCLK(sys_gic, SYS_CLK_EN0_REG2, 30, CLK_IS_CRITICAL); 1009 static T7_SYS_PCLK(sys_ts_gpu, SYS_CLK_EN0_REG2, 31, 0); 1010 static T7_SYS_PCLK(sys_ts_nna, SYS_CLK_EN0_REG3, 0, 0); 1011 static T7_SYS_PCLK(sys_ts_vpu, SYS_CLK_EN0_REG3, 1, 0); 1012 static T7_SYS_PCLK(sys_ts_hevc, SYS_CLK_EN0_REG3, 2, 0); 1013 static T7_SYS_PCLK(sys_pwm_ao_ab, SYS_CLK_EN0_REG3, 3, 0); 1014 static T7_SYS_PCLK(sys_pwm_ao_cd, SYS_CLK_EN0_REG3, 4, 0); 1015 static T7_SYS_PCLK(sys_pwm_ao_ef, SYS_CLK_EN0_REG3, 5, 0); 1016 static T7_SYS_PCLK(sys_pwm_ao_gh, SYS_CLK_EN0_REG3, 6, 0); 1017 static T7_SYS_PCLK(sys_pwm_ab, SYS_CLK_EN0_REG3, 7, 0); 1018 static T7_SYS_PCLK(sys_pwm_cd, SYS_CLK_EN0_REG3, 8, 0); 1019 static T7_SYS_PCLK(sys_pwm_ef, SYS_CLK_EN0_REG3, 9, 0); 1020 1021 /* Array of all clocks registered by this provider */ 1022 static struct clk_hw *t7_peripherals_hw_clks[] = { 1023 [CLKID_RTC_DUALDIV_IN] = &t7_rtc_dualdiv_in.hw, 1024 [CLKID_RTC_DUALDIV_DIV] = &t7_rtc_dualdiv_div.hw, 1025 [CLKID_RTC_DUALDIV_SEL] = &t7_rtc_dualdiv_sel.hw, 1026 [CLKID_RTC_DUALDIV] = &t7_rtc_dualdiv.hw, 1027 [CLKID_RTC] = &t7_rtc.hw, 1028 [CLKID_CECA_DUALDIV_IN] = &t7_ceca_dualdiv_in.hw, 1029 [CLKID_CECA_DUALDIV_DIV] = &t7_ceca_dualdiv_div.hw, 1030 [CLKID_CECA_DUALDIV_SEL] = &t7_ceca_dualdiv_sel.hw, 1031 [CLKID_CECA_DUALDIV] = &t7_ceca_dualdiv.hw, 1032 [CLKID_CECA] = &t7_ceca.hw, 1033 [CLKID_CECB_DUALDIV_IN] = &t7_cecb_dualdiv_in.hw, 1034 [CLKID_CECB_DUALDIV_DIV] = &t7_cecb_dualdiv_div.hw, 1035 [CLKID_CECB_DUALDIV_SEL] = &t7_cecb_dualdiv_sel.hw, 1036 [CLKID_CECB_DUALDIV] = &t7_cecb_dualdiv.hw, 1037 [CLKID_CECB] = &t7_cecb.hw, 1038 [CLKID_SC_SEL] = &t7_sc_sel.hw, 1039 [CLKID_SC_DIV] = &t7_sc_div.hw, 1040 [CLKID_SC] = &t7_sc.hw, 1041 [CLKID_DSPA_0_SEL] = &t7_dspa_0_sel.hw, 1042 [CLKID_DSPA_0_DIV] = &t7_dspa_0_div.hw, 1043 [CLKID_DSPA_0] = &t7_dspa_0.hw, 1044 [CLKID_DSPA_1_SEL] = &t7_dspa_1_sel.hw, 1045 [CLKID_DSPA_1_DIV] = &t7_dspa_1_div.hw, 1046 [CLKID_DSPA_1] = &t7_dspa_1.hw, 1047 [CLKID_DSPA] = &t7_dspa.hw, 1048 [CLKID_DSPB_0_SEL] = &t7_dspb_0_sel.hw, 1049 [CLKID_DSPB_0_DIV] = &t7_dspb_0_div.hw, 1050 [CLKID_DSPB_0] = &t7_dspb_0.hw, 1051 [CLKID_DSPB_1_SEL] = &t7_dspb_1_sel.hw, 1052 [CLKID_DSPB_1_DIV] = &t7_dspb_1_div.hw, 1053 [CLKID_DSPB_1] = &t7_dspb_1.hw, 1054 [CLKID_DSPB] = &t7_dspb.hw, 1055 [CLKID_24M] = &t7_24m.hw, 1056 [CLKID_24M_DIV2] = &t7_24m_div2.hw, 1057 [CLKID_12M] = &t7_12m.hw, 1058 [CLKID_25M_DIV] = &t7_25m_div.hw, 1059 [CLKID_25M] = &t7_25m.hw, 1060 [CLKID_ANAKIN_0_SEL] = &t7_anakin_0_sel.hw, 1061 [CLKID_ANAKIN_0_DIV] = &t7_anakin_0_div.hw, 1062 [CLKID_ANAKIN_0] = &t7_anakin_0.hw, 1063 [CLKID_ANAKIN_1_SEL] = &t7_anakin_1_sel.hw, 1064 [CLKID_ANAKIN_1_DIV] = &t7_anakin_1_div.hw, 1065 [CLKID_ANAKIN_1] = &t7_anakin_1.hw, 1066 [CLKID_ANAKIN_01_SEL] = &t7_anakin_01_sel.hw, 1067 [CLKID_ANAKIN] = &t7_anakin.hw, 1068 [CLKID_MIPI_CSI_PHY_0_SEL] = &t7_mipi_csi_phy_0_sel.hw, 1069 [CLKID_MIPI_CSI_PHY_0_DIV] = &t7_mipi_csi_phy_0_div.hw, 1070 [CLKID_MIPI_CSI_PHY_0] = &t7_mipi_csi_phy_0.hw, 1071 [CLKID_MIPI_CSI_PHY_1_SEL] = &t7_mipi_csi_phy_1_sel.hw, 1072 [CLKID_MIPI_CSI_PHY_1_DIV] = &t7_mipi_csi_phy_1_div.hw, 1073 [CLKID_MIPI_CSI_PHY_1] = &t7_mipi_csi_phy_1.hw, 1074 [CLKID_MIPI_CSI_PHY] = &t7_mipi_csi_phy.hw, 1075 [CLKID_MIPI_ISP_SEL] = &t7_mipi_isp_sel.hw, 1076 [CLKID_MIPI_ISP_DIV] = &t7_mipi_isp_div.hw, 1077 [CLKID_MIPI_ISP] = &t7_mipi_isp.hw, 1078 [CLKID_TS_DIV] = &t7_ts_div.hw, 1079 [CLKID_TS] = &t7_ts.hw, 1080 [CLKID_MALI_0_SEL] = &t7_mali_0_sel.hw, 1081 [CLKID_MALI_0_DIV] = &t7_mali_0_div.hw, 1082 [CLKID_MALI_0] = &t7_mali_0.hw, 1083 [CLKID_MALI_1_SEL] = &t7_mali_1_sel.hw, 1084 [CLKID_MALI_1_DIV] = &t7_mali_1_div.hw, 1085 [CLKID_MALI_1] = &t7_mali_1.hw, 1086 [CLKID_MALI] = &t7_mali.hw, 1087 [CLKID_ETH_RMII_SEL] = &t7_eth_rmii_sel.hw, 1088 [CLKID_ETH_RMII_DIV] = &t7_eth_rmii_div.hw, 1089 [CLKID_ETH_RMII] = &t7_eth_rmii.hw, 1090 [CLKID_FCLK_DIV2_DIV8] = &t7_fdiv2_div8.hw, 1091 [CLKID_ETH_125M] = &t7_eth_125m.hw, 1092 [CLKID_SD_EMMC_A_SEL] = &t7_sd_emmc_a_sel.hw, 1093 [CLKID_SD_EMMC_A_DIV] = &t7_sd_emmc_a_div.hw, 1094 [CLKID_SD_EMMC_A] = &t7_sd_emmc_a.hw, 1095 [CLKID_SD_EMMC_B_SEL] = &t7_sd_emmc_b_sel.hw, 1096 [CLKID_SD_EMMC_B_DIV] = &t7_sd_emmc_b_div.hw, 1097 [CLKID_SD_EMMC_B] = &t7_sd_emmc_b.hw, 1098 [CLKID_SD_EMMC_C_SEL] = &t7_sd_emmc_c_sel.hw, 1099 [CLKID_SD_EMMC_C_DIV] = &t7_sd_emmc_c_div.hw, 1100 [CLKID_SD_EMMC_C] = &t7_sd_emmc_c.hw, 1101 [CLKID_SPICC0_SEL] = &t7_spicc0_sel.hw, 1102 [CLKID_SPICC0_DIV] = &t7_spicc0_div.hw, 1103 [CLKID_SPICC0] = &t7_spicc0.hw, 1104 [CLKID_SPICC1_SEL] = &t7_spicc1_sel.hw, 1105 [CLKID_SPICC1_DIV] = &t7_spicc1_div.hw, 1106 [CLKID_SPICC1] = &t7_spicc1.hw, 1107 [CLKID_SPICC2_SEL] = &t7_spicc2_sel.hw, 1108 [CLKID_SPICC2_DIV] = &t7_spicc2_div.hw, 1109 [CLKID_SPICC2] = &t7_spicc2.hw, 1110 [CLKID_SPICC3_SEL] = &t7_spicc3_sel.hw, 1111 [CLKID_SPICC3_DIV] = &t7_spicc3_div.hw, 1112 [CLKID_SPICC3] = &t7_spicc3.hw, 1113 [CLKID_SPICC4_SEL] = &t7_spicc4_sel.hw, 1114 [CLKID_SPICC4_DIV] = &t7_spicc4_div.hw, 1115 [CLKID_SPICC4] = &t7_spicc4.hw, 1116 [CLKID_SPICC5_SEL] = &t7_spicc5_sel.hw, 1117 [CLKID_SPICC5_DIV] = &t7_spicc5_div.hw, 1118 [CLKID_SPICC5] = &t7_spicc5.hw, 1119 [CLKID_SARADC_SEL] = &t7_saradc_sel.hw, 1120 [CLKID_SARADC_DIV] = &t7_saradc_div.hw, 1121 [CLKID_SARADC] = &t7_saradc.hw, 1122 [CLKID_PWM_A_SEL] = &t7_pwm_a_sel.hw, 1123 [CLKID_PWM_A_DIV] = &t7_pwm_a_div.hw, 1124 [CLKID_PWM_A] = &t7_pwm_a.hw, 1125 [CLKID_PWM_B_SEL] = &t7_pwm_b_sel.hw, 1126 [CLKID_PWM_B_DIV] = &t7_pwm_b_div.hw, 1127 [CLKID_PWM_B] = &t7_pwm_b.hw, 1128 [CLKID_PWM_C_SEL] = &t7_pwm_c_sel.hw, 1129 [CLKID_PWM_C_DIV] = &t7_pwm_c_div.hw, 1130 [CLKID_PWM_C] = &t7_pwm_c.hw, 1131 [CLKID_PWM_D_SEL] = &t7_pwm_d_sel.hw, 1132 [CLKID_PWM_D_DIV] = &t7_pwm_d_div.hw, 1133 [CLKID_PWM_D] = &t7_pwm_d.hw, 1134 [CLKID_PWM_E_SEL] = &t7_pwm_e_sel.hw, 1135 [CLKID_PWM_E_DIV] = &t7_pwm_e_div.hw, 1136 [CLKID_PWM_E] = &t7_pwm_e.hw, 1137 [CLKID_PWM_F_SEL] = &t7_pwm_f_sel.hw, 1138 [CLKID_PWM_F_DIV] = &t7_pwm_f_div.hw, 1139 [CLKID_PWM_F] = &t7_pwm_f.hw, 1140 [CLKID_PWM_AO_A_SEL] = &t7_pwm_ao_a_sel.hw, 1141 [CLKID_PWM_AO_A_DIV] = &t7_pwm_ao_a_div.hw, 1142 [CLKID_PWM_AO_A] = &t7_pwm_ao_a.hw, 1143 [CLKID_PWM_AO_B_SEL] = &t7_pwm_ao_b_sel.hw, 1144 [CLKID_PWM_AO_B_DIV] = &t7_pwm_ao_b_div.hw, 1145 [CLKID_PWM_AO_B] = &t7_pwm_ao_b.hw, 1146 [CLKID_PWM_AO_C_SEL] = &t7_pwm_ao_c_sel.hw, 1147 [CLKID_PWM_AO_C_DIV] = &t7_pwm_ao_c_div.hw, 1148 [CLKID_PWM_AO_C] = &t7_pwm_ao_c.hw, 1149 [CLKID_PWM_AO_D_SEL] = &t7_pwm_ao_d_sel.hw, 1150 [CLKID_PWM_AO_D_DIV] = &t7_pwm_ao_d_div.hw, 1151 [CLKID_PWM_AO_D] = &t7_pwm_ao_d.hw, 1152 [CLKID_PWM_AO_E_SEL] = &t7_pwm_ao_e_sel.hw, 1153 [CLKID_PWM_AO_E_DIV] = &t7_pwm_ao_e_div.hw, 1154 [CLKID_PWM_AO_E] = &t7_pwm_ao_e.hw, 1155 [CLKID_PWM_AO_F_SEL] = &t7_pwm_ao_f_sel.hw, 1156 [CLKID_PWM_AO_F_DIV] = &t7_pwm_ao_f_div.hw, 1157 [CLKID_PWM_AO_F] = &t7_pwm_ao_f.hw, 1158 [CLKID_PWM_AO_G_SEL] = &t7_pwm_ao_g_sel.hw, 1159 [CLKID_PWM_AO_G_DIV] = &t7_pwm_ao_g_div.hw, 1160 [CLKID_PWM_AO_G] = &t7_pwm_ao_g.hw, 1161 [CLKID_PWM_AO_H_SEL] = &t7_pwm_ao_h_sel.hw, 1162 [CLKID_PWM_AO_H_DIV] = &t7_pwm_ao_h_div.hw, 1163 [CLKID_PWM_AO_H] = &t7_pwm_ao_h.hw, 1164 [CLKID_SYS_DDR] = &t7_sys_ddr.hw, 1165 [CLKID_SYS_DOS] = &t7_sys_dos.hw, 1166 [CLKID_SYS_MIPI_DSI_A] = &t7_sys_mipi_dsi_a.hw, 1167 [CLKID_SYS_MIPI_DSI_B] = &t7_sys_mipi_dsi_b.hw, 1168 [CLKID_SYS_ETHPHY] = &t7_sys_ethphy.hw, 1169 [CLKID_SYS_MALI] = &t7_sys_mali.hw, 1170 [CLKID_SYS_AOCPU] = &t7_sys_aocpu.hw, 1171 [CLKID_SYS_AUCPU] = &t7_sys_aucpu.hw, 1172 [CLKID_SYS_CEC] = &t7_sys_cec.hw, 1173 [CLKID_SYS_GDC] = &t7_sys_gdc.hw, 1174 [CLKID_SYS_DESWARP] = &t7_sys_deswarp.hw, 1175 [CLKID_SYS_AMPIPE_NAND] = &t7_sys_ampipe_nand.hw, 1176 [CLKID_SYS_AMPIPE_ETH] = &t7_sys_ampipe_eth.hw, 1177 [CLKID_SYS_AM2AXI0] = &t7_sys_am2axi0.hw, 1178 [CLKID_SYS_AM2AXI1] = &t7_sys_am2axi1.hw, 1179 [CLKID_SYS_AM2AXI2] = &t7_sys_am2axi2.hw, 1180 [CLKID_SYS_SD_EMMC_A] = &t7_sys_sd_emmc_a.hw, 1181 [CLKID_SYS_SD_EMMC_B] = &t7_sys_sd_emmc_b.hw, 1182 [CLKID_SYS_SD_EMMC_C] = &t7_sys_sd_emmc_c.hw, 1183 [CLKID_SYS_SMARTCARD] = &t7_sys_smartcard.hw, 1184 [CLKID_SYS_ACODEC] = &t7_sys_acodec.hw, 1185 [CLKID_SYS_SPIFC] = &t7_sys_spifc.hw, 1186 [CLKID_SYS_MSR_CLK] = &t7_sys_msr_clk.hw, 1187 [CLKID_SYS_IR_CTRL] = &t7_sys_ir_ctrl.hw, 1188 [CLKID_SYS_AUDIO] = &t7_sys_audio.hw, 1189 [CLKID_SYS_ETH] = &t7_sys_eth.hw, 1190 [CLKID_SYS_UART_A] = &t7_sys_uart_a.hw, 1191 [CLKID_SYS_UART_B] = &t7_sys_uart_b.hw, 1192 [CLKID_SYS_UART_C] = &t7_sys_uart_c.hw, 1193 [CLKID_SYS_UART_D] = &t7_sys_uart_d.hw, 1194 [CLKID_SYS_UART_E] = &t7_sys_uart_e.hw, 1195 [CLKID_SYS_UART_F] = &t7_sys_uart_f.hw, 1196 [CLKID_SYS_AIFIFO] = &t7_sys_aififo.hw, 1197 [CLKID_SYS_SPICC2] = &t7_sys_spicc2.hw, 1198 [CLKID_SYS_SPICC3] = &t7_sys_spicc3.hw, 1199 [CLKID_SYS_SPICC4] = &t7_sys_spicc4.hw, 1200 [CLKID_SYS_TS_A73] = &t7_sys_ts_a73.hw, 1201 [CLKID_SYS_TS_A53] = &t7_sys_ts_a53.hw, 1202 [CLKID_SYS_SPICC5] = &t7_sys_spicc5.hw, 1203 [CLKID_SYS_G2D] = &t7_sys_g2d.hw, 1204 [CLKID_SYS_SPICC0] = &t7_sys_spicc0.hw, 1205 [CLKID_SYS_SPICC1] = &t7_sys_spicc1.hw, 1206 [CLKID_SYS_PCIE] = &t7_sys_pcie.hw, 1207 [CLKID_SYS_USB] = &t7_sys_usb.hw, 1208 [CLKID_SYS_PCIE_PHY] = &t7_sys_pcie_phy.hw, 1209 [CLKID_SYS_I2C_AO_A] = &t7_sys_i2c_ao_a.hw, 1210 [CLKID_SYS_I2C_AO_B] = &t7_sys_i2c_ao_b.hw, 1211 [CLKID_SYS_I2C_M_A] = &t7_sys_i2c_m_a.hw, 1212 [CLKID_SYS_I2C_M_B] = &t7_sys_i2c_m_b.hw, 1213 [CLKID_SYS_I2C_M_C] = &t7_sys_i2c_m_c.hw, 1214 [CLKID_SYS_I2C_M_D] = &t7_sys_i2c_m_d.hw, 1215 [CLKID_SYS_I2C_M_E] = &t7_sys_i2c_m_e.hw, 1216 [CLKID_SYS_I2C_M_F] = &t7_sys_i2c_m_f.hw, 1217 [CLKID_SYS_HDMITX_APB] = &t7_sys_hdmitx_apb.hw, 1218 [CLKID_SYS_I2C_S_A] = &t7_sys_i2c_s_a.hw, 1219 [CLKID_SYS_HDMIRX_PCLK] = &t7_sys_hdmirx_pclk.hw, 1220 [CLKID_SYS_MMC_APB] = &t7_sys_mmc_apb.hw, 1221 [CLKID_SYS_MIPI_ISP_PCLK] = &t7_sys_mipi_isp_pclk.hw, 1222 [CLKID_SYS_RSA] = &t7_sys_rsa.hw, 1223 [CLKID_SYS_PCLK_SYS_APB] = &t7_sys_pclk_sys_apb.hw, 1224 [CLKID_SYS_A73PCLK_APB] = &t7_sys_a73pclk_apb.hw, 1225 [CLKID_SYS_DSPA] = &t7_sys_dspa.hw, 1226 [CLKID_SYS_DSPB] = &t7_sys_dspb.hw, 1227 [CLKID_SYS_VPU_INTR] = &t7_sys_vpu_intr.hw, 1228 [CLKID_SYS_SAR_ADC] = &t7_sys_sar_adc.hw, 1229 [CLKID_SYS_GIC] = &t7_sys_gic.hw, 1230 [CLKID_SYS_TS_GPU] = &t7_sys_ts_gpu.hw, 1231 [CLKID_SYS_TS_NNA] = &t7_sys_ts_nna.hw, 1232 [CLKID_SYS_TS_VPU] = &t7_sys_ts_vpu.hw, 1233 [CLKID_SYS_TS_HEVC] = &t7_sys_ts_hevc.hw, 1234 [CLKID_SYS_PWM_AO_AB] = &t7_sys_pwm_ao_ab.hw, 1235 [CLKID_SYS_PWM_AO_CD] = &t7_sys_pwm_ao_cd.hw, 1236 [CLKID_SYS_PWM_AO_EF] = &t7_sys_pwm_ao_ef.hw, 1237 [CLKID_SYS_PWM_AO_GH] = &t7_sys_pwm_ao_gh.hw, 1238 [CLKID_SYS_PWM_AB] = &t7_sys_pwm_ab.hw, 1239 [CLKID_SYS_PWM_CD] = &t7_sys_pwm_cd.hw, 1240 [CLKID_SYS_PWM_EF] = &t7_sys_pwm_ef.hw, 1241 }; 1242 1243 static const struct meson_clkc_data t7_peripherals_data = { 1244 .hw_clks = { 1245 .hws = t7_peripherals_hw_clks, 1246 .num = ARRAY_SIZE(t7_peripherals_hw_clks), 1247 }, 1248 }; 1249 1250 static const struct of_device_id t7_peripherals_clkc_match_table[] = { 1251 { 1252 .compatible = "amlogic,t7-peripherals-clkc", 1253 .data = &t7_peripherals_data 1254 }, 1255 {} 1256 }; 1257 MODULE_DEVICE_TABLE(of, t7_peripherals_clkc_match_table); 1258 1259 static struct platform_driver t7_peripherals_clkc_driver = { 1260 .probe = meson_clkc_mmio_probe, 1261 .driver = { 1262 .name = "t7-peripherals-clkc", 1263 .of_match_table = t7_peripherals_clkc_match_table, 1264 }, 1265 }; 1266 module_platform_driver(t7_peripherals_clkc_driver); 1267 1268 MODULE_DESCRIPTION("Amlogic T7 Peripherals Clock Controller driver"); 1269 MODULE_AUTHOR("Jian Hu <jian.hu@amlogic.com>"); 1270 MODULE_LICENSE("GPL"); 1271 MODULE_IMPORT_NS("CLK_MESON"); 1272