Merge drm/drm-fixes into drm-misc-fixes

7.0-rc1 was just released, let's merge it to kick the new release cycle.

Signed-off-by: Maxime Ripard <mripard@kernel.org>

Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk updates from Stephen Boyd:
"Not much changed in the clk framework this time except the clk.h
consumer

Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk updates from Stephen Boyd:
"Not much changed in the clk framework this time except the clk.h
consumer API moved the context saving APIs around to fix a build error
in certain configurations.

There was a change to the core framework for CLK_OPS_PARENT_ENABLE
behavior during registration, but it wrecked existing drivers that
didn't expect things to be turned off during clk registration so it
got reverted.

This cycle is really a large collection of new clk drivers, primarily
for Qualcomm SoCs but also for Amlogic, SpacemiT, Google, and Aspeed.
Another big change in here is support for automatic hardware clock
gating on Samsung SoCs where the clks turn on and off when needed.
Ideally more vendors move to this method for better power savings. The
highlights are in the updates section below.

Beyond all the new drivers we have a bunch of cleanups like converting
drivers from divider_round_rate() to divider_determine_rate() and
using scoped for each OF child loops. Otherwise it's the usual data
fixes and plugging reference leaks, etc. that's all pretty ordinary
but not critical enough to fix until the next release.

New Drivers:
- Qualcomm Kaanapali global, tcsr, rpmh, display, gpu, camera, and
video clk controllers
- Qualcomm SM8750 camera clk controllers
- Qualcomm MSM8940 and SDM439 global clk controllers
- Google GS101 Display Process Unit (DPU) clk controllers
- SpacemiT K3 clk controllers
- Amlogic t7 clk controllers
- Aspeed AST2700 clk controllers

Updates:
- Convert clock dividers from round_rate() to determine_rate()
- Fix sparse warnings, kernel-doc warnings, and plug leaked OF refs
- Automatic hardware clk gating on Google GS101 SoCs
- Amlogic s4 video clks
- CAN-FD clks and resets on Renesas RZ/T2H, RZ/N2H, RZ/V2H, and
RZ/V2N
- Expanded Serial Peripheral Interface (xSPI) clocks and resets on
Renesas RZ/T21H and RZ/N2H
- DMAC, interrupt controller (ICU), SPI, and thermal (TSU) clocks and
resets on Renesas RZ/V2N
- More serial (RSCI) clocks and resets on Renesas RZ/V2H and RZ/V2N
- CPU frequency scaling on T-HEAD TH1520"

* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (165 commits)
clk: aspeed: Add reset for HACE/VIDEO
dt-bindings: clock: aspeed: Add VIDEO reset definition
clk: aspeed: add AST2700 clock driver
MAINTAINERS: Add entry for ASPEED clock drivers.
clk: aspeed: Move the existing ASPEED clk drivers into aspeed subdirectory.
Revert "clk: Respect CLK_OPS_PARENT_ENABLE during recalc"
clk: Disable KUNIT_UML_PCI
dt-bindings: clk: rs9: Fix DIF pattern match
clk: rs9: Convert to DEFINE_SIMPLE_DEV_PM_OPS()
clk: rs9: Reserve 8 struct clk_hw slots for for 9FGV0841
clk: qcom: sm8750: Constify 'qcom_cc_desc' in SM8750 camcc
clk: zynqmp: pll: Fix zynqmp_clk_divider_determine_rate kerneldoc
clk: zynqmp: divider: Fix zynqmp_clk_divider_determine_rate kerneldoc
clk: mediatek: Fix error handling in runtime PM setup
clk: mediatek: don't select clk-mt8192 for all ARM64 builds
clk: mediatek: Add mfg_eb as parent to mt8196 mfgpll clocks
clk: mediatek: Refactor pllfh registration to pass device
clk: mediatek: Pass device to clk_hw_register for PLLs
clk: mediatek: Refactor pll registration to pass device
clk: Respect CLK_OPS_PARENT_ENABLE during recalc
...

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Merge branches 'clk-amlogic', 'clk-thead', 'clk-mediatek' and 'clk-samsung' into clk-next

* clk-amlogic:
clk: meson: gxbb: use the existing HHI_HDMI_PLL_CNTL3 macro
clk: meson: g12a: Limit the H

Merge branches 'clk-amlogic', 'clk-thead', 'clk-mediatek' and 'clk-samsung' into clk-next

* clk-amlogic:
clk: meson: gxbb: use the existing HHI_HDMI_PLL_CNTL3 macro
clk: meson: g12a: Limit the HDMI PLL OD to /4
clk: meson: gxbb: Limit the HDMI PLL OD to /4 on GXL/GXM SoCs
clk: amlogic: remove potentially unsafe flags from S4 video clocks
clk: amlogic: add video-related clocks for S4 SoC
dt-bindings: clock: add video clock indices for Amlogic S4 SoC
clk: meson: t7: add t7 clock peripherals controller driver
clk: meson: t7: add support for the T7 SoC PLL clock
dt-bindings: clock: add Amlogic T7 peripherals clock controller
dt-bindings: clock: add Amlogic T7 SCMI clock controller
dt-bindings: clock: add Amlogic T7 PLL clock controller

* clk-thead:
clk: thead: th1520-ap: Support CPU frequency scaling
clk: thead: th1520-ap: Add macro to define multiplexers with flags
clk: thead: th1520-ap: Support setting PLL rates
clk: thead: th1520-ap: Add C910 bus clock
clk: thead: th1520-ap: Poll for PLL lock and wait for stability
dt-bindings: clock: thead,th1520-clk-ap: Add ID for C910 bus clock

* clk-mediatek:
Revert "clk: Respect CLK_OPS_PARENT_ENABLE during recalc"
clk: mediatek: Fix error handling in runtime PM setup
clk: mediatek: don't select clk-mt8192 for all ARM64 builds
clk: mediatek: Add mfg_eb as parent to mt8196 mfgpll clocks
clk: mediatek: Refactor pllfh registration to pass device
clk: mediatek: Pass device to clk_hw_register for PLLs
clk: mediatek: Refactor pll registration to pass device
clk: Respect CLK_OPS_PARENT_ENABLE during recalc
dt-bindings: clock: mediatek,mt7622-pciesys: Remove syscon compatible
clk: mediatek: Drop __initconst from gates

* clk-samsung:
clk: samsung: gs101: add support for Display Process Unit (DPU) clocks
dt-bindings: samsung: exynos-sysreg: add gs101 dpu compatible
dt-bindings: clock: google,gs101-clock: Add DPU clock management unit
dt-bindings: clock: google,gs101-clock: fix alphanumeric ordering
clk: samsung: fix sysreg save/restore when PM is enabled for CMU
clk: samsung: avoid warning message on legacy Exynos (auto clock gating)
clk: samsung: gs101: Enable auto_clock_gate mode for each gs101 CMU
clk: samsung: Implement automatic clock gating mode for CMUs
dt-bindings: clock: google,gs101-clock: add samsung,sysreg property as required
clk: samsung: exynosautov920: add clock support
dt-bindings: clock: exynosautov920: add MFD clock definitions

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Merge tag 'clk-meson-v6.20-1' of https://github.com/BayLibre/clk-meson into clk-amlogic

Pull Amlogic clk driver updates from Jerome Brunet:

- Add support for Amlogic t7 clock controllers
- Add vi

Merge tag 'clk-meson-v6.20-1' of https://github.com/BayLibre/clk-meson into clk-amlogic

Pull Amlogic clk driver updates from Jerome Brunet:

- Add support for Amlogic t7 clock controllers
- Add video clocks on Amlogic s4
- HDMI PLL post divider fixes on Amlogic gx/g12 SoCs

* tag 'clk-meson-v6.20-1' of https://github.com/BayLibre/clk-meson:
clk: meson: gxbb: use the existing HHI_HDMI_PLL_CNTL3 macro
clk: meson: g12a: Limit the HDMI PLL OD to /4
clk: meson: gxbb: Limit the HDMI PLL OD to /4 on GXL/GXM SoCs
clk: amlogic: remove potentially unsafe flags from S4 video clocks
clk: amlogic: add video-related clocks for S4 SoC
dt-bindings: clock: add video clock indices for Amlogic S4 SoC
clk: meson: t7: add t7 clock peripherals controller driver
clk: meson: t7: add support for the T7 SoC PLL clock
dt-bindings: clock: add Amlogic T7 peripherals clock controller
dt-bindings: clock: add Amlogic T7 SCMI clock controller
dt-bindings: clock: add Amlogic T7 PLL clock controller

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clk: meson: t7: add t7 clock peripherals controller driver

Add Peripheral clock controller driver for the Amlogic T7 SoC family.

Signed-off-by: Jian Hu <jian.hu@amlogic.com>
Link: https://lore.kern

clk: meson: t7: add t7 clock peripherals controller driver

Add Peripheral clock controller driver for the Amlogic T7 SoC family.

Signed-off-by: Jian Hu <jian.hu@amlogic.com>
Link: https://lore.kernel.org/r/20251212022619.3072132-6-jian.hu@amlogic.com
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>

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