1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2024 Google LLC
4 * Author: Chen-Yu Tsai <wenst@chromium.org>
5 *
6 * Based on driver in downstream ChromeOS v5.15 kernel.
7 *
8 * Copyright (c) 2014 MediaTek Inc.
9 * Author: Chiawen Lee <chiawen.lee@mediatek.com>
10 */
11
12 #include <dt-bindings/clock/mt8173-clk.h>
13
14 #include <linux/bitfield.h>
15 #include <linux/clk.h>
16 #include <linux/mfd/syscon.h>
17 #include <linux/module.h>
18 #include <linux/of.h>
19 #include <linux/platform_device.h>
20 #include <linux/pm_domain.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/regmap.h>
23
24 #include "clk-gate.h"
25 #include "clk-mtk.h"
26
27 static const struct mtk_gate_regs mfg_cg_regs = {
28 .sta_ofs = 0x0000,
29 .clr_ofs = 0x0008,
30 .set_ofs = 0x0004,
31 };
32
33 #define GATE_MFG(_id, _name, _parent, _shift, _flags) \
34 GATE_MTK_FLAGS(_id, _name, _parent, &mfg_cg_regs, _shift, &mtk_clk_gate_ops_setclr, _flags)
35
36 /* TODO: The block actually has dividers for the core and mem clocks. */
37 static const struct mtk_gate mfg_clks[] = {
38 GATE_MFG(CLK_MFG_AXI, "mfg_axi", "axi_mfg_in_sel", 0, CLK_SET_RATE_PARENT),
39 GATE_MFG(CLK_MFG_MEM, "mfg_mem", "mem_mfg_in_sel", 1, CLK_SET_RATE_PARENT),
40 GATE_MFG(CLK_MFG_G3D, "mfg_g3d", "mfg_sel", 2, CLK_SET_RATE_PARENT),
41 GATE_MFG(CLK_MFG_26M, "mfg_26m", "clk26m", 3, 0),
42 };
43
44 struct mt8173_mfgtop_data {
45 struct clk_hw_onecell_data *clk_data;
46 struct regmap *regmap;
47 struct generic_pm_domain genpd;
48 struct of_phandle_args parent_pd, child_pd;
49 struct clk *clk_26m;
50 };
51
52 /* Delay count in clock cycles */
53 #define MFG_ACTIVE_POWER_CON0 0x24
54 #define RST_B_DELAY_CNT GENMASK(7, 0) /* pwr_rst_b de-assert delay during power-up */
55 #define CLK_EN_DELAY_CNT GENMASK(15, 8) /* CLK_DIS deassert delay during power-up */
56 #define CLK_DIS_DELAY_CNT GENMASK(23, 16) /* CLK_DIS assert delay during power-down */
57 #define FORCE_ABORT BIT(30) /* write 1 to force abort a power event */
58 #define ACTIVE_PWRCTL_EN BIT(31) /* enable ACTIVE_POWER */
59
60 #define MFG_ACTIVE_POWER_CON1 0x28
61 #define PWR_ON_S_DELAY_CNT GENMASK(7, 0) /* pwr_on_s assert delay during power-up */
62 #define ISO_DELAY_CNT GENMASK(15, 8) /* ISO assert delay during power-down */
63 #define ISOOFF_DELAY_CNT GENMASK(23, 16) /* ISO de-assert delay during power-up */
64 #define RST_DELAY_CNT GENMASK(31, 24) /* pwr_rsb_b assert delay during power-down */
65
clk_mt8173_mfgtop_power_on(struct generic_pm_domain * domain)66 static int clk_mt8173_mfgtop_power_on(struct generic_pm_domain *domain)
67 {
68 struct mt8173_mfgtop_data *data = container_of(domain, struct mt8173_mfgtop_data, genpd);
69 int ret;
70
71 /* drives internal power management */
72 ret = clk_prepare_enable(data->clk_26m);
73 if (ret)
74 return ret;
75
76 /* Power on/off delays for various signals */
77 regmap_write(data->regmap, MFG_ACTIVE_POWER_CON0,
78 FIELD_PREP(RST_B_DELAY_CNT, 77) |
79 FIELD_PREP(CLK_EN_DELAY_CNT, 61) |
80 FIELD_PREP(CLK_DIS_DELAY_CNT, 60) |
81 FIELD_PREP(ACTIVE_PWRCTL_EN, 0));
82 regmap_write(data->regmap, MFG_ACTIVE_POWER_CON1,
83 FIELD_PREP(PWR_ON_S_DELAY_CNT, 11) |
84 FIELD_PREP(ISO_DELAY_CNT, 68) |
85 FIELD_PREP(ISOOFF_DELAY_CNT, 69) |
86 FIELD_PREP(RST_DELAY_CNT, 77));
87
88 /* Magic numbers related to core switch sequence and delays */
89 regmap_write(data->regmap, 0xe0, 0x7a710184);
90 regmap_write(data->regmap, 0xe4, 0x835f6856);
91 regmap_write(data->regmap, 0xe8, 0x002b0234);
92 regmap_write(data->regmap, 0xec, 0x80000000);
93 regmap_write(data->regmap, 0xa0, 0x08000000);
94
95 return 0;
96 }
97
clk_mt8173_mfgtop_power_off(struct generic_pm_domain * domain)98 static int clk_mt8173_mfgtop_power_off(struct generic_pm_domain *domain)
99 {
100 struct mt8173_mfgtop_data *data = container_of(domain, struct mt8173_mfgtop_data, genpd);
101
102 /* Magic numbers related to core switch sequence and delays */
103 regmap_write(data->regmap, 0xec, 0);
104
105 /* drives internal power management */
106 clk_disable_unprepare(data->clk_26m);
107
108 return 0;
109 }
110
clk_mt8173_mfgtop_probe(struct platform_device * pdev)111 static int clk_mt8173_mfgtop_probe(struct platform_device *pdev)
112 {
113 struct device *dev = &pdev->dev;
114 struct device_node *node = dev->of_node;
115 struct mt8173_mfgtop_data *data;
116 int ret;
117
118 data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
119 if (!data)
120 return -ENOMEM;
121
122 platform_set_drvdata(pdev, data);
123
124 data->clk_data = mtk_devm_alloc_clk_data(dev, ARRAY_SIZE(mfg_clks));
125 if (!data->clk_data)
126 return -ENOMEM;
127
128 /* MTK clock gates also uses regmap */
129 data->regmap = device_node_to_regmap(node);
130 if (IS_ERR(data->regmap))
131 return dev_err_probe(dev, PTR_ERR(data->regmap), "Failed to get regmap\n");
132
133 data->child_pd.np = node;
134 data->child_pd.args_count = 0;
135 ret = of_parse_phandle_with_args(node, "power-domains", "#power-domain-cells", 0,
136 &data->parent_pd);
137 if (ret)
138 return dev_err_probe(dev, ret, "Failed to parse power domain\n");
139
140 devm_pm_runtime_enable(dev);
141 /*
142 * Do a pm_runtime_resume_and_get() to workaround a possible
143 * deadlock between clk_register() and the genpd framework.
144 */
145 ret = pm_runtime_resume_and_get(dev);
146 if (ret) {
147 dev_err_probe(dev, ret, "Failed to runtime resume device\n");
148 goto put_of_node;
149 }
150
151 ret = mtk_clk_register_gates(dev, node, mfg_clks, ARRAY_SIZE(mfg_clks),
152 data->clk_data);
153 if (ret) {
154 dev_err_probe(dev, ret, "Failed to register clock gates\n");
155 goto put_pm_runtime;
156 }
157
158 data->clk_26m = clk_hw_get_clk(data->clk_data->hws[CLK_MFG_26M], "26m");
159 if (IS_ERR(data->clk_26m)) {
160 ret = dev_err_probe(dev, PTR_ERR(data->clk_26m), "Failed to get 26 MHz clock\n");
161 goto unregister_clks;
162 }
163
164 ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, data->clk_data);
165 if (ret) {
166 dev_err_probe(dev, ret, "Failed to add clk OF provider\n");
167 goto put_26m_clk;
168 }
169
170 data->genpd.name = "mfg-top";
171 data->genpd.power_on = clk_mt8173_mfgtop_power_on;
172 data->genpd.power_off = clk_mt8173_mfgtop_power_off;
173 ret = pm_genpd_init(&data->genpd, NULL, true);
174 if (ret) {
175 dev_err_probe(dev, ret, "Failed to add power domain\n");
176 goto del_clk_provider;
177 }
178
179 ret = of_genpd_add_provider_simple(node, &data->genpd);
180 if (ret) {
181 dev_err_probe(dev, ret, "Failed to add power domain OF provider\n");
182 goto remove_pd;
183 }
184
185 ret = of_genpd_add_subdomain(&data->parent_pd, &data->child_pd);
186 if (ret) {
187 dev_err_probe(dev, ret, "Failed to link PM domains\n");
188 goto del_pd_provider;
189 }
190
191 pm_runtime_put(dev);
192 return 0;
193
194 del_pd_provider:
195 of_genpd_del_provider(node);
196 remove_pd:
197 pm_genpd_remove(&data->genpd);
198 del_clk_provider:
199 of_clk_del_provider(node);
200 put_26m_clk:
201 clk_put(data->clk_26m);
202 unregister_clks:
203 mtk_clk_unregister_gates(mfg_clks, ARRAY_SIZE(mfg_clks), data->clk_data);
204 put_pm_runtime:
205 pm_runtime_put_sync(dev);
206 put_of_node:
207 of_node_put(data->parent_pd.np);
208 return ret;
209 }
210
clk_mt8173_mfgtop_remove(struct platform_device * pdev)211 static void clk_mt8173_mfgtop_remove(struct platform_device *pdev)
212 {
213 struct mt8173_mfgtop_data *data = platform_get_drvdata(pdev);
214 struct device_node *node = pdev->dev.of_node;
215
216 of_genpd_remove_subdomain(&data->parent_pd, &data->child_pd);
217 of_genpd_del_provider(node);
218 pm_genpd_remove(&data->genpd);
219 of_clk_del_provider(node);
220 clk_put(data->clk_26m);
221 mtk_clk_unregister_gates(mfg_clks, ARRAY_SIZE(mfg_clks), data->clk_data);
222 of_node_put(data->parent_pd.np);
223 }
224
225 static const struct of_device_id of_match_clk_mt8173_mfgtop[] = {
226 { .compatible = "mediatek,mt8173-mfgtop" },
227 { /* sentinel */ }
228 };
229 MODULE_DEVICE_TABLE(of, of_match_clk_mt8173_mfgtop);
230
231 static struct platform_driver clk_mt8173_mfgtop_drv = {
232 .probe = clk_mt8173_mfgtop_probe,
233 .remove = clk_mt8173_mfgtop_remove,
234 .driver = {
235 .name = "clk-mt8173-mfgtop",
236 .of_match_table = of_match_clk_mt8173_mfgtop,
237 },
238 };
239 module_platform_driver(clk_mt8173_mfgtop_drv);
240
241 MODULE_DESCRIPTION("MediaTek MT8173 mfgtop clock driver");
242 MODULE_LICENSE("GPL");
243