1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * PLL clock driver for the Mobileye EyeQ5, EyeQ6L and EyeQ6H platforms. 4 * 5 * This controller handles: 6 * - Read-only PLLs, all derived from the same main crystal clock. 7 * - It also exposes divider clocks, those are children to PLLs. 8 * - Fixed factor clocks, children to PLLs. 9 * 10 * Parent clock is expected to be constant. This driver's registers live in a 11 * shared region called OLB. Some PLLs and fixed-factors are initialised early 12 * by of_clk_init(); if so, two clk providers are registered. 13 * 14 * We use eqc_ as prefix, as-in "EyeQ Clock", but way shorter. 15 * 16 * Copyright (C) 2024 Mobileye Vision Technologies Ltd. 17 */ 18 19 /* 20 * Set pr_fmt() for printing from eqc_early_init(). 21 * It is called at of_clk_init() stage (read: really early). 22 */ 23 #define pr_fmt(fmt) "clk-eyeq: " fmt 24 25 #include <linux/array_size.h> 26 #include <linux/auxiliary_bus.h> 27 #include <linux/bitfield.h> 28 #include <linux/bits.h> 29 #include <linux/clk-provider.h> 30 #include <linux/device.h> 31 #include <linux/err.h> 32 #include <linux/errno.h> 33 #include <linux/init.h> 34 #include <linux/io-64-nonatomic-hi-lo.h> 35 #include <linux/io.h> 36 #include <linux/module.h> 37 #include <linux/of.h> 38 #include <linux/of_address.h> 39 #include <linux/overflow.h> 40 #include <linux/platform_device.h> 41 #include <linux/printk.h> 42 #include <linux/slab.h> 43 #include <linux/spinlock.h> 44 #include <linux/types.h> 45 46 #include <dt-bindings/clock/mobileye,eyeq5-clk.h> 47 #include <dt-bindings/clock/mobileye,eyeq6lplus-clk.h> 48 49 /* In frac mode, it enables fractional noise canceling DAC. Else, no function. */ 50 #define PCSR0_DAC_EN BIT(0) 51 /* Fractional or integer mode */ 52 #define PCSR0_DSM_EN BIT(1) 53 #define PCSR0_PLL_EN BIT(2) 54 /* All clocks output held at 0 */ 55 #define PCSR0_FOUTPOSTDIV_EN BIT(3) 56 #define PCSR0_POST_DIV1 GENMASK(6, 4) 57 #define PCSR0_POST_DIV2 GENMASK(9, 7) 58 #define PCSR0_REF_DIV GENMASK(15, 10) 59 #define PCSR0_INTIN GENMASK(27, 16) 60 #define PCSR0_BYPASS BIT(28) 61 /* Bits 30..29 are reserved */ 62 #define PCSR0_PLL_LOCKED BIT(31) 63 64 #define PCSR1_RESET BIT(0) 65 #define PCSR1_SSGC_DIV GENMASK(4, 1) 66 /* Spread amplitude (% = 0.1 * SPREAD[4:0]) */ 67 #define PCSR1_SPREAD GENMASK(9, 5) 68 #define PCSR1_DIS_SSCG BIT(10) 69 /* Down-spread or center-spread */ 70 #define PCSR1_DOWN_SPREAD BIT(11) 71 #define PCSR1_FRAC_IN GENMASK(31, 12) 72 73 struct eqc_pll { 74 unsigned int index; 75 const char *name; 76 unsigned int reg64; 77 }; 78 79 /* 80 * Divider clock. Divider is 2*(v+1), with v the register value. 81 * Min divider is 2, max is 2*(2^width). 82 */ 83 struct eqc_div { 84 unsigned int index; 85 const char *name; 86 unsigned int parent; 87 unsigned int reg; 88 u8 shift; 89 u8 width; 90 }; 91 92 struct eqc_fixed_factor { 93 unsigned int index; 94 const char *name; 95 unsigned int mult; 96 unsigned int div; 97 unsigned int parent; 98 }; 99 100 struct eqc_match_data { 101 unsigned int pll_count; 102 const struct eqc_pll *plls; 103 104 unsigned int div_count; 105 const struct eqc_div *divs; 106 107 unsigned int fixed_factor_count; 108 const struct eqc_fixed_factor *fixed_factors; 109 110 const char *reset_auxdev_name; 111 const char *pinctrl_auxdev_name; 112 const char *eth_phy_auxdev_name; 113 114 unsigned int early_clk_count; 115 }; 116 117 struct eqc_early_match_data { 118 unsigned int early_pll_count; 119 const struct eqc_pll *early_plls; 120 121 unsigned int early_fixed_factor_count; 122 const struct eqc_fixed_factor *early_fixed_factors; 123 124 /* 125 * We want our of_xlate callback to EPROBE_DEFER instead of dev_err() 126 * and EINVAL. For that, we must know the total clock count. 127 */ 128 unsigned int late_clk_count; 129 }; 130 131 /* 132 * Both factors (mult and div) must fit in 32 bits. When an operation overflows, 133 * this function throws away low bits so that factors still fit in 32 bits. 134 * 135 * Precision loss depends on amplitude of mult and div. Worst theoretical 136 * loss is: (UINT_MAX+1) / UINT_MAX - 1 = 2.3e-10. 137 * This is 1Hz every 4.3GHz. 138 */ 139 static void eqc_pll_downshift_factors(unsigned long *mult, unsigned long *div) 140 { 141 unsigned long biggest; 142 unsigned int shift; 143 144 /* This function can be removed if mult/div switch to unsigned long. */ 145 static_assert(sizeof_field(struct clk_fixed_factor, mult) == sizeof(unsigned int)); 146 static_assert(sizeof_field(struct clk_fixed_factor, div) == sizeof(unsigned int)); 147 148 /* No overflow, nothing to be done. */ 149 if (*mult <= UINT_MAX && *div <= UINT_MAX) 150 return; 151 152 /* 153 * Compute the shift required to bring the biggest factor into unsigned 154 * int range. That is, shift its highest set bit to the unsigned int 155 * most significant bit. 156 */ 157 biggest = max(*mult, *div); 158 shift = __fls(biggest) - (BITS_PER_BYTE * sizeof(unsigned int)) + 1; 159 160 *mult >>= shift; 161 *div >>= shift; 162 } 163 164 static int eqc_pll_parse_registers(u32 r0, u32 r1, unsigned long *mult, 165 unsigned long *div, unsigned long *acc) 166 { 167 unsigned long spread; 168 169 if (r0 & PCSR0_BYPASS) { 170 *mult = 1; 171 *div = 1; 172 *acc = 0; 173 return 0; 174 } 175 176 if (!(r0 & PCSR0_PLL_LOCKED)) 177 return -EINVAL; 178 179 *mult = FIELD_GET(PCSR0_INTIN, r0); 180 *div = FIELD_GET(PCSR0_REF_DIV, r0); 181 182 /* Fractional mode, in 2^20 (0x100000) parts. */ 183 if (r0 & PCSR0_DSM_EN) { 184 *div *= (1ULL << 20); 185 *mult = *mult * (1ULL << 20) + FIELD_GET(PCSR1_FRAC_IN, r1); 186 } 187 188 if (!*mult || !*div) 189 return -EINVAL; 190 191 if (r1 & (PCSR1_RESET | PCSR1_DIS_SSCG)) { 192 *acc = 0; 193 return 0; 194 } 195 196 /* 197 * Spread spectrum. 198 * 199 * Spread is in 1/1024 parts of frequency. Clock accuracy 200 * is half the spread value expressed in parts per billion. 201 * 202 * accuracy = (spread * 1e9) / (1024 * 2) 203 * 204 * Care is taken to avoid overflowing or losing precision. 205 */ 206 spread = FIELD_GET(PCSR1_SPREAD, r1); 207 *acc = DIV_ROUND_CLOSEST(spread * 1000000000, 1024 * 2); 208 209 if (r1 & PCSR1_DOWN_SPREAD) { 210 /* 211 * Downspreading: the central frequency is half a 212 * spread lower. 213 */ 214 *mult *= 2048 - spread; 215 *div *= 2048; 216 217 /* 218 * Previous operation might overflow 32 bits. If it 219 * does, throw away the least amount of low bits. 220 */ 221 eqc_pll_downshift_factors(mult, div); 222 } 223 224 return 0; 225 } 226 227 static void eqc_probe_init_plls(struct device *dev, const struct eqc_match_data *data, 228 void __iomem *base, struct clk_hw_onecell_data *cells) 229 { 230 unsigned long mult, div, acc; 231 const struct eqc_pll *pll; 232 struct clk_hw *hw; 233 unsigned int i; 234 u32 r0, r1; 235 u64 val; 236 int ret; 237 238 for (i = 0; i < data->pll_count; i++) { 239 pll = &data->plls[i]; 240 241 val = readq(base + pll->reg64); 242 r0 = val; 243 r1 = val >> 32; 244 245 ret = eqc_pll_parse_registers(r0, r1, &mult, &div, &acc); 246 if (ret) { 247 dev_warn(dev, "failed parsing state of %s\n", pll->name); 248 cells->hws[pll->index] = ERR_PTR(ret); 249 continue; 250 } 251 252 hw = clk_hw_register_fixed_factor_with_accuracy_fwname(dev, 253 dev->of_node, pll->name, "ref", 0, mult, div, acc); 254 cells->hws[pll->index] = hw; 255 if (IS_ERR(hw)) 256 dev_warn(dev, "failed registering %s: %pe\n", pll->name, hw); 257 } 258 } 259 260 static void eqc_probe_init_divs(struct device *dev, const struct eqc_match_data *data, 261 void __iomem *base, struct clk_hw_onecell_data *cells) 262 { 263 struct clk_parent_data parent_data = { }; 264 const struct eqc_div *div; 265 struct clk_hw *parent; 266 void __iomem *reg; 267 struct clk_hw *hw; 268 unsigned int i; 269 270 for (i = 0; i < data->div_count; i++) { 271 div = &data->divs[i]; 272 reg = base + div->reg; 273 parent = cells->hws[div->parent]; 274 275 if (IS_ERR(parent)) { 276 /* Parent is in early clk provider. */ 277 parent_data.index = div->parent; 278 parent_data.hw = NULL; 279 } else { 280 /* Avoid clock lookup when we already have the hw reference. */ 281 parent_data.index = 0; 282 parent_data.hw = parent; 283 } 284 285 hw = clk_hw_register_divider_table_parent_data(dev, div->name, 286 &parent_data, 0, reg, div->shift, div->width, 287 CLK_DIVIDER_EVEN_INTEGERS, NULL, NULL); 288 cells->hws[div->index] = hw; 289 if (IS_ERR(hw)) 290 dev_warn(dev, "failed registering %s: %pe\n", 291 div->name, hw); 292 } 293 } 294 295 static void eqc_probe_init_fixed_factors(struct device *dev, 296 const struct eqc_match_data *data, 297 struct clk_hw_onecell_data *cells) 298 { 299 const struct eqc_fixed_factor *ff; 300 struct clk_hw *hw, *parent_hw; 301 unsigned int i; 302 303 for (i = 0; i < data->fixed_factor_count; i++) { 304 ff = &data->fixed_factors[i]; 305 parent_hw = cells->hws[ff->parent]; 306 307 if (IS_ERR(parent_hw)) { 308 /* Parent is in early clk provider. */ 309 hw = clk_hw_register_fixed_factor_index(dev, ff->name, 310 ff->parent, 0, ff->mult, ff->div); 311 } else { 312 /* Avoid clock lookup when we already have the hw reference. */ 313 hw = clk_hw_register_fixed_factor_parent_hw(dev, ff->name, 314 parent_hw, 0, ff->mult, ff->div); 315 } 316 317 cells->hws[ff->index] = hw; 318 if (IS_ERR(hw)) 319 dev_warn(dev, "failed registering %s: %pe\n", 320 ff->name, hw); 321 } 322 } 323 324 static void eqc_auxdev_create_optional(struct device *dev, void __iomem *base, 325 const char *name) 326 { 327 struct auxiliary_device *adev; 328 329 if (name) { 330 adev = devm_auxiliary_device_create(dev, name, 331 (void __force *)base); 332 if (!adev) 333 dev_warn(dev, "failed creating auxiliary device %s.%s\n", 334 KBUILD_MODNAME, name); 335 } 336 } 337 338 static int eqc_probe(struct platform_device *pdev) 339 { 340 struct device *dev = &pdev->dev; 341 struct device_node *np = dev->of_node; 342 const struct eqc_match_data *data; 343 struct clk_hw_onecell_data *cells; 344 unsigned int i, clk_count; 345 struct resource *res; 346 void __iomem *base; 347 348 data = device_get_match_data(dev); 349 if (!data) 350 return 0; /* No clocks nor auxdevs, we are done. */ 351 352 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 353 if (!res) 354 return -ENODEV; 355 356 base = ioremap(res->start, resource_size(res)); 357 if (!base) 358 return -ENOMEM; 359 360 /* Init optional auxiliary devices. */ 361 eqc_auxdev_create_optional(dev, base, data->reset_auxdev_name); 362 eqc_auxdev_create_optional(dev, base, data->pinctrl_auxdev_name); 363 eqc_auxdev_create_optional(dev, base, data->eth_phy_auxdev_name); 364 365 if (data->pll_count + data->div_count + data->fixed_factor_count == 0) 366 return 0; /* Zero clocks, we are done. */ 367 368 clk_count = data->pll_count + data->div_count + 369 data->fixed_factor_count + data->early_clk_count; 370 cells = kzalloc_flex(*cells, hws, clk_count); 371 if (!cells) 372 return -ENOMEM; 373 374 cells->num = clk_count; 375 376 /* Early PLLs are marked as errors: the early provider will get queried. */ 377 for (i = 0; i < clk_count; i++) 378 cells->hws[i] = ERR_PTR(-EINVAL); 379 380 eqc_probe_init_plls(dev, data, base, cells); 381 382 eqc_probe_init_divs(dev, data, base, cells); 383 384 eqc_probe_init_fixed_factors(dev, data, cells); 385 386 return of_clk_add_hw_provider(np, of_clk_hw_onecell_get, cells); 387 } 388 389 /* Required early for GIC timer (pll-cpu) and UARTs (pll-per). */ 390 static const struct eqc_pll eqc_eyeq5_early_plls[] = { 391 { .index = EQ5C_PLL_CPU, .name = "pll-cpu", .reg64 = 0x02C }, 392 { .index = EQ5C_PLL_PER, .name = "pll-per", .reg64 = 0x05C }, 393 }; 394 395 static const struct eqc_pll eqc_eyeq5_plls[] = { 396 { .index = EQ5C_PLL_VMP, .name = "pll-vmp", .reg64 = 0x034 }, 397 { .index = EQ5C_PLL_PMA, .name = "pll-pma", .reg64 = 0x03C }, 398 { .index = EQ5C_PLL_VDI, .name = "pll-vdi", .reg64 = 0x044 }, 399 { .index = EQ5C_PLL_DDR0, .name = "pll-ddr0", .reg64 = 0x04C }, 400 { .index = EQ5C_PLL_PCI, .name = "pll-pci", .reg64 = 0x054 }, 401 { .index = EQ5C_PLL_PMAC, .name = "pll-pmac", .reg64 = 0x064 }, 402 { .index = EQ5C_PLL_MPC, .name = "pll-mpc", .reg64 = 0x06C }, 403 { .index = EQ5C_PLL_DDR1, .name = "pll-ddr1", .reg64 = 0x074 }, 404 }; 405 406 enum { 407 /* 408 * EQ5C_PLL_CPU children. 409 * EQ5C_PER_OCC_PCI is the last clock exposed in dt-bindings. 410 */ 411 EQ5C_CPU_OCC = EQ5C_PER_OCC_PCI + 1, 412 EQ5C_CPU_SI_CSS0, 413 EQ5C_CPU_CPC, 414 EQ5C_CPU_CM, 415 EQ5C_CPU_MEM, 416 EQ5C_CPU_OCC_ISRAM, 417 EQ5C_CPU_ISRAM, 418 EQ5C_CPU_OCC_DBU, 419 EQ5C_CPU_SI_DBU_TP, 420 421 /* 422 * EQ5C_PLL_VDI children. 423 */ 424 EQ5C_VDI_OCC_VDI, 425 EQ5C_VDI_VDI, 426 EQ5C_VDI_OCC_CAN_SER, 427 EQ5C_VDI_CAN_SER, 428 EQ5C_VDI_I2C_SER, 429 430 /* 431 * EQ5C_PLL_PER children. 432 */ 433 EQ5C_PER_PERIPH, 434 EQ5C_PER_CAN, 435 EQ5C_PER_TIMER, 436 EQ5C_PER_CCF, 437 EQ5C_PER_OCC_MJPEG, 438 EQ5C_PER_HSM, 439 EQ5C_PER_MJPEG, 440 EQ5C_PER_FCMU_A, 441 }; 442 443 static const struct eqc_fixed_factor eqc_eyeq5_early_fixed_factors[] = { 444 /* EQ5C_PLL_CPU children */ 445 { EQ5C_CPU_OCC, "occ-cpu", 1, 1, EQ5C_PLL_CPU }, 446 { EQ5C_CPU_SI_CSS0, "si-css0", 1, 1, EQ5C_CPU_OCC }, 447 { EQ5C_CPU_CORE0, "core0", 1, 1, EQ5C_CPU_SI_CSS0 }, 448 { EQ5C_CPU_CORE1, "core1", 1, 1, EQ5C_CPU_SI_CSS0 }, 449 { EQ5C_CPU_CORE2, "core2", 1, 1, EQ5C_CPU_SI_CSS0 }, 450 { EQ5C_CPU_CORE3, "core3", 1, 1, EQ5C_CPU_SI_CSS0 }, 451 452 /* EQ5C_PLL_PER children */ 453 { EQ5C_PER_OCC, "occ-periph", 1, 16, EQ5C_PLL_PER }, 454 { EQ5C_PER_UART, "uart", 1, 1, EQ5C_PER_OCC }, 455 }; 456 457 static const struct eqc_fixed_factor eqc_eyeq5_fixed_factors[] = { 458 /* EQ5C_PLL_CPU children */ 459 { EQ5C_CPU_CPC, "cpc", 1, 1, EQ5C_CPU_SI_CSS0 }, 460 { EQ5C_CPU_CM, "cm", 1, 1, EQ5C_CPU_SI_CSS0 }, 461 { EQ5C_CPU_MEM, "mem", 1, 1, EQ5C_CPU_SI_CSS0 }, 462 { EQ5C_CPU_OCC_ISRAM, "occ-isram", 1, 2, EQ5C_PLL_CPU }, 463 { EQ5C_CPU_ISRAM, "isram", 1, 1, EQ5C_CPU_OCC_ISRAM }, 464 { EQ5C_CPU_OCC_DBU, "occ-dbu", 1, 10, EQ5C_PLL_CPU }, 465 { EQ5C_CPU_SI_DBU_TP, "si-dbu-tp", 1, 1, EQ5C_CPU_OCC_DBU }, 466 467 /* EQ5C_PLL_VDI children */ 468 { EQ5C_VDI_OCC_VDI, "occ-vdi", 1, 2, EQ5C_PLL_VDI }, 469 { EQ5C_VDI_VDI, "vdi", 1, 1, EQ5C_VDI_OCC_VDI }, 470 { EQ5C_VDI_OCC_CAN_SER, "occ-can-ser", 1, 16, EQ5C_PLL_VDI }, 471 { EQ5C_VDI_CAN_SER, "can-ser", 1, 1, EQ5C_VDI_OCC_CAN_SER }, 472 { EQ5C_VDI_I2C_SER, "i2c-ser", 1, 20, EQ5C_PLL_VDI }, 473 474 /* EQ5C_PLL_PER children */ 475 { EQ5C_PER_PERIPH, "periph", 1, 1, EQ5C_PER_OCC }, 476 { EQ5C_PER_CAN, "can", 1, 1, EQ5C_PER_OCC }, 477 { EQ5C_PER_SPI, "spi", 1, 1, EQ5C_PER_OCC }, 478 { EQ5C_PER_I2C, "i2c", 1, 1, EQ5C_PER_OCC }, 479 { EQ5C_PER_TIMER, "timer", 1, 1, EQ5C_PER_OCC }, 480 { EQ5C_PER_GPIO, "gpio", 1, 1, EQ5C_PER_OCC }, 481 { EQ5C_PER_EMMC, "emmc-sys", 1, 10, EQ5C_PLL_PER }, 482 { EQ5C_PER_CCF, "ccf-ctrl", 1, 4, EQ5C_PLL_PER }, 483 { EQ5C_PER_OCC_MJPEG, "occ-mjpeg", 1, 2, EQ5C_PLL_PER }, 484 { EQ5C_PER_HSM, "hsm", 1, 1, EQ5C_PER_OCC_MJPEG }, 485 { EQ5C_PER_MJPEG, "mjpeg", 1, 1, EQ5C_PER_OCC_MJPEG }, 486 { EQ5C_PER_FCMU_A, "fcmu-a", 1, 20, EQ5C_PLL_PER }, 487 { EQ5C_PER_OCC_PCI, "occ-pci-sys", 1, 8, EQ5C_PLL_PER }, 488 }; 489 490 static const struct eqc_div eqc_eyeq5_divs[] = { 491 { 492 .index = EQ5C_DIV_OSPI, 493 .name = "div-ospi", 494 .parent = EQ5C_PLL_PER, 495 .reg = 0x11C, 496 .shift = 0, 497 .width = 4, 498 }, 499 }; 500 501 static const struct eqc_early_match_data eqc_eyeq5_early_match_data __initconst = { 502 .early_pll_count = ARRAY_SIZE(eqc_eyeq5_early_plls), 503 .early_plls = eqc_eyeq5_early_plls, 504 505 .early_fixed_factor_count = ARRAY_SIZE(eqc_eyeq5_early_fixed_factors), 506 .early_fixed_factors = eqc_eyeq5_early_fixed_factors, 507 508 .late_clk_count = ARRAY_SIZE(eqc_eyeq5_plls) + ARRAY_SIZE(eqc_eyeq5_divs) + 509 ARRAY_SIZE(eqc_eyeq5_fixed_factors), 510 }; 511 512 static const struct eqc_match_data eqc_eyeq5_match_data = { 513 .pll_count = ARRAY_SIZE(eqc_eyeq5_plls), 514 .plls = eqc_eyeq5_plls, 515 516 .div_count = ARRAY_SIZE(eqc_eyeq5_divs), 517 .divs = eqc_eyeq5_divs, 518 519 .fixed_factor_count = ARRAY_SIZE(eqc_eyeq5_fixed_factors), 520 .fixed_factors = eqc_eyeq5_fixed_factors, 521 522 .reset_auxdev_name = "reset", 523 .pinctrl_auxdev_name = "pinctrl", 524 .eth_phy_auxdev_name = "phy", 525 526 .early_clk_count = ARRAY_SIZE(eqc_eyeq5_early_plls) + 527 ARRAY_SIZE(eqc_eyeq5_early_fixed_factors), 528 }; 529 530 static const struct eqc_pll eqc_eyeq6l_plls[] = { 531 { .index = EQ6LC_PLL_DDR, .name = "pll-ddr", .reg64 = 0x02C }, 532 { .index = EQ6LC_PLL_CPU, .name = "pll-cpu", .reg64 = 0x034 }, /* also acc */ 533 { .index = EQ6LC_PLL_PER, .name = "pll-per", .reg64 = 0x03C }, 534 { .index = EQ6LC_PLL_VDI, .name = "pll-vdi", .reg64 = 0x044 }, 535 }; 536 537 static const struct eqc_match_data eqc_eyeq6l_match_data = { 538 .pll_count = ARRAY_SIZE(eqc_eyeq6l_plls), 539 .plls = eqc_eyeq6l_plls, 540 541 .reset_auxdev_name = "reset", 542 }; 543 544 static const struct eqc_pll eqc_eyeq6lplus_early_plls[] = { 545 { .index = EQ6LPC_PLL_CPU, .name = "pll-cpu", .reg64 = 0x058 }, 546 }; 547 548 static const struct eqc_pll eqc_eyeq6lplus_plls[] = { 549 { .index = EQ6LPC_PLL_DDR, .name = "pll-ddr", .reg64 = 0x02C }, 550 { .index = EQ6LPC_PLL_ACC, .name = "pll-acc", .reg64 = 0x034 }, 551 { .index = EQ6LPC_PLL_PER, .name = "pll-per", .reg64 = 0x03C }, 552 { .index = EQ6LPC_PLL_VDI, .name = "pll-vdi", .reg64 = 0x044 }, 553 }; 554 555 static const struct eqc_fixed_factor eqc_eyeq6lplus_early_fixed_factors[] = { 556 { EQ6LPC_CPU_OCC, "occ-cpu", 1, 1, EQ6LPC_PLL_CPU }, 557 }; 558 559 static const struct eqc_fixed_factor eqc_eyeq6lplus_fixed_factors[] = { 560 { EQ6LPC_DDR_OCC, "occ-ddr", 1, 1, EQ6LPC_PLL_DDR }, 561 562 { EQ6LPC_ACC_VDI, "vdi-div", 1, 10, EQ6LPC_PLL_ACC }, 563 { EQ6LPC_ACC_OCC, "occ-acc", 1, 1, EQ6LPC_PLL_ACC }, 564 { EQ6LPC_ACC_FCMU, "fcmu-a-clk", 1, 10, EQ6LPC_ACC_OCC }, 565 566 { EQ6LPC_PER_OCC, "occ-per", 1, 1, EQ6LPC_PLL_PER }, 567 { EQ6LPC_PER_I2C_SER, "i2c-ser-clk", 1, 10, EQ6LPC_PER_OCC }, 568 { EQ6LPC_PER_PCLK, "pclk", 1, 4, EQ6LPC_PER_OCC }, 569 { EQ6LPC_PER_TSU, "tsu-clk", 1, 8, EQ6LPC_PER_OCC }, 570 { EQ6LPC_PER_OSPI, "ospi-ref-clk", 1, 10, EQ6LPC_PER_OCC }, 571 { EQ6LPC_PER_GPIO, "gpio-clk", 1, 4, EQ6LPC_PER_OCC }, 572 { EQ6LPC_PER_TIMER, "timer-clk", 1, 4, EQ6LPC_PER_OCC }, 573 { EQ6LPC_PER_I2C, "i2c-clk", 1, 4, EQ6LPC_PER_OCC }, 574 { EQ6LPC_PER_UART, "uart-clk", 1, 4, EQ6LPC_PER_OCC }, 575 { EQ6LPC_PER_SPI, "spi-clk", 1, 4, EQ6LPC_PER_OCC }, 576 { EQ6LPC_PER_PERIPH, "periph-clk", 1, 1, EQ6LPC_PER_OCC }, 577 578 { EQ6LPC_VDI_OCC, "occ-vdi", 1, 1, EQ6LPC_PLL_VDI }, 579 }; 580 581 static const struct eqc_early_match_data eqc_eyeq6lplus_early_match_data __initconst = { 582 .early_pll_count = ARRAY_SIZE(eqc_eyeq6lplus_early_plls), 583 .early_plls = eqc_eyeq6lplus_early_plls, 584 585 .early_fixed_factor_count = ARRAY_SIZE(eqc_eyeq6lplus_early_fixed_factors), 586 .early_fixed_factors = eqc_eyeq6lplus_early_fixed_factors, 587 588 .late_clk_count = ARRAY_SIZE(eqc_eyeq6lplus_plls) + 589 ARRAY_SIZE(eqc_eyeq6lplus_fixed_factors), 590 }; 591 592 static const struct eqc_match_data eqc_eyeq6lplus_match_data = { 593 .pll_count = ARRAY_SIZE(eqc_eyeq6lplus_plls), 594 .plls = eqc_eyeq6lplus_plls, 595 596 .fixed_factor_count = ARRAY_SIZE(eqc_eyeq6lplus_fixed_factors), 597 .fixed_factors = eqc_eyeq6lplus_fixed_factors, 598 599 .reset_auxdev_name = "reset", 600 .pinctrl_auxdev_name = "pinctrl", 601 602 .early_clk_count = ARRAY_SIZE(eqc_eyeq6lplus_early_plls) + 603 ARRAY_SIZE(eqc_eyeq6lplus_early_fixed_factors), 604 }; 605 606 static const struct eqc_match_data eqc_eyeq6h_west_match_data = { 607 .reset_auxdev_name = "reset_west", 608 }; 609 610 static const struct eqc_pll eqc_eyeq6h_east_plls[] = { 611 { .index = 0, .name = "pll-east", .reg64 = 0x074 }, 612 }; 613 614 static const struct eqc_match_data eqc_eyeq6h_east_match_data = { 615 .pll_count = ARRAY_SIZE(eqc_eyeq6h_east_plls), 616 .plls = eqc_eyeq6h_east_plls, 617 618 .reset_auxdev_name = "reset_east", 619 }; 620 621 static const struct eqc_pll eqc_eyeq6h_south_plls[] = { 622 { .index = EQ6HC_SOUTH_PLL_VDI, .name = "pll-vdi", .reg64 = 0x000 }, 623 { .index = EQ6HC_SOUTH_PLL_PCIE, .name = "pll-pcie", .reg64 = 0x008 }, 624 { .index = EQ6HC_SOUTH_PLL_PER, .name = "pll-per", .reg64 = 0x010 }, 625 { .index = EQ6HC_SOUTH_PLL_ISP, .name = "pll-isp", .reg64 = 0x018 }, 626 }; 627 628 static const struct eqc_div eqc_eyeq6h_south_divs[] = { 629 { 630 .index = EQ6HC_SOUTH_DIV_EMMC, 631 .name = "div-emmc", 632 .parent = EQ6HC_SOUTH_PLL_PER, 633 .reg = 0x070, 634 .shift = 4, 635 .width = 4, 636 }, 637 { 638 .index = EQ6HC_SOUTH_DIV_OSPI_REF, 639 .name = "div-ospi-ref", 640 .parent = EQ6HC_SOUTH_PLL_PER, 641 .reg = 0x090, 642 .shift = 4, 643 .width = 4, 644 }, 645 { 646 .index = EQ6HC_SOUTH_DIV_OSPI_SYS, 647 .name = "div-ospi-sys", 648 .parent = EQ6HC_SOUTH_PLL_PER, 649 .reg = 0x090, 650 .shift = 8, 651 .width = 1, 652 }, 653 { 654 .index = EQ6HC_SOUTH_DIV_TSU, 655 .name = "div-tsu", 656 .parent = EQ6HC_SOUTH_PLL_PCIE, 657 .reg = 0x098, 658 .shift = 4, 659 .width = 8, 660 }, 661 }; 662 663 static const struct eqc_match_data eqc_eyeq6h_south_match_data = { 664 .pll_count = ARRAY_SIZE(eqc_eyeq6h_south_plls), 665 .plls = eqc_eyeq6h_south_plls, 666 667 .div_count = ARRAY_SIZE(eqc_eyeq6h_south_divs), 668 .divs = eqc_eyeq6h_south_divs, 669 }; 670 671 static const struct eqc_pll eqc_eyeq6h_ddr0_plls[] = { 672 { .index = 0, .name = "pll-ddr0", .reg64 = 0x074 }, 673 }; 674 675 static const struct eqc_match_data eqc_eyeq6h_ddr0_match_data = { 676 .pll_count = ARRAY_SIZE(eqc_eyeq6h_ddr0_plls), 677 .plls = eqc_eyeq6h_ddr0_plls, 678 }; 679 680 static const struct eqc_pll eqc_eyeq6h_ddr1_plls[] = { 681 { .index = 0, .name = "pll-ddr1", .reg64 = 0x074 }, 682 }; 683 684 static const struct eqc_match_data eqc_eyeq6h_ddr1_match_data = { 685 .pll_count = ARRAY_SIZE(eqc_eyeq6h_ddr1_plls), 686 .plls = eqc_eyeq6h_ddr1_plls, 687 }; 688 689 static const struct eqc_pll eqc_eyeq6h_acc_plls[] = { 690 { .index = EQ6HC_ACC_PLL_XNN, .name = "pll-xnn", .reg64 = 0x040 }, 691 { .index = EQ6HC_ACC_PLL_VMP, .name = "pll-vmp", .reg64 = 0x050 }, 692 { .index = EQ6HC_ACC_PLL_PMA, .name = "pll-pma", .reg64 = 0x05C }, 693 { .index = EQ6HC_ACC_PLL_MPC, .name = "pll-mpc", .reg64 = 0x068 }, 694 { .index = EQ6HC_ACC_PLL_NOC, .name = "pll-noc", .reg64 = 0x070 }, 695 }; 696 697 static const struct eqc_match_data eqc_eyeq6h_acc_match_data = { 698 .pll_count = ARRAY_SIZE(eqc_eyeq6h_acc_plls), 699 .plls = eqc_eyeq6h_acc_plls, 700 701 .reset_auxdev_name = "reset_acc", 702 }; 703 704 static const struct of_device_id eqc_match_table[] = { 705 { .compatible = "mobileye,eyeq5-olb", .data = &eqc_eyeq5_match_data }, 706 { .compatible = "mobileye,eyeq6l-olb", .data = &eqc_eyeq6l_match_data }, 707 { .compatible = "mobileye,eyeq6lplus-olb", .data = &eqc_eyeq6lplus_match_data }, 708 { .compatible = "mobileye,eyeq6h-west-olb", .data = &eqc_eyeq6h_west_match_data }, 709 { .compatible = "mobileye,eyeq6h-east-olb", .data = &eqc_eyeq6h_east_match_data }, 710 { .compatible = "mobileye,eyeq6h-south-olb", .data = &eqc_eyeq6h_south_match_data }, 711 { .compatible = "mobileye,eyeq6h-ddr0-olb", .data = &eqc_eyeq6h_ddr0_match_data }, 712 { .compatible = "mobileye,eyeq6h-ddr1-olb", .data = &eqc_eyeq6h_ddr1_match_data }, 713 { .compatible = "mobileye,eyeq6h-acc-olb", .data = &eqc_eyeq6h_acc_match_data }, 714 {} 715 }; 716 717 static struct platform_driver eqc_driver = { 718 .probe = eqc_probe, 719 .driver = { 720 .name = "clk-eyeq", 721 .of_match_table = eqc_match_table, 722 .suppress_bind_attrs = true, 723 }, 724 }; 725 builtin_platform_driver(eqc_driver); 726 727 /* Required early for GIC timer. */ 728 static const struct eqc_pll eqc_eyeq6h_central_early_plls[] = { 729 { .index = EQ6HC_CENTRAL_PLL_CPU, .name = "pll-cpu", .reg64 = 0x02C }, 730 }; 731 732 static const struct eqc_fixed_factor eqc_eyeq6h_central_early_fixed_factors[] = { 733 { EQ6HC_CENTRAL_CPU_OCC, "occ-cpu", 1, 1, EQ6HC_CENTRAL_PLL_CPU }, 734 }; 735 736 static const struct eqc_early_match_data eqc_eyeq6h_central_early_match_data __initconst = { 737 .early_pll_count = ARRAY_SIZE(eqc_eyeq6h_central_early_plls), 738 .early_plls = eqc_eyeq6h_central_early_plls, 739 740 .early_fixed_factor_count = ARRAY_SIZE(eqc_eyeq6h_central_early_fixed_factors), 741 .early_fixed_factors = eqc_eyeq6h_central_early_fixed_factors, 742 }; 743 744 /* Required early for UART. */ 745 static const struct eqc_pll eqc_eyeq6h_west_early_plls[] = { 746 { .index = EQ6HC_WEST_PLL_PER, .name = "pll-west", .reg64 = 0x074 }, 747 }; 748 749 static const struct eqc_fixed_factor eqc_eyeq6h_west_early_fixed_factors[] = { 750 { EQ6HC_WEST_PER_OCC, "west-per-occ", 1, 10, EQ6HC_WEST_PLL_PER }, 751 { EQ6HC_WEST_PER_UART, "west-per-uart", 1, 1, EQ6HC_WEST_PER_OCC }, 752 }; 753 754 static const struct eqc_early_match_data eqc_eyeq6h_west_early_match_data __initconst = { 755 .early_pll_count = ARRAY_SIZE(eqc_eyeq6h_west_early_plls), 756 .early_plls = eqc_eyeq6h_west_early_plls, 757 758 .early_fixed_factor_count = ARRAY_SIZE(eqc_eyeq6h_west_early_fixed_factors), 759 .early_fixed_factors = eqc_eyeq6h_west_early_fixed_factors, 760 }; 761 762 static void __init eqc_early_init(struct device_node *np, 763 const struct eqc_early_match_data *early_data) 764 { 765 struct clk_hw_onecell_data *cells; 766 unsigned int i, clk_count; 767 void __iomem *base; 768 int ret; 769 770 clk_count = early_data->early_pll_count + early_data->early_fixed_factor_count + 771 early_data->late_clk_count; 772 cells = kzalloc_flex(*cells, hws, clk_count); 773 if (!cells) { 774 ret = -ENOMEM; 775 goto err; 776 } 777 778 cells->num = clk_count; 779 780 /* 781 * Mark all clocks as deferred; some are registered here, the rest at 782 * platform device probe. 783 * 784 * Once the platform device is probed, its provider will take priority 785 * when looking up clocks. 786 */ 787 for (i = 0; i < clk_count; i++) 788 cells->hws[i] = ERR_PTR(-EPROBE_DEFER); 789 790 /* Offsets (reg64) of early PLLs are relative to OLB block. */ 791 base = of_iomap(np, 0); 792 if (!base) { 793 ret = -ENODEV; 794 goto err; 795 } 796 797 for (i = 0; i < early_data->early_pll_count; i++) { 798 const struct eqc_pll *pll = &early_data->early_plls[i]; 799 unsigned long mult, div, acc; 800 struct clk_hw *hw; 801 u32 r0, r1; 802 u64 val; 803 804 val = readq(base + pll->reg64); 805 r0 = val; 806 r1 = val >> 32; 807 808 ret = eqc_pll_parse_registers(r0, r1, &mult, &div, &acc); 809 if (ret) { 810 pr_err("failed parsing state of %s\n", pll->name); 811 goto err; 812 } 813 814 hw = clk_hw_register_fixed_factor_with_accuracy_fwname(NULL, 815 np, pll->name, "ref", 0, mult, div, acc); 816 cells->hws[pll->index] = hw; 817 if (IS_ERR(hw)) { 818 pr_err("failed registering %s: %pe\n", pll->name, hw); 819 ret = PTR_ERR(hw); 820 goto err; 821 } 822 } 823 824 for (i = 0; i < early_data->early_fixed_factor_count; i++) { 825 const struct eqc_fixed_factor *ff = &early_data->early_fixed_factors[i]; 826 struct clk_hw *parent_hw = cells->hws[ff->parent]; 827 struct clk_hw *hw; 828 829 hw = clk_hw_register_fixed_factor_parent_hw(NULL, ff->name, 830 parent_hw, 0, ff->mult, ff->div); 831 cells->hws[ff->index] = hw; 832 if (IS_ERR(hw)) { 833 pr_err("failed registering %s: %pe\n", ff->name, hw); 834 ret = PTR_ERR(hw); 835 goto err; 836 } 837 } 838 839 ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, cells); 840 if (ret) { 841 pr_err("failed registering clk provider: %d\n", ret); 842 goto err; 843 } 844 845 return; 846 847 err: 848 /* 849 * We are doomed. The system will not be able to boot. 850 * 851 * Let's still try to be good citizens by freeing resources and print 852 * a last error message that might help debugging. 853 */ 854 855 pr_err("failed clk init: %d\n", ret); 856 857 if (cells) { 858 of_clk_del_provider(np); 859 860 for (i = 0; i < early_data->early_pll_count; i++) { 861 const struct eqc_pll *pll = &early_data->early_plls[i]; 862 struct clk_hw *hw = cells->hws[pll->index]; 863 864 if (!IS_ERR_OR_NULL(hw)) 865 clk_hw_unregister_fixed_factor(hw); 866 } 867 868 kfree(cells); 869 } 870 } 871 872 static void __init eqc_eyeq5_early_init(struct device_node *np) 873 { 874 eqc_early_init(np, &eqc_eyeq5_early_match_data); 875 } 876 CLK_OF_DECLARE_DRIVER(eqc_eyeq5, "mobileye,eyeq5-olb", eqc_eyeq5_early_init); 877 878 static void __init eqc_eyeq6h_central_early_init(struct device_node *np) 879 { 880 eqc_early_init(np, &eqc_eyeq6h_central_early_match_data); 881 } 882 CLK_OF_DECLARE_DRIVER(eqc_eyeq6h_central, "mobileye,eyeq6h-central-olb", 883 eqc_eyeq6h_central_early_init); 884 885 static void __init eqc_eyeq6h_west_early_init(struct device_node *np) 886 { 887 eqc_early_init(np, &eqc_eyeq6h_west_early_match_data); 888 } 889 CLK_OF_DECLARE_DRIVER(eqc_eyeq6h_west, "mobileye,eyeq6h-west-olb", 890 eqc_eyeq6h_west_early_init); 891 892 static void __init eqc_eyeq6lplus_early_init(struct device_node *np) 893 { 894 eqc_early_init(np, &eqc_eyeq6lplus_early_match_data); 895 } 896 CLK_OF_DECLARE_DRIVER(eqc_eyeq6lplus, "mobileye,eyeq6lplus-olb", eqc_eyeq6lplus_early_init); 897