1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * SAMA7G5 PMC code. 4 * 5 * Copyright (C) 2020 Microchip Technology Inc. and its subsidiaries 6 * 7 * Author: Claudiu Beznea <claudiu.beznea@microchip.com> 8 * 9 */ 10 #include <linux/clk.h> 11 #include <linux/clk-provider.h> 12 #include <linux/mfd/syscon.h> 13 #include <linux/slab.h> 14 15 #include <dt-bindings/clock/at91.h> 16 17 #include "pmc.h" 18 19 #define SAMA7G5_INIT_TABLE(_table, _count) \ 20 do { \ 21 u8 _i; \ 22 for (_i = 0; _i < (_count); _i++) \ 23 (_table)[_i] = _i; \ 24 } while (0) 25 26 #define SAMA7G5_FILL_TABLE(_to, _from, _count) \ 27 do { \ 28 u8 _i; \ 29 for (_i = 0; _i < (_count); _i++) { \ 30 (_to)[_i] = (_from)[_i]; \ 31 } \ 32 } while (0) 33 34 static DEFINE_SPINLOCK(pmc_pll_lock); 35 static DEFINE_SPINLOCK(pmc_mck0_lock); 36 static DEFINE_SPINLOCK(pmc_mckX_lock); 37 38 /* 39 * PLL clocks identifiers 40 * @PLL_ID_CPU: CPU PLL identifier 41 * @PLL_ID_SYS: System PLL identifier 42 * @PLL_ID_DDR: DDR PLL identifier 43 * @PLL_ID_IMG: Image subsystem PLL identifier 44 * @PLL_ID_BAUD: Baud PLL identifier 45 * @PLL_ID_AUDIO: Audio PLL identifier 46 * @PLL_ID_ETH: Ethernet PLL identifier 47 */ 48 enum pll_ids { 49 PLL_ID_CPU, 50 PLL_ID_SYS, 51 PLL_ID_DDR, 52 PLL_ID_IMG, 53 PLL_ID_BAUD, 54 PLL_ID_AUDIO, 55 PLL_ID_ETH, 56 PLL_ID_MAX, 57 }; 58 59 /* 60 * PLL type identifiers 61 * @PLL_TYPE_FRAC: fractional PLL identifier 62 * @PLL_TYPE_DIV: divider PLL identifier 63 */ 64 enum pll_type { 65 PLL_TYPE_FRAC, 66 PLL_TYPE_DIV, 67 }; 68 69 /* Layout for fractional PLLs. */ 70 static const struct clk_pll_layout pll_layout_frac = { 71 .mul_mask = GENMASK(31, 24), 72 .frac_mask = GENMASK(21, 0), 73 .mul_shift = 24, 74 .frac_shift = 0, 75 }; 76 77 /* Layout for DIVPMC dividers. */ 78 static const struct clk_pll_layout pll_layout_divpmc = { 79 .div_mask = GENMASK(7, 0), 80 .endiv_mask = BIT(29), 81 .div_shift = 0, 82 .endiv_shift = 29, 83 }; 84 85 /* Layout for DIVIO dividers. */ 86 static const struct clk_pll_layout pll_layout_divio = { 87 .div_mask = GENMASK(19, 12), 88 .endiv_mask = BIT(30), 89 .div_shift = 12, 90 .endiv_shift = 30, 91 }; 92 93 /* 94 * CPU PLL output range. 95 * Notice: The upper limit has been setup to 1000000002 due to hardware 96 * block which cannot output exactly 1GHz. 97 */ 98 static const struct clk_range cpu_pll_outputs[] = { 99 { .min = 2343750, .max = 1000000002 }, 100 }; 101 102 /* PLL output range. */ 103 static const struct clk_range pll_outputs[] = { 104 { .min = 2343750, .max = 1200000000 }, 105 }; 106 107 /* CPU PLL characteristics. */ 108 static const struct clk_pll_characteristics cpu_pll_characteristics = { 109 .input = { .min = 12000000, .max = 50000000 }, 110 .num_output = ARRAY_SIZE(cpu_pll_outputs), 111 .output = cpu_pll_outputs, 112 }; 113 114 /* PLL characteristics. */ 115 static const struct clk_pll_characteristics pll_characteristics = { 116 .input = { .min = 12000000, .max = 50000000 }, 117 .num_output = ARRAY_SIZE(pll_outputs), 118 .output = pll_outputs, 119 }; 120 121 /* 122 * PLL clocks description 123 * @n: clock name 124 * @p: clock parent 125 * @l: clock layout 126 * @c: clock characteristics 127 * @t: clock type 128 * @f: clock flags 129 * @eid: export index in sama7g5->chws[] array 130 * @safe_div: intermediate divider need to be set on PRE_RATE_CHANGE 131 * notification 132 */ 133 static const struct { 134 const char *n; 135 const char *p; 136 const struct clk_pll_layout *l; 137 const struct clk_pll_characteristics *c; 138 unsigned long f; 139 u8 t; 140 u8 eid; 141 u8 safe_div; 142 } sama7g5_plls[][PLL_ID_MAX] = { 143 [PLL_ID_CPU] = { 144 { .n = "cpupll_fracck", 145 .p = "mainck", 146 .l = &pll_layout_frac, 147 .c = &cpu_pll_characteristics, 148 .t = PLL_TYPE_FRAC, 149 /* 150 * This feeds cpupll_divpmcck which feeds CPU. It should 151 * not be disabled. 152 */ 153 .f = CLK_IS_CRITICAL, }, 154 155 { .n = "cpupll_divpmcck", 156 .p = "cpupll_fracck", 157 .l = &pll_layout_divpmc, 158 .c = &cpu_pll_characteristics, 159 .t = PLL_TYPE_DIV, 160 /* This feeds CPU. It should not be disabled. */ 161 .f = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 162 .eid = PMC_CPUPLL, 163 /* 164 * Safe div=15 should be safe even for switching b/w 1GHz and 165 * 90MHz (frac pll might go up to 1.2GHz). 166 */ 167 .safe_div = 15, }, 168 }, 169 170 [PLL_ID_SYS] = { 171 { .n = "syspll_fracck", 172 .p = "mainck", 173 .l = &pll_layout_frac, 174 .c = &pll_characteristics, 175 .t = PLL_TYPE_FRAC, 176 /* 177 * This feeds syspll_divpmcck which may feed critical parts 178 * of the systems like timers. Therefore it should not be 179 * disabled. 180 */ 181 .f = CLK_IS_CRITICAL | CLK_SET_RATE_GATE, }, 182 183 { .n = "syspll_divpmcck", 184 .p = "syspll_fracck", 185 .l = &pll_layout_divpmc, 186 .c = &pll_characteristics, 187 .t = PLL_TYPE_DIV, 188 /* 189 * This may feed critical parts of the systems like timers. 190 * Therefore it should not be disabled. 191 */ 192 .f = CLK_IS_CRITICAL | CLK_SET_RATE_GATE, 193 .eid = PMC_SYSPLL, }, 194 }, 195 196 [PLL_ID_DDR] = { 197 { .n = "ddrpll_fracck", 198 .p = "mainck", 199 .l = &pll_layout_frac, 200 .c = &pll_characteristics, 201 .t = PLL_TYPE_FRAC, 202 /* 203 * This feeds ddrpll_divpmcck which feeds DDR. It should not 204 * be disabled. 205 */ 206 .f = CLK_IS_CRITICAL | CLK_SET_RATE_GATE, }, 207 208 { .n = "ddrpll_divpmcck", 209 .p = "ddrpll_fracck", 210 .l = &pll_layout_divpmc, 211 .c = &pll_characteristics, 212 .t = PLL_TYPE_DIV, 213 /* This feeds DDR. It should not be disabled. */ 214 .f = CLK_IS_CRITICAL | CLK_SET_RATE_GATE, }, 215 }, 216 217 [PLL_ID_IMG] = { 218 { .n = "imgpll_fracck", 219 .p = "mainck", 220 .l = &pll_layout_frac, 221 .c = &pll_characteristics, 222 .t = PLL_TYPE_FRAC, 223 .f = CLK_SET_RATE_GATE, }, 224 225 { .n = "imgpll_divpmcck", 226 .p = "imgpll_fracck", 227 .l = &pll_layout_divpmc, 228 .c = &pll_characteristics, 229 .t = PLL_TYPE_DIV, 230 .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | 231 CLK_SET_RATE_PARENT, }, 232 }, 233 234 [PLL_ID_BAUD] = { 235 { .n = "baudpll_fracck", 236 .p = "mainck", 237 .l = &pll_layout_frac, 238 .c = &pll_characteristics, 239 .t = PLL_TYPE_FRAC, 240 .f = CLK_SET_RATE_GATE, }, 241 242 { .n = "baudpll_divpmcck", 243 .p = "baudpll_fracck", 244 .l = &pll_layout_divpmc, 245 .c = &pll_characteristics, 246 .t = PLL_TYPE_DIV, 247 .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | 248 CLK_SET_RATE_PARENT, }, 249 }, 250 251 [PLL_ID_AUDIO] = { 252 { .n = "audiopll_fracck", 253 .p = "main_xtal", 254 .l = &pll_layout_frac, 255 .c = &pll_characteristics, 256 .t = PLL_TYPE_FRAC, 257 .f = CLK_SET_RATE_GATE, }, 258 259 { .n = "audiopll_divpmcck", 260 .p = "audiopll_fracck", 261 .l = &pll_layout_divpmc, 262 .c = &pll_characteristics, 263 .t = PLL_TYPE_DIV, 264 .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | 265 CLK_SET_RATE_PARENT, 266 .eid = PMC_AUDIOPMCPLL, }, 267 268 { .n = "audiopll_diviock", 269 .p = "audiopll_fracck", 270 .l = &pll_layout_divio, 271 .c = &pll_characteristics, 272 .t = PLL_TYPE_DIV, 273 .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | 274 CLK_SET_RATE_PARENT, 275 .eid = PMC_AUDIOIOPLL, }, 276 }, 277 278 [PLL_ID_ETH] = { 279 { .n = "ethpll_fracck", 280 .p = "main_xtal", 281 .l = &pll_layout_frac, 282 .c = &pll_characteristics, 283 .t = PLL_TYPE_FRAC, 284 .f = CLK_SET_RATE_GATE, }, 285 286 { .n = "ethpll_divpmcck", 287 .p = "ethpll_fracck", 288 .l = &pll_layout_divpmc, 289 .c = &pll_characteristics, 290 .t = PLL_TYPE_DIV, 291 .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | 292 CLK_SET_RATE_PARENT, }, 293 }, 294 }; 295 296 /* 297 * Master clock (MCK[1..4]) description 298 * @n: clock name 299 * @ep: extra parents names array 300 * @ep_chg_chg_id: index in parents array that specifies the changeable 301 * parent 302 * @ep_count: extra parents count 303 * @ep_mux_table: mux table for extra parents 304 * @id: clock id 305 * @c: true if clock is critical and cannot be disabled 306 */ 307 static const struct { 308 const char *n; 309 const char *ep[4]; 310 int ep_chg_id; 311 u8 ep_count; 312 u8 ep_mux_table[4]; 313 u8 id; 314 u8 c; 315 } sama7g5_mckx[] = { 316 { .n = "mck1", 317 .id = 1, 318 .ep = { "syspll_divpmcck", }, 319 .ep_mux_table = { 5, }, 320 .ep_count = 1, 321 .ep_chg_id = INT_MIN, 322 .c = 1, }, 323 324 { .n = "mck2", 325 .id = 2, 326 .ep = { "ddrpll_divpmcck", }, 327 .ep_mux_table = { 6, }, 328 .ep_count = 1, 329 .ep_chg_id = INT_MIN, 330 .c = 1, }, 331 332 { .n = "mck3", 333 .id = 3, 334 .ep = { "syspll_divpmcck", "ddrpll_divpmcck", "imgpll_divpmcck", }, 335 .ep_mux_table = { 5, 6, 7, }, 336 .ep_count = 3, 337 .ep_chg_id = 5, }, 338 339 { .n = "mck4", 340 .id = 4, 341 .ep = { "syspll_divpmcck", }, 342 .ep_mux_table = { 5, }, 343 .ep_count = 1, 344 .ep_chg_id = INT_MIN, 345 .c = 1, }, 346 }; 347 348 /* 349 * System clock description 350 * @n: clock name 351 * @p: clock parent name 352 * @id: clock id 353 */ 354 static const struct { 355 const char *n; 356 const char *p; 357 u8 id; 358 } sama7g5_systemck[] = { 359 { .n = "pck0", .p = "prog0", .id = 8, }, 360 { .n = "pck1", .p = "prog1", .id = 9, }, 361 { .n = "pck2", .p = "prog2", .id = 10, }, 362 { .n = "pck3", .p = "prog3", .id = 11, }, 363 { .n = "pck4", .p = "prog4", .id = 12, }, 364 { .n = "pck5", .p = "prog5", .id = 13, }, 365 { .n = "pck6", .p = "prog6", .id = 14, }, 366 { .n = "pck7", .p = "prog7", .id = 15, }, 367 }; 368 369 /* Mux table for programmable clocks. */ 370 static u32 sama7g5_prog_mux_table[] = { 0, 1, 2, 5, 6, 7, 8, 9, 10, }; 371 372 /* 373 * Peripheral clock description 374 * @n: clock name 375 * @p: clock parent name 376 * @r: clock range values 377 * @id: clock id 378 * @chgp: index in parent array of the changeable parent 379 */ 380 static const struct { 381 const char *n; 382 const char *p; 383 struct clk_range r; 384 u8 chgp; 385 u8 id; 386 } sama7g5_periphck[] = { 387 { .n = "pioA_clk", .p = "mck0", .id = 11, }, 388 { .n = "securam_clk", .p = "mck0", .id = 18, }, 389 { .n = "sfr_clk", .p = "mck1", .id = 19, }, 390 { .n = "hsmc_clk", .p = "mck1", .id = 21, }, 391 { .n = "xdmac0_clk", .p = "mck1", .id = 22, }, 392 { .n = "xdmac1_clk", .p = "mck1", .id = 23, }, 393 { .n = "xdmac2_clk", .p = "mck1", .id = 24, }, 394 { .n = "acc_clk", .p = "mck1", .id = 25, }, 395 { .n = "aes_clk", .p = "mck1", .id = 27, }, 396 { .n = "tzaesbasc_clk", .p = "mck1", .id = 28, }, 397 { .n = "asrc_clk", .p = "mck1", .id = 30, .r = { .max = 200000000, }, }, 398 { .n = "cpkcc_clk", .p = "mck0", .id = 32, }, 399 { .n = "csi_clk", .p = "mck3", .id = 33, .r = { .max = 266000000, }, .chgp = 1, }, 400 { .n = "csi2dc_clk", .p = "mck3", .id = 34, .r = { .max = 266000000, }, .chgp = 1, }, 401 { .n = "eic_clk", .p = "mck1", .id = 37, }, 402 { .n = "flex0_clk", .p = "mck1", .id = 38, }, 403 { .n = "flex1_clk", .p = "mck1", .id = 39, }, 404 { .n = "flex2_clk", .p = "mck1", .id = 40, }, 405 { .n = "flex3_clk", .p = "mck1", .id = 41, }, 406 { .n = "flex4_clk", .p = "mck1", .id = 42, }, 407 { .n = "flex5_clk", .p = "mck1", .id = 43, }, 408 { .n = "flex6_clk", .p = "mck1", .id = 44, }, 409 { .n = "flex7_clk", .p = "mck1", .id = 45, }, 410 { .n = "flex8_clk", .p = "mck1", .id = 46, }, 411 { .n = "flex9_clk", .p = "mck1", .id = 47, }, 412 { .n = "flex10_clk", .p = "mck1", .id = 48, }, 413 { .n = "flex11_clk", .p = "mck1", .id = 49, }, 414 { .n = "gmac0_clk", .p = "mck1", .id = 51, }, 415 { .n = "gmac1_clk", .p = "mck1", .id = 52, }, 416 { .n = "icm_clk", .p = "mck1", .id = 55, }, 417 { .n = "isc_clk", .p = "mck3", .id = 56, .r = { .max = 266000000, }, .chgp = 1, }, 418 { .n = "i2smcc0_clk", .p = "mck1", .id = 57, .r = { .max = 200000000, }, }, 419 { .n = "i2smcc1_clk", .p = "mck1", .id = 58, .r = { .max = 200000000, }, }, 420 { .n = "matrix_clk", .p = "mck1", .id = 60, }, 421 { .n = "mcan0_clk", .p = "mck1", .id = 61, .r = { .max = 200000000, }, }, 422 { .n = "mcan1_clk", .p = "mck1", .id = 62, .r = { .max = 200000000, }, }, 423 { .n = "mcan2_clk", .p = "mck1", .id = 63, .r = { .max = 200000000, }, }, 424 { .n = "mcan3_clk", .p = "mck1", .id = 64, .r = { .max = 200000000, }, }, 425 { .n = "mcan4_clk", .p = "mck1", .id = 65, .r = { .max = 200000000, }, }, 426 { .n = "mcan5_clk", .p = "mck1", .id = 66, .r = { .max = 200000000, }, }, 427 { .n = "pdmc0_clk", .p = "mck1", .id = 68, .r = { .max = 200000000, }, }, 428 { .n = "pdmc1_clk", .p = "mck1", .id = 69, .r = { .max = 200000000, }, }, 429 { .n = "pit64b0_clk", .p = "mck1", .id = 70, }, 430 { .n = "pit64b1_clk", .p = "mck1", .id = 71, }, 431 { .n = "pit64b2_clk", .p = "mck1", .id = 72, }, 432 { .n = "pit64b3_clk", .p = "mck1", .id = 73, }, 433 { .n = "pit64b4_clk", .p = "mck1", .id = 74, }, 434 { .n = "pit64b5_clk", .p = "mck1", .id = 75, }, 435 { .n = "pwm_clk", .p = "mck1", .id = 77, }, 436 { .n = "qspi0_clk", .p = "mck1", .id = 78, }, 437 { .n = "qspi1_clk", .p = "mck1", .id = 79, }, 438 { .n = "sdmmc0_clk", .p = "mck1", .id = 80, }, 439 { .n = "sdmmc1_clk", .p = "mck1", .id = 81, }, 440 { .n = "sdmmc2_clk", .p = "mck1", .id = 82, }, 441 { .n = "sha_clk", .p = "mck1", .id = 83, }, 442 { .n = "spdifrx_clk", .p = "mck1", .id = 84, .r = { .max = 200000000, }, }, 443 { .n = "spdiftx_clk", .p = "mck1", .id = 85, .r = { .max = 200000000, }, }, 444 { .n = "ssc0_clk", .p = "mck1", .id = 86, .r = { .max = 200000000, }, }, 445 { .n = "ssc1_clk", .p = "mck1", .id = 87, .r = { .max = 200000000, }, }, 446 { .n = "tcb0_ch0_clk", .p = "mck1", .id = 88, .r = { .max = 200000000, }, }, 447 { .n = "tcb0_ch1_clk", .p = "mck1", .id = 89, .r = { .max = 200000000, }, }, 448 { .n = "tcb0_ch2_clk", .p = "mck1", .id = 90, .r = { .max = 200000000, }, }, 449 { .n = "tcb1_ch0_clk", .p = "mck1", .id = 91, .r = { .max = 200000000, }, }, 450 { .n = "tcb1_ch1_clk", .p = "mck1", .id = 92, .r = { .max = 200000000, }, }, 451 { .n = "tcb1_ch2_clk", .p = "mck1", .id = 93, .r = { .max = 200000000, }, }, 452 { .n = "tcpca_clk", .p = "mck1", .id = 94, }, 453 { .n = "tcpcb_clk", .p = "mck1", .id = 95, }, 454 { .n = "tdes_clk", .p = "mck1", .id = 96, }, 455 { .n = "trng_clk", .p = "mck1", .id = 97, }, 456 { .n = "udphsa_clk", .p = "mck1", .id = 104, }, 457 { .n = "udphsb_clk", .p = "mck1", .id = 105, }, 458 { .n = "uhphs_clk", .p = "mck1", .id = 106, }, 459 }; 460 461 /* 462 * Generic clock description 463 * @n: clock name 464 * @pp: PLL parents 465 * @pp_mux_table: PLL parents mux table 466 * @r: clock output range 467 * @pp_chg_id: id in parent array of changeable PLL parent 468 * @pp_count: PLL parents count 469 * @id: clock id 470 */ 471 static const struct { 472 const char *n; 473 const char *pp[8]; 474 const char pp_mux_table[8]; 475 struct clk_range r; 476 int pp_chg_id; 477 u8 pp_count; 478 u8 id; 479 } sama7g5_gck[] = { 480 { .n = "adc_gclk", 481 .id = 26, 482 .r = { .max = 100000000, }, 483 .pp = { "syspll_divpmcck", "imgpll_divpmcck", "audiopll_divpmcck", }, 484 .pp_mux_table = { 5, 7, 9, }, 485 .pp_count = 3, 486 .pp_chg_id = INT_MIN, }, 487 488 { .n = "asrc_gclk", 489 .id = 30, 490 .r = { .max = 200000000 }, 491 .pp = { "audiopll_divpmcck", }, 492 .pp_mux_table = { 9, }, 493 .pp_count = 1, 494 .pp_chg_id = 3, }, 495 496 { .n = "csi_gclk", 497 .id = 33, 498 .r = { .max = 27000000 }, 499 .pp = { "ddrpll_divpmcck", "imgpll_divpmcck", }, 500 .pp_mux_table = { 6, 7, }, 501 .pp_count = 2, 502 .pp_chg_id = INT_MIN, }, 503 504 { .n = "flex0_gclk", 505 .id = 38, 506 .r = { .max = 200000000 }, 507 .pp = { "syspll_divpmcck", "baudpll_divpmcck", }, 508 .pp_mux_table = { 5, 8, }, 509 .pp_count = 2, 510 .pp_chg_id = INT_MIN, }, 511 512 { .n = "flex1_gclk", 513 .id = 39, 514 .r = { .max = 200000000 }, 515 .pp = { "syspll_divpmcck", "baudpll_divpmcck", }, 516 .pp_mux_table = { 5, 8, }, 517 .pp_count = 2, 518 .pp_chg_id = INT_MIN, }, 519 520 { .n = "flex2_gclk", 521 .id = 40, 522 .r = { .max = 200000000 }, 523 .pp = { "syspll_divpmcck", "baudpll_divpmcck", }, 524 .pp_mux_table = { 5, 8, }, 525 .pp_count = 2, 526 .pp_chg_id = INT_MIN, }, 527 528 { .n = "flex3_gclk", 529 .id = 41, 530 .r = { .max = 200000000 }, 531 .pp = { "syspll_divpmcck", "baudpll_divpmcck", }, 532 .pp_mux_table = { 5, 8, }, 533 .pp_count = 2, 534 .pp_chg_id = INT_MIN, }, 535 536 { .n = "flex4_gclk", 537 .id = 42, 538 .r = { .max = 200000000 }, 539 .pp = { "syspll_divpmcck", "baudpll_divpmcck", }, 540 .pp_mux_table = { 5, 8, }, 541 .pp_count = 2, 542 .pp_chg_id = INT_MIN, }, 543 544 { .n = "flex5_gclk", 545 .id = 43, 546 .r = { .max = 200000000 }, 547 .pp = { "syspll_divpmcck", "baudpll_divpmcck", }, 548 .pp_mux_table = { 5, 8, }, 549 .pp_count = 2, 550 .pp_chg_id = INT_MIN, }, 551 552 { .n = "flex6_gclk", 553 .id = 44, 554 .r = { .max = 200000000 }, 555 .pp = { "syspll_divpmcck", "baudpll_divpmcck", }, 556 .pp_mux_table = { 5, 8, }, 557 .pp_count = 2, 558 .pp_chg_id = INT_MIN, }, 559 560 { .n = "flex7_gclk", 561 .id = 45, 562 .r = { .max = 200000000 }, 563 .pp = { "syspll_divpmcck", "baudpll_divpmcck", }, 564 .pp_mux_table = { 5, 8, }, 565 .pp_count = 2, 566 .pp_chg_id = INT_MIN, }, 567 568 { .n = "flex8_gclk", 569 .id = 46, 570 .r = { .max = 200000000 }, 571 .pp = { "syspll_divpmcck", "baudpll_divpmcck", }, 572 .pp_mux_table = { 5, 8, }, 573 .pp_count = 2, 574 .pp_chg_id = INT_MIN, }, 575 576 { .n = "flex9_gclk", 577 .id = 47, 578 .r = { .max = 200000000 }, 579 .pp = { "syspll_divpmcck", "baudpll_divpmcck", }, 580 .pp_mux_table = { 5, 8, }, 581 .pp_count = 2, 582 .pp_chg_id = INT_MIN, }, 583 584 { .n = "flex10_gclk", 585 .id = 48, 586 .r = { .max = 200000000 }, 587 .pp = { "syspll_divpmcck", "baudpll_divpmcck", }, 588 .pp_mux_table = { 5, 8, }, 589 .pp_count = 2, 590 .pp_chg_id = INT_MIN, }, 591 592 { .n = "flex11_gclk", 593 .id = 49, 594 .r = { .max = 200000000 }, 595 .pp = { "syspll_divpmcck", "baudpll_divpmcck", }, 596 .pp_mux_table = { 5, 8, }, 597 .pp_count = 2, 598 .pp_chg_id = INT_MIN, }, 599 600 { .n = "gmac0_gclk", 601 .id = 51, 602 .r = { .max = 125000000 }, 603 .pp = { "ethpll_divpmcck", }, 604 .pp_mux_table = { 10, }, 605 .pp_count = 1, 606 .pp_chg_id = 3, }, 607 608 { .n = "gmac1_gclk", 609 .id = 52, 610 .r = { .max = 50000000 }, 611 .pp = { "ethpll_divpmcck", }, 612 .pp_mux_table = { 10, }, 613 .pp_count = 1, 614 .pp_chg_id = INT_MIN, }, 615 616 { .n = "gmac0_tsu_gclk", 617 .id = 53, 618 .r = { .max = 300000000 }, 619 .pp = { "audiopll_divpmcck", "ethpll_divpmcck", }, 620 .pp_mux_table = { 9, 10, }, 621 .pp_count = 2, 622 .pp_chg_id = INT_MIN, }, 623 624 { .n = "gmac1_tsu_gclk", 625 .id = 54, 626 .r = { .max = 300000000 }, 627 .pp = { "audiopll_divpmcck", "ethpll_divpmcck", }, 628 .pp_mux_table = { 9, 10, }, 629 .pp_count = 2, 630 .pp_chg_id = INT_MIN, }, 631 632 { .n = "i2smcc0_gclk", 633 .id = 57, 634 .r = { .max = 100000000 }, 635 .pp = { "syspll_divpmcck", "audiopll_divpmcck", }, 636 .pp_mux_table = { 5, 9, }, 637 .pp_count = 2, 638 .pp_chg_id = 4, }, 639 640 { .n = "i2smcc1_gclk", 641 .id = 58, 642 .r = { .max = 100000000 }, 643 .pp = { "syspll_divpmcck", "audiopll_divpmcck", }, 644 .pp_mux_table = { 5, 9, }, 645 .pp_count = 2, 646 .pp_chg_id = 4, }, 647 648 { .n = "mcan0_gclk", 649 .id = 61, 650 .r = { .max = 200000000 }, 651 .pp = { "syspll_divpmcck", "baudpll_divpmcck", }, 652 .pp_mux_table = { 5, 8, }, 653 .pp_count = 2, 654 .pp_chg_id = INT_MIN, }, 655 656 { .n = "mcan1_gclk", 657 .id = 62, 658 .r = { .max = 200000000 }, 659 .pp = { "syspll_divpmcck", "baudpll_divpmcck", }, 660 .pp_mux_table = { 5, 8, }, 661 .pp_count = 2, 662 .pp_chg_id = INT_MIN, }, 663 664 { .n = "mcan2_gclk", 665 .id = 63, 666 .r = { .max = 200000000 }, 667 .pp = { "syspll_divpmcck", "baudpll_divpmcck", }, 668 .pp_mux_table = { 5, 8, }, 669 .pp_count = 2, 670 .pp_chg_id = INT_MIN, }, 671 672 { .n = "mcan3_gclk", 673 .id = 64, 674 .r = { .max = 200000000 }, 675 .pp = { "syspll_divpmcck", "baudpll_divpmcck", }, 676 .pp_mux_table = { 5, 8, }, 677 .pp_count = 2, 678 .pp_chg_id = INT_MIN, }, 679 680 { .n = "mcan4_gclk", 681 .id = 65, 682 .r = { .max = 200000000 }, 683 .pp = { "syspll_divpmcck", "baudpll_divpmcck", }, 684 .pp_mux_table = { 5, 8, }, 685 .pp_count = 2, 686 .pp_chg_id = INT_MIN, }, 687 688 { .n = "mcan5_gclk", 689 .id = 66, 690 .r = { .max = 200000000 }, 691 .pp = { "syspll_divpmcck", "baudpll_divpmcck", }, 692 .pp_mux_table = { 5, 8, }, 693 .pp_count = 2, 694 .pp_chg_id = INT_MIN, }, 695 696 { .n = "pdmc0_gclk", 697 .id = 68, 698 .r = { .max = 50000000 }, 699 .pp = { "syspll_divpmcck", "baudpll_divpmcck", }, 700 .pp_mux_table = { 5, 8, }, 701 .pp_count = 2, 702 .pp_chg_id = INT_MIN, }, 703 704 { .n = "pdmc1_gclk", 705 .id = 69, 706 .r = { .max = 50000000, }, 707 .pp = { "syspll_divpmcck", "baudpll_divpmcck", }, 708 .pp_mux_table = { 5, 8, }, 709 .pp_count = 2, 710 .pp_chg_id = INT_MIN, }, 711 712 { .n = "pit64b0_gclk", 713 .id = 70, 714 .r = { .max = 200000000 }, 715 .pp = { "syspll_divpmcck", "imgpll_divpmcck", "baudpll_divpmcck", 716 "audiopll_divpmcck", "ethpll_divpmcck", }, 717 .pp_mux_table = { 5, 7, 8, 9, 10, }, 718 .pp_count = 5, 719 .pp_chg_id = INT_MIN, }, 720 721 { .n = "pit64b1_gclk", 722 .id = 71, 723 .r = { .max = 200000000 }, 724 .pp = { "syspll_divpmcck", "imgpll_divpmcck", "baudpll_divpmcck", 725 "audiopll_divpmcck", "ethpll_divpmcck", }, 726 .pp_mux_table = { 5, 7, 8, 9, 10, }, 727 .pp_count = 5, 728 .pp_chg_id = INT_MIN, }, 729 730 { .n = "pit64b2_gclk", 731 .id = 72, 732 .r = { .max = 200000000 }, 733 .pp = { "syspll_divpmcck", "imgpll_divpmcck", "baudpll_divpmcck", 734 "audiopll_divpmcck", "ethpll_divpmcck", }, 735 .pp_mux_table = { 5, 7, 8, 9, 10, }, 736 .pp_count = 5, 737 .pp_chg_id = INT_MIN, }, 738 739 { .n = "pit64b3_gclk", 740 .id = 73, 741 .r = { .max = 200000000 }, 742 .pp = { "syspll_divpmcck", "imgpll_divpmcck", "baudpll_divpmcck", 743 "audiopll_divpmcck", "ethpll_divpmcck", }, 744 .pp_mux_table = { 5, 7, 8, 9, 10, }, 745 .pp_count = 5, 746 .pp_chg_id = INT_MIN, }, 747 748 { .n = "pit64b4_gclk", 749 .id = 74, 750 .r = { .max = 200000000 }, 751 .pp = { "syspll_divpmcck", "imgpll_divpmcck", "baudpll_divpmcck", 752 "audiopll_divpmcck", "ethpll_divpmcck", }, 753 .pp_mux_table = { 5, 7, 8, 9, 10, }, 754 .pp_count = 5, 755 .pp_chg_id = INT_MIN, }, 756 757 { .n = "pit64b5_gclk", 758 .id = 75, 759 .r = { .max = 200000000 }, 760 .pp = { "syspll_divpmcck", "imgpll_divpmcck", "baudpll_divpmcck", 761 "audiopll_divpmcck", "ethpll_divpmcck", }, 762 .pp_mux_table = { 5, 7, 8, 9, 10, }, 763 .pp_count = 5, 764 .pp_chg_id = INT_MIN, }, 765 766 { .n = "qspi0_gclk", 767 .id = 78, 768 .r = { .max = 200000000 }, 769 .pp = { "syspll_divpmcck", "baudpll_divpmcck", }, 770 .pp_mux_table = { 5, 8, }, 771 .pp_count = 2, 772 .pp_chg_id = INT_MIN, }, 773 774 { .n = "qspi1_gclk", 775 .id = 79, 776 .r = { .max = 200000000 }, 777 .pp = { "syspll_divpmcck", "baudpll_divpmcck", }, 778 .pp_mux_table = { 5, 8, }, 779 .pp_count = 2, 780 .pp_chg_id = INT_MIN, }, 781 782 { .n = "sdmmc0_gclk", 783 .id = 80, 784 .r = { .max = 208000000 }, 785 .pp = { "syspll_divpmcck", "baudpll_divpmcck", }, 786 .pp_mux_table = { 5, 8, }, 787 .pp_count = 2, 788 .pp_chg_id = 4, }, 789 790 { .n = "sdmmc1_gclk", 791 .id = 81, 792 .r = { .max = 208000000 }, 793 .pp = { "syspll_divpmcck", "baudpll_divpmcck", }, 794 .pp_mux_table = { 5, 8, }, 795 .pp_count = 2, 796 .pp_chg_id = 4, }, 797 798 { .n = "sdmmc2_gclk", 799 .id = 82, 800 .r = { .max = 208000000 }, 801 .pp = { "syspll_divpmcck", "baudpll_divpmcck", }, 802 .pp_mux_table = { 5, 8, }, 803 .pp_count = 2, 804 .pp_chg_id = 4, }, 805 806 { .n = "spdifrx_gclk", 807 .id = 84, 808 .r = { .max = 150000000 }, 809 .pp = { "syspll_divpmcck", "audiopll_divpmcck", }, 810 .pp_mux_table = { 5, 9, }, 811 .pp_count = 2, 812 .pp_chg_id = 4, }, 813 814 { .n = "spdiftx_gclk", 815 .id = 85, 816 .r = { .max = 25000000 }, 817 .pp = { "syspll_divpmcck", "audiopll_divpmcck", }, 818 .pp_mux_table = { 5, 9, }, 819 .pp_count = 2, 820 .pp_chg_id = 4, }, 821 822 { .n = "tcb0_ch0_gclk", 823 .id = 88, 824 .r = { .max = 200000000 }, 825 .pp = { "syspll_divpmcck", "imgpll_divpmcck", "baudpll_divpmcck", 826 "audiopll_divpmcck", "ethpll_divpmcck", }, 827 .pp_mux_table = { 5, 7, 8, 9, 10, }, 828 .pp_count = 5, 829 .pp_chg_id = INT_MIN, }, 830 831 { .n = "tcb1_ch0_gclk", 832 .id = 91, 833 .r = { .max = 200000000 }, 834 .pp = { "syspll_divpmcck", "imgpll_divpmcck", "baudpll_divpmcck", 835 "audiopll_divpmcck", "ethpll_divpmcck", }, 836 .pp_mux_table = { 5, 7, 8, 9, 10, }, 837 .pp_count = 5, 838 .pp_chg_id = INT_MIN, }, 839 840 { .n = "tcpca_gclk", 841 .id = 94, 842 .r = { .max = 32768, }, 843 .pp_chg_id = INT_MIN, }, 844 845 { .n = "tcpcb_gclk", 846 .id = 95, 847 .r = { .max = 32768, }, 848 .pp_chg_id = INT_MIN, }, 849 }; 850 851 /* MCK0 characteristics. */ 852 static const struct clk_master_characteristics mck0_characteristics = { 853 .output = { .min = 32768, .max = 200000000 }, 854 .divisors = { 1, 2, 4, 3, 5 }, 855 .have_div3_pres = 1, 856 }; 857 858 /* MCK0 layout. */ 859 static const struct clk_master_layout mck0_layout = { 860 .mask = 0x773, 861 .pres_shift = 4, 862 .offset = 0x28, 863 }; 864 865 /* Programmable clock layout. */ 866 static const struct clk_programmable_layout programmable_layout = { 867 .pres_mask = 0xff, 868 .pres_shift = 8, 869 .css_mask = 0x1f, 870 .have_slck_mck = 0, 871 .is_pres_direct = 1, 872 }; 873 874 /* Peripheral clock layout. */ 875 static const struct clk_pcr_layout sama7g5_pcr_layout = { 876 .offset = 0x88, 877 .cmd = BIT(31), 878 .gckcss_mask = GENMASK(12, 8), 879 .pid_mask = GENMASK(6, 0), 880 }; 881 882 static void __init sama7g5_pmc_setup(struct device_node *np) 883 { 884 const char *td_slck_name, *md_slck_name, *mainxtal_name; 885 struct pmc_data *sama7g5_pmc; 886 const char *parent_names[10]; 887 void **alloc_mem = NULL; 888 int alloc_mem_size = 0; 889 struct regmap *regmap; 890 struct clk_hw *hw; 891 bool bypass; 892 int i, j; 893 894 i = of_property_match_string(np, "clock-names", "td_slck"); 895 if (i < 0) 896 return; 897 898 td_slck_name = of_clk_get_parent_name(np, i); 899 900 i = of_property_match_string(np, "clock-names", "md_slck"); 901 if (i < 0) 902 return; 903 904 md_slck_name = of_clk_get_parent_name(np, i); 905 906 i = of_property_match_string(np, "clock-names", "main_xtal"); 907 if (i < 0) 908 return; 909 910 mainxtal_name = of_clk_get_parent_name(np, i); 911 912 regmap = device_node_to_regmap(np); 913 if (IS_ERR(regmap)) 914 return; 915 916 sama7g5_pmc = pmc_data_allocate(PMC_CPU + 1, 917 nck(sama7g5_systemck), 918 nck(sama7g5_periphck), 919 nck(sama7g5_gck), 8); 920 if (!sama7g5_pmc) 921 return; 922 923 alloc_mem = kmalloc(sizeof(void *) * 924 (ARRAY_SIZE(sama7g5_mckx) + ARRAY_SIZE(sama7g5_gck)), 925 GFP_KERNEL); 926 if (!alloc_mem) 927 goto err_free; 928 929 hw = at91_clk_register_main_rc_osc(regmap, "main_rc_osc", 12000000, 930 50000000); 931 if (IS_ERR(hw)) 932 goto err_free; 933 934 bypass = of_property_read_bool(np, "atmel,osc-bypass"); 935 936 hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name, 937 bypass); 938 if (IS_ERR(hw)) 939 goto err_free; 940 941 parent_names[0] = "main_rc_osc"; 942 parent_names[1] = "main_osc"; 943 hw = at91_clk_register_sam9x5_main(regmap, "mainck", parent_names, 2); 944 if (IS_ERR(hw)) 945 goto err_free; 946 947 sama7g5_pmc->chws[PMC_MAIN] = hw; 948 949 for (i = 0; i < PLL_ID_MAX; i++) { 950 for (j = 0; j < 3; j++) { 951 struct clk_hw *parent_hw; 952 953 if (!sama7g5_plls[i][j].n) 954 continue; 955 956 switch (sama7g5_plls[i][j].t) { 957 case PLL_TYPE_FRAC: 958 if (!strcmp(sama7g5_plls[i][j].p, "mainck")) 959 parent_hw = sama7g5_pmc->chws[PMC_MAIN]; 960 else 961 parent_hw = __clk_get_hw(of_clk_get_by_name(np, 962 sama7g5_plls[i][j].p)); 963 964 hw = sam9x60_clk_register_frac_pll(regmap, 965 &pmc_pll_lock, sama7g5_plls[i][j].n, 966 sama7g5_plls[i][j].p, parent_hw, i, 967 sama7g5_plls[i][j].c, 968 sama7g5_plls[i][j].l, 969 sama7g5_plls[i][j].f); 970 break; 971 972 case PLL_TYPE_DIV: 973 hw = sam9x60_clk_register_div_pll(regmap, 974 &pmc_pll_lock, sama7g5_plls[i][j].n, 975 sama7g5_plls[i][j].p, i, 976 sama7g5_plls[i][j].c, 977 sama7g5_plls[i][j].l, 978 sama7g5_plls[i][j].f, 979 sama7g5_plls[i][j].safe_div); 980 break; 981 982 default: 983 continue; 984 } 985 986 if (IS_ERR(hw)) 987 goto err_free; 988 989 if (sama7g5_plls[i][j].eid) 990 sama7g5_pmc->chws[sama7g5_plls[i][j].eid] = hw; 991 } 992 } 993 994 parent_names[0] = "cpupll_divpmcck"; 995 hw = at91_clk_register_master_div(regmap, "mck0", "cpupll_divpmcck", 996 &mck0_layout, &mck0_characteristics, 997 &pmc_mck0_lock, CLK_GET_RATE_NOCACHE, 5); 998 if (IS_ERR(hw)) 999 goto err_free; 1000 1001 sama7g5_pmc->chws[PMC_MCK] = hw; 1002 1003 parent_names[0] = md_slck_name; 1004 parent_names[1] = td_slck_name; 1005 parent_names[2] = "mainck"; 1006 for (i = 0; i < ARRAY_SIZE(sama7g5_mckx); i++) { 1007 u8 num_parents = 3 + sama7g5_mckx[i].ep_count; 1008 u32 *mux_table; 1009 1010 mux_table = kmalloc_array(num_parents, sizeof(*mux_table), 1011 GFP_KERNEL); 1012 if (!mux_table) 1013 goto err_free; 1014 1015 SAMA7G5_INIT_TABLE(mux_table, 3); 1016 SAMA7G5_FILL_TABLE(&mux_table[3], sama7g5_mckx[i].ep_mux_table, 1017 sama7g5_mckx[i].ep_count); 1018 SAMA7G5_FILL_TABLE(&parent_names[3], sama7g5_mckx[i].ep, 1019 sama7g5_mckx[i].ep_count); 1020 1021 hw = at91_clk_sama7g5_register_master(regmap, sama7g5_mckx[i].n, 1022 num_parents, parent_names, mux_table, 1023 &pmc_mckX_lock, sama7g5_mckx[i].id, 1024 sama7g5_mckx[i].c, 1025 sama7g5_mckx[i].ep_chg_id); 1026 if (IS_ERR(hw)) 1027 goto err_free; 1028 1029 alloc_mem[alloc_mem_size++] = mux_table; 1030 } 1031 1032 hw = at91_clk_sama7g5_register_utmi(regmap, "utmick", "main_xtal"); 1033 if (IS_ERR(hw)) 1034 goto err_free; 1035 1036 sama7g5_pmc->chws[PMC_UTMI] = hw; 1037 1038 parent_names[0] = md_slck_name; 1039 parent_names[1] = td_slck_name; 1040 parent_names[2] = "mainck"; 1041 parent_names[3] = "syspll_divpmcck"; 1042 parent_names[4] = "ddrpll_divpmcck"; 1043 parent_names[5] = "imgpll_divpmcck"; 1044 parent_names[6] = "baudpll_divpmcck"; 1045 parent_names[7] = "audiopll_divpmcck"; 1046 parent_names[8] = "ethpll_divpmcck"; 1047 for (i = 0; i < 8; i++) { 1048 char name[6]; 1049 1050 snprintf(name, sizeof(name), "prog%d", i); 1051 1052 hw = at91_clk_register_programmable(regmap, name, parent_names, 1053 9, i, 1054 &programmable_layout, 1055 sama7g5_prog_mux_table); 1056 if (IS_ERR(hw)) 1057 goto err_free; 1058 1059 sama7g5_pmc->pchws[i] = hw; 1060 } 1061 1062 for (i = 0; i < ARRAY_SIZE(sama7g5_systemck); i++) { 1063 hw = at91_clk_register_system(regmap, sama7g5_systemck[i].n, 1064 sama7g5_systemck[i].p, 1065 sama7g5_systemck[i].id); 1066 if (IS_ERR(hw)) 1067 goto err_free; 1068 1069 sama7g5_pmc->shws[sama7g5_systemck[i].id] = hw; 1070 } 1071 1072 for (i = 0; i < ARRAY_SIZE(sama7g5_periphck); i++) { 1073 hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock, 1074 &sama7g5_pcr_layout, 1075 sama7g5_periphck[i].n, 1076 sama7g5_periphck[i].p, 1077 sama7g5_periphck[i].id, 1078 &sama7g5_periphck[i].r, 1079 sama7g5_periphck[i].chgp ? 0 : 1080 INT_MIN); 1081 if (IS_ERR(hw)) 1082 goto err_free; 1083 1084 sama7g5_pmc->phws[sama7g5_periphck[i].id] = hw; 1085 } 1086 1087 parent_names[0] = md_slck_name; 1088 parent_names[1] = td_slck_name; 1089 parent_names[2] = "mainck"; 1090 for (i = 0; i < ARRAY_SIZE(sama7g5_gck); i++) { 1091 u8 num_parents = 3 + sama7g5_gck[i].pp_count; 1092 u32 *mux_table; 1093 1094 mux_table = kmalloc_array(num_parents, sizeof(*mux_table), 1095 GFP_KERNEL); 1096 if (!mux_table) 1097 goto err_free; 1098 1099 SAMA7G5_INIT_TABLE(mux_table, 3); 1100 SAMA7G5_FILL_TABLE(&mux_table[3], sama7g5_gck[i].pp_mux_table, 1101 sama7g5_gck[i].pp_count); 1102 SAMA7G5_FILL_TABLE(&parent_names[3], sama7g5_gck[i].pp, 1103 sama7g5_gck[i].pp_count); 1104 1105 hw = at91_clk_register_generated(regmap, &pmc_pcr_lock, 1106 &sama7g5_pcr_layout, 1107 sama7g5_gck[i].n, 1108 parent_names, mux_table, 1109 num_parents, 1110 sama7g5_gck[i].id, 1111 &sama7g5_gck[i].r, 1112 sama7g5_gck[i].pp_chg_id); 1113 if (IS_ERR(hw)) 1114 goto err_free; 1115 1116 sama7g5_pmc->ghws[sama7g5_gck[i].id] = hw; 1117 alloc_mem[alloc_mem_size++] = mux_table; 1118 } 1119 1120 of_clk_add_hw_provider(np, of_clk_hw_pmc_get, sama7g5_pmc); 1121 1122 return; 1123 1124 err_free: 1125 if (alloc_mem) { 1126 for (i = 0; i < alloc_mem_size; i++) 1127 kfree(alloc_mem[i]); 1128 kfree(alloc_mem); 1129 } 1130 1131 kfree(sama7g5_pmc); 1132 } 1133 1134 /* Some clks are used for a clocksource */ 1135 CLK_OF_DECLARE(sama7g5_pmc, "microchip,sama7g5-pmc", sama7g5_pmc_setup); 1136