Merge remote-tracking branch 'torvalds/master' into perf-tools

To pick up changes in other trees that may affect perf, such as libbpf
and in general the header files that perf has copies of, so that

Merge remote-tracking branch 'torvalds/master' into perf-tools

To pick up changes in other trees that may affect perf, such as libbpf
and in general the header files that perf has copies of, so that we can
do the sync with the kernel sources.

Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>

show more ...

Merge tag 'kvmarm-fixes-6.12-1' of git://git.kernel.org/pub/scm/linux/kernel/git/kvmarm/kvmarm into HEAD

KVM/arm64 fixes for 6.12, take #1

- Fix pKVM error path on init, making sure we do not chang

Merge tag 'kvmarm-fixes-6.12-1' of git://git.kernel.org/pub/scm/linux/kernel/git/kvmarm/kvmarm into HEAD

KVM/arm64 fixes for 6.12, take #1

- Fix pKVM error path on init, making sure we do not change critical
system registers as we're about to fail

- Make sure that the host's vector length is at capped by a value
common to all CPUs

- Fix kvm_has_feat*() handling of "negative" features, as the current
code is pretty broken

- Promote Joey to the status of official reviewer, while James steps
down -- hopefully only temporarly

show more ...

Merge tag 'asoc-fix-v6.12-rc1' of https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound into for-linus

ASoC: Fixes for v6.12

A bunch of fixes here that came in during the merge window and t

Merge tag 'asoc-fix-v6.12-rc1' of https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound into for-linus

ASoC: Fixes for v6.12

A bunch of fixes here that came in during the merge window and the first
week of release, plus some new quirks and device IDs. There's nothing
major here, it's a bit bigger than it might've been due to there being
no fixes sent during the merge window due to your vacation.

show more ...

Merge remote-tracking branch 'drm/drm-fixes' into drm-misc-fixes

Required for a panthor fix that broke when
FOP_UNSIGNED_OFFSET was added in place of FMODE_UNSIGNED_OFFSET.

Signed-off-by: Maarten L

Merge remote-tracking branch 'drm/drm-fixes' into drm-misc-fixes

Required for a panthor fix that broke when
FOP_UNSIGNED_OFFSET was added in place of FMODE_UNSIGNED_OFFSET.

Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>

show more ...

Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net

Cross-merge networking fixes after downstream PR.

No conflicts and no adjacent changes.

Signed-off-by: Paolo Abeni <pabeni@redhat.com>

Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk updates from Stephen Boyd:
"The core clk framework is left largely untouched this time around
except

Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk updates from Stephen Boyd:
"The core clk framework is left largely untouched this time around
except for support for the newly ratified DT property
'assigned-clock-rates-u64'.

I'm much more excited about the support for loading DT overlays from
KUnit tests so that we can test how the clk framework parses DT nodes
during clk registration. The clk framework has some places that are
highly DeviceTree dependent so this charts the path to extend the
KUnit tests to cover even more framework code in the future. I've got
some more tests on the list that use the DT overlay support, but they
uncovered issues with clk unregistration that I'm still working on
fixing.

Outside the core, the clk driver update pile is dominated by Qualcomm
and Renesas SoCs, making it fairly usual. Looking closer, there are
fixes for things all over the place, like adding missing clk
frequencies or moving defines for the number of clks out of DT binding
headers into the drivers. There are even conversions of DT bindings to
YAML and migration away from strings to describe clk topology. Overall
it doesn't look unusual so I expect the new drivers to be where we'll
have fixes in the coming weeks.

Core:
- KUnit tests for clk registration and fixed rate basic clk type
- A couple more devm helpers, one consumer and one provider
- Support for assigned-clock-rates-u64

New Drivers:
- Camera, display and GPU clocks on Qualcomm SM4450
- Camera clocks on Qualcomm SM8150
- Rockchip rk3576 clks
- Microchip SAM9X7 clks
- Renesas RZ/V2H(P) (R9A09G057) clks

Updates:
- Mark a bunch of struct freq_tbl const to reduce .data usage
- Add Qualcomm MSM8226 A7PLL and Regera PLL support
- Fix the Qualcomm Lucid 5LPE PLL configuration sequence to not reuse
Trion, as they do differ
- A number of fixes to the Qualcomm SM8550 display clock driver
- Fold Qualcomm SM8650 display clock driver into SM8550 one
- Add missing clocks and GDSCs needed for audio on Qualcomm MSM8998
- Add missing USB MP resets, GPLL9, and QUPv3 DFS to Qualcomm SC8180X
- Fix sdcc clk frequency tables on Qualcomm SC8180X
- Drop the Qualcomm SM8150 gcc_cpuss_ahb_clk_src
- Mark Qualcomm PCIe GDSCs as RET_ON on sm8250 and sm8540 to avoid
them turning off during suspend
- Use the HW_CTRL mechanism on Qualcomm SM8550 video clock controller
GDSCs
- Get rid of CLK_NR_CLKS defines in Rockchip DT binding headers
- Some fixes for Rockchip rk3228 and rk3588
- Exynos850: Add clock for Thermal Management Unit
- Exynos7885: Fix duplicated ID in the header, add missing TOP PLLs
and add clocks for USB block in the FSYS clock controller
- ExynosAutov9: Add DPUM clock controller
- ExynosAutov920: Add new (first) clock controllers: TOP and PERIC0
(and a bit more complete bindings)
- Use clk_hw pointer instead of fw_name for acm_aud_clk[0-1]_sel
clocks on i.MX8Q as parents in ACM provider
- Add i.MX95 NETCMIX support to the block control provider
- Fix parents for ENETx_REF_SEL clocks on i.MX6UL
- Add USB clocks, resets and power domains on Renesas RZ/G3S
- Add Generic Timer (GTM), I2C Bus Interface (RIIC), SD/MMC Host
Interface (SDHI) and Watchdog Timer (WDT) clocks and resets on
Renesas RZ/V2H
- Add PCIe, PWM, and CAN-FD clocks on Renesas R-Car V4M
- Add LCD controller clocks and resets on Renesas RZ/G2UL
- Add DMA clocks and resets on Renesas RZ/G3S
- Add fractional multiplication PLL support on Renesas R-Car Gen4
- Document support for the Renesas RZ/G2M v3.0 (r8a774a3) SoC
- Support for the Microchip SAM9X7 SoC as follows:
- Updates for the Microchip PLL drivers
- DT binding documentation updates (for the new clock driver and for
the slow clock controller that SAM9X7 is using)
- A fix for the Microchip SAMA7G5 clock driver to avoid allocating
more memory than necessary
- Constify some Amlogic structs
- Add SM1 eARC clocks for Amlogic
- Introduce a symbol namespace for Amlogic clock specific symbols
- Add reset controller support to audiomix block control on i.MX
- Add CLK_SET_RATE_PARENT flag to all audiomix clocks and to i.MX7D
lcdif_pixel_src clock
- Fix parent clocks for earc_phy and audpll on i.MX8MP
- Fix default parents for enet[12]_ref_sel on i.MX6UL
- Add ops in composite 8M and 93 that allow no-op on disable
- Add check for PCC present bit on composite 7ULP register
- Fix fractional part for fracn-gppll on prepare in i.MX
- Fix clock tree update for TF-A managed clocks on i.MX8M
- Drop CLK_SET_PARENT_GATE for DRAM mux on i.MX7D
- Add the SAI7 IPG clock for i.MX8MN
- Mark the 'nand_usdhc_bus' clock as non-critical on i.MX8MM
- Add LVDS bypass clocks on i.MX8QXP
- Add muxes for MIPI and PHY ref clocks on i.MX
- Reorder dc0_bypass0_clk, lcd_pxl and dc1_disp clocks on i.MX8QXP
- Add 1039.5MHz and 800MHz rates to fracn-gppll table on i.MX
- Add CLK_SET_RATE_PARENT for media_disp pixel clocks on i.MX8QXP
- Add some module descriptions to the i.MX generic and the i.MXRT1050
driver
- Fix return value for bypass for composite i.MX7ULP
- Move Mediatek clk bindings to clock/
- Convert some more clk bindings to dt schema"

* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (180 commits)
clk: Switch back to struct platform_driver::remove()
dt-bindings: clock, reset: fix top-comment indentation rk3576 headers
clk: rockchip: remove unused mclk_pdm0_p/pdm0_p definitions
clk: provide devm_clk_get_optional_enabled_with_rate()
clk: fixed-rate: add devm_clk_hw_register_fixed_rate_parent_data()
clk: imx6ul: fix clock parent for IMX6UL_CLK_ENETx_REF_SEL
clk: renesas: r9a09g057: Add clock and reset entries for GTM/RIIC/SDHI/WDT
clk: renesas: rzv2h: Add support for dynamic switching divider clocks
clk: renesas: r9a08g045: Add clocks, resets and power domains for USB
clk: rockchip: fix error for unknown clocks
clk: rockchip: rk3588: drop unused code
clk: rockchip: Add clock controller for the RK3576
clk: rockchip: Add new pll type pll_rk3588_ddr
dt-bindings: clock, reset: Add support for rk3576
dt-bindings: clock: rockchip,rk3588-cru: drop unneeded assigned-clocks
clk: rockchip: rk3588: Fix 32k clock name for pmu_24m_32k_100m_src_p
clk: imx95: enable the clock of NETCMIX block control
dt-bindings: clock: add RMII clock selection
dt-bindings: clock: add i.MX95 NETCMIX block control
clk: imx: imx8: Use clk_hw pointer for self registered clock in clk_parent_data
...

show more ...

Merge branches 'clk-amlogic', 'clk-microchip' and 'clk-imx' into clk-next

* clk-amlogic:
clk: meson: introduce symbol namespace for amlogic clocks
clk: meson: axg-audio: add sm1 earcrx clocks

Merge branches 'clk-amlogic', 'clk-microchip' and 'clk-imx' into clk-next

* clk-amlogic:
clk: meson: introduce symbol namespace for amlogic clocks
clk: meson: axg-audio: add sm1 earcrx clocks
clk: meson: axg-audio: setup regmap max_register based on the SoC
dt-bindings: clock: axg-audio: add earcrx clock ids
clk: meson: s4: pll: Constify struct regmap_config
clk: meson: s4: peripherals: Constify struct regmap_config
clk: meson: c3: pll: Constify struct regmap_config
clk: meson: c3: peripherals: Constify struct regmap_config
clk: meson: a1: pll: Constify struct regmap_config
clk: meson: a1: peripherals: Constify struct regmap_config

* clk-microchip:
clk: at91: sama7g5: Allocate only the needed amount of memory for PLLs
clk: at91: sam9x7: add sam9x7 pmc driver
dt-bindings: clock: at91: Allow PLLs to be exported and referenced in DT
clk: at91: sama7g5: move mux table macros to header file
clk: at91: sam9x7: add support for HW PLL freq dividers
clk: at91: clk-sam9x60-pll: re-factor to support individual core freq outputs
dt-bindings: clocks: atmel,at91rm9200-pmc: add sam9x7 clock controller
dt-bindings: clocks: atmel,at91sam9x5-sckc: add sam9x7

* clk-imx: (27 commits)
clk: imx6ul: fix clock parent for IMX6UL_CLK_ENETx_REF_SEL
clk: imx95: enable the clock of NETCMIX block control
dt-bindings: clock: add RMII clock selection
dt-bindings: clock: add i.MX95 NETCMIX block control
clk: imx: imx8: Use clk_hw pointer for self registered clock in clk_parent_data
clk: imx: composite-7ulp: Use NULL instead of 0
clk: imx: add missing MODULE_DESCRIPTION() macros
clk: imx: clk-imx8mp: Allow media_disp pixel clock reconfigure parent rate
clk: imx: fracn-gppll: update rate table
clk: imx: imx8qxp: Parent should be initialized earlier than the clock
clk: imx: imx8qxp: Register dc0_bypass0_clk before disp clk
clk: imx: imx8qxp: Add clock muxes for MIPI and PHY ref clocks
clk: imx: imx8qxp: Add LVDS bypass clocks
clk: imx: imx8mm: Change the 'nand_usdhc_bus' clock to non-critical one
clk: imx: imx8mn: add sai7_ipg_clk clock settings
clk: imx: add CLK_SET_RATE_PARENT for lcdif_pixel_src for i.MX7D
clk: imx: Remove CLK_SET_PARENT_GATE for DRAM mux for i.MX7D
clk: imx: imx8mp: fix clock tree update of TF-A managed clocks
clk: imx: fracn-gppll: fix fractional part of PLL getting lost
clk: imx: composite-7ulp: Check the PCC present bit
...

show more ...

Merge tag 'clk-microchip-6.12' of https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into clk-microchip

Pull Microchip clk driver updates from Claudiu Beznea:

- support for the Microchip S

Merge tag 'clk-microchip-6.12' of https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into clk-microchip

Pull Microchip clk driver updates from Claudiu Beznea:

- support for the Microchip SAM9X7 SoC as follows:
- updates on the PLL drivers
- a new clock driver was added for SAM9X7
- dt-binding documentation updates (for the new clock driver and for
the slow clock controller that SAM9X7 is using)
- a fix for the Microchip SAMA7G5 clock driver to avoid allocating mode
than necessary memory

* tag 'clk-microchip-6.12' of https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux:
clk: at91: sama7g5: Allocate only the needed amount of memory for PLLs
clk: at91: sam9x7: add sam9x7 pmc driver
dt-bindings: clock: at91: Allow PLLs to be exported and referenced in DT
clk: at91: sama7g5: move mux table macros to header file
clk: at91: sam9x7: add support for HW PLL freq dividers
clk: at91: clk-sam9x60-pll: re-factor to support individual core freq outputs
dt-bindings: clocks: atmel,at91rm9200-pmc: add sam9x7 clock controller
dt-bindings: clocks: atmel,at91sam9x5-sckc: add sam9x7

show more ...

clk: at91: sama7g5: Allocate only the needed amount of memory for PLLs

The maximum number of PLL components on SAMA7G5 is 3 (one fractional
part and 2 dividers). Allocate the needed amount of memory

clk: at91: sama7g5: Allocate only the needed amount of memory for PLLs

The maximum number of PLL components on SAMA7G5 is 3 (one fractional
part and 2 dividers). Allocate the needed amount of memory for
sama7g5_plls 2d array. Previous code used to allocate 7 array entries for
each PLL. While at it, replace 3 with PLL_COMPID_MAX in the loop which
parses the sama7g5_plls 2d array.

Fixes: cb783bbbcf54 ("clk: at91: sama7g5: add clock support for sama7g5")
Acked-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lore.kernel.org/r/20240714141315.19480-1-claudiu.beznea@tuxon.dev
Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>

show more ...

clk: at91: sama7g5: move mux table macros to header file

Move the mux table init and fill macro function definitions from the
sama7g5 pmc driver to the pmc.h header file since they will be used
by o

clk: at91: sama7g5: move mux table macros to header file

Move the mux table init and fill macro function definitions from the
sama7g5 pmc driver to the pmc.h header file since they will be used
by other SoC's pmc drivers as well like sam9x7.

Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
Link: https://lore.kernel.org/r/20240729070753.1990866-1-varshini.rajendran@microchip.com
Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>

show more ...

clk: at91: clk-sam9x60-pll: re-factor to support individual core freq outputs

SAM9X7 SoC family supports different core output frequencies for
different PLL IDs. To handle the same in the PLL driver

clk: at91: clk-sam9x60-pll: re-factor to support individual core freq outputs

SAM9X7 SoC family supports different core output frequencies for
different PLL IDs. To handle the same in the PLL driver, a separate
parameter core_output is added. The sam9x60 and sama7g5 SoC PMC drivers
are aligned to the PLL driver by adding the core output freq range in
the PLL characteristics configurations.

Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
Link: https://lore.kernel.org/r/20240729070737.1990756-1-varshini.rajendran@microchip.com
Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>

show more ...

Merge branch 'next' into for-linus

Prepare input updates for 6.7 merge window.

Merge tag 'v6.5' into next

Sync up with mainline to bring in updates to the shared infrastructure.

Merge drm/drm-next into drm-intel-next

Catching-up with drm-next and drm-intel-gt-next.
It will unblock a code refactor around the platform
definitions (names vs acronyms).

Signed-off-by: Rodrigo V

Merge drm/drm-next into drm-intel-next

Catching-up with drm-next and drm-intel-gt-next.
It will unblock a code refactor around the platform
definitions (names vs acronyms).

Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

show more ...

Merge drm/drm-next into drm-intel-gt-next

Need to pull in b3e4aae612ec ("drm/i915/hdcp: Modify hdcp_gsc_message msg sending mechanism") as
a dependency for https://patchwork.freedesktop.org/series/1

Merge drm/drm-next into drm-intel-gt-next

Need to pull in b3e4aae612ec ("drm/i915/hdcp: Modify hdcp_gsc_message msg sending mechanism") as
a dependency for https://patchwork.freedesktop.org/series/121735/

Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>

show more ...

Merge drm/drm-next into drm-misc-next

Backmerging to get v6.5-rc2.

Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de>

ASoC: Merge v6.5-rc2

Get a similar baseline to my other branches, and fixes for people using
the branch.

Merge v6.5-rc1 into drm-misc-fixes

Boris needs 6.5-rc1 in drm-misc-fixes to prevent a conflict.

Signed-off-by: Maxime Ripard <mripard@kernel.org>

Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull more clk updates from Stephen Boyd:
"Another set of clk driver updates and fixes for the merge window. The

Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull more clk updates from Stephen Boyd:
"Another set of clk driver updates and fixes for the merge window. The
driver updates needed more time to bake in linux-next.

Updates:
- Support for more clk controllers in Qualcomm SoCs such as SM8350,
SM8450, SDX75, SC8280XP, and IPQ9574
- Runtime PM enablement of some more Qualcomm clk controllers
- Various fixes to Qualcomm clk driver data to use correct clk_ops
and to check halt bits properly
- AT91 updates to modernize with clk_parent_data structures

Fixes:
- Remove 'syscon' from dt binding fix for ti,j721e-system-controller
- Fix determine rate in the Tegra driver that got wrecked by the
refactorting of muxes this merge window"

* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (69 commits)
clk: tegra: Avoid calling an uninitialized function
dt-bindings: mfd: ti,j721e-system-controller: Remove syscon from example
clk: at91: sama7g5: s/ep_chg_chg_id/ep_chg_id
clk: at91: sama7g5: switch to parent_hw and parent_data
clk: at91: sckc: switch to parent_data/parent_hw
clk: at91: clk-sam9x60-pll: add support for parent_hw
clk: at91: clk-utmi: add support for parent_hw
clk: at91: clk-system: add support for parent_hw
clk: at91: clk-programmable: add support for parent_hw
clk: at91: clk-peripheral: add support for parent_hw
clk: at91: clk-master: add support for parent_hw
clk: at91: clk-generated: add support for parent_hw
clk: at91: clk-main: add support for parent_data/parent_hw
clk: qcom: gcc-sc8280xp: Add runtime PM
clk: qcom: gpucc-sc8280xp: Add runtime PM
clk: qcom: mmcc-msm8974: fix MDSS_GDSC power flags
clk: qcom: gpucc-sm6375: Enable runtime pm
dt-bindings: clock: sm6375-gpucc: Add VDD_GX
clk: qcom: gcc-sm6115: Add missing PLL config properties
clk: qcom: clk-alpha-pll: Add a way to update some bits of test_ctl(_hi)
...

show more ...

Merge branches 'clk-qcom' and 'clk-microchip' into clk-next

* clk-qcom: (63 commits)
clk: qcom: gcc-sc8280xp: Add runtime PM
clk: qcom: gpucc-sc8280xp: Add runtime PM
clk: qcom: mmcc-msm8974:

Merge branches 'clk-qcom' and 'clk-microchip' into clk-next

* clk-qcom: (63 commits)
clk: qcom: gcc-sc8280xp: Add runtime PM
clk: qcom: gpucc-sc8280xp: Add runtime PM
clk: qcom: mmcc-msm8974: fix MDSS_GDSC power flags
clk: qcom: gpucc-sm6375: Enable runtime pm
dt-bindings: clock: sm6375-gpucc: Add VDD_GX
clk: qcom: gcc-sm6115: Add missing PLL config properties
clk: qcom: clk-alpha-pll: Add a way to update some bits of test_ctl(_hi)
clk: qcom: gcc-ipq6018: remove duplicate initializers
clk: qcom: gcc-ipq9574: Enable crypto clocks
dt-bindings: clock: Add crypto clock and reset definitions
clk: qcom: Add lpass audio clock controller driver for SC8280XP
clk: qcom: Add lpass clock controller driver for SC8280XP
dt-bindings: clock: Add LPASS AUDIOCC and reset controller for SC8280XP
dt-bindings: clock: Add LPASSCC and reset controller for SC8280XP
dt-bindings: clock: qcom,mmcc: define clocks/clock-names for MSM8226
clk: qcom: gpucc-sm8550: Add support for graphics clock controller
clk: qcom: Add support for SM8450 GPUCC
clk: qcom: gcc-sm8450: Enable hw_clk_ctrl
clk: qcom: rcg2: Make hw_clk_ctrl toggleable
dt-bindings: clock: qcom: Add SM8550 graphics clock controller
...

* clk-microchip:
clk: at91: sama7g5: s/ep_chg_chg_id/ep_chg_id
clk: at91: sama7g5: switch to parent_hw and parent_data
clk: at91: sckc: switch to parent_data/parent_hw
clk: at91: clk-sam9x60-pll: add support for parent_hw
clk: at91: clk-utmi: add support for parent_hw
clk: at91: clk-system: add support for parent_hw
clk: at91: clk-programmable: add support for parent_hw
clk: at91: clk-peripheral: add support for parent_hw
clk: at91: clk-master: add support for parent_hw
clk: at91: clk-generated: add support for parent_hw
clk: at91: clk-main: add support for parent_data/parent_hw

show more ...

Merge tag 'clk-microchip-6.5-2' of https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into clk-microchip

Pull Microchip clk driver updates from Claudiu Beznea:

It contains support for paren

Merge tag 'clk-microchip-6.5-2' of https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into clk-microchip

Pull Microchip clk driver updates from Claudiu Beznea:

It contains support for parent_data, parent_hw in AT91 clock drivers
used by SAMA7G5 SoC (e.g. main, master, generic, peripheral, programmable,
system, utmi, slow clocks) and also the update of SAMA7G5 to use
this new support.

* tag 'clk-microchip-6.5-2' of https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux:
clk: at91: sama7g5: s/ep_chg_chg_id/ep_chg_id
clk: at91: sama7g5: switch to parent_hw and parent_data
clk: at91: sckc: switch to parent_data/parent_hw
clk: at91: clk-sam9x60-pll: add support for parent_hw
clk: at91: clk-utmi: add support for parent_hw
clk: at91: clk-system: add support for parent_hw
clk: at91: clk-programmable: add support for parent_hw
clk: at91: clk-peripheral: add support for parent_hw
clk: at91: clk-master: add support for parent_hw
clk: at91: clk-generated: add support for parent_hw
clk: at91: clk-main: add support for parent_data/parent_hw

show more ...

clk: at91: sama7g5: s/ep_chg_chg_id/ep_chg_id

s/ep_chg_chg_id/ep_chg_id in documentation of master clock structure.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Reviewed-by: Maxime

clk: at91: sama7g5: s/ep_chg_chg_id/ep_chg_id

s/ep_chg_chg_id/ep_chg_id in documentation of master clock structure.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Reviewed-by: Maxime Ripard <mripard@kernel.org>
Link: https://lore.kernel.org/r/20230615093227.576102-12-claudiu.beznea@microchip.com

show more ...

clk: at91: sama7g5: switch to parent_hw and parent_data

Switch SAMA7G5 clocks to use parent_hw and parent_data. Having
parent_hw instead of parent names improves to clock registration
speed and re-p

clk: at91: sama7g5: switch to parent_hw and parent_data

Switch SAMA7G5 clocks to use parent_hw and parent_data. Having
parent_hw instead of parent names improves to clock registration
speed and re-parenting. Extra time saved on registration is
~250us when running at 800MHz.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Reviewed-by: Maxime Ripard <mripard@kernel.org>
Link: https://lore.kernel.org/r/20230615093227.576102-11-claudiu.beznea@microchip.com

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clk: at91: clk-sam9x60-pll: add support for parent_hw

Add support for parent_hw in SAM9X60 PLL clock drivers.
With this parent-child relation is described with pointers rather
than strings making re

clk: at91: clk-sam9x60-pll: add support for parent_hw

Add support for parent_hw in SAM9X60 PLL clock drivers.
With this parent-child relation is described with pointers rather
than strings making registration a bit faster.

All the SoC based drivers that rely on clk-sam9x60-pll were adapted
to the new API change. The switch itself for SoCs will be done
in subsequent patches.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Reviewed-by: Maxime Ripard <mripard@kernel.org>
Link: https://lore.kernel.org/r/20230615093227.576102-9-claudiu.beznea@microchip.com

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clk: at91: clk-utmi: add support for parent_hw

Add support for parent_hw in utmi clock drivers.
With this parent-child relation is described with pointers rather
than strings making registration a b

clk: at91: clk-utmi: add support for parent_hw

Add support for parent_hw in utmi clock drivers.
With this parent-child relation is described with pointers rather
than strings making registration a bit faster.

All the SoC based drivers that rely on clk-utmi were adapted
to the new API change. The switch itself for SoCs will be done
in subsequent patches.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Reviewed-by: Maxime Ripard <mripard@kernel.org>
Link: https://lore.kernel.org/r/20230615093227.576102-8-claudiu.beznea@microchip.com

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