1 /* 2 * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com> 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 * 9 */ 10 11 #include <linux/clk-provider.h> 12 #include <linux/clkdev.h> 13 #include <linux/clk/at91_pmc.h> 14 #include <linux/delay.h> 15 #include <linux/of.h> 16 #include <linux/of_address.h> 17 #include <linux/of_irq.h> 18 #include <linux/io.h> 19 #include <linux/interrupt.h> 20 #include <linux/irq.h> 21 #include <linux/sched.h> 22 #include <linux/wait.h> 23 24 #include "pmc.h" 25 26 #define SLOW_CLOCK_FREQ 32768 27 #define MAINF_DIV 16 28 #define MAINFRDY_TIMEOUT (((MAINF_DIV + 1) * USEC_PER_SEC) / \ 29 SLOW_CLOCK_FREQ) 30 #define MAINF_LOOP_MIN_WAIT (USEC_PER_SEC / SLOW_CLOCK_FREQ) 31 #define MAINF_LOOP_MAX_WAIT MAINFRDY_TIMEOUT 32 33 #define MOR_KEY_MASK (0xff << 16) 34 35 struct clk_main_osc { 36 struct clk_hw hw; 37 struct at91_pmc *pmc; 38 unsigned int irq; 39 wait_queue_head_t wait; 40 }; 41 42 #define to_clk_main_osc(hw) container_of(hw, struct clk_main_osc, hw) 43 44 struct clk_main_rc_osc { 45 struct clk_hw hw; 46 struct at91_pmc *pmc; 47 unsigned int irq; 48 wait_queue_head_t wait; 49 unsigned long frequency; 50 unsigned long accuracy; 51 }; 52 53 #define to_clk_main_rc_osc(hw) container_of(hw, struct clk_main_rc_osc, hw) 54 55 struct clk_rm9200_main { 56 struct clk_hw hw; 57 struct at91_pmc *pmc; 58 }; 59 60 #define to_clk_rm9200_main(hw) container_of(hw, struct clk_rm9200_main, hw) 61 62 struct clk_sam9x5_main { 63 struct clk_hw hw; 64 struct at91_pmc *pmc; 65 unsigned int irq; 66 wait_queue_head_t wait; 67 u8 parent; 68 }; 69 70 #define to_clk_sam9x5_main(hw) container_of(hw, struct clk_sam9x5_main, hw) 71 72 static irqreturn_t clk_main_osc_irq_handler(int irq, void *dev_id) 73 { 74 struct clk_main_osc *osc = dev_id; 75 76 wake_up(&osc->wait); 77 disable_irq_nosync(osc->irq); 78 79 return IRQ_HANDLED; 80 } 81 82 static int clk_main_osc_prepare(struct clk_hw *hw) 83 { 84 struct clk_main_osc *osc = to_clk_main_osc(hw); 85 struct at91_pmc *pmc = osc->pmc; 86 u32 tmp; 87 88 tmp = pmc_read(pmc, AT91_CKGR_MOR) & ~MOR_KEY_MASK; 89 if (tmp & AT91_PMC_OSCBYPASS) 90 return 0; 91 92 if (!(tmp & AT91_PMC_MOSCEN)) { 93 tmp |= AT91_PMC_MOSCEN | AT91_PMC_KEY; 94 pmc_write(pmc, AT91_CKGR_MOR, tmp); 95 } 96 97 while (!(pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_MOSCS)) { 98 enable_irq(osc->irq); 99 wait_event(osc->wait, 100 pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_MOSCS); 101 } 102 103 return 0; 104 } 105 106 static void clk_main_osc_unprepare(struct clk_hw *hw) 107 { 108 struct clk_main_osc *osc = to_clk_main_osc(hw); 109 struct at91_pmc *pmc = osc->pmc; 110 u32 tmp = pmc_read(pmc, AT91_CKGR_MOR); 111 112 if (tmp & AT91_PMC_OSCBYPASS) 113 return; 114 115 if (!(tmp & AT91_PMC_MOSCEN)) 116 return; 117 118 tmp &= ~(AT91_PMC_KEY | AT91_PMC_MOSCEN); 119 pmc_write(pmc, AT91_CKGR_MOR, tmp | AT91_PMC_KEY); 120 } 121 122 static int clk_main_osc_is_prepared(struct clk_hw *hw) 123 { 124 struct clk_main_osc *osc = to_clk_main_osc(hw); 125 struct at91_pmc *pmc = osc->pmc; 126 u32 tmp = pmc_read(pmc, AT91_CKGR_MOR); 127 128 if (tmp & AT91_PMC_OSCBYPASS) 129 return 1; 130 131 return !!((pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_MOSCS) && 132 (pmc_read(pmc, AT91_CKGR_MOR) & AT91_PMC_MOSCEN)); 133 } 134 135 static const struct clk_ops main_osc_ops = { 136 .prepare = clk_main_osc_prepare, 137 .unprepare = clk_main_osc_unprepare, 138 .is_prepared = clk_main_osc_is_prepared, 139 }; 140 141 static struct clk * __init 142 at91_clk_register_main_osc(struct at91_pmc *pmc, 143 unsigned int irq, 144 const char *name, 145 const char *parent_name, 146 bool bypass) 147 { 148 int ret; 149 struct clk_main_osc *osc; 150 struct clk *clk = NULL; 151 struct clk_init_data init; 152 153 if (!pmc || !irq || !name || !parent_name) 154 return ERR_PTR(-EINVAL); 155 156 osc = kzalloc(sizeof(*osc), GFP_KERNEL); 157 if (!osc) 158 return ERR_PTR(-ENOMEM); 159 160 init.name = name; 161 init.ops = &main_osc_ops; 162 init.parent_names = &parent_name; 163 init.num_parents = 1; 164 init.flags = CLK_IGNORE_UNUSED; 165 166 osc->hw.init = &init; 167 osc->pmc = pmc; 168 osc->irq = irq; 169 170 init_waitqueue_head(&osc->wait); 171 irq_set_status_flags(osc->irq, IRQ_NOAUTOEN); 172 ret = request_irq(osc->irq, clk_main_osc_irq_handler, 173 IRQF_TRIGGER_HIGH, name, osc); 174 if (ret) { 175 kfree(osc); 176 return ERR_PTR(ret); 177 } 178 179 if (bypass) 180 pmc_write(pmc, AT91_CKGR_MOR, 181 (pmc_read(pmc, AT91_CKGR_MOR) & 182 ~(MOR_KEY_MASK | AT91_PMC_MOSCEN)) | 183 AT91_PMC_OSCBYPASS | AT91_PMC_KEY); 184 185 clk = clk_register(NULL, &osc->hw); 186 if (IS_ERR(clk)) { 187 free_irq(irq, osc); 188 kfree(osc); 189 } 190 191 return clk; 192 } 193 194 void __init of_at91rm9200_clk_main_osc_setup(struct device_node *np, 195 struct at91_pmc *pmc) 196 { 197 struct clk *clk; 198 unsigned int irq; 199 const char *name = np->name; 200 const char *parent_name; 201 bool bypass; 202 203 of_property_read_string(np, "clock-output-names", &name); 204 bypass = of_property_read_bool(np, "atmel,osc-bypass"); 205 parent_name = of_clk_get_parent_name(np, 0); 206 207 irq = irq_of_parse_and_map(np, 0); 208 if (!irq) 209 return; 210 211 clk = at91_clk_register_main_osc(pmc, irq, name, parent_name, bypass); 212 if (IS_ERR(clk)) 213 return; 214 215 of_clk_add_provider(np, of_clk_src_simple_get, clk); 216 } 217 218 static irqreturn_t clk_main_rc_osc_irq_handler(int irq, void *dev_id) 219 { 220 struct clk_main_rc_osc *osc = dev_id; 221 222 wake_up(&osc->wait); 223 disable_irq_nosync(osc->irq); 224 225 return IRQ_HANDLED; 226 } 227 228 static int clk_main_rc_osc_prepare(struct clk_hw *hw) 229 { 230 struct clk_main_rc_osc *osc = to_clk_main_rc_osc(hw); 231 struct at91_pmc *pmc = osc->pmc; 232 u32 tmp; 233 234 tmp = pmc_read(pmc, AT91_CKGR_MOR) & ~MOR_KEY_MASK; 235 236 if (!(tmp & AT91_PMC_MOSCRCEN)) { 237 tmp |= AT91_PMC_MOSCRCEN | AT91_PMC_KEY; 238 pmc_write(pmc, AT91_CKGR_MOR, tmp); 239 } 240 241 while (!(pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_MOSCRCS)) { 242 enable_irq(osc->irq); 243 wait_event(osc->wait, 244 pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_MOSCRCS); 245 } 246 247 return 0; 248 } 249 250 static void clk_main_rc_osc_unprepare(struct clk_hw *hw) 251 { 252 struct clk_main_rc_osc *osc = to_clk_main_rc_osc(hw); 253 struct at91_pmc *pmc = osc->pmc; 254 u32 tmp = pmc_read(pmc, AT91_CKGR_MOR); 255 256 if (!(tmp & AT91_PMC_MOSCRCEN)) 257 return; 258 259 tmp &= ~(MOR_KEY_MASK | AT91_PMC_MOSCRCEN); 260 pmc_write(pmc, AT91_CKGR_MOR, tmp | AT91_PMC_KEY); 261 } 262 263 static int clk_main_rc_osc_is_prepared(struct clk_hw *hw) 264 { 265 struct clk_main_rc_osc *osc = to_clk_main_rc_osc(hw); 266 struct at91_pmc *pmc = osc->pmc; 267 268 return !!((pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_MOSCRCS) && 269 (pmc_read(pmc, AT91_CKGR_MOR) & AT91_PMC_MOSCRCEN)); 270 } 271 272 static unsigned long clk_main_rc_osc_recalc_rate(struct clk_hw *hw, 273 unsigned long parent_rate) 274 { 275 struct clk_main_rc_osc *osc = to_clk_main_rc_osc(hw); 276 277 return osc->frequency; 278 } 279 280 static unsigned long clk_main_rc_osc_recalc_accuracy(struct clk_hw *hw, 281 unsigned long parent_acc) 282 { 283 struct clk_main_rc_osc *osc = to_clk_main_rc_osc(hw); 284 285 return osc->accuracy; 286 } 287 288 static const struct clk_ops main_rc_osc_ops = { 289 .prepare = clk_main_rc_osc_prepare, 290 .unprepare = clk_main_rc_osc_unprepare, 291 .is_prepared = clk_main_rc_osc_is_prepared, 292 .recalc_rate = clk_main_rc_osc_recalc_rate, 293 .recalc_accuracy = clk_main_rc_osc_recalc_accuracy, 294 }; 295 296 static struct clk * __init 297 at91_clk_register_main_rc_osc(struct at91_pmc *pmc, 298 unsigned int irq, 299 const char *name, 300 u32 frequency, u32 accuracy) 301 { 302 int ret; 303 struct clk_main_rc_osc *osc; 304 struct clk *clk = NULL; 305 struct clk_init_data init; 306 307 if (!pmc || !irq || !name || !frequency) 308 return ERR_PTR(-EINVAL); 309 310 osc = kzalloc(sizeof(*osc), GFP_KERNEL); 311 if (!osc) 312 return ERR_PTR(-ENOMEM); 313 314 init.name = name; 315 init.ops = &main_rc_osc_ops; 316 init.parent_names = NULL; 317 init.num_parents = 0; 318 init.flags = CLK_IS_ROOT | CLK_IGNORE_UNUSED; 319 320 osc->hw.init = &init; 321 osc->pmc = pmc; 322 osc->irq = irq; 323 osc->frequency = frequency; 324 osc->accuracy = accuracy; 325 326 init_waitqueue_head(&osc->wait); 327 irq_set_status_flags(osc->irq, IRQ_NOAUTOEN); 328 ret = request_irq(osc->irq, clk_main_rc_osc_irq_handler, 329 IRQF_TRIGGER_HIGH, name, osc); 330 if (ret) 331 return ERR_PTR(ret); 332 333 clk = clk_register(NULL, &osc->hw); 334 if (IS_ERR(clk)) { 335 free_irq(irq, osc); 336 kfree(osc); 337 } 338 339 return clk; 340 } 341 342 void __init of_at91sam9x5_clk_main_rc_osc_setup(struct device_node *np, 343 struct at91_pmc *pmc) 344 { 345 struct clk *clk; 346 unsigned int irq; 347 u32 frequency = 0; 348 u32 accuracy = 0; 349 const char *name = np->name; 350 351 of_property_read_string(np, "clock-output-names", &name); 352 of_property_read_u32(np, "clock-frequency", &frequency); 353 of_property_read_u32(np, "clock-accuracy", &accuracy); 354 355 irq = irq_of_parse_and_map(np, 0); 356 if (!irq) 357 return; 358 359 clk = at91_clk_register_main_rc_osc(pmc, irq, name, frequency, 360 accuracy); 361 if (IS_ERR(clk)) 362 return; 363 364 of_clk_add_provider(np, of_clk_src_simple_get, clk); 365 } 366 367 368 static int clk_main_probe_frequency(struct at91_pmc *pmc) 369 { 370 unsigned long prep_time, timeout; 371 u32 tmp; 372 373 timeout = jiffies + usecs_to_jiffies(MAINFRDY_TIMEOUT); 374 do { 375 prep_time = jiffies; 376 tmp = pmc_read(pmc, AT91_CKGR_MCFR); 377 if (tmp & AT91_PMC_MAINRDY) 378 return 0; 379 usleep_range(MAINF_LOOP_MIN_WAIT, MAINF_LOOP_MAX_WAIT); 380 } while (time_before(prep_time, timeout)); 381 382 return -ETIMEDOUT; 383 } 384 385 static unsigned long clk_main_recalc_rate(struct at91_pmc *pmc, 386 unsigned long parent_rate) 387 { 388 u32 tmp; 389 390 if (parent_rate) 391 return parent_rate; 392 393 pr_warn("Main crystal frequency not set, using approximate value\n"); 394 tmp = pmc_read(pmc, AT91_CKGR_MCFR); 395 if (!(tmp & AT91_PMC_MAINRDY)) 396 return 0; 397 398 return ((tmp & AT91_PMC_MAINF) * SLOW_CLOCK_FREQ) / MAINF_DIV; 399 } 400 401 static int clk_rm9200_main_prepare(struct clk_hw *hw) 402 { 403 struct clk_rm9200_main *clkmain = to_clk_rm9200_main(hw); 404 405 return clk_main_probe_frequency(clkmain->pmc); 406 } 407 408 static int clk_rm9200_main_is_prepared(struct clk_hw *hw) 409 { 410 struct clk_rm9200_main *clkmain = to_clk_rm9200_main(hw); 411 412 return !!(pmc_read(clkmain->pmc, AT91_CKGR_MCFR) & AT91_PMC_MAINRDY); 413 } 414 415 static unsigned long clk_rm9200_main_recalc_rate(struct clk_hw *hw, 416 unsigned long parent_rate) 417 { 418 struct clk_rm9200_main *clkmain = to_clk_rm9200_main(hw); 419 420 return clk_main_recalc_rate(clkmain->pmc, parent_rate); 421 } 422 423 static const struct clk_ops rm9200_main_ops = { 424 .prepare = clk_rm9200_main_prepare, 425 .is_prepared = clk_rm9200_main_is_prepared, 426 .recalc_rate = clk_rm9200_main_recalc_rate, 427 }; 428 429 static struct clk * __init 430 at91_clk_register_rm9200_main(struct at91_pmc *pmc, 431 const char *name, 432 const char *parent_name) 433 { 434 struct clk_rm9200_main *clkmain; 435 struct clk *clk = NULL; 436 struct clk_init_data init; 437 438 if (!pmc || !name) 439 return ERR_PTR(-EINVAL); 440 441 if (!parent_name) 442 return ERR_PTR(-EINVAL); 443 444 clkmain = kzalloc(sizeof(*clkmain), GFP_KERNEL); 445 if (!clkmain) 446 return ERR_PTR(-ENOMEM); 447 448 init.name = name; 449 init.ops = &rm9200_main_ops; 450 init.parent_names = &parent_name; 451 init.num_parents = 1; 452 init.flags = 0; 453 454 clkmain->hw.init = &init; 455 clkmain->pmc = pmc; 456 457 clk = clk_register(NULL, &clkmain->hw); 458 if (IS_ERR(clk)) 459 kfree(clkmain); 460 461 return clk; 462 } 463 464 void __init of_at91rm9200_clk_main_setup(struct device_node *np, 465 struct at91_pmc *pmc) 466 { 467 struct clk *clk; 468 const char *parent_name; 469 const char *name = np->name; 470 471 parent_name = of_clk_get_parent_name(np, 0); 472 of_property_read_string(np, "clock-output-names", &name); 473 474 clk = at91_clk_register_rm9200_main(pmc, name, parent_name); 475 if (IS_ERR(clk)) 476 return; 477 478 of_clk_add_provider(np, of_clk_src_simple_get, clk); 479 } 480 481 static irqreturn_t clk_sam9x5_main_irq_handler(int irq, void *dev_id) 482 { 483 struct clk_sam9x5_main *clkmain = dev_id; 484 485 wake_up(&clkmain->wait); 486 disable_irq_nosync(clkmain->irq); 487 488 return IRQ_HANDLED; 489 } 490 491 static int clk_sam9x5_main_prepare(struct clk_hw *hw) 492 { 493 struct clk_sam9x5_main *clkmain = to_clk_sam9x5_main(hw); 494 struct at91_pmc *pmc = clkmain->pmc; 495 496 while (!(pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_MOSCSELS)) { 497 enable_irq(clkmain->irq); 498 wait_event(clkmain->wait, 499 pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_MOSCSELS); 500 } 501 502 return clk_main_probe_frequency(pmc); 503 } 504 505 static int clk_sam9x5_main_is_prepared(struct clk_hw *hw) 506 { 507 struct clk_sam9x5_main *clkmain = to_clk_sam9x5_main(hw); 508 509 return !!(pmc_read(clkmain->pmc, AT91_PMC_SR) & AT91_PMC_MOSCSELS); 510 } 511 512 static unsigned long clk_sam9x5_main_recalc_rate(struct clk_hw *hw, 513 unsigned long parent_rate) 514 { 515 struct clk_sam9x5_main *clkmain = to_clk_sam9x5_main(hw); 516 517 return clk_main_recalc_rate(clkmain->pmc, parent_rate); 518 } 519 520 static int clk_sam9x5_main_set_parent(struct clk_hw *hw, u8 index) 521 { 522 struct clk_sam9x5_main *clkmain = to_clk_sam9x5_main(hw); 523 struct at91_pmc *pmc = clkmain->pmc; 524 u32 tmp; 525 526 if (index > 1) 527 return -EINVAL; 528 529 tmp = pmc_read(pmc, AT91_CKGR_MOR) & ~MOR_KEY_MASK; 530 531 if (index && !(tmp & AT91_PMC_MOSCSEL)) 532 pmc_write(pmc, AT91_CKGR_MOR, tmp | AT91_PMC_MOSCSEL); 533 else if (!index && (tmp & AT91_PMC_MOSCSEL)) 534 pmc_write(pmc, AT91_CKGR_MOR, tmp & ~AT91_PMC_MOSCSEL); 535 536 while (!(pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_MOSCSELS)) { 537 enable_irq(clkmain->irq); 538 wait_event(clkmain->wait, 539 pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_MOSCSELS); 540 } 541 542 return 0; 543 } 544 545 static u8 clk_sam9x5_main_get_parent(struct clk_hw *hw) 546 { 547 struct clk_sam9x5_main *clkmain = to_clk_sam9x5_main(hw); 548 549 return !!(pmc_read(clkmain->pmc, AT91_CKGR_MOR) & AT91_PMC_MOSCEN); 550 } 551 552 static const struct clk_ops sam9x5_main_ops = { 553 .prepare = clk_sam9x5_main_prepare, 554 .is_prepared = clk_sam9x5_main_is_prepared, 555 .recalc_rate = clk_sam9x5_main_recalc_rate, 556 .set_parent = clk_sam9x5_main_set_parent, 557 .get_parent = clk_sam9x5_main_get_parent, 558 }; 559 560 static struct clk * __init 561 at91_clk_register_sam9x5_main(struct at91_pmc *pmc, 562 unsigned int irq, 563 const char *name, 564 const char **parent_names, 565 int num_parents) 566 { 567 int ret; 568 struct clk_sam9x5_main *clkmain; 569 struct clk *clk = NULL; 570 struct clk_init_data init; 571 572 if (!pmc || !irq || !name) 573 return ERR_PTR(-EINVAL); 574 575 if (!parent_names || !num_parents) 576 return ERR_PTR(-EINVAL); 577 578 clkmain = kzalloc(sizeof(*clkmain), GFP_KERNEL); 579 if (!clkmain) 580 return ERR_PTR(-ENOMEM); 581 582 init.name = name; 583 init.ops = &sam9x5_main_ops; 584 init.parent_names = parent_names; 585 init.num_parents = num_parents; 586 init.flags = CLK_SET_PARENT_GATE; 587 588 clkmain->hw.init = &init; 589 clkmain->pmc = pmc; 590 clkmain->irq = irq; 591 clkmain->parent = !!(pmc_read(clkmain->pmc, AT91_CKGR_MOR) & 592 AT91_PMC_MOSCEN); 593 init_waitqueue_head(&clkmain->wait); 594 irq_set_status_flags(clkmain->irq, IRQ_NOAUTOEN); 595 ret = request_irq(clkmain->irq, clk_sam9x5_main_irq_handler, 596 IRQF_TRIGGER_HIGH, name, clkmain); 597 if (ret) 598 return ERR_PTR(ret); 599 600 clk = clk_register(NULL, &clkmain->hw); 601 if (IS_ERR(clk)) { 602 free_irq(clkmain->irq, clkmain); 603 kfree(clkmain); 604 } 605 606 return clk; 607 } 608 609 void __init of_at91sam9x5_clk_main_setup(struct device_node *np, 610 struct at91_pmc *pmc) 611 { 612 struct clk *clk; 613 const char *parent_names[2]; 614 int num_parents; 615 unsigned int irq; 616 const char *name = np->name; 617 618 num_parents = of_clk_get_parent_count(np); 619 if (num_parents <= 0 || num_parents > 2) 620 return; 621 622 of_clk_parent_fill(np, parent_names, num_parents); 623 624 of_property_read_string(np, "clock-output-names", &name); 625 626 irq = irq_of_parse_and_map(np, 0); 627 if (!irq) 628 return; 629 630 clk = at91_clk_register_sam9x5_main(pmc, irq, name, parent_names, 631 num_parents); 632 if (IS_ERR(clk)) 633 return; 634 635 of_clk_add_provider(np, of_clk_src_simple_get, clk); 636 } 637