1 /* 2 * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com> 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 * 9 */ 10 11 #include <linux/clk-provider.h> 12 #include <linux/clkdev.h> 13 #include <linux/clk/at91_pmc.h> 14 #include <linux/delay.h> 15 #include <linux/of.h> 16 #include <linux/of_address.h> 17 #include <linux/of_irq.h> 18 #include <linux/io.h> 19 #include <linux/interrupt.h> 20 #include <linux/irq.h> 21 #include <linux/sched.h> 22 #include <linux/wait.h> 23 24 #include "pmc.h" 25 26 #define SLOW_CLOCK_FREQ 32768 27 #define MAINF_DIV 16 28 #define MAINFRDY_TIMEOUT (((MAINF_DIV + 1) * USEC_PER_SEC) / \ 29 SLOW_CLOCK_FREQ) 30 #define MAINF_LOOP_MIN_WAIT (USEC_PER_SEC / SLOW_CLOCK_FREQ) 31 #define MAINF_LOOP_MAX_WAIT MAINFRDY_TIMEOUT 32 33 #define MOR_KEY_MASK (0xff << 16) 34 35 struct clk_main_osc { 36 struct clk_hw hw; 37 struct at91_pmc *pmc; 38 unsigned int irq; 39 wait_queue_head_t wait; 40 }; 41 42 #define to_clk_main_osc(hw) container_of(hw, struct clk_main_osc, hw) 43 44 struct clk_main_rc_osc { 45 struct clk_hw hw; 46 struct at91_pmc *pmc; 47 unsigned int irq; 48 wait_queue_head_t wait; 49 unsigned long frequency; 50 unsigned long accuracy; 51 }; 52 53 #define to_clk_main_rc_osc(hw) container_of(hw, struct clk_main_rc_osc, hw) 54 55 struct clk_rm9200_main { 56 struct clk_hw hw; 57 struct at91_pmc *pmc; 58 }; 59 60 #define to_clk_rm9200_main(hw) container_of(hw, struct clk_rm9200_main, hw) 61 62 struct clk_sam9x5_main { 63 struct clk_hw hw; 64 struct at91_pmc *pmc; 65 unsigned int irq; 66 wait_queue_head_t wait; 67 u8 parent; 68 }; 69 70 #define to_clk_sam9x5_main(hw) container_of(hw, struct clk_sam9x5_main, hw) 71 72 static irqreturn_t clk_main_osc_irq_handler(int irq, void *dev_id) 73 { 74 struct clk_main_osc *osc = dev_id; 75 76 wake_up(&osc->wait); 77 disable_irq_nosync(osc->irq); 78 79 return IRQ_HANDLED; 80 } 81 82 static int clk_main_osc_prepare(struct clk_hw *hw) 83 { 84 struct clk_main_osc *osc = to_clk_main_osc(hw); 85 struct at91_pmc *pmc = osc->pmc; 86 u32 tmp; 87 88 tmp = pmc_read(pmc, AT91_CKGR_MOR) & ~MOR_KEY_MASK; 89 if (tmp & AT91_PMC_OSCBYPASS) 90 return 0; 91 92 if (!(tmp & AT91_PMC_MOSCEN)) { 93 tmp |= AT91_PMC_MOSCEN | AT91_PMC_KEY; 94 pmc_write(pmc, AT91_CKGR_MOR, tmp); 95 } 96 97 while (!(pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_MOSCS)) { 98 enable_irq(osc->irq); 99 wait_event(osc->wait, 100 pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_MOSCS); 101 } 102 103 return 0; 104 } 105 106 static void clk_main_osc_unprepare(struct clk_hw *hw) 107 { 108 struct clk_main_osc *osc = to_clk_main_osc(hw); 109 struct at91_pmc *pmc = osc->pmc; 110 u32 tmp = pmc_read(pmc, AT91_CKGR_MOR); 111 112 if (tmp & AT91_PMC_OSCBYPASS) 113 return; 114 115 if (!(tmp & AT91_PMC_MOSCEN)) 116 return; 117 118 tmp &= ~(AT91_PMC_KEY | AT91_PMC_MOSCEN); 119 pmc_write(pmc, AT91_CKGR_MOR, tmp | AT91_PMC_KEY); 120 } 121 122 static int clk_main_osc_is_prepared(struct clk_hw *hw) 123 { 124 struct clk_main_osc *osc = to_clk_main_osc(hw); 125 struct at91_pmc *pmc = osc->pmc; 126 u32 tmp = pmc_read(pmc, AT91_CKGR_MOR); 127 128 if (tmp & AT91_PMC_OSCBYPASS) 129 return 1; 130 131 return !!((pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_MOSCS) && 132 (pmc_read(pmc, AT91_CKGR_MOR) & AT91_PMC_MOSCEN)); 133 } 134 135 static const struct clk_ops main_osc_ops = { 136 .prepare = clk_main_osc_prepare, 137 .unprepare = clk_main_osc_unprepare, 138 .is_prepared = clk_main_osc_is_prepared, 139 }; 140 141 static struct clk * __init 142 at91_clk_register_main_osc(struct at91_pmc *pmc, 143 unsigned int irq, 144 const char *name, 145 const char *parent_name, 146 bool bypass) 147 { 148 int ret; 149 struct clk_main_osc *osc; 150 struct clk *clk = NULL; 151 struct clk_init_data init; 152 153 if (!pmc || !irq || !name || !parent_name) 154 return ERR_PTR(-EINVAL); 155 156 osc = kzalloc(sizeof(*osc), GFP_KERNEL); 157 if (!osc) 158 return ERR_PTR(-ENOMEM); 159 160 init.name = name; 161 init.ops = &main_osc_ops; 162 init.parent_names = &parent_name; 163 init.num_parents = 1; 164 init.flags = CLK_IGNORE_UNUSED; 165 166 osc->hw.init = &init; 167 osc->pmc = pmc; 168 osc->irq = irq; 169 170 init_waitqueue_head(&osc->wait); 171 irq_set_status_flags(osc->irq, IRQ_NOAUTOEN); 172 ret = request_irq(osc->irq, clk_main_osc_irq_handler, 173 IRQF_TRIGGER_HIGH, name, osc); 174 if (ret) 175 return ERR_PTR(ret); 176 177 if (bypass) 178 pmc_write(pmc, AT91_CKGR_MOR, 179 (pmc_read(pmc, AT91_CKGR_MOR) & 180 ~(MOR_KEY_MASK | AT91_PMC_MOSCEN)) | 181 AT91_PMC_OSCBYPASS | AT91_PMC_KEY); 182 183 clk = clk_register(NULL, &osc->hw); 184 if (IS_ERR(clk)) { 185 free_irq(irq, osc); 186 kfree(osc); 187 } 188 189 return clk; 190 } 191 192 void __init of_at91rm9200_clk_main_osc_setup(struct device_node *np, 193 struct at91_pmc *pmc) 194 { 195 struct clk *clk; 196 unsigned int irq; 197 const char *name = np->name; 198 const char *parent_name; 199 bool bypass; 200 201 of_property_read_string(np, "clock-output-names", &name); 202 bypass = of_property_read_bool(np, "atmel,osc-bypass"); 203 parent_name = of_clk_get_parent_name(np, 0); 204 205 irq = irq_of_parse_and_map(np, 0); 206 if (!irq) 207 return; 208 209 clk = at91_clk_register_main_osc(pmc, irq, name, parent_name, bypass); 210 if (IS_ERR(clk)) 211 return; 212 213 of_clk_add_provider(np, of_clk_src_simple_get, clk); 214 } 215 216 static irqreturn_t clk_main_rc_osc_irq_handler(int irq, void *dev_id) 217 { 218 struct clk_main_rc_osc *osc = dev_id; 219 220 wake_up(&osc->wait); 221 disable_irq_nosync(osc->irq); 222 223 return IRQ_HANDLED; 224 } 225 226 static int clk_main_rc_osc_prepare(struct clk_hw *hw) 227 { 228 struct clk_main_rc_osc *osc = to_clk_main_rc_osc(hw); 229 struct at91_pmc *pmc = osc->pmc; 230 u32 tmp; 231 232 tmp = pmc_read(pmc, AT91_CKGR_MOR) & ~MOR_KEY_MASK; 233 234 if (!(tmp & AT91_PMC_MOSCRCEN)) { 235 tmp |= AT91_PMC_MOSCRCEN | AT91_PMC_KEY; 236 pmc_write(pmc, AT91_CKGR_MOR, tmp); 237 } 238 239 while (!(pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_MOSCRCS)) { 240 enable_irq(osc->irq); 241 wait_event(osc->wait, 242 pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_MOSCRCS); 243 } 244 245 return 0; 246 } 247 248 static void clk_main_rc_osc_unprepare(struct clk_hw *hw) 249 { 250 struct clk_main_rc_osc *osc = to_clk_main_rc_osc(hw); 251 struct at91_pmc *pmc = osc->pmc; 252 u32 tmp = pmc_read(pmc, AT91_CKGR_MOR); 253 254 if (!(tmp & AT91_PMC_MOSCRCEN)) 255 return; 256 257 tmp &= ~(MOR_KEY_MASK | AT91_PMC_MOSCRCEN); 258 pmc_write(pmc, AT91_CKGR_MOR, tmp | AT91_PMC_KEY); 259 } 260 261 static int clk_main_rc_osc_is_prepared(struct clk_hw *hw) 262 { 263 struct clk_main_rc_osc *osc = to_clk_main_rc_osc(hw); 264 struct at91_pmc *pmc = osc->pmc; 265 266 return !!((pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_MOSCRCS) && 267 (pmc_read(pmc, AT91_CKGR_MOR) & AT91_PMC_MOSCRCEN)); 268 } 269 270 static unsigned long clk_main_rc_osc_recalc_rate(struct clk_hw *hw, 271 unsigned long parent_rate) 272 { 273 struct clk_main_rc_osc *osc = to_clk_main_rc_osc(hw); 274 275 return osc->frequency; 276 } 277 278 static unsigned long clk_main_rc_osc_recalc_accuracy(struct clk_hw *hw, 279 unsigned long parent_acc) 280 { 281 struct clk_main_rc_osc *osc = to_clk_main_rc_osc(hw); 282 283 return osc->accuracy; 284 } 285 286 static const struct clk_ops main_rc_osc_ops = { 287 .prepare = clk_main_rc_osc_prepare, 288 .unprepare = clk_main_rc_osc_unprepare, 289 .is_prepared = clk_main_rc_osc_is_prepared, 290 .recalc_rate = clk_main_rc_osc_recalc_rate, 291 .recalc_accuracy = clk_main_rc_osc_recalc_accuracy, 292 }; 293 294 static struct clk * __init 295 at91_clk_register_main_rc_osc(struct at91_pmc *pmc, 296 unsigned int irq, 297 const char *name, 298 u32 frequency, u32 accuracy) 299 { 300 int ret; 301 struct clk_main_rc_osc *osc; 302 struct clk *clk = NULL; 303 struct clk_init_data init; 304 305 if (!pmc || !irq || !name || !frequency) 306 return ERR_PTR(-EINVAL); 307 308 osc = kzalloc(sizeof(*osc), GFP_KERNEL); 309 if (!osc) 310 return ERR_PTR(-ENOMEM); 311 312 init.name = name; 313 init.ops = &main_rc_osc_ops; 314 init.parent_names = NULL; 315 init.num_parents = 0; 316 init.flags = CLK_IS_ROOT | CLK_IGNORE_UNUSED; 317 318 osc->hw.init = &init; 319 osc->pmc = pmc; 320 osc->irq = irq; 321 osc->frequency = frequency; 322 osc->accuracy = accuracy; 323 324 init_waitqueue_head(&osc->wait); 325 irq_set_status_flags(osc->irq, IRQ_NOAUTOEN); 326 ret = request_irq(osc->irq, clk_main_rc_osc_irq_handler, 327 IRQF_TRIGGER_HIGH, name, osc); 328 if (ret) 329 return ERR_PTR(ret); 330 331 clk = clk_register(NULL, &osc->hw); 332 if (IS_ERR(clk)) { 333 free_irq(irq, osc); 334 kfree(osc); 335 } 336 337 return clk; 338 } 339 340 void __init of_at91sam9x5_clk_main_rc_osc_setup(struct device_node *np, 341 struct at91_pmc *pmc) 342 { 343 struct clk *clk; 344 unsigned int irq; 345 u32 frequency = 0; 346 u32 accuracy = 0; 347 const char *name = np->name; 348 349 of_property_read_string(np, "clock-output-names", &name); 350 of_property_read_u32(np, "clock-frequency", &frequency); 351 of_property_read_u32(np, "clock-accuracy", &accuracy); 352 353 irq = irq_of_parse_and_map(np, 0); 354 if (!irq) 355 return; 356 357 clk = at91_clk_register_main_rc_osc(pmc, irq, name, frequency, 358 accuracy); 359 if (IS_ERR(clk)) 360 return; 361 362 of_clk_add_provider(np, of_clk_src_simple_get, clk); 363 } 364 365 366 static int clk_main_probe_frequency(struct at91_pmc *pmc) 367 { 368 unsigned long prep_time, timeout; 369 u32 tmp; 370 371 timeout = jiffies + usecs_to_jiffies(MAINFRDY_TIMEOUT); 372 do { 373 prep_time = jiffies; 374 tmp = pmc_read(pmc, AT91_CKGR_MCFR); 375 if (tmp & AT91_PMC_MAINRDY) 376 return 0; 377 usleep_range(MAINF_LOOP_MIN_WAIT, MAINF_LOOP_MAX_WAIT); 378 } while (time_before(prep_time, timeout)); 379 380 return -ETIMEDOUT; 381 } 382 383 static unsigned long clk_main_recalc_rate(struct at91_pmc *pmc, 384 unsigned long parent_rate) 385 { 386 u32 tmp; 387 388 if (parent_rate) 389 return parent_rate; 390 391 tmp = pmc_read(pmc, AT91_CKGR_MCFR); 392 if (!(tmp & AT91_PMC_MAINRDY)) 393 return 0; 394 395 return ((tmp & AT91_PMC_MAINF) * SLOW_CLOCK_FREQ) / MAINF_DIV; 396 } 397 398 static int clk_rm9200_main_prepare(struct clk_hw *hw) 399 { 400 struct clk_rm9200_main *clkmain = to_clk_rm9200_main(hw); 401 402 return clk_main_probe_frequency(clkmain->pmc); 403 } 404 405 static int clk_rm9200_main_is_prepared(struct clk_hw *hw) 406 { 407 struct clk_rm9200_main *clkmain = to_clk_rm9200_main(hw); 408 409 return !!(pmc_read(clkmain->pmc, AT91_CKGR_MCFR) & AT91_PMC_MAINRDY); 410 } 411 412 static unsigned long clk_rm9200_main_recalc_rate(struct clk_hw *hw, 413 unsigned long parent_rate) 414 { 415 struct clk_rm9200_main *clkmain = to_clk_rm9200_main(hw); 416 417 return clk_main_recalc_rate(clkmain->pmc, parent_rate); 418 } 419 420 static const struct clk_ops rm9200_main_ops = { 421 .prepare = clk_rm9200_main_prepare, 422 .is_prepared = clk_rm9200_main_is_prepared, 423 .recalc_rate = clk_rm9200_main_recalc_rate, 424 }; 425 426 static struct clk * __init 427 at91_clk_register_rm9200_main(struct at91_pmc *pmc, 428 const char *name, 429 const char *parent_name) 430 { 431 struct clk_rm9200_main *clkmain; 432 struct clk *clk = NULL; 433 struct clk_init_data init; 434 435 if (!pmc || !name) 436 return ERR_PTR(-EINVAL); 437 438 if (!parent_name) 439 return ERR_PTR(-EINVAL); 440 441 clkmain = kzalloc(sizeof(*clkmain), GFP_KERNEL); 442 if (!clkmain) 443 return ERR_PTR(-ENOMEM); 444 445 init.name = name; 446 init.ops = &rm9200_main_ops; 447 init.parent_names = &parent_name; 448 init.num_parents = 1; 449 init.flags = 0; 450 451 clkmain->hw.init = &init; 452 clkmain->pmc = pmc; 453 454 clk = clk_register(NULL, &clkmain->hw); 455 if (IS_ERR(clk)) 456 kfree(clkmain); 457 458 return clk; 459 } 460 461 void __init of_at91rm9200_clk_main_setup(struct device_node *np, 462 struct at91_pmc *pmc) 463 { 464 struct clk *clk; 465 const char *parent_name; 466 const char *name = np->name; 467 468 parent_name = of_clk_get_parent_name(np, 0); 469 of_property_read_string(np, "clock-output-names", &name); 470 471 clk = at91_clk_register_rm9200_main(pmc, name, parent_name); 472 if (IS_ERR(clk)) 473 return; 474 475 of_clk_add_provider(np, of_clk_src_simple_get, clk); 476 } 477 478 static irqreturn_t clk_sam9x5_main_irq_handler(int irq, void *dev_id) 479 { 480 struct clk_sam9x5_main *clkmain = dev_id; 481 482 wake_up(&clkmain->wait); 483 disable_irq_nosync(clkmain->irq); 484 485 return IRQ_HANDLED; 486 } 487 488 static int clk_sam9x5_main_prepare(struct clk_hw *hw) 489 { 490 struct clk_sam9x5_main *clkmain = to_clk_sam9x5_main(hw); 491 struct at91_pmc *pmc = clkmain->pmc; 492 493 while (!(pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_MOSCSELS)) { 494 enable_irq(clkmain->irq); 495 wait_event(clkmain->wait, 496 pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_MOSCSELS); 497 } 498 499 return clk_main_probe_frequency(pmc); 500 } 501 502 static int clk_sam9x5_main_is_prepared(struct clk_hw *hw) 503 { 504 struct clk_sam9x5_main *clkmain = to_clk_sam9x5_main(hw); 505 506 return !!(pmc_read(clkmain->pmc, AT91_PMC_SR) & AT91_PMC_MOSCSELS); 507 } 508 509 static unsigned long clk_sam9x5_main_recalc_rate(struct clk_hw *hw, 510 unsigned long parent_rate) 511 { 512 struct clk_sam9x5_main *clkmain = to_clk_sam9x5_main(hw); 513 514 return clk_main_recalc_rate(clkmain->pmc, parent_rate); 515 } 516 517 static int clk_sam9x5_main_set_parent(struct clk_hw *hw, u8 index) 518 { 519 struct clk_sam9x5_main *clkmain = to_clk_sam9x5_main(hw); 520 struct at91_pmc *pmc = clkmain->pmc; 521 u32 tmp; 522 523 if (index > 1) 524 return -EINVAL; 525 526 tmp = pmc_read(pmc, AT91_CKGR_MOR) & ~MOR_KEY_MASK; 527 528 if (index && !(tmp & AT91_PMC_MOSCSEL)) 529 pmc_write(pmc, AT91_CKGR_MOR, tmp | AT91_PMC_MOSCSEL); 530 else if (!index && (tmp & AT91_PMC_MOSCSEL)) 531 pmc_write(pmc, AT91_CKGR_MOR, tmp & ~AT91_PMC_MOSCSEL); 532 533 while (!(pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_MOSCSELS)) { 534 enable_irq(clkmain->irq); 535 wait_event(clkmain->wait, 536 pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_MOSCSELS); 537 } 538 539 return 0; 540 } 541 542 static u8 clk_sam9x5_main_get_parent(struct clk_hw *hw) 543 { 544 struct clk_sam9x5_main *clkmain = to_clk_sam9x5_main(hw); 545 546 return !!(pmc_read(clkmain->pmc, AT91_CKGR_MOR) & AT91_PMC_MOSCEN); 547 } 548 549 static const struct clk_ops sam9x5_main_ops = { 550 .prepare = clk_sam9x5_main_prepare, 551 .is_prepared = clk_sam9x5_main_is_prepared, 552 .recalc_rate = clk_sam9x5_main_recalc_rate, 553 .set_parent = clk_sam9x5_main_set_parent, 554 .get_parent = clk_sam9x5_main_get_parent, 555 }; 556 557 static struct clk * __init 558 at91_clk_register_sam9x5_main(struct at91_pmc *pmc, 559 unsigned int irq, 560 const char *name, 561 const char **parent_names, 562 int num_parents) 563 { 564 int ret; 565 struct clk_sam9x5_main *clkmain; 566 struct clk *clk = NULL; 567 struct clk_init_data init; 568 569 if (!pmc || !irq || !name) 570 return ERR_PTR(-EINVAL); 571 572 if (!parent_names || !num_parents) 573 return ERR_PTR(-EINVAL); 574 575 clkmain = kzalloc(sizeof(*clkmain), GFP_KERNEL); 576 if (!clkmain) 577 return ERR_PTR(-ENOMEM); 578 579 init.name = name; 580 init.ops = &sam9x5_main_ops; 581 init.parent_names = parent_names; 582 init.num_parents = num_parents; 583 init.flags = CLK_SET_PARENT_GATE; 584 585 clkmain->hw.init = &init; 586 clkmain->pmc = pmc; 587 clkmain->irq = irq; 588 clkmain->parent = !!(pmc_read(clkmain->pmc, AT91_CKGR_MOR) & 589 AT91_PMC_MOSCEN); 590 init_waitqueue_head(&clkmain->wait); 591 irq_set_status_flags(clkmain->irq, IRQ_NOAUTOEN); 592 ret = request_irq(clkmain->irq, clk_sam9x5_main_irq_handler, 593 IRQF_TRIGGER_HIGH, name, clkmain); 594 if (ret) 595 return ERR_PTR(ret); 596 597 clk = clk_register(NULL, &clkmain->hw); 598 if (IS_ERR(clk)) { 599 free_irq(clkmain->irq, clkmain); 600 kfree(clkmain); 601 } 602 603 return clk; 604 } 605 606 void __init of_at91sam9x5_clk_main_setup(struct device_node *np, 607 struct at91_pmc *pmc) 608 { 609 struct clk *clk; 610 const char *parent_names[2]; 611 int num_parents; 612 unsigned int irq; 613 const char *name = np->name; 614 int i; 615 616 num_parents = of_count_phandle_with_args(np, "clocks", "#clock-cells"); 617 if (num_parents <= 0 || num_parents > 2) 618 return; 619 620 for (i = 0; i < num_parents; ++i) { 621 parent_names[i] = of_clk_get_parent_name(np, i); 622 if (!parent_names[i]) 623 return; 624 } 625 626 of_property_read_string(np, "clock-output-names", &name); 627 628 irq = irq_of_parse_and_map(np, 0); 629 if (!irq) 630 return; 631 632 clk = at91_clk_register_sam9x5_main(pmc, irq, name, parent_names, 633 num_parents); 634 if (IS_ERR(clk)) 635 return; 636 637 of_clk_add_provider(np, of_clk_src_simple_get, clk); 638 } 639