1 // SPDX-License-Identifier: GPL-2.0+
2 // Copyright IBM Corp
3
4 #define pr_fmt(fmt) "clk-aspeed: " fmt
5
6 #include <linux/mfd/syscon.h>
7 #include <linux/of.h>
8 #include <linux/of_address.h>
9 #include <linux/platform_device.h>
10 #include <linux/regmap.h>
11 #include <linux/slab.h>
12
13 #include <dt-bindings/clock/aspeed-clock.h>
14
15 #include "clk-aspeed.h"
16
17 #define ASPEED_NUM_CLKS 38
18
19 #define ASPEED_RESET2_OFFSET 32
20
21 #define ASPEED_RESET_CTRL 0x04
22 #define ASPEED_CLK_SELECTION 0x08
23 #define ASPEED_CLK_STOP_CTRL 0x0c
24 #define ASPEED_MPLL_PARAM 0x20
25 #define ASPEED_HPLL_PARAM 0x24
26 #define AST2500_HPLL_BYPASS_EN BIT(20)
27 #define AST2400_HPLL_PROGRAMMED BIT(18)
28 #define AST2400_HPLL_BYPASS_EN BIT(17)
29 #define ASPEED_MISC_CTRL 0x2c
30 #define UART_DIV13_EN BIT(12)
31 #define ASPEED_MAC_CLK_DLY 0x48
32 #define ASPEED_STRAP 0x70
33 #define CLKIN_25MHZ_EN BIT(23)
34 #define AST2400_CLK_SOURCE_SEL BIT(18)
35 #define ASPEED_CLK_SELECTION_2 0xd8
36 #define ASPEED_RESET_CTRL2 0xd4
37
38 /* Globally visible clocks */
39 static DEFINE_SPINLOCK(aspeed_clk_lock);
40
41 /* Keeps track of all clocks */
42 static struct clk_hw_onecell_data *aspeed_clk_data;
43
44 static void __iomem *scu_base;
45
46 /* TODO: ask Aspeed about the actual parent data */
47 static const struct aspeed_gate_data aspeed_gates[] = {
48 /* clk rst name parent flags */
49 [ASPEED_CLK_GATE_ECLK] = { 0, 6, "eclk-gate", "eclk", 0 }, /* Video Engine */
50 [ASPEED_CLK_GATE_GCLK] = { 1, 7, "gclk-gate", NULL, 0 }, /* 2D engine */
51 [ASPEED_CLK_GATE_MCLK] = { 2, -1, "mclk-gate", "mpll", CLK_IS_CRITICAL }, /* SDRAM */
52 [ASPEED_CLK_GATE_VCLK] = { 3, -1, "vclk-gate", NULL, 0 }, /* Video Capture */
53 [ASPEED_CLK_GATE_BCLK] = { 4, 8, "bclk-gate", "bclk", CLK_IS_CRITICAL }, /* PCIe/PCI */
54 [ASPEED_CLK_GATE_DCLK] = { 5, -1, "dclk-gate", NULL, CLK_IS_CRITICAL }, /* DAC */
55 [ASPEED_CLK_GATE_REFCLK] = { 6, -1, "refclk-gate", "clkin", CLK_IS_CRITICAL },
56 [ASPEED_CLK_GATE_USBPORT2CLK] = { 7, 3, "usb-port2-gate", NULL, 0 }, /* USB2.0 Host port 2 */
57 [ASPEED_CLK_GATE_LCLK] = { 8, 5, "lclk-gate", NULL, 0 }, /* LPC */
58 [ASPEED_CLK_GATE_USBUHCICLK] = { 9, 15, "usb-uhci-gate", NULL, 0 }, /* USB1.1 (requires port 2 enabled) */
59 [ASPEED_CLK_GATE_D1CLK] = { 10, 13, "d1clk-gate", NULL, 0 }, /* GFX CRT */
60 [ASPEED_CLK_GATE_YCLK] = { 13, 4, "yclk-gate", NULL, 0 }, /* HAC */
61 [ASPEED_CLK_GATE_USBPORT1CLK] = { 14, 14, "usb-port1-gate", NULL, 0 }, /* USB2 hub/USB2 host port 1/USB1.1 dev */
62 [ASPEED_CLK_GATE_UART1CLK] = { 15, -1, "uart1clk-gate", "uart", 0 }, /* UART1 */
63 [ASPEED_CLK_GATE_UART2CLK] = { 16, -1, "uart2clk-gate", "uart", 0 }, /* UART2 */
64 [ASPEED_CLK_GATE_UART5CLK] = { 17, -1, "uart5clk-gate", "uart", 0 }, /* UART5 */
65 [ASPEED_CLK_GATE_ESPICLK] = { 19, -1, "espiclk-gate", NULL, 0 }, /* eSPI */
66 [ASPEED_CLK_GATE_MAC1CLK] = { 20, 11, "mac1clk-gate", "mac", 0 }, /* MAC1 */
67 [ASPEED_CLK_GATE_MAC2CLK] = { 21, 12, "mac2clk-gate", "mac", 0 }, /* MAC2 */
68 [ASPEED_CLK_GATE_RSACLK] = { 24, -1, "rsaclk-gate", NULL, 0 }, /* RSA */
69 [ASPEED_CLK_GATE_UART3CLK] = { 25, -1, "uart3clk-gate", "uart", 0 }, /* UART3 */
70 [ASPEED_CLK_GATE_UART4CLK] = { 26, -1, "uart4clk-gate", "uart", 0 }, /* UART4 */
71 [ASPEED_CLK_GATE_SDCLK] = { 27, 16, "sdclk-gate", NULL, 0 }, /* SDIO/SD */
72 [ASPEED_CLK_GATE_LHCCLK] = { 28, -1, "lhclk-gate", "lhclk", 0 }, /* LPC master/LPC+ */
73 };
74
75 static const char * const eclk_parent_names[] = {
76 "mpll",
77 "hpll",
78 "dpll",
79 };
80
81 static const struct clk_div_table ast2500_eclk_div_table[] = {
82 { 0x0, 2 },
83 { 0x1, 2 },
84 { 0x2, 3 },
85 { 0x3, 4 },
86 { 0x4, 5 },
87 { 0x5, 6 },
88 { 0x6, 7 },
89 { 0x7, 8 },
90 { 0 }
91 };
92
93 static const struct clk_div_table ast2500_mac_div_table[] = {
94 { 0x0, 4 }, /* Yep, really. Aspeed confirmed this is correct */
95 { 0x1, 4 },
96 { 0x2, 6 },
97 { 0x3, 8 },
98 { 0x4, 10 },
99 { 0x5, 12 },
100 { 0x6, 14 },
101 { 0x7, 16 },
102 { 0 }
103 };
104
105 static const struct clk_div_table ast2400_div_table[] = {
106 { 0x0, 2 },
107 { 0x1, 4 },
108 { 0x2, 6 },
109 { 0x3, 8 },
110 { 0x4, 10 },
111 { 0x5, 12 },
112 { 0x6, 14 },
113 { 0x7, 16 },
114 { 0 }
115 };
116
117 static const struct clk_div_table ast2500_div_table[] = {
118 { 0x0, 4 },
119 { 0x1, 8 },
120 { 0x2, 12 },
121 { 0x3, 16 },
122 { 0x4, 20 },
123 { 0x5, 24 },
124 { 0x6, 28 },
125 { 0x7, 32 },
126 { 0 }
127 };
128
aspeed_ast2400_calc_pll(const char * name,u32 val)129 static struct clk_hw *aspeed_ast2400_calc_pll(const char *name, u32 val)
130 {
131 unsigned int mult, div;
132
133 if (val & AST2400_HPLL_BYPASS_EN) {
134 /* Pass through mode */
135 mult = div = 1;
136 } else {
137 /* F = 24Mhz * (2-OD) * [(N + 2) / (D + 1)] */
138 u32 n = (val >> 5) & 0x3f;
139 u32 od = (val >> 4) & 0x1;
140 u32 d = val & 0xf;
141
142 mult = (2 - od) * (n + 2);
143 div = d + 1;
144 }
145 return clk_hw_register_fixed_factor(NULL, name, "clkin", 0,
146 mult, div);
147 };
148
aspeed_ast2500_calc_pll(const char * name,u32 val)149 static struct clk_hw *aspeed_ast2500_calc_pll(const char *name, u32 val)
150 {
151 unsigned int mult, div;
152
153 if (val & AST2500_HPLL_BYPASS_EN) {
154 /* Pass through mode */
155 mult = div = 1;
156 } else {
157 /* F = clkin * [(M+1) / (N+1)] / (P + 1) */
158 u32 p = (val >> 13) & 0x3f;
159 u32 m = (val >> 5) & 0xff;
160 u32 n = val & 0x1f;
161
162 mult = (m + 1) / (n + 1);
163 div = p + 1;
164 }
165
166 return clk_hw_register_fixed_factor(NULL, name, "clkin", 0,
167 mult, div);
168 }
169
170 static const struct aspeed_clk_soc_data ast2500_data = {
171 .div_table = ast2500_div_table,
172 .eclk_div_table = ast2500_eclk_div_table,
173 .mac_div_table = ast2500_mac_div_table,
174 .calc_pll = aspeed_ast2500_calc_pll,
175 };
176
177 static const struct aspeed_clk_soc_data ast2400_data = {
178 .div_table = ast2400_div_table,
179 .eclk_div_table = ast2400_div_table,
180 .mac_div_table = ast2400_div_table,
181 .calc_pll = aspeed_ast2400_calc_pll,
182 };
183
aspeed_clk_is_enabled(struct clk_hw * hw)184 static int aspeed_clk_is_enabled(struct clk_hw *hw)
185 {
186 struct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw);
187 u32 clk = BIT(gate->clock_idx);
188 u32 rst = BIT(gate->reset_idx);
189 u32 enval = (gate->flags & CLK_GATE_SET_TO_DISABLE) ? 0 : clk;
190 u32 reg;
191
192 /*
193 * If the IP is in reset, treat the clock as not enabled,
194 * this happens with some clocks such as the USB one when
195 * coming from cold reset. Without this, aspeed_clk_enable()
196 * will fail to lift the reset.
197 */
198 if (gate->reset_idx >= 0) {
199 regmap_read(gate->map, ASPEED_RESET_CTRL, ®);
200 if (reg & rst)
201 return 0;
202 }
203
204 regmap_read(gate->map, ASPEED_CLK_STOP_CTRL, ®);
205
206 return ((reg & clk) == enval) ? 1 : 0;
207 }
208
aspeed_clk_enable(struct clk_hw * hw)209 static int aspeed_clk_enable(struct clk_hw *hw)
210 {
211 struct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw);
212 unsigned long flags;
213 u32 clk = BIT(gate->clock_idx);
214 u32 rst = BIT(gate->reset_idx);
215 u32 enval;
216
217 spin_lock_irqsave(gate->lock, flags);
218
219 if (aspeed_clk_is_enabled(hw)) {
220 spin_unlock_irqrestore(gate->lock, flags);
221 return 0;
222 }
223
224 if (gate->reset_idx >= 0) {
225 /* Put IP in reset */
226 regmap_update_bits(gate->map, ASPEED_RESET_CTRL, rst, rst);
227
228 /* Delay 100us */
229 udelay(100);
230 }
231
232 /* Enable clock */
233 enval = (gate->flags & CLK_GATE_SET_TO_DISABLE) ? 0 : clk;
234 regmap_update_bits(gate->map, ASPEED_CLK_STOP_CTRL, clk, enval);
235
236 if (gate->reset_idx >= 0) {
237 /* A delay of 10ms is specified by the ASPEED docs */
238 mdelay(10);
239
240 /* Take IP out of reset */
241 regmap_update_bits(gate->map, ASPEED_RESET_CTRL, rst, 0);
242 }
243
244 spin_unlock_irqrestore(gate->lock, flags);
245
246 return 0;
247 }
248
aspeed_clk_disable(struct clk_hw * hw)249 static void aspeed_clk_disable(struct clk_hw *hw)
250 {
251 struct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw);
252 unsigned long flags;
253 u32 clk = BIT(gate->clock_idx);
254 u32 enval;
255
256 spin_lock_irqsave(gate->lock, flags);
257
258 enval = (gate->flags & CLK_GATE_SET_TO_DISABLE) ? clk : 0;
259 regmap_update_bits(gate->map, ASPEED_CLK_STOP_CTRL, clk, enval);
260
261 spin_unlock_irqrestore(gate->lock, flags);
262 }
263
264 static const struct clk_ops aspeed_clk_gate_ops = {
265 .enable = aspeed_clk_enable,
266 .disable = aspeed_clk_disable,
267 .is_enabled = aspeed_clk_is_enabled,
268 };
269
270 static const u8 aspeed_resets[] = {
271 /* SCU04 resets */
272 [ASPEED_RESET_XDMA] = 25,
273 [ASPEED_RESET_MCTP] = 24,
274 [ASPEED_RESET_ADC] = 23,
275 [ASPEED_RESET_JTAG_MASTER] = 22,
276 [ASPEED_RESET_MIC] = 18,
277 [ASPEED_RESET_PWM] = 9,
278 [ASPEED_RESET_PECI] = 10,
279 [ASPEED_RESET_I2C] = 2,
280 [ASPEED_RESET_AHB] = 1,
281 [ASPEED_RESET_HACE] = 4,
282 [ASPEED_RESET_VIDEO] = 6,
283
284 /*
285 * SCUD4 resets start at an offset to separate them from
286 * the SCU04 resets.
287 */
288 [ASPEED_RESET_CRT1] = ASPEED_RESET2_OFFSET + 5,
289 };
290
aspeed_reset_deassert(struct reset_controller_dev * rcdev,unsigned long id)291 static int aspeed_reset_deassert(struct reset_controller_dev *rcdev,
292 unsigned long id)
293 {
294 struct aspeed_reset *ar = to_aspeed_reset(rcdev);
295 u32 reg = ASPEED_RESET_CTRL;
296 u32 bit = aspeed_resets[id];
297
298 if (bit >= ASPEED_RESET2_OFFSET) {
299 bit -= ASPEED_RESET2_OFFSET;
300 reg = ASPEED_RESET_CTRL2;
301 }
302
303 return regmap_update_bits(ar->map, reg, BIT(bit), 0);
304 }
305
aspeed_reset_assert(struct reset_controller_dev * rcdev,unsigned long id)306 static int aspeed_reset_assert(struct reset_controller_dev *rcdev,
307 unsigned long id)
308 {
309 struct aspeed_reset *ar = to_aspeed_reset(rcdev);
310 u32 reg = ASPEED_RESET_CTRL;
311 u32 bit = aspeed_resets[id];
312
313 if (bit >= ASPEED_RESET2_OFFSET) {
314 bit -= ASPEED_RESET2_OFFSET;
315 reg = ASPEED_RESET_CTRL2;
316 }
317
318 return regmap_update_bits(ar->map, reg, BIT(bit), BIT(bit));
319 }
320
aspeed_reset_status(struct reset_controller_dev * rcdev,unsigned long id)321 static int aspeed_reset_status(struct reset_controller_dev *rcdev,
322 unsigned long id)
323 {
324 struct aspeed_reset *ar = to_aspeed_reset(rcdev);
325 u32 reg = ASPEED_RESET_CTRL;
326 u32 bit = aspeed_resets[id];
327 int ret, val;
328
329 if (bit >= ASPEED_RESET2_OFFSET) {
330 bit -= ASPEED_RESET2_OFFSET;
331 reg = ASPEED_RESET_CTRL2;
332 }
333
334 ret = regmap_read(ar->map, reg, &val);
335 if (ret)
336 return ret;
337
338 return !!(val & BIT(bit));
339 }
340
341 static const struct reset_control_ops aspeed_reset_ops = {
342 .assert = aspeed_reset_assert,
343 .deassert = aspeed_reset_deassert,
344 .status = aspeed_reset_status,
345 };
346
aspeed_clk_hw_register_gate(struct device * dev,const char * name,const char * parent_name,unsigned long flags,struct regmap * map,u8 clock_idx,u8 reset_idx,u8 clk_gate_flags,spinlock_t * lock)347 static struct clk_hw *aspeed_clk_hw_register_gate(struct device *dev,
348 const char *name, const char *parent_name, unsigned long flags,
349 struct regmap *map, u8 clock_idx, u8 reset_idx,
350 u8 clk_gate_flags, spinlock_t *lock)
351 {
352 struct aspeed_clk_gate *gate;
353 struct clk_init_data init;
354 struct clk_hw *hw;
355 int ret;
356
357 gate = kzalloc_obj(*gate);
358 if (!gate)
359 return ERR_PTR(-ENOMEM);
360
361 init.name = name;
362 init.ops = &aspeed_clk_gate_ops;
363 init.flags = flags;
364 init.parent_names = parent_name ? &parent_name : NULL;
365 init.num_parents = parent_name ? 1 : 0;
366
367 gate->map = map;
368 gate->clock_idx = clock_idx;
369 gate->reset_idx = reset_idx;
370 gate->flags = clk_gate_flags;
371 gate->lock = lock;
372 gate->hw.init = &init;
373
374 hw = &gate->hw;
375 ret = clk_hw_register(dev, hw);
376 if (ret) {
377 kfree(gate);
378 hw = ERR_PTR(ret);
379 }
380
381 return hw;
382 }
383
aspeed_clk_probe(struct platform_device * pdev)384 static int aspeed_clk_probe(struct platform_device *pdev)
385 {
386 const struct aspeed_clk_soc_data *soc_data;
387 struct device *dev = &pdev->dev;
388 struct aspeed_reset *ar;
389 struct regmap *map;
390 struct clk_hw *hw;
391 u32 val, rate;
392 int i, ret;
393
394 map = syscon_node_to_regmap(dev->of_node);
395 if (IS_ERR(map)) {
396 dev_err(dev, "no syscon regmap\n");
397 return PTR_ERR(map);
398 }
399
400 ar = devm_kzalloc(dev, sizeof(*ar), GFP_KERNEL);
401 if (!ar)
402 return -ENOMEM;
403
404 ar->map = map;
405 ar->rcdev.owner = THIS_MODULE;
406 ar->rcdev.nr_resets = ARRAY_SIZE(aspeed_resets);
407 ar->rcdev.ops = &aspeed_reset_ops;
408 ar->rcdev.of_node = dev->of_node;
409
410 ret = devm_reset_controller_register(dev, &ar->rcdev);
411 if (ret) {
412 dev_err(dev, "could not register reset controller\n");
413 return ret;
414 }
415
416 /* SoC generations share common layouts but have different divisors */
417 soc_data = of_device_get_match_data(dev);
418 if (!soc_data) {
419 dev_err(dev, "no match data for platform\n");
420 return -EINVAL;
421 }
422
423 /* UART clock div13 setting */
424 regmap_read(map, ASPEED_MISC_CTRL, &val);
425 if (val & UART_DIV13_EN)
426 rate = 24000000 / 13;
427 else
428 rate = 24000000;
429 /* TODO: Find the parent data for the uart clock */
430 hw = clk_hw_register_fixed_rate(dev, "uart", NULL, 0, rate);
431 if (IS_ERR(hw))
432 return PTR_ERR(hw);
433 aspeed_clk_data->hws[ASPEED_CLK_UART] = hw;
434
435 /*
436 * Memory controller (M-PLL) PLL. This clock is configured by the
437 * bootloader, and is exposed to Linux as a read-only clock rate.
438 */
439 regmap_read(map, ASPEED_MPLL_PARAM, &val);
440 hw = soc_data->calc_pll("mpll", val);
441 if (IS_ERR(hw))
442 return PTR_ERR(hw);
443 aspeed_clk_data->hws[ASPEED_CLK_MPLL] = hw;
444
445 /* SD/SDIO clock divider and gate */
446 hw = clk_hw_register_gate(dev, "sd_extclk_gate", "hpll", 0,
447 scu_base + ASPEED_CLK_SELECTION, 15, 0,
448 &aspeed_clk_lock);
449 if (IS_ERR(hw))
450 return PTR_ERR(hw);
451 hw = clk_hw_register_divider_table(dev, "sd_extclk", "sd_extclk_gate",
452 0, scu_base + ASPEED_CLK_SELECTION, 12, 3, 0,
453 soc_data->div_table,
454 &aspeed_clk_lock);
455 if (IS_ERR(hw))
456 return PTR_ERR(hw);
457 aspeed_clk_data->hws[ASPEED_CLK_SDIO] = hw;
458
459 /* MAC AHB bus clock divider */
460 hw = clk_hw_register_divider_table(dev, "mac", "hpll", 0,
461 scu_base + ASPEED_CLK_SELECTION, 16, 3, 0,
462 soc_data->mac_div_table,
463 &aspeed_clk_lock);
464 if (IS_ERR(hw))
465 return PTR_ERR(hw);
466 aspeed_clk_data->hws[ASPEED_CLK_MAC] = hw;
467
468 if (of_device_is_compatible(pdev->dev.of_node, "aspeed,ast2500-scu")) {
469 /* RMII 50MHz RCLK */
470 hw = clk_hw_register_fixed_rate(dev, "mac12rclk", "hpll", 0,
471 50000000);
472 if (IS_ERR(hw))
473 return PTR_ERR(hw);
474
475 /* RMII1 50MHz (RCLK) output enable */
476 hw = clk_hw_register_gate(dev, "mac1rclk", "mac12rclk", 0,
477 scu_base + ASPEED_MAC_CLK_DLY, 29, 0,
478 &aspeed_clk_lock);
479 if (IS_ERR(hw))
480 return PTR_ERR(hw);
481 aspeed_clk_data->hws[ASPEED_CLK_MAC1RCLK] = hw;
482
483 /* RMII2 50MHz (RCLK) output enable */
484 hw = clk_hw_register_gate(dev, "mac2rclk", "mac12rclk", 0,
485 scu_base + ASPEED_MAC_CLK_DLY, 30, 0,
486 &aspeed_clk_lock);
487 if (IS_ERR(hw))
488 return PTR_ERR(hw);
489 aspeed_clk_data->hws[ASPEED_CLK_MAC2RCLK] = hw;
490 }
491
492 /* LPC Host (LHCLK) clock divider */
493 hw = clk_hw_register_divider_table(dev, "lhclk", "hpll", 0,
494 scu_base + ASPEED_CLK_SELECTION, 20, 3, 0,
495 soc_data->div_table,
496 &aspeed_clk_lock);
497 if (IS_ERR(hw))
498 return PTR_ERR(hw);
499 aspeed_clk_data->hws[ASPEED_CLK_LHCLK] = hw;
500
501 /* P-Bus (BCLK) clock divider */
502 hw = clk_hw_register_divider_table(dev, "bclk", "hpll", 0,
503 scu_base + ASPEED_CLK_SELECTION_2, 0, 2, 0,
504 soc_data->div_table,
505 &aspeed_clk_lock);
506 if (IS_ERR(hw))
507 return PTR_ERR(hw);
508 aspeed_clk_data->hws[ASPEED_CLK_BCLK] = hw;
509
510 /* Fixed 24MHz clock */
511 hw = clk_hw_register_fixed_rate(NULL, "fixed-24m", "clkin",
512 0, 24000000);
513 if (IS_ERR(hw))
514 return PTR_ERR(hw);
515 aspeed_clk_data->hws[ASPEED_CLK_24M] = hw;
516
517 hw = clk_hw_register_mux(dev, "eclk-mux", eclk_parent_names,
518 ARRAY_SIZE(eclk_parent_names), 0,
519 scu_base + ASPEED_CLK_SELECTION, 2, 0x3, 0,
520 &aspeed_clk_lock);
521 if (IS_ERR(hw))
522 return PTR_ERR(hw);
523 aspeed_clk_data->hws[ASPEED_CLK_ECLK_MUX] = hw;
524
525 hw = clk_hw_register_divider_table(dev, "eclk", "eclk-mux", 0,
526 scu_base + ASPEED_CLK_SELECTION, 28,
527 3, 0, soc_data->eclk_div_table,
528 &aspeed_clk_lock);
529 if (IS_ERR(hw))
530 return PTR_ERR(hw);
531 aspeed_clk_data->hws[ASPEED_CLK_ECLK] = hw;
532
533 /*
534 * TODO: There are a number of clocks that not included in this driver
535 * as more information is required:
536 * D2-PLL
537 * D-PLL
538 * YCLK
539 * RGMII
540 * RMII
541 * UART[1..5] clock source mux
542 */
543
544 for (i = 0; i < ARRAY_SIZE(aspeed_gates); i++) {
545 const struct aspeed_gate_data *gd = &aspeed_gates[i];
546 u32 gate_flags;
547
548 /* Special case: the USB port 1 clock (bit 14) is always
549 * working the opposite way from the other ones.
550 */
551 gate_flags = (gd->clock_idx == 14) ? 0 : CLK_GATE_SET_TO_DISABLE;
552 hw = aspeed_clk_hw_register_gate(dev,
553 gd->name,
554 gd->parent_name,
555 gd->flags,
556 map,
557 gd->clock_idx,
558 gd->reset_idx,
559 gate_flags,
560 &aspeed_clk_lock);
561 if (IS_ERR(hw))
562 return PTR_ERR(hw);
563 aspeed_clk_data->hws[i] = hw;
564 }
565
566 return 0;
567 };
568
569 static const struct of_device_id aspeed_clk_dt_ids[] = {
570 { .compatible = "aspeed,ast2400-scu", .data = &ast2400_data },
571 { .compatible = "aspeed,ast2500-scu", .data = &ast2500_data },
572 { }
573 };
574
575 static struct platform_driver aspeed_clk_driver = {
576 .probe = aspeed_clk_probe,
577 .driver = {
578 .name = "aspeed-clk",
579 .of_match_table = aspeed_clk_dt_ids,
580 .suppress_bind_attrs = true,
581 },
582 };
583 builtin_platform_driver(aspeed_clk_driver);
584
aspeed_ast2400_cc(struct regmap * map)585 static void __init aspeed_ast2400_cc(struct regmap *map)
586 {
587 struct clk_hw *hw;
588 u32 val, div, clkin, hpll;
589 const u16 hpll_rates[][4] = {
590 {384, 360, 336, 408},
591 {400, 375, 350, 425},
592 };
593 int rate;
594
595 /*
596 * CLKIN is the crystal oscillator, 24, 48 or 25MHz selected by
597 * strapping
598 */
599 regmap_read(map, ASPEED_STRAP, &val);
600 rate = (val >> 8) & 3;
601 if (val & CLKIN_25MHZ_EN) {
602 clkin = 25000000;
603 hpll = hpll_rates[1][rate];
604 } else if (val & AST2400_CLK_SOURCE_SEL) {
605 clkin = 48000000;
606 hpll = hpll_rates[0][rate];
607 } else {
608 clkin = 24000000;
609 hpll = hpll_rates[0][rate];
610 }
611 hw = clk_hw_register_fixed_rate(NULL, "clkin", NULL, 0, clkin);
612 pr_debug("clkin @%u MHz\n", clkin / 1000000);
613
614 /*
615 * High-speed PLL clock derived from the crystal. This the CPU clock,
616 * and we assume that it is enabled. It can be configured through the
617 * HPLL_PARAM register, or set to a specified frequency by strapping.
618 */
619 regmap_read(map, ASPEED_HPLL_PARAM, &val);
620 if (val & AST2400_HPLL_PROGRAMMED)
621 hw = aspeed_ast2400_calc_pll("hpll", val);
622 else
623 hw = clk_hw_register_fixed_rate(NULL, "hpll", "clkin", 0,
624 hpll * 1000000);
625
626 aspeed_clk_data->hws[ASPEED_CLK_HPLL] = hw;
627
628 /*
629 * Strap bits 11:10 define the CPU/AHB clock frequency ratio (aka HCLK)
630 * 00: Select CPU:AHB = 1:1
631 * 01: Select CPU:AHB = 2:1
632 * 10: Select CPU:AHB = 4:1
633 * 11: Select CPU:AHB = 3:1
634 */
635 regmap_read(map, ASPEED_STRAP, &val);
636 val = (val >> 10) & 0x3;
637 div = val + 1;
638 if (div == 3)
639 div = 4;
640 else if (div == 4)
641 div = 3;
642 hw = clk_hw_register_fixed_factor(NULL, "ahb", "hpll", 0, 1, div);
643 aspeed_clk_data->hws[ASPEED_CLK_AHB] = hw;
644
645 /* APB clock clock selection register SCU08 (aka PCLK) */
646 hw = clk_hw_register_divider_table(NULL, "apb", "hpll", 0,
647 scu_base + ASPEED_CLK_SELECTION, 23, 3, 0,
648 ast2400_div_table,
649 &aspeed_clk_lock);
650 aspeed_clk_data->hws[ASPEED_CLK_APB] = hw;
651 }
652
aspeed_ast2500_cc(struct regmap * map)653 static void __init aspeed_ast2500_cc(struct regmap *map)
654 {
655 struct clk_hw *hw;
656 u32 val, freq, div;
657
658 /* CLKIN is the crystal oscillator, 24 or 25MHz selected by strapping */
659 regmap_read(map, ASPEED_STRAP, &val);
660 if (val & CLKIN_25MHZ_EN)
661 freq = 25000000;
662 else
663 freq = 24000000;
664 hw = clk_hw_register_fixed_rate(NULL, "clkin", NULL, 0, freq);
665 pr_debug("clkin @%u MHz\n", freq / 1000000);
666
667 /*
668 * High-speed PLL clock derived from the crystal. This the CPU clock,
669 * and we assume that it is enabled
670 */
671 regmap_read(map, ASPEED_HPLL_PARAM, &val);
672 aspeed_clk_data->hws[ASPEED_CLK_HPLL] = aspeed_ast2500_calc_pll("hpll", val);
673
674 /* Strap bits 11:9 define the AXI/AHB clock frequency ratio (aka HCLK)*/
675 regmap_read(map, ASPEED_STRAP, &val);
676 val = (val >> 9) & 0x7;
677 WARN(val == 0, "strapping is zero: cannot determine ahb clock");
678 div = 2 * (val + 1);
679 hw = clk_hw_register_fixed_factor(NULL, "ahb", "hpll", 0, 1, div);
680 aspeed_clk_data->hws[ASPEED_CLK_AHB] = hw;
681
682 /* APB clock clock selection register SCU08 (aka PCLK) */
683 regmap_read(map, ASPEED_CLK_SELECTION, &val);
684 val = (val >> 23) & 0x7;
685 div = 4 * (val + 1);
686 hw = clk_hw_register_fixed_factor(NULL, "apb", "hpll", 0, 1, div);
687 aspeed_clk_data->hws[ASPEED_CLK_APB] = hw;
688 };
689
aspeed_cc_init(struct device_node * np)690 static void __init aspeed_cc_init(struct device_node *np)
691 {
692 struct regmap *map;
693 u32 val;
694 int ret;
695 int i;
696
697 scu_base = of_iomap(np, 0);
698 if (!scu_base)
699 return;
700
701 aspeed_clk_data = kzalloc_flex(*aspeed_clk_data, hws, ASPEED_NUM_CLKS);
702 if (!aspeed_clk_data)
703 return;
704 aspeed_clk_data->num = ASPEED_NUM_CLKS;
705
706 /*
707 * This way all clocks fetched before the platform device probes,
708 * except those we assign here for early use, will be deferred.
709 */
710 for (i = 0; i < ASPEED_NUM_CLKS; i++)
711 aspeed_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER);
712
713 map = syscon_node_to_regmap(np);
714 if (IS_ERR(map)) {
715 pr_err("no syscon regmap\n");
716 return;
717 }
718 /*
719 * We check that the regmap works on this very first access,
720 * but as this is an MMIO-backed regmap, subsequent regmap
721 * access is not going to fail and we skip error checks from
722 * this point.
723 */
724 ret = regmap_read(map, ASPEED_STRAP, &val);
725 if (ret) {
726 pr_err("failed to read strapping register\n");
727 return;
728 }
729
730 if (of_device_is_compatible(np, "aspeed,ast2400-scu"))
731 aspeed_ast2400_cc(map);
732 else if (of_device_is_compatible(np, "aspeed,ast2500-scu"))
733 aspeed_ast2500_cc(map);
734 else
735 pr_err("unknown platform, failed to add clocks\n");
736 ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, aspeed_clk_data);
737 if (ret)
738 pr_err("failed to add DT provider: %d\n", ret);
739 };
740 CLK_OF_DECLARE_DRIVER(aspeed_cc_g5, "aspeed,ast2500-scu", aspeed_cc_init);
741 CLK_OF_DECLARE_DRIVER(aspeed_cc_g4, "aspeed,ast2400-scu", aspeed_cc_init);
742