1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2026, Advanced Micro Devices, Inc. 4 */ 5 6 #include <drm/amdxdna_accel.h> 7 #include <drm/drm_device.h> 8 9 #include "aie4_pci.h" 10 #include "amdxdna_pci_drv.h" 11 12 #define NPU3_MBOX_BAR 0 13 14 #define NPU3_MBOX_BUFFER_BAR 2 15 #define NPU3_MBOX_INFO_OFF 0x0 16 17 #define NPU3_DOORBELL_BAR 2 18 #define NPU3_DOORBELL_OFF 0x0 19 20 /* PCIe BAR Index for NPU3 */ 21 #define NPU3_REG_BAR_INDEX 0 22 #define NPU3_PSP_BAR_INDEX 4 23 #define NPU3_SMU_BAR_INDEX 5 24 25 #define MMNPU_APERTURE3_BASE 0x3810000 26 #define MMNPU_APERTURE4_BASE 0x3B10000 27 28 #define NPU3_PSP_BAR_BASE MMNPU_APERTURE3_BASE 29 #define NPU3_SMU_BAR_BASE MMNPU_APERTURE4_BASE 30 31 #define MPASP_C2PMSG_123_ALT_1 0x3810AEC 32 #define MPASP_C2PMSG_156_ALT_1 0x3810B70 33 #define MPASP_C2PMSG_157_ALT_1 0x3810B74 34 #define MPASP_C2PMSG_73_ALT_1 0x3810A24 35 36 #define MP1_C2PMSG_59_ALT_1 0x3B109EC 37 #define MP1_C2PMSG_61_ALT_1 0x3B109F4 38 #define MP1_C2PMSG_60_ALT_1 0x3B109F0 39 40 static const struct amdxdna_fw_feature_tbl npu3_fw_feature_table[] = { 41 { .major = 5, .min_minor = 10 }, 42 { 0 } 43 }; 44 45 static const struct amdxdna_dev_priv npu3_dev_priv = { 46 .npufw_path = "npu.dev.sbin", 47 .certfw_path = "cert.dev.sbin", 48 .mbox_bar = NPU3_MBOX_BAR, 49 .mbox_rbuf_bar = NPU3_MBOX_BUFFER_BAR, 50 .mbox_info_off = NPU3_MBOX_INFO_OFF, 51 .doorbell_off = NPU3_DOORBELL_OFF, 52 .psp_regs_off = { 53 DEFINE_BAR_OFFSET(PSP_CMD_REG, NPU3_PSP, MPASP_C2PMSG_123_ALT_1), 54 DEFINE_BAR_OFFSET(PSP_ARG0_REG, NPU3_PSP, MPASP_C2PMSG_156_ALT_1), 55 DEFINE_BAR_OFFSET(PSP_ARG1_REG, NPU3_PSP, MPASP_C2PMSG_157_ALT_1), 56 DEFINE_BAR_OFFSET(PSP_ARG2_REG, NPU3_PSP, MPASP_C2PMSG_123_ALT_1), 57 DEFINE_BAR_OFFSET(PSP_INTR_REG, NPU3_PSP, MPASP_C2PMSG_73_ALT_1), 58 DEFINE_BAR_OFFSET(PSP_STATUS_REG, NPU3_PSP, MPASP_C2PMSG_123_ALT_1), 59 DEFINE_BAR_OFFSET(PSP_RESP_REG, NPU3_PSP, MPASP_C2PMSG_156_ALT_1), 60 /* npu3 doesn't use 8th pwaitmode register */ 61 }, 62 .smu_regs_off = { 63 DEFINE_BAR_OFFSET(SMU_CMD_REG, NPU3_SMU, MP1_C2PMSG_59_ALT_1), 64 DEFINE_BAR_OFFSET(SMU_ARG_REG, NPU3_SMU, MP1_C2PMSG_61_ALT_1), 65 DEFINE_BAR_OFFSET(SMU_INTR_REG, NPU3_SMU, MMNPU_APERTURE4_BASE), 66 DEFINE_BAR_OFFSET(SMU_RESP_REG, NPU3_SMU, MP1_C2PMSG_60_ALT_1), 67 DEFINE_BAR_OFFSET(SMU_OUT_REG, NPU3_SMU, MP1_C2PMSG_61_ALT_1), 68 }, 69 }; 70 71 static const struct amdxdna_dev_priv npu3_dev_vf_priv = { 72 /* vf device does not load firmware */ 73 .mbox_bar = NPU3_MBOX_BAR, 74 .mbox_rbuf_bar = NPU3_MBOX_BUFFER_BAR, 75 .mbox_info_off = NPU3_MBOX_INFO_OFF, 76 /* vf device does not have smu and psp */ 77 }; 78 79 const struct amdxdna_dev_info dev_npu3_pf_info = { 80 .mbox_bar = NPU3_MBOX_BAR, 81 .sram_bar = NPU3_MBOX_BUFFER_BAR, 82 .psp_bar = NPU3_PSP_BAR_INDEX, 83 .smu_bar = NPU3_SMU_BAR_INDEX, 84 .default_vbnv = "RyzenAI-npu3-pf", 85 .device_type = AMDXDNA_DEV_TYPE_PF, 86 .dev_priv = &npu3_dev_priv, 87 .fw_feature_tbl = npu3_fw_feature_table, 88 .ops = &aie4_pf_ops, 89 }; 90 91 const struct amdxdna_dev_info dev_npu3_vf_info = { 92 .mbox_bar = NPU3_MBOX_BAR, 93 .sram_bar = NPU3_MBOX_BUFFER_BAR, 94 .doorbell_bar = NPU3_DOORBELL_BAR, 95 .default_vbnv = "RyzenAI-npu3-vf", 96 .device_type = AMDXDNA_DEV_TYPE_UMQ, 97 .dev_priv = &npu3_dev_vf_priv, 98 .fw_feature_tbl = npu3_fw_feature_table, 99 .ops = &aie4_vf_ops, 100 }; 101